Linux-ARM-Kernel Archive on lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH v19 05/15] clocksource/drivers/arm_arch_timer: rework PPI determination
From: Mark Rutland @ 2017-01-16 17:29 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161221064603.11830-6-fu.wei@linaro.org>

On Wed, Dec 21, 2016 at 02:45:53PM +0800, fu.wei at linaro.org wrote:
[...]

> -	if (is_hyp_mode_available() || !arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) {
> -		bool has_ppi;
> +	if (is_hyp_mode_available() && is_kernel_in_hyp_mode())
> +		return ARCH_TIMER_HYP_PPI;
>  
> -		if (is_kernel_in_hyp_mode()) {
> -			arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI;
> -			has_ppi = !!arch_timer_ppi[ARCH_TIMER_HYP_PPI];
> -		} else {
> -			arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
> -			has_ppi = (!!arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] ||
> -				   !!arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
> -		}
> +	if (arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
> +		return ARCH_TIMER_VIRT_PPI;
>  
> -		if (!has_ppi) {
> -			pr_warn("No interrupt available, giving up\n");
> -			return -EINVAL;
> -		}
> -	}
> +	if (IS_ENABLED(CONFIG_ARM64))
> +		return ARCH_TIMER_PHYS_NONSECURE_PPI;
> +
> +	return ARCH_TIMER_PHYS_SECURE_PPI;

For a 32-bit platform booted at hyp (with a virt PPI available), the new
logic will select ARCH_TIMER_VIRT_PPI. I beleive that will break KVM.

I think the logic should be:

	if (is_kernel_in_hyp_mode())
		return ARCH_TIMER_HYP_PPI;

	if (!is_hyp_mode_available() &&
	    arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
	    	return ARCH_TIMER_VIRT_PPI;
	
	if (IS_ENABLED(CONFIG_ARM64))
		return ARCH_TIMER_PHYS_NONSECURE_PPI;
	
	return ARCH_TIMER_PHYS_SECURE_PPI;

Please use that instead (keeping the comment you retained).

> +static int __init arch_timer_init(void)
> +{
> +	int ret;
>  
>  	ret = arch_timer_register();
>  	if (ret)
> @@ -904,6 +906,13 @@ static int __init arch_timer_of_init(struct device_node *np)
>  	if (IS_ENABLED(CONFIG_ARM) &&
>  	    of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
>  		arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
> +	else
> +		arch_timer_uses_ppi = arch_timer_select_ppi();
> +
> +	if (!arch_timer_ppi[arch_timer_uses_ppi]) {
> +		pr_err("No interrupt available, giving up\n");
> +		return -EINVAL;
> +	}
>  
>  	/* On some systems, the counter stops ticking when in suspend. */
>  	arch_counter_suspend_stop = of_property_read_bool(np,
> @@ -1049,6 +1058,12 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
>  	/* Get the frequency from CNTFRQ */
>  	arch_timer_detect_rate(NULL, NULL);
>  
> +	arch_timer_uses_ppi = arch_timer_select_ppi();
> +	if (!arch_timer_ppi[arch_timer_uses_ppi]) {
> +		pr_err("No interrupt available, giving up\n");
> +		return -EINVAL;
> +	}

I see that we have to duplicate this so we can special-case the
DT-specific behaviour, so that's fine by me.

If you can fix the arch_timer_select_ppi() logic as above, this should
be fine.

Thanks,
Mark.

^ permalink raw reply

* [PATCH 2/2] spi: pca2xx-pci: Allow MSI
From: Jan Kiszka @ 2017-01-16 17:33 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1484558980.2133.134.camel@linux.intel.com>

On 2017-01-16 10:29, Andy Shevchenko wrote:
> On Mon, 2017-01-16 at 10:06 +0100, Jan Kiszka wrote:
>> Now that the core is ready for edge-triggered interrupts, we can
>> safely
>> allow the PCI versions that provide this to enable the feature and,
>> thus, have less shared interrupts.
>>
> 
> My comments below.
> 
>> -	 if (IS_ERR(ssp->clk))
>> +	if (IS_ERR(ssp->clk))
>>  		return PTR_ERR(ssp->clk);
> 
> This doesn't belong to the patch.
>  
>> +	pci_set_master(dev);
>> +
>> +	ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
>> +	if (ret < 0) {
>> +		clk_unregister(ssp->clk);
>> +		return ret;
>> +	}
>> +	ssp->irq = pci_irq_vector(dev, 0);
>> +
> 
> This looks good, though I would put it closer to the initial place of
> ssp->irq assignment, i.e. before clock registering.
> 
>> +		pci_free_irq_vectors(dev);
>> +	pci_free_irq_vectors(dev);
> 
> You know my answer, right? So, please be sure that we are using
> pcim_alloc_irq_vectors().
> 
> Yes, I know there is (was?) no such API, needs to be created. Currently
> this might make a mess on ->remove().
> 

FWIW, I've an updated version of this patch already, addressing the
remarks. Just waiting for a reply on the other patch now.

Jan

-- 
Siemens AG, Corporate Technology, CT RDA ITP SES-DE
Corporate Competence Center Embedded Linux

^ permalink raw reply

* [PATCH v2] IOMMU: SMMUv2: Support for Extended Stream ID (16 bit)
From: Robin Murphy @ 2017-01-16 17:36 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170116141111.29444-1-aleksey.makarov@linaro.org>

On 16/01/17 14:11, Aleksey Makarov wrote:
> Enable the Extended Stream ID feature when available.
> 
> This patch on top of series "KVM PCIe/MSI passthrough on ARM/ARM64
> and IOVA reserved regions" by Eric Auger [1] allows to passthrough
> an external PCIe network card on a ThunderX server successfully.
> 
> Without this patch that card caused a warning like
> 
> 	pci 0006:90:00.0: stream ID 0x9000 out of range for SMMU (0x7fff)
> 
> during boot.
> 
> [1] https://lkml.kernel.org/r/1484127714-3263-1-git-send-email-eric.auger at redhat.com
> 
> Signed-off-by: Aleksey Makarov <aleksey.makarov@linaro.org>
> ---
> v2:
> - remove unnecessary parentheses (Robin Murphy)
> - refactor testing SMR fields to after setting sCR0 as theirs width
>   depends on sCR0_EXIDENABLE (Robin Murphy)
> 
> v1 (rfc):
> https://lkml.kernel.org/r/20170110115755.19102-1-aleksey.makarov at linaro.org
> 
>  drivers/iommu/arm-smmu.c | 67 ++++++++++++++++++++++++++++++++++--------------
>  1 file changed, 48 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index 13d26009b8e0..c33df4083d24 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -24,6 +24,7 @@
>   *	- v7/v8 long-descriptor format
>   *	- Non-secure access to the SMMU
>   *	- Context fault reporting
> + *	- Extended Stream ID (16 bit)
>   */
>  
>  #define pr_fmt(fmt) "arm-smmu: " fmt
> @@ -87,6 +88,7 @@
>  #define sCR0_CLIENTPD			(1 << 0)
>  #define sCR0_GFRE			(1 << 1)
>  #define sCR0_GFIE			(1 << 2)
> +#define sCR0_EXIDENABLE			(1 << 3)
>  #define sCR0_GCFGFRE			(1 << 4)
>  #define sCR0_GCFGFIE			(1 << 5)
>  #define sCR0_USFCFG			(1 << 10)
> @@ -126,6 +128,7 @@
>  #define ID0_NUMIRPT_MASK		0xff
>  #define ID0_NUMSIDB_SHIFT		9
>  #define ID0_NUMSIDB_MASK		0xf
> +#define ID0_EXIDS			(1 << 8)
>  #define ID0_NUMSMRG_SHIFT		0
>  #define ID0_NUMSMRG_MASK		0xff
>  
> @@ -169,6 +172,7 @@
>  #define ARM_SMMU_GR0_S2CR(n)		(0xc00 + ((n) << 2))
>  #define S2CR_CBNDX_SHIFT		0
>  #define S2CR_CBNDX_MASK			0xff
> +#define S2CR_EXIDVALID			(1 << 10)
>  #define S2CR_TYPE_SHIFT			16
>  #define S2CR_TYPE_MASK			0x3
>  enum arm_smmu_s2cr_type {
> @@ -354,6 +358,7 @@ struct arm_smmu_device {
>  #define ARM_SMMU_FEAT_FMT_AARCH64_64K	(1 << 9)
>  #define ARM_SMMU_FEAT_FMT_AARCH32_L	(1 << 10)
>  #define ARM_SMMU_FEAT_FMT_AARCH32_S	(1 << 11)
> +#define ARM_SMMU_FEAT_EXIDS		(1 << 12)
>  	u32				features;
>  
>  #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
> @@ -1051,7 +1056,7 @@ static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx)
>  	struct arm_smmu_smr *smr = smmu->smrs + idx;
>  	u32 reg = smr->id << SMR_ID_SHIFT | smr->mask << SMR_MASK_SHIFT;
>  
> -	if (smr->valid)
> +	if (!(smmu->features & ARM_SMMU_FEAT_EXIDS) && smr->valid)
>  		reg |= SMR_VALID;
>  	writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_SMR(idx));
>  }
> @@ -1063,6 +1068,9 @@ static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx)
>  		  (s2cr->cbndx & S2CR_CBNDX_MASK) << S2CR_CBNDX_SHIFT |
>  		  (s2cr->privcfg & S2CR_PRIVCFG_MASK) << S2CR_PRIVCFG_SHIFT;
>  
> +	if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs &&
> +	    smmu->smrs[idx].valid)
> +		reg |= S2CR_EXIDVALID;
>  	writel_relaxed(reg, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_S2CR(idx));
>  }
>  
> @@ -1073,6 +1081,35 @@ static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx)
>  		arm_smmu_write_smr(smmu, idx);
>  }
>  
> +/*
> + * The width of SMR's mask field depends on sCR0_EXIDENABLE, so this function
> + * should be called after sCR0 is written.
> + */
> +static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu)
> +{
> +	void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
> +	u32 smr;
> +
> +	if (!smmu->smrs)
> +		return;
> +
> +	/*
> +	 * SMR.ID bits may not be preserved if the corresponding
> +	 * MASK bits are set, so check each one separately.
> +	 * We can reject masters later if they try to claim IDs
> +	 * outside these masks.
> +	 */
> +	smr = smmu->streamid_mask << SMR_ID_SHIFT;
> +	writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
> +	smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
> +	smmu->streamid_mask = smr >> SMR_ID_SHIFT;
> +
> +	smr = smmu->streamid_mask << SMR_MASK_SHIFT;
> +	writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
> +	smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
> +	smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT;
> +}
> +
>  static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask)
>  {
>  	struct arm_smmu_smr *smrs = smmu->smrs;
> @@ -1674,6 +1711,9 @@ static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
>  	if (smmu->features & ARM_SMMU_FEAT_VMID16)
>  		reg |= sCR0_VMID16EN;
>  
> +	if (smmu->features & ARM_SMMU_FEAT_EXIDS)
> +		reg |= sCR0_EXIDENABLE;
> +
>  	/* Push the button */
>  	__arm_smmu_tlb_sync(smmu);
>  	writel(reg, ARM_SMMU_GR0_NS(smmu) + ARM_SMMU_GR0_sCR0);
> @@ -1761,11 +1801,14 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
>  			   "\t(IDR0.CTTW overridden by FW configuration)\n");
>  
>  	/* Max. number of entries we have for stream matching/indexing */
> -	size = 1 << ((id >> ID0_NUMSIDB_SHIFT) & ID0_NUMSIDB_MASK);
> +	if (smmu->version == ARM_SMMU_V2 && id & ID0_EXIDS) {
> +		smmu->features |= ARM_SMMU_FEAT_EXIDS;
> +		size = 1 << 16;
> +	} else {
> +		size = 1 << ((id >> ID0_NUMSIDB_SHIFT) & ID0_NUMSIDB_MASK);
> +	}
>  	smmu->streamid_mask = size - 1;
>  	if (id & ID0_SMS) {
> -		u32 smr;
> -
>  		smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
>  		size = (id >> ID0_NUMSMRG_SHIFT) & ID0_NUMSMRG_MASK;
>  		if (size == 0) {
> @@ -1774,21 +1817,6 @@ static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
>  			return -ENODEV;
>  		}
>  
> -		/*
> -		 * SMR.ID bits may not be preserved if the corresponding MASK
> -		 * bits are set, so check each one separately. We can reject
> -		 * masters later if they try to claim IDs outside these masks.
> -		 */
> -		smr = smmu->streamid_mask << SMR_ID_SHIFT;
> -		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
> -		smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
> -		smmu->streamid_mask = smr >> SMR_ID_SHIFT;
> -
> -		smr = smmu->streamid_mask << SMR_MASK_SHIFT;
> -		writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
> -		smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
> -		smmu->smr_mask_mask = smr >> SMR_MASK_SHIFT;
> -
>  		/* Zero-initialised to mark as invalid */
>  		smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs),
>  					  GFP_KERNEL);

The only downside is that the print following this will now always claim
a bogus "... mask 0x0" - I guess we could probably just not print a mask
here, since it's not overly interesting in itself, and add_device will
still show the offending mask in full if it ever actually matters (as in
the commit message).

> @@ -2120,6 +2148,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev)
>  	iommu_register_instance(dev->fwnode, &arm_smmu_ops);
>  	platform_set_drvdata(pdev, smmu);
>  	arm_smmu_device_reset(smmu);
> +	arm_smmu_test_smr_masks(smmu);

Otherwise, this is ceratinly an awful lot neater than what I had in mind
for preserving the existing behaviour :)

Robin.

>  
>  	/* Oh, for a proper bus abstraction */
>  	if (!iommu_present(&platform_bus_type))
> 

^ permalink raw reply

* [PATCH] rtc: sun6i: Switch to the external oscillator
From: Alexandre Belloni @ 2017-01-16 17:40 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170116161349.5btadrfmqbxhrb2c@lukather>

On 16/01/2017 at 17:13:49 +0100, Maxime Ripard wrote :
> On Mon, Jan 16, 2017 at 04:39:59PM +0100, Alexandre Belloni wrote:
> > On 16/01/2017 at 16:21:48 +0100, Maxime Ripard wrote :
> > > The RTC is clocked from either an internal, imprecise, oscillator or an
> > > external one, which is usually much more accurate.
> > > 
> > > The difference perceived between the time elapsed and the time reported by
> > > the RTC is in a 10% scale, which prevents the RTC from being useful at all.
> > > 
> > > Fortunately, the external oscillator is reported to be mandatory in the
> > > Allwinner datasheet, so we can just switch to it.
> > > 
> > 
> > Still, I'm wondering whether the external clock should be taken.
> > 
> > We've had issues with at91 and tegra where this external clock was
> > suddenly able to be stopped, breaking the RTC because the CCF was not
> > aware the RTC was using it.
> 
> That's a very good point...
> 
> > See:
> > http://patchwork.ozlabs.org/patch/502459/
> > http://patchwork.ozlabs.org/patch/714517/
> > 
> > Your reply can be that you don't care now and this has a low probability
> > and you'll handle the case when it happens and that will be fine.
> 
> This is a bit more complicated for us.
> 
> The internal oscillator is running at 667kHz, with a 30% accuracy. The
> external oscillator is supposed to run at 32768Hz, with a maximum
> tolerance of 50ppm.
> 
> The RTC has an internal mux, between the internal and external
> oscillators. If the internal is picked, a (variable) divider of 20 is
> applied by default.
> 
> The output of that mux is also one of the parent of many of our clocks
> in our main clock unit (for example the CPU one), so we need to have
> that parenthood relationship expressed. I guess we could rework the
> driver to first register the clock through the early clock probing
> stuff, and then have the rest of the RTC to probe.
> 
> However, we also need to do so while remaining backward compatible
> from a DT point of view.
> 
> I guess we could:
>   - Add the two oscillators to the DTSI, with their proper accuracy
>   - Put them both as parent clocks of the RTC node
>   - Split the clock part and the RTC part in the driver, and have the
>     clock part, if there is a clocks property in the node (which
>     covers the backward case), register the mux, and pick the clock
>     with the best accuracy. We don't change anything at the RTC level.
>   - Change the parent clock of the CCU for the RTC.
> 
> That would work for you?

That would definitively be better. If the 667kHz oscillator is not an
input to any other IP, you may as well register it directly from the
driver instead of representing it as a node.

-- 
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com

^ permalink raw reply

* [PATCH v2 0/4] Add support for Allwinner V3s SoC
From: Icenowy Zheng @ 2017-01-16 17:43 UTC (permalink / raw)
  To: linux-arm-kernel

Allwinner produced a single-core Cortex-A7 SoC, V3s, with integrated 64MiB DDR2
DRAM, and in LQFP package. With such a package, it has been easier for hackers
to DIY a board (no BGA needed, and no DRAM wiring needed).

Add support for this SoC, as well as one board with it (Lichee Pi Zero).

Pinctrl driver have already been merged when v1. It's now removed in the patchset.

Icenowy Zheng (4):
  arm: sunxi: add support for V3s SoC
  clk: sunxi-ng: add support for V3s CCU
  ARM: dts: sunxi: add dtsi file for V3s SoC
  ARM: dts: sunxi: add support for Lichee Pi Zero board

 Documentation/arm/sunxi/README                |   4 +
 arch/arm/boot/dts/Makefile                    |   3 +-
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts |  73 ++++
 arch/arm/boot/dts/sun8i-v3s.dtsi              | 285 +++++++++++++
 arch/arm/mach-sunxi/sunxi.c                   |   1 +
 drivers/clk/sunxi-ng/Kconfig                  |  11 +
 drivers/clk/sunxi-ng/Makefile                 |   1 +
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c          | 590 ++++++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.h          |  63 +++
 include/dt-bindings/clock/sun8i-v3s-ccu.h     | 107 +++++
 include/dt-bindings/reset/sun8i-v3s-ccu.h     |  78 ++++
 11 files changed, 1215 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
 create mode 100644 arch/arm/boot/dts/sun8i-v3s.dtsi
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
 create mode 100644 include/dt-bindings/clock/sun8i-v3s-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-v3s-ccu.h

-- 
2.11.0

^ permalink raw reply

* [PATCH] coresight: STM: Balance enable/disable
From: Mathieu Poirier @ 2017-01-16 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <c59476a6-f2c8-6b00-ca46-d2d2379d44c9@arm.com>

On 13 January 2017 at 10:11, Suzuki K Poulose <Suzuki.Poulose@arm.com> wrote:
> On 13/01/17 16:48, Mathieu Poirier wrote:
>>
>> On 10 January 2017 at 04:21, Suzuki K Poulose <suzuki.poulose@arm.com>
>> wrote:
>>>
>>> The stm is automatically enabled when an application sets the policy
>>> via ->link() call back by using coresight_enable(), which keeps the
>>> refcount of the current users of the STM. However, the unlink() callback
>>> issues stm_disable() directly, which leaves the STM turned off, without
>>> the coresight layer knowing about it. This prevents any further uses
>>> of the STM hardware as the coresight layer still thinks the STM is
>>> turned on and doesn't issue an stm_enable(). Even manually enabling
>>> the STM via sysfs can't really enable the hw.
>>>
> ...
>>>
>>>
>>> This patch balances the unlink operation by using the
>>> coresight_disable(),
>>> keeping the coresight layer in sync with the hardware state.
>>>
>>> Fixes: commit 237483aa5cf43 ("coresight: stm: adding driver for CoreSight
>>> STM component")
>>> Cc: Pratik Patel <pratikp@codeaurora.org>
>>> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
>>> Cc: Chunyan Zhang <zhang.chunyan@linaro.org>
>>> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>>> Cc: stable at vger.kernel.org # 4.7+
>>> Reported-by: Robert Walker <robert.walker@arm.com>
>>> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
>>> ---
>>>  drivers/hwtracing/coresight/coresight-stm.c | 2 +-
>>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/hwtracing/coresight/coresight-stm.c
>>> b/drivers/hwtracing/coresight/coresight-stm.c
>>> index 3524452..57b7330 100644
>>> --- a/drivers/hwtracing/coresight/coresight-stm.c
>>> +++ b/drivers/hwtracing/coresight/coresight-stm.c
>>> @@ -356,7 +356,7 @@ static void stm_generic_unlink(struct stm_data
>>> *stm_data,
>>>         if (!drvdata || !drvdata->csdev)
>>>                 return;
>>>
>>> -       stm_disable(drvdata->csdev, NULL);
>>> +       coresight_disable(drvdata->csdev);
>>>  }
>>>
>>>  static phys_addr_t
>>
>>
>> Applied - thanks,
>
>
> Mathieu, Greg,
>
> I think this should go into 4.10 (either way, as fix in this cycle or via
> stable after the release). I think
> it would be easier if it goes in as fix during one of these rc cycle.
>
> Please let me know your thoughts.

I'm good with squeezing this patch in the 4.10 cycle.  From here I
suppose the easiest for Greg is for you to send another patch with
Chunyan's Reviewed-by and my ack.

>
> Suzuki
>
>> Mathieu
>>
>>> --
>>> 2.7.4
>>>
>

^ permalink raw reply

* [PATCH v19 06/15] clocksource/drivers/arm_arch_timer: Rework counter frequency detection.
From: Mark Rutland @ 2017-01-16 17:50 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161221064603.11830-7-fu.wei@linaro.org>

On Wed, Dec 21, 2016 at 02:45:54PM +0800, fu.wei at linaro.org wrote:
> From: Fu Wei <fu.wei@linaro.org>
> 
> Currently, the counter frequency detection call(arch_timer_detect_rate)
> combines all the ways to get counter frequency: device-tree property,
> system coprocessor register, MMIO timer. But in the most of use cases,
> we don't need all the ways to try:
> For example, reading device-tree property will be needed only when
> system boot with device-tree, getting frequency from MMIO timer register
> will beneeded only when we init MMIO timer.
> 
> This patch separates paths to determine frequency:
> Separate out device-tree code, keep them in device-tree init function.

Splitting these out makes sense to me.

> Separate out the MMIO frequency and the sysreg frequency detection call,
> and use the appropriate one for the counter.

> Signed-off-by: Fu Wei <fu.wei@linaro.org>
> Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
> ---
>  drivers/clocksource/arm_arch_timer.c | 49 +++++++++++++++++++++++-------------
>  1 file changed, 31 insertions(+), 18 deletions(-)
> 
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index c7b4482..9a1f138 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -488,27 +488,31 @@ static int arch_timer_starting_cpu(unsigned int cpu)
>  	return 0;
>  }
>  
> -static void
> -arch_timer_detect_rate(void __iomem *cntbase, struct device_node *np)
> +static void arch_timer_detect_rate(void)
>  {
> -	/* Who has more than one independent system counter? */
> -	if (arch_timer_rate)
> -		return;
> +	/*
> +	 * Try to get the timer frequency from
> +	 * cntfrq_el0(system coprocessor register).
> +	 */
> +	if (!arch_timer_rate)
> +		arch_timer_rate = arch_timer_get_cntfrq();
> +
> +	/* Check the timer frequency. */
> +	if (!arch_timer_rate)
> +		pr_warn("frequency not available\n");
> +}
>  
> +static void arch_timer_mem_detect_rate(void __iomem *cntbase)
> +{
>  	/*
> -	 * Try to determine the frequency from the device tree or CNTFRQ,
> -	 * if ACPI is enabled, get the frequency from CNTFRQ ONLY.
> +	 * Try to determine the frequency from
> +	 * CNTFRQ in memory-mapped timer.
>  	 */
> -	if (!acpi_disabled ||
> -	    of_property_read_u32(np, "clock-frequency", &arch_timer_rate)) {
> -		if (cntbase)
> -			arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
> -		else
> -			arch_timer_rate = arch_timer_get_cntfrq();
> -	}
> +	if (!arch_timer_rate)
> +		arch_timer_rate = readl_relaxed(cntbase + CNTFRQ);
>  
>  	/* Check the timer frequency. */
> -	if (arch_timer_rate == 0)
> +	if (!arch_timer_rate)
>  		pr_warn("frequency not available\n");
>  }

There's a subtle change in behaviour here. Previously for ACPI we'd only
ever use the sysreg CNTFRQ value for arch_timer_rate, whereas now we
might use the MMIO timer rate. Maybe that's not a big deal, but I will
need to think.

Generally, the logic to determine the rate is fairly gnarly regardless.

It would be nice if we could split the MMIO and sysreg rates entirely,
and kill the implicit relationship between the two, or at least make one
canonical and warn if the two differ.

Thanks,
Mark.

^ permalink raw reply

* [PATCH 1/2] spi: pxa2xx: Prepare for edge-triggered interrupts
From: Andy Shevchenko @ 2017-01-16 17:53 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <7cb06bc7-bcb6-a212-8241-20ad4b2a4a90@siemens.com>

On Mon, Jan 16, 2017 at 1:18 PM, Jan Kiszka <jan.kiszka@siemens.com> wrote:
> On 2017-01-16 10:24, Andy Shevchenko wrote:
>> On Mon, 2017-01-16 at 10:05 +0100, Jan Kiszka wrote:
>>> When using the a device with edge-triggered interrupts, such as MSIs,
>>> the interrupt handler has to ensure that there is a point in time
>>> during
>>> its execution where all interrupts sources are silent so that a new
>>> event can trigger a new interrupt again.
>>>
>>> This is achieved here by looping over SSSR evaluation. We need to take
>>> into account that SSCR1 may be changed by the transfer handler, thus
>>> we
>>> need to redo the mask calculation, at least regarding the volatile
>>> interrupt enable bit (TIE).
>>
>> Could you split this to two patches, one just move the code under
>> question to a helper function (no functional change), the other does
>> what you state in commit message here?
>
> IMHO, factoring out some helper called from the loop in ssp_int won't be
> a natural split due to the large number of local variables being shared
> here. But maybe I'm not seeing the design you have in mind, so please
> propose a useful helper function signature.

At least everything starting from if (!...) {} can be a helper with
only one parameter. Something like:

static int handle_bad_msg(struct driver_data *drv_data)
{
  if (...)
    return 0;

  ...handle it...
  return 1;
}

Let's start from above.

P.S. Btw, you totally missed SPI list/maintainers. And you are using
wrong Jarkko's address.

-- 
With Best Regards,
Andy Shevchenko

^ permalink raw reply

* [PATCH] coresight: STM: Balance enable/disable
From: Suzuki K Poulose @ 2017-01-16 18:00 UTC (permalink / raw)
  To: linux-arm-kernel

The stm is automatically enabled when an application sets the policy
via ->link() call back by using coresight_enable(), which keeps the
refcount of the current users of the STM. However, the unlink() callback
issues stm_disable() directly, which leaves the STM turned off, without
the coresight layer knowing about it. This prevents any further uses
of the STM hardware as the coresight layer still thinks the STM is
turned on and doesn't enable the hardware when required. Even manually
enabling the STM via sysfs can't really enable the hw.

e.g,

 $ echo 1 > $CS_DEVS/$ETR/enable_sink
 $ mkdir -p $CONFIG_FS/stp-policy/$source.0/stm_test/
 $ echo 32768 65535 > $CONFIG_FS/stp-policy/$source.0/stm_test/channels
 $ echo 64 > $CS_DEVS/$source/traceid
 $ ./stm_app
 Sending 64000 byte blocks of pattern 0 at 0us intervals
 Success to map channel(32768~32783) to 0xffffa95fa000
 Sending on channel 32768
 $ dd if=/dev/$ETR of=~/trace.bin.1
 597+1 records in
 597+1 records out
 305920 bytes (306 kB) copied, 0.399952 s, 765 kB/s
 $ ./stm_app
 Sending 64000 byte blocks of pattern 0 at 0us intervals
 Success to map channel(32768~32783) to 0xffff7e9e2000
 Sending on channel 32768
 $ dd if=/dev/$ETR of=~/trace.bin.2
 0+0 records in
 0+0 records out
 0 bytes (0 B) copied, 0.0232083 s, 0.0 kB/s

 Note that we don't get any data from the ETR for the second session.

 Also dmesg shows :

 [   77.520458] coresight-tmc 20800000.etr: TMC-ETR enabled
 [   77.537097] coresight-replicator etr_replicator at 20890000: REPLICATOR enabled
 [   77.558828] coresight-replicator main_replicator at 208a0000: REPLICATOR enabled
 [   77.581068] coresight-funnel 208c0000.main_funnel: FUNNEL inport 0 enabled
 [   77.602217] coresight-tmc 20840000.etf: TMC-ETF enabled
 [   77.618422] coresight-stm 20860000.stm: STM tracing enabled
 [  139.554252] coresight-stm 20860000.stm: STM tracing disabled
  # End of first tracing session
 [  146.351135] coresight-tmc 20800000.etr: TMC read start
 [  146.514486] coresight-tmc 20800000.etr: TMC read end
  # Note that the STM is not turned on via stm_generic_link()->coresight_enable()
  # and hence none of the components are turned on.
 [  152.479080] coresight-tmc 20800000.etr: TMC read start
 [  152.542632] coresight-tmc 20800000.etr: TMC read end

This patch fixes the problem by balancing the unlink operation by using
the coresight_disable(), keeping the coresight layer in sync with the
hardware state and thus allowing normal usage of the STM component.

Fixes: commit 237483aa5cf43 ("coresight: stm: adding driver for CoreSight STM component")
Cc: Pratik Patel <pratikp@codeaurora.org>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: stable at vger.kernel.org # 4.7+
Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reported-by: Robert Walker <robert.walker@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---

Greg,

Without this patch, the coresight STM IP can only be used for one tracing
session per boot, seriously limiting its usability.

---
 drivers/hwtracing/coresight/coresight-stm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/hwtracing/coresight/coresight-stm.c b/drivers/hwtracing/coresight/coresight-stm.c
index e4c55c5..93fc26f 100644
--- a/drivers/hwtracing/coresight/coresight-stm.c
+++ b/drivers/hwtracing/coresight/coresight-stm.c
@@ -356,7 +356,7 @@ static void stm_generic_unlink(struct stm_data *stm_data,
 	if (!drvdata || !drvdata->csdev)
 		return;
 
-	stm_disable(drvdata->csdev, NULL);
+	coresight_disable(drvdata->csdev);
 }
 
 static phys_addr_t
-- 
2.7.4

^ permalink raw reply related

* [PATCH v2 1/4] arm: sunxi: add support for V3s SoC
From: Icenowy Zheng @ 2017-01-16 18:01 UTC (permalink / raw)
  To: linux-arm-kernel

Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB
integrated DRAM, and several peripherals.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v2:
- Used linux-sunxi.org wiki hosted address of V3s datasheet.

Note: the V3s datasheet contains its user manual.

 Documentation/arm/sunxi/README | 4 ++++
 arch/arm/mach-sunxi/sunxi.c    | 1 +
 2 files changed, 5 insertions(+)

diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index cd0243302bc1..a455b305c62c 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -67,6 +67,10 @@ SunXi family
         + Datasheet
           http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
 
+      - Allwinner V3s (sun8i)
+        + Datasheet
+          http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+
     * Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
       - Allwinner A80
         + Datasheet
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 2e2bde271205..f246bfc6cfe4 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -64,6 +64,7 @@ static const char * const sun8i_board_dt_compat[] = {
 	"allwinner,sun8i-a33",
 	"allwinner,sun8i-a83t",
 	"allwinner,sun8i-h3",
+	"allwinner,sun8i-v3s",
 	NULL,
 };
 
-- 
2.11.0

^ permalink raw reply related

* [PATCH v2 2/4] clk: sunxi-ng: add support for V3s CCU
From: Icenowy Zheng @ 2017-01-16 18:01 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170116180116.36729-2-icenowy@aosc.xyz>

V3s has a similar but cut-down CCU to H3.

Add support for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---

I think I should make a comparsion between V3s and H3 CCU here:
(I won't mention the missing/added clocks here, only list conflicting clocks)

- "bus-ehci0" is at different bit (The bit that is "bus-ehci0" on V3s is
  "bus-ehci2" on H3)
- The mux of "ce" is different. (According the view at V3s datasheet by the
  author of sun4i-ss, V3s may have sun4i-ss, not sun8i-ce)
- The mux of "de" is different. (V3s do not have "pll-de", but it can mux "de"
  to "pll-video")
- Clocks about CSI largely differs. (As V3s is designed as a camera SoC, and
  it have an extra "pll-isp")

 drivers/clk/sunxi-ng/Kconfig              |  11 +
 drivers/clk/sunxi-ng/Makefile             |   1 +
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c      | 590 ++++++++++++++++++++++++++++++
 drivers/clk/sunxi-ng/ccu-sun8i-v3s.h      |  63 ++++
 include/dt-bindings/clock/sun8i-v3s-ccu.h | 107 ++++++
 include/dt-bindings/reset/sun8i-v3s-ccu.h |  78 ++++
 6 files changed, 850 insertions(+)
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
 create mode 100644 drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
 create mode 100644 include/dt-bindings/clock/sun8i-v3s-ccu.h
 create mode 100644 include/dt-bindings/reset/sun8i-v3s-ccu.h

diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 8454c6e3dd65..1ca48255802f 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -109,4 +109,15 @@ config SUN8I_H3_CCU
 	select SUNXI_CCU_PHASE
 	default MACH_SUN8I
 
+config SUN8I_V3S_CCU
+	bool "Support for the Allwinner V3s CCU"
+	select SUNXI_CCU_DIV
+	select SUNXI_CCU_NK
+	select SUNXI_CCU_NKM
+	select SUNXI_CCU_NKMP
+	select SUNXI_CCU_NM
+	select SUNXI_CCU_MP
+	select SUNXI_CCU_PHASE
+	default MACH_SUN8I
+
 endif
diff --git a/drivers/clk/sunxi-ng/Makefile b/drivers/clk/sunxi-ng/Makefile
index 24fbc6e5deb8..d1cd81a0f112 100644
--- a/drivers/clk/sunxi-ng/Makefile
+++ b/drivers/clk/sunxi-ng/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_SUN6I_A31_CCU)	+= ccu-sun6i-a31.o
 obj-$(CONFIG_SUN8I_A23_CCU)	+= ccu-sun8i-a23.o
 obj-$(CONFIG_SUN8I_A33_CCU)	+= ccu-sun8i-a33.o
 obj-$(CONFIG_SUN8I_H3_CCU)	+= ccu-sun8i-h3.o
+obj-$(CONFIG_SUN8I_V3S_CCU)	+= ccu-sun8i-v3s.o
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
new file mode 100644
index 000000000000..e569af9338c2
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.c
@@ -0,0 +1,590 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on ccu-sun8i-h3.c, which is:
+ * Copyright (c) 2016 Maxime Ripard. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/of_address.h>
+
+#include "ccu_common.h"
+#include "ccu_reset.h"
+
+#include "ccu_div.h"
+#include "ccu_gate.h"
+#include "ccu_mp.h"
+#include "ccu_mult.h"
+#include "ccu_nk.h"
+#include "ccu_nkm.h"
+#include "ccu_nkmp.h"
+#include "ccu_nm.h"
+#include "ccu_phase.h"
+
+#include "ccu-sun8i-v3s.h"
+
+static SUNXI_CCU_NKMP_WITH_GATE_LOCK(pll_cpu_clk, "pll-cpu",
+				     "osc24M", 0x000,
+				     8, 5,	/* N */
+				     4, 2,	/* K */
+				     0, 2,	/* M */
+				     16, 2,	/* P */
+				     BIT(31),	/* gate */
+				     BIT(28),	/* lock */
+				     0);
+
+/*
+ * The Audio PLL is supposed to have 4 outputs: 3 fixed factors from
+ * the base (2x, 4x and 8x), and one variable divider (the one true
+ * pll audio).
+ *
+ * We don't have any need for the variable divider for now, so we just
+ * hardcode it to match with the clock names
+ */
+#define SUN8I_V3S_PLL_AUDIO_REG	0x008
+
+static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
+				   "osc24M", 0x008,
+				   8, 7,	/* N */
+				   0, 5,	/* M */
+				   BIT(31),	/* gate */
+				   BIT(28),	/* lock */
+				   0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
+					"osc24M", 0x0010,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
+					"osc24M", 0x0018,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NKM_WITH_GATE_LOCK(pll_ddr_clk, "pll-ddr",
+				    "osc24M", 0x020,
+				    8, 5,	/* N */
+				    4, 2,	/* K */
+				    0, 2,	/* M */
+				    BIT(31),	/* gate */
+				    BIT(28),	/* lock */
+				    0);
+
+static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph0_clk, "pll-periph0",
+					   "osc24M", 0x028,
+					   8, 5,	/* N */
+					   4, 2,	/* K */
+					   BIT(31),	/* gate */
+					   BIT(28),	/* lock */
+					   2,		/* post-div */
+					   0);
+
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_isp_clk, "pll-isp",
+					"osc24M", 0x002c,
+					8, 7,		/* N */
+					0, 4,		/* M */
+					BIT(24),	/* frac enable */
+					BIT(25),	/* frac select */
+					270000000,	/* frac rate 0 */
+					297000000,	/* frac rate 1 */
+					BIT(31),	/* gate */
+					BIT(28),	/* lock */
+					0);
+
+static SUNXI_CCU_NK_WITH_GATE_LOCK_POSTDIV(pll_periph1_clk, "pll-periph1",
+					   "osc24M", 0x044,
+					   8, 5,	/* N */
+					   4, 2,	/* K */
+					   BIT(31),	/* gate */
+					   BIT(28),	/* lock */
+					   2,		/* post-div */
+					   0);
+
+static const char * const cpu_parents[] = { "osc32k", "osc24M",
+					     "pll-cpu" , "pll-cpu" };
+static SUNXI_CCU_MUX(cpu_clk, "cpu", cpu_parents,
+		     0x050, 16, 2, CLK_IS_CRITICAL);
+
+static SUNXI_CCU_M(axi_clk, "axi", "cpu", 0x050, 0, 2, 0);
+
+static const char * const ahb1_parents[] = { "osc32k", "osc24M",
+					     "axi" , "pll-periph0" };
+static struct ccu_div ahb1_clk = {
+	.div		= _SUNXI_CCU_DIV_FLAGS(4, 2, CLK_DIVIDER_POWER_OF_TWO),
+
+	.mux		= {
+		.shift	= 12,
+		.width	= 2,
+
+		.variable_prediv	= {
+			.index	= 3,
+			.shift	= 6,
+			.width	= 2,
+		},
+	},
+
+	.common		= {
+		.reg		= 0x054,
+		.features	= CCU_FEATURE_VARIABLE_PREDIV,
+		.hw.init	= CLK_HW_INIT_PARENTS("ahb1",
+						      ahb1_parents,
+						      &ccu_div_ops,
+						      0),
+	},
+};
+
+static struct clk_div_table apb1_div_table[] = {
+	{ .val = 0, .div = 2 },
+	{ .val = 1, .div = 2 },
+	{ .val = 2, .div = 4 },
+	{ .val = 3, .div = 8 },
+	{ /* Sentinel */ },
+};
+static SUNXI_CCU_DIV_TABLE(apb1_clk, "apb1", "ahb1",
+			   0x054, 8, 2, apb1_div_table, 0);
+
+static const char * const apb2_parents[] = { "osc32k", "osc24M",
+					     "pll-periph0" , "pll-periph0" };
+static SUNXI_CCU_MP_WITH_MUX(apb2_clk, "apb2", apb2_parents, 0x058,
+			     0, 5,	/* M */
+			     16, 2,	/* P */
+			     24, 2,	/* mux */
+			     0);
+
+static const char * const ahb2_parents[] = { "ahb1" , "pll-periph0" };
+static const struct ccu_mux_fixed_prediv ahb2_fixed_predivs[] = {
+	{ .index = 1, .div = 2 },
+};
+static struct ccu_mux ahb2_clk = {
+	.mux		= {
+		.shift	= 0,
+		.width	= 1,
+		.fixed_predivs	= ahb2_fixed_predivs,
+		.n_predivs	= ARRAY_SIZE(ahb2_fixed_predivs),
+	},
+
+	.common		= {
+		.reg		= 0x05c,
+		.features	= CCU_FEATURE_FIXED_PREDIV,
+		.hw.init	= CLK_HW_INIT_PARENTS("ahb2",
+						      ahb2_parents,
+						      &ccu_mux_ops,
+						      0),
+	},
+};
+
+static SUNXI_CCU_GATE(bus_ce_clk,	"bus-ce",	"ahb1",
+		      0x060, BIT(5), 0);
+static SUNXI_CCU_GATE(bus_dma_clk,	"bus-dma",	"ahb1",
+		      0x060, BIT(6), 0);
+static SUNXI_CCU_GATE(bus_mmc0_clk,	"bus-mmc0",	"ahb1",
+		      0x060, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_mmc1_clk,	"bus-mmc1",	"ahb1",
+		      0x060, BIT(9), 0);
+static SUNXI_CCU_GATE(bus_mmc2_clk,	"bus-mmc2",	"ahb1",
+		      0x060, BIT(10), 0);
+static SUNXI_CCU_GATE(bus_dram_clk,	"bus-dram",	"ahb1",
+		      0x060, BIT(14), 0);
+static SUNXI_CCU_GATE(bus_emac_clk,	"bus-emac",	"ahb2",
+		      0x060, BIT(17), 0);
+static SUNXI_CCU_GATE(bus_hstimer_clk,	"bus-hstimer",	"ahb1",
+		      0x060, BIT(19), 0);
+static SUNXI_CCU_GATE(bus_spi0_clk,	"bus-spi0",	"ahb1",
+		      0x060, BIT(20), 0);
+static SUNXI_CCU_GATE(bus_otg_clk,	"bus-otg",	"ahb1",
+		      0x060, BIT(24), 0);
+static SUNXI_CCU_GATE(bus_ehci0_clk,	"bus-ehci0",	"ahb1",
+		      0x060, BIT(26), 0);
+static SUNXI_CCU_GATE(bus_ohci0_clk,	"bus-ohci0",	"ahb1",
+		      0x060, BIT(29), 0);
+
+static SUNXI_CCU_GATE(bus_ve_clk,	"bus-ve",	"ahb1",
+		      0x064, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_tcon0_clk,	"bus-tcon0",	"ahb1",
+		      0x064, BIT(4), 0);
+static SUNXI_CCU_GATE(bus_csi_clk,	"bus-csi",	"ahb1",
+		      0x064, BIT(8), 0);
+static SUNXI_CCU_GATE(bus_de_clk,	"bus-de",	"ahb1",
+		      0x064, BIT(12), 0);
+
+static SUNXI_CCU_GATE(bus_codec_clk,	"bus-codec",	"apb1",
+		      0x068, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_pio_clk,	"bus-pio",	"apb1",
+		      0x068, BIT(5), 0);
+
+static SUNXI_CCU_GATE(bus_i2c0_clk,	"bus-i2c0",	"apb2",
+		      0x06c, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_i2c1_clk,	"bus-i2c1",	"apb2",
+		      0x06c, BIT(1), 0);
+static SUNXI_CCU_GATE(bus_uart0_clk,	"bus-uart0",	"apb2",
+		      0x06c, BIT(16), 0);
+static SUNXI_CCU_GATE(bus_uart1_clk,	"bus-uart1",	"apb2",
+		      0x06c, BIT(17), 0);
+static SUNXI_CCU_GATE(bus_uart2_clk,	"bus-uart2",	"apb2",
+		      0x06c, BIT(18), 0);
+
+static SUNXI_CCU_GATE(bus_ephy_clk,	"bus-ephy",	"ahb1",
+		      0x070, BIT(0), 0);
+static SUNXI_CCU_GATE(bus_dbg_clk,	"bus-dbg",	"ahb1",
+		      0x070, BIT(7), 0);
+
+static const char * const mod0_default_parents[] = { "osc24M", "pll-periph0",
+						     "pll-periph1" };
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc0_clk, "mmc0", mod0_default_parents, 0x088,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_PHASE(mmc0_sample_clk, "mmc0_sample", "mmc0",
+		       0x088, 20, 3, 0);
+static SUNXI_CCU_PHASE(mmc0_output_clk, "mmc0_output", "mmc0",
+		       0x088, 8, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc1_clk, "mmc1", mod0_default_parents, 0x08c,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_PHASE(mmc1_sample_clk, "mmc1_sample", "mmc1",
+		       0x08c, 20, 3, 0);
+static SUNXI_CCU_PHASE(mmc1_output_clk, "mmc1_output", "mmc1",
+		       0x08c, 8, 3, 0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(mmc2_clk, "mmc2", mod0_default_parents, 0x090,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_PHASE(mmc2_sample_clk, "mmc2_sample", "mmc2",
+		       0x090, 20, 3, 0);
+static SUNXI_CCU_PHASE(mmc2_output_clk, "mmc2_output", "mmc2",
+		       0x090, 8, 3, 0);
+
+static const char * const ce_parents[] = { "osc24M", "pll-periph0", };
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(ce_clk, "ce", ce_parents, 0x09c,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_MP_WITH_MUX_GATE(spi0_clk, "spi0", mod0_default_parents, 0x0a0,
+				  0, 4,		/* M */
+				  16, 2,	/* P */
+				  24, 2,	/* mux */
+				  BIT(31),	/* gate */
+				  0);
+
+static SUNXI_CCU_GATE(usb_phy0_clk,	"usb-phy0",	"osc24M",
+		      0x0cc, BIT(8), 0);
+static SUNXI_CCU_GATE(usb_ohci0_clk,	"usb-ohci0",	"osc24M",
+		      0x0cc, BIT(16), 0);
+
+static const char * const dram_parents[] = { "pll-ddr", "pll-periph0-2x" };
+static SUNXI_CCU_M_WITH_MUX(dram_clk, "dram", dram_parents,
+			    0x0f4, 0, 4, 20, 2, CLK_IS_CRITICAL);
+
+static SUNXI_CCU_GATE(dram_ve_clk,	"dram-ve",	"dram",
+		      0x100, BIT(0), 0);
+static SUNXI_CCU_GATE(dram_csi_clk,	"dram-csi",	"dram",
+		      0x100, BIT(1), 0);
+static SUNXI_CCU_GATE(dram_ehci_clk,	"dram-ehci",	"dram",
+		      0x100, BIT(17), 0);
+static SUNXI_CCU_GATE(dram_ohci_clk,	"dram-ohci",	"dram",
+		      0x100, BIT(18), 0);
+
+static const char * const de_parents[] = { "pll-video", "pll-periph0" };
+static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
+				 0x104, 0, 4, 24, 2, BIT(31), 0);
+
+static const char * const tcon_parents[] = { "pll-video" };
+static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
+				 0x118, 0, 4, 24, 3, BIT(31), 0);
+
+static SUNXI_CCU_GATE(csi_misc_clk,	"csi-misc",	"osc24M",
+		      0x130, BIT(31), 0);
+
+static const char * const csi_mclk_parents[] = { "osc24M", "pll-video",
+						 "pll-periph0", "pll-periph1" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi0_mclk_clk, "csi0-mclk", csi_mclk_parents,
+				 0x130, 0, 5, 8, 3, BIT(15), 0);
+
+static const char * const csi1_sclk_parents[] = { "pll-video", "pll-isp" };
+static SUNXI_CCU_M_WITH_MUX_GATE(csi1_sclk_clk, "csi-sclk", csi1_sclk_parents,
+				 0x134, 16, 4, 24, 3, BIT(31), 0);
+
+static SUNXI_CCU_M_WITH_MUX_GATE(csi1_mclk_clk, "csi-mclk", csi_mclk_parents,
+				 0x134, 0, 5, 8, 3, BIT(15), 0);
+
+static SUNXI_CCU_M_WITH_GATE(ve_clk, "ve", "pll-ve",
+			     0x13c, 16, 3, BIT(31), 0);
+
+static SUNXI_CCU_GATE(ac_dig_clk,	"ac-dig",	"pll-audio",
+		      0x140, BIT(31), CLK_SET_RATE_PARENT);
+static SUNXI_CCU_GATE(avs_clk,		"avs",		"osc24M",
+		      0x144, BIT(31), 0);
+
+static const char * const mbus_parents[] = { "osc24M", "pll-periph0-2x", "pll-ddr" };
+static SUNXI_CCU_M_WITH_MUX_GATE(mbus_clk, "mbus", mbus_parents,
+				 0x15c, 0, 3, 24, 2, BIT(31), CLK_IS_CRITICAL);
+
+static const char * const mipi_csi_parents[] = { "pll-video", "pll-periph0",
+						 "pll-isp" };
+static SUNXI_CCU_M_WITH_MUX_GATE(mipi_csi_clk, "mipi-csi", mipi_csi_parents,
+			     0x16c, 0, 3, 24, 2, BIT(31), 0);
+
+static struct ccu_common *sun8i_v3s_ccu_clks[] = {
+	&pll_cpu_clk.common,
+	&pll_audio_base_clk.common,
+	&pll_video_clk.common,
+	&pll_ve_clk.common,
+	&pll_ddr_clk.common,
+	&pll_periph0_clk.common,
+	&pll_isp_clk.common,
+	&pll_periph1_clk.common,
+	&cpu_clk.common,
+	&axi_clk.common,
+	&ahb1_clk.common,
+	&apb1_clk.common,
+	&apb2_clk.common,
+	&ahb2_clk.common,
+	&bus_ce_clk.common,
+	&bus_dma_clk.common,
+	&bus_mmc0_clk.common,
+	&bus_mmc1_clk.common,
+	&bus_mmc2_clk.common,
+	&bus_dram_clk.common,
+	&bus_emac_clk.common,
+	&bus_hstimer_clk.common,
+	&bus_spi0_clk.common,
+	&bus_otg_clk.common,
+	&bus_ehci0_clk.common,
+	&bus_ohci0_clk.common,
+	&bus_ve_clk.common,
+	&bus_tcon0_clk.common,
+	&bus_csi_clk.common,
+	&bus_de_clk.common,
+	&bus_codec_clk.common,
+	&bus_pio_clk.common,
+	&bus_i2c0_clk.common,
+	&bus_i2c1_clk.common,
+	&bus_uart0_clk.common,
+	&bus_uart1_clk.common,
+	&bus_uart2_clk.common,
+	&bus_ephy_clk.common,
+	&bus_dbg_clk.common,
+	&mmc0_clk.common,
+	&mmc0_sample_clk.common,
+	&mmc0_output_clk.common,
+	&mmc1_clk.common,
+	&mmc1_sample_clk.common,
+	&mmc1_output_clk.common,
+	&mmc2_clk.common,
+	&mmc2_sample_clk.common,
+	&mmc2_output_clk.common,
+	&ce_clk.common,
+	&spi0_clk.common,
+	&usb_phy0_clk.common,
+	&usb_ohci0_clk.common,
+	&dram_clk.common,
+	&dram_ve_clk.common,
+	&dram_csi_clk.common,
+	&dram_ohci_clk.common,
+	&dram_ehci_clk.common,
+	&de_clk.common,
+	&tcon_clk.common,
+	&csi_misc_clk.common,
+	&csi0_mclk_clk.common,
+	&csi1_sclk_clk.common,
+	&csi1_mclk_clk.common,
+	&ve_clk.common,
+	&ac_dig_clk.common,
+	&avs_clk.common,
+	&mbus_clk.common,
+	&mipi_csi_clk.common,
+};
+
+/* We hardcode the divider to 4 for now */
+static CLK_FIXED_FACTOR(pll_audio_clk, "pll-audio",
+			"pll-audio-base", 4, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_2x_clk, "pll-audio-2x",
+			"pll-audio-base", 2, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_4x_clk, "pll-audio-4x",
+			"pll-audio-base", 1, 1, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_audio_8x_clk, "pll-audio-8x",
+			"pll-audio-base", 1, 2, CLK_SET_RATE_PARENT);
+static CLK_FIXED_FACTOR(pll_periph0_2x_clk, "pll-periph0-2x",
+			"pll-periph0", 1, 2, 0);
+
+static struct clk_hw_onecell_data sun8i_v3s_hw_clks = {
+	.hws	= {
+		[CLK_PLL_CPU]		= &pll_cpu_clk.common.hw,
+		[CLK_PLL_AUDIO_BASE]	= &pll_audio_base_clk.common.hw,
+		[CLK_PLL_AUDIO]		= &pll_audio_clk.hw,
+		[CLK_PLL_AUDIO_2X]	= &pll_audio_2x_clk.hw,
+		[CLK_PLL_AUDIO_4X]	= &pll_audio_4x_clk.hw,
+		[CLK_PLL_AUDIO_8X]	= &pll_audio_8x_clk.hw,
+		[CLK_PLL_VIDEO]		= &pll_video_clk.common.hw,
+		[CLK_PLL_VE]		= &pll_ve_clk.common.hw,
+		[CLK_PLL_DDR]		= &pll_ddr_clk.common.hw,
+		[CLK_PLL_PERIPH0]	= &pll_periph0_clk.common.hw,
+		[CLK_PLL_PERIPH0_2X]	= &pll_periph0_2x_clk.hw,
+		[CLK_PLL_ISP]		= &pll_isp_clk.common.hw,
+		[CLK_PLL_PERIPH1]	= &pll_periph1_clk.common.hw,
+		[CLK_CPU]		= &cpu_clk.common.hw,
+		[CLK_AXI]		= &axi_clk.common.hw,
+		[CLK_AHB1]		= &ahb1_clk.common.hw,
+		[CLK_APB1]		= &apb1_clk.common.hw,
+		[CLK_APB2]		= &apb2_clk.common.hw,
+		[CLK_AHB2]		= &ahb2_clk.common.hw,
+		[CLK_BUS_CE]		= &bus_ce_clk.common.hw,
+		[CLK_BUS_DMA]		= &bus_dma_clk.common.hw,
+		[CLK_BUS_MMC0]		= &bus_mmc0_clk.common.hw,
+		[CLK_BUS_MMC1]		= &bus_mmc1_clk.common.hw,
+		[CLK_BUS_MMC2]		= &bus_mmc2_clk.common.hw,
+		[CLK_BUS_DRAM]		= &bus_dram_clk.common.hw,
+		[CLK_BUS_EMAC]		= &bus_emac_clk.common.hw,
+		[CLK_BUS_HSTIMER]	= &bus_hstimer_clk.common.hw,
+		[CLK_BUS_SPI0]		= &bus_spi0_clk.common.hw,
+		[CLK_BUS_OTG]		= &bus_otg_clk.common.hw,
+		[CLK_BUS_EHCI0]		= &bus_ehci0_clk.common.hw,
+		[CLK_BUS_OHCI0]		= &bus_ohci0_clk.common.hw,
+		[CLK_BUS_VE]		= &bus_ve_clk.common.hw,
+		[CLK_BUS_TCON0]		= &bus_tcon0_clk.common.hw,
+		[CLK_BUS_CSI]		= &bus_csi_clk.common.hw,
+		[CLK_BUS_DE]		= &bus_de_clk.common.hw,
+		[CLK_BUS_CODEC]		= &bus_codec_clk.common.hw,
+		[CLK_BUS_PIO]		= &bus_pio_clk.common.hw,
+		[CLK_BUS_I2C0]		= &bus_i2c0_clk.common.hw,
+		[CLK_BUS_I2C1]		= &bus_i2c1_clk.common.hw,
+		[CLK_BUS_UART0]		= &bus_uart0_clk.common.hw,
+		[CLK_BUS_UART1]		= &bus_uart1_clk.common.hw,
+		[CLK_BUS_UART2]		= &bus_uart2_clk.common.hw,
+		[CLK_BUS_EPHY]		= &bus_ephy_clk.common.hw,
+		[CLK_BUS_DBG]		= &bus_dbg_clk.common.hw,
+		[CLK_MMC0]		= &mmc0_clk.common.hw,
+		[CLK_MMC0_SAMPLE]	= &mmc0_sample_clk.common.hw,
+		[CLK_MMC0_OUTPUT]	= &mmc0_output_clk.common.hw,
+		[CLK_MMC1]		= &mmc1_clk.common.hw,
+		[CLK_MMC1_SAMPLE]	= &mmc1_sample_clk.common.hw,
+		[CLK_MMC1_OUTPUT]	= &mmc1_output_clk.common.hw,
+		[CLK_CE]		= &ce_clk.common.hw,
+		[CLK_SPI0]		= &spi0_clk.common.hw,
+		[CLK_USB_PHY0]		= &usb_phy0_clk.common.hw,
+		[CLK_USB_OHCI0]		= &usb_ohci0_clk.common.hw,
+		[CLK_DRAM]		= &dram_clk.common.hw,
+		[CLK_DRAM_VE]		= &dram_ve_clk.common.hw,
+		[CLK_DRAM_CSI]		= &dram_csi_clk.common.hw,
+		[CLK_DRAM_EHCI]		= &dram_ehci_clk.common.hw,
+		[CLK_DRAM_OHCI]		= &dram_ohci_clk.common.hw,
+		[CLK_DE]		= &de_clk.common.hw,
+		[CLK_TCON0]		= &tcon_clk.common.hw,
+		[CLK_CSI_MISC]		= &csi_misc_clk.common.hw,
+		[CLK_CSI0_MCLK]		= &csi0_mclk_clk.common.hw,
+		[CLK_CSI1_SCLK]		= &csi1_sclk_clk.common.hw,
+		[CLK_CSI1_MCLK]		= &csi1_mclk_clk.common.hw,
+		[CLK_VE]		= &ve_clk.common.hw,
+		[CLK_AC_DIG]		= &ac_dig_clk.common.hw,
+		[CLK_AVS]		= &avs_clk.common.hw,
+		[CLK_MBUS]		= &mbus_clk.common.hw,
+		[CLK_MIPI_CSI]		= &mipi_csi_clk.common.hw,
+	},
+	.num	= CLK_NUMBER,
+};
+
+static struct ccu_reset_map sun8i_v3s_ccu_resets[] = {
+	[RST_USB_PHY0]		=  { 0x0cc, BIT(0) },
+
+	[RST_MBUS]		=  { 0x0fc, BIT(31) },
+
+	[RST_BUS_CE]		=  { 0x2c0, BIT(5) },
+	[RST_BUS_DMA]		=  { 0x2c0, BIT(6) },
+	[RST_BUS_MMC0]		=  { 0x2c0, BIT(8) },
+	[RST_BUS_MMC1]		=  { 0x2c0, BIT(9) },
+	[RST_BUS_MMC2]		=  { 0x2c0, BIT(10) },
+	[RST_BUS_DRAM]		=  { 0x2c0, BIT(14) },
+	[RST_BUS_EMAC]		=  { 0x2c0, BIT(17) },
+	[RST_BUS_HSTIMER]	=  { 0x2c0, BIT(19) },
+	[RST_BUS_SPI0]		=  { 0x2c0, BIT(20) },
+	[RST_BUS_OTG]		=  { 0x2c0, BIT(23) },
+	[RST_BUS_EHCI0]		=  { 0x2c0, BIT(26) },
+	[RST_BUS_OHCI0]		=  { 0x2c0, BIT(29) },
+
+	[RST_BUS_VE]		=  { 0x2c4, BIT(0) },
+	[RST_BUS_TCON0]		=  { 0x2c4, BIT(3) },
+	[RST_BUS_CSI]		=  { 0x2c4, BIT(8) },
+	[RST_BUS_DE]		=  { 0x2c4, BIT(12) },
+	[RST_BUS_DBG]		=  { 0x2c4, BIT(31) },
+
+	[RST_BUS_EPHY]		=  { 0x2c8, BIT(2) },
+
+	[RST_BUS_CODEC]		=  { 0x2d0, BIT(0) },
+
+	[RST_BUS_I2C0]		=  { 0x2d8, BIT(0) },
+	[RST_BUS_I2C1]		=  { 0x2d8, BIT(1) },
+	[RST_BUS_UART0]		=  { 0x2d8, BIT(16) },
+	[RST_BUS_UART1]		=  { 0x2d8, BIT(17) },
+	[RST_BUS_UART2]		=  { 0x2d8, BIT(18) },
+};
+
+static const struct sunxi_ccu_desc sun8i_v3s_ccu_desc = {
+	.ccu_clks	= sun8i_v3s_ccu_clks,
+	.num_ccu_clks	= ARRAY_SIZE(sun8i_v3s_ccu_clks),
+
+	.hw_clks	= &sun8i_v3s_hw_clks,
+
+	.resets		= sun8i_v3s_ccu_resets,
+	.num_resets	= ARRAY_SIZE(sun8i_v3s_ccu_resets),
+};
+
+static void __init sun8i_v3s_ccu_setup(struct device_node *node)
+{
+	void __iomem *reg;
+	u32 val;
+
+	reg = of_io_request_and_map(node, 0, of_node_full_name(node));
+	if (IS_ERR(reg)) {
+		pr_err("%s: Could not map the clock registers\n",
+		       of_node_full_name(node));
+		return;
+	}
+
+	/* Force the PLL-Audio-1x divider to 4 */
+	val = readl(reg + SUN8I_V3S_PLL_AUDIO_REG);
+	val &= ~GENMASK(19, 16);
+	writel(val | (3 << 16), reg + SUN8I_V3S_PLL_AUDIO_REG);
+
+	sunxi_ccu_probe(node, reg, &sun8i_v3s_ccu_desc);
+}
+CLK_OF_DECLARE(sun8i_v3s_ccu, "allwinner,sun8i-v3s-ccu",
+	       sun8i_v3s_ccu_setup);
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
new file mode 100644
index 000000000000..77fee2a4888e
--- /dev/null
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-v3s.h
@@ -0,0 +1,63 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ * 
+ * Based on ccu-sun8i-h3.h, which is:
+ * Copyright (c) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CCU_SUN8I_H3_H_
+#define _CCU_SUN8I_H3_H_
+
+#include <dt-bindings/clock/sun8i-v3s-ccu.h>
+#include <dt-bindings/reset/sun8i-v3s-ccu.h>
+
+#define CLK_PLL_CPU		0
+#define CLK_PLL_AUDIO_BASE	1
+#define CLK_PLL_AUDIO		2
+#define CLK_PLL_AUDIO_2X	3
+#define CLK_PLL_AUDIO_4X	4
+#define CLK_PLL_AUDIO_8X	5
+#define CLK_PLL_VIDEO		6
+#define CLK_PLL_VE		7
+#define CLK_PLL_DDR		8
+#define CLK_PLL_PERIPH0		9
+#define CLK_PLL_PERIPH0_2X	10
+#define CLK_PLL_ISP		11
+#define CLK_PLL_PERIPH1		12
+/* Reserve one number for not implemented and not used PLL_DDR1 */
+
+/* The CPU clock is exported */
+
+#define CLK_AXI			15
+#define CLK_AHB1		16
+#define CLK_APB1		17
+#define CLK_APB2		18
+#define CLK_AHB2		19
+
+/* All the bus gates are exported */
+
+/* The first bunch of module clocks are exported */
+
+#define CLK_DRAM		58
+
+/* All the DRAM gates are exported */
+
+/* Some more module clocks are exported */
+
+#define CLK_MBUS		72
+
+/* And the GPU module clock is exported */
+
+#define CLK_NUMBER		(CLK_MIPI_CSI + 1)
+
+#endif /* _CCU_SUN8I_H3_H_ */
diff --git a/include/dt-bindings/clock/sun8i-v3s-ccu.h b/include/dt-bindings/clock/sun8i-v3s-ccu.h
new file mode 100644
index 000000000000..c0d5d5599c87
--- /dev/null
+++ b/include/dt-bindings/clock/sun8i-v3s-ccu.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-h3-ccu.h, which is:
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SUN8I_V3S_H_
+#define _DT_BINDINGS_CLK_SUN8I_V3S_H_
+
+#define CLK_CPU			14
+
+#define CLK_BUS_CE		20
+#define CLK_BUS_DMA		21
+#define CLK_BUS_MMC0		22
+#define CLK_BUS_MMC1		23
+#define CLK_BUS_MMC2		24
+#define CLK_BUS_DRAM		25
+#define CLK_BUS_EMAC		26
+#define CLK_BUS_HSTIMER		27
+#define CLK_BUS_SPI0		28
+#define CLK_BUS_OTG		29
+#define CLK_BUS_EHCI0		30
+#define CLK_BUS_OHCI0		31
+#define CLK_BUS_VE		32
+#define CLK_BUS_TCON0		33
+#define CLK_BUS_CSI		34
+#define CLK_BUS_DE		35
+#define CLK_BUS_CODEC		36
+#define CLK_BUS_PIO		37
+#define CLK_BUS_I2C0		38
+#define CLK_BUS_I2C1		39
+#define CLK_BUS_UART0		40
+#define CLK_BUS_UART1		41
+#define CLK_BUS_UART2		42
+#define CLK_BUS_EPHY		43
+#define CLK_BUS_DBG		44
+
+#define CLK_MMC0		45
+#define CLK_MMC0_SAMPLE		46
+#define CLK_MMC0_OUTPUT		47
+#define CLK_MMC1		48
+#define CLK_MMC1_SAMPLE		49
+#define CLK_MMC1_OUTPUT		50
+#define CLK_MMC2		51
+#define CLK_MMC2_SAMPLE		52
+#define CLK_MMC2_OUTPUT		53
+#define CLK_CE			54
+#define CLK_SPI0		55
+#define CLK_USB_PHY0		56
+#define CLK_USB_OHCI0		57
+
+#define CLK_DRAM_VE		59
+#define CLK_DRAM_CSI		60
+#define CLK_DRAM_EHCI		61
+#define CLK_DRAM_OHCI		62
+#define CLK_DE			63
+#define CLK_TCON0		64
+#define CLK_CSI_MISC		65
+#define CLK_CSI0_MCLK		66
+#define CLK_CSI1_SCLK		67
+#define CLK_CSI1_MCLK		68
+#define CLK_VE			69
+#define CLK_AC_DIG		70
+#define CLK_AVS			71
+
+#define CLK_MIPI_CSI		73
+
+#endif /* _DT_BINDINGS_CLK_SUN8I_V3S_H_ */
diff --git a/include/dt-bindings/reset/sun8i-v3s-ccu.h b/include/dt-bindings/reset/sun8i-v3s-ccu.h
new file mode 100644
index 000000000000..b58ef21a2e18
--- /dev/null
+++ b/include/dt-bindings/reset/sun8i-v3s-ccu.h
@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * Based on sun8i-v3s-ccu.h, which is
+ * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef _DT_BINDINGS_RST_SUN8I_V3S_H_
+#define _DT_BINDINGS_RST_SUN8I_V3S_H_
+
+#define RST_USB_PHY0		0
+
+#define RST_MBUS		1
+
+#define RST_BUS_CE		5
+#define RST_BUS_DMA		6
+#define RST_BUS_MMC0		7
+#define RST_BUS_MMC1		8
+#define RST_BUS_MMC2		9
+#define RST_BUS_DRAM		11
+#define RST_BUS_EMAC		12
+#define RST_BUS_HSTIMER		14
+#define RST_BUS_SPI0		15
+#define RST_BUS_OTG		17
+#define RST_BUS_EHCI0		18
+#define RST_BUS_OHCI0		22
+#define RST_BUS_VE		26
+#define RST_BUS_TCON0		27
+#define RST_BUS_CSI		30
+#define RST_BUS_DE		34
+#define RST_BUS_DBG		38
+#define RST_BUS_EPHY		39
+#define RST_BUS_CODEC		40
+#define RST_BUS_I2C0		46
+#define RST_BUS_I2C1		47
+#define RST_BUS_UART0		49
+#define RST_BUS_UART1		50
+#define RST_BUS_UART2		51
+
+#endif /* _DT_BINDINGS_RST_SUN8I_H3_H_ */
-- 
2.11.0

^ permalink raw reply related

* [PATCH v2 3/4] ARM: dts: sunxi: add dtsi file for V3s SoC
From: Icenowy Zheng @ 2017-01-16 18:01 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170116180116.36729-2-icenowy@aosc.xyz>

As we have the pinctrl and clock support for the V3s SoC, it's now to
run a mainline Linux on it.

So add a .dtsi file for it.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
Changes in v2:
- Added I2C here.

 arch/arm/boot/dts/sun8i-v3s.dtsi | 285 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 285 insertions(+)
 create mode 100644 arch/arm/boot/dts/sun8i-v3s.dtsi

diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi
new file mode 100644
index 000000000000..a9711fa8a82e
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v3s.dtsi
@@ -0,0 +1,285 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/clock/sun8i-v3s-ccu.h>
+#include <dt-bindings/reset/sun8i-v3s-ccu.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu at 0 {
+			compatible = "arm,cortex-a7";
+			device_type = "cpu";
+			reg = <0>;
+			clocks = <&ccu CLK_CPU>;
+		};
+	};
+
+	timer {
+		compatible = "arm,armv7-timer";
+		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+	};
+
+	clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		osc24M: osc24M_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			clock-output-names = "osc24M";
+		};
+
+		osc32k: osc32k_clk {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <32768>;
+			clock-output-names = "osc32k";
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		mmc0: mmc at 01c0f000 {
+			compatible = "allwinner,sun7i-a20-mmc";
+			reg = <0x01c0f000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC0>,
+				 <&ccu CLK_MMC0>,
+				 <&ccu CLK_MMC0_OUTPUT>,
+				 <&ccu CLK_MMC0_SAMPLE>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ccu RST_BUS_MMC0>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc1: mmc at 01c10000 {
+			compatible = "allwinner,sun7i-a20-mmc";
+			reg = <0x01c10000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC1>,
+				 <&ccu CLK_MMC1>,
+				 <&ccu CLK_MMC1_OUTPUT>,
+				 <&ccu CLK_MMC1_SAMPLE>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ccu RST_BUS_MMC1>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		mmc2: mmc at 01c11000 {
+			compatible = "allwinner,sun7i-a20-mmc";
+			reg = <0x01c11000 0x1000>;
+			clocks = <&ccu CLK_BUS_MMC2>,
+				 <&ccu CLK_MMC2>,
+				 <&ccu CLK_MMC2_OUTPUT>,
+				 <&ccu CLK_MMC2_SAMPLE>;
+			clock-names = "ahb",
+				      "mmc",
+				      "output",
+				      "sample";
+			resets = <&ccu RST_BUS_MMC2>;
+			reset-names = "ahb";
+			interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		ccu: clock at 01c20000 {
+			compatible = "allwinner,sun8i-v3s-ccu";
+			reg = <0x01c20000 0x400>;
+			clocks = <&osc24M>, <&osc32k>;
+			clock-names = "hosc", "losc";
+			#clock-cells = <1>;
+			#reset-cells = <1>;
+		};
+
+		rtc: rtc at 01c20400 {
+			compatible = "allwinner,sun6i-a31-rtc";
+			reg = <0x01c20400 0x54>;
+			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		pio: pinctrl at 01c20800 {
+			compatible = "allwinner,sun8i-v3s-pinctrl";
+			reg = <0x01c20800 0x400>;
+			interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
+			clock-names = "apb", "hosc", "losc";
+			gpio-controller;
+			#gpio-cells = <3>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+
+			i2c0_pins: i2c0 {
+				pins = "PB6", "PB7";
+				function = "i2c0";
+			};
+
+			uart0_pins_a: uart0 at 0 {
+				pins = "PB8", "PB9";
+				function = "uart0";
+			};
+
+			mmc0_pins_a: mmc0 at 0 {
+				pins = "PF0", "PF1", "PF2", "PF3",
+				       "PF4", "PF5";
+				function = "mmc0";
+				drive-strength = <30>;
+				bias-pull-up;
+			};
+		};
+
+		timer at 01c20c00 {
+			compatible = "allwinner,sun4i-a10-timer";
+			reg = <0x01c20c00 0xa0>;
+			interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&osc24M>;
+		};
+
+		wdt0: watchdog at 01c20ca0 {
+			compatible = "allwinner,sun6i-a31-wdt";
+			reg = <0x01c20ca0 0x20>;
+			interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		uart0: serial at 01c28000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28000 0x400>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART0>;
+			resets = <&ccu RST_BUS_UART0>;
+			status = "disabled";
+		};
+
+		uart1: serial at 01c28400 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28400 0x400>;
+			interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART1>;
+			resets = <&ccu RST_BUS_UART1>;
+			status = "disabled";
+		};
+
+		uart2: serial at 01c28800 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x01c28800 0x400>;
+			interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&ccu CLK_BUS_UART2>;
+			resets = <&ccu RST_BUS_UART2>;
+			status = "disabled";
+		};
+
+		i2c0: i2c at 01c2ac00 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2ac00 0x400>;
+			interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C0>;
+			resets = <&ccu RST_BUS_I2C0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&i2c0_pins>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		i2c1: i2c at 01c2b000 {
+			compatible = "allwinner,sun6i-a31-i2c";
+			reg = <0x01c2b000 0x400>;
+			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&ccu CLK_BUS_I2C1>;
+			resets = <&ccu RST_BUS_I2C1>;
+			status = "disabled";
+			#address-cells = <1>;
+			#size-cells = <0>;
+		};
+
+		gic: interrupt-controller at 01c81000 {
+			compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
+			reg = <0x01c81000 0x1000>,
+			      <0x01c82000 0x1000>,
+			      <0x01c84000 0x2000>,
+			      <0x01c86000 0x2000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+		};
+	};
+};
-- 
2.11.0

^ permalink raw reply related

* [PATCH v2 4/4] ARM: dts: sunxi: add support for Lichee Pi Zero board
From: Icenowy Zheng @ 2017-01-16 18:01 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170116180116.36729-2-icenowy@aosc.xyz>

Lichee Pi Zero is a small-sized V3s board, which is
breadboard-compatible, and with a MicroUSB port with both OTG function
and power function.

Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
---
 arch/arm/boot/dts/Makefile                    |  3 +-
 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 73 +++++++++++++++++++++++++++
 2 files changed, 75 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index cccdbcb557b6..3e099e9b1ad7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -853,7 +853,8 @@ dtb-$(CONFIG_MACH_SUN8I) += \
 	sun8i-h3-orangepi-pc-plus.dtb \
 	sun8i-h3-orangepi-plus.dtb \
 	sun8i-h3-orangepi-plus2e.dtb \
-	sun8i-r16-parrot.dtb
+	sun8i-r16-parrot.dtb \
+	sun8i-v3s-licheepi-zero.dtb
 dtb-$(CONFIG_MACH_SUN9I) += \
 	sun9i-a80-optimus.dtb \
 	sun9i-a80-cubieboard4.dtb
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
new file mode 100644
index 000000000000..0099affc6ce3
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-v3s.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+/ {
+	model = "Lichee Pi Zero";
+	compatible = "licheepi,licheepi-zero", "allwinner,sun8i-v3s";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&mmc0 {
+	pinctrl-0 = <&mmc0_pins_a>;
+	pinctrl-names = "default";
+	broken-cd;
+	bus-width = <4>;
+	vmmc-supply = <&reg_vcc3v3>;
+	status = "okay";
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pins_a>;
+	pinctrl-names = "default";
+	status = "okay";
+};
-- 
2.11.0

^ permalink raw reply related

* [BUG] linux-next cannot compile in AES crypto code of ARM
From: Icenowy Zheng @ 2017-01-16 18:16 UTC (permalink / raw)
  To: linux-arm-kernel

I'm trying build linux-next for Allwinner H3 (ARMv7 SoC).

My compiler is GCC 6.2.0.

When building, I got following error:
```
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S: Assembler messages:
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:21: Error: selected processor does not support `tt .req ip' in ARM mode
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movw tt,#:lower16:crypto_ft_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movt tt,#:upper16:crypto_ft_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movwls tt,#:lower16:crypto_fl_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movtls tt,#:upper16:crypto_fl_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movw tt,#:lower16:crypto_it_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movt tt,#:upper16:crypto_it_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movwls tt,#:lower16:crypto_il_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movtls tt,#:upper16:crypto_il_tab'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
/home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
```

^ permalink raw reply

* [PATCH 1/2] spi: pxa2xx: Prepare for edge-triggered interrupts
From: Jan Kiszka @ 2017-01-16 18:19 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <CAHp75VfAiZZaU8VzUjwvaCMnAVapp46KoRz8yD8aG2BanBnRyA@mail.gmail.com>

On 2017-01-16 18:53, Andy Shevchenko wrote:
> On Mon, Jan 16, 2017 at 1:18 PM, Jan Kiszka <jan.kiszka@siemens.com> wrote:
>> On 2017-01-16 10:24, Andy Shevchenko wrote:
>>> On Mon, 2017-01-16 at 10:05 +0100, Jan Kiszka wrote:
>>>> When using the a device with edge-triggered interrupts, such as MSIs,
>>>> the interrupt handler has to ensure that there is a point in time
>>>> during
>>>> its execution where all interrupts sources are silent so that a new
>>>> event can trigger a new interrupt again.
>>>>
>>>> This is achieved here by looping over SSSR evaluation. We need to take
>>>> into account that SSCR1 may be changed by the transfer handler, thus
>>>> we
>>>> need to redo the mask calculation, at least regarding the volatile
>>>> interrupt enable bit (TIE).
>>>
>>> Could you split this to two patches, one just move the code under
>>> question to a helper function (no functional change), the other does
>>> what you state in commit message here?
>>
>> IMHO, factoring out some helper called from the loop in ssp_int won't be
>> a natural split due to the large number of local variables being shared
>> here. But maybe I'm not seeing the design you have in mind, so please
>> propose a useful helper function signature.
> 
> At least everything starting from if (!...) {} can be a helper with
> only one parameter. Something like:
> 
> static int handle_bad_msg(struct driver_data *drv_data)
> {
>   if (...)
>     return 0;
> 
>   ...handle it...
>   return 1;
> }
> 
> Let's start from above.

OK, but I'll factor out only the handling block, ie. after the if.
That's more consistent.

> 
> P.S. Btw, you totally missed SPI list/maintainers. And you are using
> wrong Jarkko's address.

Data-mined this from the list, both typical target group as well as
Jarkko's address that he tends to use. Will adjust.

Jan

-- 
Siemens AG, Corporate Technology, CT RDA ITP SES-DE
Corporate Competence Center Embedded Linux

^ permalink raw reply

* [PATCH v12 6/7] arm64: pmu: Detect and enable multiple PMUs in an ACPI system
From: Lorenzo Pieralisi @ 2017-01-16 18:28 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1484068672-15852-7-git-send-email-jeremy.linton@arm.com>

On Tue, Jan 10, 2017 at 11:17:51AM -0600, Jeremy Linton wrote:

[...]

> +static int __init pmu_acpi_init(void)
> +{
> +	struct pmu_types *pmu, *safe_temp;
> +	bool unused_madt_entries;
> +	LIST_HEAD(pmus);
> +
> +	if (acpi_disabled)
> +		return 0;
> +
> +	unused_madt_entries = arm_pmu_acpi_determine_cpu_types(&pmus);

IIUC (and that's an if) unused_madt_entries is a "buffer" that you add
to all platform devices you manage to create through midr matching to
make sure there are enough resource entries when/if a cpu of the
respective type is onlined.

If that's the case unused_madt_entries can't be a bool.

Second question I have is what happens if cpus that aren't online
have an midr that differs from all the entries parsed at init time
(ie those you created a platform device for), that's certainly
a pesky corner case though.

Thanks,
Lorenzo

> +
> +	list_for_each_entry_safe(pmu, safe_temp, &pmus, list) {
> +		pmu->cpu_count += unused_madt_entries;
> +		pmu_acpi_register(pmu);
> +
> +		list_del(&pmu->list);
> +		kfree(pmu);
> +	}
> +
> +	return 0;
> +}
> +
> +arch_initcall(pmu_acpi_init);
> -- 
> 2.5.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-acpi" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

^ permalink raw reply

* [BUG] linux-next cannot compile in AES crypto code of ARM
From: Robin Murphy @ 2017-01-16 18:29 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <534751484590587@web17h.yandex.ru>

On 16/01/17 18:16, Icenowy Zheng wrote:
> I'm trying build linux-next for Allwinner H3 (ARMv7 SoC).
> 
> My compiler is GCC 6.2.0.

The patch to fix this[1] is already in Linux-next; alternatively you
could also go back to an older binutils (without ARMv8-M support) to
avoid it for the time being.

Robin.

[1]:https://www.mail-archive.com/linux-crypto at vger.kernel.org/msg23076.html

> 
> When building, I got following error:
> ```
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S: Assembler messages:
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:21: Error: selected processor does not support `tt .req ip' in ARM mode
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movw tt,#:lower16:crypto_ft_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movt tt,#:upper16:crypto_ft_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movwls tt,#:lower16:crypto_fl_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `movtls tt,#:upper16:crypto_fl_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:174: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movw tt,#:lower16:crypto_it_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movt tt,#:upper16:crypto_it_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r10,[tt,r10,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r11,[tt,r11,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movwls tt,#:lower16:crypto_il_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `movtls tt,#:upper16:crypto_il_tab'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r4,[tt,r4,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r5,[tt,r5,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r6,[tt,r6,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r7,[tt,r7,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t1,[tt,t1,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t2,[tt,t2,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r9,[tt,r9,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr t0,[tt,t0,lsl#2]'
> /home/icenowy/git-repos/linux/arch/arm/crypto/aes-cipher-core.S:178: Error: ARM register expected -- `ldr r8,[tt,r8,lsl#2]'
> ```
> 
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
> 

^ permalink raw reply

* [PATCH v19 10/15] clocksource/drivers/arm_arch_timer: Refactor the timer init code to prepare for GTDT
From: Mark Rutland @ 2017-01-16 18:30 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20161221064603.11830-11-fu.wei@linaro.org>

On Wed, Dec 21, 2016 at 02:45:58PM +0800, fu.wei at linaro.org wrote:
> From: Fu Wei <fu.wei@linaro.org>
> 
> The patch refactor original memory-mapped timer init code:
>     (1) Refactor "arch_timer_mem_init", make it become a common code for
>         memory-mapped timer init.
>     (2) Add a new function "arch_timer_mem_of_init" for DT init.

As a general note, please write proper commit messages, describing what
the problem is, and why we are making the changes. These bullet points
don't add anything to what can be derived from a glance at the code.

For this patch, you can use:

  clocksource: arm_arch_timer: refactor MMIO timer probing

  Currently the code to probe MMIO architected timers mixes DT parsing
  with actual poking of hardware. This makes the code harder than
  necessary to understand, and makes it difficult to add support for
  probing via ACPI.

  This patch factors all the DT-specific logic out of
  arch_timer_mem_init(), into a new function, arch_timer_mem_of_init().
  The former pokes the hardware and determines the suitablility of
  frames based on a datastructure populated by the latter.

  This cleanly separates the two and will make it possible to add
  probing using the ACPI GTDT in subsequent patches.

[...]

> +	for_each_available_child_of_node(np, frame_node) {
> +		int n;
> +		struct arch_timer_mem_frame *frame = &timer_mem->frame[i];
> +
> +		if (of_property_read_u32(frame_node, "frame-number", &n)) {
> +			pr_err("Missing frame-number\n");
> +			of_node_put(frame_node);
> +			goto out;
> +		}
> +		frame->frame_nr = n;
> +
> +		if (of_address_to_resource(frame_node, 0, &res)) {
> +			of_node_put(frame_node);
> +			goto out;
> +		}
> +		frame->cntbase = res.start;
> +		frame->size = resource_size(&res);
> +
> +		frame->virt_irq = irq_of_parse_and_map(frame_node,
> +						       ARCH_TIMER_VIRT_SPI);
> +		frame->phys_irq = irq_of_parse_and_map(frame_node,
> +						       ARCH_TIMER_PHYS_SPI);
>  
> -	if (!arch_timer_needs_of_probing())
> +		if (++i >= ARCH_TIMER_MEM_MAX_FRAMES)
> +			break;
> +	}

It would be good if we could warn upon seeing more than
ARCH_TIMER_MEM_MAX_FRAMES children, since that's obviously an error.

Thanks,
Mark.

^ permalink raw reply

* [PATCH 1/3] watchdog: imx2: Only i.MX35 and later have a WMCR register
From: Fabio Estevam @ 2017-01-16 18:34 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170109095039.11979-2-u.kleine-koenig@pengutronix.de>

On Mon, Jan 9, 2017 at 7:50 AM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:
> Commit 5fe65ce7ccbb ("watchdog: imx2_wdt: Disable power down counter on
> boot") introduced a write to the WMCR register that doesn't exist on
> i.MX21, i.MX27 and i.MX31 and so makes the SoC hang during probe.
>
> So teach the driver to differentiate between these two types. Note that
> this effectively undoes commit 5fe65ce7ccbb for machines using dt until
> their dtb is updated accordingly. This is critical iff the bootloader
> doesn't disable the power down counter and the #WDOG signal actually
> does something to the machine.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

^ permalink raw reply

* [PATCH 2/3] dts: teach newer i.MX machines to have the i.MX35 type watchdog
From: Fabio Estevam @ 2017-01-16 18:35 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170109095039.11979-3-u.kleine-koenig@pengutronix.de>

On Mon, Jan 9, 2017 at 7:50 AM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:
> Only i.MX35 and newer feature a WMCR register that should be written to. Older
> SoCs hang when this address is written.
>
> Signed-off-by: Uwe Kleine-K?nig <u.kleine-koenig@pengutronix.de>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

Only a minor nit: Subject could: ARM: dts: imx: teach...

^ permalink raw reply

* [PATCH 3/3] watchdog: imx2: add compatibility for new i.MX35 type watchdog
From: Fabio Estevam @ 2017-01-16 18:36 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20170109095039.11979-4-u.kleine-koenig@pengutronix.de>

On Mon, Jan 9, 2017 at 7:50 AM, Uwe Kleine-K?nig
<u.kleine-koenig@pengutronix.de> wrote:
> When the watchdog driver learned about the i.MX35 type watchdog a new
> compatibility string was introduced. Older dtb continue to use the
> old fsl,imx21-wdt string and so stop writing the WMCR register which is
> critical iff the machine powers off when WDOG becomes active and the
> bootloader doesn't stop the power down counter.
>
> It's unknown which boards are affected and I guess most of them are not.

At least imx31 pdk is affected.

> Also note this is only an issue if a new kernel is operated with an old
> dtb as the SoC dtsi files are fixed accordingly.
>
> XXX: the XXX introduced needs to be changed to HEAD~2 when got a stable commit id.

This comment should not be here.


Other than that:

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

^ permalink raw reply

* [PATCH v2 0/3] spi: pca2xx: Prepare for and enable MSI support
From: Jan Kiszka @ 2017-01-16 18:44 UTC (permalink / raw)
  To: linux-arm-kernel

This enhances the pca2xx driver's interrupt handler with support for
edge-triggered interrupts and makes use of that for PCI-hosted variants,
like the Intel Quark SoC.

Changes in v2:
- factored out handle_bad_msg (Andy)
- reordered code in patch 3, avoiding unneeded pci_free_irq_vectors (Andy)

Jan

Jan Kiszka (3):
  spi: pxa2xx: Factor out handle_bad_msg
  spi: pxa2xx: Prepare for edge-triggered interrupts
  spi: pca2xx-pci: Allow MSI

 drivers/spi/spi-pxa2xx-pci.c |  8 ++++++-
 drivers/spi/spi-pxa2xx.c     | 51 +++++++++++++++++++++++++-------------------
 2 files changed, 36 insertions(+), 23 deletions(-)

-- 
2.1.4

^ permalink raw reply

* [PATCH v2 1/3] spi: pxa2xx: Factor out handle_bad_msg
From: Jan Kiszka @ 2017-01-16 18:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1484592296.git.jan.kiszka@siemens.com>

As suggested by Andy Shevchenko: Decouple this corner cause from the
general handling logic in ssp_int.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 drivers/spi/spi-pxa2xx.c | 29 +++++++++++++++--------------
 1 file changed, 15 insertions(+), 14 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index dd7b5b4..0d10090 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -732,6 +732,20 @@ static irqreturn_t interrupt_transfer(struct driver_data *drv_data)
 	return IRQ_HANDLED;
 }
 
+static void handle_bad_msg(struct driver_data *drv_data)
+{
+	pxa2xx_spi_write(drv_data, SSCR0,
+			 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE);
+	pxa2xx_spi_write(drv_data, SSCR1,
+			 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1);
+	if (!pxa25x_ssp_comp(drv_data))
+		pxa2xx_spi_write(drv_data, SSTO, 0);
+	write_SSSR_CS(drv_data, drv_data->clear_sr);
+
+	dev_err(&drv_data->pdev->dev,
+		"bad message state in interrupt handler\n");
+}
+
 static irqreturn_t ssp_int(int irq, void *dev_id)
 {
 	struct driver_data *drv_data = dev_id;
@@ -772,20 +786,7 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
 		return IRQ_NONE;
 
 	if (!drv_data->master->cur_msg) {
-
-		pxa2xx_spi_write(drv_data, SSCR0,
-				 pxa2xx_spi_read(drv_data, SSCR0)
-				 & ~SSCR0_SSE);
-		pxa2xx_spi_write(drv_data, SSCR1,
-				 pxa2xx_spi_read(drv_data, SSCR1)
-				 & ~drv_data->int_cr1);
-		if (!pxa25x_ssp_comp(drv_data))
-			pxa2xx_spi_write(drv_data, SSTO, 0);
-		write_SSSR_CS(drv_data, drv_data->clear_sr);
-
-		dev_err(&drv_data->pdev->dev,
-			"bad message state in interrupt handler\n");
-
+		handle_bad_msg(drv_data);
 		/* Never fail */
 		return IRQ_HANDLED;
 	}
-- 
2.1.4

^ permalink raw reply related

* [PATCH v2 2/3] spi: pxa2xx: Prepare for edge-triggered interrupts
From: Jan Kiszka @ 2017-01-16 18:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1484592296.git.jan.kiszka@siemens.com>

When using the a device with edge-triggered interrupts, such as MSIs,
the interrupt handler has to ensure that there is a point in time during
its execution where all interrupts sources are silent so that a new
event can trigger a new interrupt again.

This is achieved here by looping over SSSR evaluation. We need to take
into account that SSCR1 may be changed by the transfer handler, thus we
need to redo the mask calculation, at least regarding the volatile
interrupt enable bit (TIE).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 drivers/spi/spi-pxa2xx.c | 30 ++++++++++++++++++------------
 1 file changed, 18 insertions(+), 12 deletions(-)

diff --git a/drivers/spi/spi-pxa2xx.c b/drivers/spi/spi-pxa2xx.c
index 0d10090..ac49b80 100644
--- a/drivers/spi/spi-pxa2xx.c
+++ b/drivers/spi/spi-pxa2xx.c
@@ -751,6 +751,7 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
 	struct driver_data *drv_data = dev_id;
 	u32 sccr1_reg;
 	u32 mask = drv_data->mask_sr;
+	irqreturn_t ret = IRQ_NONE;
 	u32 status;
 
 	/*
@@ -774,24 +775,29 @@ static irqreturn_t ssp_int(int irq, void *dev_id)
 
 	sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
 
-	/* Ignore possible writes if we don't need to write */
-	if (!(sccr1_reg & SSCR1_TIE))
-		mask &= ~SSSR_TFS;
-
 	/* Ignore RX timeout interrupt if it is disabled */
 	if (!(sccr1_reg & SSCR1_TINTE))
 		mask &= ~SSSR_TINT;
 
-	if (!(status & mask))
-		return IRQ_NONE;
+	while (1) {
+		/* Ignore possible writes if we don't need to write */
+		if (!(sccr1_reg & SSCR1_TIE))
+			mask &= ~SSSR_TFS;
 
-	if (!drv_data->master->cur_msg) {
-		handle_bad_msg(drv_data);
-		/* Never fail */
-		return IRQ_HANDLED;
-	}
+		if (!(status & mask))
+			return ret;
+
+		if (!drv_data->master->cur_msg) {
+			handle_bad_msg(drv_data);
+			/* Never fail */
+			return IRQ_HANDLED;
+		}
+
+		ret |= drv_data->transfer_handler(drv_data);
 
-	return drv_data->transfer_handler(drv_data);
+		status = pxa2xx_spi_read(drv_data, SSSR);
+		sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1);
+	}
 }
 
 /*
-- 
2.1.4

^ permalink raw reply related

* [PATCH v2 3/3] spi: pca2xx-pci: Allow MSI
From: Jan Kiszka @ 2017-01-16 18:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <cover.1484592296.git.jan.kiszka@siemens.com>

Now that the core is ready for edge-triggered interrupts, we can safely
allow the PCI versions that provide this to enable the feature and,
thus, have less shared interrupts.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
 drivers/spi/spi-pxa2xx-pci.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spi-pxa2xx-pci.c b/drivers/spi/spi-pxa2xx-pci.c
index 58d2d48..58dcadb 100644
--- a/drivers/spi/spi-pxa2xx-pci.c
+++ b/drivers/spi/spi-pxa2xx-pci.c
@@ -203,10 +203,16 @@ static int pxa2xx_spi_pci_probe(struct pci_dev *dev,
 	ssp = &spi_pdata.ssp;
 	ssp->phys_base = pci_resource_start(dev, 0);
 	ssp->mmio_base = pcim_iomap_table(dev)[0];
-	ssp->irq = dev->irq;
 	ssp->port_id = (c->port_id >= 0) ? c->port_id : dev->devfn;
 	ssp->type = c->type;
 
+	pci_set_master(dev);
+
+	ret = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
+	if (ret < 0)
+		return ret;
+	ssp->irq = pci_irq_vector(dev, 0);
+
 	snprintf(buf, sizeof(buf), "pxa2xx-spi.%d", ssp->port_id);
 	ssp->clk = clk_register_fixed_rate(&dev->dev, buf , NULL, 0,
 					   c->max_clk_rate);
-- 
2.1.4

^ permalink raw reply related


This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox