* [PATCH v4] ARM64: dts: meson-gx: Add reserved memory zone and usable memory range
From: Neil Armstrong @ 2017-01-17 8:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMhYfhrd-hy=N-FYDEPmumR0=QNzn5xTLxFuKG7apo5qiw@mail.gmail.com>
On 01/17/2017 07:07 AM, Olof Johansson wrote:
> On Mon, Jan 16, 2017 at 2:39 AM, Neil Armstrong <narmstrong@baylibre.com> wrote:
>> On 01/15/2017 03:43 PM, Andreas F?rber wrote:
>>> Am 13.01.2017 um 21:03 schrieb Kevin Hilman:
>>>> Neil Armstrong <narmstrong@baylibre.com> writes:
>>>>
>>>>> The Amlogic Meson GXBB/GXL/GXM secure monitor uses part of the memory space,
>>>>> this patch adds this reserved zone and redefines the usable memory range.
>>>>>
>>>>> The memory node is also moved from the dtsi files into the proper dts files
>>>>> to handle variants memory sizes.
>>>>>
>>>>> This patch also fixes the memory sizes for the following platforms :
>>>>> - gxl-s905x-p212 : 1GiB instead of 2GiB, a proper 2GiB dts should be pushed
>>>>> - gxm-s912-q201 : 1GiB instead of 2GiB, a proper 2GiB dts should be pushed
>>>>> - gxl-s905d-p231 : 1GiB instead of 2GiB, a proper 2GiB dts should be pushed
>>>>> - gxl-nexbox-a95x : 1GiB instead of 2GiB, a proper 2GiB dts should be pushed
>>>>>
>>>>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>>>>
>>>> Queued for v4.10-rc.
>>>
>>> What is the motivation for this change? I have a local U-Boot patch to
>>> detect the amount of memory available as done downstream, but U-Boot
>>> only updates the reg property that you seem to be abandoning here...
>>>
>>> So for devices that come in multiple RAM configurations - like R-Box Pro
>>> - this would require separate .dts files now! This looks very wrong to
>>> me, especially since I am not aware of other platforms doing the same.
>>> Instead, there's memory reservations for top and bottom done in U-Boot
>>> for reg, plus reserved-memory nodes for anything in the middle.
>>>
>>> Another thing to consider is that uEFI boot (bootefi) handles memory
>>> reservation differently yet again, on the bootloader level. I have had
>>> that working fine on Odroid-C2 and Vega S95.
>>>
>>> So if there's no bug this is fixing (none mentioned in commit message) I
>>> strongly object to this patch.
>>>
>>> Regards,
>>> Andreas
>>>
>>
>> Hi Andreas,
>>
>> Like I replied of my RFT patch :
>> I really disagree about relying on any work or properties added by any bootloader here, Amlogic SoCs has
>> a lot of u-boot versions in the field, and the Odroid-C2 is part of this.
>>
>> Even if Odroid-c2 is in mainline U-Boot or not, the mainline Linux kernel should work using
>> any U-boot version even with the one provided by Amlogic on their openlinux distribution channel.
>>
>> Handling multiple RAM configuration is another story, and the Arm-Soc and DT maintainers should give us
>> their advices.
>
> Is there a way to detect what firmware is running and marking off
> memory from early kernel init instead? That'll take care of the
> concerns about memory size variance as well.
>
>> Actually there is a severe bug fixed here that cause a huge crash if such memory is not reserved while
>> running stock u-boot version on various shipped products and Amlogic's own development boards.
>>
>> The bug is easily triggered by running :
>> # stress --vm 4 --vm-bytes 128M --timeout 10s &
>> [ 46.937975] Bad mode in Error handler detected on CPU1, code 0xbf000000 -- SError
>> ...
>> [ 47.058536] Internal error: Attempting to execute userspace memory: 8600000f [#3] PREEMPT SMP
>> ...
>>
>> Note this is a fix targeted for 4.10 to make the system stable and various users reported some severe
>> crash now the system has more drivers and read-world use-cases are running on Amlogic SoCs.
>>
>> Please feel free to push whatever changes that makes this memory reservation more coherent for 4.11,
>> and respect the behavior of already shipped u-boot version and mainline U-Boot, UEFI, whatever...
>
> Technically we're not in regression territory here, since the platform
> is obviously still in bringup and these aren't bugs that have been
> introduced in this release. So I think we can take a little while to
> sort out if there's a solution that, even if not ideal, at least is on
> the path towards the proper fix and not away from it -- which this
> seems to be.
>
>
> -Olof
>
Hi Olof, Andreas,
As I finally understand, the real issue here is the usage of the "linux,useable-memory" property that
overrides the reg property that is changed by the bootloader to provide the "real" memory size.
As I understand the mainline U-Boot does it right, and it's a good news, and it seems uEFI need to provide
some specialized memory range aswell, but the vendor U-Boot versions only provide the full memory range here.
It seems obvious that whatever range is provided by u-boot, the first 16MiB should be reserved.
The stress-ng package provides this "stress" command and is used to force the kernel to map more memory
zones, but I also got the issue while running a fully fledged Desktop Environment thanks to the
recently merged DRM driver.
You may not be able to trigger the issue since it seems Amlogic reduces this reserved size on GXL/GXM :
https://github.com/khadas/linux/commit/698df2c6cfbb0d1a9359743208e83517b31da6ce
But it should be confirmed.
Kevin asked me initially to handle this "start of ddr" reserved zone via a reserved-memory entry, but
at that time it seemed a better idea to use "linux,useable-memory", but I recon it may be an error.
I will push a v5 with a supplementary reserved-memory entry and will postpone the boards memory size
fixup for a future DTS cleanup.
Andreas, is this ok for you ?
This issue exists since forever on mainline linux, and even 4.9 has it.
Olof, How could a similar fix go in 4.9 stable ?
Thanks,
Neil
^ permalink raw reply
* [PATCH v1] ARM: dts: imx: add fsl, imx35-wdt compatible to all relevant watchdog nodes
From: Uwe Kleine-König @ 2017-01-17 8:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117012336.6891-1-vz@mleia.com>
On Tue, Jan 17, 2017 at 03:23:36AM +0200, Vladimir Zapolskiy wrote:
> Watchdog device controller found on all modern SoCs from i.MX series
> and firstly introduced in i.MX35 is not one in one compatible with the
> watchdog controllers on i.MX21, i.MX27 and i.MX31, the latter
> controlles don't have WICR (and pretimeout notification support) and
> WMCR registers. To get benefit from the more advanced watchdog device
> and to avoid operations over non-existing registers on legacy SoCs add
> fsl,imx35-wdt compatible to descriptions of all i.MX35 compatible
> watchdog controllers.
>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> RFC change is found at https://patchwork.kernel.org/patch/9350007
>
> Changes from RFC to v1:
> * added the same change to devicetree bindings documentation, thanks
> to Baruch Siach for review,
> * replaced a new shared compatible derived from i.MX25 with an earlier
> from i.MX35 SoC one, thanks to Uwe Kleine-K?nig for review.
>
> Compatible "fsl,imx21-wdt" is preserved as a generic one, because
> interface to a watchdog controller on i.MX35 is a superset of the
> interface to a i.MX21 watchdog controller.
One could argue here, but apart from the discussion if this is correct
or not, choosing this way has the upside that teaching the driver after
this change about the i.MX35 type doesn't make the machines based on the
newer type suffer from a breakage for one commit.
> Documentation/devicetree/bindings/watchdog/fsl-imx-wdt.txt | 2 +-
When I created my patch set for this breakage I wondered if the
documentation should point out which are the unique types.
> arch/arm/boot/dts/imx25.dtsi | 3 ++-
> arch/arm/boot/dts/imx50.dtsi | 3 ++-
> arch/arm/boot/dts/imx51.dtsi | 6 ++++--
> arch/arm/boot/dts/imx53.dtsi | 6 ++++--
> arch/arm/boot/dts/imx6qdl.dtsi | 6 ++++--
> arch/arm/boot/dts/imx6sl.dtsi | 6 ++++--
> arch/arm/boot/dts/imx6sx.dtsi | 9 ++++++---
> arch/arm/boot/dts/imx6ul.dtsi | 6 ++++--
> arch/arm/boot/dts/imx7s.dtsi | 12 ++++++++----
> arch/arm/boot/dts/ls1021a.dtsi | 2 +-
> arch/arm/boot/dts/vfxxx.dtsi | 3 ++-
The imx21 type is also used in
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
What about these?
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* drm: rockchip: CONFIG_DRM_FBDEV_EMULATION will crash the HDMI down sometimes
From: Mark yao @ 2017-01-17 8:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <edb88801-6ea1-3909-2e4e-ba78df6d3c7c@rock-chips.com>
static void vop_plane_atomic_update(struct drm_plane *plane,
struct drm_plane_state *old_state)
{
if (WARN_ON(!vop->is_enabled))
return;
The issues seems vop is not enable. but commit planes is using
DRM_PLANE_COMMIT_ACTIVE_ONLY...
Hi Randy
Can you add some print for this bug:
1, I think vop_crtc_enable function should be call before
vop_plane_atomic_update, you can add some print to verified it.
2, also add a trace on vop_crtc_disable.
3, print the status of crtc->state->active and
plane_crtc_active(plane->state) when bug happen.
Thanks.
On 2017?01?17? 15:58, Randy Li wrote:
> Hello:
> I want to enable the video output at RK3288 Firefly board, but I
> found if I enable CONFIG_DRM_FBDEV_EMULATION, the HDMI would crash
> down sometimes but sometimes it works. After disable that opinion, I
> never meet a problem. I have not verified it with eDP as I meet a big
> problem in there.
>
> [ OK ] Stopped LSB: Load kernel modules needed to enable cpufreq
> scaling.
> [ 33.282843] [drm:drm_atomic_helper_commit_cleanup_done
> [drm_kms_helper]] *ERROR* [CRTC:27:crtc-0] flip_done timed out
> [ 33.361489] ------------[ cut here ]------------
> [ 33.366251] WARNING: CPU: 2 PID: 476 at
> /home/ayaka/workspace/rk3288/kernel/linux-kernel/drivers/gpu/drm/rockchip/rockchip_drm$
> vop.c:730 vop_plane_atomic_update+0x1218/0x177c [rockchipdrm]
> [ 33.383071] Modules linked in: rockchip_vop_reg rockchipdrm
> dw_hdmi_rockchip dw_hdmi drm_kms_helper cfbfillrect mali_kbase sys$
> opyarea gpio_ir_recv cfbimgblt sysfillrect rc_core dwc2 sysimgblt
> fb_sys_fops panel_simple cfbcopyarea rk_crypto drm nvmem_rockch$
> p_efuse udc_core des_generic phy_rockchip_usb pwm_rockchip pwm_bl
> backlight fb
> [ 33.412751] CPU: 2 PID: 476 Comm: X Tainted: G W
> 4.10.0-rc3-next-20170111+ #148
> [ 33.421182] Hardware name: Rockchip (Device Tree)
> [ 33.425905] [<c0112b98>] (unwind_backtrace) from [<c010dab8>]
> (show_stack+0x20/0x24)
> [ 33.433652] [<c010dab8>] (show_stack) from [<c044973c>]
> (dump_stack+0x8c/0xa0)
> [ 33.440881] [<c044973c>] (dump_stack) from [<c0125f88>]
> (__warn+0xf8/0x110)
> [ 33.447839] [<c0125f88>] (__warn) from [<c01260b8>]
> (warn_slowpath_null+0x30/0x38)
> [ 33.455431] [<c01260b8>] (warn_slowpath_null) from [<bf5cb4dc>]
> (vop_plane_atomic_update+0x1218/0x177c [rockchipdrm])
> [ 33.466126] [<bf5cb4dc>] (vop_plane_atomic_update [rockchipdrm])
> from [<bf4d8590>] (drm_atomic_helper_commit_planes+0xd4/0x2b8
> [drm_kms_helper])
> [ 33.479160] [<bf4d8590>] (drm_atomic_helper_commit_planes
> [drm_kms_helper]) from [<bf5c6a88>] (rockchip_atomic_commit_tail+0x4$
> /0x68 [rockchipdrm])
> [ 33.492451] [<bf5c6a88>] (rockchip_atomic_commit_tail
> [rockchipdrm]) from [<bf4dc714>] (commit_tail+0x50/0xb8 [drm_kms_helper]$
> [ 33.504061] [<bf4dc714>] (commit_tail [drm_kms_helper]) from
> [<bf4dc870>] (drm_atomic_helper_commit+0xd4/0x13c [drm_kms_helper$
> )
> [ 33.515850] [<bf4dc870>] (drm_atomic_helper_commit
> [drm_kms_helper]) from [<bf09318c>] (drm_atomic_commit+0x5c/0x68 [drm])
> [ 33.527126] [<bf09318c>] (drm_atomic_commit [drm]) from
> [<bf4e00f8>] (restore_fbdev_mode+0x160/0x300 [drm_kms_helper])
> [ 33.537952] [<bf4e00f8>] (restore_fbdev_mode [drm_kms_helper]) from
> [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked+0x$
> 0/0x84 [drm_kms_helper])
> [ 33.551590] [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked
> [drm_kms_helper]) from [<bf5c6218>] (rockchip_drm_lastclos$
> +0x1c/0x20 [rockchipdrm])
> [ 33.565404] [<bf5c6218>] (rockchip_drm_lastclose [rockchipdrm])
> from [<bf07d20c>] (drm_lastclose+0x48/0xd8 [drm])
> [ 33.575977] [<bf07d20c>] (drm_lastclose [drm]) from [<bf07d560>]
> (drm_release+0x2c4/0x36c [drm])
> [ 33.584927] [<bf07d560>] (drm_release [drm]) from [<c02d7b34>]
> (__fput+0x9c/0x1e8)
> [ 33.592501] [<c02d7b34>] (__fput) from [<c02d7cf0>]
> (____fput+0x18/0x1c)
> [ 33.599206] [<c02d7cf0>] (____fput) from [<c0146ed4>]
> (task_work_run+0xcc/0xf0)
> [ 33.606519] [<c0146ed4>] (task_work_run) from [<c010d1b0>]
> (do_work_pending+0xd0/0xd4)
> [ 33.614439] [<c010d1b0>] (do_work_pending) from [<c0108e28>]
> (slow_work_pending+0xc/0x20)
> [ 33.622674] ---[ end trace 95ed2c3f167607d2 ]---
> [ 33.627327] ------------[ cut here ]------------
> [ 33.632013] WARNING: CPU: 2 PID: 476 at
> /home/ayaka/workspace/rk3288/kernel/linux-kernel/drivers/gpu/drm/rockchip/rockchip_drm_
> vop.c:1017 vop_crtc_atomic_flush+0x27c/0x2b8 [rockchipdrm]
> [ 33.648542] Modules linked in: rockchip_vop_reg rockchipdrm
> dw_hdmi_rockchip dw_hdmi drm_kms_helper cfbfillrect mali_kbase sysc
> opyarea gpio_ir_recv cfbimgblt sysfillrect rc_core dwc2 sysimgblt
> fb_sys_fops panel_simple cfbcopyarea rk_crypto drm nvmem_rockchi
> p_efuse udc_core des_generic phy_rockchip_usb pwm_rockchip pwm_bl
> backlight fb
> [ 33.678191] CPU: 2 PID: 476 Comm: X Tainted: G W
> 4.10.0-rc3-next-20170111+ #148
> [ 33.686621] Hardware name: Rockchip (Device Tree)
> [ 33.691339] [<c0112b98>] (unwind_backtrace) from [<c010dab8>]
> (show_stack+0x20/0x24)
> [ 33.699084] [<c010dab8>] (show_stack) from [<c044973c>]
> (dump_stack+0x8c/0xa0)
> [ 33.706309] [<c044973c>] (dump_stack) from [<c0125f88>]
> (__warn+0xf8/0x110)
> [ 33.713275] [<c0125f88>] (__warn) from [<c01260b8>]
> (warn_slowpath_null+0x30/0x38)
> [ 33.720864] [<c01260b8>] (warn_slowpath_null) from [<bf5c83e0>]
> (vop_crtc_atomic_flush+0x27c/0x2b8 [rockchipdrm])
> [ 33.731208] [<bf5c83e0>] (vop_crtc_atomic_flush [rockchipdrm]) from
> [<bf4d868c>] (drm_atomic_helper_commit_planes+0x1d0/0x2b8 [
> drm_kms_helper])
> [ 33.744159] [<bf4d868c>] (drm_atomic_helper_commit_planes
> [drm_kms_helper]) from [<bf5c6a88>] (rockchip_atomic_commit_tail+0x44
> /0x68 [rockchipdrm])
> [ 33.757451] [<bf5c6a88>] (rockchip_atomic_commit_tail
> [rockchipdrm]) from [<bf4dc714>] (commit_tail+0x50/0xb8 [drm_kms_helper])
> [ 33.769064] [<bf4dc714>] (commit_tail [drm_kms_helper]) from
> [<bf4dc870>] (drm_atomic_helper_commit+0xd4/0x13c [drm_kms_helper]
> )
> [ 33.780861] [<bf4dc870>] (drm_atomic_helper_commit
> [drm_kms_helper]) from [<bf09318c>] (drm_atomic_commit+0x5c/0x68 [drm])
> [ 33.792131] [<bf09318c>] (drm_atomic_commit [drm]) from
> [<bf4e00f8>] (restore_fbdev_mode+0x160/0x300 [drm_kms_helper])
> [ 33.802956] [<bf4e00f8>] (restore_fbdev_mode [drm_kms_helper]) from
> [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked+0x4
> 0/0x84 [drm_kms_helper])
> [ 33.816590] [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked
> [drm_kms_helper]) from [<bf5c6218>] (rockchip_drm_lastclose
> +0x1c/0x20 [rockchipdrm])
> [ 33.830406] [<bf5c6218>] (rockchip_drm_lastclose [rockchipdrm])
> from [<bf07d20c>] (drm_lastclose+0x48/0xd8 [drm])
> [ 33.840975] [<bf07d20c>] (drm_lastclose [drm]) from [<bf07d560>]
> (drm_release+0x2c4/0x36c [drm])
> [ 33.849923] [<bf07d560>] (drm_release [drm]) from [<c02d7b34>]
> (__fput+0x9c/0x1e8)
> [ 33.857497] [<c02d7b34>] (__fput) from [<c02d7cf0>]
> (____fput+0x18/0x1c)
> [ 33.864201] [<c02d7cf0>] (____fput) from [<c0146ed4>]
> (task_work_run+0xcc/0xf0)
> [ 33.871514] [<c0146ed4>] (task_work_run) from [<c010d1b0>]
> (do_work_pending+0xd0/0xd4)
> [ 33.879434] [<c010d1b0>] (do_work_pending) from [<c0108e28>]
> (slow_work_pending+0xc/0x20)
> [ 33.887671] ---[ end trace 95ed2c3f167607d3 ]---
> [ 33.892322] ------------[ cut here ]------------
> [ 33.897058] WARNING: CPU: 2 PID: 476 at
> /home/ayaka/workspace/rk3288/kernel/linux-kernel/drivers/gpu/drm/drm_atomic_helper.c:15
> 63 drm_atomic_helper_commit_hw_done+0xc0/0xc8 [drm_kms_helper]
> [ 33.913937] Modules linked in: rockchip_vop_reg rockchipdrm
> dw_hdmi_rockchip dw_hdmi drm_kms_helper cfbfillrect mali_kbase sysc
> opyarea gpio_ir_recv cfbimgblt sysfillrect rc_core dwc2 sysimgblt
> fb_sys_fops panel_simple cfbcopyarea rk_crypto drm nvmem_rockchi
> p_efuse udc_core des_generic phy_rockchip_usb pwm_rockchip pwm_bl
> backlight fb
> [ 33.943581] CPU: 2 PID: 476 Comm: X Tainted: G W
> 4.10.0-rc3-next-20170111+ #148
> [ 33.952010] Hardware name: Rockchip (Device Tree)
> [ 33.956726] [<c0112b98>] (unwind_backtrace) from [<c010dab8>]
> (show_stack+0x20/0x24)
> [ 33.964470] [<c010dab8>] (show_stack) from [<c044973c>]
> (dump_stack+0x8c/0xa0)
> [ 33.971695] [<c044973c>] (dump_stack) from [<c0125f88>]
> (__warn+0xf8/0x110)
> [ 33.978661] [<c0125f88>] (__warn) from [<c01260b8>]
> (warn_slowpath_null+0x30/0x38)
> [ 33.986301] [<c01260b8>] (warn_slowpath_null) from [<bf4d9410>]
> (drm_atomic_helper_commit_hw_done+0xc0/0xc8 [drm_kms_helper])
> [ 33.997686] [<bf4d9410>] (drm_atomic_helper_commit_hw_done
> [drm_kms_helper]) from [<bf5c6a90>] (rockchip_atomic_commit_tail+0x4
> c/0x68 [rockchipdrm])
> [ 34.011062] [<bf5c6a90>] (rockchip_atomic_commit_tail
> [rockchipdrm]) from [<bf4dc714>] (commit_tail+0x50/0xb8 [drm_kms_helper])
> [ 34.022670] [<bf4dc714>] (commit_tail [drm_kms_helper]) from
> [<bf4dc870>] (drm_atomic_helper_commit+0xd4/0x13c [drm_kms_helper]
> )
> [ 34.034458] [<bf4dc870>] (drm_atomic_helper_commit
> [drm_kms_helper]) from [<bf09318c>] (drm_atomic_commit+0x5c/0x68 [drm])
> [ 34.045728] [<bf09318c>] (drm_atomic_commit [drm]) from
> [<bf4e00f8>] (restore_fbdev_mode+0x160/0x300 [drm_kms_helper])
> [ 34.056555] [<bf4e00f8>] (restore_fbdev_mode [drm_kms_helper]) from
> [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked+0x4
> 0/0x84 [drm_kms_helper])
> [ 34.070190] [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked
> [drm_kms_helper]) from [<bf5c6218>] (rockchip_drm_lastclose
> +0x1c/0x20 [rockchipdrm])
> [ 34.084005] [<bf5c6218>] (rockchip_drm_lastclose [rockchipdrm])
> from [<bf07d20c>] (drm_lastclose+0x48/0xd8 [drm])
> [ 34.094581] [<bf07d20c>] (drm_lastclose [drm]) from [<bf07d560>]
> (drm_release+0x2c4/0x36c [drm])
> [ 34.103526] [<bf07d560>] (drm_release [drm]) from [<c02d7b34>]
> (__fput+0x9c/0x1e8)
> [ 34.111099] [<c02d7b34>] (__fput) from [<c02d7cf0>]
> (____fput+0x18/0x1c)
> [ 34.117802] [<c02d7cf0>] (____fput) from [<c0146ed4>]
> (task_work_run+0xcc/0xf0)
> [ 34.125115] [<c0146ed4>] (task_work_run) from [<c010d1b0>]
> (do_work_pending+0xd0/0xd4)
> [ 34.133034] [<c010d1b0>] (do_work_pending) from [<c0108e28>]
> (slow_work_pending+0xc/0x20)
> [ 34.141250] ---[ end trace 95ed2c3f167607d4 ]---
> [ 34.145921] ------------[ cut here ]------------
> [ 34.150566] WARNING: CPU: 2 PID: 476 at
> /home/ayaka/workspace/rk3288/kernel/linux-kernel/drivers/gpu/drm/rockchip/rockchip_drm_
> vop.c:828 vop_crtc_enable_vblank+0x1ac/0x1b4 [rockchipdrm]
> [ 34.167054] Modules linked in: rockchip_vop_reg rockchipdrm
> dw_hdmi_rockchip dw_hdmi drm_kms_helper cfbfillrect mali_kbase sysc
> opyarea gpio_ir_recv cfbimgblt sysfillrect rc_core dwc2 sysimgblt
> fb_sys_fops panel_simple cfbcopyarea rk_crypto drm nvmem_rockchi
> p_efuse udc_core des_generic phy_rockchip_usb pwm_rockchip pwm_bl
> backlight fb
> [ 34.196651] CPU: 2 PID: 476 Comm: X Tainted: G W
> 4.10.0-rc3-next-20170111+ #148
> [ 34.205078] Hardware name: Rockchip (Device Tree)
> [ 34.209794] [<c0112b98>] (unwind_backtrace) from [<c010dab8>]
> (show_stack+0x20/0x24)
> [ 34.217538] [<c010dab8>] (show_stack) from [<c044973c>]
> (dump_stack+0x8c/0xa0)
> [ 34.224763] [<c044973c>] (dump_stack) from [<c0125f88>]
> (__warn+0xf8/0x110)
> [ 34.231729] [<c0125f88>] (__warn) from [<c01260b8>]
> (warn_slowpath_null+0x30/0x38)
> [ 34.239318] [<c01260b8>] (warn_slowpath_null) from [<bf5c7b7c>]
> (vop_crtc_enable_vblank+0x1ac/0x1b4 [rockchipdrm])
> [ 34.249693] [<bf5c7b7c>] (vop_crtc_enable_vblank [rockchipdrm])
> from [<bf5c61f0>] (rockchip_drm_crtc_enable_vblank+0x48/0x54 [r
> ockchipdrm])
> [ 34.262378] [<bf5c61f0>] (rockchip_drm_crtc_enable_vblank
> [rockchipdrm]) from [<bf07ff80>] (drm_vblank_enable+0x8c/0xf8 [drm])
> [ 34.274077] [<bf07ff80>] (drm_vblank_enable [drm]) from
> [<bf0800b4>] (drm_vblank_get+0xc8/0xf0 [drm])
> [ 34.283616] [<bf0800b4>] (drm_vblank_get [drm]) from [<bf0800fc>]
> (drm_crtc_vblank_get+0x20/0x24 [drm])
> [ 34.293239] [<bf0800fc>] (drm_crtc_vblank_get [drm]) from
> [<bf4dc00c>] (drm_atomic_helper_wait_for_vblanks.part.0+0xa8/0x2a8 [d
> rm_kms_helper])
> [ 34.306146] [<bf4dc00c>] (drm_atomic_helper_wait_for_vblanks.part.0
> [drm_kms_helper]) from [<bf4dc230>] (drm_atomic_helper_wait
> _for_vblanks+0x24/0x28 [drm_kms_helper])
> [ 34.321176] [<bf4dc230>] (drm_atomic_helper_wait_for_vblanks
> [drm_kms_helper]) from [<bf5c6a9c>] (rockchip_atomic_commit_tail+0
> x58/0x68 [rockchipdrm])
> [ 34.334725] [<bf5c6a9c>] (rockchip_atomic_commit_tail
> [rockchipdrm]) from [<bf4dc714>] (commit_tail+0x50/0xb8 [drm_kms_helper])
> [ 34.346330] [<bf4dc714>] (commit_tail [drm_kms_helper]) from
> [<bf4dc870>] (drm_atomic_helper_commit+0xd4/0x13c [drm_kms_helper]
> )
> [ 34.358117] [<bf4dc870>] (drm_atomic_helper_commit
> [drm_kms_helper]) from [<bf09318c>] (drm_atomic_commit+0x5c/0x68 [drm])
> [ 34.369386] [<bf09318c>] (drm_atomic_commit [drm]) from
> [<bf4e00f8>] (restore_fbdev_mode+0x160/0x300 [drm_kms_helper])
> [ 34.380209] [<bf4e00f8>] (restore_fbdev_mode [drm_kms_helper]) from
> [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked+0x4
> 0/0x84 [drm_kms_helper])
> [ 34.393845] [<bf4e171c>] (drm_fb_helper_restore_fbdev_mode_unlocked
> [drm_kms_helper]) from [<bf5c6218>] (rockchip_drm_lastclose
> +0x1c/0x20 [rockchipdrm])
> [ 34.407664] [<bf5c6218>] (rockchip_drm_lastclose [rockchipdrm])
> from [<bf07d20c>] (drm_lastclose+0x48/0xd8 [drm])
> [ 34.418237] [<bf07d20c>] (drm_lastclose [drm]) from [<bf07d560>]
> (drm_release+0x2c4/0x36c [drm])
> [ 34.427179] [<bf07d560>] (drm_release [drm]) from [<c02d7b34>]
> (__fput+0x9c/0x1e8)
> [ 34.434754] [<c02d7b34>] (__fput) from [<c02d7cf0>]
> (____fput+0x18/0x1c)
> [ 34.441458] [<c02d7cf0>] (____fput) from [<c0146ed4>]
> (task_work_run+0xcc/0xf0)
> [ 34.448769] [<c0146ed4>] (task_work_run) from [<c010d1b0>]
> (do_work_pending+0xd0/0xd4)
> [ 34.456688] [<c010d1b0>] (do_work_pending) from [<c0108e28>]
> (slow_work_pending+0xc/0x20)
> [ 34.464856] ---[ end trace 95ed2c3f167607d5 ]---
--
?ark Yao
^ permalink raw reply
* [PATCH v29 9/9] Documentation: dt: chosen properties for arm64 kdump
From: Dave Young @ 2017-01-17 8:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170116082505.GL20972@linaro.org>
On 01/16/17 at 05:25pm, AKASHI Takahiro wrote:
> On Fri, Jan 13, 2017 at 11:17:56AM +0000, Mark Rutland wrote:
> > On Fri, Jan 13, 2017 at 06:13:49PM +0900, AKASHI Takahiro wrote:
> > > On Thu, Jan 12, 2017 at 03:39:45PM +0000, Mark Rutland wrote:
> > > > On Wed, Dec 28, 2016 at 01:37:34PM +0900, AKASHI Takahiro wrote:
> > > > > +linux,crashkernel-base
> > > > > +linux,crashkernel-size
> > > > > +----------------------
> > > > > +
> > > > > +These properties (currently used on PowerPC and arm64) indicates
> > > > > +the base address and the size, respectively, of the reserved memory
> > > > > +range for crash dump kernel.
> > > >
> > > > From this description, it's not clear to me what the (expected)
> > > > consumers of this property are, nor what is expected to provide it.
> > > >
> > > > In previous rounds of review, I had assumed that this was used to
> > > > describe a preference to the first kernel as to what region of memory
> > > > should be used for a subsequent kdump kernel. Looking around, I'm not
> > > > sure if I was correct in that assessment.
> > > >
> > > > I see that arch/powerpc seems to consume this property to configure
> > > > crashk_res, but it also rewrites it based on crashk_res, presumably for
> > > > the benefit of userspace. It's not clear to me how on powerpc the kdump
> > > > kernel knows its memory range -- is more DT modification done in the
> > > > kernel and/or userspace?
> > >
> > > I don't believe that powerpc will rewrite the property any way.
> > > As far as I know from *the source code*, powerpc kernel retrieves
> > > the memory range for crash dump kernel from a kernel command line, i.e.
> > > crashkernel=, and then exposes it through DT to userspace (assuming
> > > kexec-tools).
> >
> > The rewriting I describe is in export_crashk_values() in
> > arch/powerpc/kernel/machine_kexec.c, where the code deletes existing the
> > properties, and adds new ones, to the DT exposed to userspace.
> >
> > So I think we're just quibbling over the definition of "rewrite".
>
> Gotcha
>
> > > > arm64 we should either ensure that /proc/iomem is consistently usable
> > > > (and have userspace consistently use it), or we should expose a new file
> > > > specifically to expose this information.
> > >
> > > The thing that I had in my mind when adding this property is that
> > > /proc/iomem would be obsolete in the future, then we should have
> > > an alternative in hand.
> >
> > Ok.
> >
> > My disagreement is with using the DT as a channel to convey information
> > from the kernel to userspace.
> >
> > I'm more than happy for a new file or other mechanism to express this
> > information. For example, we could add
> > /sys/kernel/kexec_crash_{base,size} or similar.
>
> It may make sense because /sys/kernel/kexec_crash_size already exists,
> so why not kexec_crash_base?
> My concern, however, is that this kind of interface might prevent us from
> allowing multiple regions to be reserved for crash dump kernel in the future.
> (There is an assumption that we have only one region at least on arm64 though.)
In x86 there could be two ranges, one for softiotlb under 4G and another
for range over 4G, but kexec_crash_size only shows the size of
over-4g-range.
It is better to use /proc/iomem, most arches use /proc/iomem. Do you
have any reason why it will be obsolete? At least for the time being it
is fine.
>
> Thanks,
> -Takahiro AKASHI
>
> >
> > > > Further, I do not think we need this property. It makes more sense to me
> > > > for the preference of a a region to be described to the *first* kernel
> > > > using the command line consistently.
> > > >
> > > > So I think we should drop this property, and not use it on arm64. Please
> > > > document this as powerpc only.
> > >
> > > OK, but if we drop the property from arm64 code, we have no reason
> > > to leave its description in this patch.
> > > (In fact, there are a few more (undocumented) properties that only ppc
> > > uses for kdump.)
> >
> > I'm happy to drop it, then.
> >
> > > > > +linux,usable-memory-range
> > > > > +-------------------------
> > > > > +
> > > > > +This property (currently used only on arm64) holds the memory range,
> > > > > +the base address and the size, which can be used as system ram on
> > > > > +the *current* kernel. Note that, if this property is present, any memory
> > > > > +regions under "memory" nodes in DT blob or ones marked as "conventional
> > > > > +memory" in EFI memory map should be ignored.
> > > >
> > > > Could you please replace this with:
> > > >
> > > > This property (arm64 only) holds a base address and size, describing a
> > > > limited region in which memory may be considered available for use by
> > > > the kernel. Memory outside of this range is not available for use.
> > > >
> > > > This property describes a limitation: memory within this range is only
> > > > valid when also described through another mechanism that the kernel
> > > > would otherwise use to determine available memory (e.g. memory nodes
> > > > or the EFI memory map). Valid memory may be sparse within the range.
> > >
> > > Sure.
> >
> > Cheers!
> >
> > Thanks,
> > Mark.
>
> _______________________________________________
> kexec mailing list
> kexec at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kexec
^ permalink raw reply
* Dropping device tree pinmux nodes for GPIO usage (Was: [PATCH 3/5] arm64: dts: sun50i: add MMC nodes)
From: Maxime Ripard @ 2017-01-17 8:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170115155931.l5tjcdhbz6sj3wke@localhost>
On Sun, Jan 15, 2017 at 04:59:32PM +0100, Rask Ingemann Lambertsen wrote:
> On Tue, Jan 03, 2017 at 10:52:12AM +0800, Chen-Yu Tsai wrote:
> > On Tue, Jan 3, 2017 at 7:03 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> > > +
> > > + mmc0_default_cd_pin: mmc0_cd_pin at 0 {
> > > + pins = "PF6";
> > > + function = "gpio_in";
> > > + bias-pull-up;
> > > + };
> >
> > We are starting to drop pinmux nodes for gpio usage.
>
> How do we get the equivalent of bias-pull-up/down and drive-strength if we
> run across a pin that needs it?
Hmm, that's actually a very good question...
For those cases, leave the pinctrl node for now, we'll deal with that
in due time
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v2] watchdog: imx2: fix hang-up on boot for i.MX21, i.MX27 and i.MX31 SoCs
From: Uwe Kleine-König @ 2017-01-17 8:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117012353.6948-1-vz@mleia.com>
Hello Vladimir,
On Tue, Jan 17, 2017 at 03:23:53AM +0200, Vladimir Zapolskiy wrote:
> Power down counter enable/disable bit switch is located in WMCR register,
> but watchdog controllers found on legacy i.MX21, i.MX27 and i.MX31 SoCs
> don't have this register. As a result of writing data to the non-existing
> register on driver probe the SoC hangs up, to fix the problem add more OF
> compatible strings and on this basis get information about availability of
> the WMCR register.
>
> Fixes: 5fe65ce7ccbb ("watchdog: imx2_wdt: Disable power down counter on boot")
> Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> Tested-by: Magnus Lilja <lilja.magnus@gmail.com>
> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: <stable@vger.kernel.org>
> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
> ---
> Changes from v1 to v2:
> * removed i.MX27 and i.MX31 compatibles from the list, since it is expected
> that their DTB files has a reference to the listed i.MX21 compatible,
> many thanks to Uwe Kleine-K?nig for the hint,
> * start the list of compatibles from an i.MX35 specific one, since it is
> agreed that i.MX35 precedes i.MX25, thanks to Uwe Kleine-K?nig for review,
> * added a comment describing any potential changes in future over the list
> of watchdog compatible values,
> * added all collected tags to the commit message.
>
> Changes from RFC to v1:
> * replaced private data struct with a macro as suggested by Guenter,
I didn't see the RFC, but I like a data struct better. It has some
overhead, but allows for easier expansion later, needs less casting and
is easier to understand for a reader (see below).
> * updated the comment in the source code to reflect the change,
> * rearranged and simplified the logic of detecting WMCR presence,
> * pulled the fix out from the series with optional proposed DTS changes.
>
> drivers/watchdog/imx2_wdt.c | 41 ++++++++++++++++++++++++++++++++++++-----
> 1 file changed, 36 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/watchdog/imx2_wdt.c b/drivers/watchdog/imx2_wdt.c
> index 4874b0f..e08c367 100644
> --- a/drivers/watchdog/imx2_wdt.c
> +++ b/drivers/watchdog/imx2_wdt.c
> @@ -30,6 +30,7 @@
> #include <linux/module.h>
> #include <linux/moduleparam.h>
> #include <linux/of_address.h>
> +#include <linux/of_device.h>
> #include <linux/platform_device.h>
> #include <linux/regmap.h>
> #include <linux/watchdog.h>
> @@ -57,6 +58,7 @@
> #define IMX2_WDT_WICR_WICT 0xFF /* -> Interrupt Count Timeout */
>
> #define IMX2_WDT_WMCR 0x08 /* Misc Register */
> +#define IMX2_WDT_NO_WMCR ((void *)true) /* Indicates unavailable WMCR */
I wouldn't group this to the register definition because it serves a
different purpose. Also the negation isn't that nice, making it hard to
understand
if (of_id && !of_id->data)
below. If a struct would be used, the code would be much easier to
understand. Compare to
if (type->has_WMCR)
in my patch which is understandable on first sight.
> #define IMX2_WDT_MAX_TIME 128
> #define IMX2_WDT_DEFAULT_TIME 60 /* in seconds */
> @@ -70,6 +72,8 @@ struct imx2_wdt_device {
> bool ext_reset;
> };
>
> +static const struct of_device_id imx2_wdt_dt_ids[];
You don't need this if you use dev->driver->of_match_table (or still
better of_device_get_match_data (see my patch)).
> +
> static bool nowayout = WATCHDOG_NOWAYOUT;
> module_param(nowayout, bool, 0);
> MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
> @@ -242,6 +246,7 @@ static const struct regmap_config imx2_wdt_regmap_config = {
>
> static int __init imx2_wdt_probe(struct platform_device *pdev)
> {
> + const struct of_device_id *of_id;
> struct imx2_wdt_device *wdev;
> struct watchdog_device *wdog;
> struct resource *res;
> @@ -310,11 +315,13 @@ static int __init imx2_wdt_probe(struct platform_device *pdev)
> }
>
> /*
> - * Disable the watchdog power down counter at boot. Otherwise the power
> - * down counter will pull down the #WDOG interrupt line for one clock
> - * cycle.
> + * If watchdog controller has WMCR, disable the watchdog power
> + * down counter at boot. Otherwise the power down counter will
> + * pull down the #WDOG interrupt line for one clock cycle.
> */
> - regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
> + of_id = of_match_device(imx2_wdt_dt_ids, &pdev->dev);
> + if (of_id && !of_id->data)
> + regmap_write(wdev->regmap, IMX2_WDT_WMCR, 0);
The fix is not complete as this test doesn't work correctly when the wdt
device isn't instanciated by dt but by a platform file (see my patch).
> ret = watchdog_register_device(wdog);
> if (ret) {
> @@ -411,8 +418,32 @@ static int imx2_wdt_resume(struct device *dev)
> static SIMPLE_DEV_PM_OPS(imx2_wdt_pm_ops, imx2_wdt_suspend,
> imx2_wdt_resume);
>
> +/*
> + * The list of compatibles is added to achieve compatibility between
> + * old DTS and new kernel while fixing the incompatibility between
> + * i.MX21/i.MX27/i.MX31 and i.MX35/i.MX25/etc. watchdog controllers.
This comment should be after fsl,imx21-wdt and fsl,imx35-wdt. After all
these are not there for backward compatibility.
> + * Please do *NOT* extend the list by adding a compatible value for
> + * a controller, which is compatible with one of the already listed,
> + * almost certainly "fsl,imx35-wdt" compatible serves newer i.MX SoCs.
> + *
> + * You may consider to shrink the list at your own risk, but this may
> + * break the backward compatibility and users may have to update their
> + * DTB, which is good eventually.
I'd skip the last paragraph.
> + */
> static const struct of_device_id imx2_wdt_dt_ids[] = {
> - { .compatible = "fsl,imx21-wdt", },
> + { .compatible = "fsl,imx21-wdt", .data = IMX2_WDT_NO_WMCR },
> + { .compatible = "fsl,imx35-wdt", },
> + { .compatible = "fsl,imx25-wdt", },
> + { .compatible = "fsl,imx50-wdt", },
> + { .compatible = "fsl,imx51-wdt", },
> + { .compatible = "fsl,imx53-wdt", },
> + { .compatible = "fsl,imx6q-wdt", },
> + { .compatible = "fsl,imx6sl-wdt", },
> + { .compatible = "fsl,imx6sx-wdt", },
> + { .compatible = "fsl,imx6ul-wdt", },
> + { .compatible = "fsl,imx7d-wdt", },
> + { .compatible = "fsl,vf610-wdt", },
> { /* sentinel */ }
> };
> MODULE_DEVICE_TABLE(of, imx2_wdt_dt_ids);
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-K?nig |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* [PATCH v3 1/3] dt: bindings: add documentation for zx2967 family reset controller
From: Philipp Zabel @ 2017-01-17 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484623377-16208-1-git-send-email-baoyou.xie@linaro.org>
On Tue, 2017-01-17 at 11:22 +0800, Baoyou Xie wrote:
> This patch adds dt-binding documentation for zx2967 family
> reset controller.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> Reviewed-by: Shawn Guo <shawnguo@kernel.org>
Thanks, I've applied all three patches with Shawn's Reviewed-by: on the
driver patch.
regards
Philipp
> ---
> .../devicetree/bindings/reset/zte,zx2967-reset.txt | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
>
> diff --git a/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
> new file mode 100644
> index 0000000..b015508
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/zte,zx2967-reset.txt
> @@ -0,0 +1,20 @@
> +ZTE zx2967 SoCs Reset Controller
> +=======================================
> +
> +Please also refer to reset.txt in this directory for common reset
> +controller binding usage.
> +
> +Required properties:
> +- compatible: should be one of the following.
> + * zte,zx296718-reset
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +- #reset-cells: must be 1.
> +
> +example:
> +
> + reset: reset-controller at 1461060 {
> + compatible = "zte,zx296718-reset";
> + reg = <0x01461060 0x8>;
> + #reset-cells = <1>;
> + };
^ permalink raw reply
* [GIT PULL] STM32 DT changes for v4.11 #1
From: Alexandre Torgue @ 2017-01-17 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170117065309.GS16607@localhost>
Hi Olof
On 01/17/2017 07:53 AM, Olof Johansson wrote:
> On Mon, Jan 16, 2017 at 04:49:29PM +0100, Alexandre Torgue wrote:
>> Hi Olof, Arnd and Kevin,
>>
>> Please consider this first round of STM32 DT updates for v4.11:
>>
>> The following changes since commit 7ce7d89f48834cefece7804d38fc5d85382edf77:
>>
>> Linux 4.10-rc1 (2016-12-25 16:13:08 -0800)
>>
>> are available in the git repository at:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git
>> tags/stm32-dt-for-v4.11-1
>>
>> for you to fetch changes up to d99c66406a846748e26989759caa7e966c1804dd:
>>
>> ARM: dts: stm32: enable RTC on stm32429i-eval (2017-01-16 14:38:14 +0100)
>>
>> ----------------------------------------------------------------
>> STM32 DT updates for v4.11, round 1.
>>
>> Highlights:
>> ----------
>>
>> - ADD RTC support on STM32F429 MCU
>> - Enable RTC on STM32F469and STM32F429 boards
>> - ADD ADC support on STM32F429 MCU
>> - Enable ADC on STM32F429 Eval board
>> - Add I2S external clock
>> - Fix memory size for STM32F429 Disco
>>
>> Note:
>> -----
>> First patch "clk: stm32f4: Update DT bindings documentation")
>> has already been merged in clock tree.
>
> Ugh. That patch doesn't just update documentation. It also updates the
> dt-include file.
>
> So, if it's already been merged into the clock tree, then we can't merge
> a separate copy here.
>
> By now, easiest is to hold off making use of it until it's on a shared
> branch, i.e. next release. Use the numerical values until then.
I know it is not a comfortable situation. I discussed this point with
Arnd last week. The result of the discussion was to start from 4.10-rc1
+ "patch include/dt-bindings..." and to add my patches then create pull
request. Maybe I miss something.
>
>> ----------------------------------------------------------------
>> Amelie Delaunay (5):
>> ARM: dts: stm32: set HSE_RTC clock frequency to 1 MHz on stm32f429
>> ARM: dts: stm32: Add RTC support for STM32F429 MCU
>> ARM: dts: stm32: enable RTC on stm32f429-disco
>> ARM: dts: stm32: enable RTC on stm32f469-disco
>> ARM: dts: stm32: enable RTC on stm32429i-eval
>>
>> Bruno Herrera (1):
>> ARM: dts: stm32: Fix memory size from 8MB to 16MB on stm32f469-disco
>> board
>>
>> Bruno Meirelles Herrera (1):
>> ARM: dts: stm32: Add missing USART3 pin config to stm32f469-disco
>> board
>>
>> Fabrice GASNIER (2):
>> ARM: dts: stm32: Add ADC support to stm32f429
>> ARM: dts: stm32: enable ADC on stm32f429i-eval board
>>
>> Gabriel Fernandez (3):
>> clk: stm32f4: Update DT bindings documentation
>> ARM: dts: stm32: Add external I2S clock on stm32f429 MCU
>> ARM: dts: stm32: Include auxiliary stm32fx clock definition
>
> How did you generate this pull request? You didn't include a diffstat with it,
> which is useful for us to make sure that what we merged is what you expected us
> to merge.
Sorry!! A bad copy/paste.
regards
Alex
>
> Not merging, please revisit based on the above.
>
>
> -Olof
>
^ permalink raw reply
* [PATCH v1 3/3] watchdog: zx2967: add watchdog controller driver for ZTE's zx2967 family
From: Shawn Guo @ 2017-01-17 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484540395-3335-3-git-send-email-baoyou.xie@linaro.org>
On Mon, Jan 16, 2017 at 12:19:55PM +0800, Baoyou Xie wrote:
> This patch adds watchdog controller driver for ZTE's zx2967 family.
>
> Signed-off-by: Baoyou Xie <baoyou.xie@linaro.org>
> ---
> drivers/watchdog/Kconfig | 10 ++
> drivers/watchdog/Makefile | 1 +
> drivers/watchdog/zx2967_wdt.c | 405 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 416 insertions(+)
> create mode 100644 drivers/watchdog/zx2967_wdt.c
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 3eb58cb..79027da 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -714,6 +714,16 @@ config ASPEED_WATCHDOG
> To compile this driver as a module, choose M here: the
> module will be called aspeed_wdt.
>
> +config ZX2967_WATCHDOG
> + tristate "ZTE zx2967 SoCs watchdog support"
> + depends on ARCH_ZX
> + select WATCHDOG_CORE
> + help
> + Say Y here to include support for the watchdog timer
> + in ZTE zx2967 SoCs.
> + To compile this driver as a module, choose M here: the
> + module will be called zx2967_wdt.
> +
> # AVR32 Architecture
>
> config AT32AP700X_WDT
> diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
> index caa9f4a..ea08925 100644
> --- a/drivers/watchdog/Makefile
> +++ b/drivers/watchdog/Makefile
> @@ -82,6 +82,7 @@ obj-$(CONFIG_BCM7038_WDT) += bcm7038_wdt.o
> obj-$(CONFIG_ATLAS7_WATCHDOG) += atlas7_wdt.o
> obj-$(CONFIG_RENESAS_WDT) += renesas_wdt.o
> obj-$(CONFIG_ASPEED_WATCHDOG) += aspeed_wdt.o
> +obj-$(CONFIG_ZX2967_WATCHDOG) += zx2967_wdt.o
>
> # AVR32 Architecture
> obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
> diff --git a/drivers/watchdog/zx2967_wdt.c b/drivers/watchdog/zx2967_wdt.c
> new file mode 100644
> index 0000000..8791dd2
> --- /dev/null
> +++ b/drivers/watchdog/zx2967_wdt.c
> @@ -0,0 +1,405 @@
> +/*
> + * watchdog driver for ZTE's zx2967 family
> + *
> + * Copyright (C) 2017 ZTE Ltd.
> + *
> + * Author: Baoyou Xie <baoyou.xie@linaro.org>
> + *
> + * License terms: GNU General Public License (GPL) version 2
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_address.h>
> +#include <linux/platform_device.h>
> +#include <linux/reboot.h>
> +#include <linux/reset.h>
> +#include <linux/watchdog.h>
> +
> +#define ZX2967_WDT_CFG_REG 0x4
> +#define ZX2967_WDT_LOAD_REG 0x8
> +#define ZX2967_WDT_REFRESH_REG 0x18
> +#define ZX2967_WDT_START_REG 0x1c
> +
> +#define ZX2967_WDT_REFRESH_MASK 0x3f
> +
> +#define ZX2967_WDT_CFG_DIV(n) ((((n)&0xff) - 1) << 8)
Please have a space before and after '&' operator.
> +#define ZX2967_WDT_START_EN 0x1
> +
> +#define ZX2967_WDT_WRITEKEY 0x12340000
> +
> +#define ZX2967_WDT_DIV_DEFAULT 16
> +#define ZX2967_WDT_DEFAULT_TIMEOUT 32
> +#define ZX2967_WDT_MIN_TIMEOUT 1
> +#define ZX2967_WDT_MAX_TIMEOUT 500
> +#define ZX2967_WDT_MAX_COUNT 0xffff
> +
> +#define ZX2967_WDT_FLAG_REBOOT_MON (1 << 0)
> +
> +#define ZX2967_RESET_MASK_REG 0xb0
> +
> +#define zx2967_wdt_write_reg(v, r) \
> + writel((v) | ZX2967_WDT_WRITEKEY, r)
> +#define zx2967_wdt_read_reg(r) readl(r)
I think inline functions are better than macros in this case.
> +
> +static bool nowayout = WATCHDOG_NOWAYOUT;
> +static unsigned int timeout = ZX2967_WDT_DEFAULT_TIMEOUT;
The variable name is too generic. For example, the same name is used in
functions like __zx2967_wdt_set_timeout().
> +
> +struct zx2967_wdt {
> + struct device *dev;
> + struct clk *clock;
> + void __iomem *reg_base;
> + unsigned int conf;
> + unsigned int load;
> + unsigned int flags;
> + spinlock_t lock;
> + struct watchdog_device wdt_device;
> + struct notifier_block restart_handler;
> + struct notifier_block reboot_handler;
> +};
> +
> +static void zx2967_wdt_refresh(struct zx2967_wdt *wdt)
> +{
> + unsigned int val;
u32 for 32-bit register access is more readable.
> +
> + spin_lock(&wdt->lock);
> +
> + val = zx2967_wdt_read_reg(wdt->reg_base + ZX2967_WDT_REFRESH_REG);
> + val ^= ZX2967_WDT_REFRESH_MASK;
> + zx2967_wdt_write_reg(val, wdt->reg_base + ZX2967_WDT_REFRESH_REG);
> +
> + spin_unlock(&wdt->lock);
> +}
> +
> +static void __zx2967_wdt_stop(struct zx2967_wdt *wdt)
> +{
> + unsigned int val;
> +
> + spin_lock(&wdt->lock);
> +
> + val = zx2967_wdt_read_reg(wdt->reg_base + ZX2967_WDT_START_REG);
> + val &= ~(ZX2967_WDT_START_EN);
The parentheses is not needed.
> + zx2967_wdt_write_reg(val, wdt->reg_base + ZX2967_WDT_START_REG);
> +
> + spin_unlock(&wdt->lock);
> +}
> +
> +static void __zx2967_wdt_start(struct zx2967_wdt *wdt)
> +{
> + unsigned int val;
> +
> + spin_lock(&wdt->lock);
> +
> + val = zx2967_wdt_read_reg(wdt->reg_base + ZX2967_WDT_START_REG);
> + val |= ZX2967_WDT_START_EN;
> + zx2967_wdt_write_reg(val, wdt->reg_base + ZX2967_WDT_START_REG);
> +
> + spin_unlock(&wdt->lock);
> +}
> +
> +static unsigned int
> +__zx2967_wdt_set_timeout(struct zx2967_wdt *wdt, unsigned int timeout)
> +{
> + unsigned int freq = clk_get_rate(wdt->clock);
> + unsigned int divisor = ZX2967_WDT_DIV_DEFAULT, count;
Unless the variables are closely related, it's more conventional to have
each variable on a new line.
> +
> + count = timeout * freq;
> + if (count > divisor * ZX2967_WDT_MAX_COUNT)
> + divisor = DIV_ROUND_UP(count, ZX2967_WDT_MAX_COUNT);
> + count = DIV_ROUND_UP(count, divisor);
> + zx2967_wdt_write_reg(ZX2967_WDT_CFG_DIV(divisor),
> + wdt->reg_base + ZX2967_WDT_CFG_REG);
> + zx2967_wdt_write_reg(count, wdt->reg_base + ZX2967_WDT_LOAD_REG);
> + zx2967_wdt_refresh(wdt);
> +
> + wdt->load = count;
> + dev_info(wdt->dev, "count=%d, timeout=%d, divisor=%d\n",
> + count, timeout, divisor);
Noisy. Maybe dev_dbg().
> +
> + return (count * divisor) / freq;
> +}
> +
> +static int zx2967_wdt_set_timeout(struct watchdog_device *wdd,
> + unsigned int timeout)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + if (watchdog_timeout_invalid(&wdt->wdt_device, timeout)) {
> + dev_err(wdt->dev, "timeout %d is invalid\n", timeout);
> +
Drop the newline.
> + return -EINVAL;
> + }
> +
> + wdd->timeout = __zx2967_wdt_set_timeout(wdt, timeout);
> +
> + return 0;
> +}
> +
> +static int zx2967_wdt_start(struct watchdog_device *wdd)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + __zx2967_wdt_stop(wdt);
> + zx2967_wdt_set_timeout(wdd, wdd->timeout);
> + __zx2967_wdt_start(wdt);
> +
> + return 0;
> +}
> +
> +static int zx2967_wdt_stop(struct watchdog_device *wdd)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + __zx2967_wdt_stop(wdt);
> +
> + return 0;
> +}
> +
> +static int zx2967_wdt_keepalive(struct watchdog_device *wdd)
> +{
> + struct zx2967_wdt *wdt = watchdog_get_drvdata(wdd);
> +
> + zx2967_wdt_refresh(wdt);
> +
> + return 0;
> +}
> +
> +#define ZX2967_WDT_OPTIONS \
> + (WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING | WDIOF_MAGICCLOSE)
> +static const struct watchdog_info zx2967_wdt_ident = {
> + .options = ZX2967_WDT_OPTIONS,
> + .firmware_version = 0,
> + .identity = "zx2967 watchdog",
> +};
> +
> +static struct watchdog_ops zx2967_wdt_ops = {
> + .owner = THIS_MODULE,
> + .start = zx2967_wdt_start,
> + .stop = zx2967_wdt_stop,
> + .ping = zx2967_wdt_keepalive,
> + .set_timeout = zx2967_wdt_set_timeout,
> +};
> +
> +static void zx2967_wdt_fix_sysdown(struct zx2967_wdt *wdt)
> +{
> + __zx2967_wdt_stop(wdt);
> + __zx2967_wdt_set_timeout(wdt, 15);
> + __zx2967_wdt_start(wdt);
> +}
> +
> +static int zx2967_wdt_notify_sys(struct notifier_block *this,
> + unsigned long code, void *unused)
> +{
> + struct zx2967_wdt *wdt = container_of(this, struct zx2967_wdt,
> + reboot_handler);
> +
> + wdt->flags |= ZX2967_WDT_FLAG_REBOOT_MON;
> + switch (code) {
> + case SYS_HALT:
> + case SYS_POWER_OFF:
> + case SYS_RESTART:
> + zx2967_wdt_fix_sysdown(wdt);
> + break;
> + default:
> + break;
> + }
> +
> + return 0;
> +}
> +
> +static int zx2967_wdt_restart(struct notifier_block *this,
> + unsigned long mode, void *cmd)
> +{
> + struct zx2967_wdt *wdt;
> +
> + wdt = container_of(this, struct zx2967_wdt, restart_handler);
> +
> + zx2967_wdt_stop(&wdt->wdt_device);
> +
> + zx2967_wdt_write_reg(0x80, wdt->reg_base + ZX2967_WDT_LOAD_REG);
> + zx2967_wdt_refresh(wdt);
> + zx2967_wdt_write_reg(ZX2967_WDT_START_EN,
> + wdt->reg_base + ZX2967_WDT_START_REG);
> +
> + zx2967_wdt_start(&wdt->wdt_device);
> + /* wait for reset*/
> + mdelay(500);
> +
> + return NOTIFY_DONE;
> +}
> +
> +static void zx2967_reset_mask_config(struct device *dev)
> +{
> + struct device_node *np = NULL;
> + void __iomem *reg;
> + unsigned int val, mask, config, size;
> + const unsigned int *prop;
> +
> + prop = of_get_property(dev->of_node, "reset-mask-config", &size);
> + if (size < (sizeof(*prop) * 2)) {
> + dev_err(dev, "bad data for reset-mask-config");
> + return;
> + }
> + config = be32_to_cpup(prop++);
> + mask = be32_to_cpup(prop);
> + np = of_find_compatible_node(NULL, NULL, "zte,aon-sysctrl");
> + if (!np) {
> + dev_err(dev, "Cannot found pcu device node\n");
> + return;
> + }
> + reg = of_iomap(np, 0) + ZX2967_RESET_MASK_REG;
> + of_node_put(np);
We should use syscon interface to access sysctrl block.
> +
> + val = readl(reg);
> + val &= ~mask;
> + val |= config;
> + writel(val, reg);
> +}
> +
> +static int zx2967_wdt_probe(struct platform_device *pdev)
> +{
> + struct device *dev;
> + struct zx2967_wdt *wdt;
> + struct resource *base;
> + int err, ret = 0;
> + unsigned int rate, val;
> +
> + struct reset_control *rstc;
> +
> + dev = &pdev->dev;
> +
> + wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
> + if (!wdt) {
> + ret = -ENOMEM;
> + goto out;
> + }
return -ENOMEM;
> +
> + platform_set_drvdata(pdev, wdt);
> +
> + wdt->dev = dev;
> + spin_lock_init(&wdt->lock);
> +
> + wdt->wdt_device.info = &zx2967_wdt_ident;
> + wdt->wdt_device.ops = &zx2967_wdt_ops;
> + wdt->wdt_device.timeout = ZX2967_WDT_DEFAULT_TIMEOUT;
> + wdt->wdt_device.max_timeout = ZX2967_WDT_MAX_TIMEOUT;
> + wdt->wdt_device.min_timeout = ZX2967_WDT_MIN_TIMEOUT;
> + wdt->wdt_device.parent = &pdev->dev;
> +
> + base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + wdt->reg_base = devm_ioremap_resource(dev, base);
It should be error checked.
> +
> + if (of_find_property(dev->of_node, "reset-mask-config", NULL))
> + zx2967_reset_mask_config(dev);
> +
> + wdt->reboot_handler.notifier_call = zx2967_wdt_notify_sys;
> + ret = register_reboot_notifier(&wdt->reboot_handler);
> + wdt->clock = devm_clk_get(dev, "wdtclk");
> + if (IS_ERR(wdt->clock)) {
> + dev_err(dev, "failed to find watchdog clock source\n");
> + ret = PTR_ERR(wdt->clock);
> + goto out;
> + }
> + ret = clk_prepare_enable(wdt->clock);
> + if (ret < 0) {
> + dev_err(dev, "failed to enable clock\n");
> + goto out;
> + }
> +
> + rate = clk_get_rate(wdt->clock);
> + if (rate == 24000000)
> + ret = clk_set_rate(wdt->clock, 32768);
> + rate = clk_get_rate(wdt->clock);
> +
> + rstc = devm_reset_control_get(dev, "wdtrst");
> + if (!rstc) {
> + dev_info(dev, "rstc get failed");
> + } else {
> + reset_control_assert(rstc);
> + mdelay(10);
> + reset_control_deassert(rstc);
> + }
> +
> + watchdog_set_drvdata(&wdt->wdt_device, wdt);
> +
> + watchdog_init_timeout(&wdt->wdt_device, timeout, &pdev->dev);
> + watchdog_set_nowayout(&wdt->wdt_device, nowayout);
> +
> + zx2967_wdt_stop(&wdt->wdt_device);
> +
> + err = watchdog_register_device(&wdt->wdt_device);
> + if (unlikely(err)) {
> + ret = err;
> + goto fail_register;
> + }
> +
> + wdt->restart_handler.notifier_call = zx2967_wdt_restart;
> + wdt->restart_handler.priority = 128;
> + ret = register_restart_handler(&wdt->restart_handler);
> + if (ret) {
> + pr_err("cannot register restart handler, %d\n", ret);
dev_err()
> + goto fail_restart;
> + }
> +
> + val = zx2967_wdt_read_reg(wdt->reg_base + ZX2967_WDT_START_REG);
> + dev_info(&pdev->dev, "watchdog enabled (timeout=%d sec, nowayout=%d)",
> + wdt->wdt_device.timeout, nowayout);
> +
> + return 0;
> +
> +fail_restart:
> + watchdog_unregister_device(&wdt->wdt_device);
> +fail_register:
> + clk_disable_unprepare(wdt->clock);
> +out:
> + return ret;
> +}
> +
> +static int zx2967_wdt_remove(struct platform_device *pdev)
> +{
> + struct zx2967_wdt *wdt = platform_get_drvdata(pdev);
> +
> + unregister_restart_handler(&wdt->restart_handler);
> + watchdog_unregister_device(&wdt->wdt_device);
> + clk_disable_unprepare(wdt->clock);
> +
> + return 0;
> +}
> +
> +static void zx2967_wdt_shutdown(struct platform_device *pdev)
> +{
> + struct zx2967_wdt *wdt = platform_get_drvdata(pdev);
> +
> + if (!(wdt->flags & ZX2967_WDT_FLAG_REBOOT_MON))
> + zx2967_wdt_stop(&wdt->wdt_device);
> +}
> +
> +static const struct of_device_id zx2967_wdt_match[] = {
> + { .compatible = "zte,zx296718-wdt", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(of, zx2967_wdt_match);
> +
> +static const struct platform_device_id zx2967_wdt_ids[] = {
> + { .name = "zx2967-wdt", },
> + {}
> +};
> +MODULE_DEVICE_TABLE(platform, zx2967_wdt_ids);
This is not needed, as we do not support platform probe but only DT on
ZTE platforms.
Shawn
> +
> +static struct platform_driver zx2967_wdt_driver = {
> + .probe = zx2967_wdt_probe,
> + .remove = zx2967_wdt_remove,
> + .shutdown = zx2967_wdt_shutdown,
> + .id_table = zx2967_wdt_ids,
> + .driver = {
> + .name = "zx2967-wdt",
> + .of_match_table = of_match_ptr(zx2967_wdt_match),
> + },
> +};
> +module_platform_driver(zx2967_wdt_driver);
> +
> +MODULE_AUTHOR("Baoyou Xie <baoyou.xie@linaro.org>");
> +MODULE_DESCRIPTION("ZTE zx2967 Watchdog Device Driver");
> +MODULE_LICENSE("GPL");
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH] ARM: dts: imx6q-utilite-pro: enable 2nd display pipeline
From: Philipp Zabel @ 2017-01-17 8:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ec9676f344eb4786a28a3c7b969f0e94@rwthex-s1-b.rwth-ad.de>
Hi Christopher,
On Fri, 2016-12-02 at 15:37 +0100, christopher.spinrath at rwth-aachen.de
wrote:
> From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
>
> Apart from the already enabled Designware HDMI port, the Utilite Pro
> has a second display pipeline which has the following shape:
>
> IPU1 DI0 --> Parallel display --> tfp410 rgb24 to DVI encoder
> --> HDMI connector.
> Enable support for it.
>
> In addition, since this pipeline is hardwired to IPU1, sever the link
> between IPU1 and the SoC-internal Designware HDMI encoder forcing the
> latter to be connected to IPU2 instead of IPU1. Otherwise, it is not
> possible to drive both displays at high resolution due to the bandwidth
> limitations of a single IPU.
>
> Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
>
> ---
>
> Hi all,
>
> the removal of the link between IPU1 and the Designware HDMI encoder is the
> result of a discussion I had with Philipp Zabel:
>
> https://lists.freedesktop.org/archives/dri-devel/2016-November/125399.html .
>
> Altough it is not possible to connect anything else to IPU1 on the Utilite, this
> approach has at least one disadvantage: if the resolution is low enough such
> that a single IPU can handle both displays then muxing both displays to IPU1
> would reduce the power consumption.
>
> However, IMHO omitting the link IPU1 <--> DW HDMI is still the preferrable
> solution since I'm not aware of any OS/driver that is capable of switching IPUs
> or can handle the bandwidth limitation in a sane way. In particular, Linux is
> unusable when both displays are supposed to be driven at high resolution and
> both muxing options for the DW HDMI are available (this is not a userspace
> issue; the system becomes almost unresponsive as soon as the kernel sets the
> initial resolution).
>
> Cheers,
> Christopher
>
> P.S.: this patch depends on the tfp410 bridge driver which has recently been
> merged into drm-next.
>
> arch/arm/boot/dts/imx6q-utilite-pro.dts | 115 ++++++++++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
> index 2200994..69bdd82 100644
> --- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
> +++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
> @@ -59,6 +59,33 @@
> rtc1 = &snvs_rtc;
> };
>
> + encoder {
> + compatible = "ti,tfp410";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> +
> + tfp410_in: endpoint {
> + remote-endpoint = <¶llel_display_out>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> +
> + tfp410_out: endpoint {
> + remote-endpoint = <&hdmi_connector_in>;
> + };
> + };
> + };
> + };
> +
> gpio-keys {
> compatible = "gpio-keys";
> pinctrl-names = "default";
> @@ -72,6 +99,19 @@
> };
> };
>
> + hdmi-connector {
> + compatible = "hdmi-connector";
> +
> + type = "a";
> + ddc-i2c-bus = <&i2c_dvi_ddc>;
> +
> + port {
> + hdmi_connector_in: endpoint {
> + remote-endpoint = <&tfp410_out>;
> + };
> + };
> + };
> +
> i2cmux {
> compatible = "i2c-mux-gpio";
> pinctrl-names = "default";
> @@ -105,8 +145,46 @@
> #size-cells = <0>;
> };
> };
> +
> + parallel-display {
> + compatible = "fsl,imx-parallel-display";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ipu1>;
> +
> + interface-pix-fmt = "rgb24";
This is not necessary if the connector created by the tpf410 has the
correct media bus format set in its display_info structure. This can be
done in tfp410_attach, before calling drm_mode_connector_attach_encoder:
u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
drm_display_info_set_bus_formats(&dvi->connector.display_info,
&bus_format, 1);
After this is done, the above line should be removed in a follow-up
patch.
> + port at 0 {
> + reg = <0>;
> +
> + parallel_display_in: endpoint {
> + remote-endpoint = <&ipu1_di0_disp0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <1>;
> +
> + parallel_display_out: endpoint {
> + remote-endpoint = <&tfp410_in>;
> + };
> + };
> + };
> };
>
> +/*
> + * A single IPU is not able to drive both display interfaces available on the
> + * Utilite Pro at high resolution due to its bandwidth limitation. Since the
> + * tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the
> + * SoC-internal Designware HDMI encoder forcing the latter to be connected to
> + * IPU2 instead of IPU1.
> + */
> +/delete-node/&ipu1_di0_hdmi;
> +/delete-node/&hdmi_mux_0;
> +/delete-node/&ipu1_di1_hdmi;
> +/delete-node/&hdmi_mux_1;
> +
> &hdmi {
> ddc-i2c-bus = <&i2c2>;
> status = "okay";
> @@ -151,6 +229,39 @@
> >;
> };
>
> + pinctrl_ipu1: ipu1grp {
> + fsl,pins = <
> + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
> + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
> + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
> + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
> + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
> + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
> + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
> + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
> + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
> + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
> + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
> + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
> + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
> + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
> + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
> + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
> + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
> + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
> + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
> + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
> + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
> + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
> + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
> + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
> + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
> + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
> + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
> + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
> + >;
> + };
> +
> pinctrl_uart2: uart2grp {
> fsl,pins = <
> MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
> @@ -194,6 +305,10 @@
> };
> };
>
> +&ipu1_di0_disp0 {
> + remote-endpoint = <¶llel_display_in>;
> +};
> +
> &pcie {
> pcie at 0,0 {
> reg = <0x000000 0 0 0 0>;
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
regards
Philipp
^ permalink raw reply
* [PATCH] ARM: shmobile: r8a7779: marzen: Fix sata device status
From: Simon Horman @ 2017-01-17 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484585813-22534-1-git-send-email-geert+renesas@glider.be>
On Mon, Jan 16, 2017 at 05:56:53PM +0100, Geert Uytterhoeven wrote:
> Device nodes representing I/O devices should be marked disabled in the
> SoC-specific DTS, and overridden by board-specific DTSes where needed.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have queued this up for v4.11.
^ permalink raw reply
* [PATCH] arm64: dts: r8a7795: Add missing power-domains property for sata
From: Simon Horman @ 2017-01-17 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484585873-30075-1-git-send-email-geert+renesas@glider.be>
On Mon, Jan 16, 2017 at 05:57:53PM +0100, Geert Uytterhoeven wrote:
> This went unnoticed as the sata_rcar driver doesn't support Runtime PM
> yet, but manages module clocks manually.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have queued this up for v4.11.
^ permalink raw reply
* [PATCH] clocksource: exynos_mct: clear irq at stop local mct to fix suspend
From: Thomas Gleixner @ 2017-01-17 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484628876-22065-1-git-send-email-jy0922.shim@samsung.com>
On Tue, 17 Jan 2017, Joonyoung Shim wrote:
> This patch adds clear interrupt to exynos4_mct_dying_cpu(). Without
Please read Documentation/process/SubmittingPatches. Search for 'This
patch' ....
A changelog should explain the problem first and then explain the concept
of the fix. You start explaining WHAT the patch does and not what the
problem is.
> clearing, after turning on non boot cpu at wakeup from suspend to
> ram, not cleared tick interrupt occurs and it causes following null
> deference for MCT_INT_SPI type mct.
This has nothing to do with suspend. That can happen with a normal cpu
offline/online sequence as well, which happens to be utilized by
suspend/resume.
Please trim back traces so they contain only useful information. There is
no point in having all these useless stack entries and whatever, which do
not at all help to diagnose the problem.
I'll fix that up when applying the patch. Checkout the resulting changelog
and please be more careful next time.
> [ 51.251378] Unable to handle kernel NULL pointer dereference at virtual address 00000040
> [ 51.257980] pgd = c0004000
> [ 51.260666] [00000040] *pgd=00000000
> [ 51.264222] Internal error: Oops: 5 [#1] PREEMPT SMP ARM
> [ 51.269503] Modules linked in:
> [ 51.272541] CPU: 7 PID: 53 Comm: ksoftirqd/7 Tainted: G W 4.9.0-rc7-next-20161201-00007-g74076859ec44 #140
> [ 51.283282] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
> [ 51.289348] task: ee942d00 task.stack: ee960000
> [ 51.293861] PC is at tick_periodic+0x38/0xb0
> [ 51.298102] LR is at tick_handle_periodic+0x1c/0x90
> [ 51.486409] [<c0183358>] (tick_periodic) from [<ef013ec0>] (0xef013ec0)
> [ 51.492990] Code: ee1d2f90 e34c30b6 e8bd4070 e7923003 (e5933040)
> [ 51.499057] ---[ end trace 995703fe1bede0b4 ]---
> Fixes: 56a94f13919c ("clocksource: exynos_mct: Avoid blocking calls in the cpu hotplug notifier")
> Cc: stable at vger.kernel.org #v4.2+ #v4.1.4+ #3.18.18+ #v3.16.18+ #v3.12.46+
Adding the version tags is pointless when you have a Fixes tag, which
allows the stable maintainers to find the affected kernels automatically.
> Reported-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
This Signed-off-by sequence is wrong.
Seung-Woo reported the problem. You wrote the patch and sent it to the
mailing list. The above sequence suggests that you wrote the patch and
Seung-Woo sent it to the mailing list, which is obviously not the case.
Thanks,
tglx
^ permalink raw reply
* [PATCH v2 2/4] clk: sunxi-ng: add support for V3s CCU
From: Maxime Ripard @ 2017-01-17 9:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170116180116.36729-3-icenowy@aosc.xyz>
Hi,
On Tue, Jan 17, 2017 at 02:01:14AM +0800, Icenowy Zheng wrote:
> V3s has a similar but cut-down CCU to H3.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
Output from checkpatch:
total: 5 errors, 2 warnings, 3 checks, 857 lines checked
> I think I should make a comparsion between V3s and H3 CCU here:
> (I won't mention the missing/added clocks here, only list conflicting clocks)
That should be in your commit log.
> - "bus-ehci0" is at different bit (The bit that is "bus-ehci0" on V3s is
> "bus-ehci2" on H3)
> - The mux of "ce" is different. (According the view at V3s datasheet by the
> author of sun4i-ss, V3s may have sun4i-ss, not sun8i-ce)
> - The mux of "de" is different. (V3s do not have "pll-de", but it can mux "de"
> to "pll-video")
> - Clocks about CSI largely differs. (As V3s is designed as a camera SoC, and
> it have an extra "pll-isp")
OK.
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v2 1/4] arm: sunxi: add support for V3s SoC
From: Maxime Ripard @ 2017-01-17 9:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170116180116.36729-2-icenowy@aosc.xyz>
On Tue, Jan 17, 2017 at 02:01:13AM +0800, Icenowy Zheng wrote:
> Allwinner V3s is a low-end single-core Cortex-A7 SoC, with 64MB
> integrated DRAM, and several peripherals.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes in v2:
> - Used linux-sunxi.org wiki hosted address of V3s datasheet.
>
> Note: the V3s datasheet contains its user manual.
That would be great to use User Manual in the filename rather than
datasheet then. The datasheet is something different.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] tcb_clksrc: Use 32 bit tcb as sched_clock
From: Daniel Lezcano @ 2017-01-17 9:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170111135059.21318-1-david.engraf@sysgo.com>
On 11/01/2017 14:50, David Engraf wrote:
> On newer boards the TC can be read as single 32 bit value without locking.
> Thus the clock can be used as reference for sched_clock which is much more
> accurate than the jiffies implementation.
>
> Tested on a Atmel SAMA5D2 board.
Is this change backward compatible ?
> Signed-off-by: David Engraf <david.engraf@sysgo.com>
> ---
> drivers/clocksource/tcb_clksrc.c | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
> index d4ca996..745844e 100644
> --- a/drivers/clocksource/tcb_clksrc.c
> +++ b/drivers/clocksource/tcb_clksrc.c
> @@ -10,6 +10,7 @@
> #include <linux/io.h>
> #include <linux/platform_device.h>
> #include <linux/atmel_tc.h>
> +#include <linux/sched_clock.h>
>
>
> /*
> @@ -56,11 +57,16 @@ static u64 tc_get_cycles(struct clocksource *cs)
> return (upper << 16) | lower;
> }
>
> -static u64 tc_get_cycles32(struct clocksource *cs)
> +static u32 tc_get_cv32(void)
> {
> return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
> }
>
> +static u64 tc_get_cycles32(struct clocksource *cs)
> +{
> + return tc_get_cv32();
> +}
> +
> static struct clocksource clksrc = {
> .name = "tcb_clksrc",
> .rating = 200,
> @@ -69,6 +75,11 @@ static struct clocksource clksrc = {
> .flags = CLOCK_SOURCE_IS_CONTINUOUS,
> };
>
> +static u64 notrace tc_read_sched_clock(void)
> +{
> + return tc_get_cv32();
> +}
> +
> #ifdef CONFIG_GENERIC_CLOCKEVENTS
>
> struct tc_clkevt_device {
> @@ -339,6 +350,9 @@ static int __init tcb_clksrc_init(void)
> clksrc.read = tc_get_cycles32;
> /* setup ony channel 0 */
> tcb_setup_single_chan(tc, best_divisor_idx);
> +
> + /* register sched_clock on chips with single 32 bit counter */
> + sched_clock_register(tc_read_sched_clock, 32, divided_rate);
> } else {
> /* tclib will give us three clocks no matter what the
> * underlying platform supports.
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH v19 00/15] acpi, clocksource: add GTDT driver and GTDT support in arm_arch_timer
From: Fu Wei @ 2017-01-17 9:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170116170010.GH5908@leverpostej>
Hi Mark,
On 17 January 2017 at 01:00, Mark Rutland <mark.rutland@arm.com> wrote:
> Hi,
>
> On Wed, Dec 21, 2016 at 02:45:48PM +0800, fu.wei at linaro.org wrote:
>> From: Fu Wei <fu.wei@linaro.org>
>>
>> This patchset:
>> (1)Preparation for adding GTDT support in arm_arch_timer:
>> 1. Move some enums and marcos to header file;
>> 2. Add a new enum for spi type;
>> 3. Improve printk relevant code;
>> 4. Rename some enums and defines;
>
> Can we please rework these first few patches into a series:
>
> 1. Clean up printk() usage
> 2. Rename the type macros
> 3. Rename the PPI enum & enum values
> 4. Move the type macro and PPI enum into a header
> 5. Add new enum for SPIs
>
> Please leave CNTHCL_* as they originally were. It's not part of the
> interface of the driver, and leaving them as they are will save us an
> interdependency with KVM.
>
> I'm happy to queue that immediately, as it's purely structural and
> shouldn't have a functional impact anywhere. That will also shrink the
> series a bit, and we can rebase the following patches atop of that.
Thanks for your suggestion, I have finished this improvement.
It will be in v20.
https://git.linaro.org/people/fu.wei/linux.git/log/?h=topic-gtdt-wakeup-timer_upstream_v20_devel
>
>> 5. Rework PPI determination;
>> 6. Rework counter frequency detection;
>> 7. Refactor arch_timer_needs_probing, move it into DT init call
>> 8. Introduce some new structs and refactor the MMIO timer init code
>> for reusing some common code.
>
> I'll review these in separate replies.
>
> Thanks,
> Mark.
--
Best regards,
Fu Wei
Software Engineer
Red Hat
^ permalink raw reply
* [PATCH v3] Add some DT nodes for Mediatek MT2701
From: Erin Lo @ 2017-01-17 9:24 UTC (permalink / raw)
To: linux-arm-kernel
This patch series based on v4.10-rc2, include MT2701 spi/nand/auxadc/thermal controller DT nodes.
Dependent on "Add clock and power domain DT nodes for Mediatek MT2701"[1].
Change in v3:
1. Since some patches in v2 have been applied to v4.10-next/dts32, they were not included in v3 series.
2. Remove iommu DT nodes since it will be sent with its driver patch series later.
3. Remove ethernet DT nodes since it will be sent with its driver patch series later.
4. Modify thermal resets pin define from hard code to name.
Change in v2:
1. Add spi/auxadc pin setting
2. Add ethernet node and pin setting
3. Add thermal controller node
[1] http://lists.infradead.org/pipermail/linux-mediatek/2016-December/007637.html
Dawei Chien (1):
arm: dts: mt2701: Add thermal device node.
arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
--
1.9.1
^ permalink raw reply
* [PATCH v3] arm: dts: mt2701: Add thermal device node.
From: Erin Lo @ 2017-01-17 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484645049-4477-1-git-send-email-erin.lo@mediatek.com>
From: Dawei Chien <dawei.chien@mediatek.com>
Add thermal controller device nodes for MT2701.
Signed-off-by: Dawei Chien <dawei.chien@mediatek.com>
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 43 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 4cfec57..26a88cb 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -89,6 +89,36 @@
clock-output-names = "rtc32k";
};
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <1000>; /* milliseconds */
+ polling-delay = <1000>; /* milliseconds */
+
+ thermal-sensors = <&thermal 0>;
+ sustainable-power = <1000>;
+
+ trips {
+ threshold: trip-point at 0 {
+ temperature = <68000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ target: trip-point at 1 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit: cpu_crit at 0 {
+ temperature = <115000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupt-parent = <&gic>;
@@ -270,6 +300,19 @@
status = "disabled";
};
+ thermal: thermal at 1100b000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "mediatek,mt2701-thermal";
+ reg = <0 0x1100b000 0 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
+ clock-names = "therm", "auxadc";
+ resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
+ reset-names = "therm";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ };
+
nandc: nfi at 1100d000 {
compatible = "mediatek,mt2701-nfc";
reg = <0 0x1100d000 0 0x1000>;
--
1.9.1
^ permalink raw reply related
* [PATCH v7 07/15] irqchip: gicv3-its: platform-msi: scan MADT to create platform msi domain
From: Matthias Brugger @ 2017-01-17 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484147199-4267-8-git-send-email-hanjun.guo@linaro.org>
On 11/01/17 16:06, Hanjun Guo wrote:
> With the introduction of its_pmsi_init_one(), we can add some code
> on top for ACPI support of platform MSI.
>
> We are scanning the MADT table to get the ITS entry(ies), then use
> the information to create the platform msi domain for devices connect
> to it, just like the PCI MSI for ITS did.
>
> Signed-off-by: Hanjun Guo <hanjun.guo@linaro.org>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Sinan Kaya <okaya@codeaurora.org>
> Cc: Tomasz Nowicki <tn@semihalf.com>
> Cc: Thomas Gleixner <tglx@linutronix.de>
> ---
> drivers/irqchip/irq-gic-v3-its-platform-msi.c | 36 +++++++++++++++++++++++++++
> 1 file changed, 36 insertions(+)
>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
> diff --git a/drivers/irqchip/irq-gic-v3-its-platform-msi.c b/drivers/irqchip/irq-gic-v3-its-platform-msi.c
> index 3d9efd1..ebe933e 100644
> --- a/drivers/irqchip/irq-gic-v3-its-platform-msi.c
> +++ b/drivers/irqchip/irq-gic-v3-its-platform-msi.c
> @@ -103,6 +103,41 @@ static int __init its_pmsi_init_one(struct fwnode_handle *fwnode,
> return 0;
> }
>
> +#ifdef CONFIG_ACPI
> +static int __init
> +its_pmsi_parse_madt(struct acpi_subtable_header *header,
> + const unsigned long end)
> +{
> + struct acpi_madt_generic_translator *its_entry;
> + struct fwnode_handle *domain_handle;
> + const char *node_name;
> + int err = -ENXIO;
> +
> + its_entry = (struct acpi_madt_generic_translator *)header;
> + node_name = kasprintf(GFP_KERNEL, "ITS at 0x%lx",
> + (long)its_entry->base_address);
> + domain_handle = iort_find_domain_token(its_entry->translation_id);
> + if (!domain_handle) {
> + pr_err("%s: Unable to locate ITS domain handle\n", node_name);
> + goto out;
> + }
> +
> + err = its_pmsi_init_one(domain_handle, node_name);
> +
> +out:
> + kfree(node_name);
> + return err;
> +}
> +
> +static void __init its_pmsi_acpi_init(void)
> +{
> + acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
> + its_pmsi_parse_madt, 0);
> +}
> +#else
> +static inline void its_pmsi_acpi_init(void) { }
> +#endif
> +
> static void __init its_pmsi_of_init(void)
> {
> struct device_node *np;
> @@ -119,6 +154,7 @@ static void __init its_pmsi_of_init(void)
> static int __init its_pmsi_init(void)
> {
> its_pmsi_of_init();
> + its_pmsi_acpi_init();
> return 0;
> }
> early_initcall(its_pmsi_init);
>
^ permalink raw reply
* [PATCH] tcb_clksrc: Use 32 bit tcb as sched_clock
From: David Engraf @ 2017-01-17 9:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e9fa8375-70e9-e621-954e-48c3190171ad@linaro.org>
Am 17.01.2017 um 10:13 schrieb Daniel Lezcano:
> On 11/01/2017 14:50, David Engraf wrote:
>> On newer boards the TC can be read as single 32 bit value without locking.
>> Thus the clock can be used as reference for sched_clock which is much more
>> accurate than the jiffies implementation.
>>
>> Tested on a Atmel SAMA5D2 board.
>
> Is this change backward compatible ?
The way how the driver reads the clock hasn't been changed. I've only
introduced the call to sched_clock_register() which will use this clock
for the scheduler as long as no better clock is already used. So I don't
see a backward compatibility problem.
Best regards
- David
>
>> Signed-off-by: David Engraf <david.engraf@sysgo.com>
>> ---
>> drivers/clocksource/tcb_clksrc.c | 16 +++++++++++++++-
>> 1 file changed, 15 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/clocksource/tcb_clksrc.c b/drivers/clocksource/tcb_clksrc.c
>> index d4ca996..745844e 100644
>> --- a/drivers/clocksource/tcb_clksrc.c
>> +++ b/drivers/clocksource/tcb_clksrc.c
>> @@ -10,6 +10,7 @@
>> #include <linux/io.h>
>> #include <linux/platform_device.h>
>> #include <linux/atmel_tc.h>
>> +#include <linux/sched_clock.h>
>>
>>
>> /*
>> @@ -56,11 +57,16 @@ static u64 tc_get_cycles(struct clocksource *cs)
>> return (upper << 16) | lower;
>> }
>>
>> -static u64 tc_get_cycles32(struct clocksource *cs)
>> +static u32 tc_get_cv32(void)
>> {
>> return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));
>> }
>>
>> +static u64 tc_get_cycles32(struct clocksource *cs)
>> +{
>> + return tc_get_cv32();
>> +}
>> +
>> static struct clocksource clksrc = {
>> .name = "tcb_clksrc",
>> .rating = 200,
>> @@ -69,6 +75,11 @@ static struct clocksource clksrc = {
>> .flags = CLOCK_SOURCE_IS_CONTINUOUS,
>> };
>>
>> +static u64 notrace tc_read_sched_clock(void)
>> +{
>> + return tc_get_cv32();
>> +}
>> +
>> #ifdef CONFIG_GENERIC_CLOCKEVENTS
>>
>> struct tc_clkevt_device {
>> @@ -339,6 +350,9 @@ static int __init tcb_clksrc_init(void)
>> clksrc.read = tc_get_cycles32;
>> /* setup ony channel 0 */
>> tcb_setup_single_chan(tc, best_divisor_idx);
>> +
>> + /* register sched_clock on chips with single 32 bit counter */
>> + sched_clock_register(tc_read_sched_clock, 32, divided_rate);
>> } else {
>> /* tclib will give us three clocks no matter what the
>> * underlying platform supports.
>>
>
>
^ permalink raw reply
* [PATCH v2 11/11] drm/rockchip/dsi: fix insufficient bandwidth of some panel
From: Chris Zhong @ 2017-01-17 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170116124453.2154def9.john@metanate.com>
Hi John
On 01/16/2017 08:44 PM, John Keeping wrote:
> On Mon, 16 Jan 2017 18:08:31 +0800, Chris Zhong wrote:
>
>> Set the lanes bps to 1 / 0.9 times of pclk, the margin is not enough
>> for some panel, it will cause the screen display is not normal, so
>> increases the badnwidth to 1 / 0.8.
>>
>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
>>
>> ---
>>
>> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 4 ++--
>> 1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>> index 9dfa73d..5a973fe 100644
>> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
>> @@ -501,8 +501,8 @@ static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi)
>>
>> mpclk = DIV_ROUND_UP(dsi->mode->clock, MSEC_PER_SEC);
>> if (mpclk) {
>> - /* take 1 / 0.9, since mbps must big than bandwidth of RGB */
>> - tmp = mpclk * (bpp / dsi->lanes) * 10 / 9;
>> + /* take 1 / 0.8, since mbps must big than bandwidth of RGB */
>> + tmp = mpclk * (bpp / dsi->lanes) * 10 / 8;
> This and patch 9 are just hacking around the underlying problem in order
> to make particular panels work. I'm pretty sure the actual issue is the
> use of hardcoded values when configuring the PHY, since the PHY
> parameters are specified in clock cycles but the MIPI spec requires
> absolute time durations.
>
> I posted a series addressing this a while ago, although I screwed up
> sending it so some patches were included twice and since no one
> expressed any interest I didn't post a cleaned up version.
>
> The relevant patch is here:
>
> https://patchwork.kernel.org/patch/9340193/
Thanks very much, your patches are very useful for me. It looks your
method is correct.
And I am very confused why Mark Yao and me did not receive your patches
before,
although we have subscribed the <linux-rockchip@lists.infradead.org>.
In addition, could you tell me which device ware you testing with these
mipi patches.
I going to test them these day.
Chris Zhong
>> if (tmp < max_mbps)
>> target_mbps = tmp;
>> else
>
>
^ permalink raw reply
* [05/26] drm/rockchip: dw-mipi-dsi: fix command header writes
From: Chris Zhong @ 2017-01-17 9:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20160919171747.28512-6-john@metanate.com>
same as https://patchwork.kernel.org/patch/9518417/
Tested-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Chris Zhong <zyw@rock-chips.com>
On 09/20/2016 01:17 AM, John Keeping wrote:
> In a couple of places here we use "val" for the value that is about to
> be written to a register but then reuse the same variable for the value
> of a status register before we get around to writing it. Rename the
> value to be written to so that we write the value we intend to and not
> what we have just read from the status register.
>
> Signed-off-by: John Keeping <john@metanate.com>
> ---
> drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 10 ++++++----
> 1 file changed, 6 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> index fac2429b9d6d..03915bf9c97d 100644
> --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c
> @@ -543,9 +543,10 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host,
> return 0;
> }
>
> -static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
> +static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
> {
> int ret;
> + u32 val;
>
> ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
> val, !(val & GEN_CMD_FULL), 1000,
> @@ -555,7 +556,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 val)
> return ret;
> }
>
> - dsi_write(dsi, DSI_GEN_HDR, val);
> + dsi_write(dsi, DSI_GEN_HDR, hdr_val);
>
> ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS,
> val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY),
> @@ -588,8 +589,9 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
> {
> const u32 *tx_buf = msg->tx_buf;
> int len = msg->tx_len, pld_data_bytes = sizeof(*tx_buf), ret;
> - u32 val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
> + u32 hdr_val = GEN_HDATA(msg->tx_len) | GEN_HTYPE(msg->type);
> u32 remainder = 0;
> + u32 val;
>
> if (msg->tx_len < 3) {
> dev_err(dsi->dev, "wrong tx buf length %zu for long write\n",
> @@ -618,7 +620,7 @@ static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi,
> }
> }
>
> - return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val);
> + return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val);
> }
>
> static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
^ permalink raw reply
* [PATCH v3 0/9] irqchip/ls-scfg-msi: Update MSI driver
From: Minghuan Lian @ 2017-01-17 9:32 UTC (permalink / raw)
To: linux-arm-kernel
This patch set is to update Layerscape MSI driver.
1. fix the compatible strings typo
2. Add MSI support to LS1046a
3. Add MSI support to LS1043a v1.1
4. Add MSI affinity support
Minghuan Lian (9):
irqchip/ls-scfg-msi: fix typo of MSI compatible strings
arm: dts: ls1021a: fix typo of MSI compatible string
arm64: dts: ls1043a: fix typo of MSI compatible string
arm: dts: ls1021a: share all MSIs
arm64: dts: ls1043a: share all MSIs
arm64: dts: ls1046a: add MSI dts node
irqchip/ls-scfg-msi: add LS1046a MSI support
irqchip/ls-scfg-msi: add LS1043a v1.1 MSI support
irqchip/ls-scfg-msi: add MSI affinity support
.../interrupt-controller/fsl,ls-scfg-msi.txt | 8 +-
arch/arm/boot/dts/ls1021a.dtsi | 8 +-
arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 12 +-
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 31 +++
drivers/irqchip/irq-ls-scfg-msi.c | 256 ++++++++++++++++++---
5 files changed, 268 insertions(+), 47 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH v3 1/9] irqchip/ls-scfg-msi: fix typo of MSI compatible strings
From: Minghuan Lian @ 2017-01-17 9:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1484645563-29877-1-git-send-email-Minghuan.Lian@nxp.com>
The patch is to fix typo of the Layerscape SCFG MSI dts compatible
strings. "1" is replaced by "l".
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
---
v3-v1:
- None
.../devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt | 6 +++---
drivers/irqchip/irq-ls-scfg-msi.c | 6 ++++--
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
index 9e38949..2755cd1 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
@@ -4,8 +4,8 @@ Required properties:
- compatible: should be "fsl,<soc-name>-msi" to identify
Layerscape PCIe MSI controller block such as:
- "fsl,1s1021a-msi"
- "fsl,1s1043a-msi"
+ "fsl,ls1021a-msi"
+ "fsl,ls1043a-msi"
- msi-controller: indicates that this is a PCIe MSI controller node
- reg: physical base address of the controller and length of memory mapped.
- interrupts: an interrupt to the parent interrupt controller.
@@ -23,7 +23,7 @@ MSI controller node
Examples:
msi1: msi-controller at 1571000 {
- compatible = "fsl,1s1043a-msi";
+ compatible = "fsl,ls1043a-msi";
reg = <0x0 0x1571000 0x0 0x8>,
msi-controller;
interrupts = <0 116 0x4>;
diff --git a/drivers/irqchip/irq-ls-scfg-msi.c b/drivers/irqchip/irq-ls-scfg-msi.c
index 02cca74c..cef67cc 100644
--- a/drivers/irqchip/irq-ls-scfg-msi.c
+++ b/drivers/irqchip/irq-ls-scfg-msi.c
@@ -219,8 +219,10 @@ static int ls_scfg_msi_remove(struct platform_device *pdev)
}
static const struct of_device_id ls_scfg_msi_id[] = {
- { .compatible = "fsl,1s1021a-msi", },
- { .compatible = "fsl,1s1043a-msi", },
+ { .compatible = "fsl,1s1021a-msi", }, /* a typo */
+ { .compatible = "fsl,1s1043a-msi", }, /* a typo */
+ { .compatible = "fsl,ls1021a-msi", },
+ { .compatible = "fsl,ls1043a-msi", },
{},
};
--
1.9.1
^ permalink raw reply related
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