* [PATCH v5 15/22] KVM: arm64: vgic-its: vgic_its_alloc_ite/device
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
Add two new helpers to allocate an its ite and an its device.
This will avoid duplication on restore path.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
v4 -> v5:
- add Marc's A-b
v3 -> v4:
- fix allocation
- add comment about its_lock mutex hold
v1 -> v2:
- report itt_size fix and remove ITE_SIZE
- s/itte/ite/g
---
virt/kvm/arm/vgic/vgic-its.c | 73 ++++++++++++++++++++++++++++++--------------
1 file changed, 50 insertions(+), 23 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 55267ab..56c5123 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -742,6 +742,27 @@ static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
kfree(collection);
}
+/* Must be called with its_lock mutex held */
+static int vgic_its_alloc_ite(struct its_device *device,
+ struct its_ite **itep,
+ struct its_collection *collection,
+ u32 lpi_id, u32 event_id)
+{
+ struct its_ite *ite;
+
+ ite = kzalloc(sizeof(*ite), GFP_KERNEL);
+ if (!ite)
+ return -ENOMEM;
+
+ ite->event_id = event_id;
+ ite->collection = collection;
+ ite->lpi = lpi_id;
+
+ list_add_tail(&ite->ite_list, &device->itt_head);
+ *itep = ite;
+ return 0;
+}
+
/*
* The MAPTI and MAPI commands map LPIs to ITTEs.
* Must be called with its_lock mutex held.
@@ -755,7 +776,7 @@ static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
struct its_ite *ite;
struct its_device *device;
struct its_collection *collection, *new_coll = NULL;
- int lpi_nr;
+ int lpi_nr, ret;
struct vgic_irq *irq;
device = find_its_device(its, device_id);
@@ -785,19 +806,13 @@ static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
new_coll = collection;
}
- ite = kzalloc(sizeof(struct its_ite), GFP_KERNEL);
- if (!ite) {
+ ret = vgic_its_alloc_ite(device, &ite, collection, lpi_nr, event_id);
+ if (ret) {
if (new_coll)
vgic_its_free_collection(its, coll_id);
- return -ENOMEM;
+ return ret;
}
- ite->event_id = event_id;
- list_add_tail(&ite->ite_list, &device->itt_head);
-
- ite->collection = collection;
- ite->lpi = lpi_nr;
-
irq = vgic_add_lpi(kvm, lpi_nr);
if (IS_ERR(irq)) {
if (new_coll)
@@ -836,6 +851,29 @@ static void vgic_its_unmap_device(struct kvm *kvm, struct its_device *device)
kfree(device);
}
+/* Must be called with its_lock mutex held */
+static int vgic_its_alloc_device(struct vgic_its *its,
+ struct its_device **devp,
+ u32 device_id, gpa_t itt_addr,
+ u8 nb_eventid_bits)
+{
+ struct its_device *device;
+
+ device = kzalloc(sizeof(*device), GFP_KERNEL);
+ if (!device)
+ return -ENOMEM;
+
+ device->device_id = device_id;
+ device->itt_addr = itt_addr;
+ device->nb_eventid_bits = nb_eventid_bits;
+ INIT_LIST_HEAD(&device->itt_head);
+
+ list_add_tail(&device->dev_list, &its->device_list);
+ *devp = device;
+
+ return 0;
+}
+
/*
* MAPD maps or unmaps a device ID to Interrupt Translation Tables (ITTs).
* Must be called with the its_lock mutex held.
@@ -872,19 +910,8 @@ static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
if (!valid)
return 0;
- device = kzalloc(sizeof(struct its_device), GFP_KERNEL);
- if (!device)
- return -ENOMEM;
-
- device->device_id = device_id;
- device->nb_eventid_bits = nb_eventid_bits;
- device->itt_addr = itt_addr;
-
- INIT_LIST_HEAD(&device->itt_head);
-
- list_add_tail(&device->dev_list, &its->device_list);
-
- return 0;
+ return vgic_its_alloc_device(its, &device, device_id,
+ itt_addr, nb_eventid_bits);
}
/*
--
2.5.5
^ permalink raw reply related
* [PATCH v5 14/22] KVM: arm64: vgic-its: KVM_DEV_ARM_ITS_SAVE/RESTORE_TABLES
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
Introduce new attributes in KVM_DEV_ARM_VGIC_GRP_CTRL group:
- KVM_DEV_ARM_ITS_SAVE_TABLES: saves the ITS tables into guest RAM
- KVM_DEV_ARM_ITS_RESTORE_TABLES: restores them into VGIC internal
structures.
We hold the vcpus lock during the save and restore to make
sure no vcpu is running.
At this stage the functionality is not yet implemented. Only
the skeleton is put in place.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- use KVM_DEV_ARM_ITS_SAVE_TABLES and KVM_DEV_ARM_ITS_RESTORE_TABLES
- rename *flush* into *save*
- call its_sync_lpi_pending_table at the end of restore
- use abi framework
v3 -> v4:
- pass kvm struct handle to vgic_its_flush/restore_pending_tables
- take the kvm lock and vcpu locks
- ABI revision check
- check attr->attr is null
v1 -> v2:
- remove useless kvm parameter
---
arch/arm/include/uapi/asm/kvm.h | 4 +-
arch/arm64/include/uapi/asm/kvm.h | 4 +-
virt/kvm/arm/vgic/vgic-its.c | 108 ++++++++++++++++++++++++++++++++++++--
3 files changed, 110 insertions(+), 6 deletions(-)
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index 4beb83b..8e6563c 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -199,7 +199,9 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
#define VGIC_LEVEL_INFO_LINE_LEVEL 0
-#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
+#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
/* KVM_IRQ_LINE irq field index values */
#define KVM_ARM_IRQ_TYPE_SHIFT 24
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index 7e8dd69..1e35115 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -219,7 +219,9 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
#define VGIC_LEVEL_INFO_LINE_LEVEL 0
-#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+#define KVM_DEV_ARM_VGIC_CTRL_INIT 0
+#define KVM_DEV_ARM_ITS_SAVE_TABLES 1
+#define KVM_DEV_ARM_ITS_RESTORE_TABLES 2
/* Device Control API on vcpu fd */
#define KVM_ARM_VCPU_PMU_V3_CTRL 0
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index de1ed6d..55267ab 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -1648,12 +1648,68 @@ int vgic_its_attr_regs_access(struct kvm_device *dev,
}
/**
+ * vgic_its_save_device_tables - Save the device table and all ITT
+ * into guest RAM
+ */
+static int vgic_its_save_device_tables(struct vgic_its *its)
+{
+ return -ENXIO;
+}
+
+/**
+ * vgic_its_restore_device_tables - Restore the device table and all ITT
+ * from guest RAM to internal data structs
+ */
+static int vgic_its_restore_device_tables(struct vgic_its *its)
+{
+ return -ENXIO;
+}
+
+/**
+ * vgic_its_save_collection_table - Save the collection table into
+ * guest RAM
+ */
+static int vgic_its_save_collection_table(struct vgic_its *its)
+{
+ return -ENXIO;
+}
+
+/**
+ * vgic_its_restore_collection_table - reads the collection table
+ * in guest memory and restores the ITS internal state. Requires the
+ * BASER registers to be restored before.
+ */
+static int vgic_its_restore_collection_table(struct vgic_its *its)
+{
+ return -ENXIO;
+}
+
+/**
* vgic_its_save_tables_v0 - Save the ITS tables into guest ARM
* according to v0 ABI
*/
static int vgic_its_save_tables_v0(struct vgic_its *its)
{
- return -ENXIO;
+ struct kvm *kvm = its->dev->kvm;
+ int ret;
+
+ mutex_lock(&kvm->lock);
+
+ if (!lock_all_vcpus(kvm)) {
+ mutex_unlock(&kvm->lock);
+ return -EBUSY;
+ }
+
+ ret = vgic_its_save_device_tables(its);
+ if (ret)
+ goto out;
+
+ ret = vgic_its_save_collection_table(its);
+
+out:
+ unlock_all_vcpus(kvm);
+ mutex_unlock(&kvm->lock);
+ return ret;
}
/**
@@ -1663,7 +1719,41 @@ static int vgic_its_save_tables_v0(struct vgic_its *its)
*/
static int vgic_its_restore_tables_v0(struct vgic_its *its)
{
- return -ENXIO;
+ struct kvm *kvm = its->dev->kvm;
+ struct kvm_vcpu *vcpu;
+ int ret, c;
+
+ mutex_lock(&kvm->lock);
+
+ if (!lock_all_vcpus(kvm)) {
+ mutex_unlock(&kvm->lock);
+ return -EBUSY;
+ }
+
+ ret = vgic_its_restore_collection_table(its);
+ if (ret)
+ goto out;
+
+ ret = vgic_its_restore_device_tables(its);
+
+ kvm_for_each_vcpu(c, vcpu, kvm) {
+ ret = its_sync_lpi_pending_table(vcpu);
+ if (ret)
+ break;
+ }
+
+out:
+ unlock_all_vcpus(kvm);
+ mutex_unlock(&kvm->lock);
+
+ if (ret)
+ return ret;
+
+ /*
+ * On restore path, MSI injections can happen before the
+ * first VCPU run so let's complete the GIC init here.
+ */
+ return kvm_vgic_map_resources(its->dev->kvm);
}
static int vgic_its_commit_v0(struct vgic_its *its)
@@ -1718,6 +1808,10 @@ static int vgic_its_has_attr(struct kvm_device *dev,
switch (attr->attr) {
case KVM_DEV_ARM_VGIC_CTRL_INIT:
return 0;
+ case KVM_DEV_ARM_ITS_SAVE_TABLES:
+ return 0;
+ case KVM_DEV_ARM_ITS_RESTORE_TABLES:
+ return 0;
}
break;
case KVM_DEV_ARM_VGIC_GRP_ITS_REGS:
@@ -1753,14 +1847,20 @@ static int vgic_its_set_attr(struct kvm_device *dev,
return 0;
}
- case KVM_DEV_ARM_VGIC_GRP_CTRL:
+ case KVM_DEV_ARM_VGIC_GRP_CTRL: {
+ const struct vgic_its_abi *abi = vgic_its_get_abi(its);
+
switch (attr->attr) {
case KVM_DEV_ARM_VGIC_CTRL_INIT:
its->initialized = true;
return 0;
+ case KVM_DEV_ARM_ITS_SAVE_TABLES:
+ return abi->save_tables(its);
+ case KVM_DEV_ARM_ITS_RESTORE_TABLES:
+ return abi->restore_tables(its);
}
- break;
+ }
case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
u64 __user *uaddr = (u64 __user *)(long)attr->addr;
u64 reg;
--
2.5.5
^ permalink raw reply related
* [PATCH v5 13/22] KVM: arm64: vgic-its: Check the device id matches TYPER DEVBITS range
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
On MAPD we currently check the device id can be stored in the device table.
Let's first check it can be encoded within the range defined by TYPER
DEVBITS.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- use GIC_ENCODE_SZ macro
v3 -> v4:
- VITS_TYPER_DEVBITS set to 16 for homogeneity
- use BIT_ULL
---
virt/kvm/arm/vgic/vgic-its.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 757598d..de1ed6d 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -194,6 +194,7 @@ static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
#define GIC_LPI_OFFSET 8192
#define VITS_TYPER_IDBITS 16
+#define VITS_TYPER_DEVBITS 16
/*
* Finds and returns a collection in the ITS collection table.
@@ -394,7 +395,7 @@ static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
* To avoid memory waste in the guest, we keep the number of IDBits and
* DevBits low - as least for the time being.
*/
- reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
+ reg |= GIC_ENCODE_SZ(VITS_TYPER_DEVBITS, 5) << GITS_TYPER_DEVBITS_SHIFT;
reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
@@ -639,10 +640,10 @@ static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its,
* Check whether an ID can be stored into the corresponding guest table.
* For a direct table this is pretty easy, but gets a bit nasty for
* indirect tables. We check whether the resulting guest physical address
- * is actually valid (covered by a memslot and guest accessbible).
+ * is actually valid (covered by a memslot and guest accessible).
* For this we have to read the respective first level entry.
*/
-static bool vgic_its_check_id(struct vgic_its *its, u64 baser, int id)
+static bool vgic_its_check_id(struct vgic_its *its, u64 baser, u32 id)
{
int l1_tbl_size = GITS_BASER_NR_PAGES(baser) * SZ_64K;
int index;
@@ -650,6 +651,9 @@ static bool vgic_its_check_id(struct vgic_its *its, u64 baser, int id)
gfn_t gfn;
int esz = GITS_BASER_ENTRY_SIZE(baser);
+ if (id >= BIT_ULL(VITS_TYPER_DEVBITS))
+ return false;
+
if (!(baser & GITS_BASER_INDIRECT)) {
phys_addr_t addr;
--
2.5.5
^ permalink raw reply related
* [PATCH v5 12/22] KVM: arm64: vgic-its: Interpret MAPD ITT_addr field
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
Up to now the MAPD ITT_addr had been ignored. We will need it
for save/restore. Let's record it in the its_device struct.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- its_cmd_get_ittaddr macro now returns the actual ITT GPA
v3 -> v4:
- in vgic_its_cmd_handle_mapd, itt_addr directly is shifted
- correct ittaddr bitmask to support 48bit GPA
---
virt/kvm/arm/vgic/vgic-its.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 0f3c8f3..757598d 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -106,6 +106,7 @@ struct its_device {
/* the head for the list of ITTEs */
struct list_head itt_head;
u32 nb_eventid_bits;
+ gpa_t itt_addr;
u32 device_id;
};
@@ -569,6 +570,7 @@ static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
#define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32)
#define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32)
#define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16)
+#define its_cmd_get_ittaddr(cmd) (its_cmd_mask_field(cmd, 2, 8, 47) << 8)
#define its_cmd_get_target_addr(cmd) its_cmd_mask_field(cmd, 2, 16, 32)
#define its_cmd_get_validbit(cmd) its_cmd_mask_field(cmd, 2, 63, 1)
@@ -840,6 +842,7 @@ static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
u32 device_id = its_cmd_get_deviceid(its_cmd);
bool valid = its_cmd_get_validbit(its_cmd);
u8 nb_eventid_bits = its_cmd_get_size(its_cmd);
+ gpa_t itt_addr = its_cmd_get_ittaddr(its_cmd);
struct its_device *device;
if (!vgic_its_check_id(its, its->baser_device_table, device_id))
@@ -871,6 +874,7 @@ static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
device->device_id = device_id;
device->nb_eventid_bits = nb_eventid_bits;
+ device->itt_addr = itt_addr;
INIT_LIST_HEAD(&device->itt_head);
--
2.5.5
^ permalink raw reply related
* [PATCH v5 11/22] KVM: arm64: vgic-its: Interpret MAPD Size field and check related errors
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
Up to now the MAPD's ITT size field has been ignored. It encodes
the number of eventid bit minus 1. It should be used to check
the eventid when a MAPTI command is issued on a device. Let's
store the number of eventid bits in the its_device and do the
check on MAPTI. Also make sure the ITT size field does
not exceed the GITS_TYPER IDBITS field.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- its_cmd_get_size macro now returns the actual number of eventid bits
- use GIC_ENCODE_SZ macro to encode ID_bits
v3 -> v4:
- VITS_TYPER_IDBITS set to 16 to be homogeneous with VITS_ESZ definition
and correct users
- nb_eventid_bits correspond to the actual number of eventid bits
---
include/linux/irqchip/arm-gic-v3.h | 2 ++
virt/kvm/arm/vgic/vgic-its.c | 15 ++++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 54c20bd..0c6798c 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -345,9 +345,11 @@
#define E_ITS_INT_UNMAPPED_INTERRUPT 0x010307
#define E_ITS_CLEAR_UNMAPPED_INTERRUPT 0x010507
#define E_ITS_MAPD_DEVICE_OOR 0x010801
+#define E_ITS_MAPD_ITTSIZE_OOR 0x010802
#define E_ITS_MAPC_PROCNUM_OOR 0x010902
#define E_ITS_MAPC_COLLECTION_OOR 0x010903
#define E_ITS_MAPTI_UNMAPPED_DEVICE 0x010a04
+#define E_ITS_MAPTI_ID_OOR 0x010a05
#define E_ITS_MAPTI_PHYSICALID_OOR 0x010a06
#define E_ITS_INV_UNMAPPED_INTERRUPT 0x010c07
#define E_ITS_INVALL_UNMAPPED_COLLECTION 0x010d09
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 1b5797e..0f3c8f3 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -105,6 +105,7 @@ struct its_device {
/* the head for the list of ITTEs */
struct list_head itt_head;
+ u32 nb_eventid_bits;
u32 device_id;
};
@@ -191,6 +192,8 @@ static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
#define GIC_LPI_OFFSET 8192
+#define VITS_TYPER_IDBITS 16
+
/*
* Finds and returns a collection in the ITS collection table.
* Must be called with the its_lock mutex held.
@@ -391,7 +394,7 @@ static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
* DevBits low - as least for the time being.
*/
reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
- reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
+ reg |= GIC_ENCODE_SZ(VITS_TYPER_IDBITS, 5) << GITS_TYPER_IDBITS_SHIFT;
reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
return extract_bytes(reg, addr & 7, len);
@@ -562,6 +565,7 @@ static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
#define its_cmd_get_command(cmd) its_cmd_mask_field(cmd, 0, 0, 8)
#define its_cmd_get_deviceid(cmd) its_cmd_mask_field(cmd, 0, 32, 32)
+#define its_cmd_get_size(cmd) (its_cmd_mask_field(cmd, 1, 0, 5) + 1)
#define its_cmd_get_id(cmd) its_cmd_mask_field(cmd, 1, 0, 32)
#define its_cmd_get_physical_id(cmd) its_cmd_mask_field(cmd, 1, 32, 32)
#define its_cmd_get_collection(cmd) its_cmd_mask_field(cmd, 2, 0, 16)
@@ -752,6 +756,9 @@ static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
if (!device)
return E_ITS_MAPTI_UNMAPPED_DEVICE;
+ if (event_id >= BIT_ULL(device->nb_eventid_bits))
+ return E_ITS_MAPTI_ID_OOR;
+
if (its_cmd_get_command(its_cmd) == GITS_CMD_MAPTI)
lpi_nr = its_cmd_get_physical_id(its_cmd);
else
@@ -832,11 +839,15 @@ static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
{
u32 device_id = its_cmd_get_deviceid(its_cmd);
bool valid = its_cmd_get_validbit(its_cmd);
+ u8 nb_eventid_bits = its_cmd_get_size(its_cmd);
struct its_device *device;
if (!vgic_its_check_id(its, its->baser_device_table, device_id))
return E_ITS_MAPD_DEVICE_OOR;
+ if (valid && nb_eventid_bits > VITS_TYPER_IDBITS)
+ return E_ITS_MAPD_ITTSIZE_OOR;
+
device = find_its_device(its, device_id);
/*
@@ -859,6 +870,8 @@ static int vgic_its_cmd_handle_mapd(struct kvm *kvm, struct vgic_its *its,
return -ENOMEM;
device->device_id = device_id;
+ device->nb_eventid_bits = nb_eventid_bits;
+
INIT_LIST_HEAD(&device->itt_head);
list_add_tail(&device->dev_list, &its->device_list);
--
2.5.5
^ permalink raw reply related
* [PATCH v5 10/22] KVM: arm64: vgic-its: Implement vgic_mmio_uaccess_write_its_iidr
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
The GITS_IIDR revision field is used to encode the migration ABI
revision. So we need to restore it to check the table layout is
readable by the destination.
By writing the IIDR, userspace thus force the ABI revision to be
used and this msut be less or equal than the max revision KVM supports.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5
- rename user_revision into abi_rev and REV into MAX_ABI_REV
- IIDR reports abi_rev set by userspace if any.
- If value set by userspace exceeds the max supported revision, an
error is reported.
- add some defines
v4: creation
---
include/linux/irqchip/arm-gic-v3.h | 4 ++++
virt/kvm/arm/vgic/vgic-its.c | 23 ++++++++++++++++++++---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 9648bad..54c20bd 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -241,6 +241,10 @@
#define GITS_TYPER_PTA (1UL << 19)
#define GITS_TYPER_HWCOLLCNT_SHIFT 24
+#define GITS_IIDR_REV_SHIFT 12
+#define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
+#define GITS_IIDR_PRODUCTID_SHIFT 24
+
#define GITS_CBASER_VALID (1ULL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT (10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 69ecfe4..1b5797e 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -401,7 +401,23 @@ static unsigned long vgic_mmio_read_its_iidr(struct kvm *kvm,
struct vgic_its *its,
gpa_t addr, unsigned int len)
{
- return (PRODUCT_ID_KVM << 24) | (IMPLEMENTER_ARM << 0);
+ return (PRODUCT_ID_KVM << GITS_IIDR_PRODUCTID_SHIFT) |
+ (its->abi_rev << GITS_IIDR_REV_SHIFT) | IMPLEMENTER_ARM;
+}
+
+static int vgic_mmio_uaccess_write_its_iidr(struct kvm *kvm,
+ struct vgic_its *its,
+ gpa_t addr, unsigned int len,
+ unsigned long val)
+{
+ u64 tmp = 0;
+
+ tmp = update_64bit_reg(tmp, addr & 3, len, val);
+ tmp = GITS_IIDR_REV(tmp);
+
+ if (tmp > MAX_ABI_REV)
+ return -EINVAL;
+ return vgic_its_set_abi(its, tmp);
}
static unsigned long vgic_mmio_read_its_idregs(struct kvm *kvm,
@@ -1382,8 +1398,9 @@ static struct vgic_register_region its_registers[] = {
REGISTER_ITS_DESC(GITS_CTLR,
vgic_mmio_read_its_ctlr, vgic_mmio_write_its_ctlr, 4,
VGIC_ACCESS_32bit),
- REGISTER_ITS_DESC(GITS_IIDR,
- vgic_mmio_read_its_iidr, its_mmio_write_wi, 4,
+ REGISTER_ITS_DESC_UACCESS(GITS_IIDR,
+ vgic_mmio_read_its_iidr, its_mmio_write_wi,
+ vgic_mmio_uaccess_write_its_iidr, 4,
VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_TYPER,
vgic_mmio_read_its_typer, its_mmio_write_wi, 8,
--
2.5.5
^ permalink raw reply related
* [PATCH v5 09/22] KVM: arm64: vgic-its: Introduce migration ABI infrastructure
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
We plan to support different migration ABIs, ie. characterizing
the ITS table layout format in guest RAM. Typically a new ABI will
be needed if vLPIs get supported for nested use case.
So let's introduce an array of supported ABIs (at the moment a single
ABI is supported though). The following characteristics are foreseen
to vary with the ABI: size of table entries, save/restore operation.
By default the MAX_ABI_REV is applied on its creation. In subsequent
patches we will introduce a way for the userspace to change the ABI
in use.
The entry sizes now are set according to the ABI version and not
hardcoded anymore.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v5: creation and squash KVM: arm64: ITS: Report the ITE size in
GITS_TYPER
---
include/kvm/arm_vgic.h | 3 ++
include/linux/irqchip/arm-gic-v3.h | 4 ++
virt/kvm/arm/vgic/vgic-its.c | 82 ++++++++++++++++++++++++++++++++++++--
3 files changed, 85 insertions(+), 4 deletions(-)
diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h
index c0b3d99..285474a 100644
--- a/include/kvm/arm_vgic.h
+++ b/include/kvm/arm_vgic.h
@@ -162,6 +162,9 @@ struct vgic_its {
u32 creadr;
u32 cwriter;
+ /* migration ABI revision in use */
+ u32 abi_rev;
+
/* Protects the device and collection lists */
struct mutex its_lock;
struct list_head device_list;
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index 97cbca1..9648bad 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -132,6 +132,8 @@
#define GIC_BASER_SHAREABILITY(reg, type) \
(GIC_BASER_##type << reg##_SHAREABILITY_SHIFT)
+#define GIC_ENCODE_SZ(n, w) (((unsigned long)(n) - 1) & GENMASK_ULL(((w) - 1), 0))
+
#define GICR_PROPBASER_SHAREABILITY_SHIFT (10)
#define GICR_PROPBASER_INNER_CACHEABILITY_SHIFT (7)
#define GICR_PROPBASER_OUTER_CACHEABILITY_SHIFT (56)
@@ -232,6 +234,7 @@
#define GITS_CTLR_QUIESCENT (1U << 31)
#define GITS_TYPER_PLPIS (1UL << 0)
+#define GITS_TYPER_ITT_ENTRY_SIZE_SHIFT 4
#define GITS_TYPER_IDBITS_SHIFT 8
#define GITS_TYPER_DEVBITS_SHIFT 13
#define GITS_TYPER_DEVBITS(r) ((((r) >> GITS_TYPER_DEVBITS_SHIFT) & 0x1f) + 1)
@@ -290,6 +293,7 @@
#define GITS_BASER_TYPE(r) (((r) >> GITS_BASER_TYPE_SHIFT) & 7)
#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
+#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
#define GITS_BASER_SHAREABILITY_SHIFT (10)
#define GITS_BASER_InnerShareable \
GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 79ed1c2..69ecfe4 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -33,6 +33,12 @@
#include "vgic.h"
#include "vgic-mmio.h"
+/* Highest migration ABI revision supported by this code */
+#define MAX_ABI_REV 0
+
+static int vgic_its_set_abi(struct vgic_its *its, int rev);
+static const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its);
+
/*
* Creates a new (reference to a) struct vgic_irq for a given LPI.
* If this LPI is already mapped on another ITS, we increase its refcount
@@ -123,6 +129,15 @@ struct its_ite {
u32 event_id;
};
+struct vgic_its_abi {
+ int cte_esz;
+ int dte_esz;
+ int ite_esz;
+ int (*save_tables)(struct vgic_its *its);
+ int (*restore_tables)(struct vgic_its *its);
+ int (*commit)(struct vgic_its *its);
+};
+
/*
* Find and returns a device in the device table for an ITS.
* Must be called with the its_lock mutex held.
@@ -364,6 +379,7 @@ static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
struct vgic_its *its,
gpa_t addr, unsigned int len)
{
+ const struct vgic_its_abi *abi = vgic_its_get_abi(its);
u64 reg = GITS_TYPER_PLPIS;
/*
@@ -376,6 +392,7 @@ static unsigned long vgic_mmio_read_its_typer(struct kvm *kvm,
*/
reg |= 0x0f << GITS_TYPER_DEVBITS_SHIFT;
reg |= 0x0f << GITS_TYPER_IDBITS_SHIFT;
+ reg |= GIC_ENCODE_SZ(abi->ite_esz, 4) << GITS_TYPER_ITT_ENTRY_SIZE_SHIFT;
return extract_bytes(reg, addr & 7, len);
}
@@ -1268,6 +1285,7 @@ static void vgic_mmio_write_its_baser(struct kvm *kvm,
gpa_t addr, unsigned int len,
unsigned long val)
{
+ const struct vgic_its_abi *abi = vgic_its_get_abi(its);
u64 entry_size, device_type;
u64 reg, *regptr, clearbits = 0;
@@ -1278,12 +1296,12 @@ static void vgic_mmio_write_its_baser(struct kvm *kvm,
switch (BASER_INDEX(addr)) {
case 0:
regptr = &its->baser_device_table;
- entry_size = 8;
+ entry_size = abi->dte_esz;
device_type = GITS_BASER_TYPE_DEVICE;
break;
case 1:
regptr = &its->baser_coll_table;
- entry_size = 8;
+ entry_size = abi->cte_esz;
device_type = GITS_BASER_TYPE_COLLECTION;
clearbits = GITS_BASER_INDIRECT;
break;
@@ -1425,7 +1443,6 @@ static int vgic_register_its_iodev(struct kvm *kvm, struct vgic_its *its)
(GIC_BASER_CACHEABILITY(GITS_BASER, INNER, RaWb) | \
GIC_BASER_CACHEABILITY(GITS_BASER, OUTER, SameAsInner) | \
GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable) | \
- ((8ULL - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | \
GITS_BASER_PAGE_SIZE_64K)
#define INITIAL_PROPBASER_VALUE \
@@ -1465,7 +1482,7 @@ static int vgic_its_create(struct kvm_device *dev, u32 type)
dev->private = its;
- return 0;
+ return vgic_its_set_abi(its, MAX_ABI_REV);
}
static void vgic_its_destroy(struct kvm_device *kvm_dev)
@@ -1592,6 +1609,63 @@ int vgic_its_attr_regs_access(struct kvm_device *dev,
return ret;
}
+/**
+ * vgic_its_save_tables_v0 - Save the ITS tables into guest ARM
+ * according to v0 ABI
+ */
+static int vgic_its_save_tables_v0(struct vgic_its *its)
+{
+ return -ENXIO;
+}
+
+/**
+ * vgic_its_restore_tables_v0 - Restore the ITS tables from guest RAM
+ * to internal data structs according to V0 ABI
+ *
+ */
+static int vgic_its_restore_tables_v0(struct vgic_its *its)
+{
+ return -ENXIO;
+}
+
+static int vgic_its_commit_v0(struct vgic_its *its)
+{
+ const struct vgic_its_abi *abi;
+
+ abi = vgic_its_get_abi(its);
+ its->baser_coll_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
+ its->baser_device_table &= ~GITS_BASER_ENTRY_SIZE_MASK;
+
+ its->baser_coll_table |= (GIC_ENCODE_SZ(abi->cte_esz, 5)
+ << GITS_BASER_ENTRY_SIZE_SHIFT);
+
+ its->baser_device_table |= (GIC_ENCODE_SZ(abi->dte_esz, 5)
+ << GITS_BASER_ENTRY_SIZE_SHIFT);
+ return 0;
+}
+
+static const struct vgic_its_abi abi[MAX_ABI_REV + 1] = {
+ {.cte_esz = 8, .dte_esz = 8, .ite_esz = 8,
+ .save_tables = vgic_its_save_tables_v0,
+ .restore_tables = vgic_its_restore_tables_v0,
+ . commit = vgic_its_commit_v0,
+ },
+};
+
+inline const struct vgic_its_abi *vgic_its_get_abi(struct vgic_its *its)
+{
+ return &abi[its->abi_rev];
+}
+
+int vgic_its_set_abi(struct vgic_its *its, int rev)
+{
+ const struct vgic_its_abi *abi;
+
+ its->abi_rev = rev;
+ abi = vgic_its_get_abi(its);
+ return abi->commit(its);
+}
+
static int vgic_its_has_attr(struct kvm_device *dev,
struct kvm_device_attr *attr)
{
--
2.5.5
^ permalink raw reply related
* [PATCH v5 08/22] KVM: arm64: vgic-its: Implement vgic_mmio_uaccess_write_its_creadr
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
GITS_CREADR needs to be restored so let's implement the associated
uaccess_write_its callback. The write only is allowed if the its
is disabled.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- keep Stalled bit
- vgic_mmio_uaccess_write_its_creadr can now return an error
v3 -> v4:
- REGISTER_ITS_DESC_UACCESS now introduced in this patch
- we now check the its is disabled
---
virt/kvm/arm/vgic/vgic-its.c | 42 ++++++++++++++++++++++++++++++++++++++++--
1 file changed, 40 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index a9a2c12..79ed1c2 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -1213,6 +1213,33 @@ static unsigned long vgic_mmio_read_its_creadr(struct kvm *kvm,
return extract_bytes(its->creadr, addr & 0x7, len);
}
+static int vgic_mmio_uaccess_write_its_creadr(struct kvm *kvm,
+ struct vgic_its *its,
+ gpa_t addr, unsigned int len,
+ unsigned long val)
+{
+ int ret = 0;
+ u32 reg;
+
+ mutex_lock(&its->cmd_lock);
+
+ if (its->enabled) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ reg = update_64bit_reg(its->creadr, addr & 7, len, val);
+ if (ITS_CMD_OFFSET(reg) >= ITS_CMD_BUFFER_SIZE(its->cbaser)) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ its->creadr = reg;
+out:
+ mutex_unlock(&its->cmd_lock);
+ return ret;
+}
+
#define BASER_INDEX(addr) (((addr) / sizeof(u64)) & 0x7)
static unsigned long vgic_mmio_read_its_baser(struct kvm *kvm,
struct vgic_its *its,
@@ -1317,6 +1344,16 @@ static void vgic_mmio_write_its_ctlr(struct kvm *kvm, struct vgic_its *its,
.its_write = wr, \
}
+#define REGISTER_ITS_DESC_UACCESS(off, rd, wr, uwr, length, acc)\
+{ \
+ .reg_offset = off, \
+ .len = length, \
+ .access_flags = acc, \
+ .its_read = rd, \
+ .its_write = wr, \
+ .uaccess_its_write = uwr, \
+}
+
static void its_mmio_write_wi(struct kvm *kvm, struct vgic_its *its,
gpa_t addr, unsigned int len, unsigned long val)
{
@@ -1339,8 +1376,9 @@ static struct vgic_register_region its_registers[] = {
REGISTER_ITS_DESC(GITS_CWRITER,
vgic_mmio_read_its_cwriter, vgic_mmio_write_its_cwriter, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
- REGISTER_ITS_DESC(GITS_CREADR,
- vgic_mmio_read_its_creadr, its_mmio_write_wi, 8,
+ REGISTER_ITS_DESC_UACCESS(GITS_CREADR,
+ vgic_mmio_read_its_creadr, its_mmio_write_wi,
+ vgic_mmio_uaccess_write_its_creadr, 8,
VGIC_ACCESS_64bit | VGIC_ACCESS_32bit),
REGISTER_ITS_DESC(GITS_BASER,
vgic_mmio_read_its_baser, vgic_mmio_write_its_baser, 0x40,
--
2.5.5
^ permalink raw reply related
* [PATCH v5 07/22] KVM: arm64: vgic-its: Implement vgic_its_has_attr_regs and attr_regs_access
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
This patch implements vgic_its_has_attr_regs and vgic_its_attr_regs_access
upon the MMIO framework. VGIC ITS KVM device KVM_DEV_ARM_VGIC_GRP_ITS_REGS
group becomes functional.
At least GITS_CREADR and GITS_IIDR require to differentiate a guest write
action from a user access. As such let's introduce a new uaccess_its_write
vgic_register_region callback.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- use GITS_TYPER instead of offset 0x8
- uaccess_its_write now can return an error
v3 -> v4:
- remove changes to the REGISTER_ITS_DESC macro. This will be handled in
subsequent patch with the introduction of a new REGISTER_ITS_DESC_UACCESS
macro
- fix IIDR access and add a comment wrt full length access
- handle endianness
- add kvm lock and vcpus lock
---
virt/kvm/arm/vgic/vgic-its.c | 79 +++++++++++++++++++++++++++++++++++++++++--
virt/kvm/arm/vgic/vgic-mmio.h | 9 +++--
2 files changed, 84 insertions(+), 4 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index f687e91..a9a2c12 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -1469,14 +1469,89 @@ static void vgic_its_destroy(struct kvm_device *kvm_dev)
int vgic_its_has_attr_regs(struct kvm_device *dev,
struct kvm_device_attr *attr)
{
- return -ENXIO;
+ const struct vgic_register_region *region;
+ struct vgic_io_device iodev = {
+ .regions = its_registers,
+ .nr_regions = ARRAY_SIZE(its_registers),
+ };
+ gpa_t offset = attr->attr;
+
+ region = vgic_find_mmio_region(iodev.regions,
+ iodev.nr_regions,
+ offset);
+ if (!region)
+ return -ENXIO;
+
+ return 0;
}
int vgic_its_attr_regs_access(struct kvm_device *dev,
struct kvm_device_attr *attr,
u64 *reg, bool is_write)
{
- return -ENXIO;
+ const struct vgic_register_region *region;
+ struct vgic_io_device iodev = {
+ .regions = its_registers,
+ .nr_regions = ARRAY_SIZE(its_registers),
+ };
+ struct vgic_its *its = dev->private;
+ gpa_t addr, offset = attr->attr;
+ unsigned int len;
+ unsigned long data = 0;
+ int ret = 0;
+
+ /*
+ * Among supported registers, only GITS_CTLR (0x0) and GITS_IIDR (0x4)
+ * are 32 bits. Others are 64 bits.
+ */
+ if ((offset < GITS_TYPER && offset & 0x3) ||
+ (offset >= GITS_TYPER && offset & 0x7))
+ return -EINVAL;
+
+ mutex_lock(&dev->kvm->lock);
+
+ if (IS_VGIC_ADDR_UNDEF(its->vgic_its_base)) {
+ ret = -ENXIO;
+ goto out;
+ }
+
+ region = vgic_find_mmio_region(iodev.regions,
+ iodev.nr_regions,
+ offset);
+ if (!region) {
+ ret = -ENXIO;
+ goto out;
+ }
+
+ if (!lock_all_vcpus(dev->kvm)) {
+ ret = -EBUSY;
+ goto out;
+ }
+
+ addr = its->vgic_its_base + offset;
+
+ /*
+ * Only full length register accesses are supported although
+ * the architecture spec theoretically allows upper/lower 32
+ * bits to be accessed independently
+ */
+ len = region->access_flags & VGIC_ACCESS_64bit ? 8 : 4;
+
+ if (is_write) {
+ data = vgic_data_mmio_bus_to_host(reg, len);
+ if (region->uaccess_its_write)
+ ret = region->uaccess_its_write(dev->kvm, its, addr,
+ len, data);
+ else
+ region->its_write(dev->kvm, its, addr, len, data);
+ } else {
+ data = region->its_read(dev->kvm, its, addr, len);
+ vgic_data_host_to_mmio_bus(reg, len, data);
+ }
+ unlock_all_vcpus(dev->kvm);
+out:
+ mutex_unlock(&dev->kvm->lock);
+ return ret;
}
static int vgic_its_has_attr(struct kvm_device *dev,
diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
index 6eec91b..ea4171a 100644
--- a/virt/kvm/arm/vgic/vgic-mmio.h
+++ b/virt/kvm/arm/vgic/vgic-mmio.h
@@ -36,8 +36,13 @@ struct vgic_register_region {
};
unsigned long (*uaccess_read)(struct kvm_vcpu *vcpu, gpa_t addr,
unsigned int len);
- void (*uaccess_write)(struct kvm_vcpu *vcpu, gpa_t addr,
- unsigned int len, unsigned long val);
+ union {
+ void (*uaccess_write)(struct kvm_vcpu *vcpu, gpa_t addr,
+ unsigned int len, unsigned long val);
+ int (*uaccess_its_write)(struct kvm *kvm, struct vgic_its *its,
+ gpa_t addr, unsigned int len,
+ unsigned long val);
+ };
};
extern struct kvm_io_device_ops kvm_io_gic_ops;
--
2.5.5
^ permalink raw reply related
* [PATCH v5 06/22] KVM: arm/arm64: vgic: expose (un)lock_all_vcpus
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
We need to use those helpers in vgic-its.c so let's
expose them in the private vgic header.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
v4 -> v5:
- Add Marc's A-b
---
virt/kvm/arm/vgic/vgic-kvm-device.c | 4 ++--
virt/kvm/arm/vgic/vgic.h | 3 +++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-kvm-device.c b/virt/kvm/arm/vgic/vgic-kvm-device.c
index d181d2b..859bfa8 100644
--- a/virt/kvm/arm/vgic/vgic-kvm-device.c
+++ b/virt/kvm/arm/vgic/vgic-kvm-device.c
@@ -259,13 +259,13 @@ static void unlock_vcpus(struct kvm *kvm, int vcpu_lock_idx)
}
}
-static void unlock_all_vcpus(struct kvm *kvm)
+void unlock_all_vcpus(struct kvm *kvm)
{
unlock_vcpus(kvm, atomic_read(&kvm->online_vcpus) - 1);
}
/* Returns true if all vcpus were locked, false otherwise */
-static bool lock_all_vcpus(struct kvm *kvm)
+bool lock_all_vcpus(struct kvm *kvm)
{
struct kvm_vcpu *tmp_vcpu;
int c;
diff --git a/virt/kvm/arm/vgic/vgic.h b/virt/kvm/arm/vgic/vgic.h
index 6cf557e..b87f1c6 100644
--- a/virt/kvm/arm/vgic/vgic.h
+++ b/virt/kvm/arm/vgic/vgic.h
@@ -184,4 +184,7 @@ int vgic_init(struct kvm *kvm);
int vgic_debug_init(struct kvm *kvm);
int vgic_debug_destroy(struct kvm *kvm);
+bool lock_all_vcpus(struct kvm *kvm);
+void unlock_all_vcpus(struct kvm *kvm);
+
#endif
--
2.5.5
^ permalink raw reply related
* [PATCH v5 05/22] KVM: arm64: vgic-its: KVM_DEV_ARM_VGIC_GRP_ITS_REGS group
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
The ITS KVM device exposes a new KVM_DEV_ARM_VGIC_GRP_ITS_REGS
group which allows the userspace to save/restore ITS registers.
At this stage the get/set/has operations are not yet implemented.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
v4 -> v5:
- Add Marc's A-b
v3 -> v4:
- added Andre's R-b
---
arch/arm/include/uapi/asm/kvm.h | 1 +
arch/arm64/include/uapi/asm/kvm.h | 1 +
virt/kvm/arm/vgic/vgic-its.c | 36 +++++++++++++++++++++++++++++++++++-
3 files changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/uapi/asm/kvm.h b/arch/arm/include/uapi/asm/kvm.h
index 6ebd3e6..4beb83b 100644
--- a/arch/arm/include/uapi/asm/kvm.h
+++ b/arch/arm/include/uapi/asm/kvm.h
@@ -192,6 +192,7 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
+#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
diff --git a/arch/arm64/include/uapi/asm/kvm.h b/arch/arm64/include/uapi/asm/kvm.h
index c286035..7e8dd69 100644
--- a/arch/arm64/include/uapi/asm/kvm.h
+++ b/arch/arm64/include/uapi/asm/kvm.h
@@ -212,6 +212,7 @@ struct kvm_arch_memory_slot {
#define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
#define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
#define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO 7
+#define KVM_DEV_ARM_VGIC_GRP_ITS_REGS 8
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT 10
#define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
(0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 3ffcbbe..f687e91 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -1466,6 +1466,19 @@ static void vgic_its_destroy(struct kvm_device *kvm_dev)
kfree(its);
}
+int vgic_its_has_attr_regs(struct kvm_device *dev,
+ struct kvm_device_attr *attr)
+{
+ return -ENXIO;
+}
+
+int vgic_its_attr_regs_access(struct kvm_device *dev,
+ struct kvm_device_attr *attr,
+ u64 *reg, bool is_write)
+{
+ return -ENXIO;
+}
+
static int vgic_its_has_attr(struct kvm_device *dev,
struct kvm_device_attr *attr)
{
@@ -1482,6 +1495,8 @@ static int vgic_its_has_attr(struct kvm_device *dev,
return 0;
}
break;
+ case KVM_DEV_ARM_VGIC_GRP_ITS_REGS:
+ return vgic_its_has_attr_regs(dev, attr);
}
return -ENXIO;
}
@@ -1521,6 +1536,15 @@ static int vgic_its_set_attr(struct kvm_device *dev,
return 0;
}
break;
+ case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
+ u64 __user *uaddr = (u64 __user *)(long)attr->addr;
+ u64 reg;
+
+ if (get_user(reg, uaddr))
+ return -EFAULT;
+
+ return vgic_its_attr_regs_access(dev, attr, ®, true);
+ }
}
return -ENXIO;
}
@@ -1541,10 +1565,20 @@ static int vgic_its_get_attr(struct kvm_device *dev,
if (copy_to_user(uaddr, &addr, sizeof(addr)))
return -EFAULT;
break;
+ }
+ case KVM_DEV_ARM_VGIC_GRP_ITS_REGS: {
+ u64 __user *uaddr = (u64 __user *)(long)attr->addr;
+ u64 reg;
+ int ret;
+
+ ret = vgic_its_attr_regs_access(dev, attr, ®, false);
+ if (ret)
+ return ret;
+ return put_user(reg, uaddr);
+ }
default:
return -ENXIO;
}
- }
return 0;
}
--
2.5.5
^ permalink raw reply related
* [PATCH v5 04/22] arm/arm64: vgic: turn vgic_find_mmio_region into public
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
We plan to use vgic_find_mmio_region in vgic-its.c so let's
turn it into a public function.
Also let's take the opportunity to rename the region parameter
into regions to emphasize this latter is an array of regions.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
v4 -> v5:
- add Marc's A-b
v3 -> v4:
- rename region parameter into regions
- add Andre's R-b
---
virt/kvm/arm/vgic/vgic-mmio.c | 11 +++++------
virt/kvm/arm/vgic/vgic-mmio.h | 5 +++++
2 files changed, 10 insertions(+), 6 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
index 2a5db13..1c17b2a 100644
--- a/virt/kvm/arm/vgic/vgic-mmio.c
+++ b/virt/kvm/arm/vgic/vgic-mmio.c
@@ -446,13 +446,12 @@ static int match_region(const void *key, const void *elt)
return 0;
}
-/* Find the proper register handler entry given a certain address offset. */
-static const struct vgic_register_region *
-vgic_find_mmio_region(const struct vgic_register_region *region, int nr_regions,
- unsigned int offset)
+const struct vgic_register_region *
+vgic_find_mmio_region(const struct vgic_register_region *regions,
+ int nr_regions, unsigned int offset)
{
- return bsearch((void *)(uintptr_t)offset, region, nr_regions,
- sizeof(region[0]), match_region);
+ return bsearch((void *)(uintptr_t)offset, regions, nr_regions,
+ sizeof(regions[0]), match_region);
}
void vgic_set_vmcr(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr)
diff --git a/virt/kvm/arm/vgic/vgic-mmio.h b/virt/kvm/arm/vgic/vgic-mmio.h
index 98bb566..6eec91b 100644
--- a/virt/kvm/arm/vgic/vgic-mmio.h
+++ b/virt/kvm/arm/vgic/vgic-mmio.h
@@ -192,4 +192,9 @@ u64 vgic_sanitise_shareability(u64 reg);
u64 vgic_sanitise_field(u64 reg, u64 field_mask, int field_shift,
u64 (*sanitise_fn)(u64));
+/* Find the proper register handler entry given a certain address offset */
+const struct vgic_register_region *
+vgic_find_mmio_region(const struct vgic_register_region *regions,
+ int nr_regions, unsigned int offset);
+
#endif
--
2.5.5
^ permalink raw reply related
* [PATCH v5 03/22] KVM: arm/arm64: vgic-its: rename itte into ite
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
The actual abbreviation for the interrupt translation table entry
is ITE. Let's rename all itte instances by ite.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
---
v5: Add Marc's A-b
---
virt/kvm/arm/vgic/vgic-its.c | 148 +++++++++++++++++++++----------------------
1 file changed, 74 insertions(+), 74 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 8d1da1a..3ffcbbe 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -114,8 +114,8 @@ struct its_collection {
#define its_is_collection_mapped(coll) ((coll) && \
((coll)->target_addr != COLLECTION_NOT_MAPPED))
-struct its_itte {
- struct list_head itte_list;
+struct its_ite {
+ struct list_head ite_list;
struct vgic_irq *irq;
struct its_collection *collection;
@@ -143,27 +143,27 @@ static struct its_device *find_its_device(struct vgic_its *its, u32 device_id)
* Device ID/Event ID pair on an ITS.
* Must be called with the its_lock mutex held.
*/
-static struct its_itte *find_itte(struct vgic_its *its, u32 device_id,
+static struct its_ite *find_ite(struct vgic_its *its, u32 device_id,
u32 event_id)
{
struct its_device *device;
- struct its_itte *itte;
+ struct its_ite *ite;
device = find_its_device(its, device_id);
if (device == NULL)
return NULL;
- list_for_each_entry(itte, &device->itt_head, itte_list)
- if (itte->event_id == event_id)
- return itte;
+ list_for_each_entry(ite, &device->itt_head, ite_list)
+ if (ite->event_id == event_id)
+ return ite;
return NULL;
}
/* To be used as an iterator this macro misses the enclosing parentheses */
-#define for_each_lpi_its(dev, itte, its) \
+#define for_each_lpi_its(dev, ite, its) \
list_for_each_entry(dev, &(its)->device_list, dev_list) \
- list_for_each_entry(itte, &(dev)->itt_head, itte_list)
+ list_for_each_entry(ite, &(dev)->itt_head, ite_list)
/*
* We only implement 48 bits of PA at the moment, although the ITS
@@ -270,18 +270,18 @@ static int vgic_copy_lpi_list(struct kvm *kvm, u32 **intid_ptr)
* Needs to be called whenever either the collection for a LPIs has
* changed or the collection itself got retargeted.
*/
-static void update_affinity_itte(struct kvm *kvm, struct its_itte *itte)
+static void update_affinity_ite(struct kvm *kvm, struct its_ite *ite)
{
struct kvm_vcpu *vcpu;
- if (!its_is_collection_mapped(itte->collection))
+ if (!its_is_collection_mapped(ite->collection))
return;
- vcpu = kvm_get_vcpu(kvm, itte->collection->target_addr);
+ vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
- spin_lock(&itte->irq->irq_lock);
- itte->irq->target_vcpu = vcpu;
- spin_unlock(&itte->irq->irq_lock);
+ spin_lock(&ite->irq->irq_lock);
+ ite->irq->target_vcpu = vcpu;
+ spin_unlock(&ite->irq->irq_lock);
}
/*
@@ -292,13 +292,13 @@ static void update_affinity_collection(struct kvm *kvm, struct vgic_its *its,
struct its_collection *coll)
{
struct its_device *device;
- struct its_itte *itte;
+ struct its_ite *ite;
- for_each_lpi_its(device, itte, its) {
- if (!itte->collection || coll != itte->collection)
+ for_each_lpi_its(device, ite, its) {
+ if (!ite->collection || coll != ite->collection)
continue;
- update_affinity_itte(kvm, itte);
+ update_affinity_ite(kvm, ite);
}
}
@@ -425,25 +425,25 @@ static int vgic_its_trigger_msi(struct kvm *kvm, struct vgic_its *its,
u32 devid, u32 eventid)
{
struct kvm_vcpu *vcpu;
- struct its_itte *itte;
+ struct its_ite *ite;
if (!its->enabled)
return -EBUSY;
- itte = find_itte(its, devid, eventid);
- if (!itte || !its_is_collection_mapped(itte->collection))
+ ite = find_ite(its, devid, eventid);
+ if (!ite || !its_is_collection_mapped(ite->collection))
return E_ITS_INT_UNMAPPED_INTERRUPT;
- vcpu = kvm_get_vcpu(kvm, itte->collection->target_addr);
+ vcpu = kvm_get_vcpu(kvm, ite->collection->target_addr);
if (!vcpu)
return E_ITS_INT_UNMAPPED_INTERRUPT;
if (!vcpu->arch.vgic_cpu.lpis_enabled)
return -EBUSY;
- spin_lock(&itte->irq->irq_lock);
- itte->irq->pending_latch = true;
- vgic_queue_irq_unlock(kvm, itte->irq);
+ spin_lock(&ite->irq->irq_lock);
+ ite->irq->pending_latch = true;
+ vgic_queue_irq_unlock(kvm, ite->irq);
return 0;
}
@@ -511,15 +511,15 @@ int vgic_its_inject_msi(struct kvm *kvm, struct kvm_msi *msi)
}
/* Requires the its_lock to be held. */
-static void its_free_itte(struct kvm *kvm, struct its_itte *itte)
+static void its_free_ite(struct kvm *kvm, struct its_ite *ite)
{
- list_del(&itte->itte_list);
+ list_del(&ite->ite_list);
/* This put matches the get in vgic_add_lpi. */
- if (itte->irq)
- vgic_put_irq(kvm, itte->irq);
+ if (ite->irq)
+ vgic_put_irq(kvm, ite->irq);
- kfree(itte);
+ kfree(ite);
}
static u64 its_cmd_mask_field(u64 *its_cmd, int word, int shift, int size)
@@ -544,17 +544,17 @@ static int vgic_its_cmd_handle_discard(struct kvm *kvm, struct vgic_its *its,
{
u32 device_id = its_cmd_get_deviceid(its_cmd);
u32 event_id = its_cmd_get_id(its_cmd);
- struct its_itte *itte;
+ struct its_ite *ite;
- itte = find_itte(its, device_id, event_id);
- if (itte && itte->collection) {
+ ite = find_ite(its, device_id, event_id);
+ if (ite && ite->collection) {
/*
* Though the spec talks about removing the pending state, we
* don't bother here since we clear the ITTE anyway and the
* pending state is a property of the ITTE struct.
*/
- its_free_itte(kvm, itte);
+ its_free_ite(kvm, ite);
return 0;
}
@@ -572,26 +572,26 @@ static int vgic_its_cmd_handle_movi(struct kvm *kvm, struct vgic_its *its,
u32 event_id = its_cmd_get_id(its_cmd);
u32 coll_id = its_cmd_get_collection(its_cmd);
struct kvm_vcpu *vcpu;
- struct its_itte *itte;
+ struct its_ite *ite;
struct its_collection *collection;
- itte = find_itte(its, device_id, event_id);
- if (!itte)
+ ite = find_ite(its, device_id, event_id);
+ if (!ite)
return E_ITS_MOVI_UNMAPPED_INTERRUPT;
- if (!its_is_collection_mapped(itte->collection))
+ if (!its_is_collection_mapped(ite->collection))
return E_ITS_MOVI_UNMAPPED_COLLECTION;
collection = find_collection(its, coll_id);
if (!its_is_collection_mapped(collection))
return E_ITS_MOVI_UNMAPPED_COLLECTION;
- itte->collection = collection;
+ ite->collection = collection;
vcpu = kvm_get_vcpu(kvm, collection->target_addr);
- spin_lock(&itte->irq->irq_lock);
- itte->irq->target_vcpu = vcpu;
- spin_unlock(&itte->irq->irq_lock);
+ spin_lock(&ite->irq->irq_lock);
+ ite->irq->target_vcpu = vcpu;
+ spin_unlock(&ite->irq->irq_lock);
return 0;
}
@@ -679,7 +679,7 @@ static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
{
struct its_collection *collection;
struct its_device *device;
- struct its_itte *itte;
+ struct its_ite *ite;
/*
* Clearing the mapping for that collection ID removes the
@@ -690,10 +690,10 @@ static void vgic_its_free_collection(struct vgic_its *its, u32 coll_id)
if (!collection)
return;
- for_each_lpi_its(device, itte, its)
- if (itte->collection &&
- itte->collection->collection_id == coll_id)
- itte->collection = NULL;
+ for_each_lpi_its(device, ite, its)
+ if (ite->collection &&
+ ite->collection->collection_id == coll_id)
+ ite->collection = NULL;
list_del(&collection->coll_list);
kfree(collection);
@@ -709,7 +709,7 @@ static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
u32 device_id = its_cmd_get_deviceid(its_cmd);
u32 event_id = its_cmd_get_id(its_cmd);
u32 coll_id = its_cmd_get_collection(its_cmd);
- struct its_itte *itte;
+ struct its_ite *ite;
struct its_device *device;
struct its_collection *collection, *new_coll = NULL;
int lpi_nr;
@@ -728,7 +728,7 @@ static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
return E_ITS_MAPTI_PHYSICALID_OOR;
/* If there is an existing mapping, behavior is UNPREDICTABLE. */
- if (find_itte(its, device_id, event_id))
+ if (find_ite(its, device_id, event_id))
return 0;
collection = find_collection(its, coll_id);
@@ -739,36 +739,36 @@ static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
new_coll = collection;
}
- itte = kzalloc(sizeof(struct its_itte), GFP_KERNEL);
- if (!itte) {
+ ite = kzalloc(sizeof(struct its_ite), GFP_KERNEL);
+ if (!ite) {
if (new_coll)
vgic_its_free_collection(its, coll_id);
return -ENOMEM;
}
- itte->event_id = event_id;
- list_add_tail(&itte->itte_list, &device->itt_head);
+ ite->event_id = event_id;
+ list_add_tail(&ite->ite_list, &device->itt_head);
- itte->collection = collection;
- itte->lpi = lpi_nr;
+ ite->collection = collection;
+ ite->lpi = lpi_nr;
irq = vgic_add_lpi(kvm, lpi_nr);
if (IS_ERR(irq)) {
if (new_coll)
vgic_its_free_collection(its, coll_id);
- its_free_itte(kvm, itte);
+ its_free_ite(kvm, ite);
return PTR_ERR(irq);
}
- itte->irq = irq;
+ ite->irq = irq;
- update_affinity_itte(kvm, itte);
+ update_affinity_ite(kvm, ite);
/*
* We "cache" the configuration table entries in out struct vgic_irq's.
* However we only have those structs for mapped IRQs, so we read in
* the respective config data from memory here upon mapping the LPI.
*/
- update_lpi_config(kvm, itte->irq, NULL);
+ update_lpi_config(kvm, ite->irq, NULL);
return 0;
}
@@ -776,15 +776,15 @@ static int vgic_its_cmd_handle_mapi(struct kvm *kvm, struct vgic_its *its,
/* Requires the its_lock to be held. */
static void vgic_its_unmap_device(struct kvm *kvm, struct its_device *device)
{
- struct its_itte *itte, *temp;
+ struct its_ite *ite, *temp;
/*
* The spec says that unmapping a device with still valid
* ITTEs associated is UNPREDICTABLE. We remove all ITTEs,
* since we cannot leave the memory unreferenced.
*/
- list_for_each_entry_safe(itte, temp, &device->itt_head, itte_list)
- its_free_itte(kvm, itte);
+ list_for_each_entry_safe(ite, temp, &device->itt_head, ite_list)
+ its_free_ite(kvm, ite);
list_del(&device->dev_list);
kfree(device);
@@ -883,14 +883,14 @@ static int vgic_its_cmd_handle_clear(struct kvm *kvm, struct vgic_its *its,
{
u32 device_id = its_cmd_get_deviceid(its_cmd);
u32 event_id = its_cmd_get_id(its_cmd);
- struct its_itte *itte;
+ struct its_ite *ite;
- itte = find_itte(its, device_id, event_id);
- if (!itte)
+ ite = find_ite(its, device_id, event_id);
+ if (!ite)
return E_ITS_CLEAR_UNMAPPED_INTERRUPT;
- itte->irq->pending_latch = false;
+ ite->irq->pending_latch = false;
return 0;
}
@@ -904,14 +904,14 @@ static int vgic_its_cmd_handle_inv(struct kvm *kvm, struct vgic_its *its,
{
u32 device_id = its_cmd_get_deviceid(its_cmd);
u32 event_id = its_cmd_get_id(its_cmd);
- struct its_itte *itte;
+ struct its_ite *ite;
- itte = find_itte(its, device_id, event_id);
- if (!itte)
+ ite = find_ite(its, device_id, event_id);
+ if (!ite)
return E_ITS_INV_UNMAPPED_INTERRUPT;
- return update_lpi_config(kvm, itte->irq, NULL);
+ return update_lpi_config(kvm, ite->irq, NULL);
}
/*
@@ -1435,7 +1435,7 @@ static void vgic_its_destroy(struct kvm_device *kvm_dev)
struct kvm *kvm = kvm_dev->kvm;
struct vgic_its *its = kvm_dev->private;
struct its_device *dev;
- struct its_itte *itte;
+ struct its_ite *ite;
struct list_head *dev_cur, *dev_temp;
struct list_head *cur, *temp;
@@ -1450,8 +1450,8 @@ static void vgic_its_destroy(struct kvm_device *kvm_dev)
list_for_each_safe(dev_cur, dev_temp, &its->device_list) {
dev = container_of(dev_cur, struct its_device, dev_list);
list_for_each_safe(cur, temp, &dev->itt_head) {
- itte = (container_of(cur, struct its_itte, itte_list));
- its_free_itte(kvm, itte);
+ ite = (container_of(cur, struct its_ite, ite_list));
+ its_free_ite(kvm, ite);
}
list_del(dev_cur);
kfree(dev);
--
2.5.5
^ permalink raw reply related
* [PATCH v5 02/22] KVM: arm/arm64: Add GICV3 pending table save API documentation
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
Add description for how to save GICV3 LPI pending bit into
guest RAM pending tables.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v5: creation
---
Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt
index c1a2461..9293b45 100644
--- a/Documentation/virtual/kvm/devices/arm-vgic-v3.txt
+++ b/Documentation/virtual/kvm/devices/arm-vgic-v3.txt
@@ -167,11 +167,17 @@ Groups:
KVM_DEV_ARM_VGIC_CTRL_INIT
request the initialization of the VGIC, no additional parameter in
kvm_device_attr.addr.
+ KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
+ save all LPI pending bits into guest RAM pending tables.
+
+ The first kB of the pending table is not altered by this operation.
Errors:
-ENXIO: VGIC not properly configured as required prior to calling
this attribute
-ENODEV: no online VCPU
-ENOMEM: memory shortage when allocating vgic internal data
+ -EFAULT: Invalid guest ram access
+ -EBUSY: One or more VCPUS are running
KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO
--
2.5.5
^ permalink raw reply related
* [PATCH v5 01/22] KVM: arm/arm64: Add ITS save/restore API documentation
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164934-988-1-git-send-email-eric.auger@redhat.com>
Add description for how to access ITS registers and how to save/restore
ITS tables into/from memory.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
v4 -> v5:
- take into account Christoffer's comments
- pending table save on GICV3 side now
v3 -> v4:
- take into account Peter's comments:
- typos
- KVM_DEV_ARM_VGIC_GRP_ITS_TABLES kvm_device_attr = 0
- add a validity bit in DTE
- document all fields in CTE and ITE
- document ABI revision
- take into account Andre's comments:
- document restrictions about GITS_CREADR writing and GITS_IIDR
- document -EBUSY error if one or more VCPUS are runnning
- document 64b registers only can be accessed with 64b access
- itt_addr field matches bits [51:8] of the itt_addr
v1 -> v2:
- DTE and ITE now are 8 bytes
- DTE and ITE now indexed by deviceid/eventid
- use ITE name instead of ITTE
- mentions ITT_addr matches bits [51:8] of the actual address
- mentions LE layout
---
Documentation/virtual/kvm/devices/arm-vgic-its.txt | 99 ++++++++++++++++++++++
1 file changed, 99 insertions(+)
diff --git a/Documentation/virtual/kvm/devices/arm-vgic-its.txt b/Documentation/virtual/kvm/devices/arm-vgic-its.txt
index 6081a5b..b5f010d 100644
--- a/Documentation/virtual/kvm/devices/arm-vgic-its.txt
+++ b/Documentation/virtual/kvm/devices/arm-vgic-its.txt
@@ -32,7 +32,106 @@ Groups:
KVM_DEV_ARM_VGIC_CTRL_INIT
request the initialization of the ITS, no additional parameter in
kvm_device_attr.addr.
+
+ KVM_DEV_ARM_ITS_SAVE_TABLES
+ save the ITS table data into guest RAM, at the location provisioned
+ by the guest in corresponding registers/table entries.
+
+ The layout of the tables in guest memory defines an ABI. The entries
+ are laid out in little endian format as described in the last paragraph.
+
+ KVM_DEV_ARM_ITS_RESTORE_TABLES
+ restore the ITS tables from guest RAM to ITS internal structures.
+
+ The GICV3 must be restored before the ITS and all ITS registers but
+ the GITS_CTLR must be restored before restoring the ITS tables.
+
+ The GITS_IIDR read-only register must also be restored before
+ the table restore as the IIDR revision field encodes the ABI revision.
+
Errors:
-ENXIO: ITS not properly configured as required prior to setting
this attribute
-ENOMEM: Memory shortage when allocating ITS internal data
+ -EINVAL: Inconsistent restored data
+ -EFAULT: Invalid guest ram access
+ -EBUSY: One or more VCPUS are running
+
+ KVM_DEV_ARM_VGIC_GRP_ITS_REGS
+ Attributes:
+ The attr field of kvm_device_attr encodes the offset of the
+ ITS register, relative to the ITS control frame base address
+ (ITS_base).
+
+ kvm_device_attr.addr points to a __u64 value whatever the width
+ of the addressed register (32/64 bits). 64 bit registers can only
+ be accessed with full length.
+
+ Writes to read-only registers are ignored by the kernel except for:
+ - GITS_READR. It needs to be restored otherwise commands in the queue
+ will be re-executed after restoring CWRITER. GITS_READR must be restored
+ before restoring the GITS_CTLR which is likely to enable the ITS.
+ Also it needs to be restored after GITS_CBASER since a write to
+ GITS_CBASER resets GITS_CREADR.
+ - GITS_IIDR. Its Revision field encodes the table layout ABI revision.
+ In the future we might implement direct injection of virtual LPIS.
+ This will require an upgrade of the table layout and an evolution of
+ the ABI. GITS_IIDR must be restored before the table restoration.
+
+ For other registers, getting or setting a register has the same
+ effect as reading/writing the register on real hardware.
+ Errors:
+ -ENXIO: Offset does not correspond to any supported register
+ -EFAULT: Invalid user pointer for attr->addr
+ -EINVAL: Offset is not 64-bit aligned
+ -EBUSY: one or more VCPUS are running
+
+ ITS Table ABI REV0:
+ -------------------
+
+ Revision 0 of the ABI only supports physical LPIs.
+
+ The device table and ITT are indexed by the deviceid and eventid,
+ respectively. The collection table is not indexed by collectionid:
+ CTE are written in the table in the order of collection creation. All
+ entries are 8 bytes.
+
+ Device Table Entry (DTE):
+
+ bits: | 63| 62 ... 49 | 48 ... 5 | 4 ... 0 |
+ values: | V | next | ITT_addr | Size |
+
+ where;
+ - V indicates whether the entry is valid. If not, other fields
+ are not meaningful.
+ - next: equals to 0 if this entry is the last one; otherwise it
+ corresponds to the deviceid offset to the next DTE, capped by
+ 2^14 -1.
+ - ITT_addr matches bits [51:8] of the ITT address (256B aligned).
+ - Size specifies the supported number of bits for the deviceid,
+ minus one
+
+ Collection Table Entry (CTE):
+
+ bits: | 63| 62 .. 52 | 51 ... 16 | 15 ... 0 |
+ values: | V | RES0 | RDBase | ICID |
+
+ where:
+ - V indicates whether the entry is valid. If not, other fields are
+ not meaningful.
+ - RES0: reserved field with Should-Be-Zero-or-Preserved behavior.
+ - RDBase is the PE number (GICR_TYPER.Processor_Number semantic),
+ - ICID is the collection ID
+
+ Interrupt Translation Entry (ITE):
+
+ bits: | 63 ... 48 | 47 ... 16 | 15 ... 0 |
+ values: | next | pINTID | ICID |
+
+ where:
+ - next: equals to 0 if this entry is the last one; otherwise it corresponds
+ to the eventid offset to the next ITE capped by 2^16 -1.
+ - pINTID is the physical LPI ID; if zero, it means the entry is not valid
+ and other fields are not meaningful.
+ - ICID is the collection ID
+
--
2.5.5
^ permalink raw reply related
* [PATCH v5 00/22] vITS save/restore
From: Eric Auger @ 2017-04-14 10:15 UTC (permalink / raw)
To: linux-arm-kernel
This series specifies and implements an API aimed at saving and restoring
the state of the in-kernel emulated ITS device.
The ITS is programmed through registers and tables. Those latter
are allocated by the guest. Their base address is programmed in
registers or table entries before the ITS is enabled.
The ITS is free to use some of them to flush its internal caches. This
is likely to be used when entering low power state.
Therefore, for save/restore use case, it looks natural to use this
guest RAM allocated space to save the table related data. However,
currently, The ITS in-kernel emulated device does not use all of those
tables and for those it uses, it does not always sync them with its
cached data. Additional sync must happen for:
- the collection table
- the device table
- the per-device translation tables
- the LPI pending tables.
The LPI configation table and the command queues do not need extra
syncs.
Best Regards
Eric
Git: complete series available at
https://github.com/eauger/linux/tree/v4.11-rc6-its-mig-v5
* Testing:
- on Cavium ThunderX using a virtio-net-pci guest,
virsh save/restore commands and virt-manager live migration.
Tested with 1 and 2 stage device table.
History:
v4 -> v5:
- user API changes:
- ITS table save/restore triggered through ITS KVM device
KVM_DEV_ARM_VGIC_GRP_CTRL group, KVM_DEV_ARM_ITS_SAVE_TABLES,
KVM_DEV_ARM_ITS_RESTORE_TABLES
- RDIST pending table flush triggered through GICV3 KVM device
KVM_DEV_ARM_VGIC_GRP_CTRL/KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
- Introduce an ABI infrastructure, entry size report using this infra
- IIDR reports ABI chosen set by userspace if any
- pending table save moved to vgic-v3.c
- use optimisation in pending table save
- check target_addr when restore cte
- pending table sync called from restore_tables
- added KVM: arm64: vgic-its: Fix pending table sync
- simplify loopup_table and use kvm_read_guest()
- sort the device and ITE list on save
- add defines for shifts and masks, GIC_ENCODE_SZ macro
v3 -> v4:
- update the DTE format (ITT_addr 52 bit support, validity bit addition)
- Document ABI revision and implement check
- iidr save/restore (including a new patch for iidr user write access)
- changed locking: kvm lock + vcpu lock
- fix nb_eventid_bits mixup
- 2 new patches aiming at exposing next_segment() and lock_all_vcpus()
- rework errror handling of lookup_table functions
- I took into account all Andre's comments/suggestions except:
- trigger the save/restore of pending tables from GICV3 KVM device
instead of ITS KVM device
- implement ITS flush/restore in KVM_DEV_ARM_VGIC_GRP_CTRL
ITS group
See the ML replies for current justifications. In case other people
strongly disagree of course I will change the code.
v2 -> v3:
- fix restore ITS ITT_addr bit masking
v1 -> v2:
- rebased on Vijaya's v11
- all entries now are 8 byte large
- devid/eventid indexing for device table and ITT
- support 2 stage device table
- common infra to read indexed tables
- add cpu <-> le64 conversions
- itte renamed into ite
- do not care anymore about pending table 1st KB
(not needed at the moment for coarse mapping)
RFC v1
- creation
Eric Auger (22):
KVM: arm/arm64: Add ITS save/restore API documentation
KVM: arm/arm64: Add GICV3 pending table save API documentation
KVM: arm/arm64: vgic-its: rename itte into ite
arm/arm64: vgic: turn vgic_find_mmio_region into public
KVM: arm64: vgic-its: KVM_DEV_ARM_VGIC_GRP_ITS_REGS group
KVM: arm/arm64: vgic: expose (un)lock_all_vcpus
KVM: arm64: vgic-its: Implement vgic_its_has_attr_regs and
attr_regs_access
KVM: arm64: vgic-its: Implement vgic_mmio_uaccess_write_its_creadr
KVM: arm64: vgic-its: Introduce migration ABI infrastructure
KVM: arm64: vgic-its: Implement vgic_mmio_uaccess_write_its_iidr
KVM: arm64: vgic-its: Interpret MAPD Size field and check related
errors
KVM: arm64: vgic-its: Interpret MAPD ITT_addr field
KVM: arm64: vgic-its: Check the device id matches TYPER DEVBITS range
KVM: arm64: vgic-its: KVM_DEV_ARM_ITS_SAVE/RESTORE_TABLES
KVM: arm64: vgic-its: vgic_its_alloc_ite/device
KVM: arm64: vgic-its: Add infrastructure for table lookup
KVM: arm64: vgic-its: Collection table save/restore
KVM: arm64: vgic-its: vgic_its_check_id returns the entry's GPA
KVM: arm64: vgic-its: ITT save and restore
KVM: arm64: vgic-its: Device table save/restore
KVM: arm64: vgic-its: Fix pending table sync
KVM: arm64: vgic-v3: KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES
Documentation/virtual/kvm/devices/arm-vgic-its.txt | 99 ++
Documentation/virtual/kvm/devices/arm-vgic-v3.txt | 6 +
arch/arm/include/uapi/asm/kvm.h | 6 +-
arch/arm64/include/uapi/asm/kvm.h | 6 +-
include/kvm/arm_vgic.h | 3 +
include/linux/irqchip/arm-gic-v3.h | 12 +
virt/kvm/arm/vgic/vgic-its.c | 1126 +++++++++++++++++---
virt/kvm/arm/vgic/vgic-kvm-device.c | 24 +-
virt/kvm/arm/vgic/vgic-mmio.c | 11 +-
virt/kvm/arm/vgic/vgic-mmio.h | 14 +-
virt/kvm/arm/vgic/vgic-v3.c | 54 +
virt/kvm/arm/vgic/vgic.h | 24 +
12 files changed, 1251 insertions(+), 134 deletions(-)
--
2.5.5
^ permalink raw reply
* [PATCH v7 9/9] ARM: configs: stm32: Add simple panel support in STM32 defconfig
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This patch adds simple panel support in stm32_defconfig file
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/configs/stm32_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index c2ff2e7..0d38263 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -49,6 +49,8 @@ CONFIG_SERIAL_STM32_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_DRM=y
+CONFIG_DRM_PANEL_SIMPLE=y
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
--
1.9.1
^ permalink raw reply related
* [PATCH v7 8/9] ARM: configs: stm32: Add DRM support in STM32 defconfig
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This patch adds DRM (Direct Rendering Manager) support
in stm32_defconfig file
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index a9d8e3c..c2ff2e7 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -48,6 +48,7 @@ CONFIG_SERIAL_STM32=y
CONFIG_SERIAL_STM32_CONSOLE=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
+CONFIG_DRM=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
--
1.9.1
^ permalink raw reply related
* [PATCH v7 7/9] ARM: dts: stm32: Enable ltdc & simple panel on stm32f429-Eval board
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Enable ltdc & enable am-480272h3tmqw-t01h panel.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 59 ++++++++++++++++++++++++++++++++++++
1 file changed, 59 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 3c99466..631f08a 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -124,6 +124,65 @@
clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
clock-names = "main_clk";
};
+
+ panel_rgb: panel-rgb {
+ compatible = "ampire,am-480272h3tmqw-t01h";
+ status = "okay";
+ port {
+ panel_in_rgb: endpoint {
+ remote-endpoint = <<dc_out_rgb>;
+ };
+ };
+ };
+};
+
+&pinctrl {
+ pinctrl_ltdc: ltdc at 0 {
+ pins {
+ pinmux = <STM32F429_PI12_FUNC_LCD_HSYNC>,
+ <STM32F429_PI13_FUNC_LCD_VSYNC>,
+ <STM32F429_PI14_FUNC_LCD_CLK>,
+ <STM32F429_PI15_FUNC_LCD_R0>,
+ <STM32F429_PJ0_FUNC_LCD_R1>,
+ <STM32F429_PJ1_FUNC_LCD_R2>,
+ <STM32F429_PJ2_FUNC_LCD_R3>,
+ <STM32F429_PJ3_FUNC_LCD_R4>,
+ <STM32F429_PJ4_FUNC_LCD_R5>,
+ <STM32F429_PJ5_FUNC_LCD_R6>,
+ <STM32F429_PJ6_FUNC_LCD_R7>,
+ <STM32F429_PJ7_FUNC_LCD_G0>,
+ <STM32F429_PJ8_FUNC_LCD_G1>,
+ <STM32F429_PJ9_FUNC_LCD_G2>,
+ <STM32F429_PJ10_FUNC_LCD_G3>,
+ <STM32F429_PJ11_FUNC_LCD_G4>,
+ <STM32F429_PJ12_FUNC_LCD_B0>,
+ <STM32F429_PJ13_FUNC_LCD_B1>,
+ <STM32F429_PJ14_FUNC_LCD_B2>,
+ <STM32F429_PJ15_FUNC_LCD_B3>,
+ <STM32F429_PK0_FUNC_LCD_G5>,
+ <STM32F429_PK1_FUNC_LCD_G6>,
+ <STM32F429_PK2_FUNC_LCD_G7>,
+ <STM32F429_PK3_FUNC_LCD_B4>,
+ <STM32F429_PK4_FUNC_LCD_B5>,
+ <STM32F429_PK5_FUNC_LCD_B6>,
+ <STM32F429_PK6_FUNC_LCD_B7>,
+ <STM32F429_PK7_FUNC_LCD_DE>;
+ slew-rate = <2>;
+ };
+ };
+};
+
+<dc {
+ status = "okay";
+ pinctrl-0 = <&pinctrl_ltdc>;
+ pinctrl-names = "default";
+ dma-ranges;
+
+ port {
+ ltdc_out_rgb: endpoint {
+ remote-endpoint = <&panel_in_rgb>;
+ };
+ };
};
&adc {
--
1.9.1
^ permalink raw reply related
* [PATCH v7 6/9] ARM: dts: stm32: Add ltdc support on stm32f429 MCU
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Add LTDC (Lcd-tft Display Controller) support.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 12 +++++++++++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index ee0da97..23debd9 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -543,7 +543,17 @@
reg = <0x40007000 0x400>;
};
- pin-controller {
+ ltdc: display-controller at 40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+ status = "disabled";
+ };
+
+ pinctrl: pin-controller {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,stm32f429-pinctrl";
--
1.9.1
^ permalink raw reply related
* [PATCH v7 5/9] MAINTAINERS: add maintainers for DRM STM driver
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Add Philippe Cornu and myself as maintainers.
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c36dfae..84cf73f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -4424,6 +4424,15 @@ S: Maintained
F: drivers/gpu/drm/sti
F: Documentation/devicetree/bindings/display/st,stih4xx.txt
+DRM DRIVERS FOR STM
+M: Yannick Fertre <yannick.fertre@st.com>
+M: Philippe Cornu <philippe.cornu@st.com>
+L: dri-devel at lists.freedesktop.org
+T: git git://anongit.freedesktop.org/drm/drm-misc
+S: Maintained
+F: drivers/gpu/drm/stm
+F: Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
+
DRM DRIVER FOR TDFX VIDEO CARDS
S: Orphan / Obsolete
F: drivers/gpu/drm/tdfx/
--
1.9.1
^ permalink raw reply related
* [PATCH v7 4/9] drm/stm: Add STM32 LTDC driver
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This controller provides output signals to interface directly a variety
of LCD and TFT panels. These output signals are: RGB signals
(up to 24bpp), vertical & horizontal synchronisations, data enable and
the pixel clock.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
drivers/gpu/drm/Kconfig | 2 +
drivers/gpu/drm/Makefile | 1 +
drivers/gpu/drm/stm/Kconfig | 16 +
drivers/gpu/drm/stm/Makefile | 7 +
drivers/gpu/drm/stm/drv.c | 221 ++++++++
drivers/gpu/drm/stm/ltdc.c | 1161 ++++++++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/stm/ltdc.h | 40 ++
7 files changed, 1448 insertions(+)
create mode 100644 drivers/gpu/drm/stm/Kconfig
create mode 100644 drivers/gpu/drm/stm/Makefile
create mode 100644 drivers/gpu/drm/stm/drv.c
create mode 100644 drivers/gpu/drm/stm/ltdc.c
create mode 100644 drivers/gpu/drm/stm/ltdc.h
diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
index 78d7fc0..f57540d 100644
--- a/drivers/gpu/drm/Kconfig
+++ b/drivers/gpu/drm/Kconfig
@@ -246,6 +246,8 @@ source "drivers/gpu/drm/fsl-dcu/Kconfig"
source "drivers/gpu/drm/tegra/Kconfig"
+source "drivers/gpu/drm/stm/Kconfig"
+
source "drivers/gpu/drm/panel/Kconfig"
source "drivers/gpu/drm/bridge/Kconfig"
diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
index 59f0f9b..aa62ded 100644
--- a/drivers/gpu/drm/Makefile
+++ b/drivers/gpu/drm/Makefile
@@ -82,6 +82,7 @@ obj-$(CONFIG_DRM_BOCHS) += bochs/
obj-$(CONFIG_DRM_VIRTIO_GPU) += virtio/
obj-$(CONFIG_DRM_MSM) += msm/
obj-$(CONFIG_DRM_TEGRA) += tegra/
+obj-$(CONFIG_DRM_STM) += stm/
obj-$(CONFIG_DRM_STI) += sti/
obj-$(CONFIG_DRM_IMX) += imx/
obj-$(CONFIG_DRM_MEDIATEK) += mediatek/
diff --git a/drivers/gpu/drm/stm/Kconfig b/drivers/gpu/drm/stm/Kconfig
new file mode 100644
index 0000000..2c4817f
--- /dev/null
+++ b/drivers/gpu/drm/stm/Kconfig
@@ -0,0 +1,16 @@
+config DRM_STM
+ tristate "DRM Support for STMicroelectronics SoC Series"
+ depends on DRM && (ARCH_STM32 || ARCH_MULTIPLATFORM)
+ select DRM_KMS_HELPER
+ select DRM_GEM_CMA_HELPER
+ select DRM_KMS_CMA_HELPER
+ select DRM_PANEL
+ select VIDEOMODE_HELPERS
+ select FB_PROVIDE_GET_FB_UNMAPPED_AREA
+ default y
+
+ help
+ Enable support for the on-chip display controller on
+ STMicroelectronics STM32 MCUs.
+ To compile this driver as a module, choose M here: the module
+ will be called stm-drm.
diff --git a/drivers/gpu/drm/stm/Makefile b/drivers/gpu/drm/stm/Makefile
new file mode 100644
index 0000000..e114d45
--- /dev/null
+++ b/drivers/gpu/drm/stm/Makefile
@@ -0,0 +1,7 @@
+ccflags-y := -Iinclude/drm
+
+stm-drm-y := \
+ drv.o \
+ ltdc.o
+
+obj-$(CONFIG_DRM_STM) += stm-drm.o
diff --git a/drivers/gpu/drm/stm/drv.c b/drivers/gpu/drm/stm/drv.c
new file mode 100644
index 0000000..83ab48f
--- /dev/null
+++ b/drivers/gpu/drm/stm/drv.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/component.h>
+#include <linux/of_platform.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+
+#include "ltdc.h"
+
+#define DRIVER_NAME "stm"
+#define DRIVER_DESC "STMicroelectronics SoC DRM"
+#define DRIVER_DATE "20170330"
+#define DRIVER_MAJOR 1
+#define DRIVER_MINOR 0
+#define DRIVER_PATCH_LEVEL 0
+
+#define STM_MAX_FB_WIDTH 2048
+#define STM_MAX_FB_HEIGHT 2048 /* same as width to handle orientation */
+
+static void drv_output_poll_changed(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ drm_fbdev_cma_hotplug_event(ldev->fbdev);
+}
+
+static const struct drm_mode_config_funcs drv_mode_config_funcs = {
+ .fb_create = drm_fb_cma_create,
+ .output_poll_changed = drv_output_poll_changed,
+ .atomic_check = drm_atomic_helper_check,
+ .atomic_commit = drm_atomic_helper_commit,
+};
+
+static void drv_lastclose(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ drm_fbdev_cma_restore_mode(ldev->fbdev);
+}
+
+DEFINE_DRM_GEM_CMA_FOPS(drv_driver_fops);
+
+static struct drm_driver drv_driver = {
+ .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_PRIME |
+ DRIVER_ATOMIC,
+ .lastclose = drv_lastclose,
+ .name = DRIVER_NAME,
+ .desc = DRIVER_DESC,
+ .date = DRIVER_DATE,
+ .major = DRIVER_MAJOR,
+ .minor = DRIVER_MINOR,
+ .patchlevel = DRIVER_PATCH_LEVEL,
+ .fops = &drv_driver_fops,
+ .dumb_create = drm_gem_cma_dumb_create,
+ .dumb_map_offset = drm_gem_cma_dumb_map_offset,
+ .dumb_destroy = drm_gem_dumb_destroy,
+ .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
+ .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
+ .gem_free_object_unlocked = drm_gem_cma_free_object,
+ .gem_vm_ops = &drm_gem_cma_vm_ops,
+ .gem_prime_export = drm_gem_prime_export,
+ .gem_prime_import = drm_gem_prime_import,
+ .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
+ .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
+ .gem_prime_vmap = drm_gem_cma_prime_vmap,
+ .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
+ .gem_prime_mmap = drm_gem_cma_prime_mmap,
+ .enable_vblank = ltdc_crtc_enable_vblank,
+ .disable_vblank = ltdc_crtc_disable_vblank,
+};
+
+static int drv_load(struct drm_device *ddev)
+{
+ struct platform_device *pdev = to_platform_device(ddev->dev);
+ struct drm_fbdev_cma *fbdev;
+ struct ltdc_device *ldev;
+ int ret;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ ldev = devm_kzalloc(ddev->dev, sizeof(*ldev), GFP_KERNEL);
+ if (!ldev)
+ return -ENOMEM;
+
+ ddev->dev_private = (void *)ldev;
+
+ drm_mode_config_init(ddev);
+
+ /*
+ * set max width and height as default value.
+ * this value would be used to check framebuffer size limitation
+ * at drm_mode_addfb().
+ */
+ ddev->mode_config.min_width = 0;
+ ddev->mode_config.min_height = 0;
+ ddev->mode_config.max_width = STM_MAX_FB_WIDTH;
+ ddev->mode_config.max_height = STM_MAX_FB_HEIGHT;
+ ddev->mode_config.funcs = &drv_mode_config_funcs;
+
+ ret = ltdc_load(ddev);
+ if (ret)
+ goto err;
+
+ drm_mode_config_reset(ddev);
+ drm_kms_helper_poll_init(ddev);
+
+ if (ddev->mode_config.num_connector) {
+ ldev = ddev->dev_private;
+ fbdev = drm_fbdev_cma_init(ddev, 16,
+ ddev->mode_config.num_connector);
+ if (IS_ERR(fbdev)) {
+ DRM_DEBUG("Warning: fails to create fbdev\n");
+ fbdev = NULL;
+ }
+ ldev->fbdev = fbdev;
+ }
+
+ platform_set_drvdata(pdev, ddev);
+
+ return 0;
+err:
+ drm_mode_config_cleanup(ddev);
+ return ret;
+}
+
+static void drv_unload(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ if (ldev->fbdev) {
+ drm_fbdev_cma_fini(ldev->fbdev);
+ ldev->fbdev = NULL;
+ }
+ drm_kms_helper_poll_fini(ddev);
+ ltdc_unload(ddev);
+ drm_mode_config_cleanup(ddev);
+}
+
+static int stm_drm_platform_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct drm_device *ddev;
+ int ret;
+
+ DRM_DEBUG("%s\n", __func__);
+
+ dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
+
+ ddev = drm_dev_alloc(&drv_driver, dev);
+ if (IS_ERR(ddev))
+ return PTR_ERR(ddev);
+
+ ret = drv_load(ddev);
+ if (ret)
+ goto err_unref;
+
+ ret = drm_dev_register(ddev, 0);
+ if (ret)
+ goto err_unref;
+
+ return 0;
+
+err_unref:
+ drm_dev_unref(ddev);
+
+ return ret;
+}
+
+static int stm_drm_platform_remove(struct platform_device *pdev)
+{
+ struct drm_device *ddev = platform_get_drvdata(pdev);
+
+ DRM_DEBUG("%s\n", __func__);
+
+ drm_dev_unregister(ddev);
+ drv_unload(ddev);
+ drm_dev_unref(ddev);
+
+ return 0;
+}
+
+static const struct of_device_id drv_dt_ids[] = {
+ { .compatible = "st,stm32-ltdc"},
+ { /* end node */ },
+};
+MODULE_DEVICE_TABLE(of, drv_dt_ids);
+
+static struct platform_driver stm_drm_platform_driver = {
+ .probe = stm_drm_platform_probe,
+ .remove = stm_drm_platform_remove,
+ .driver = {
+ .name = DRIVER_NAME,
+ .of_match_table = drv_dt_ids,
+ },
+};
+
+module_platform_driver(stm_drm_platform_driver);
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
+MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c
new file mode 100644
index 0000000..a373178
--- /dev/null
+++ b/drivers/gpu/drm/stm/ltdc.c
@@ -0,0 +1,1161 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_address.h>
+#include <linux/of_graph.h>
+#include <linux/reset.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_of.h>
+#include <drm/drm_panel.h>
+#include <drm/drm_plane_helper.h>
+
+#include <video/videomode.h>
+
+#include "ltdc.h"
+
+#define NB_CRTC 1
+#define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
+
+#define MAX_IRQ 4
+
+#define HWVER_10200 0x010200
+#define HWVER_10300 0x010300
+#define HWVER_20101 0x020101
+
+/*
+ * The address of some registers depends on the HW version: such registers have
+ * an extra offset specified with reg_ofs.
+ */
+#define REG_OFS_NONE 0
+#define REG_OFS_4 4 /* Insertion of "Layer Configuration 2" reg */
+#define REG_OFS (ldev->caps.reg_ofs)
+#define LAY_OFS 0x80 /* Register Offset between 2 layers */
+
+/* Global register offsets */
+#define LTDC_IDR 0x0000 /* IDentification */
+#define LTDC_LCR 0x0004 /* Layer Count */
+#define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */
+#define LTDC_BPCR 0x000C /* Back Porch Configuration */
+#define LTDC_AWCR 0x0010 /* Active Width Configuration */
+#define LTDC_TWCR 0x0014 /* Total Width Configuration */
+#define LTDC_GCR 0x0018 /* Global Control */
+#define LTDC_GC1R 0x001C /* Global Configuration 1 */
+#define LTDC_GC2R 0x0020 /* Global Configuration 2 */
+#define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */
+#define LTDC_GACR 0x0028 /* GAmma Correction */
+#define LTDC_BCCR 0x002C /* Background Color Configuration */
+#define LTDC_IER 0x0034 /* Interrupt Enable */
+#define LTDC_ISR 0x0038 /* Interrupt Status */
+#define LTDC_ICR 0x003C /* Interrupt Clear */
+#define LTDC_LIPCR 0x0040 /* Line Interrupt Position Configuration */
+#define LTDC_CPSR 0x0044 /* Current Position Status */
+#define LTDC_CDSR 0x0048 /* Current Display Status */
+
+/* Layer register offsets */
+#define LTDC_L1LC1R (0x0080) /* L1 Layer Configuration 1 */
+#define LTDC_L1LC2R (0x0084) /* L1 Layer Configuration 2 */
+#define LTDC_L1CR (0x0084 + REG_OFS) /* L1 Control */
+#define LTDC_L1WHPCR (0x0088 + REG_OFS) /* L1 Window Hor Position Config */
+#define LTDC_L1WVPCR (0x008C + REG_OFS) /* L1 Window Vert Position Config */
+#define LTDC_L1CKCR (0x0090 + REG_OFS) /* L1 Color Keying Configuration */
+#define LTDC_L1PFCR (0x0094 + REG_OFS) /* L1 Pixel Format Configuration */
+#define LTDC_L1CACR (0x0098 + REG_OFS) /* L1 Constant Alpha Config */
+#define LTDC_L1DCCR (0x009C + REG_OFS) /* L1 Default Color Configuration */
+#define LTDC_L1BFCR (0x00A0 + REG_OFS) /* L1 Blend Factors Configuration */
+#define LTDC_L1FBBCR (0x00A4 + REG_OFS) /* L1 FrameBuffer Bus Control */
+#define LTDC_L1AFBCR (0x00A8 + REG_OFS) /* L1 AuxFB Control */
+#define LTDC_L1CFBAR (0x00AC + REG_OFS) /* L1 Color FrameBuffer Address */
+#define LTDC_L1CFBLR (0x00B0 + REG_OFS) /* L1 Color FrameBuffer Length */
+#define LTDC_L1CFBLNR (0x00B4 + REG_OFS) /* L1 Color FrameBuffer Line Nb */
+#define LTDC_L1AFBAR (0x00B8 + REG_OFS) /* L1 AuxFB Address */
+#define LTDC_L1AFBLR (0x00BC + REG_OFS) /* L1 AuxFB Length */
+#define LTDC_L1AFBLNR (0x00C0 + REG_OFS) /* L1 AuxFB Line Number */
+#define LTDC_L1CLUTWR (0x00C4 + REG_OFS) /* L1 CLUT Write */
+#define LTDC_L1YS1R (0x00E0 + REG_OFS) /* L1 YCbCr Scale 1 */
+#define LTDC_L1YS2R (0x00E4 + REG_OFS) /* L1 YCbCr Scale 2 */
+
+/* Bit definitions */
+#define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */
+#define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */
+
+#define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */
+#define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */
+
+#define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */
+#define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */
+
+#define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */
+#define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */
+
+#define GCR_LTDCEN BIT(0) /* LTDC ENable */
+#define GCR_DEN BIT(16) /* Dither ENable */
+#define GCR_PCPOL BIT(28) /* Pixel Clock POLarity */
+#define GCR_DEPOL BIT(29) /* Data Enable POLarity */
+#define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity */
+#define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity */
+
+#define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */
+#define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */
+#define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */
+#define GC1R_PBEN BIT(12) /* Precise Blending ENable */
+#define GC1R_DT GENMASK(15, 14) /* Dithering Technique */
+#define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */
+#define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */
+#define GC1R_BCP BIT(22) /* Background Colour Programmable */
+#define GC1R_BBEN BIT(23) /* Background Blending ENabled */
+#define GC1R_LNIP BIT(24) /* Line Number IRQ Position */
+#define GC1R_TP BIT(25) /* Timing Programmable */
+#define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */
+#define GC1R_SPP BIT(27) /* Sync Polarity Programmable */
+#define GC1R_DWP BIT(28) /* Dither Width Programmable */
+#define GC1R_STREN BIT(29) /* STatus Registers ENabled */
+#define GC1R_BMEN BIT(31) /* Blind Mode ENabled */
+
+#define GC2R_EDCA BIT(0) /* External Display Control Ability */
+#define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */
+#define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
+#define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
+#define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */
+#define GC2R_EDCEN BIT(7) /* External Display Control ENabled */
+
+#define SRCR_IMR BIT(0) /* IMmediate Reload */
+#define SRCR_VBR BIT(1) /* Vertical Blanking Reload */
+
+#define BCCR_BCBLACK 0x00 /* Background Color BLACK */
+#define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */
+#define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */
+#define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */
+#define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */
+
+#define IER_LIE BIT(0) /* Line Interrupt Enable */
+#define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */
+#define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */
+#define IER_RRIE BIT(3) /* Register Reload Interrupt enable */
+
+#define ISR_LIF BIT(0) /* Line Interrupt Flag */
+#define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */
+#define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */
+#define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */
+
+#define LXCR_LEN BIT(0) /* Layer ENable */
+#define LXCR_COLKEN BIT(1) /* Color Keying Enable */
+#define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
+
+#define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */
+#define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */
+
+#define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */
+#define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */
+
+#define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */
+
+#define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */
+
+#define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */
+#define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */
+
+#define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */
+#define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */
+
+#define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */
+
+#define HSPOL_AL 0 /* Horizontal Sync POLarity Active Low */
+#define VSPOL_AL 0 /* Vertical Sync POLarity Active Low */
+#define DEPOL_AL 0 /* Data Enable POLarity Active Low */
+#define PCPOL_IPC 0 /* Input Pixel Clock */
+#define HSPOL_AH GCR_HSPOL /* Horizontal Sync POLarity Active High */
+#define VSPOL_AH GCR_VSPOL /* Vertical Sync POLarity Active High */
+#define DEPOL_AH GCR_DEPOL /* Data Enable POLarity Active High */
+#define PCPOL_IIPC GCR_PCPOL /* Inverted Input Pixel Clock */
+#define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */
+#define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */
+#define BF1_CA 0x400 /* Constant Alpha */
+#define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
+#define BF2_1CA 0x005 /* 1 - Constant Alpha */
+
+#define NB_PF 8 /* Max nb of HW pixel format */
+
+enum ltdc_pix_fmt {
+ PF_NONE,
+ /* RGB formats */
+ PF_ARGB8888, /* ARGB [32 bits] */
+ PF_RGBA8888, /* RGBA [32 bits] */
+ PF_RGB888, /* RGB [24 bits] */
+ PF_RGB565, /* RGB [16 bits] */
+ PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */
+ PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */
+ /* Indexed formats */
+ PF_L8, /* Indexed 8 bits [8 bits] */
+ PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */
+ PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */
+};
+
+/* The index gives the encoding of the pixel format for an HW version */
+static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = {
+ PF_ARGB8888, /* 0x00 */
+ PF_RGB888, /* 0x01 */
+ PF_RGB565, /* 0x02 */
+ PF_ARGB1555, /* 0x03 */
+ PF_ARGB4444, /* 0x04 */
+ PF_L8, /* 0x05 */
+ PF_AL44, /* 0x06 */
+ PF_AL88 /* 0x07 */
+};
+
+static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = {
+ PF_ARGB8888, /* 0x00 */
+ PF_RGB888, /* 0x01 */
+ PF_RGB565, /* 0x02 */
+ PF_RGBA8888, /* 0x03 */
+ PF_AL44, /* 0x04 */
+ PF_L8, /* 0x05 */
+ PF_ARGB1555, /* 0x06 */
+ PF_ARGB4444 /* 0x07 */
+};
+
+static inline u32 reg_read(void __iomem *base, u32 reg)
+{
+ return readl_relaxed(base + reg);
+}
+
+static inline void reg_write(void __iomem *base, u32 reg, u32 val)
+{
+ writel_relaxed(val, base + reg);
+}
+
+static inline void reg_set(void __iomem *base, u32 reg, u32 mask)
+{
+ reg_write(base, reg, reg_read(base, reg) | mask);
+}
+
+static inline void reg_clear(void __iomem *base, u32 reg, u32 mask)
+{
+ reg_write(base, reg, reg_read(base, reg) & ~mask);
+}
+
+static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
+ u32 val)
+{
+ reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
+}
+
+static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc)
+{
+ return (struct ltdc_device *)crtc->dev->dev_private;
+}
+
+static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane)
+{
+ return (struct ltdc_device *)plane->dev->dev_private;
+}
+
+static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc)
+{
+ return (struct ltdc_device *)enc->dev->dev_private;
+}
+
+static inline struct ltdc_device *connector_to_ltdc(struct drm_connector *con)
+{
+ return (struct ltdc_device *)con->dev->dev_private;
+}
+
+static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt)
+{
+ enum ltdc_pix_fmt pf;
+
+ switch (drm_fmt) {
+ case DRM_FORMAT_ARGB8888:
+ case DRM_FORMAT_XRGB8888:
+ pf = PF_ARGB8888;
+ break;
+ case DRM_FORMAT_RGBA8888:
+ case DRM_FORMAT_RGBX8888:
+ pf = PF_RGBA8888;
+ break;
+ case DRM_FORMAT_RGB888:
+ pf = PF_RGB888;
+ break;
+ case DRM_FORMAT_RGB565:
+ pf = PF_RGB565;
+ break;
+ case DRM_FORMAT_ARGB1555:
+ case DRM_FORMAT_XRGB1555:
+ pf = PF_ARGB1555;
+ break;
+ case DRM_FORMAT_ARGB4444:
+ case DRM_FORMAT_XRGB4444:
+ pf = PF_ARGB4444;
+ break;
+ case DRM_FORMAT_C8:
+ pf = PF_L8;
+ break;
+ default:
+ pf = PF_NONE;
+ break;
+ /* Note: There are no DRM_FORMAT for AL44 and AL88 */
+ }
+
+ return pf;
+}
+
+static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf)
+{
+ switch (pf) {
+ case PF_ARGB8888:
+ return DRM_FORMAT_ARGB8888;
+ case PF_RGBA8888:
+ return DRM_FORMAT_RGBA8888;
+ case PF_RGB888:
+ return DRM_FORMAT_RGB888;
+ case PF_RGB565:
+ return DRM_FORMAT_RGB565;
+ case PF_ARGB1555:
+ return DRM_FORMAT_ARGB1555;
+ case PF_ARGB4444:
+ return DRM_FORMAT_ARGB4444;
+ case PF_L8:
+ return DRM_FORMAT_C8;
+ case PF_AL44: /* No DRM support */
+ case PF_AL88: /* No DRM support */
+ case PF_NONE:
+ default:
+ return 0;
+ }
+}
+
+static irqreturn_t ltdc_irq_thread(int irq, void *arg)
+{
+ struct drm_device *ddev = arg;
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0);
+
+ /* Line IRQ : trigger the vblank event */
+ if (ldev->irq_status & ISR_LIF)
+ drm_crtc_handle_vblank(crtc);
+
+ /* Save FIFO Underrun & Transfer Error status */
+ mutex_lock(&ldev->err_lock);
+ if (ldev->irq_status & ISR_FUIF)
+ ldev->error_status |= ISR_FUIF;
+ if (ldev->irq_status & ISR_TERRIF)
+ ldev->error_status |= ISR_TERRIF;
+ mutex_unlock(&ldev->err_lock);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t ltdc_irq(int irq, void *arg)
+{
+ struct drm_device *ddev = arg;
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ /* Read & Clear the interrupt status */
+ ldev->irq_status = reg_read(ldev->regs, LTDC_ISR);
+ reg_write(ldev->regs, LTDC_ICR, ldev->irq_status);
+
+ return IRQ_WAKE_THREAD;
+}
+
+/*
+ * DRM_CRTC
+ */
+
+static void ltdc_crtc_load_lut(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ unsigned int i, lay;
+
+ for (lay = 0; lay < ldev->caps.nb_layers; lay++)
+ for (i = 0; i < 256; i++)
+ reg_write(ldev->regs, LTDC_L1CLUTWR + lay * LAY_OFS,
+ ldev->clut[i]);
+}
+
+static void ltdc_crtc_enable(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /* Sets the background color value */
+ reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK);
+
+ /* Enable IRQ */
+ reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
+
+ /* Immediately commit the planes */
+ reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
+
+ /* Enable LTDC */
+ reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN);
+
+ drm_crtc_vblank_on(crtc);
+}
+
+static void ltdc_crtc_disable(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_pending_vblank_event *event = crtc->state->event;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_crtc_vblank_off(crtc);
+
+ /* disable LTDC */
+ reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN);
+
+ /* disable IRQ */
+ reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE);
+
+ /* immediately commit disable of layers before switching off LTDC */
+ reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR);
+}
+
+static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_display_mode *mode = &crtc->state->adjusted_mode;
+ struct videomode vm;
+ int rate = mode->clock * 1000;
+ u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h;
+ u32 total_width, total_height;
+ u32 val;
+
+ drm_display_mode_to_videomode(mode, &vm);
+
+ DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name);
+ DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive);
+ DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n",
+ vm.hfront_porch, vm.hback_porch, vm.hsync_len,
+ vm.vfront_porch, vm.vback_porch, vm.vsync_len);
+
+ /* Convert video timings to ltdc timings */
+ hsync = vm.hsync_len - 1;
+ vsync = vm.vsync_len - 1;
+ accum_hbp = hsync + vm.hback_porch;
+ accum_vbp = vsync + vm.vback_porch;
+ accum_act_w = accum_hbp + vm.hactive;
+ accum_act_h = accum_vbp + vm.vactive;
+ total_width = accum_act_w + vm.hfront_porch;
+ total_height = accum_act_h + vm.vfront_porch;
+
+ clk_disable(ldev->pixel_clk);
+
+ if (clk_set_rate(ldev->pixel_clk, rate) < 0) {
+ DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate);
+ return;
+ }
+
+ clk_enable(ldev->pixel_clk);
+
+ /* Configures the HS, VS, DE and PC polarities. */
+ val = HSPOL_AL | HSPOL_AL | DEPOL_AL | PCPOL_IPC;
+
+ if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH)
+ val |= HSPOL_AH;
+
+ if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH)
+ val |= VSPOL_AH;
+
+ if (vm.flags & DISPLAY_FLAGS_DE_HIGH)
+ val |= DEPOL_AH;
+
+ if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
+ val |= PCPOL_IIPC;
+
+ reg_update_bits(ldev->regs, LTDC_GCR,
+ GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
+
+ /* Set Synchronization size */
+ val = (hsync << 16) | vsync;
+ reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val);
+
+ /* Set Accumulated Back porch */
+ val = (accum_hbp << 16) | accum_vbp;
+ reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val);
+
+ /* Set Accumulated Active Width */
+ val = (accum_act_w << 16) | accum_act_h;
+ reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val);
+
+ /* Set total width & height */
+ val = (total_width << 16) | total_height;
+ reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val);
+
+ reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1));
+}
+
+static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc,
+ struct drm_crtc_state *old_crtc_state)
+{
+ struct ltdc_device *ldev = crtc_to_ltdc(crtc);
+ struct drm_pending_vblank_event *event = crtc->state->event;
+
+ DRM_DEBUG_ATOMIC("\n");
+
+ /* Commit shadow registers = update planes at next vblank */
+ reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR);
+
+ if (event) {
+ crtc->state->event = NULL;
+
+ spin_lock_irq(&crtc->dev->event_lock);
+ if (drm_crtc_vblank_get(crtc) == 0)
+ drm_crtc_arm_vblank_event(crtc, event);
+ else
+ drm_crtc_send_vblank_event(crtc, event);
+ spin_unlock_irq(&crtc->dev->event_lock);
+ }
+}
+
+static struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = {
+ .load_lut = ltdc_crtc_load_lut,
+ .enable = ltdc_crtc_enable,
+ .disable = ltdc_crtc_disable,
+ .mode_set_nofb = ltdc_crtc_mode_set_nofb,
+ .atomic_flush = ltdc_crtc_atomic_flush,
+};
+
+int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG_DRIVER("\n");
+ reg_set(ldev->regs, LTDC_IER, IER_LIE);
+
+ return 0;
+}
+
+void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG_DRIVER("\n");
+ reg_clear(ldev->regs, LTDC_IER, IER_LIE);
+}
+
+static struct drm_crtc_funcs ltdc_crtc_funcs = {
+ .destroy = drm_crtc_cleanup,
+ .set_config = drm_atomic_helper_set_config,
+ .page_flip = drm_atomic_helper_page_flip,
+ .reset = drm_atomic_helper_crtc_reset,
+ .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
+};
+
+/*
+ * DRM_PLANE
+ */
+
+static int ltdc_plane_atomic_check(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct drm_framebuffer *fb = state->fb;
+ u32 src_x, src_y, src_w, src_h;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (!fb)
+ return 0;
+
+ /* convert src_ from 16:16 format */
+ src_x = state->src_x >> 16;
+ src_y = state->src_y >> 16;
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+
+ /* Reject scaling */
+ if ((src_w != state->crtc_w) || (src_h != state->crtc_h)) {
+ DRM_ERROR("Scaling is not supported");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void ltdc_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *oldstate)
+{
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ struct drm_plane_state *state = plane->state;
+ struct drm_framebuffer *fb = state->fb;
+ u32 lofs = plane->index * LAY_OFS;
+ u32 x0 = state->crtc_x;
+ u32 x1 = state->crtc_x + state->crtc_w - 1;
+ u32 y0 = state->crtc_y;
+ u32 y1 = state->crtc_y + state->crtc_h - 1;
+ u32 src_x, src_y, src_w, src_h;
+ u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr;
+ enum ltdc_pix_fmt pf;
+
+ if (!state->crtc || !fb) {
+ DRM_DEBUG_DRIVER("fb or crtc NULL");
+ return;
+ }
+
+ /* convert src_ from 16:16 format */
+ src_x = state->src_x >> 16;
+ src_y = state->src_y >> 16;
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+
+ DRM_DEBUG_DRIVER(
+ "plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n",
+ plane->base.id, fb->base.id,
+ src_w, src_h, src_x, src_y,
+ state->crtc_w, state->crtc_h, state->crtc_x, state->crtc_y);
+
+ bpcr = reg_read(ldev->regs, LTDC_BPCR);
+ ahbp = (bpcr & BPCR_AHBP) >> 16;
+ avbp = bpcr & BPCR_AVBP;
+
+ /* Configures the horizontal start and stop position */
+ val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp);
+ reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs,
+ LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val);
+
+ /* Configures the vertical start and stop position */
+ val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp);
+ reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs,
+ LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val);
+
+ /* Specifies the pixel format */
+ pf = to_ltdc_pixelformat(fb->format->format);
+ for (val = 0; val < NB_PF; val++)
+ if (ldev->caps.pix_fmt_hw[val] == pf)
+ break;
+
+ if (val == NB_PF) {
+ DRM_ERROR("Pixel format %.4s not supported\n",
+ (char *)&fb->format->format);
+ val = 0; /* set by default ARGB 32 bits */
+ }
+ reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val);
+
+ /* Configures the color frame buffer pitch in bytes & line length */
+ pitch_in_bytes = fb->pitches[0];
+ line_length = drm_format_plane_cpp(fb->format->format, 0) *
+ (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1;
+ val = ((pitch_in_bytes << 16) | line_length);
+ reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs,
+ LXCFBLR_CFBLL | LXCFBLR_CFBP, val);
+
+ /* Specifies the constant alpha value */
+ val = CONSTA_MAX;
+ reg_update_bits(ldev->regs, LTDC_L1CACR + lofs,
+ LXCACR_CONSTA, val);
+
+ /* Specifies the blending factors */
+ val = BF1_PAXCA | BF2_1PAXCA;
+ reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs,
+ LXBFCR_BF2 | LXBFCR_BF1, val);
+
+ /* Configures the frame buffer line number */
+ val = y1 - y0 + 1;
+ reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs,
+ LXCFBLNR_CFBLN, val);
+
+ /* Sets the FB address */
+ paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0);
+
+ DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr);
+ reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr);
+
+ /* Enable layer and CLUT if needed */
+ val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0;
+ val |= LXCR_LEN;
+ reg_update_bits(ldev->regs, LTDC_L1CR + lofs,
+ LXCR_LEN | LXCR_CLUTEN, val);
+
+ mutex_lock(&ldev->err_lock);
+ if (ldev->error_status & ISR_FUIF) {
+ DRM_DEBUG_DRIVER("Fifo underrun\n");
+ ldev->error_status &= ~ISR_FUIF;
+ }
+ if (ldev->error_status & ISR_TERRIF) {
+ DRM_DEBUG_DRIVER("Transfer error\n");
+ ldev->error_status &= ~ISR_TERRIF;
+ }
+ mutex_unlock(&ldev->err_lock);
+}
+
+static void ltdc_plane_atomic_disable(struct drm_plane *plane,
+ struct drm_plane_state *oldstate)
+{
+ struct ltdc_device *ldev = plane_to_ltdc(plane);
+ u32 lofs = plane->index * LAY_OFS;
+
+ /* disable layer */
+ reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN);
+
+ DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n",
+ oldstate->crtc->base.id, plane->base.id);
+}
+
+static struct drm_plane_funcs ltdc_plane_funcs = {
+ .update_plane = drm_atomic_helper_update_plane,
+ .disable_plane = drm_atomic_helper_disable_plane,
+ .destroy = drm_plane_cleanup,
+ .set_property = drm_atomic_helper_plane_set_property,
+ .reset = drm_atomic_helper_plane_reset,
+ .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
+};
+
+static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = {
+ .atomic_check = ltdc_plane_atomic_check,
+ .atomic_update = ltdc_plane_atomic_update,
+ .atomic_disable = ltdc_plane_atomic_disable,
+};
+
+static struct drm_plane *ltdc_plane_create(struct drm_device *ddev,
+ enum drm_plane_type type)
+{
+ unsigned long possible_crtcs = CRTC_MASK;
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct device *dev = ddev->dev;
+ struct drm_plane *plane;
+ unsigned int i, nb_fmt = 0;
+ u32 formats[NB_PF];
+ u32 drm_fmt;
+ int ret;
+
+ /* Get supported pixel formats */
+ for (i = 0; i < NB_PF; i++) {
+ drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]);
+ if (!drm_fmt)
+ continue;
+ formats[nb_fmt++] = drm_fmt;
+ }
+
+ plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL);
+ if (!plane)
+ return 0;
+
+ ret = drm_universal_plane_init(ddev, plane, possible_crtcs,
+ <dc_plane_funcs, formats, nb_fmt,
+ type, NULL);
+ if (ret < 0)
+ return 0;
+
+ drm_plane_helper_add(plane, <dc_plane_helper_funcs);
+
+ DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id);
+
+ return plane;
+}
+
+static void ltdc_plane_destroy_all(struct drm_device *ddev)
+{
+ struct drm_plane *plane, *plane_temp;
+
+ list_for_each_entry_safe(plane, plane_temp,
+ &ddev->mode_config.plane_list, head)
+ drm_plane_cleanup(plane);
+}
+
+static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct drm_plane *primary, *overlay;
+ unsigned int i;
+ int res;
+
+ primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY);
+ if (!primary) {
+ DRM_ERROR("Can not create primary plane\n");
+ return -EINVAL;
+ }
+
+ res = drm_crtc_init_with_planes(ddev, crtc, primary, NULL,
+ <dc_crtc_funcs, NULL);
+ if (res) {
+ DRM_ERROR("Can not initialize CRTC\n");
+ goto cleanup;
+ }
+
+ drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs);
+
+ DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id);
+
+ /* Add planes. Note : the first layer is used by primary plane */
+ for (i = 1; i < ldev->caps.nb_layers; i++) {
+ overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY);
+ if (!overlay) {
+ res = -ENOMEM;
+ DRM_ERROR("Can not create overlay plane %d\n", i);
+ goto cleanup;
+ }
+ }
+
+ return 0;
+
+cleanup:
+ ltdc_plane_destroy_all(ddev);
+ return res;
+}
+
+/*
+ * DRM_ENCODER
+ */
+
+static void ltdc_rgb_encoder_enable(struct drm_encoder *encoder)
+{
+ struct ltdc_device *ldev = encoder_to_ltdc(encoder);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_panel_prepare(ldev->panel);
+ drm_panel_enable(ldev->panel);
+}
+
+static void ltdc_rgb_encoder_disable(struct drm_encoder *encoder)
+{
+ struct ltdc_device *ldev = encoder_to_ltdc(encoder);
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_panel_disable(ldev->panel);
+ drm_panel_unprepare(ldev->panel);
+}
+
+static const struct drm_encoder_helper_funcs ltdc_rgb_encoder_helper_funcs = {
+ .enable = ltdc_rgb_encoder_enable,
+ .disable = ltdc_rgb_encoder_disable,
+};
+
+static const struct drm_encoder_funcs ltdc_rgb_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static struct drm_encoder *ltdc_rgb_encoder_create(struct drm_device *ddev)
+{
+ struct drm_encoder *encoder;
+
+ encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL);
+ if (!encoder)
+ return NULL;
+
+ encoder->possible_crtcs = CRTC_MASK;
+ encoder->possible_clones = 0; /* No cloning support */
+
+ drm_encoder_init(ddev, encoder, <dc_rgb_encoder_funcs,
+ DRM_MODE_ENCODER_DPI, NULL);
+
+ drm_encoder_helper_add(encoder, <dc_rgb_encoder_helper_funcs);
+
+ DRM_DEBUG_DRIVER("RGB encoder:%d created\n", encoder->base.id);
+
+ return encoder;
+}
+
+/*
+ * DRM_CONNECTOR
+ */
+
+static int ltdc_rgb_connector_get_modes(struct drm_connector *connector)
+{
+ struct drm_device *ddev = connector->dev;
+ struct ltdc_device *ldev = ddev->dev_private;
+ int ret = 0;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ if (ldev->panel)
+ ret = drm_panel_get_modes(ldev->panel);
+
+ return ret < 0 ? 0 : ret;
+}
+
+static struct drm_connector_helper_funcs ltdc_rgb_connector_helper_funcs = {
+ .get_modes = ltdc_rgb_connector_get_modes,
+};
+
+static enum drm_connector_status
+ltdc_rgb_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct ltdc_device *ldev = connector_to_ltdc(connector);
+
+ return ldev->panel ? connector_status_connected :
+ connector_status_disconnected;
+}
+
+static void ltdc_rgb_connector_destroy(struct drm_connector *connector)
+{
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_connector_unregister(connector);
+ drm_connector_cleanup(connector);
+}
+
+static const struct drm_connector_funcs ltdc_rgb_connector_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .detect = ltdc_rgb_connector_detect,
+ .destroy = ltdc_rgb_connector_destroy,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+struct drm_connector *ltdc_rgb_connector_create(struct drm_device *ddev)
+{
+ struct drm_connector *connector;
+ int err;
+
+ connector = devm_kzalloc(ddev->dev, sizeof(*connector), GFP_KERNEL);
+ if (!connector) {
+ DRM_ERROR("Failed to allocate connector\n");
+ return NULL;
+ }
+
+ connector->polled = DRM_CONNECTOR_POLL_HPD;
+
+ err = drm_connector_init(ddev, connector, <dc_rgb_connector_funcs,
+ DRM_MODE_CONNECTOR_DPI);
+ if (err) {
+ DRM_ERROR("Failed to initialize connector\n");
+ return NULL;
+ }
+
+ drm_connector_helper_add(connector, <dc_rgb_connector_helper_funcs);
+
+ DRM_DEBUG_DRIVER("RGB connector:%d created\n", connector->base.id);
+
+ return connector;
+}
+
+static int ltdc_get_caps(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+ u32 bus_width_log2, lcr, gc2r;
+
+ /* at least 1 layer must be managed */
+ lcr = reg_read(ldev->regs, LTDC_LCR);
+
+ ldev->caps.nb_layers = max_t(int, lcr, 1);
+
+ /* set data bus width */
+ gc2r = reg_read(ldev->regs, LTDC_GC2R);
+ bus_width_log2 = (gc2r & GC2R_BW) >> 4;
+ ldev->caps.bus_width = 8 << bus_width_log2;
+ ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR);
+
+ switch (ldev->caps.hw_version) {
+ case HWVER_10200:
+ case HWVER_10300:
+ ldev->caps.reg_ofs = REG_OFS_NONE;
+ ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0;
+ break;
+ case HWVER_20101:
+ ldev->caps.reg_ofs = REG_OFS_4;
+ ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1;
+ break;
+ default:
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static struct drm_panel *ltdc_get_panel(struct drm_device *ddev)
+{
+ struct device *dev = ddev->dev;
+ struct device_node *np = dev->of_node;
+ struct device_node *entity, *port = NULL;
+ struct drm_panel *panel = NULL;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ /*
+ * Parse ltdc node to get remote port and find RGB panel / HDMI slave
+ * If a dsi or a bridge (hdmi, lvds...) is connected to ltdc,
+ * a remote port & RGB panel will not be found.
+ */
+ for_each_endpoint_of_node(np, entity) {
+ if (!of_device_is_available(entity))
+ continue;
+
+ port = of_graph_get_remote_port_parent(entity);
+ if (port) {
+ panel = of_drm_find_panel(port);
+ of_node_put(port);
+ if (panel) {
+ DRM_DEBUG_DRIVER("remote panel %s\n",
+ port->full_name);
+ } else {
+ DRM_DEBUG_DRIVER("panel missing\n");
+ of_node_put(entity);
+ }
+ }
+ }
+
+ return panel;
+}
+
+int ltdc_load(struct drm_device *ddev)
+{
+ struct platform_device *pdev = to_platform_device(ddev->dev);
+ struct ltdc_device *ldev = ddev->dev_private;
+ struct device *dev = ddev->dev;
+ struct device_node *np = dev->of_node;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector = NULL;
+ struct drm_crtc *crtc;
+ struct reset_control *rstc;
+ struct resource res;
+ int irq, ret, i;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ ldev->panel = ltdc_get_panel(ddev);
+ if (!ldev->panel)
+ return -EPROBE_DEFER;
+
+ rstc = of_reset_control_get(np, NULL);
+
+ mutex_init(&ldev->err_lock);
+
+ ldev->pixel_clk = devm_clk_get(dev, "lcd");
+ if (IS_ERR(ldev->pixel_clk)) {
+ DRM_ERROR("Unable to get lcd clock\n");
+ return -ENODEV;
+ }
+
+ if (clk_prepare_enable(ldev->pixel_clk)) {
+ DRM_ERROR("Unable to prepare pixel clock\n");
+ return -ENODEV;
+ }
+
+ if (of_address_to_resource(np, 0, &res)) {
+ DRM_ERROR("Unable to get resource\n");
+ return -ENODEV;
+ }
+
+ ldev->regs = devm_ioremap_resource(dev, &res);
+ if (IS_ERR(ldev->regs)) {
+ DRM_ERROR("Unable to get ltdc registers\n");
+ return PTR_ERR(ldev->regs);
+ }
+
+ for (i = 0; i < MAX_IRQ; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0)
+ continue;
+
+ ret = devm_request_threaded_irq(dev, irq, ltdc_irq,
+ ltdc_irq_thread, IRQF_ONESHOT,
+ dev_name(dev), ddev);
+ if (ret) {
+ DRM_ERROR("Failed to register LTDC interrupt\n");
+ return ret;
+ }
+ }
+
+ if (!IS_ERR(rstc))
+ reset_control_deassert(rstc);
+
+ /* Disable interrupts */
+ reg_clear(ldev->regs, LTDC_IER,
+ IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE);
+
+ ret = ltdc_get_caps(ddev);
+ if (ret) {
+ DRM_ERROR("hardware identifier (0x%08x) not supported!\n",
+ ldev->caps.hw_version);
+ return ret;
+ }
+
+ DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version);
+
+ if (ldev->panel) {
+ encoder = ltdc_rgb_encoder_create(ddev);
+ if (!encoder) {
+ DRM_ERROR("Failed to create RGB encoder\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ connector = ltdc_rgb_connector_create(ddev);
+ if (!connector) {
+ DRM_ERROR("Failed to create RGB connector\n");
+ ret = -EINVAL;
+ goto err;
+ }
+
+ ret = drm_mode_connector_attach_encoder(connector, encoder);
+ if (ret) {
+ DRM_ERROR("Failed to attach connector to encoder\n");
+ goto err;
+ }
+
+ drm_panel_attach(ldev->panel, connector);
+ }
+
+ crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL);
+ if (!crtc) {
+ DRM_ERROR("Failed to allocate crtc\n");
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ ret = ltdc_crtc_init(ddev, crtc);
+ if (ret) {
+ DRM_ERROR("Failed to init crtc\n");
+ goto err;
+ }
+
+ ret = drm_vblank_init(ddev, NB_CRTC);
+ if (ret) {
+ DRM_ERROR("Failed calling drm_vblank_init()\n");
+ goto err;
+ }
+
+ /* Allow usage of vblank without having to call drm_irq_install */
+ ddev->irq_enabled = 1;
+
+ return 0;
+err:
+ if (ldev->panel)
+ drm_panel_detach(ldev->panel);
+
+ clk_disable_unprepare(ldev->pixel_clk);
+
+ return ret;
+}
+
+void ltdc_unload(struct drm_device *ddev)
+{
+ struct ltdc_device *ldev = ddev->dev_private;
+
+ DRM_DEBUG_DRIVER("\n");
+
+ drm_vblank_cleanup(ddev);
+
+ if (ldev->panel)
+ drm_panel_detach(ldev->panel);
+
+ clk_disable_unprepare(ldev->pixel_clk);
+}
+
+MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>");
+MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>");
+MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
+MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>");
+MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpu/drm/stm/ltdc.h b/drivers/gpu/drm/stm/ltdc.h
new file mode 100644
index 0000000..d7a9c73
--- /dev/null
+++ b/drivers/gpu/drm/stm/ltdc.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) STMicroelectronics SA 2017
+ *
+ * Authors: Philippe Cornu <philippe.cornu@st.com>
+ * Yannick Fertre <yannick.fertre@st.com>
+ * Fabien Dessenne <fabien.dessenne@st.com>
+ * Mickael Reulier <mickael.reulier@st.com>
+ *
+ * License terms: GNU General Public License (GPL), version 2
+ */
+
+#ifndef _LTDC_H_
+#define _LTDC_H_
+
+struct ltdc_caps {
+ u32 hw_version; /* hardware version */
+ u32 nb_layers; /* number of supported layers */
+ u32 reg_ofs; /* register offset for applicable regs */
+ u32 bus_width; /* bus width (32 or 64 bits) */
+ const u32 *pix_fmt_hw; /* supported pixel formats */
+};
+
+struct ltdc_device {
+ struct drm_fbdev_cma *fbdev;
+ void __iomem *regs;
+ struct clk *pixel_clk; /* lcd pixel clock */
+ struct drm_panel *panel;
+ struct mutex err_lock; /* protecting error_status */
+ struct ltdc_caps caps;
+ u32 clut[256]; /* color look up table */
+ u32 error_status;
+ u32 irq_status;
+};
+
+int ltdc_crtc_enable_vblank(struct drm_device *dev, unsigned int pipe);
+void ltdc_crtc_disable_vblank(struct drm_device *dev, unsigned int pipe);
+int ltdc_load(struct drm_device *ddev);
+void ltdc_unload(struct drm_device *ddev);
+
+#endif
--
1.9.1
^ permalink raw reply related
* [PATCH v7 3/9] dt-bindings: display: Add STM32 LTDC driver
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
This patch adds documentation of device tree bindings for the STM32 LTDC
(Lcd-Tft Display Controller).
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
.../devicetree/bindings/display/st,stm32-ltdc.txt | 36 ++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
new file mode 100644
index 0000000..8e14769
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.txt
@@ -0,0 +1,36 @@
+* STMicroelectronics STM32 lcd-tft display controller
+
+- ltdc: lcd-tft display controller host
+ must be a sub-node of st-display-subsystem
+ Required properties:
+ - compatible: "st,stm32-ltdc"
+ - reg: Physical base address of the IP registers and length of memory mapped region.
+ - clocks: A list of phandle + clock-specifier pairs, one for each
+ entry in 'clock-names'.
+ - clock-names: A list of clock names. For ltdc it should contain:
+ - "lcd" for the clock feeding the output pixel clock & IP clock.
+ - resets: reset to be used by the device (defined by use of RCC macro).
+ Required nodes:
+ - Video port for RGB output.
+
+Example:
+
+/ {
+ ...
+ soc {
+ ...
+ ltdc: display-controller at 40016800 {
+ compatible = "st,stm32-ltdc";
+ reg = <0x40016800 0x200>;
+ interrupts = <88>, <89>;
+ resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
+ clocks = <&rcc 1 CLK_LCD>;
+ clock-names = "lcd";
+
+ port {
+ ltdc_out_rgb: endpoint {
+ };
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [PATCH v7 2/9] drm/fb-cma-helper: Add drm_fb_cma_get_gem_addr()
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Add function drm_fb_cma_get_gem_addr() which return the physical address
of framebuffer (1st pixel). This function will usually be called by plane
callback (atomic_update).
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
drivers/gpu/drm/drm_fb_cma_helper.c | 27 +++++++++++++++++++++++++++
include/drm/drm_fb_cma_helper.h | 4 ++++
2 files changed, 31 insertions(+)
diff --git a/drivers/gpu/drm/drm_fb_cma_helper.c b/drivers/gpu/drm/drm_fb_cma_helper.c
index 50abd1f..d2b77b0 100644
--- a/drivers/gpu/drm/drm_fb_cma_helper.c
+++ b/drivers/gpu/drm/drm_fb_cma_helper.c
@@ -260,6 +260,33 @@ struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_obj);
/**
+ * drm_fb_cma_get_gem_addr() - Get physical address for framebuffer
+ * @fb: The framebuffer
+ * @state: Which state of drm plane
+ * @plane: Which plane
+ * Return the CMA GEM address for given framebuffer.
+ *
+ * This function will usually be called from the PLANE callback functions.
+ */
+dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
+ struct drm_plane_state *state,
+ unsigned int plane)
+{
+ struct drm_fb_cma *fb_cma = to_fb_cma(fb);
+ dma_addr_t paddr;
+
+ if (plane >= 4)
+ return 0;
+
+ paddr = fb_cma->obj[plane]->paddr + fb->offsets[plane];
+ paddr += fb->format->cpp[plane] * (state->src_x >> 16);
+ paddr += fb->pitches[plane] * (state->src_y >> 16);
+
+ return paddr;
+}
+EXPORT_SYMBOL_GPL(drm_fb_cma_get_gem_addr);
+
+/**
* drm_fb_cma_prepare_fb() - Prepare CMA framebuffer
* @plane: Which plane
* @state: Plane state attach fence to
diff --git a/include/drm/drm_fb_cma_helper.h b/include/drm/drm_fb_cma_helper.h
index a5ecc0a..199a63f 100644
--- a/include/drm/drm_fb_cma_helper.h
+++ b/include/drm/drm_fb_cma_helper.h
@@ -41,6 +41,10 @@ struct drm_framebuffer *drm_fb_cma_create(struct drm_device *dev,
struct drm_gem_cma_object *drm_fb_cma_get_gem_obj(struct drm_framebuffer *fb,
unsigned int plane);
+dma_addr_t drm_fb_cma_get_gem_addr(struct drm_framebuffer *fb,
+ struct drm_plane_state *state,
+ unsigned int plane);
+
int drm_fb_cma_prepare_fb(struct drm_plane *plane,
struct drm_plane_state *state);
--
1.9.1
^ permalink raw reply related
* [PATCH v7 1/9] drm/cma: Update DEFINE_DRM_GEM_CMA_FOPS to add get_unmapped_area
From: Yannick Fertre @ 2017-04-14 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492164819-10513-1-git-send-email-yannick.fertre@st.com>
Missing field get_unmapped_area which is necessary with device without MMU
Signed-off-by: Yannick Fertre <yannick.fertre@st.com>
---
include/drm/drm_gem_cma_helper.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/drm/drm_gem_cma_helper.h b/include/drm/drm_gem_cma_helper.h
index f962d33..7320b14 100644
--- a/include/drm/drm_gem_cma_helper.h
+++ b/include/drm/drm_gem_cma_helper.h
@@ -50,6 +50,7 @@ struct drm_gem_cma_object {
.read = drm_read,\
.llseek = noop_llseek,\
.mmap = drm_gem_cma_mmap,\
+ .get_unmapped_area = drm_gem_cma_get_unmapped_area,\
}
/* free GEM object */
--
1.9.1
^ permalink raw reply related
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