* [PATCH V5 1/4] arm64: dts: Add basic DT to support Spreadtrum's SP9860G
From: Chunyan Zhang @ 2017-04-19 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1490599960-27330-1-git-send-email-chunyan.zhang@spreadtrum.com>
Hi Arnd, Olof
Could you please take this patch through arm-soc git if there are no
further comments? (The three other patches in this series have been
taken by Greg.)
Thanks,
Chunyan
On 27 March 2017 at 15:32, Chunyan Zhang <chunyan.zhang@spreadtrum.com> wrote:
> From: Orson Zhai <orson.zhai@spreadtrum.com>
>
> SC9860G is a 8 cores of A53 SoC with 4G LTE support SoC from Spreadtrum.
>
> According to regular hierarchy of sprd dts, whale2.dtsi contains SoC
> peripherals IP nodes, sc9860.dtsi contains stuff related to ARM core stuff
> and sp9860g dts is for the board level.
>
> Signed-off-by: Orson Zhai <orson.zhai@spreadtrum.com>
> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
> Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> ---
> arch/arm64/boot/dts/sprd/Makefile | 3 +-
> arch/arm64/boot/dts/sprd/sc9860.dtsi | 569 ++++++++++++++++++++++++++++++
> arch/arm64/boot/dts/sprd/sp9860g-1h10.dts | 56 +++
> arch/arm64/boot/dts/sprd/whale2.dtsi | 71 ++++
> 4 files changed, 698 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/sprd/sc9860.dtsi
> create mode 100644 arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
> create mode 100644 arch/arm64/boot/dts/sprd/whale2.dtsi
>
> diff --git a/arch/arm64/boot/dts/sprd/Makefile b/arch/arm64/boot/dts/sprd/Makefile
> index b658c5e..f0535e6 100644
> --- a/arch/arm64/boot/dts/sprd/Makefile
> +++ b/arch/arm64/boot/dts/sprd/Makefile
> @@ -1,4 +1,5 @@
> -dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb
> +dtb-$(CONFIG_ARCH_SPRD) += sc9836-openphone.dtb \
> + sp9860g-1h10.dtb
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
> new file mode 100644
> index 0000000..7b7d8ce
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
> @@ -0,0 +1,569 @@
> +/*
> + * Spreadtrum SC9860 SoC
> + *
> + * Copyright (C) 2016, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "whale2.dtsi"
> +
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> + core1 {
> + cpu = <&CPU1>;
> + };
> + core2 {
> + cpu = <&CPU2>;
> + };
> + core3 {
> + cpu = <&CPU3>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&CPU4>;
> + };
> + core1 {
> + cpu = <&CPU5>;
> + };
> + core2 {
> + cpu = <&CPU6>;
> + };
> + core3 {
> + cpu = <&CPU7>;
> + };
> + };
> + };
> +
> + CPU0: cpu at 530000 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530000>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU1: cpu at 530001 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530001>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU2: cpu at 530002 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530002>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU3: cpu at 530003 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530003>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU4: cpu at 530100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU5: cpu at 530101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530101>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU6: cpu at 530102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530102>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> +
> + CPU7: cpu at 530103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x530103>;
> + enable-method = "psci";
> + cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
> + };
> + };
> +
> + idle-states{
> + entry-method = "arm,psci";
> +
> + CORE_PD: core_pd {
> + compatible = "arm,idle-state";
> + entry-latency-us = <1000>;
> + exit-latency-us = <700>;
> + min-residency-us = <2500>;
> + local-timer-stop;
> + arm,psci-suspend-param = <0x00010002>;
> + };
> +
> + CLUSTER_PD: cluster_pd {
> + compatible = "arm,idle-state";
> + entry-latency-us = <1000>;
> + exit-latency-us = <1000>;
> + min-residency-us = <3000>;
> + local-timer-stop;
> + arm,psci-suspend-param = <0x01010003>;
> + };
> + };
> +
> + gic: interrupt-controller at 12001000 {
> + compatible = "arm,gic-400";
> + reg = <0 0x12001000 0 0x1000>,
> + <0 0x12002000 0 0x2000>,
> + <0 0x12004000 0 0x2000>,
> + <0 0x12006000 0 0x2000>;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8)
> + | IRQ_TYPE_LEVEL_LOW)>;
> + };
> +
> + pmu {
> + compatible = "arm,cortex-a53-pmu", "arm,armv8-pmuv3";
> + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-affinity = <&CPU0>,
> + <&CPU1>,
> + <&CPU2>,
> + <&CPU3>,
> + <&CPU4>,
> + <&CPU5>,
> + <&CPU6>,
> + <&CPU7>;
> + };
> +
> + soc {
> + funnel at 10001000 { /* SoC Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x10001000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + soc_funnel_out_port: endpoint {
> + remote-endpoint = <&etb_in>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + soc_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&main_funnel_out_port>;
> + };
> + };
> +
> + port at 2 {
> + reg = <4>;
> + soc_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpioint =
> + <&stm_out_port>;
> + };
> + };
> + };
> + };
> +
> + etb at 10003000 {
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x10003000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + port {
> + etb_in: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&soc_funnel_out_port>;
> + };
> + };
> + };
> +
> + stm at 10006000 {
> + compatible = "arm,coresight-stm", "arm,primecell";
> + reg = <0 0x10006000 0 0x1000>,
> + <0 0x01000000 0 0x180000>;
> + reg-names = "stm-base", "stm-stimulus-base";
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + port {
> + stm_out_port: endpoint {
> + remote-endpoint =
> + <&soc_funnel_in_port1>;
> + };
> + };
> + };
> +
> + funnel at 11001000 { /* Cluster0 Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x11001000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster0_funnel_out_port: endpoint {
> + remote-endpoint =
> + <&cluster0_etf_in>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster0_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm0_out>;
> + };
> + };
> +
> + port at 2 {
> + reg = <1>;
> + cluster0_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm1_out>;
> + };
> + };
> +
> + port at 3 {
> + reg = <2>;
> + cluster0_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm2_out>;
> + };
> + };
> +
> + port at 4 {
> + reg = <4>;
> + cluster0_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm3_out>;
> + };
> + };
> + };
> + };
> +
> + funnel at 11002000 { /* Cluster1 Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x11002000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster1_funnel_out_port: endpoint {
> + remote-endpoint =
> + <&cluster1_etf_in>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster1_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm4_out>;
> + };
> + };
> +
> + port at 2 {
> + reg = <1>;
> + cluster1_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm5_out>;
> + };
> + };
> +
> + port at 3 {
> + reg = <2>;
> + cluster1_funnel_in_port2: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm6_out>;
> + };
> + };
> +
> + port at 4 {
> + reg = <3>;
> + cluster1_funnel_in_port3: endpoint {
> + slave-mode;
> + remote-endpoint = <&etm7_out>;
> + };
> + };
> + };
> + };
> +
> + etf at 11003000 { /* ETF on Cluster0 */
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x11003000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster0_etf_out: endpoint {
> + remote-endpoint =
> + <&main_funnel_in_port0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster0_etf_in: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster0_funnel_out_port>;
> + };
> + };
> + };
> + };
> +
> + etf at 11004000 { /* ETF on Cluster1 */
> + compatible = "arm,coresight-tmc", "arm,primecell";
> + reg = <0 0x11004000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + cluster1_etf_out: endpoint {
> + remote-endpoint =
> + <&main_funnel_in_port1>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + cluster1_etf_in: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster1_funnel_out_port>;
> + };
> + };
> + };
> + };
> +
> + funnel at 11005000 { /* Main Funnel */
> + compatible = "arm,coresight-funnel", "arm,primecell";
> + reg = <0 0x11005000 0 0x1000>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 0 {
> + reg = <0>;
> + main_funnel_out_port: endpoint {
> + remote-endpoint =
> + <&soc_funnel_in_port0>;
> + };
> + };
> +
> + port at 1 {
> + reg = <0>;
> + main_funnel_in_port0: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster0_etf_out>;
> + };
> + };
> +
> + port at 2 {
> + reg = <1>;
> + main_funnel_in_port1: endpoint {
> + slave-mode;
> + remote-endpoint =
> + <&cluster1_etf_out>;
> + };
> + };
> + };
> + };
> +
> + etm at 11440000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11440000 0 0x1000>;
> + cpu = <&CPU0>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm0_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm at 11540000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11540000 0 0x1000>;
> + cpu = <&CPU1>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm1_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm at 11640000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11640000 0 0x1000>;
> + cpu = <&CPU2>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm2_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm at 11740000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11740000 0 0x1000>;
> + cpu = <&CPU3>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm3_out: endpoint {
> + remote-endpoint =
> + <&cluster0_funnel_in_port3>;
> + };
> + };
> + };
> +
> + etm at 11840000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11840000 0 0x1000>;
> + cpu = <&CPU4>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm4_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port0>;
> + };
> + };
> + };
> +
> + etm at 11940000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11940000 0 0x1000>;
> + cpu = <&CPU5>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm5_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port1>;
> + };
> + };
> + };
> +
> + etm at 11a40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11a40000 0 0x1000>;
> + cpu = <&CPU6>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm6_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port2>;
> + };
> + };
> + };
> +
> + etm at 11b40000 {
> + compatible = "arm,coresight-etm4x", "arm,primecell";
> + reg = <0 0x11b40000 0 0x1000>;
> + cpu = <&CPU7>;
> + clocks = <&ext_26m>;
> + clock-names = "apb_pclk";
> +
> + port {
> + etm7_out: endpoint {
> + remote-endpoint =
> + <&cluster1_funnel_in_port3>;
> + };
> + };
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
> new file mode 100644
> index 0000000..ae0b28c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sprd/sp9860g-1h10.dts
> @@ -0,0 +1,56 @@
> +/*
> + * Spreadtrum SP9860g board
> + *
> + * Copyright (C) 2017, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +/dts-v1/;
> +
> +#include "sc9860.dtsi"
> +
> +/ {
> + model = "Spreadtrum SP9860G 3GFHD Board";
> +
> + compatible = "sprd,sp9860g-1h10", "sprd,sc9860";
> +
> + aliases {
> + serial0 = &uart0; /* for Bluetooth */
> + serial1 = &uart1; /* UART console */
> + serial2 = &uart2; /* Reserved */
> + serial3 = &uart3; /* for GPS */
> + };
> +
> + memory{
> + device_type = "memory";
> + reg = <0x0 0x80000000 0 0x60000000>,
> + <0x1 0x80000000 0 0x60000000>;
> + };
> +
> + chosen {
> + stdout-path = "serial1:115200n8";
> + };
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> +
> +&uart1 {
> + status = "okay";
> +};
> +
> +&uart2 {
> + status = "okay";
> +};
> +
> +&uart3 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/sprd/whale2.dtsi b/arch/arm64/boot/dts/sprd/whale2.dtsi
> new file mode 100644
> index 0000000..7c217c5
> --- /dev/null
> +++ b/arch/arm64/boot/dts/sprd/whale2.dtsi
> @@ -0,0 +1,71 @@
> +/*
> + * Spreadtrum Whale2 platform peripherals
> + *
> + * Copyright (C) 2016, Spreadtrum Communications Inc.
> + *
> + * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + */
> +
> +/ {
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + ap-apb {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0 0x0 0x70000000 0x10000000>;
> +
> + uart0: serial at 0 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x0 0x100>;
> + interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> +
> + uart1: serial at 100000 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x100000 0x100>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> +
> + uart2: serial at 200000 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x200000 0x100>;
> + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> +
> + uart3: serial at 300000 {
> + compatible = "sprd,sc9860-uart",
> + "sprd,sc9836-uart";
> + reg = <0x300000 0x100>;
> + interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ext_26m>;
> + status = "disabled";
> + };
> + };
> +
> + };
> +
> + ext_26m: ext-26m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "ext_26m";
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* LDM/STM alignment fixups on arm64
From: Russell King - ARM Linux @ 2017-04-19 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <58F75D02.1030104@codeaurora.org>
On Wed, Apr 19, 2017 at 06:20:10PM +0530, Srinivas Ramana wrote:
> I don't have any application with me right now. But i just tried passing an
> intentional misaligned address in a test program. When i say intentional,
> please note this code is buggy and should be fixed.
Until there's reports of some application that regresses, there is
nothing to fix.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
^ permalink raw reply
* [GIT PULL 3/4] soc/tegra: Core SoC changes for v4.12-rc1
From: Olof Johansson @ 2017-04-19 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170406231020.32048-3-thierry.reding@gmail.com>
On Fri, Apr 07, 2017 at 01:10:19AM +0200, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.12-soc
>
> for you to fetch changes up to 1fd09e5d884a5ff4060948e0cf8f5d7eed16e936:
>
> soc/tegra: Add initial flowctrl support for Tegra132/210 (2017-04-04 15:52:31 +0200)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> soc/tegra: Core SoC changes for v4.12-rc1
>
> This contains PMC support for Tegra186 as well as a proper driver for
> the flow controller found on SoCs up to Tegra210. This also turns the
> fuse driver into an explicitly non-modular driver.
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 4/4] arm64: tegra: Device tree changes for v4.12-rc1
From: Olof Johansson @ 2017-04-19 13:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170406231020.32048-4-thierry.reding@gmail.com>
On Fri, Apr 07, 2017 at 01:10:20AM +0200, Thierry Reding wrote:
> Hi ARM SoC maintainers,
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.12-arm64-dt
>
> for you to fetch changes up to 18236a14883b718ce973e4c090db6ecb49b38287:
>
> arm64: tegra: Update the Tegra132 flowctrl compatible string (2017-04-04 17:15:05 +0200)
>
> Thanks,
> Thierry
>
> ----------------------------------------------------------------
> arm64: tegra: Device tree changes for v4.12-rc1
>
> This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
> SDHCI and GPIO. It also enables various features on the P2771 devkit.
>
> A small fix is made to the compatible string list for the flow
> controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.
Nice, merged. Any chance we'll see Jetson TX2 support for 4.13?
Thanks,
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 DT Updates for v4.12
From: Olof Johansson @ 2017-04-19 13:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491533253-13389-1-git-send-email-andy.gross@linaro.org>
On Thu, Apr 06, 2017 at 09:47:33PM -0500, Andy Gross wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-for-4.12
>
> for you to fetch changes up to 6c8583d6feeb45a4c812114f6087e9911b93ea48:
>
> arm64: dts: msm8996: Add ADSP PIL node (2017-03-29 13:43:52 -0500)
>
> ----------------------------------------------------------------
> Qualcomm ARM64 Updates for v4.12
>
> * Fixup MSM8996 SMP2P and add ADSP PIL / SLPI SMP2P node
> * Replace PMU compatible w/ A53 specific one
> * Add APQ8016 ramoops
> * Update MSM8916 hexagon node
> * Add PM8994 RTC
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v4.12
From: Olof Johansson @ 2017-04-19 13:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1491578743.git.horms+renesas@verge.net.au>
On Fri, Apr 07, 2017 at 11:57:59AM -0400, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these second round of Renesas ARM64 based SoC DT updates
> for v4.12.
>
> This pull request is based on the previous round of
> such requests, tagged as renesas-arm64-dt-for-v4.12,
> which you have already pulled.
>
>
> The following changes since commit 3cbe33367d4fd480a92fbc131a96fa925be9e95d:
>
> arm64: dts: r8a7796: salvator-x: Drop superfluous status update for frequency override (2017-03-13 10:21:16 +0100)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt2-for-v4.12
>
> for you to fetch changes up to 6922bd71adab0a7fe8ffbdc3e72a46431fa29656:
>
> arm64: dts: r8a7795: salvator-x: Drop _clk suffix from X12 clock node name (2017-04-05 14:17:19 -0400)
>
> ----------------------------------------------------------------
> Second Round of Renesas ARM64 Based SoC DT Updates for v4.12
>
> Corrections:
> * r8a7795: Correct SATA device size to 2MiB for r8a7795 SoC
>
> Cleanup:
> * Drop _clk suffix from X12 clock node name for r8a7795 SoC
>
> Enhancements:
> * Add reset control properties for r8a779[56]
>
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 4/5] arm64: dts: exynos: DTS for v4.12
From: Olof Johansson @ 2017-04-19 13:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170408141004.386-5-krzk@kernel.org>
On Sat, Apr 08, 2017 at 04:10:03PM +0200, Krzysztof Kozlowski wrote:
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt64-4.12
>
> for you to fetch changes up to e3c07546747cdec07ff15c984bc6cebc9c9f788c:
>
> arm64: dts: exynos: Add the burst and esc clock frequency properties to DSI node (2017-03-08 08:55:39 +0200)
>
> ----------------------------------------------------------------
> Samsung DeviceTree ARM64 update for v4.12:
> 1. Add IR, touchscreen and panel to TM2/TM2E boards.
> 2. Add proper clock frequency properties to DSI nodes.
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 2/2] Rockchip dts64 updates for 4.12 part2
From: Olof Johansson @ 2017-04-19 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1589941.s7YUBqhHWQ@phil>
On Mon, Apr 10, 2017 at 11:56:37AM +0200, Heiko Stuebner wrote:
> The following changes since commit 41b464ef10219e45513d1bcaddacd47ce0bd6136:
>
> arm64: dts: rockchip: fix PCIe domain number for rk3399 (2017-03-22 17:50:09 +0100)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v4.12-rockchip-dts64-2
>
> for you to fetch changes up to 2f513bd9eac1a2642b40387d4f89c3987641e59b:
>
> arm64: dts: rockchip: fix the memory size of PX5 Evaluation board (2017-04-07 22:29:11 +0200)
>
> ----------------------------------------------------------------
> Basic support for new rk3328, a 4-core Cortex-A53 soc and a fix for the
> default memory definition on the px5 eval board. While the bootloader
> should already override it with the actual amount, it's better to not
> carry around wrong values.
>
> ----------------------------------------------------------------
> Andy Yan (1):
> arm64: dts: rockchip: fix the memory size of PX5 Evaluation board
>
> Liang Chen (4):
> dt-bindings: add binding for rk3328-grf
> arm64: dts: rockchip: add core dtsi file for RK3328 SoCs
> dt-bindings: document rockchip rk3328-evb board
> arm64: dts: rockchip: add RK3328 eavluation board devicetree
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 4/5] Freescale arm64 device tree updates for 4.12
From: Olof Johansson @ 2017-04-19 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491835076-1995-4-git-send-email-shawnguo@kernel.org>
On Mon, Apr 10, 2017 at 10:37:55PM +0800, Shawn Guo wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-dt64-4.12
>
> for you to fetch changes up to 6678254bb4a46dc47620f993a4b71480a3c56ee4:
>
> dt-bindings: arm: Add entry for FSL LS1088A RDB, QDS boards (2017-04-04 20:57:27 +0800)
>
> ----------------------------------------------------------------
> Freescale arm64 device tree updates for 4.12:
> - Add support of LS2088A SoC, which is a derivative of existing
> LS2080A SoC, and the major difference is on ARM cores.
> - Add support of LS1088A SoC which includes eight Cortex-A53 cores
> with 32 KB L1 D-cache and I-cache respectively.
> - Add crypto and thermal device support for LS1012A platform.
> - Add ECC register region for SATA device on LS1012A, LS1043A and
> LS1046A platforms.
Merged, thanks!
-Olof
^ permalink raw reply
* [PATCH v6 6/8] coresight: add support for CPU debug module
From: Suzuki K Poulose @ 2017-04-19 13:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491485461-22800-7-git-send-email-leo.yan@linaro.org>
On 06/04/17 14:30, Leo Yan wrote:
> Coresight includes debug module and usually the module connects with CPU
> debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
> description for related info in "Part H: External Debug".
>
> Chapter H7 "The Sample-based Profiling Extension" introduces several
> sampling registers, e.g. we can check program counter value with
> combined CPU exception level, secure state, etc. So this is helpful for
> analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
> loop with IRQ disabled. In this case the CPU cannot switch context and
> handle any interrupt (including IPIs), as the result it cannot handle
> SMP call for stack dump.
>
> This patch is to enable coresight debug module, so firstly this driver
> is to bind apb clock for debug module and this is to ensure the debug
> module can be accessed from program or external debugger. And the driver
> uses sample-based registers for debug purpose, e.g. when system triggers
> panic, the driver will dump program counter and combined context
> registers (EDCIDSR, EDVIDSR); by parsing context registers so can
> quickly get to know CPU secure state, exception level, etc.
>
> Some of the debug module registers are located in CPU power domain, so
> this requires the CPU power domain stays on when access related debug
> registers, but the power management for CPU power domain is quite
> dependent on SoC integration for power management. For the platforms
> which with sane power controller implementations, this driver follows
> the method to set EDPRCR to try to pull the CPU out of low power state
> and then set 'no power down request' bit so the CPU has no chance to
> lose power.
>
> If the SoC has not followed up this design well for power management
> controller, the user should use the command line parameter or sysfs
> to constrain all or partial idle states to ensure the CPU power
> domain is enabled and access coresight CPU debug component safely.
Hi Leo,
This version looks good to me. I have two minor comments below.
> +
> +static struct notifier_block debug_notifier = {
> + .notifier_call = debug_notifier_call,
> +};
> +
> +static int debug_enable_func(void)
> +{
> + struct debug_drvdata *drvdata;
> + int cpu;
> +
> + for_each_possible_cpu(cpu) {
> + drvdata = per_cpu(debug_drvdata, cpu);
> + if (!drvdata)
> + continue;
> +
> + pm_runtime_get_sync(drvdata->dev);
> + }
> +
> + return atomic_notifier_chain_register(&panic_notifier_list,
> + &debug_notifier);
> +}
> +
> +static int debug_disable_func(void)
> +{
> + struct debug_drvdata *drvdata;
> + int cpu;
> +
> + for_each_possible_cpu(cpu) {
> + drvdata = per_cpu(debug_drvdata, cpu);
> + if (!drvdata)
> + continue;
> +
> + pm_runtime_put(drvdata->dev);
> + }
> +
> + return atomic_notifier_chain_unregister(&panic_notifier_list,
> + &debug_notifier);
> +}
I believe you should, reverse the order of these operations in debug_disable_func()
to prevent getting a panic notifier after we have released the power domain for the
debug.
i.e, :
atomic_notifier_chain_unregister(...);
for_each_possible_cpu(cpu) {}
> +
> +static ssize_t debug_func_knob_write(struct file *f,
> + const char __user *buf, size_t count, loff_t *ppos)
> +{
> + u8 val;
> + int ret;
> +
> + ret = kstrtou8_from_user(buf, count, 2, &val);
> + if (ret)
> + return ret;
> +
> + mutex_lock(&debug_lock);
> +
> + if (val == debug_enable)
> + goto out;
> +
> + if (val)
> + ret = debug_enable_func();
> + else
> + ret = debug_disable_func();
> +
> + if (ret) {
> + pr_err("%s: unable to %s debug function: %d\n",
> + __func__, val ? "enable" : "disable", ret);
> + goto err;
> + }
> +
> + debug_enable = val;
> +out:
> + ret = count;
> +err:
> + mutex_unlock(&debug_lock);
> + return ret;
> +}
> +
> +static ssize_t debug_func_knob_read(struct file *f,
> + char __user *ubuf, size_t count, loff_t *ppos)
> +{
> + ssize_t ret;
> + char buf[2];
> +
> + mutex_lock(&debug_lock);
> +
> + buf[0] = '0' + debug_enable;
> + buf[1] = '\n';
> + ret = simple_read_from_buffer(ubuf, count, ppos, buf, sizeof(buf));
> +
> + mutex_unlock(&debug_lock);
> + return ret;
> +}
> +
> +static const struct file_operations debug_func_knob_fops = {
> + .open = simple_open,
> + .read = debug_func_knob_read,
> + .write = debug_func_knob_write,
> +};
> +
> +static int debug_func_init(void)
> +{
> + struct dentry *file;
> + int ret;
> +
> + /* Create debugfs node */
> + debug_debugfs_dir = debugfs_create_dir("coresight_cpu_debug", NULL);
> + if (!debug_debugfs_dir) {
> + pr_err("%s: unable to create debugfs directory\n", __func__);
> + return -ENOMEM;
> + }
> +
> + file = debugfs_create_file("enable", S_IRUGO | S_IWUSR,
> + debug_debugfs_dir, NULL, &debug_func_knob_fops);
> + if (!file) {
> + pr_err("%s: unable to create enable knob file\n", __func__);
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + /* Use sysfs node to enable functionality */
> + if (!debug_enable)
> + return 0;
> +
> + /* Register function to be called for panic */
> + ret = atomic_notifier_chain_register(&panic_notifier_list,
> + &debug_notifier);
> + if (ret) {
> + pr_err("%s: unable to register notifier: %d\n",
> + __func__, ret);
> + goto err;
> + }
> +
Since we depend on the value of debug_enable above, below in debug_probe()
and in debug_remove(), we should protect these paths using the debug_lock mutex,
like we do above, to make sure we don't create a race.
> + return 0;
> +
> +err:
> + debugfs_remove_recursive(debug_debugfs_dir);
> + return ret;
> +}
> +
> +static void debug_func_exit(void)
> +{
> + debugfs_remove_recursive(debug_debugfs_dir);
> +
> + /* Unregister panic notifier callback */
> + if (debug_enable)
> + atomic_notifier_chain_unregister(&panic_notifier_list,
> + &debug_notifier);
> +}
> +
> +static int debug_probe(struct amba_device *adev, const struct amba_id *id)
> +{
> + void __iomem *base;
> + struct device *dev = &adev->dev;
> + struct debug_drvdata *drvdata;
> + struct resource *res = &adev->res;
> + struct device_node *np = adev->dev.of_node;
> + int ret;
> +
> + drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
> + if (!drvdata)
> + return -ENOMEM;
> +
> + drvdata->cpu = np ? of_coresight_get_cpu(np) : 0;
> + if (per_cpu(debug_drvdata, drvdata->cpu)) {
> + dev_err(dev, "CPU%d drvdata has been initialized\n",
> + drvdata->cpu);
May be we could warn about a possible issue in the DT ?
Cheers
Suzuki
^ permalink raw reply
* [GIT PULL 2/2] ZTE arm64 device tree changes for 4.12
From: Olof Johansson @ 2017-04-19 13:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491837665-2579-2-git-send-email-shawnguo@kernel.org>
On Mon, Apr 10, 2017 at 11:21:05PM +0800, Shawn Guo wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/zte-dt64-4.12
>
> for you to fetch changes up to f006aaf7b11230e38a35f09d706e751fa77eb799:
>
> arm64: dts: zte: add tvenc device for zx296718 (2017-03-24 16:25:19 +0800)
>
> ----------------------------------------------------------------
> ZTE arm64 device tree updates for 4.12:
> - Add mmc devices for ZX296718 SoC and enable those available on
> zx296718-evb board.
> - Add VOU controller device, output devices HDMI and TVENC, and enable
> display support for zx296718-evb board.
> - Remove pll_vga clock from ZX296718 device tree, as it's not a fixed
> rate clock.
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] arm64: dts: hisilicon dts updates for v4.12
From: Olof Johansson @ 2017-04-19 13:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <58EBA861.2010809@hisilicon.com>
On Mon, Apr 10, 2017 at 04:44:33PM +0100, Wei Xu wrote:
> Hi Arnd, Hi Olof, Hi Kevin,
>
> Please help to pull the following changes.
> Thanks!
>
> Best Regards,
> Wei
>
> ---
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://github.com/hisilicon/linux-hisi.git tags/hisi-arm64-dt-for-4.12
>
> for you to fetch changes up to d4e1eaeee56894f45d0093f9d432be0c868f7c4c:
>
> arm64: dts: hisi: add pinctrl dtsi file for HiKey960 development board (2017-04-10 23:34:26 +0800)
>
> ----------------------------------------------------------------
> ARM64: DT: Hisilicon SoC DT updates for 4.12
>
> - Reset the hi6220 mmc hosts to avoid hang
> - Add the binding for the hi3798cv200 SoC and the poplar board
> - Add basic dts files to support the hi3798cv200 poplar board
> - Enable the Mbigen, XGE, RoCE and SAS for the hip07 d05 board
> - Add driver strength MACRO for the hi3660 SoC
> - Add the pinctrl dtsi file for hikey960 board to configure the pins
Merged, thanks.
-Olof
^ permalink raw reply
* [PATCH v2 1/6] arm64: dts: Add symlinks for cros-ec-keyboard and cros-ec-sbs
From: Heiko Stuebner @ 2017-04-19 13:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOesGMirj2j5P7_Ri4CSCux+O3hH_wxvrra7-p33AdXO4Ej5Hg@mail.gmail.com>
Am Mittwoch, 19. April 2017, 21:54:09 CEST schrieb Olof Johansson:
> Hi,
>
> On Tue, Feb 28, 2017 at 3:20 AM, Heiko Stuebner <heiko@sntech.de> wrote:
> > Hi Olof,
> >
> > Am Dienstag, 21. Februar 2017, 15:47:31 CET schrieb Olof Johansson:
> >> On Thu, Feb 9, 2017 at 5:05 PM, Brian Norris <briannorris@chromium.org> wrote:
> >> > From: Douglas Anderson <dianders@chromium.org>
> >> >
> >> > We'd like to be able to use the cros-ec-keyboard.dtsi and
> >> > cros-ec-sbs.dtsi snippets for arm64 devices. Currently those files live
> >> > in the arm/boot/dts directory.
> >> >
> >> > Let's follow the convention set by commit 8ee57b8182c4 ("ARM64: dts:
> >> > vexpress: Use a symlink to vexpress-v2m-rs1.dtsi from arch=arm") and use
> >> > a symlink. Note that in this case we put the files in a new
> >> > "include/common" directory since these snippets may need to be
> >> > referenced by dts files in many different subdirectories.
> >>
> >> I'd rather have something like this:
> >>
> >> https://marc.info/?m=147547436324674&w=2
> >>
> >> Instead of having everybody move things over. I.e. make it easy to
> >> refer to the arm version from arm64 instead of creating a "common"
> >> layer inbetween.
> >
> > just so it gets noticed, I've done and tested [0], which hopefully should
> > implement your suggestions above.
> >
> > If that looks ok, how do you want that picked up? Should I just include
> > them in my regular rockchip branches or do you to pick them into some
> > immutable branch, if other surprise-users turn up in time for 4.12?
>
> Sigh. I completely dropped the ball on this, and I didn't see it
> included in any of your pull requests for 4.12 since I never actually
> acked that approach.
>
> I've applied the patches onto a dt/include-paths stable branch, but
> we're late for merging dependent code on top of it for 4.12.
Didn't you merge the patches into a branch already and the rk3399-gru
support on top of it?
Aka
https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git/log/?h=shared/dt-symlinks
Which one of my previous pull requests was already based on.
Heiko
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt64 for v4.12 (#2)
From: Olof Johansson @ 2017-04-19 13:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87y3v4uvd2.fsf@free-electrons.com>
On Thu, Apr 13, 2017 at 06:26:33PM +0200, Gregory CLEMENT wrote:
> Hi,
>
> Here is the second pull request for dt64 for mvebu for v4.12.
>
> Gregory
>
> The following changes since commit 60894719241e2b3d6d202304de9ad33a8da3685c:
>
> arm64: marvell: dts: add PPv2.2 description to Armada 7K/8K (2017-03-23 17:46:23 +0100)
>
> are available in the git repository at:
>
> git://git.infradead.org/linux-mvebu.git tags/mvebu-dt64-4.12-2
>
> for you to fetch changes up to 7ba2ef7c7200e476ee2cede7bcffcf7749e02f5c:
>
> arm64: marvell: dts: enable the crypto engine on the Armada 8040 DB (2017-04-12 10:36:30 +0200)
>
> ----------------------------------------------------------------
> mvebu dt64 for 4.12 (part 2)
>
> - crypto engine description for the Armada 7k/8k SoCs and the boards
> using it
> - SDHCI description for the Armada 37xx and 7k/8k SoCs and the boards
> using it
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm Defconfig Updates for v4.12
From: Olof Johansson @ 2017-04-19 13:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491533302-13487-1-git-send-email-andy.gross@linaro.org>
On Thu, Apr 06, 2017 at 09:48:22PM -0500, Andy Gross wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-defconfig-for-4.12
>
> for you to fetch changes up to 806766915051b43b783cc5621a6ea3a1e5e84aee:
>
> ARM: qcom_defconfig: Enable Qualcomm remoteproc and related drivers (2017-03-28 16:23:24 -0500)
Merged, thanks.
-Olof
^ permalink raw reply
* [PATCH v2 1/6] arm64: dts: Add symlinks for cros-ec-keyboard and cros-ec-sbs
From: Olof Johansson @ 2017-04-19 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2579212.374vCSe9xi@phil>
On Wed, Apr 19, 2017 at 10:25 PM, Heiko Stuebner <heiko@sntech.de> wrote:
> Am Mittwoch, 19. April 2017, 21:54:09 CEST schrieb Olof Johansson:
>> Hi,
>>
>> On Tue, Feb 28, 2017 at 3:20 AM, Heiko Stuebner <heiko@sntech.de> wrote:
>> > Hi Olof,
>> >
>> > Am Dienstag, 21. Februar 2017, 15:47:31 CET schrieb Olof Johansson:
>> >> On Thu, Feb 9, 2017 at 5:05 PM, Brian Norris <briannorris@chromium.org> wrote:
>> >> > From: Douglas Anderson <dianders@chromium.org>
>> >> >
>> >> > We'd like to be able to use the cros-ec-keyboard.dtsi and
>> >> > cros-ec-sbs.dtsi snippets for arm64 devices. Currently those files live
>> >> > in the arm/boot/dts directory.
>> >> >
>> >> > Let's follow the convention set by commit 8ee57b8182c4 ("ARM64: dts:
>> >> > vexpress: Use a symlink to vexpress-v2m-rs1.dtsi from arch=arm") and use
>> >> > a symlink. Note that in this case we put the files in a new
>> >> > "include/common" directory since these snippets may need to be
>> >> > referenced by dts files in many different subdirectories.
>> >>
>> >> I'd rather have something like this:
>> >>
>> >> https://marc.info/?m=147547436324674&w=2
>> >>
>> >> Instead of having everybody move things over. I.e. make it easy to
>> >> refer to the arm version from arm64 instead of creating a "common"
>> >> layer inbetween.
>> >
>> > just so it gets noticed, I've done and tested [0], which hopefully should
>> > implement your suggestions above.
>> >
>> > If that looks ok, how do you want that picked up? Should I just include
>> > them in my regular rockchip branches or do you to pick them into some
>> > immutable branch, if other surprise-users turn up in time for 4.12?
>>
>> Sigh. I completely dropped the ball on this, and I didn't see it
>> included in any of your pull requests for 4.12 since I never actually
>> acked that approach.
>>
>> I've applied the patches onto a dt/include-paths stable branch, but
>> we're late for merging dependent code on top of it for 4.12.
>
> Didn't you merge the patches into a branch already and the rk3399-gru
> support on top of it?
>
> Aka
> https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git/log/?h=shared/dt-symlinks
>
> Which one of my previous pull requests was already based on.
Yeah, ignore the above (the original branch is the one to use). I must
be turning blind.
Adding Maxime on Cc since I asked him to move over to the new include
model post-rc1 for some of his stuff.
-Olof
^ permalink raw reply
* [GIT PULL 5/5] ARM: defconfig: exynos for v4.12
From: Olof Johansson @ 2017-04-19 13:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170408141004.386-2-krzk@kernel.org>
On Sat, Apr 08, 2017 at 04:10:00PM +0200, Krzysztof Kozlowski wrote:
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-defconfig-4.12
>
> for you to fetch changes up to fd2694a112d6b53eba8d8e182fef0dccdab6c9e8:
>
> ARM: exynos_defconfig: Increase CONFIG_CMA_SIZE_MBYTES to 96 (2017-03-07 21:01:52 +0200)
>
> ----------------------------------------------------------------
> Samsung defconfig ARM update for v4.12:
> 1. Enable DYNAMIC_DEBUG because it is useful for debugging.
> 2. Increase CMA memory region to allow handling H.264 1080p videos.
>
> ----------------------------------------------------------------
> Krzysztof Kozlowski (1):
> ARM: exynos_defconfig: Enable DYNAMIC_DEBUG and get rid of old ext3
>
> Shuah Khan (1):
> ARM: exynos_defconfig: Increase CONFIG_CMA_SIZE_MBYTES to 96
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 5/5] i.MX defconfig updates for 4.12
From: Olof Johansson @ 2017-04-19 13:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491835076-1995-5-git-send-email-shawnguo@kernel.org>
On Mon, Apr 10, 2017 at 10:37:56PM +0800, Shawn Guo wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-defconfig-4.12
>
> for you to fetch changes up to c5054a98bce49ab2956e0dbc3fdfd6345716b16b:
>
> ARM: imx_v6_v7_defconfig: Select SMSC_PHY (2017-03-30 21:21:34 +0800)
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL 2/2] omap defconfig changes for v4.12
From: Olof Johansson @ 2017-04-19 13:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <58ebe107.04ab630a.24f7e.7ce2SMTPIN_ADDED_BROKEN@mx.google.com>
On Mon, Apr 10, 2017 at 12:46:07PM -0700, Tony Lindgren wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.12/defconfig-signed
>
> for you to fetch changes up to 25ea8207abb80652629670095d4a2e06915c4cd2:
>
> ARM: omap2plus_defconfig: Enable droid 4 devices (2017-04-10 09:29:40 -0700)
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm Driver Updates for v4.12
From: Olof Johansson @ 2017-04-19 13:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491533316-13528-1-git-send-email-andy.gross@linaro.org>
On Thu, Apr 06, 2017 at 09:48:36PM -0500, Andy Gross wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-drivers-for-4.12
>
> for you to fetch changes up to b182cc4d597a6e73ff04ee1b7fb4f1a28f56ae3d:
>
> firmware: qcom_scm: add two scm calls for iommu secure page table (2017-03-28 16:03:21 -0500)
>
> ----------------------------------------------------------------
> Qualcomm ARM Based Driver Updates for v4.12
>
> * Add SCM APIs for restore_sec_cfg and iommu secure page table
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL] ARM/clk move ICST library to drivers/clk
From: Olof Johansson @ 2017-04-19 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdbPagc3fVyzryRYhcwnQ2WA-z7fSbW+VpR09iLqvVEhjQ@mail.gmail.com>
On Fri, Apr 07, 2017 at 12:03:16PM +0200, Linus Walleij wrote:
> Hi ARM SoC folks,
>
> this moves the ICST library from arch/arm to drivers/clk
> so it can be reused from there.
>
> The patches are ACKed by Stephen Boyd.
>
> Please pull it into some cleanup branch in ARM SoC.
>
> Yours,
> Linus Walleij
>
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator.git
> tags/arm-to-clk-icst
>
> for you to fetch changes up to ba3fae06c7a4e80ab9d48a8a045b352da97cf23d:
>
> ARM/clk: move the ICST library to drivers/clk (2017-04-07 11:58:12 +0200)
>
> ----------------------------------------------------------------
> This moves the ICST helper library from arch/arm to drivers/clk
We don't have a cleanup branch this release, so I merged this into
next/drivers.
Thanks!
-Olof
^ permalink raw reply
* [GIT PULL 1/5] i.MX driver changes for 4.12
From: Olof Johansson @ 2017-04-19 13:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491835076-1995-1-git-send-email-shawnguo@kernel.org>
On Mon, Apr 10, 2017 at 10:37:52PM +0800, Shawn Guo wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/imx-drivers-4.12
>
> for you to fetch changes up to 44c43c98213fb123819c67c128a5d6c9a9a12280:
>
> soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver (2017-04-07 20:47:34 +0800)
>
> ----------------------------------------------------------------
> i.MX drivers updates for 4.12:
> - A series from Lucas Stach which partly rewrites the imx gpc driver
> to support multiple power domains, and moves the related code from
> imx platform into drivers folder.
> - A series from Dong Aisheng which fixes the issues with Lucas' code
> changes and improves things.
> - Add workaround for i.MX6QP hardware erratum ERR009619 that is PRE
> clocks may be stalled during the power up sequencing of the PU power
> domain.
> - Add imx-gpcv2 driver to support power domains managed by GPCv2 IP
> block found on i.MX7 series of SoCs.
>
> ----------------------------------------------------------------
> Andrey Smirnov (2):
> dt-bindings: Add GPCv2 power gating driver
> soc: imx: Add GPCv2 power gating driver
>
> Dong Aisheng (8):
> soc: imx: gpc: fix gpc clk get error handling
> soc: imx: gpc: fix the wrong using of regmap cache
> soc: imx: gpc: fix domain_index sanity check issue
> soc: imx: gpc: fix imx6sl gpc power domain regression
> soc: imx: gpc: fix comment when power up domain
> soc: imx: gpc: keep PGC_X_CTRL name align with reference manual
> dt-bindings: imx-gpc: correct the DOMAIN_INDEX using
> soc: imx: gpc: remove unnecessary readable_reg callback
>
> Lucas Stach (5):
> dt-bindings: add multidomain support to i.MX GPC DT binding
> soc: imx: move PGC handling to a new GPC driver
> soc: imx: gpc: add defines for domain index
> dt-bindings: imx-gpc: add i.MX6 QuadPlus compatible
> soc: imx: gpc: add workaround for i.MX6QP to the GPC PD driver
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 1/2] ZTE driver updates for 4.12
From: Olof Johansson @ 2017-04-19 13:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491837665-2579-1-git-send-email-shawnguo@kernel.org>
On Mon, Apr 10, 2017 at 11:21:04PM +0800, Shawn Guo wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git tags/zte-drivers-4.12
>
> for you to fetch changes up to 71ce8430348f989d0c78871828d96e0e616056dd:
>
> soc: zte: pm_domains: Remove .owner field for driver (2017-03-08 12:40:44 +0100)
>
> ----------------------------------------------------------------
> ZTE driver updates for 4.12:
>
> It includes a couple of small cleanups on zx296718 power domain drivers.
Merged, thanks!
-Olof
^ permalink raw reply
* [GIT PULL] Qualcomm Device Tree Changes for v4.12
From: Olof Johansson @ 2017-04-19 13:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491533330-13570-1-git-send-email-andy.gross@linaro.org>
On Thu, Apr 06, 2017 at 09:48:50PM -0500, Andy Gross wrote:
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-dts-for-4.12
>
> for you to fetch changes up to 21677ecca20151e61c3290ef37c5cd7afec60a5a:
>
> Revert "ARM: dts: qcom: msm8974: Add USB gadget nodes" (2017-04-06 18:48:53 -0500)
>
> ----------------------------------------------------------------
> Qualcomm Device Tree Changes for v4.12
>
> * Add Coresight components for MSM8974
> * Fixup MSM8974 ADSP XO clk and add RPMCC node
> * Fix typo in APQ8060
> * Add SDCs on MSM8660
> * Revert MSM8974 USB gadget change due to issues
Merged, thanks. Should the USB gadget revert have been a fix for 4.11 instead?
-Olof
^ permalink raw reply
* [PATCH] ARM: dts: aspeed-g4: fix AHB window size of the SMC controllers
From: Cédric Le Goater @ 2017-04-19 13:43 UTC (permalink / raw)
To: linux-arm-kernel
The window of the Aspeed AST2400 SMC Controllers to map chips on the
AHB Bus has a 256MB size. The full window range is
[ 0x20000000 - 0x2FFFFFFF ] for the FMC controller
[ 0x30000000 - 0x3FFFFFFF ] for the SPI controller
This change requires CONFIG_VMSPLIT_2G to be set.
Signed-off-by: C?dric Le Goater <clg@kaod.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index 4e3f055b365c..a7b6e04d5f1b 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -26,7 +26,7 @@
fmc: flash-controller at 1e620000 {
reg = < 0x1e620000 0x94
- 0x20000000 0x02000000 >;
+ 0x20000000 0x10000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-fmc";
@@ -41,7 +41,7 @@
spi: flash-controller at 1e630000 {
reg = < 0x1e630000 0x18
- 0x30000000 0x02000000 >;
+ 0x30000000 0x10000000 >;
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2400-spi";
--
2.7.4
^ permalink raw reply related
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