* [PATCH 06/16] clocksource: arm_arch_timer: rework PPI selection
From: Mark Rutland @ 2017-04-19 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492620273-30037-1-git-send-email-mark.rutland@arm.com>
From: Fu Wei <fu.wei@linaro.org>
Currently, the arch timer driver uses ARCH_TIMER_PHYS_SECURE_PPI to mean
the driver will use the secure PPI *and* potentially also use the
non-secure PPI. This is somewhat confusing.
For arm64 it never makes sense to use the secure PPI, but we do anyway,
inheriting this behaviour from 32-bit arm. For ACPI, we may not even
have a valid secure PPI, so we need to be able to only request the
non-secure PPI.
To that end, this patch reworks the timer driver so that we can request
the non-secure PPI alone. The PPI selection is split out into a new
function, arch_timer_select_ppi(), and verification of the selected PPI
is shifted out to callers (as DT may select the PPI by other means and
must handle this anyway).
We now consistently use arch_timer_has_nonsecure_ppi() to determine
whether we must manage a non-secure PPI *in addition* to a secure PPI.
When we only have a non-secure PPI, this returns false.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
[Mark: reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clocksource/arm_arch_timer.c | 77 +++++++++++++++++++++---------------
1 file changed, 46 insertions(+), 31 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 15059c9..94de018 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -992,7 +992,7 @@ static int __init arch_timer_register(void)
case ARCH_TIMER_PHYS_NONSECURE_PPI:
err = request_percpu_irq(ppi, arch_timer_handler_phys,
"arch_timer", arch_timer_evt);
- if (!err && arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]) {
+ if (!err && arch_timer_has_nonsecure_ppi()) {
ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
err = request_percpu_irq(ppi, arch_timer_handler_phys,
"arch_timer", arch_timer_evt);
@@ -1114,39 +1114,41 @@ static int __init arch_timer_common_init(void)
return arch_timer_arch_init();
}
-static int __init arch_timer_init(void)
+/**
+ * arch_timer_select_ppi() - Select suitable PPI for the current system.
+ *
+ * If HYP mode is available, we know that the physical timer
+ * has been configured to be accessible from PL1. Use it, so
+ * that a guest can use the virtual timer instead.
+ *
+ * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
+ * accesses to CNTP_*_EL1 registers are silently redirected to
+ * their CNTHP_*_EL2 counterparts, and use a different PPI
+ * number.
+ *
+ * If no interrupt provided for virtual timer, we'll have to
+ * stick to the physical timer. It'd better be accessible...
+ * For arm64 we never use the secure interrupt.
+ *
+ * Return: a suitable PPI type for the current system.
+ */
+static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void)
{
- int ret;
- /*
- * If HYP mode is available, we know that the physical timer
- * has been configured to be accessible from PL1. Use it, so
- * that a guest can use the virtual timer instead.
- *
- * If no interrupt provided for virtual timer, we'll have to
- * stick to the physical timer. It'd better be accessible...
- *
- * On ARMv8.1 with VH extensions, the kernel runs in HYP. VHE
- * accesses to CNTP_*_EL1 registers are silently redirected to
- * their CNTHP_*_EL2 counterparts, and use a different PPI
- * number.
- */
- if (is_hyp_mode_available() || !arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) {
- bool has_ppi;
+ if (is_kernel_in_hyp_mode())
+ return ARCH_TIMER_HYP_PPI;
- if (is_kernel_in_hyp_mode()) {
- arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI;
- has_ppi = !!arch_timer_ppi[ARCH_TIMER_HYP_PPI];
- } else {
- arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
- has_ppi = (!!arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] ||
- !!arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
- }
+ if (!is_hyp_mode_available() && arch_timer_ppi[ARCH_TIMER_VIRT_PPI])
+ return ARCH_TIMER_VIRT_PPI;
- if (!has_ppi) {
- pr_warn("No interrupt available, giving up\n");
- return -EINVAL;
- }
- }
+ if (IS_ENABLED(CONFIG_ARM64))
+ return ARCH_TIMER_PHYS_NONSECURE_PPI;
+
+ return ARCH_TIMER_PHYS_SECURE_PPI;
+}
+
+static int __init arch_timer_init(void)
+{
+ int ret;
ret = arch_timer_register();
if (ret)
@@ -1188,6 +1190,13 @@ static int __init arch_timer_of_init(struct device_node *np)
if (IS_ENABLED(CONFIG_ARM) &&
of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
+ else
+ arch_timer_uses_ppi = arch_timer_select_ppi();
+
+ if (!arch_timer_ppi[arch_timer_uses_ppi]) {
+ pr_err("No interrupt available, giving up\n");
+ return -EINVAL;
+ }
/* On some systems, the counter stops ticking when in suspend. */
arch_counter_suspend_stop = of_property_read_bool(np,
@@ -1333,6 +1342,12 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
/* Get the frequency from CNTFRQ */
arch_timer_detect_rate(NULL, NULL);
+ arch_timer_uses_ppi = arch_timer_select_ppi();
+ if (!arch_timer_ppi[arch_timer_uses_ppi]) {
+ pr_err("No interrupt available, giving up\n");
+ return -EINVAL;
+ }
+
/* Always-on capability */
arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
--
1.9.1
^ permalink raw reply related
* [PATCH 05/16] clocksource: arm_arch_timer: add a new enum for spi type
From: Mark Rutland @ 2017-04-19 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492620273-30037-1-git-send-email-mark.rutland@arm.com>
From: Fu Wei <fu.wei@linaro.org>
This patch add a new enum "arch_timer_spi_nr" and use it in the driver.
Just for code's readability, no functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clocksource/arm_arch_timer.c | 4 ++--
include/clocksource/arm_arch_timer.h | 6 ++++++
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 04218c1..15059c9 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -1258,9 +1258,9 @@ static int __init arch_timer_mem_init(struct device_node *np)
}
if (arch_timer_mem_use_virtual)
- irq = irq_of_parse_and_map(best_frame, 1);
+ irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_VIRT_SPI);
else
- irq = irq_of_parse_and_map(best_frame, 0);
+ irq = irq_of_parse_and_map(best_frame, ARCH_TIMER_PHYS_SPI);
ret = -EINVAL;
if (!irq) {
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index b898637..4a98c06 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -46,6 +46,12 @@ enum arch_timer_ppi_nr {
ARCH_TIMER_MAX_TIMER_PPI
};
+enum arch_timer_spi_nr {
+ ARCH_TIMER_PHYS_SPI,
+ ARCH_TIMER_VIRT_SPI,
+ ARCH_TIMER_MAX_TIMER_SPI
+};
+
#define ARCH_TIMER_PHYS_ACCESS 0
#define ARCH_TIMER_VIRT_ACCESS 1
#define ARCH_TIMER_MEM_PHYS_ACCESS 2
--
1.9.1
^ permalink raw reply related
* [PATCH 04/16] clocksource: arm_arch_timer: move enums and defines to header file
From: Mark Rutland @ 2017-04-19 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492620273-30037-1-git-send-email-mark.rutland@arm.com>
From: Fu Wei <fu.wei@linaro.org>
To support the arm_arch_timer via ACPI we need to share defines and enums
between the driver and the ACPI parser code.
So we split out the relevant defines and enums into arm_arch_timer.h.
No functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clocksource/arm_arch_timer.c | 11 -----------
include/clocksource/arm_arch_timer.h | 12 ++++++++++++
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 94e355b..04218c1 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -55,8 +55,6 @@
#define CNTV_TVAL 0x38
#define CNTV_CTL 0x3c
-#define ARCH_TIMER_TYPE_CP15 BIT(0)
-#define ARCH_TIMER_TYPE_MEM BIT(1)
static unsigned arch_timers_present __initdata;
static void __iomem *arch_counter_base;
@@ -69,15 +67,6 @@ struct arch_timer {
#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
static u32 arch_timer_rate;
-
-enum arch_timer_ppi_nr {
- ARCH_TIMER_PHYS_SECURE_PPI,
- ARCH_TIMER_PHYS_NONSECURE_PPI,
- ARCH_TIMER_VIRT_PPI,
- ARCH_TIMER_HYP_PPI,
- ARCH_TIMER_MAX_TIMER_PPI
-};
-
static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
static struct clock_event_device __percpu *arch_timer_evt;
diff --git a/include/clocksource/arm_arch_timer.h b/include/clocksource/arm_arch_timer.h
index caedb74..b898637 100644
--- a/include/clocksource/arm_arch_timer.h
+++ b/include/clocksource/arm_arch_timer.h
@@ -16,9 +16,13 @@
#ifndef __CLKSOURCE_ARM_ARCH_TIMER_H
#define __CLKSOURCE_ARM_ARCH_TIMER_H
+#include <linux/bitops.h>
#include <linux/timecounter.h>
#include <linux/types.h>
+#define ARCH_TIMER_TYPE_CP15 BIT(0)
+#define ARCH_TIMER_TYPE_MEM BIT(1)
+
#define ARCH_TIMER_CTRL_ENABLE (1 << 0)
#define ARCH_TIMER_CTRL_IT_MASK (1 << 1)
#define ARCH_TIMER_CTRL_IT_STAT (1 << 2)
@@ -34,6 +38,14 @@ enum arch_timer_reg {
ARCH_TIMER_REG_TVAL,
};
+enum arch_timer_ppi_nr {
+ ARCH_TIMER_PHYS_SECURE_PPI,
+ ARCH_TIMER_PHYS_NONSECURE_PPI,
+ ARCH_TIMER_VIRT_PPI,
+ ARCH_TIMER_HYP_PPI,
+ ARCH_TIMER_MAX_TIMER_PPI
+};
+
#define ARCH_TIMER_PHYS_ACCESS 0
#define ARCH_TIMER_VIRT_ACCESS 1
#define ARCH_TIMER_MEM_PHYS_ACCESS 2
--
1.9.1
^ permalink raw reply related
* [PATCH 03/16] clocksource: arm_arch_timer: rename the PPI enum
From: Mark Rutland @ 2017-04-19 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492620273-30037-1-git-send-email-mark.rutland@arm.com>
From: Fu Wei <fu.wei@linaro.org>
In preparation for moving the PPI enum out into a header, rename the
enum and its constituent values these so they are namespaced w.r.t. the
arch timer. This will aid consistency and avoid potential name clashes
when this move occurs.
No functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
[Mark: reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clocksource/arm_arch_timer.c | 82 ++++++++++++++++++------------------
1 file changed, 42 insertions(+), 40 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 38bddb9..94e355b 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -70,19 +70,19 @@ struct arch_timer {
static u32 arch_timer_rate;
-enum ppi_nr {
- PHYS_SECURE_PPI,
- PHYS_NONSECURE_PPI,
- VIRT_PPI,
- HYP_PPI,
- MAX_TIMER_PPI
+enum arch_timer_ppi_nr {
+ ARCH_TIMER_PHYS_SECURE_PPI,
+ ARCH_TIMER_PHYS_NONSECURE_PPI,
+ ARCH_TIMER_VIRT_PPI,
+ ARCH_TIMER_HYP_PPI,
+ ARCH_TIMER_MAX_TIMER_PPI
};
-static int arch_timer_ppi[MAX_TIMER_PPI];
+static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI];
static struct clock_event_device __percpu *arch_timer_evt;
-static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI;
+static enum arch_timer_ppi_nr arch_timer_uses_ppi = ARCH_TIMER_VIRT_PPI;
static bool arch_timer_c3stop;
static bool arch_timer_mem_use_virtual;
static bool arch_counter_suspend_stop;
@@ -694,14 +694,14 @@ static void __arch_timer_setup(unsigned type,
clk->cpumask = cpumask_of(smp_processor_id());
clk->irq = arch_timer_ppi[arch_timer_uses_ppi];
switch (arch_timer_uses_ppi) {
- case VIRT_PPI:
+ case ARCH_TIMER_VIRT_PPI:
clk->set_state_shutdown = arch_timer_shutdown_virt;
clk->set_state_oneshot_stopped = arch_timer_shutdown_virt;
clk->set_next_event = arch_timer_set_next_event_virt;
break;
- case PHYS_SECURE_PPI:
- case PHYS_NONSECURE_PPI:
- case HYP_PPI:
+ case ARCH_TIMER_PHYS_SECURE_PPI:
+ case ARCH_TIMER_PHYS_NONSECURE_PPI:
+ case ARCH_TIMER_HYP_PPI:
clk->set_state_shutdown = arch_timer_shutdown_phys;
clk->set_state_oneshot_stopped = arch_timer_shutdown_phys;
clk->set_next_event = arch_timer_set_next_event_phys;
@@ -789,8 +789,8 @@ static void arch_counter_set_user_access(void)
static bool arch_timer_has_nonsecure_ppi(void)
{
- return (arch_timer_uses_ppi == PHYS_SECURE_PPI &&
- arch_timer_ppi[PHYS_NONSECURE_PPI]);
+ return (arch_timer_uses_ppi == ARCH_TIMER_PHYS_SECURE_PPI &&
+ arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
}
static u32 check_ppi_trigger(int irq)
@@ -817,8 +817,9 @@ static int arch_timer_starting_cpu(unsigned int cpu)
enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
if (arch_timer_has_nonsecure_ppi()) {
- flags = check_ppi_trigger(arch_timer_ppi[PHYS_NONSECURE_PPI]);
- enable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI], flags);
+ flags = check_ppi_trigger(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
+ enable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
+ flags);
}
arch_counter_set_user_access();
@@ -862,7 +863,7 @@ static void arch_timer_banner(unsigned type)
(unsigned long)arch_timer_rate / 1000000,
(unsigned long)(arch_timer_rate / 10000) % 100,
type & ARCH_TIMER_TYPE_CP15 ?
- (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
+ (arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI) ? "virt" : "phys" :
"",
type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
type & ARCH_TIMER_TYPE_MEM ?
@@ -901,7 +902,8 @@ static void __init arch_counter_register(unsigned type)
/* Register the CP15 based counter if we have one */
if (type & ARCH_TIMER_TYPE_CP15) {
- if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI)
+ if (IS_ENABLED(CONFIG_ARM64) ||
+ arch_timer_uses_ppi == ARCH_TIMER_VIRT_PPI)
arch_timer_read_counter = arch_counter_get_cntvct;
else
arch_timer_read_counter = arch_counter_get_cntpct;
@@ -930,7 +932,7 @@ static void arch_timer_stop(struct clock_event_device *clk)
disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
if (arch_timer_has_nonsecure_ppi())
- disable_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI]);
+ disable_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
clk->set_state_shutdown(clk);
}
@@ -993,24 +995,24 @@ static int __init arch_timer_register(void)
ppi = arch_timer_ppi[arch_timer_uses_ppi];
switch (arch_timer_uses_ppi) {
- case VIRT_PPI:
+ case ARCH_TIMER_VIRT_PPI:
err = request_percpu_irq(ppi, arch_timer_handler_virt,
"arch_timer", arch_timer_evt);
break;
- case PHYS_SECURE_PPI:
- case PHYS_NONSECURE_PPI:
+ case ARCH_TIMER_PHYS_SECURE_PPI:
+ case ARCH_TIMER_PHYS_NONSECURE_PPI:
err = request_percpu_irq(ppi, arch_timer_handler_phys,
"arch_timer", arch_timer_evt);
- if (!err && arch_timer_ppi[PHYS_NONSECURE_PPI]) {
- ppi = arch_timer_ppi[PHYS_NONSECURE_PPI];
+ if (!err && arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]) {
+ ppi = arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI];
err = request_percpu_irq(ppi, arch_timer_handler_phys,
"arch_timer", arch_timer_evt);
if (err)
- free_percpu_irq(arch_timer_ppi[PHYS_SECURE_PPI],
+ free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI],
arch_timer_evt);
}
break;
- case HYP_PPI:
+ case ARCH_TIMER_HYP_PPI:
err = request_percpu_irq(ppi, arch_timer_handler_phys,
"arch_timer", arch_timer_evt);
break;
@@ -1042,7 +1044,7 @@ static int __init arch_timer_register(void)
out_unreg_notify:
free_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], arch_timer_evt);
if (arch_timer_has_nonsecure_ppi())
- free_percpu_irq(arch_timer_ppi[PHYS_NONSECURE_PPI],
+ free_percpu_irq(arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI],
arch_timer_evt);
out_free:
@@ -1139,16 +1141,16 @@ static int __init arch_timer_init(void)
* their CNTHP_*_EL2 counterparts, and use a different PPI
* number.
*/
- if (is_hyp_mode_available() || !arch_timer_ppi[VIRT_PPI]) {
+ if (is_hyp_mode_available() || !arch_timer_ppi[ARCH_TIMER_VIRT_PPI]) {
bool has_ppi;
if (is_kernel_in_hyp_mode()) {
- arch_timer_uses_ppi = HYP_PPI;
- has_ppi = !!arch_timer_ppi[HYP_PPI];
+ arch_timer_uses_ppi = ARCH_TIMER_HYP_PPI;
+ has_ppi = !!arch_timer_ppi[ARCH_TIMER_HYP_PPI];
} else {
- arch_timer_uses_ppi = PHYS_SECURE_PPI;
- has_ppi = (!!arch_timer_ppi[PHYS_SECURE_PPI] ||
- !!arch_timer_ppi[PHYS_NONSECURE_PPI]);
+ arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
+ has_ppi = (!!arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] ||
+ !!arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI]);
}
if (!has_ppi) {
@@ -1165,7 +1167,7 @@ static int __init arch_timer_init(void)
if (ret)
return ret;
- arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
+ arch_timer_kvm_info.virtual_irq = arch_timer_ppi[ARCH_TIMER_VIRT_PPI];
return 0;
}
@@ -1180,7 +1182,7 @@ static int __init arch_timer_of_init(struct device_node *np)
}
arch_timers_present |= ARCH_TIMER_TYPE_CP15;
- for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
+ for (i = ARCH_TIMER_PHYS_SECURE_PPI; i < ARCH_TIMER_MAX_TIMER_PPI; i++)
arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
arch_timer_detect_rate(NULL, np);
@@ -1196,7 +1198,7 @@ static int __init arch_timer_of_init(struct device_node *np)
*/
if (IS_ENABLED(CONFIG_ARM) &&
of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
- arch_timer_uses_ppi = PHYS_SECURE_PPI;
+ arch_timer_uses_ppi = ARCH_TIMER_PHYS_SECURE_PPI;
/* On some systems, the counter stops ticking when in suspend. */
arch_counter_suspend_stop = of_property_read_bool(np,
@@ -1323,19 +1325,19 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
arch_timers_present |= ARCH_TIMER_TYPE_CP15;
- arch_timer_ppi[PHYS_SECURE_PPI] =
+ arch_timer_ppi[ARCH_TIMER_PHYS_SECURE_PPI] =
map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
gtdt->secure_el1_flags);
- arch_timer_ppi[PHYS_NONSECURE_PPI] =
+ arch_timer_ppi[ARCH_TIMER_PHYS_NONSECURE_PPI] =
map_generic_timer_interrupt(gtdt->non_secure_el1_interrupt,
gtdt->non_secure_el1_flags);
- arch_timer_ppi[VIRT_PPI] =
+ arch_timer_ppi[ARCH_TIMER_VIRT_PPI] =
map_generic_timer_interrupt(gtdt->virtual_timer_interrupt,
gtdt->virtual_timer_flags);
- arch_timer_ppi[HYP_PPI] =
+ arch_timer_ppi[ARCH_TIMER_HYP_PPI] =
map_generic_timer_interrupt(gtdt->non_secure_el2_interrupt,
gtdt->non_secure_el2_flags);
--
1.9.1
^ permalink raw reply related
* [PATCH 02/16] clocksource: arm_arch_timer: rename type macros
From: Mark Rutland @ 2017-04-19 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492620273-30037-1-git-send-email-mark.rutland@arm.com>
From: Fu Wei <fu.wei@linaro.org>
In preparation for moving the type macros out into a header, rename
these so they are namespaced w.r.t. the arch timer. We'll apply the same
prefix to other definitions in subsequent patches. This will aid
consistency and avoid potential name clahses when this move occurs.
No functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
[Mark: reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clocksource/arm_arch_timer.c | 43 +++++++++++++++++++-----------------
1 file changed, 23 insertions(+), 20 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 467ee61..38bddb9 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -55,8 +55,8 @@
#define CNTV_TVAL 0x38
#define CNTV_CTL 0x3c
-#define ARCH_CP15_TIMER BIT(0)
-#define ARCH_MEM_TIMER BIT(1)
+#define ARCH_TIMER_TYPE_CP15 BIT(0)
+#define ARCH_TIMER_TYPE_MEM BIT(1)
static unsigned arch_timers_present __initdata;
static void __iomem *arch_counter_base;
@@ -686,7 +686,7 @@ static void __arch_timer_setup(unsigned type,
{
clk->features = CLOCK_EVT_FEAT_ONESHOT;
- if (type == ARCH_CP15_TIMER) {
+ if (type == ARCH_TIMER_TYPE_CP15) {
if (arch_timer_c3stop)
clk->features |= CLOCK_EVT_FEAT_C3STOP;
clk->name = "arch_sys_timer";
@@ -811,7 +811,7 @@ static int arch_timer_starting_cpu(unsigned int cpu)
struct clock_event_device *clk = this_cpu_ptr(arch_timer_evt);
u32 flags;
- __arch_timer_setup(ARCH_CP15_TIMER, clk);
+ __arch_timer_setup(ARCH_TIMER_TYPE_CP15, clk);
flags = check_ppi_trigger(arch_timer_ppi[arch_timer_uses_ppi]);
enable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi], flags);
@@ -855,16 +855,17 @@ static int arch_timer_starting_cpu(unsigned int cpu)
static void arch_timer_banner(unsigned type)
{
pr_info("%s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
- type & ARCH_CP15_TIMER ? "cp15" : "",
- type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
- type & ARCH_MEM_TIMER ? "mmio" : "",
+ type & ARCH_TIMER_TYPE_CP15 ? "cp15" : "",
+ type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ?
+ " and " : "",
+ type & ARCH_TIMER_TYPE_MEM ? "mmio" : "",
(unsigned long)arch_timer_rate / 1000000,
(unsigned long)(arch_timer_rate / 10000) % 100,
- type & ARCH_CP15_TIMER ?
+ type & ARCH_TIMER_TYPE_CP15 ?
(arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
"",
- type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
- type & ARCH_MEM_TIMER ?
+ type == (ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM) ? "/" : "",
+ type & ARCH_TIMER_TYPE_MEM ?
arch_timer_mem_use_virtual ? "virt" : "phys" :
"");
}
@@ -899,7 +900,7 @@ static void __init arch_counter_register(unsigned type)
u64 start_count;
/* Register the CP15 based counter if we have one */
- if (type & ARCH_CP15_TIMER) {
+ if (type & ARCH_TIMER_TYPE_CP15) {
if (IS_ENABLED(CONFIG_ARM64) || arch_timer_uses_ppi == VIRT_PPI)
arch_timer_read_counter = arch_counter_get_cntvct;
else
@@ -1062,7 +1063,7 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
t->base = base;
t->evt.irq = irq;
- __arch_timer_setup(ARCH_MEM_TIMER, &t->evt);
+ __arch_timer_setup(ARCH_TIMER_TYPE_MEM, &t->evt);
if (arch_timer_mem_use_virtual)
func = arch_timer_handler_virt_mem;
@@ -1105,13 +1106,15 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
static int __init arch_timer_common_init(void)
{
- unsigned mask = ARCH_CP15_TIMER | ARCH_MEM_TIMER;
+ unsigned mask = ARCH_TIMER_TYPE_CP15 | ARCH_TIMER_TYPE_MEM;
/* Wait until both nodes are probed if we have two timers */
if ((arch_timers_present & mask) != mask) {
- if (arch_timer_needs_probing(ARCH_MEM_TIMER, arch_timer_mem_of_match))
+ if (arch_timer_needs_probing(ARCH_TIMER_TYPE_MEM,
+ arch_timer_mem_of_match))
return 0;
- if (arch_timer_needs_probing(ARCH_CP15_TIMER, arch_timer_of_match))
+ if (arch_timer_needs_probing(ARCH_TIMER_TYPE_CP15,
+ arch_timer_of_match))
return 0;
}
@@ -1171,12 +1174,12 @@ static int __init arch_timer_of_init(struct device_node *np)
{
int i;
- if (arch_timers_present & ARCH_CP15_TIMER) {
+ if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
pr_warn("multiple nodes in dt, skipping\n");
return 0;
}
- arch_timers_present |= ARCH_CP15_TIMER;
+ arch_timers_present |= ARCH_TIMER_TYPE_CP15;
for (i = PHYS_SECURE_PPI; i < MAX_TIMER_PPI; i++)
arch_timer_ppi[i] = irq_of_parse_and_map(np, i);
@@ -1211,7 +1214,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
unsigned int irq, ret = -EINVAL;
u32 cnttidr;
- arch_timers_present |= ARCH_MEM_TIMER;
+ arch_timers_present |= ARCH_TIMER_TYPE_MEM;
cntctlbase = of_iomap(np, 0);
if (!cntctlbase) {
pr_err("Can't find CNTCTLBase\n");
@@ -1311,14 +1314,14 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
{
struct acpi_table_gtdt *gtdt;
- if (arch_timers_present & ARCH_CP15_TIMER) {
+ if (arch_timers_present & ARCH_TIMER_TYPE_CP15) {
pr_warn("already initialized, skipping\n");
return -EINVAL;
}
gtdt = container_of(table, struct acpi_table_gtdt, header);
- arch_timers_present |= ARCH_CP15_TIMER;
+ arch_timers_present |= ARCH_TIMER_TYPE_CP15;
arch_timer_ppi[PHYS_SECURE_PPI] =
map_generic_timer_interrupt(gtdt->secure_el1_interrupt,
--
1.9.1
^ permalink raw reply related
* [PATCH 01/16] clocksource: arm_arch_timer: clean up printk usage
From: Mark Rutland @ 2017-04-19 16:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492620273-30037-1-git-send-email-mark.rutland@arm.com>
From: Fu Wei <fu.wei@linaro.org>
Almost all string in the arm_arch_timer driver duplicate an common
prefix (though a few do not). For consistency, it would be better to use
pr_fmt(), and always use this prefix. At the same time, we may as well
clean up some whitespace issues in arch_timer_banner and
arch_timer_init.
No functional change.
Signed-off-by: Fu Wei <fu.wei@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
[Mark: reword commit message]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
---
drivers/clocksource/arm_arch_timer.c | 49 ++++++++++++++++++------------------
1 file changed, 25 insertions(+), 24 deletions(-)
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index bf9e9d7..467ee61 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -33,6 +33,9 @@
#include <clocksource/arm_arch_timer.h>
+#undef pr_fmt
+#define pr_fmt(fmt) "arch_timer: " fmt
+
#define CNTTIDR 0x08
#define CNTTIDR_VIRT(n) (BIT(1) << ((n) * 4))
@@ -846,22 +849,22 @@ static int arch_timer_starting_cpu(unsigned int cpu)
/* Check the timer frequency. */
if (arch_timer_rate == 0)
- pr_warn("Architected timer frequency not available\n");
+ pr_warn("frequency not available\n");
}
static void arch_timer_banner(unsigned type)
{
- pr_info("Architected %s%s%s timer(s) running at %lu.%02luMHz (%s%s%s).\n",
- type & ARCH_CP15_TIMER ? "cp15" : "",
- type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
- type & ARCH_MEM_TIMER ? "mmio" : "",
- (unsigned long)arch_timer_rate / 1000000,
- (unsigned long)(arch_timer_rate / 10000) % 100,
- type & ARCH_CP15_TIMER ?
- (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
+ pr_info("%s%s%s timer(s) running@%lu.%02luMHz (%s%s%s).\n",
+ type & ARCH_CP15_TIMER ? "cp15" : "",
+ type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? " and " : "",
+ type & ARCH_MEM_TIMER ? "mmio" : "",
+ (unsigned long)arch_timer_rate / 1000000,
+ (unsigned long)(arch_timer_rate / 10000) % 100,
+ type & ARCH_CP15_TIMER ?
+ (arch_timer_uses_ppi == VIRT_PPI) ? "virt" : "phys" :
"",
- type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
- type & ARCH_MEM_TIMER ?
+ type == (ARCH_CP15_TIMER | ARCH_MEM_TIMER) ? "/" : "",
+ type & ARCH_MEM_TIMER ?
arch_timer_mem_use_virtual ? "virt" : "phys" :
"");
}
@@ -922,8 +925,7 @@ static void __init arch_counter_register(unsigned type)
static void arch_timer_stop(struct clock_event_device *clk)
{
- pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
- clk->irq, smp_processor_id());
+ pr_debug("disable IRQ%d cpu #%d\n", clk->irq, smp_processor_id());
disable_percpu_irq(arch_timer_ppi[arch_timer_uses_ppi]);
if (arch_timer_has_nonsecure_ppi())
@@ -1016,8 +1018,7 @@ static int __init arch_timer_register(void)
}
if (err) {
- pr_err("arch_timer: can't register interrupt %d (%d)\n",
- ppi, err);
+ pr_err("can't register interrupt %d (%d)\n", ppi, err);
goto out_free;
}
@@ -1070,7 +1071,7 @@ static int __init arch_timer_mem_register(void __iomem *base, unsigned int irq)
ret = request_irq(irq, func, IRQF_TIMER, "arch_mem_timer", &t->evt);
if (ret) {
- pr_err("arch_timer: Failed to request mem timer irq\n");
+ pr_err("Failed to request mem timer irq\n");
kfree(t);
}
@@ -1148,7 +1149,7 @@ static int __init arch_timer_init(void)
}
if (!has_ppi) {
- pr_warn("arch_timer: No interrupt available, giving up\n");
+ pr_warn("No interrupt available, giving up\n");
return -EINVAL;
}
}
@@ -1162,7 +1163,7 @@ static int __init arch_timer_init(void)
return ret;
arch_timer_kvm_info.virtual_irq = arch_timer_ppi[VIRT_PPI];
-
+
return 0;
}
@@ -1171,7 +1172,7 @@ static int __init arch_timer_of_init(struct device_node *np)
int i;
if (arch_timers_present & ARCH_CP15_TIMER) {
- pr_warn("arch_timer: multiple nodes in dt, skipping\n");
+ pr_warn("multiple nodes in dt, skipping\n");
return 0;
}
@@ -1213,7 +1214,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
arch_timers_present |= ARCH_MEM_TIMER;
cntctlbase = of_iomap(np, 0);
if (!cntctlbase) {
- pr_err("arch_timer: Can't find CNTCTLBase\n");
+ pr_err("Can't find CNTCTLBase\n");
return -ENXIO;
}
@@ -1228,7 +1229,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
u32 cntacr;
if (of_property_read_u32(frame, "frame-number", &n)) {
- pr_err("arch_timer: Missing frame-number\n");
+ pr_err("Missing frame-number\n");
of_node_put(frame);
goto out;
}
@@ -1258,7 +1259,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
base = arch_counter_base = of_io_request_and_map(best_frame, 0,
"arch_mem_timer");
if (IS_ERR(base)) {
- pr_err("arch_timer: Can't map frame's registers\n");
+ pr_err("Can't map frame's registers\n");
goto out;
}
@@ -1269,7 +1270,7 @@ static int __init arch_timer_mem_init(struct device_node *np)
ret = -EINVAL;
if (!irq) {
- pr_err("arch_timer: Frame missing %s irq",
+ pr_err("Frame missing %s irq.\n",
arch_timer_mem_use_virtual ? "virt" : "phys");
goto out;
}
@@ -1311,7 +1312,7 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
struct acpi_table_gtdt *gtdt;
if (arch_timers_present & ARCH_CP15_TIMER) {
- pr_warn("arch_timer: already initialized, skipping\n");
+ pr_warn("already initialized, skipping\n");
return -EINVAL;
}
--
1.9.1
^ permalink raw reply related
* [GIT PULL 00/16] clocksource: arm_arch_timer: GTDT-based MMIO timer support
From: Mark Rutland @ 2017-04-19 16:44 UTC (permalink / raw)
To: linux-arm-kernel
Hi Daniel,
The series enables support for the MMIO architected timers (useful for
system-level idle), which need to be probed via the GTDT when using ACPI.
I realise this is a little late, but I would very much appreciate if you could
pull these arch timer GTDT patches for v4.12. The series has been largely fine
for a while now, and the major hold-ups were edge cases in error handling which
have now been addressed.
The bulk of the series is a refactoring to cleanly separate the core driver, DT
probe path, and ACPI probe path. The final patch of the series adds GTDT-based
probing of the SBSA watchdog, using the new GTDT probing infrastructure. I've
tested the patches on arm and arm64 platforms.
The ACPI parts have all been appropriately acked, and it's preferred that these
all go through the clocksource tree.
The series is based on Marc's arch-timer-errata tag, which is alread in
tip/timers/core.
Thanks,
Mark.
The following changes since commit d003d029cea8a28139b4f9b88a36b8fac864f45b:
arm64: arch_timer: Add HISILICON_ERRATUM_161010101 ACPI matching data (2017-04-07 11:22:10 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mark/linux.git tags/arch-timer-gtdt
for you to fetch changes up to ca9ae5ec4ef0ed13833b03297ab319676965492c:
acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver (2017-04-19 17:00:15 +0100)
----------------------------------------------------------------
arch timer GTDT patches
- arch_timer cleanups and refactoring
- new common GTDT parser
- GTDT-based MMIO arch_timer support
- GTDT-based SBSA watchdog support
----------------------------------------------------------------
Fu Wei (16):
clocksource: arm_arch_timer: clean up printk usage
clocksource: arm_arch_timer: rename type macros
clocksource: arm_arch_timer: rename the PPI enum
clocksource: arm_arch_timer: move enums and defines to header file
clocksource: arm_arch_timer: add a new enum for spi type
clocksource: arm_arch_timer: rework PPI selection
clocksource: arm_arch_timer: split dt-only rate handling
clocksource: arm_arch_timer: refactor arch_timer_needs_probing
clocksource: arm_arch_timer: move arch_timer_needs_of_probing into DT init call
clocksource: arm_arch_timer: add structs to describe MMIO timer
clocksource: arm_arch_timer: split MMIO timer probing.
acpi/arm64: Add GTDT table parse driver
clocksource: arm_arch_timer: simplify ACPI support code.
acpi/arm64: Add memory-mapped timer support in GTDT driver
clocksource: arm_arch_timer: add GTDT support for memory-mapped timer
acpi/arm64: Add SBSA Generic Watchdog support in GTDT driver
arch/arm64/Kconfig | 1 +
drivers/acpi/arm64/Kconfig | 3 +
drivers/acpi/arm64/Makefile | 1 +
drivers/acpi/arm64/gtdt.c | 417 +++++++++++++++++++++++++
drivers/clocksource/arm_arch_timer.c | 573 +++++++++++++++++++++++------------
include/clocksource/arm_arch_timer.h | 34 +++
include/linux/acpi.h | 7 +
7 files changed, 834 insertions(+), 202 deletions(-)
create mode 100644 drivers/acpi/arm64/gtdt.c
^ permalink raw reply
* [PATCH] ARM: dts: BCM5301X: Specify MDIO bus in the DT
From: Florian Fainelli @ 2017-04-19 16:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c3a0455a-821f-d8a8-bf8a-7ad06ad0466e@milecki.pl>
On 04/02/2017 02:25 PM, Rafa? Mi?ecki wrote:
> On 04/02/2017 11:14 PM, Florian Fainelli wrote:
>> Le 04/02/17 ? 14:08, Rafa? Mi?ecki a ?crit :
>>> From: Rafa? Mi?ecki <rafal@milecki.pl>
>>>
>>> Northstar devices have MDIO bus that may contain various PHYs attached.
>>> A common example is USB 3.0 PHY (that doesn't have an MDIO driver yet).
>>>
>>> Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
>>> ---
>>> arch/arm/boot/dts/bcm5301x.dtsi | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/bcm5301x.dtsi
>>> b/arch/arm/boot/dts/bcm5301x.dtsi
>>> index acee36a61004..6a2afe7880ae 100644
>>> --- a/arch/arm/boot/dts/bcm5301x.dtsi
>>> +++ b/arch/arm/boot/dts/bcm5301x.dtsi
>>> @@ -320,6 +320,13 @@
>>> };
>>> };
>>>
>>> + mdio at 18003000 {
>>> + compatible = "brcm,iproc-mdio";
>>> + reg = <0x18003000 0x8>;
>>> + #size-cells = <1>;
>>> + #address-cells = <0>;
>>> + };
>>
>> This looks fine, but usually the block should be enabled on a per-board
>> basis, such that there should be a status = "disabled" property here by
>> default.
>
> I think we have few blocks in bcm5301x.dtsi enabled by default. I guess
> it's
> for stuff that is always present on every SoC family board: rng, nand,
> spi to
> name few.
>
> It makes some sense, consider e.g. spi. Every Northstar board has SPI
> controller so it's enabled by default. Not every board has SPI flash, so
> it's
> disabled by default.
>
> It's there and it make sense to me. Is that OK or not?
Even though there are devices that are always enabled on a given SoC,
because the board designs are always consistent does not necessarily
make them good candidates to be enabled at the .dtsi level. This is
particularly true when there are external connections to blocks (SPI,
NAND, USB, Ethernet, MDIO to name a few), having them disabled by
default is safer as a starting point to begin with.
>
> I find MDIO situation quite simiar. It seems every Northstar board has
> MDIO bus
> just devices may differ and should not be enabled by default.
In which case, the only difference, for you would be to do to, at the
board-level DTS:
&mdio {
status = "okay";
phy at 0 {
reg = <0>;
...
};
};
versus:
&mdio {
phy at 0 {
reg = <0>;
...
};
};
I think we can afford putting the mdio node's status property in each
board-level DTS and make it clear that way that it is enabled because
there are child nodes enabled?
NB: with a CONFIG_OF system, there is no automatic probing of MDIO child
devices because it relies on child nodes being declared, but you would
still get the driver to be probed and enabled, which is a waste of
resources at best.
Thanks
--
Florian
^ permalink raw reply
* [GIT PULL] bcm2835-dt-next-2017-03-30
From: Florian Fainelli @ 2017-04-19 16:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170330191343.31647-1-eric@anholt.net>
On 03/30/2017 12:13 PM, Eric Anholt wrote:
> Hi Florian,
>
> Here's the pull request for those changes I'd misplaced from 4.11.
> This may be my last PR of the cycle. The only change I have left on
> my radar for 4.12 is
> http://lists.infradead.org/pipermail/linux-rpi-kernel/2017-March/006097.html
>
> The following changes since commit 7f31a955a0c34de0463f7ff50b2bd62a5cce4204:
>
> ARM: dts: bcm2835: add sdhost controller to devicetree (2017-03-17 17:35:50 -0700)
>
> are available in the git repository at:
>
> git://github.com/anholt/linux tags/bcm2835-dt-next-2017-03-30
>
> for you to fetch changes up to 10b6c0c2e2bb8cd1be682f8d36ef597e3419cb88:
>
> ARM: dts: bcm2835: add index to the ethernet alias (2017-03-27 10:10:39 -0700)
>
> ----------------------------------------------------------------
> This pull request brings back bcm2835 DT fixups from Baruch Siach that
> got misplaced after a PR for 4.11 got rejected.
>
> ----------------------------------------------------------------
Merged into devicetree/next, thanks Eric.
--
Florian
^ permalink raw reply
* [PATCH v2 7/7] clk: spear: fix ADC clock definition on SPEAr600
From: Stephen Boyd @ 2017-04-19 16:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492433205-13376-8-git-send-email-thomas.petazzoni@free-electrons.com>
On 04/17, Thomas Petazzoni wrote:
> There is no SPEAr600 device named "adc". Instead, the description of the
> ADC was recently added to the Device Tree, and the device name is
> "d820b000.adc", so we should associate the ADC gatable clock to this
> device name.
>
> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v2 1/2] clk: imx7d: fix USDHC NAND clock
From: Stefan Agner @ 2017-04-19 16:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170419161435.GA7065@codeaurora.org>
On 2017-04-19 09:14, Stephen Boyd wrote:
> On 04/10, Stefan Agner wrote:
>> The USDHC NAND root clock is not gated by any CCM clock gate. Remove
>> the bogus gate definition.
>>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>> ---
>
> Can this be applied? It's followed by a dtsi change and there is
> zero information about if the two depend on each other. Please
> add cover letters for these sorts of things in the future
> indicating how you expect merging to work.
This can be merged. The two changes are independent.
They look kind of dependent, but really aren't since
IMX7D_NAND_USDHC_BUS_ROOT_CLK is still in the init_on list. Should have
explicitly mentioned that, sorry about that.
--
Stefan
^ permalink raw reply
* [PATCH v2 1/2] clk: imx7d: fix USDHC NAND clock
From: Stephen Boyd @ 2017-04-19 16:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170410210015.1620-1-stefan@agner.ch>
On 04/10, Stefan Agner wrote:
> The USDHC NAND root clock is not gated by any CCM clock gate. Remove
> the bogus gate definition.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
Can this be applied? It's followed by a dtsi change and there is
zero information about if the two depend on each other. Please
add cover letters for these sorts of things in the future
indicating how you expect merging to work.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 2/2] clk: imx7d: add the missing ipg_root_clk
From: Stephen Boyd @ 2017-04-19 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491878269-9559-2-git-send-email-aisheng.dong@nxp.com>
On 04/11, Dong Aisheng wrote:
> Add the missing ipg_root_clk which actually is already used by many
> orphan clks in current tree.
>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 1/2] clk: clk-imx7d: fix ahb clk definition
From: Stephen Boyd @ 2017-04-19 16:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1491878269-9559-1-git-send-email-aisheng.dong@nxp.com>
On 04/11, Dong Aisheng wrote:
> MX7D ahb clk actually has no LPCG gate, current LPCG offset 0x4200
> used actually is for adc, not ahb. After fix, correct ocram_s_clk
> parent accordingly as well.
>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Stefan Agner <stefan@agner.ch>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [GIT PULL] Allwinner clock fixes for 4.11, bis
From: Stephen Boyd @ 2017-04-19 16:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170410182431.GI7065@codeaurora.org>
On 04/10, Stephen Boyd wrote:
> On 04/10, Maxime Ripard wrote:
> > On Thu, Apr 06, 2017 at 04:10:03PM -0700, Stephen Boyd wrote:
> > > On 04/06, Maxime Ripard wrote:
> > > > Hi Mike, Stephen,
> > > >
> > > > Please pull the following changes for one of the 4.11-rc's
> > > >
> > > > Thanks!
> > > > Maxime
> > > >
> > > > The following changes since commit b467e08a15563dede0d37d3233baa24fb97a7310:
> > > >
> > > > clk: sunxi-ng: fix recalc_rate formula of NKMP clocks (2017-03-20 10:34:05 +0100)
> > > >
> > > > are available in the git repository at:
> > > >
> > > > https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git tags/sunxi-clk-fixes-for-4.11-2
> > > >
> > > > for you to fetch changes up to d054a839a0986136374d49f9f9fbc264abae9c4c:
> > > >
> > > > clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER (2017-03-27 13:37:05 +0200)
> > > >
> > > > ----------------------------------------------------------------
> > > > Allwinner clock fixes for 4.11, bis
> > > >
> > > > A few patches to fix a build error and a few minor typos and bugs in the
> > > > sunxi-ng code
> > > >
> > > > ----------------------------------------------------------------
> > > > Chen-Yu Tsai (3):
> > > > clk: sunxi-ng: use 1 as fallback for minimum multiplier
> > > > clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum mismatch
> > > > clk: sunxi-ng: a80: Fix audio PLL comment not matching actual code
> > > >
> > > > Tobias Regnery (1):
> > > > clk: sunxi-ng: fix build error without CONFIG_RESET_CONTROLLER
> > > >
> > >
> > > Two of these are fixes for regressions in v4.10? Why are these
> > > critical for the v4.11 release? The comment patch is totally
> > > bogus, it's not fixing any sort of regression that is causing
> > > problems for people so I'm not sure why it was put into this pull
> > > request. Am I right in assuming that the only real patch we need
> > > out of here is the last one for the build error from randconfigs?
> > > If so I can cherry-pick that from the branch into fixes and the
> > > rest can go the next merge window.
> > >
> > > Not pulling for now.
> >
> > Actually, all of them but the comment fix are real fix.
> >
> > "clk: sunxi-ng: use 1 as fallback for minimum multiplier" can lead to
> > a multiplier set to 0 in some cases (depending on the rate asked for),
> > and "clk: sunxi-ng: Fix round_rate/set_rate multiplier minimum
> > mismatch" will prevent inconsistensies in factors selection between
> > round_rate and set_rate.
> >
> > So, yes, they are not critical fixes in the sense that it will fix a
> > panic. but still those are bugs.
>
> Ok so it sounds like we agree that this can all wait until v4.12.
>
Will you resend the few patches in here that aren't in the redone
PR for fixes or the PR for v4.12?
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [GIT PULL] Allwinner clock changes for 4.12
From: Stephen Boyd @ 2017-04-19 16:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170406081001.kjyrisz4f5cdy4a7@lukather>
On 04/06, Maxime Ripard wrote:
> Hi Mike, Stephen,
>
> Here is our usual patches for the next merge window.
>
> Thanks!
> Maxime
>
> The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
>
> Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git tags/sunxi-clk-for-4.12
>
> for you to fetch changes up to cb545960dea2749771c88b0cb26e5adfd12a0315:
>
> clk: sunxi-ng: Display index when clock registration fails (2017-04-06 09:10:30 +0200)
>
Pulled into clk-next.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH V2] clk: hi6220: Add the hi655x's pmic clock
From: Stephen Boyd @ 2017-04-19 16:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170416205713.GW2078@mai>
On 04/16, Daniel Lezcano wrote:
> On Wed, Apr 12, 2017 at 08:02:45AM -0700, Stephen Boyd wrote:
> > On 04/08, Daniel Lezcano wrote:
>
> > > + struct hi655x_clk *hi655x_clk;
> > > + const char *clk_name = "hi655x-clk";
> > > + int ret;
> > > +
> > > + hi655x_clk = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk), GFP_KERNEL);
> > > + if (!hi655x_clk)
> > > + return -ENOMEM;
> > > +
> > > + hi655x_clk_init = devm_kzalloc(&pdev->dev, sizeof(*hi655x_clk_init),
> > > + GFP_KERNEL);
> > > + if (!hi655x_clk_init)
> > > + return -ENOMEM;
> > > +
> > > + of_property_read_string_index(parent->of_node, "clock-output-names",
> > > + 0, &clk_name);
> > > +
> > > + hi655x_clk_init->name = clk_name;
> > > + hi655x_clk_init->ops = &hi655x_clk_ops;
> > > +
> > > + hi655x_clk->clk_hw.init = hi655x_clk_init;
> > > + hi655x_clk->hi655x = hi655x;
> > > +
> > > + platform_set_drvdata(pdev, hi655x_clk);
> > > +
> > > + ret = devm_clk_hw_register(&pdev->dev, &hi655x_clk->clk_hw);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + ret = of_clk_add_hw_provider(parent->of_node, of_clk_hw_simple_get,
> > > + &hi655x_clk->clk_hw);
> > > + if (ret)
> > > + return ret;
> > > +
> > > + ret = clk_hw_register_clkdev(&hi655x_clk->clk_hw, clk_name, NULL);
> >
> > Missed this last time. Do you use this clkdev lookup? The name is
> > usually supposed to be based on what the device is expecting,
> > instead of clk_name, and we would want some device name for the
> > third argument here.
>
> I'm not sure to get your comment. Are you saying the clk_name should be the
> third argument?
>
>
Sorry, no. I meant that con_id is typically something like "core"
or "ahb" or something like that, and dev_id is something like
"a456002.pmic_device" or whatever dev_name(pmic_dev) would return for
the consuming device. That way when we call clk_get(dev, "core")
it will find the lookup with "core" and "a456002.pmic_device" to
match up the clk lookup.
If anything, the clk_name should just go into the con_id for now,
and then it will need to be a globally unique identifier for the
clk. But that is going against how clkdev is supposed to be used.
Hence the question if you even need to use it. If not, just don't
add it. I can fix up v3 of this patch to put clk_name back at
con_id if you like. No need to resend.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* LDM/STM alignment fixups on arm64
From: Catalin Marinas @ 2017-04-19 15:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <58F75D02.1030104@codeaurora.org>
On Wed, Apr 19, 2017 at 06:20:10PM +0530, Srinivas Ramana wrote:
> On 04/19/2017 03:28 PM, Russell King - ARM Linux wrote:
> >On Wed, Apr 19, 2017 at 12:03:58PM +0530, Srinivas Ramana wrote:
> >>While understanding how the alignment are handled on arm and arm64, we came
> >>across the fixups for LDM/LDRD/STM on arm where as these fixups are not
> >>present on arm64.
> >>
> >>There may be some specific reason why these fixups are not ported to arm64.
> >>Can you please help us understand this?
> >>
> >>With this difference in how kernel handles 32-bit apps on arm and arm64,
> >>there can be apps which are working without abort on arm, but fail on arm64
> >>(SIGBUS). We have tried to get some history on web, but not successful.
> >>
> >>If this is indeed missing on arm64, do you see any issue if its ported (does
> >>it fail any guidance)?
> >
> >Do you have an application that fails because of this? Your email makes
> >it sound very theoretical.
>
> I don't have any application with me right now. But i just tried passing an
> intentional misaligned address in a test program. When i say intentional,
> please note this code is buggy and should be fixed.
>
> So, my question is when arm has such fixups to handle such cases and do
> gracefully, is there any reason why those fixups are not ported to arm64?
As Russell said, until we find some application in the wild I wouldn't
rush to provide such emulation. Such code is either broken or relying on
undefined C behaviour so they should rather be fixed. As with the
deprecated/obsolete ARMv7 instructions (SWP, CP15 barriers), we
initially decided not to implement the emulation in the arm64 kernel,
though we eventually accepted it. But in those cases the instructions
were once real and used correctly. The unaligned LDM/STM or LDRD/STRD
have never been supported by the ARM architecture. They were added to
cope with some unaligned accesses in the Linux kernel network stack (in
hindsight, they should have not been provided to user but maybe there
were good reasons, I don't know the full history here).
> Again, I do agree that apps has to fix these instances, but we do have
> fixups in arch/arm.
I also think the default on arch/arm should be SIGBUS for these
instructions on ARMv7 but this was discussed before on the list.
> I do see that the compiler can detect (if its not intentionally induced)
> such cases and avoiding to generate LDM/STM and generates multiple LDR/STR.
> So, I just want to know if it is safe to assume that the compiler would take
> care of all such misaligned addresses passed to LDM/STM?
The compiler won't detect if you break its alignment assumptions (i.e.
in your example pointers to struct locat are 64-bit aligned as per the
EABI/PCS). If you want the compiler to assume unaligned struct pointers,
you'd have to mark the structure with the packed attribute (with the
additional padding if necessary, not in your example though).
--
Catalin
^ permalink raw reply
* [PATCH v24 09/11] acpi/arm64: Add memory-mapped timer support in GTDT driver
From: Lorenzo Pieralisi @ 2017-04-19 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170419154554.GJ27829@leverpostej>
On Wed, Apr 19, 2017 at 04:45:54PM +0100, Mark Rutland wrote:
> On Wed, Apr 19, 2017 at 04:07:25PM +0100, Mark Rutland wrote:
> > On Tue, Apr 18, 2017 at 06:21:07PM +0100, Lorenzo Pieralisi wrote:
> > > On Sat, Apr 15, 2017 at 02:40:12AM +0800, fu.wei at linaro.org wrote:
>
> > > If yes, why can't it simply be written like this ?
> > >
> > > for (; i >= 0; i--, gtdt_frame--) {
> > > frame = &timer_mem->frame[gtdt_frame->frame_number];
> > >
> > > /* not sure this check is actually needed */
> > > if (gtdt_frame->common_flags & ACPI_GTDT_GT_IS_SECURE_TIMER)
> > > continue;
> > >
> > > if (frame->phys_irq > 0)
> > > acpi_unregister_gsi(gtdt_frame->timer_interrupt);
> > > if (frame->virt_irq > 0)
> > > acpi_unregister_gsi(gtdt_frame->virtual_timer_interrupt);
> > > }
> >
> > A reverse loop of this form will work.
> >
> > That requires some restructuring, and care to avoid going out of bounds
> > instantaneously with the gtdt_frame--, so as to not invoke nasal demons.
> >
> > I've attacked this locally, and will send this out after testing. I'll
> > drop the new ACPI API patch.
>
> FWIW, I've set this up so the cleanup path is:
>
> do {
> if (gtdt_frame->common_flags & ACPI_GTDT_GT_IS_SECURE_TIMER ||
> gtdt_frame->frame_number >= ARCH_TIMER_MEM_MAX_FRAMES)
> continue;
>
> frame = &timer_mem->frame[gtdt_frame->frame_number];
>
> if (frame->phys_irq > 0)
> acpi_unregister_gsi(gtdt_frame->timer_interrupt);
> frame->phys_irq = 0;
>
> if (frame->virt_irq > 0)
> acpi_unregister_gsi(gtdt_frame->virtual_timer_interrupt);
> frame->virt_irq = 0;
> } while (i-- >= 0 && gtdt_frame--);
>
> ... the zeroing is to account for duplicate frames, which I now check for in
> the probe path (as we do for DT).
>
> Can I take it per your comment on the prior version that with this change I can
> take your ack?
Yes, thanks for fixing it up, please add my:
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> I also assume that you're happy for all of the drivers/acpi/arm64/ patches in the
> series to go via the clocksource tree?
Yes that's how I expect them to go upstream, that's the simplest way.
Thanks !
Lorenzo
^ permalink raw reply
* [PATCH 4/5] Hot-remove implementation for arm64
From: Laura Abbott @ 2017-04-19 15:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu9YYoFmFwpVgrOvD+eMHAKPmG_zgTz5f7JMT6iGqgLHGw@mail.gmail.com>
On 04/18/2017 11:48 AM, Ard Biesheuvel wrote:
> On 18 April 2017 at 19:21, Mark Rutland <mark.rutland@arm.com> wrote:
>> On Fri, Apr 14, 2017 at 03:01:58PM +0100, Andrea Reale wrote:
>>> I guess it is likely that I might have made assumptions that are true
>>> for x86_64 but do not hold for arm64. Whenever you feel this is the
>>> case, I would be really grateful if you could help identify them.
>>
>> Sure thing.
>>
>>> On Tue, Apr 11, 2017 at 06:12:11PM +0100, Mark Rutland wrote:
>>>> On Tue, Apr 11, 2017 at 03:55:42PM +0100, Andrea Reale wrote:
>>
>>>>> +static void free_pagetable(struct page *page, int order, bool direct)
>>>>
>>>> This "direct" parameter needs a better name, and a description in a
>>>> comment block above this function.
>>>
>>> The name direct is inherited directly from the x86_64 hot remove code.
>>> It serves to distinguish if we are removing either a pagetable page that
>>> is mapping to the direct mapping space (I think it is called also linear
>>> mapping area somewhere else) or a pagetable page or a data page
>>> from vmemmap.
>>
>> FWIW, I've largely heard the folk call that the "linear mapping", and
>> x86 folk call that the "direct mapping". The two are interchangeable.
>>
>>> In this specific set of functions, the flag is needed because the various
>>> alloc_init_p*d used for allocating entries for direct memory mapping
>>> rely on pgd_pgtable_alloc, which in its turn calls pgtable_page_ctor;
>>> hence, we need to call the dtor.
>>
>> AFAICT, that's not true for the arm64 linear map, since that's created
>> with our early_pgtable_alloc(), which doesn't call pgtable_page_ctor().
>>
>> Judging by commit:
>>
>> 1378dc3d4ba07ccd ("arm64: mm: run pgtable_page_ctor() on non-swapper
>> translation table pages")
>>
>> ... we only do this for non-swapper page tables.
>>
>>> On the contrary, vmemmap entries are created using vmemmap_alloc_block
>>> (from within vmemmap_populate), which does not call pgtable_page_ctor
>>> when allocating pages.
>>>
>>> I am not sure I understand why the pgtable_page_ctor is not called when
>>> allocating vmemmap page tables, but that's the current situation.
>>
>> From a quick scan, I see that it's necessary to use pgtable_page_ctor()
>> for pages that will be used for userspace page tables, but it's not
>> clear to me if it's ever necessary for pages used for kernel page
>> tables.
>>
>> If it is, we appear to have a bug on arm64.
>>
>> Laura, Ard, thoughts?
>>
>
> The generic apply_to_page_range() will expect the PTE lock to be
> initialized for page table pages that are not part of init_mm. For
> arm64, that is precisely efi_mm as far as I am aware. For EFI, the
> locking is unnecessary but does no harm (the permissions are set once
> via apply_to_page_range() at boot), so I added this call when adding
> support for strict permissions in EFI rt services mappings.
>
> So I think it is appropriate for create_pgd_mapping() to be in charge
> of calling the ctor(). We simply have no destroy_pgd_mapping()
> counterpart that would be the place for the dtor() call, given that we
> never take down EFI rt services mappi >
> Whether it makes sense or not to lock/unlock in apply_to_page_range()
> is something I did not spend any brain cycles on at the time.
>
Agreed there shouldn't be a problem right now. I do think the locking is
appropriate in apply_to_page_range given what other functions also get
locked.
I really wish this were less asymmetrical though since it get hard
to reason about. It looks like hotplug_paging will call the ctor,
so is there an issue with calling hot-remove on memory that was once
hot-added or is that not a concern?
Thanks,
Laura
^ permalink raw reply
* [linux-sunxi] Re: [PATCH 2/4] ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux setting
From: Chen-Yu Tsai @ 2017-04-19 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <442479d213a83c73cd7ff44538d234ea@aosc.io>
On Wed, Apr 19, 2017 at 11:36 PM, <icenowy@aosc.io> wrote:
> ? 2017-04-19 13:09?Chen-Yu Tsai ???
>>
>> As part of our effort to move pinctrl/GPIO interlocking into the
>> driver where it belongs, this patch drops the definition and usage
>> of the mmc0_cd_pin_reference_design pinmux setting for the default
>> mmc0 card detect GPIO pin.
>>
>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
[...]
>> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
>> b/arch/arm/boot/dts/sun7i-a20.dtsi
>> index 93aa55970bd7..c03b59aaec82 100644
>> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
>> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
>> @@ -1190,12 +1190,6 @@
>> bias-pull-up;
>> };
>>
>> - mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
>> - pins = "PH1";
>> - function = "gpio_in";
>> - bias-pull-up;
>
>
> It needs pull up, so shouldn't be dropped.
>
> (Although there may be external pull-up resistors on the board;
> however last time we removed the pull-up on MMC node many boards
> failed, so we cannot rely on external pull-up resistors)
I checked the boards that I have schematics, and the reference design.
All have proper external pull-up resistors for this pin, unlike the
other mmc pins.
If some board doesn't, it really needs to be singled out and handled
separately. Have you encountered any issues?
Regards
ChenYu
>
>> - };
>> -
>> mmc2_pins_a: mmc2 at 0 {
>> pins = "PC6", "PC7", "PC8",
>> "PC9", "PC10", "PC11";
>
>
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an
> email to linux-sunxi+unsubscribe at googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* [PATCH v24 09/11] acpi/arm64: Add memory-mapped timer support in GTDT driver
From: Mark Rutland @ 2017-04-19 15:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170419150725.GH27829@leverpostej>
On Wed, Apr 19, 2017 at 04:07:25PM +0100, Mark Rutland wrote:
> On Tue, Apr 18, 2017 at 06:21:07PM +0100, Lorenzo Pieralisi wrote:
> > On Sat, Apr 15, 2017 at 02:40:12AM +0800, fu.wei at linaro.org wrote:
> > If yes, why can't it simply be written like this ?
> >
> > for (; i >= 0; i--, gtdt_frame--) {
> > frame = &timer_mem->frame[gtdt_frame->frame_number];
> >
> > /* not sure this check is actually needed */
> > if (gtdt_frame->common_flags & ACPI_GTDT_GT_IS_SECURE_TIMER)
> > continue;
> >
> > if (frame->phys_irq > 0)
> > acpi_unregister_gsi(gtdt_frame->timer_interrupt);
> > if (frame->virt_irq > 0)
> > acpi_unregister_gsi(gtdt_frame->virtual_timer_interrupt);
> > }
>
> A reverse loop of this form will work.
>
> That requires some restructuring, and care to avoid going out of bounds
> instantaneously with the gtdt_frame--, so as to not invoke nasal demons.
>
> I've attacked this locally, and will send this out after testing. I'll
> drop the new ACPI API patch.
FWIW, I've set this up so the cleanup path is:
do {
if (gtdt_frame->common_flags & ACPI_GTDT_GT_IS_SECURE_TIMER ||
gtdt_frame->frame_number >= ARCH_TIMER_MEM_MAX_FRAMES)
continue;
frame = &timer_mem->frame[gtdt_frame->frame_number];
if (frame->phys_irq > 0)
acpi_unregister_gsi(gtdt_frame->timer_interrupt);
frame->phys_irq = 0;
if (frame->virt_irq > 0)
acpi_unregister_gsi(gtdt_frame->virtual_timer_interrupt);
frame->virt_irq = 0;
} while (i-- >= 0 && gtdt_frame--);
... the zeroing is to account for duplicate frames, which I now check for in
the probe path (as we do for DT).
Can I take it per your comment on the prior version that with this change I can
take your ack?
I also assume that you're happy for all of the drivers/acpi/arm64/ patches in the
series to go via the clocksource tree?
Thanks,
Mark.
^ permalink raw reply
* [PATCH 2/4] ARM: sunxi: Drop mmc0_cd_pin_reference_design pinmux setting
From: icenowy at aosc.io @ 2017-04-19 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170419050919.6762-3-wens@csie.org>
? 2017-04-19 13:09?Chen-Yu Tsai ???
> As part of our effort to move pinctrl/GPIO interlocking into the
> driver where it belongs, this patch drops the definition and usage
> of the mmc0_cd_pin_reference_design pinmux setting for the default
> mmc0 card detect GPIO pin.
>
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> ---
> arch/arm/boot/dts/sun4i-a10-a1000.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-gemei-g9.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-hackberry.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-inet1.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-inet97fv2.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-marsboard.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-mini-xplus.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-mk802.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-mk802ii.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-pcduino.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts | 2 +-
> arch/arm/boot/dts/sun4i-a10.dtsi | 6 ------
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-hummingbird.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-icnova-swac.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-itead-ibox.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-m3.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-mk808c.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-pcduino3.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts | 2 +-
> arch/arm/boot/dts/sun7i-a20.dtsi | 6 ------
> 38 files changed, 36 insertions(+), 48 deletions(-)
>
> diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts
> b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> index f2a01fe2bebc..f80d37ddc4c6 100644
> --- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
> @@ -171,7 +171,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
> b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
> index 942d739a4384..6b02de592a02 100644
> --- a/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-ba10-tvbox.dts
> @@ -109,7 +109,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
> b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
> index 17f8c5ec011c..a7d61994b8fd 100644
> --- a/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-chuwi-v7-cw0825.dts
> @@ -128,7 +128,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> index d844938e2aa7..a698a994e5ff 100644
> --- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
> @@ -142,7 +142,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
> b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
> index aad3bec1cb39..e0777ae808c7 100644
> --- a/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-dserve-dsrv9703c.dts
> @@ -163,7 +163,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
> b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
> index 9616cdecce93..d8bfd7b74916 100644
> --- a/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-gemei-g9.dts
> @@ -146,7 +146,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH01 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
> b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
> index a1a7282199d5..856cfc9128e6 100644
> --- a/arch/arm/boot/dts/sun4i-a10-hackberry.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-hackberry.dts
> @@ -107,7 +107,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
> b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
> index bc4351bb851f..6506595268b2 100644
> --- a/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-hyundai-a7hd.dts
> @@ -79,7 +79,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-inet1.dts
> b/arch/arm/boot/dts/sun4i-a10-inet1.dts
> index b8923b92cb36..d51d8c302daf 100644
> --- a/arch/arm/boot/dts/sun4i-a10-inet1.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-inet1.dts
> @@ -161,7 +161,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
> b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
> index a1a2bbb3f9d3..a8e479fe43ca 100644
> --- a/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-inet97fv2.dts
> @@ -147,7 +147,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
> b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
> index 4a27eb9102cd..2acb89a87d41 100644
> --- a/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-inet9f-rev03.dts
> @@ -305,7 +305,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
> b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
> index 4e798f014c99..92e3e030ced3 100644
> --- a/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-itead-iteaduino-plus.dts
> @@ -100,7 +100,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
> b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
> index 308dc1513041..92b2d4af3d21 100644
> --- a/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-jesurun-q5.dts
> @@ -140,7 +140,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
> b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
> index 98a5f7258dca..0f927da28ee1 100644
> --- a/arch/arm/boot/dts/sun4i-a10-marsboard.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-marsboard.dts
> @@ -141,7 +141,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
> b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
> index 484c57493bd2..a5ed9e4e22c6 100644
> --- a/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-mini-xplus.dts
> @@ -97,7 +97,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-mk802.dts
> b/arch/arm/boot/dts/sun4i-a10-mk802.dts
> index 2b75745cd246..81db6824a2c7 100644
> --- a/arch/arm/boot/dts/sun4i-a10-mk802.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-mk802.dts
> @@ -72,7 +72,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
> b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
> index c861fa7e356c..e74a881fd9a7 100644
> --- a/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-mk802ii.dts
> @@ -83,7 +83,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
> b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
> index 3a2522a9419d..462412ee903c 100644
> --- a/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts
> @@ -145,7 +145,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
> b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
> index 83596fd2ccfc..84f55e76df0c 100644
> --- a/arch/arm/boot/dts/sun4i-a10-pcduino.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-pcduino.dts
> @@ -147,7 +147,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
> b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
> index a68c7cc53b94..c0f8c88b5a7d 100644
> --- a/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
> +++ b/arch/arm/boot/dts/sun4i-a10-pov-protab2-ips9.dts
> @@ -149,7 +149,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi
> b/arch/arm/boot/dts/sun4i-a10.dtsi
> index b63668ece151..41c2579143fd 100644
> --- a/arch/arm/boot/dts/sun4i-a10.dtsi
> +++ b/arch/arm/boot/dts/sun4i-a10.dtsi
> @@ -1030,12 +1030,6 @@
> bias-pull-up;
> };
>
> - mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
> - pins = "PH1";
> - function = "gpio_in";
> - bias-pull-up;
> - };
> -
> ps20_pins_a: ps20 at 0 {
> pins = "PI20", "PI21";
> function = "ps2";
> diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> index a2eab7aa80e0..7ac5bcc9f972 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> @@ -137,7 +137,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> index 102903e83bd2..4ebeecf9c3d7 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> @@ -178,7 +178,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
> b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
> index 99c00b9a1546..6e6264cd69f8 100644
> --- a/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-hummingbird.dts
> @@ -160,7 +160,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v0>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
> b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
> index 4da49717da21..e5cbcad3a556 100644
> --- a/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-i12-tvbox.dts
> @@ -157,7 +157,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
> b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
> index 28d3abbdc2d4..794e7617f545 100644
> --- a/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-icnova-swac.dts
> @@ -104,7 +104,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 8 5 GPIO_ACTIVE_HIGH>; /* PI5 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
> b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
> index d52222c82cb8..8a8a6dbcd414 100644
> --- a/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-itead-ibox.dts
> @@ -121,7 +121,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-m3.dts
> b/arch/arm/boot/dts/sun7i-a20-m3.dts
> index 86f69813683e..43c94787ef07 100644
> --- a/arch/arm/boot/dts/sun7i-a20-m3.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-m3.dts
> @@ -117,7 +117,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-mk808c.dts
> b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
> index c4ee30709f3a..f7413094183c 100644
> --- a/arch/arm/boot/dts/sun7i-a20-mk808c.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-mk808c.dts
> @@ -109,7 +109,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v0>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
> b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
> index 1af5b46862cb..64c8ef9a2756 100644
> --- a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb.dts
> @@ -187,7 +187,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
> b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
> index dcd0f7a0dffa..2ce1a9f13a17 100644
> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime.dts
> @@ -130,7 +130,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
> b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
> index e7d45425758c..097bd755764c 100644
> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
> @@ -131,7 +131,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> index def0ad8395bb..0b7403e4d687 100644
> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> @@ -198,7 +198,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
> b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
> index f47a5c46bc20..39bc73db72e5 100644
> --- a/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3-nano.dts
> @@ -130,7 +130,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
> b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
> index 98177b5891cb..777152a3df0f 100644
> --- a/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-pcduino3.dts
> @@ -156,7 +156,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
> b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
> index e19f17177755..f8d0aafb9f88 100644
> --- a/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-wexler-tab7200.dts
> @@ -151,7 +151,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
> b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
> index c3078d4f1093..84462d7961f5 100644
> --- a/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-wits-pro-a20-dkt.dts
> @@ -120,7 +120,7 @@
>
> &mmc0 {
> pinctrl-names = "default";
> - pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
> + pinctrl-0 = <&mmc0_pins_a>;
> vmmc-supply = <®_vcc3v3>;
> bus-width = <4>;
> cd-gpios = <&pio 7 1 GPIO_ACTIVE_HIGH>; /* PH1 */
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi
> b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 93aa55970bd7..c03b59aaec82 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -1190,12 +1190,6 @@
> bias-pull-up;
> };
>
> - mmc0_cd_pin_reference_design: mmc0_cd_pin at 0 {
> - pins = "PH1";
> - function = "gpio_in";
> - bias-pull-up;
It needs pull up, so shouldn't be dropped.
(Although there may be external pull-up resistors on the board;
however last time we removed the pull-up on MMC node many boards
failed, so we cannot rely on external pull-up resistors)
> - };
> -
> mmc2_pins_a: mmc2 at 0 {
> pins = "PC6", "PC7", "PC8",
> "PC9", "PC10", "PC11";
^ permalink raw reply
* [PATCH v6 6/8] coresight: add support for CPU debug module
From: Leo Yan @ 2017-04-19 15:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANLsYkyheVJkEjpcWAd5HHFCimfTPhgihioE7bYo1RAL=8Shdw@mail.gmail.com>
On Wed, Apr 19, 2017 at 08:52:12AM -0600, Mathieu Poirier wrote:
[...]
> >> > +static bool debug_enable;
> >> > +module_param_named(enable, debug_enable, bool, 0600);
> >> > +MODULE_PARM_DESC(enable, "Knob to enable debug functionality "
> >> > + "(default is 0, which means is disabled by default)");
> >>
> >> For this driver we have a debugFS interface so I question the validity of a
> >> kernel module parameter. Other than adding complexity to the code it offers no
> >> real added value. If a user is to insmod a module, it is just as easy to switch
> >> on the functionality using debugFS in a second step.
> >
> > This module parameter can be used for kernel command line, so
> > it's useful when user wants to dynamically turn on/off the
> > functionality at boot up time.
> >
> > Does this make sense for you? Removing this parameter is okay for
> > me, but this means users need to decide if use it by Kernel config
> > with static building in. This is a bit contradictory with before's
> > discussion.
>
> My hope was to use the kernel command line and the debugFS interface,
> avoiding the module parameter. Look at what the baycom_par and
> blacklist drivers are doing with the "__setup()" function and see if
> we can void a module parameter. If not then let it be, unless someone
> else has a better idea.
>
> [1]. drivers/net/hamradio/baycom_par.c
> [2]. drivers/s390/cio/blacklist.c
This driver supports module mode. So we can choose to use either module
parameter or __setup(). But as described in the file
Documentation/admin-guide/kernel-parameters.rst, the module parameter
is more flexible to be used at boot time or insmod the module:
"Parameters for modules which are built into the kernel need to be
specified on the kernel command line. modprobe looks through the
kernel command line (/proc/cmdline) and collects module parameters
when it loads a module, so the kernel command line can be used for
loadable modules too."
__setup() cannot support module mode, and when use __setup(), we need
register one callback function for it. The callback function is
friendly to parse complex parameters rather than module parameter.
but it's not necessary for this case.
So I'm bias to use module parameter :)
Thanks,
Leo Yan
^ permalink raw reply
* [GIT PULL 4/4] arm64: tegra: Device tree changes for v4.12-rc1
From: Thierry Reding @ 2017-04-19 15:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170419131905.GD29219@localhost>
On Wed, Apr 19, 2017 at 06:19:05AM -0700, Olof Johansson wrote:
> On Fri, Apr 07, 2017 at 01:10:20AM +0200, Thierry Reding wrote:
> > Hi ARM SoC maintainers,
> >
> > The following changes since commit c1ae3cfa0e89fa1a7ecc4c99031f5e9ae99d9201:
> >
> > Linux 4.11-rc1 (2017-03-05 12:59:56 -0800)
> >
> > are available in the git repository at:
> >
> > git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.12-arm64-dt
> >
> > for you to fetch changes up to 18236a14883b718ce973e4c090db6ecb49b38287:
> >
> > arm64: tegra: Update the Tegra132 flowctrl compatible string (2017-04-04 17:15:05 +0200)
> >
> > Thanks,
> > Thierry
> >
> > ----------------------------------------------------------------
> > arm64: tegra: Device tree changes for v4.12-rc1
> >
> > This adds a bunch of features for Tegra186, such as PMC, ethernet, I2C,
> > SDHCI and GPIO. It also enables various features on the P2771 devkit.
> >
> > A small fix is made to the compatible string list for the flow
> > controller on Tegra132 and the IOMMU is enabled for host1x on Tegra210.
>
> Nice, merged. Any chance we'll see Jetson TX2 support for 4.13?
P2771 *is* Jetson TX2. I suppose I could go and update the DTS file and
clarify that in the model string.
Thierry
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