* [PATCH v2 11/30] arm: dts: mt7623: add nand nodes to the mt7623.dtsi file
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
Add NAND/EEC nodes to the mt7623.dtsi file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 131808c..f15d65a 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -330,6 +330,31 @@
status = "disabled";
};
+ nandc: nfi at 1100d000 {
+ compatible = "mediatek,mt7623-nfc",
+ "mediatek,mt2701-nfc";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ clocks = <&pericfg CLK_PERI_NFI>,
+ <&pericfg CLK_PERI_NFI_PAD>;
+ clock-names = "nfi_clk", "pad_clk";
+ status = "disabled";
+ ecc-engine = <&bch>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ bch: ecc at 1100e000 {
+ compatible = "mediatek,mt7623-ecc",
+ "mediatek,mt2701-ecc";
+ reg = <0 0x1100e000 0 0x1000>;
+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_NFI_ECC>;
+ clock-names = "nfiecc_clk";
+ status = "disabled";
+ };
+
hifsys: syscon at 1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
--
1.9.1
^ permalink raw reply related
* [PATCH v2 10/30] arm: dts: mt7623: add spi nodes to the mt7623.dtsi file
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
Add spi controller nodes to the mt7623.dtsi file
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index adb4793..131808c 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -288,6 +288,48 @@
status = "disabled";
};
+ spi0: spi at 1100a000 {
+ compatible = "mediatek,mt7623-spi",
+ "mediatek,mt2701-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x100>;
+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI0_SEL>,
+ <&pericfg CLK_PERI_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi1: spi at 11016000 {
+ compatible = "mediatek,mt7623-spi",
+ "mediatek,mt2701-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11016000 0 0x100>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI1_SEL>,
+ <&pericfg CLK_PERI_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi at 11017000 {
+ compatible = "mediatek,mt7623-spi",
+ "mediatek,mt2701-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11017000 0 0x1000>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
+ <&topckgen CLK_TOP_SPI2_SEL>,
+ <&pericfg CLK_PERI_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
hifsys: syscon at 1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
--
1.9.1
^ permalink raw reply related
* [PATCH v2 09/30] arm: dts: mt7623: add i2c nodes to the mt7623.dtsi file
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
Add I2C nodes to the mt7623.dtsi file.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 6adc21d..adb4793 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -243,6 +243,51 @@
status = "disabled";
};
+ i2c0: i2c at 11007000 {
+ compatible = "mediatek,mt7623-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11007000 0 0x70>,
+ <0 0x11000200 0 0x80>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C0>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c at 11008000 {
+ compatible = "mediatek,mt7623-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11008000 0 0x70>,
+ <0 0x11000280 0 0x80>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C1>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c at 11009000 {
+ compatible = "mediatek,mt7623-i2c",
+ "mediatek,mt6577-i2c";
+ reg = <0 0x11009000 0 0x70>,
+ <0 0x11000300 0 0x80>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
+ clock-div = <16>;
+ clocks = <&pericfg CLK_PERI_I2C2>,
+ <&pericfg CLK_PERI_AP_DMA>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
hifsys: syscon at 1a000000 {
compatible = "mediatek,mt7623-hifsys",
"mediatek,mt2701-hifsys",
--
1.9.1
^ permalink raw reply related
* [PATCH v2 08/30] arm: dts: mt7623: add pmic wrapper nodes to the mt7623 dtsi file
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
Add PMIC wrapper node to the mt7623.dtsi file which
is necessary for the control of PMIC from Mediatek.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 1942bc7..6adc21d 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -158,6 +158,19 @@
clock-names = "system-clk", "rtc-clk";
};
+ pwrap: pwrap at 1000d000 {
+ compatible = "mediatek,mt7623-pwrap",
+ "mediatek,mt2701-pwrap";
+ reg = <0 0x1000d000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ resets = <&infracfg MT2701_INFRA_PMIC_WRAP_RST>;
+ reset-names = "pwrap";
+ clocks = <&infracfg CLK_INFRA_PMICSPI>,
+ <&infracfg CLK_INFRA_PMICWRAP>;
+ clock-names = "spi", "wrap";
+ };
+
sysirq: interrupt-controller at 10200100 {
compatible = "mediatek,mt7623-sysirq",
"mediatek,mt6577-sysirq";
--
1.9.1
^ permalink raw reply related
* [PATCH v2 07/30] arm: dts: mt7623: add pinctrl nodes to the mt7623 dtsi file
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
Add pin controller node to the mt7623.dtsi file
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 23 +++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 3cc0a3a..1942bc7 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -15,7 +15,10 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/pinctrl/mt7623-pinfunc.h>
#include <dt-bindings/power/mt2701-power.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
@@ -107,6 +110,26 @@
#reset-cells = <1>;
};
+ pio: pinctrl at 10005000 {
+ compatible = "mediatek,mt7623-pinctrl",
+ "mediatek,mt2701-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ interrupt-parent = <&gic>;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ syscfg_pctl_a: syscfg at 10005000 {
+ compatible = "mediatek,mt7623-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
scpsys: scpsys at 10006000 {
compatible = "mediatek,mt7623-scpsys",
"mediatek,mt2701-scpsys",
--
1.9.1
^ permalink raw reply related
* [PATCH v2 06/30] arm: dts: mt7623: add clock-frequency to the a7 timer node to mt7623.dtsi
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
We need to tell the driver what the timers frequency is and that the core
has not be configured by the bootrom. Not doing so makes the unit not
boot.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index adb2393..3cc0a3a 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -77,6 +77,8 @@
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <13000000>;
+ arm,cpu-registers-not-fw-configured;
};
topckgen: syscon at 10000000 {
--
1.9.1
^ permalink raw reply related
* [PATCH v2 05/30] arm: dts: mt7623: add power domain controller device node
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
Add power domain controller node (scpsys) for MT7623.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 54cff6a..adb2393 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
@@ -104,6 +105,19 @@
#reset-cells = <1>;
};
+ scpsys: scpsys at 10006000 {
+ compatible = "mediatek,mt7623-scpsys",
+ "mediatek,mt2701-scpsys",
+ "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "mm", "mfg", "ethif";
+ };
+
watchdog: watchdog at 10007000 {
compatible = "mediatek,mt7623-wdt",
"mediatek,mt6589-wdt";
--
1.9.1
^ permalink raw reply related
* [PATCH v2 04/30] arm: dts: mt7623: add subsystem clock controller device nodes
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
Add MT7623 subsystem clock controllers for hifsys and ethsys.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index b97b2ba..54cff6a 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -190,4 +190,20 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+ hifsys: syscon at 1a000000 {
+ compatible = "mediatek,mt7623-hifsys",
+ "mediatek,mt2701-hifsys",
+ "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ethsys: syscon at 1b000000 {
+ compatible = "mediatek,mt7623-ethsys",
+ "mediatek,mt2701-ethsys",
+ "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 03/30] arm: dts: mt7623: add clock controller device nodes
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: John Crispin <john@phrozen.org>
Add clock controller nodes for MT7623, including topckgen, infracfg,
pericfg and apmixedsys. This patch also cleans up two oscillators that
provide clocks for MT7623. Switch the uart clocks to the real ones while
at it.
Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
arch/arm/boot/dts/mt7623.dtsi | 64 +++++++++++++++++++++++++++++++++++++------
1 file changed, 55 insertions(+), 9 deletions(-)
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 402579a..b97b2ba 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -14,6 +14,8 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
/ {
@@ -53,16 +55,18 @@
#clock-cells = <0>;
};
- rtc_clk: dummy32k {
+ rtc32k: oscillator at 1 {
compatible = "fixed-clock";
- clock-frequency = <32000>;
#clock-cells = <0>;
+ clock-frequency = <32000>;
+ clock-output-names = "rtc32k";
};
- uart_clk: dummy26m {
+ clk26m: oscillator at 0 {
compatible = "fixed-clock";
- clock-frequency = <26000000>;
#clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
};
timer {
@@ -74,6 +78,32 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ topckgen: syscon at 10000000 {
+ compatible = "mediatek,mt7623-topckgen",
+ "mediatek,mt2701-topckgen",
+ "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg: syscon at 10001000 {
+ compatible = "mediatek,mt7623-infracfg",
+ "mediatek,mt2701-infracfg",
+ "syscon";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: syscon at 10003000 {
+ compatible = "mediatek,mt7623-pericfg",
+ "mediatek,mt2701-pericfg",
+ "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
watchdog: watchdog at 10007000 {
compatible = "mediatek,mt7623-wdt",
"mediatek,mt6589-wdt";
@@ -85,7 +115,7 @@
"mediatek,mt6577-timer";
reg = <0 0x10008000 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&system_clk>, <&rtc_clk>;
+ clocks = <&system_clk>, <&rtc32k>;
clock-names = "system-clk", "rtc-clk";
};
@@ -98,6 +128,14 @@
reg = <0 0x10200100 0 0x1c>;
};
+ apmixedsys: syscon at 10209000 {
+ compatible = "mediatek,mt7623-apmixedsys",
+ "mediatek,mt2701-apmixedsys",
+ "syscon";
+ reg = <0 0x10209000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
gic: interrupt-controller at 10211000 {
compatible = "arm,cortex-a7-gic";
interrupt-controller;
@@ -114,7 +152,9 @@
"mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x400>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART0_SEL>,
+ <&pericfg CLK_PERI_UART0>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -123,7 +163,9 @@
"mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x400>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART1_SEL>,
+ <&pericfg CLK_PERI_UART1>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -132,7 +174,9 @@
"mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x400>;
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART2_SEL>,
+ <&pericfg CLK_PERI_UART2>;
+ clock-names = "baud", "bus";
status = "disabled";
};
@@ -141,7 +185,9 @@
"mediatek,mt6577-uart";
reg = <0 0x11005000 0 0x400>;
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&uart_clk>;
+ clocks = <&pericfg CLK_PERI_UART3_SEL>,
+ <&pericfg CLK_PERI_UART3>;
+ clock-names = "baud", "bus";
status = "disabled";
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH v2 02/30] pinctrl: mediatek: reuse pinctrl driver for mt7623
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
mt7623 pinctrl driver can be compatible with mt2701 one,
so the patch reuses the driver and deletes those redundant
ones.
Cc: John Crispin <john@phrozen.org>
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 -
drivers/pinctrl/mediatek/Kconfig | 9 +-
drivers/pinctrl/mediatek/Makefile | 1 -
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 379 ----
drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h | 1936 --------------------
5 files changed, 1 insertion(+), 2325 deletions(-)
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
index 17631d0..9ffb0b2 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt
@@ -6,7 +6,6 @@ Required properties:
- compatible: value should be one of the following.
"mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
"mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
- "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
"mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
"mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
"mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 80fe3b4..fac9866 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -11,18 +11,11 @@ config PINCTRL_MTK
# For ARMv7 SoCs
config PINCTRL_MT2701
bool "Mediatek MT2701 pin control"
- depends on MACH_MT2701 || COMPILE_TEST
+ depends on MACH_MT7623 || MACH_MT2701 || COMPILE_TEST
depends on OF
default MACH_MT2701
select PINCTRL_MTK
-config PINCTRL_MT7623
- bool "Mediatek MT7623 pin control"
- depends on MACH_MT7623 || COMPILE_TEST
- depends on OF
- default MACH_MT7623
- select PINCTRL_MTK_COMMON
-
config PINCTRL_MT8135
bool "Mediatek MT8135 pin control"
depends on MACH_MT8135 || COMPILE_TEST
diff --git a/drivers/pinctrl/mediatek/Makefile b/drivers/pinctrl/mediatek/Makefile
index 3e3390a..e59c613 100644
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,7 +3,6 @@ obj-y += pinctrl-mtk-common.o
# SoC Drivers
obj-$(CONFIG_PINCTRL_MT2701) += pinctrl-mt2701.o
-obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT8135) += pinctrl-mt8135.o
obj-$(CONFIG_PINCTRL_MT8127) += pinctrl-mt8127.o
obj-$(CONFIG_PINCTRL_MT8173) += pinctrl-mt8173.o
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
deleted file mode 100644
index fa28dd6..0000000
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ /dev/null
@@ -1,379 +0,0 @@
-/*
- * Copyright (c) 2016 John Crispin <john@phrozen.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <dt-bindings/pinctrl/mt65xx.h>
-#include <linux/module.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/platform_device.h>
-#include <linux/pinctrl/pinctrl.h>
-#include <linux/regmap.h>
-
-#include "pinctrl-mtk-common.h"
-#include "pinctrl-mtk-mt7623.h"
-
-static const struct mtk_drv_group_desc mt7623_drv_grp[] = {
- /* 0E4E8SR 4/8/12/16 */
- MTK_DRV_GRP(4, 16, 1, 2, 4),
- /* 0E2E4SR 2/4/6/8 */
- MTK_DRV_GRP(2, 8, 1, 2, 2),
- /* E8E4E2 2/4/6/8/10/12/14/16 */
- MTK_DRV_GRP(2, 16, 0, 2, 2)
-};
-
-#define DRV_SEL0 0xf50
-#define DRV_SEL1 0xf60
-#define DRV_SEL2 0xf70
-#define DRV_SEL3 0xf80
-#define DRV_SEL4 0xf90
-#define DRV_SEL5 0xfa0
-#define DRV_SEL6 0xfb0
-#define DRV_SEL7 0xfe0
-#define DRV_SEL8 0xfd0
-#define DRV_SEL9 0xff0
-#define DRV_SEL10 0xf00
-
-#define MSDC0_CTRL0 0xcc0
-#define MSDC0_CTRL1 0xcd0
-#define MSDC0_CTRL2 0xce0
-#define MSDC0_CTRL3 0xcf0
-#define MSDC0_CTRL4 0xd00
-#define MSDC0_CTRL5 0xd10
-#define MSDC0_CTRL6 0xd20
-#define MSDC1_CTRL0 0xd30
-#define MSDC1_CTRL1 0xd40
-#define MSDC1_CTRL2 0xd50
-#define MSDC1_CTRL3 0xd60
-#define MSDC1_CTRL4 0xd70
-#define MSDC1_CTRL5 0xd80
-#define MSDC1_CTRL6 0xd90
-
-#define IES_EN0 0xb20
-#define IES_EN1 0xb30
-#define IES_EN2 0xb40
-
-#define SMT_EN0 0xb50
-#define SMT_EN1 0xb60
-#define SMT_EN2 0xb70
-
-static const struct mtk_pin_drv_grp mt7623_pin_drv[] = {
- MTK_PIN_DRV_GRP(0, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(1, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(2, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(3, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(4, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(5, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(6, DRV_SEL0, 0, 1),
- MTK_PIN_DRV_GRP(7, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(8, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(9, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(10, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(11, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(12, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(13, DRV_SEL0, 8, 1),
- MTK_PIN_DRV_GRP(14, DRV_SEL0, 12, 0),
- MTK_PIN_DRV_GRP(15, DRV_SEL0, 12, 0),
- MTK_PIN_DRV_GRP(18, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(19, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(20, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(21, DRV_SEL1, 4, 0),
- MTK_PIN_DRV_GRP(22, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(23, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(24, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(25, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(26, DRV_SEL1, 8, 0),
- MTK_PIN_DRV_GRP(27, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(28, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(29, DRV_SEL1, 12, 0),
- MTK_PIN_DRV_GRP(33, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(34, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(35, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(36, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(37, DRV_SEL2, 0, 0),
- MTK_PIN_DRV_GRP(39, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(40, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(41, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(42, DRV_SEL2, 8, 1),
- MTK_PIN_DRV_GRP(43, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(44, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(45, DRV_SEL2, 12, 0),
- MTK_PIN_DRV_GRP(47, DRV_SEL3, 0, 0),
- MTK_PIN_DRV_GRP(48, DRV_SEL3, 0, 0),
- MTK_PIN_DRV_GRP(49, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(53, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(54, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(55, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(56, DRV_SEL3, 12, 0),
- MTK_PIN_DRV_GRP(60, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(61, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(62, DRV_SEL4, 8, 1),
- MTK_PIN_DRV_GRP(63, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(64, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(65, DRV_SEL4, 12, 1),
- MTK_PIN_DRV_GRP(66, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(67, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(68, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(69, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(70, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(71, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(72, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(73, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(74, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(83, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(84, DRV_SEL5, 0, 1),
- MTK_PIN_DRV_GRP(105, MSDC1_CTRL1, 0, 1),
- MTK_PIN_DRV_GRP(106, MSDC1_CTRL0, 0, 1),
- MTK_PIN_DRV_GRP(107, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(108, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(109, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(110, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(111, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(112, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(113, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(114, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(115, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(116, MSDC0_CTRL1, 0, 1),
- MTK_PIN_DRV_GRP(117, MSDC0_CTRL0, 0, 1),
- MTK_PIN_DRV_GRP(118, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(119, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(120, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(121, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(126, DRV_SEL3, 4, 0),
- MTK_PIN_DRV_GRP(199, DRV_SEL0, 4, 1),
- MTK_PIN_DRV_GRP(200, DRV_SEL8, 0, 0),
- MTK_PIN_DRV_GRP(201, DRV_SEL8, 0, 0),
- MTK_PIN_DRV_GRP(203, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(204, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(205, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(206, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(207, DRV_SEL8, 4, 0),
- MTK_PIN_DRV_GRP(208, DRV_SEL8, 8, 0),
- MTK_PIN_DRV_GRP(209, DRV_SEL8, 8, 0),
- MTK_PIN_DRV_GRP(236, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(237, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(238, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(239, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(240, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(241, DRV_SEL9, 4, 0),
- MTK_PIN_DRV_GRP(242, DRV_SEL9, 8, 0),
- MTK_PIN_DRV_GRP(243, DRV_SEL9, 8, 0),
- MTK_PIN_DRV_GRP(257, MSDC0_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(261, MSDC1_CTRL2, 0, 1),
- MTK_PIN_DRV_GRP(262, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(263, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(264, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(265, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(266, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(267, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(268, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(269, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(270, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(271, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(272, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(274, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(275, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(276, DRV_SEL10, 8, 0),
- MTK_PIN_DRV_GRP(278, DRV_SEL2, 8, 1),
-};
-
-static const struct mtk_pin_spec_pupd_set_samereg mt7623_spec_pupd[] = {
- MTK_PIN_PUPD_SPEC_SR(105, MSDC1_CTRL1, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(106, MSDC1_CTRL0, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(107, MSDC1_CTRL3, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(108, MSDC1_CTRL3, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(109, MSDC1_CTRL3, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(110, MSDC1_CTRL3, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(111, MSDC0_CTRL4, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(112, MSDC0_CTRL4, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(113, MSDC0_CTRL4, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(114, MSDC0_CTRL4, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(115, MSDC0_CTRL5, 0, 1, 2),
- MTK_PIN_PUPD_SPEC_SR(116, MSDC0_CTRL1, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(117, MSDC0_CTRL0, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(118, MSDC0_CTRL3, 12, 13, 14),
- MTK_PIN_PUPD_SPEC_SR(119, MSDC0_CTRL3, 8, 9, 10),
- MTK_PIN_PUPD_SPEC_SR(120, MSDC0_CTRL3, 4, 5, 6),
- MTK_PIN_PUPD_SPEC_SR(121, MSDC0_CTRL3, 0, 1, 2),
-};
-
-static int mt7623_spec_pull_set(struct regmap *regmap, unsigned int pin,
- unsigned char align, bool isup, unsigned int r1r0)
-{
- return mtk_pctrl_spec_pull_set_samereg(regmap, mt7623_spec_pupd,
- ARRAY_SIZE(mt7623_spec_pupd), pin, align, isup, r1r0);
-}
-
-static const struct mtk_pin_ies_smt_set mt7623_ies_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, IES_EN0, 0),
- MTK_PIN_IES_SMT_SPEC(7, 9, IES_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(10, 13, IES_EN0, 2),
- MTK_PIN_IES_SMT_SPEC(14, 15, IES_EN0, 3),
- MTK_PIN_IES_SMT_SPEC(18, 21, IES_EN0, 5),
- MTK_PIN_IES_SMT_SPEC(22, 26, IES_EN0, 6),
- MTK_PIN_IES_SMT_SPEC(27, 29, IES_EN0, 7),
- MTK_PIN_IES_SMT_SPEC(33, 37, IES_EN0, 8),
- MTK_PIN_IES_SMT_SPEC(39, 42, IES_EN0, 9),
- MTK_PIN_IES_SMT_SPEC(43, 45, IES_EN0, 10),
- MTK_PIN_IES_SMT_SPEC(47, 48, IES_EN0, 11),
- MTK_PIN_IES_SMT_SPEC(49, 49, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(53, 56, IES_EN0, 14),
- MTK_PIN_IES_SMT_SPEC(60, 62, IES_EN1, 0),
- MTK_PIN_IES_SMT_SPEC(63, 65, IES_EN1, 1),
- MTK_PIN_IES_SMT_SPEC(66, 71, IES_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(72, 74, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(75, 76, IES_EN1, 3),
- MTK_PIN_IES_SMT_SPEC(83, 84, IES_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(105, 121, MSDC1_CTRL1, 4),
- MTK_PIN_IES_SMT_SPEC(122, 125, IES_EN1, 7),
- MTK_PIN_IES_SMT_SPEC(126, 126, IES_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(199, 201, IES_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(203, 207, IES_EN2, 2),
- MTK_PIN_IES_SMT_SPEC(208, 209, IES_EN2, 3),
- MTK_PIN_IES_SMT_SPEC(236, 241, IES_EN2, 6),
- MTK_PIN_IES_SMT_SPEC(242, 243, IES_EN2, 7),
- MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL2, 4),
- MTK_PIN_IES_SMT_SPEC(262, 272, IES_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(274, 276, IES_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(278, 278, IES_EN2, 13),
-};
-
-static const struct mtk_pin_ies_smt_set mt7623_smt_set[] = {
- MTK_PIN_IES_SMT_SPEC(0, 6, SMT_EN0, 0),
- MTK_PIN_IES_SMT_SPEC(7, 9, SMT_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(10, 13, SMT_EN0, 2),
- MTK_PIN_IES_SMT_SPEC(14, 15, SMT_EN0, 3),
- MTK_PIN_IES_SMT_SPEC(18, 21, SMT_EN0, 5),
- MTK_PIN_IES_SMT_SPEC(22, 26, SMT_EN0, 6),
- MTK_PIN_IES_SMT_SPEC(27, 29, SMT_EN0, 7),
- MTK_PIN_IES_SMT_SPEC(33, 37, SMT_EN0, 8),
- MTK_PIN_IES_SMT_SPEC(39, 42, SMT_EN0, 9),
- MTK_PIN_IES_SMT_SPEC(43, 45, SMT_EN0, 10),
- MTK_PIN_IES_SMT_SPEC(47, 48, SMT_EN0, 11),
- MTK_PIN_IES_SMT_SPEC(49, 49, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(53, 56, SMT_EN0, 14),
- MTK_PIN_IES_SMT_SPEC(60, 62, SMT_EN1, 0),
- MTK_PIN_IES_SMT_SPEC(63, 65, SMT_EN1, 1),
- MTK_PIN_IES_SMT_SPEC(66, 71, SMT_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(72, 74, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(75, 76, SMT_EN1, 3),
- MTK_PIN_IES_SMT_SPEC(83, 84, SMT_EN1, 2),
- MTK_PIN_IES_SMT_SPEC(105, 106, MSDC1_CTRL1, 11),
- MTK_PIN_IES_SMT_SPEC(107, 107, MSDC1_CTRL3, 3),
- MTK_PIN_IES_SMT_SPEC(108, 108, MSDC1_CTRL3, 7),
- MTK_PIN_IES_SMT_SPEC(109, 109, MSDC1_CTRL3, 11),
- MTK_PIN_IES_SMT_SPEC(110, 111, MSDC1_CTRL3, 15),
- MTK_PIN_IES_SMT_SPEC(112, 112, MSDC0_CTRL4, 11),
- MTK_PIN_IES_SMT_SPEC(113, 113, MSDC0_CTRL4, 7),
- MTK_PIN_IES_SMT_SPEC(114, 115, MSDC0_CTRL4, 3),
- MTK_PIN_IES_SMT_SPEC(116, 117, MSDC0_CTRL1, 11),
- MTK_PIN_IES_SMT_SPEC(118, 118, MSDC0_CTRL3, 15),
- MTK_PIN_IES_SMT_SPEC(119, 119, MSDC0_CTRL3, 11),
- MTK_PIN_IES_SMT_SPEC(120, 120, MSDC0_CTRL3, 7),
- MTK_PIN_IES_SMT_SPEC(121, 121, MSDC0_CTRL3, 3),
- MTK_PIN_IES_SMT_SPEC(122, 125, SMT_EN1, 7),
- MTK_PIN_IES_SMT_SPEC(126, 126, SMT_EN0, 12),
- MTK_PIN_IES_SMT_SPEC(199, 201, SMT_EN0, 1),
- MTK_PIN_IES_SMT_SPEC(203, 207, SMT_EN2, 2),
- MTK_PIN_IES_SMT_SPEC(208, 209, SMT_EN2, 3),
- MTK_PIN_IES_SMT_SPEC(236, 241, SMT_EN2, 6),
- MTK_PIN_IES_SMT_SPEC(242, 243, SMT_EN2, 7),
- MTK_PIN_IES_SMT_SPEC(261, 261, MSDC1_CTRL6, 3),
- MTK_PIN_IES_SMT_SPEC(262, 272, SMT_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(274, 276, SMT_EN2, 12),
- MTK_PIN_IES_SMT_SPEC(278, 278, SMT_EN2, 13),
-};
-
-static int mt7623_ies_smt_set(struct regmap *regmap, unsigned int pin,
- unsigned char align, int value, enum pin_config_param arg)
-{
- if (arg == PIN_CONFIG_INPUT_ENABLE)
- return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_ies_set,
- ARRAY_SIZE(mt7623_ies_set), pin, align, value);
- else if (arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
- return mtk_pconf_spec_set_ies_smt_range(regmap, mt7623_smt_set,
- ARRAY_SIZE(mt7623_smt_set), pin, align, value);
- return -EINVAL;
-}
-
-static const struct mtk_pinctrl_devdata mt7623_pinctrl_data = {
- .pins = mtk_pins_mt7623,
- .npins = ARRAY_SIZE(mtk_pins_mt7623),
- .grp_desc = mt7623_drv_grp,
- .n_grp_cls = ARRAY_SIZE(mt7623_drv_grp),
- .pin_drv_grp = mt7623_pin_drv,
- .n_pin_drv_grps = ARRAY_SIZE(mt7623_pin_drv),
- .spec_pull_set = mt7623_spec_pull_set,
- .spec_ies_smt_set = mt7623_ies_smt_set,
- .dir_offset = 0x0000,
- .pullen_offset = 0x0150,
- .pullsel_offset = 0x0280,
- .dout_offset = 0x0500,
- .din_offset = 0x0630,
- .pinmux_offset = 0x0760,
- .type1_start = 280,
- .type1_end = 280,
- .port_shf = 4,
- .port_mask = 0x1f,
- .port_align = 4,
- .eint_offsets = {
- .name = "mt7623_eint",
- .stat = 0x000,
- .ack = 0x040,
- .mask = 0x080,
- .mask_set = 0x0c0,
- .mask_clr = 0x100,
- .sens = 0x140,
- .sens_set = 0x180,
- .sens_clr = 0x1c0,
- .soft = 0x200,
- .soft_set = 0x240,
- .soft_clr = 0x280,
- .pol = 0x300,
- .pol_set = 0x340,
- .pol_clr = 0x380,
- .dom_en = 0x400,
- .dbnc_ctrl = 0x500,
- .dbnc_set = 0x600,
- .dbnc_clr = 0x700,
- .port_mask = 6,
- .ports = 6,
- },
- .ap_num = 169,
- .db_cnt = 16,
-};
-
-static int mt7623_pinctrl_probe(struct platform_device *pdev)
-{
- return mtk_pctrl_init(pdev, &mt7623_pinctrl_data, NULL);
-}
-
-static const struct of_device_id mt7623_pctrl_match[] = {
- { .compatible = "mediatek,mt7623-pinctrl", },
- {}
-};
-MODULE_DEVICE_TABLE(of, mt7623_pctrl_match);
-
-static struct platform_driver mtk_pinctrl_driver = {
- .probe = mt7623_pinctrl_probe,
- .driver = {
- .name = "mediatek-mt7623-pinctrl",
- .of_match_table = mt7623_pctrl_match,
- },
-};
-
-static int __init mtk_pinctrl_init(void)
-{
- return platform_driver_register(&mtk_pinctrl_driver);
-}
-
-arch_initcall(mtk_pinctrl_init);
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h b/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
deleted file mode 100644
index e06cfc4..0000000
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
+++ /dev/null
@@ -1,1936 +0,0 @@
-/*
- * Copyright (c) 2016 John Crispin <john@phrozen.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __PINCTRL_MTK_MT7623_H
-#define __PINCTRL_MTK_MT7623_H
-
-#include <linux/pinctrl/pinctrl.h>
-#include "pinctrl-mtk-common.h"
-
-static const struct mtk_desc_pin mtk_pins_mt7623[] = {
- MTK_PIN(
- PINCTRL_PIN(0, "PWRAP_SPI0_MI"),
- "J20", "mt7623",
- MTK_EINT_FUNCTION(0, 148),
- MTK_FUNCTION(0, "GPIO0"),
- MTK_FUNCTION(1, "PWRAP_SPIDO"),
- MTK_FUNCTION(2, "PWRAP_SPIDI")
- ),
- MTK_PIN(
- PINCTRL_PIN(1, "PWRAP_SPI0_MO"),
- "D10", "mt7623",
- MTK_EINT_FUNCTION(0, 149),
- MTK_FUNCTION(0, "GPIO1"),
- MTK_FUNCTION(1, "PWRAP_SPIDI"),
- MTK_FUNCTION(2, "PWRAP_SPIDO")
- ),
- MTK_PIN(
- PINCTRL_PIN(2, "PWRAP_INT"),
- "E11", "mt7623",
- MTK_EINT_FUNCTION(0, 150),
- MTK_FUNCTION(0, "GPIO2"),
- MTK_FUNCTION(1, "PWRAP_INT")
- ),
- MTK_PIN(
- PINCTRL_PIN(3, "PWRAP_SPI0_CK"),
- "H12", "mt7623",
- MTK_EINT_FUNCTION(0, 151),
- MTK_FUNCTION(0, "GPIO3"),
- MTK_FUNCTION(1, "PWRAP_SPICK_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(4, "PWRAP_SPI0_CSN"),
- "E12", "mt7623",
- MTK_EINT_FUNCTION(0, 152),
- MTK_FUNCTION(0, "GPIO4"),
- MTK_FUNCTION(1, "PWRAP_SPICS_B_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(5, "PWRAP_SPI0_CK2"),
- "H11", "mt7623",
- MTK_EINT_FUNCTION(0, 155),
- MTK_FUNCTION(0, "GPIO5"),
- MTK_FUNCTION(1, "PWRAP_SPICK2_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(6, "PWRAP_SPI0_CSN2"),
- "G11", "mt7623",
- MTK_EINT_FUNCTION(0, 156),
- MTK_FUNCTION(0, "GPIO6"),
- MTK_FUNCTION(1, "PWRAP_SPICS2_B_I")
- ),
- MTK_PIN(
- PINCTRL_PIN(7, "SPI1_CSN"),
- "G19", "mt7623",
- MTK_EINT_FUNCTION(0, 153),
- MTK_FUNCTION(0, "GPIO7"),
- MTK_FUNCTION(1, "SPI1_CS")
- ),
- MTK_PIN(
- PINCTRL_PIN(8, "SPI1_MI"),
- "F19", "mt7623",
- MTK_EINT_FUNCTION(0, 154),
- MTK_FUNCTION(0, "GPIO8"),
- MTK_FUNCTION(1, "SPI1_MI"),
- MTK_FUNCTION(2, "SPI1_MO")
- ),
- MTK_PIN(
- PINCTRL_PIN(9, "SPI1_MO"),
- "G20", "mt7623",
- MTK_EINT_FUNCTION(0, 157),
- MTK_FUNCTION(0, "GPIO9"),
- MTK_FUNCTION(1, "SPI1_MO"),
- MTK_FUNCTION(2, "SPI1_MI")
- ),
- MTK_PIN(
- PINCTRL_PIN(10, "RTC32K_CK"),
- "A13", "mt7623",
- MTK_EINT_FUNCTION(0, 158),
- MTK_FUNCTION(0, "GPIO10"),
- MTK_FUNCTION(1, "RTC32K_CK")
- ),
- MTK_PIN(
- PINCTRL_PIN(11, "WATCHDOG"),
- "D14", "mt7623",
- MTK_EINT_FUNCTION(0, 159),
- MTK_FUNCTION(0, "GPIO11"),
- MTK_FUNCTION(1, "WATCHDOG")
- ),
- MTK_PIN(
- PINCTRL_PIN(12, "SRCLKENA"),
- "C13", "mt7623",
- MTK_EINT_FUNCTION(0, 169),
- MTK_FUNCTION(0, "GPIO12"),
- MTK_FUNCTION(1, "SRCLKENA")
- ),
- MTK_PIN(
- PINCTRL_PIN(13, "SRCLKENAI"),
- "B13", "mt7623",
- MTK_EINT_FUNCTION(0, 161),
- MTK_FUNCTION(0, "GPIO13"),
- MTK_FUNCTION(1, "SRCLKENAI")
- ),
- MTK_PIN(
- PINCTRL_PIN(14, "GPIO14"),
- "E18", "mt7623",
- MTK_EINT_FUNCTION(0, 162),
- MTK_FUNCTION(0, "GPIO14"),
- MTK_FUNCTION(1, "URXD2"),
- MTK_FUNCTION(2, "UTXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(15, "GPIO15"),
- "E17", "mt7623",
- MTK_EINT_FUNCTION(0, 163),
- MTK_FUNCTION(0, "GPIO15"),
- MTK_FUNCTION(1, "UTXD2"),
- MTK_FUNCTION(2, "URXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(16, "GPIO16"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO16")
- ),
- MTK_PIN(
- PINCTRL_PIN(17, "GPIO17"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO17")
- ),
- MTK_PIN(
- PINCTRL_PIN(18, "PCM_CLK"),
- "C19", "mt7623",
- MTK_EINT_FUNCTION(0, 166),
- MTK_FUNCTION(0, "GPIO18"),
- MTK_FUNCTION(1, "PCM_CLK0"),
- MTK_FUNCTION(6, "AP_PCM_CLKO")
- ),
- MTK_PIN(
- PINCTRL_PIN(19, "PCM_SYNC"),
- "D19", "mt7623",
- MTK_EINT_FUNCTION(0, 167),
- MTK_FUNCTION(0, "GPIO19"),
- MTK_FUNCTION(1, "PCM_SYNC"),
- MTK_FUNCTION(6, "AP_PCM_SYNC")
- ),
- MTK_PIN(
- PINCTRL_PIN(20, "PCM_RX"),
- "D18", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO20"),
- MTK_FUNCTION(1, "PCM_RX"),
- MTK_FUNCTION(4, "PCM_TX"),
- MTK_FUNCTION(6, "AP_PCM_RX")
- ),
- MTK_PIN(
- PINCTRL_PIN(21, "PCM_TX"),
- "C18", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO21"),
- MTK_FUNCTION(1, "PCM_TX"),
- MTK_FUNCTION(4, "PCM_RX"),
- MTK_FUNCTION(6, "AP_PCM_TX")
- ),
- MTK_PIN(
- PINCTRL_PIN(22, "EINT0"),
- "H15", "mt7623",
- MTK_EINT_FUNCTION(0, 0),
- MTK_FUNCTION(0, "GPIO22"),
- MTK_FUNCTION(1, "UCTS0"),
- MTK_FUNCTION(2, "PCIE0_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(23, "EINT1"),
- "J16", "mt7623",
- MTK_EINT_FUNCTION(0, 1),
- MTK_FUNCTION(0, "GPIO23"),
- MTK_FUNCTION(1, "URTS0"),
- MTK_FUNCTION(2, "PCIE1_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(24, "EINT2"),
- "H16", "mt7623",
- MTK_EINT_FUNCTION(0, 2),
- MTK_FUNCTION(0, "GPIO24"),
- MTK_FUNCTION(1, "UCTS1"),
- MTK_FUNCTION(2, "PCIE2_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(25, "EINT3"),
- "K15", "mt7623",
- MTK_EINT_FUNCTION(0, 3),
- MTK_FUNCTION(0, "GPIO25"),
- MTK_FUNCTION(1, "URTS1")
- ),
- MTK_PIN(
- PINCTRL_PIN(26, "EINT4"),
- "G15", "mt7623",
- MTK_EINT_FUNCTION(0, 4),
- MTK_FUNCTION(0, "GPIO26"),
- MTK_FUNCTION(1, "UCTS3"),
- MTK_FUNCTION(6, "PCIE2_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(27, "EINT5"),
- "F15", "mt7623",
- MTK_EINT_FUNCTION(0, 5),
- MTK_FUNCTION(0, "GPIO27"),
- MTK_FUNCTION(1, "URTS3"),
- MTK_FUNCTION(6, "PCIE1_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(28, "EINT6"),
- "J15", "mt7623",
- MTK_EINT_FUNCTION(0, 6),
- MTK_FUNCTION(0, "GPIO28"),
- MTK_FUNCTION(1, "DRV_VBUS"),
- MTK_FUNCTION(6, "PCIE0_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(29, "EINT7"),
- "E15", "mt7623",
- MTK_EINT_FUNCTION(0, 7),
- MTK_FUNCTION(0, "GPIO29"),
- MTK_FUNCTION(1, "IDDIG"),
- MTK_FUNCTION(2, "MSDC1_WP"),
- MTK_FUNCTION(6, "PCIE2_PERST_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(30, "GPIO30"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO30")
- ),
- MTK_PIN(
- PINCTRL_PIN(31, "GPIO31"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO31")
- ),
- MTK_PIN(
- PINCTRL_PIN(32, "GPIO32"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO32")
- ),
- MTK_PIN(
- PINCTRL_PIN(33, "I2S1_DATA"),
- "Y18", "mt7623",
- MTK_EINT_FUNCTION(0, 15),
- MTK_FUNCTION(0, "GPIO33"),
- MTK_FUNCTION(1, "I2S1_DATA"),
- MTK_FUNCTION(3, "PCM_TX"),
- MTK_FUNCTION(6, "AP_PCM_TX")
- ),
- MTK_PIN(
- PINCTRL_PIN(34, "I2S1_DATA_IN"),
- "Y17", "mt7623",
- MTK_EINT_FUNCTION(0, 16),
- MTK_FUNCTION(0, "GPIO34"),
- MTK_FUNCTION(1, "I2S1_DATA_IN"),
- MTK_FUNCTION(3, "PCM_RX"),
- MTK_FUNCTION(6, "AP_PCM_RX")
- ),
- MTK_PIN(
- PINCTRL_PIN(35, "I2S1_BCK"),
- "V17", "mt7623",
- MTK_EINT_FUNCTION(0, 17),
- MTK_FUNCTION(0, "GPIO35"),
- MTK_FUNCTION(1, "I2S1_BCK"),
- MTK_FUNCTION(3, "PCM_CLK0"),
- MTK_FUNCTION(6, "AP_PCM_CLKO")
- ),
- MTK_PIN(
- PINCTRL_PIN(36, "I2S1_LRCK"),
- "W17", "mt7623",
- MTK_EINT_FUNCTION(0, 18),
- MTK_FUNCTION(0, "GPIO36"),
- MTK_FUNCTION(1, "I2S1_LRCK"),
- MTK_FUNCTION(3, "PCM_SYNC"),
- MTK_FUNCTION(6, "AP_PCM_SYNC")
- ),
- MTK_PIN(
- PINCTRL_PIN(37, "I2S1_MCLK"),
- "AA18", "mt7623",
- MTK_EINT_FUNCTION(0, 19),
- MTK_FUNCTION(0, "GPIO37"),
- MTK_FUNCTION(1, "I2S1_MCLK")
- ),
- MTK_PIN(
- PINCTRL_PIN(38, "GPIO38"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO38")
- ),
- MTK_PIN(
- PINCTRL_PIN(39, "JTMS"),
- "G21", "mt7623",
- MTK_EINT_FUNCTION(0, 21),
- MTK_FUNCTION(0, "GPIO39"),
- MTK_FUNCTION(1, "JTMS")
- ),
- MTK_PIN(
- PINCTRL_PIN(40, "GPIO40"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO40")
- ),
- MTK_PIN(
- PINCTRL_PIN(41, "JTDI"),
- "H22", "mt7623",
- MTK_EINT_FUNCTION(0, 23),
- MTK_FUNCTION(0, "GPIO41"),
- MTK_FUNCTION(1, "JTDI")
- ),
- MTK_PIN(
- PINCTRL_PIN(42, "JTDO"),
- "H21", "mt7623",
- MTK_EINT_FUNCTION(0, 24),
- MTK_FUNCTION(0, "GPIO42"),
- MTK_FUNCTION(1, "JTDO")
- ),
- MTK_PIN(
- PINCTRL_PIN(43, "NCLE"),
- "C7", "mt7623",
- MTK_EINT_FUNCTION(0, 25),
- MTK_FUNCTION(0, "GPIO43"),
- MTK_FUNCTION(1, "NCLE"),
- MTK_FUNCTION(2, "EXT_XCS2")
- ),
- MTK_PIN(
- PINCTRL_PIN(44, "NCEB1"),
- "C6", "mt7623",
- MTK_EINT_FUNCTION(0, 26),
- MTK_FUNCTION(0, "GPIO44"),
- MTK_FUNCTION(1, "NCEB1"),
- MTK_FUNCTION(2, "IDDIG")
- ),
- MTK_PIN(
- PINCTRL_PIN(45, "NCEB0"),
- "D7", "mt7623",
- MTK_EINT_FUNCTION(0, 27),
- MTK_FUNCTION(0, "GPIO45"),
- MTK_FUNCTION(1, "NCEB0"),
- MTK_FUNCTION(2, "DRV_VBUS")
- ),
- MTK_PIN(
- PINCTRL_PIN(46, "IR"),
- "D15", "mt7623",
- MTK_EINT_FUNCTION(0, 28),
- MTK_FUNCTION(0, "GPIO46"),
- MTK_FUNCTION(1, "IR")
- ),
- MTK_PIN(
- PINCTRL_PIN(47, "NREB"),
- "A6", "mt7623",
- MTK_EINT_FUNCTION(0, 29),
- MTK_FUNCTION(0, "GPIO47"),
- MTK_FUNCTION(1, "NREB")
- ),
- MTK_PIN(
- PINCTRL_PIN(48, "NRNB"),
- "B6", "mt7623",
- MTK_EINT_FUNCTION(0, 30),
- MTK_FUNCTION(0, "GPIO48"),
- MTK_FUNCTION(1, "NRNB")
- ),
- MTK_PIN(
- PINCTRL_PIN(49, "I2S0_DATA"),
- "AB18", "mt7623",
- MTK_EINT_FUNCTION(0, 31),
- MTK_FUNCTION(0, "GPIO49"),
- MTK_FUNCTION(1, "I2S0_DATA"),
- MTK_FUNCTION(3, "PCM_TX"),
- MTK_FUNCTION(6, "AP_I2S_DO")
- ),
- MTK_PIN(
- PINCTRL_PIN(50, "GPIO50"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO50")
- ),
- MTK_PIN(
- PINCTRL_PIN(51, "GPIO51"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO51")
- ),
- MTK_PIN(
- PINCTRL_PIN(52, "GPIO52"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO52")
- ),
- MTK_PIN(
- PINCTRL_PIN(53, "SPI0_CSN"),
- "E7", "mt7623",
- MTK_EINT_FUNCTION(0, 35),
- MTK_FUNCTION(0, "GPIO53"),
- MTK_FUNCTION(1, "SPI0_CS"),
- MTK_FUNCTION(5, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(54, "SPI0_CK"),
- "F7", "mt7623",
- MTK_EINT_FUNCTION(0, 36),
- MTK_FUNCTION(0, "GPIO54"),
- MTK_FUNCTION(1, "SPI0_CK")
- ),
- MTK_PIN(
- PINCTRL_PIN(55, "SPI0_MI"),
- "E6", "mt7623",
- MTK_EINT_FUNCTION(0, 37),
- MTK_FUNCTION(0, "GPIO55"),
- MTK_FUNCTION(1, "SPI0_MI"),
- MTK_FUNCTION(2, "SPI0_MO"),
- MTK_FUNCTION(3, "MSDC1_WP"),
- MTK_FUNCTION(5, "PWM2")
- ),
- MTK_PIN(
- PINCTRL_PIN(56, "SPI0_MO"),
- "G7", "mt7623",
- MTK_EINT_FUNCTION(0, 38),
- MTK_FUNCTION(0, "GPIO56"),
- MTK_FUNCTION(1, "SPI0_MO"),
- MTK_FUNCTION(2, "SPI0_MI")
- ),
- MTK_PIN(
- PINCTRL_PIN(57, "GPIO57"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO57")
- ),
- MTK_PIN(
- PINCTRL_PIN(58, "GPIO58"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO58")
- ),
- MTK_PIN(
- PINCTRL_PIN(59, "GPIO59"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO59")
- ),
- MTK_PIN(
- PINCTRL_PIN(60, "WB_RSTB"),
- "Y21", "mt7623",
- MTK_EINT_FUNCTION(0, 41),
- MTK_FUNCTION(0, "GPIO60"),
- MTK_FUNCTION(1, "WB_RSTB")
- ),
- MTK_PIN(
- PINCTRL_PIN(61, "GPIO61"),
- "AA21", "mt7623",
- MTK_EINT_FUNCTION(0, 42),
- MTK_FUNCTION(0, "GPIO61"),
- MTK_FUNCTION(1, "TEST_FD")
- ),
- MTK_PIN(
- PINCTRL_PIN(62, "GPIO62"),
- "AB22", "mt7623",
- MTK_EINT_FUNCTION(0, 43),
- MTK_FUNCTION(0, "GPIO62"),
- MTK_FUNCTION(1, "TEST_FC")
- ),
- MTK_PIN(
- PINCTRL_PIN(63, "WB_SCLK"),
- "AC23", "mt7623",
- MTK_EINT_FUNCTION(0, 44),
- MTK_FUNCTION(0, "GPIO63"),
- MTK_FUNCTION(1, "WB_SCLK")
- ),
- MTK_PIN(
- PINCTRL_PIN(64, "WB_SDATA"),
- "AB21", "mt7623",
- MTK_EINT_FUNCTION(0, 45),
- MTK_FUNCTION(0, "GPIO64"),
- MTK_FUNCTION(1, "WB_SDATA")
- ),
- MTK_PIN(
- PINCTRL_PIN(65, "WB_SEN"),
- "AB24", "mt7623",
- MTK_EINT_FUNCTION(0, 46),
- MTK_FUNCTION(0, "GPIO65"),
- MTK_FUNCTION(1, "WB_SEN")
- ),
- MTK_PIN(
- PINCTRL_PIN(66, "WB_CRTL0"),
- "AB20", "mt7623",
- MTK_EINT_FUNCTION(0, 47),
- MTK_FUNCTION(0, "GPIO66"),
- MTK_FUNCTION(1, "WB_CRTL0")
- ),
- MTK_PIN(
- PINCTRL_PIN(67, "WB_CRTL1"),
- "AC20", "mt7623",
- MTK_EINT_FUNCTION(0, 48),
- MTK_FUNCTION(0, "GPIO67"),
- MTK_FUNCTION(1, "WB_CRTL1")
- ),
- MTK_PIN(
- PINCTRL_PIN(68, "WB_CRTL2"),
- "AB19", "mt7623",
- MTK_EINT_FUNCTION(0, 49),
- MTK_FUNCTION(0, "GPIO68"),
- MTK_FUNCTION(1, "WB_CRTL2")
- ),
- MTK_PIN(
- PINCTRL_PIN(69, "WB_CRTL3"),
- "AC19", "mt7623",
- MTK_EINT_FUNCTION(0, 50),
- MTK_FUNCTION(0, "GPIO69"),
- MTK_FUNCTION(1, "WB_CRTL3")
- ),
- MTK_PIN(
- PINCTRL_PIN(70, "WB_CRTL4"),
- "AD19", "mt7623",
- MTK_EINT_FUNCTION(0, 51),
- MTK_FUNCTION(0, "GPIO70"),
- MTK_FUNCTION(1, "WB_CRTL4")
- ),
- MTK_PIN(
- PINCTRL_PIN(71, "WB_CRTL5"),
- "AE19", "mt7623",
- MTK_EINT_FUNCTION(0, 52),
- MTK_FUNCTION(0, "GPIO71"),
- MTK_FUNCTION(1, "WB_CRTL5")
- ),
- MTK_PIN(
- PINCTRL_PIN(72, "I2S0_DATA_IN"),
- "AA20", "mt7623",
- MTK_EINT_FUNCTION(0, 53),
- MTK_FUNCTION(0, "GPIO72"),
- MTK_FUNCTION(1, "I2S0_DATA_IN"),
- MTK_FUNCTION(3, "PCM_RX"),
- MTK_FUNCTION(4, "PWM0"),
- MTK_FUNCTION(5, "DISP_PWM"),
- MTK_FUNCTION(6, "AP_I2S_DI")
- ),
- MTK_PIN(
- PINCTRL_PIN(73, "I2S0_LRCK"),
- "Y20", "mt7623",
- MTK_EINT_FUNCTION(0, 54),
- MTK_FUNCTION(0, "GPIO73"),
- MTK_FUNCTION(1, "I2S0_LRCK"),
- MTK_FUNCTION(3, "PCM_SYNC"),
- MTK_FUNCTION(6, "AP_I2S_LRCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(74, "I2S0_BCK"),
- "Y19", "mt7623",
- MTK_EINT_FUNCTION(0, 55),
- MTK_FUNCTION(0, "GPIO74"),
- MTK_FUNCTION(1, "I2S0_BCK"),
- MTK_FUNCTION(3, "PCM_CLK0"),
- MTK_FUNCTION(6, "AP_I2S_BCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(75, "SDA0"),
- "K19", "mt7623",
- MTK_EINT_FUNCTION(0, 56),
- MTK_FUNCTION(0, "GPIO75"),
- MTK_FUNCTION(1, "SDA0")
- ),
- MTK_PIN(
- PINCTRL_PIN(76, "SCL0"),
- "K20", "mt7623",
- MTK_EINT_FUNCTION(0, 57),
- MTK_FUNCTION(0, "GPIO76"),
- MTK_FUNCTION(1, "SCL0")
- ),
- MTK_PIN(
- PINCTRL_PIN(77, "GPIO77"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO77")
- ),
- MTK_PIN(
- PINCTRL_PIN(78, "GPIO78"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO78")
- ),
- MTK_PIN(
- PINCTRL_PIN(79, "GPIO79"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO79")
- ),
- MTK_PIN(
- PINCTRL_PIN(80, "GPIO80"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO80")
- ),
- MTK_PIN(
- PINCTRL_PIN(81, "GPIO81"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO81")
- ),
- MTK_PIN(
- PINCTRL_PIN(82, "GPIO82"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO82")
- ),
- MTK_PIN(
- PINCTRL_PIN(83, "LCM_RST"),
- "V16", "mt7623",
- MTK_EINT_FUNCTION(0, 64),
- MTK_FUNCTION(0, "GPIO83"),
- MTK_FUNCTION(1, "LCM_RST")
- ),
- MTK_PIN(
- PINCTRL_PIN(84, "DSI_TE"),
- "V14", "mt7623",
- MTK_EINT_FUNCTION(0, 65),
- MTK_FUNCTION(0, "GPIO84"),
- MTK_FUNCTION(1, "DSI_TE")
- ),
- MTK_PIN(
- PINCTRL_PIN(85, "GPIO85"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO85")
- ),
- MTK_PIN(
- PINCTRL_PIN(86, "GPIO86"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO86")
- ),
- MTK_PIN(
- PINCTRL_PIN(87, "GPIO87"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO87")
- ),
- MTK_PIN(
- PINCTRL_PIN(88, "GPIO88"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO88")
- ),
- MTK_PIN(
- PINCTRL_PIN(89, "GPIO89"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO89")
- ),
- MTK_PIN(
- PINCTRL_PIN(90, "GPIO90"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO90")
- ),
- MTK_PIN(
- PINCTRL_PIN(91, "GPIO91"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO91")
- ),
- MTK_PIN(
- PINCTRL_PIN(92, "GPIO92"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO92")
- ),
- MTK_PIN(
- PINCTRL_PIN(93, "GPIO93"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO93")
- ),
- MTK_PIN(
- PINCTRL_PIN(94, "GPIO94"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO94")
- ),
- MTK_PIN(
- PINCTRL_PIN(95, "MIPI_TCN"),
- "AB14", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO95"),
- MTK_FUNCTION(1, "TCN")
- ),
- MTK_PIN(
- PINCTRL_PIN(96, "MIPI_TCP"),
- "AC14", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO96"),
- MTK_FUNCTION(1, "TCP")
- ),
- MTK_PIN(
- PINCTRL_PIN(97, "MIPI_TDN1"),
- "AE15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO97"),
- MTK_FUNCTION(1, "TDN1")
- ),
- MTK_PIN(
- PINCTRL_PIN(98, "MIPI_TDP1"),
- "AD15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO98"),
- MTK_FUNCTION(1, "TDP1")
- ),
- MTK_PIN(
- PINCTRL_PIN(99, "MIPI_TDN0"),
- "AB15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO99"),
- MTK_FUNCTION(1, "TDN0")
- ),
- MTK_PIN(
- PINCTRL_PIN(100, "MIPI_TDP0"),
- "AC15", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO100"),
- MTK_FUNCTION(1, "TDP0")
- ),
- MTK_PIN(
- PINCTRL_PIN(101, "GPIO101"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO101")
- ),
- MTK_PIN(
- PINCTRL_PIN(102, "GPIO102"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO102")
- ),
- MTK_PIN(
- PINCTRL_PIN(103, "GPIO103"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO103")
- ),
- MTK_PIN(
- PINCTRL_PIN(104, "GPIO104"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO104")
- ),
- MTK_PIN(
- PINCTRL_PIN(105, "MSDC1_CMD"),
- "AD2", "mt7623",
- MTK_EINT_FUNCTION(0, 78),
- MTK_FUNCTION(0, "GPIO105"),
- MTK_FUNCTION(1, "MSDC1_CMD"),
- MTK_FUNCTION(3, "SDA1"),
- MTK_FUNCTION(6, "I2SOUT_BCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(106, "MSDC1_CLK"),
- "AD3", "mt7623",
- MTK_EINT_FUNCTION(0, 79),
- MTK_FUNCTION(0, "GPIO106"),
- MTK_FUNCTION(1, "MSDC1_CLK"),
- MTK_FUNCTION(3, "SCL1"),
- MTK_FUNCTION(6, "I2SOUT_LRCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(107, "MSDC1_DAT0"),
- "AE2", "mt7623",
- MTK_EINT_FUNCTION(0, 80),
- MTK_FUNCTION(0, "GPIO107"),
- MTK_FUNCTION(1, "MSDC1_DAT0"),
- MTK_FUNCTION(5, "UTXD0"),
- MTK_FUNCTION(6, "I2SOUT_DATA_OUT")
- ),
- MTK_PIN(
- PINCTRL_PIN(108, "MSDC1_DAT1"),
- "AC1", "mt7623",
- MTK_EINT_FUNCTION(0, 81),
- MTK_FUNCTION(0, "GPIO108"),
- MTK_FUNCTION(1, "MSDC1_DAT1"),
- MTK_FUNCTION(3, "PWM0"),
- MTK_FUNCTION(5, "URXD0"),
- MTK_FUNCTION(6, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(109, "MSDC1_DAT2"),
- "AC3", "mt7623",
- MTK_EINT_FUNCTION(0, 82),
- MTK_FUNCTION(0, "GPIO109"),
- MTK_FUNCTION(1, "MSDC1_DAT2"),
- MTK_FUNCTION(3, "SDA2"),
- MTK_FUNCTION(5, "UTXD1"),
- MTK_FUNCTION(6, "PWM2")
- ),
- MTK_PIN(
- PINCTRL_PIN(110, "MSDC1_DAT3"),
- "AC4", "mt7623",
- MTK_EINT_FUNCTION(0, 83),
- MTK_FUNCTION(0, "GPIO110"),
- MTK_FUNCTION(1, "MSDC1_DAT3"),
- MTK_FUNCTION(3, "SCL2"),
- MTK_FUNCTION(5, "URXD1"),
- MTK_FUNCTION(6, "PWM3")
- ),
- MTK_PIN(
- PINCTRL_PIN(111, "MSDC0_DAT7"),
- "A2", "mt7623",
- MTK_EINT_FUNCTION(0, 84),
- MTK_FUNCTION(0, "GPIO111"),
- MTK_FUNCTION(1, "MSDC0_DAT7"),
- MTK_FUNCTION(4, "NLD7")
- ),
- MTK_PIN(
- PINCTRL_PIN(112, "MSDC0_DAT6"),
- "B3", "mt7623",
- MTK_EINT_FUNCTION(0, 85),
- MTK_FUNCTION(0, "GPIO112"),
- MTK_FUNCTION(1, "MSDC0_DAT6"),
- MTK_FUNCTION(4, "NLD6")
- ),
- MTK_PIN(
- PINCTRL_PIN(113, "MSDC0_DAT5"),
- "C4", "mt7623",
- MTK_EINT_FUNCTION(0, 86),
- MTK_FUNCTION(0, "GPIO113"),
- MTK_FUNCTION(1, "MSDC0_DAT5"),
- MTK_FUNCTION(4, "NLD5")
- ),
- MTK_PIN(
- PINCTRL_PIN(114, "MSDC0_DAT4"),
- "A4", "mt7623",
- MTK_EINT_FUNCTION(0, 87),
- MTK_FUNCTION(0, "GPIO114"),
- MTK_FUNCTION(1, "MSDC0_DAT4"),
- MTK_FUNCTION(4, "NLD4")
- ),
- MTK_PIN(
- PINCTRL_PIN(115, "MSDC0_RSTB"),
- "C5", "mt7623",
- MTK_EINT_FUNCTION(0, 88),
- MTK_FUNCTION(0, "GPIO115"),
- MTK_FUNCTION(1, "MSDC0_RSTB"),
- MTK_FUNCTION(4, "NLD8")
- ),
- MTK_PIN(
- PINCTRL_PIN(116, "MSDC0_CMD"),
- "D5", "mt7623",
- MTK_EINT_FUNCTION(0, 89),
- MTK_FUNCTION(0, "GPIO116"),
- MTK_FUNCTION(1, "MSDC0_CMD"),
- MTK_FUNCTION(4, "NALE")
- ),
- MTK_PIN(
- PINCTRL_PIN(117, "MSDC0_CLK"),
- "B1", "mt7623",
- MTK_EINT_FUNCTION(0, 90),
- MTK_FUNCTION(0, "GPIO117"),
- MTK_FUNCTION(1, "MSDC0_CLK"),
- MTK_FUNCTION(4, "NWEB")
- ),
- MTK_PIN(
- PINCTRL_PIN(118, "MSDC0_DAT3"),
- "D6", "mt7623",
- MTK_EINT_FUNCTION(0, 91),
- MTK_FUNCTION(0, "GPIO118"),
- MTK_FUNCTION(1, "MSDC0_DAT3"),
- MTK_FUNCTION(4, "NLD3")
- ),
- MTK_PIN(
- PINCTRL_PIN(119, "MSDC0_DAT2"),
- "B2", "mt7623",
- MTK_EINT_FUNCTION(0, 92),
- MTK_FUNCTION(0, "GPIO119"),
- MTK_FUNCTION(1, "MSDC0_DAT2"),
- MTK_FUNCTION(4, "NLD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(120, "MSDC0_DAT1"),
- "A3", "mt7623",
- MTK_EINT_FUNCTION(0, 93),
- MTK_FUNCTION(0, "GPIO120"),
- MTK_FUNCTION(1, "MSDC0_DAT1"),
- MTK_FUNCTION(4, "NLD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(121, "MSDC0_DAT0"),
- "B4", "mt7623",
- MTK_EINT_FUNCTION(0, 94),
- MTK_FUNCTION(0, "GPIO121"),
- MTK_FUNCTION(1, "MSDC0_DAT0"),
- MTK_FUNCTION(4, "NLD0"),
- MTK_FUNCTION(5, "WATCHDOG")
- ),
- MTK_PIN(
- PINCTRL_PIN(122, "GPIO122"),
- "H17", "mt7623",
- MTK_EINT_FUNCTION(0, 95),
- MTK_FUNCTION(0, "GPIO122"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SDA2"),
- MTK_FUNCTION(5, "URXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(123, "GPIO123"),
- "F17", "mt7623",
- MTK_EINT_FUNCTION(0, 96),
- MTK_FUNCTION(0, "GPIO123"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SCL2"),
- MTK_FUNCTION(5, "UTXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(124, "GPIO124"),
- "H18", "mt7623",
- MTK_EINT_FUNCTION(0, 97),
- MTK_FUNCTION(0, "GPIO124"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SDA1"),
- MTK_FUNCTION(5, "PWM3")
- ),
- MTK_PIN(
- PINCTRL_PIN(125, "GPIO125"),
- "G17", "mt7623",
- MTK_EINT_FUNCTION(0, 98),
- MTK_FUNCTION(0, "GPIO125"),
- MTK_FUNCTION(1, "TEST"),
- MTK_FUNCTION(4, "SCL1"),
- MTK_FUNCTION(5, "PWM4")
- ),
- MTK_PIN(
- PINCTRL_PIN(126, "I2S0_MCLK"),
- "AA19", "mt7623",
- MTK_EINT_FUNCTION(0, 99),
- MTK_FUNCTION(0, "GPIO126"),
- MTK_FUNCTION(1, "I2S0_MCLK"),
- MTK_FUNCTION(6, "AP_I2S_MCLK")
- ),
- MTK_PIN(
- PINCTRL_PIN(127, "GPIO127"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO127")
- ),
- MTK_PIN(
- PINCTRL_PIN(128, "GPIO128"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO128")
- ),
- MTK_PIN(
- PINCTRL_PIN(129, "GPIO129"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO129")
- ),
- MTK_PIN(
- PINCTRL_PIN(130, "GPIO130"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO130")
- ),
- MTK_PIN(
- PINCTRL_PIN(131, "GPIO131"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO131")
- ),
- MTK_PIN(
- PINCTRL_PIN(132, "GPIO132"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO132")
- ),
- MTK_PIN(
- PINCTRL_PIN(133, "GPIO133"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO133")
- ),
- MTK_PIN(
- PINCTRL_PIN(134, "GPIO134"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO134")
- ),
- MTK_PIN(
- PINCTRL_PIN(135, "GPIO135"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO135")
- ),
- MTK_PIN(
- PINCTRL_PIN(136, "GPIO136"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO136")
- ),
- MTK_PIN(
- PINCTRL_PIN(137, "GPIO137"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO137")
- ),
- MTK_PIN(
- PINCTRL_PIN(138, "GPIO138"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO138")
- ),
- MTK_PIN(
- PINCTRL_PIN(139, "GPIO139"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO139")
- ),
- MTK_PIN(
- PINCTRL_PIN(140, "GPIO140"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO140")
- ),
- MTK_PIN(
- PINCTRL_PIN(141, "GPIO141"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO141")
- ),
- MTK_PIN(
- PINCTRL_PIN(142, "GPIO142"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO142")
- ),
- MTK_PIN(
- PINCTRL_PIN(143, "GPIO143"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO143")
- ),
- MTK_PIN(
- PINCTRL_PIN(144, "GPIO144"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO144")
- ),
- MTK_PIN(
- PINCTRL_PIN(145, "GPIO145"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO145")
- ),
- MTK_PIN(
- PINCTRL_PIN(146, "GPIO146"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO146")
- ),
- MTK_PIN(
- PINCTRL_PIN(147, "GPIO147"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO147")
- ),
- MTK_PIN(
- PINCTRL_PIN(148, "GPIO148"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO148")
- ),
- MTK_PIN(
- PINCTRL_PIN(149, "GPIO149"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO149")
- ),
- MTK_PIN(
- PINCTRL_PIN(150, "GPIO150"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO150")
- ),
- MTK_PIN(
- PINCTRL_PIN(151, "GPIO151"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO151")
- ),
- MTK_PIN(
- PINCTRL_PIN(152, "GPIO152"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO152")
- ),
- MTK_PIN(
- PINCTRL_PIN(153, "GPIO153"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO153")
- ),
- MTK_PIN(
- PINCTRL_PIN(154, "GPIO154"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO154")
- ),
- MTK_PIN(
- PINCTRL_PIN(155, "GPIO155"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO155")
- ),
- MTK_PIN(
- PINCTRL_PIN(156, "GPIO156"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO156")
- ),
- MTK_PIN(
- PINCTRL_PIN(157, "GPIO157"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO157")
- ),
- MTK_PIN(
- PINCTRL_PIN(158, "GPIO158"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO158")
- ),
- MTK_PIN(
- PINCTRL_PIN(159, "GPIO159"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO159")
- ),
- MTK_PIN(
- PINCTRL_PIN(160, "GPIO160"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO160")
- ),
- MTK_PIN(
- PINCTRL_PIN(161, "GPIO161"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO161")
- ),
- MTK_PIN(
- PINCTRL_PIN(162, "GPIO162"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO162")
- ),
- MTK_PIN(
- PINCTRL_PIN(163, "GPIO163"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO163")
- ),
- MTK_PIN(
- PINCTRL_PIN(164, "GPIO164"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO164")
- ),
- MTK_PIN(
- PINCTRL_PIN(165, "GPIO165"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO165")
- ),
- MTK_PIN(
- PINCTRL_PIN(166, "GPIO166"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO166")
- ),
- MTK_PIN(
- PINCTRL_PIN(167, "GPIO167"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO167")
- ),
- MTK_PIN(
- PINCTRL_PIN(168, "GPIO168"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO168")
- ),
- MTK_PIN(
- PINCTRL_PIN(169, "GPIO169"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO169")
- ),
- MTK_PIN(
- PINCTRL_PIN(170, "GPIO170"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO170")
- ),
- MTK_PIN(
- PINCTRL_PIN(171, "GPIO171"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO171")
- ),
- MTK_PIN(
- PINCTRL_PIN(172, "GPIO172"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO172")
- ),
- MTK_PIN(
- PINCTRL_PIN(173, "GPIO173"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO173")
- ),
- MTK_PIN(
- PINCTRL_PIN(174, "GPIO174"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO174")
- ),
- MTK_PIN(
- PINCTRL_PIN(175, "GPIO175"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO175")
- ),
- MTK_PIN(
- PINCTRL_PIN(176, "GPIO176"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO176")
- ),
- MTK_PIN(
- PINCTRL_PIN(177, "GPIO177"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO177")
- ),
- MTK_PIN(
- PINCTRL_PIN(178, "GPIO178"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO178")
- ),
- MTK_PIN(
- PINCTRL_PIN(179, "GPIO179"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO179")
- ),
- MTK_PIN(
- PINCTRL_PIN(180, "GPIO180"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO180")
- ),
- MTK_PIN(
- PINCTRL_PIN(181, "GPIO181"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO181")
- ),
- MTK_PIN(
- PINCTRL_PIN(182, "GPIO182"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO182")
- ),
- MTK_PIN(
- PINCTRL_PIN(183, "GPIO183"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO183")
- ),
- MTK_PIN(
- PINCTRL_PIN(184, "GPIO184"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO184")
- ),
- MTK_PIN(
- PINCTRL_PIN(185, "GPIO185"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO185")
- ),
- MTK_PIN(
- PINCTRL_PIN(186, "GPIO186"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO186")
- ),
- MTK_PIN(
- PINCTRL_PIN(187, "GPIO187"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO187")
- ),
- MTK_PIN(
- PINCTRL_PIN(188, "GPIO188"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO188")
- ),
- MTK_PIN(
- PINCTRL_PIN(189, "GPIO189"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO189")
- ),
- MTK_PIN(
- PINCTRL_PIN(190, "GPIO190"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO190")
- ),
- MTK_PIN(
- PINCTRL_PIN(191, "GPIO191"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO191")
- ),
- MTK_PIN(
- PINCTRL_PIN(192, "GPIO192"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO192")
- ),
- MTK_PIN(
- PINCTRL_PIN(193, "GPIO193"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO193")
- ),
- MTK_PIN(
- PINCTRL_PIN(194, "GPIO194"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO194")
- ),
- MTK_PIN(
- PINCTRL_PIN(195, "GPIO195"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO195")
- ),
- MTK_PIN(
- PINCTRL_PIN(196, "GPIO196"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO196")
- ),
- MTK_PIN(
- PINCTRL_PIN(197, "GPIO197"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO197")
- ),
- MTK_PIN(
- PINCTRL_PIN(198, "GPIO198"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO198")
- ),
- MTK_PIN(
- PINCTRL_PIN(199, "SPI1_CK"),
- "E19", "mt7623",
- MTK_EINT_FUNCTION(0, 111),
- MTK_FUNCTION(0, "GPIO199"),
- MTK_FUNCTION(1, "SPI1_CK")
- ),
- MTK_PIN(
- PINCTRL_PIN(200, "URXD2"),
- "K18", "mt7623",
- MTK_EINT_FUNCTION(0, 112),
- MTK_FUNCTION(0, "GPIO200"),
- MTK_FUNCTION(6, "URXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(201, "UTXD2"),
- "L18", "mt7623",
- MTK_EINT_FUNCTION(0, 113),
- MTK_FUNCTION(0, "GPIO201"),
- MTK_FUNCTION(6, "UTXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(202, "GPIO202"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO202")
- ),
- MTK_PIN(
- PINCTRL_PIN(203, "PWM0"),
- "AA16", "mt7623",
- MTK_EINT_FUNCTION(0, 115),
- MTK_FUNCTION(0, "GPIO203"),
- MTK_FUNCTION(1, "PWM0"),
- MTK_FUNCTION(2, "DISP_PWM")
- ),
- MTK_PIN(
- PINCTRL_PIN(204, "PWM1"),
- "Y16", "mt7623",
- MTK_EINT_FUNCTION(0, 116),
- MTK_FUNCTION(0, "GPIO204"),
- MTK_FUNCTION(1, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(205, "PWM2"),
- "AA15", "mt7623",
- MTK_EINT_FUNCTION(0, 117),
- MTK_FUNCTION(0, "GPIO205"),
- MTK_FUNCTION(1, "PWM2")
- ),
- MTK_PIN(
- PINCTRL_PIN(206, "PWM3"),
- "AA17", "mt7623",
- MTK_EINT_FUNCTION(0, 118),
- MTK_FUNCTION(0, "GPIO206"),
- MTK_FUNCTION(1, "PWM3")
- ),
- MTK_PIN(
- PINCTRL_PIN(207, "PWM4"),
- "Y15", "mt7623",
- MTK_EINT_FUNCTION(0, 119),
- MTK_FUNCTION(0, "GPIO207"),
- MTK_FUNCTION(1, "PWM4")
- ),
- MTK_PIN(
- PINCTRL_PIN(208, "AUD_EXT_CK1"),
- "W14", "mt7623",
- MTK_EINT_FUNCTION(0, 120),
- MTK_FUNCTION(0, "GPIO208"),
- MTK_FUNCTION(1, "AUD_EXT_CK1"),
- MTK_FUNCTION(2, "PWM0"),
- MTK_FUNCTION(3, "PCIE0_PERST_N"),
- MTK_FUNCTION(5, "DISP_PWM")
- ),
- MTK_PIN(
- PINCTRL_PIN(209, "AUD_EXT_CK2"),
- "V15", "mt7623",
- MTK_EINT_FUNCTION(0, 121),
- MTK_FUNCTION(0, "GPIO209"),
- MTK_FUNCTION(1, "AUD_EXT_CK2"),
- MTK_FUNCTION(2, "MSDC1_WP"),
- MTK_FUNCTION(3, "PCIE1_PERST_N"),
- MTK_FUNCTION(5, "PWM1")
- ),
- MTK_PIN(
- PINCTRL_PIN(210, "GPIO210"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO210")
- ),
- MTK_PIN(
- PINCTRL_PIN(211, "GPIO211"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO211")
- ),
- MTK_PIN(
- PINCTRL_PIN(212, "GPIO212"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO212")
- ),
- MTK_PIN(
- PINCTRL_PIN(213, "GPIO213"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO213")
- ),
- MTK_PIN(
- PINCTRL_PIN(214, "GPIO214"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO214")
- ),
- MTK_PIN(
- PINCTRL_PIN(215, "GPIO215"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO215")
- ),
- MTK_PIN(
- PINCTRL_PIN(216, "GPIO216"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO216")
- ),
- MTK_PIN(
- PINCTRL_PIN(217, "GPIO217"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO217")
- ),
- MTK_PIN(
- PINCTRL_PIN(218, "GPIO218"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO218")
- ),
- MTK_PIN(
- PINCTRL_PIN(219, "GPIO219"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO219")
- ),
- MTK_PIN(
- PINCTRL_PIN(220, "GPIO220"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO220")
- ),
- MTK_PIN(
- PINCTRL_PIN(221, "GPIO221"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO221")
- ),
- MTK_PIN(
- PINCTRL_PIN(222, "GPIO222"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO222")
- ),
- MTK_PIN(
- PINCTRL_PIN(223, "GPIO223"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO223")
- ),
- MTK_PIN(
- PINCTRL_PIN(224, "GPIO224"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO224")
- ),
- MTK_PIN(
- PINCTRL_PIN(225, "GPIO225"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO225")
- ),
- MTK_PIN(
- PINCTRL_PIN(226, "GPIO226"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO226")
- ),
- MTK_PIN(
- PINCTRL_PIN(227, "GPIO227"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO227")
- ),
- MTK_PIN(
- PINCTRL_PIN(228, "GPIO228"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO228")
- ),
- MTK_PIN(
- PINCTRL_PIN(229, "GPIO229"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO229")
- ),
- MTK_PIN(
- PINCTRL_PIN(230, "GPIO230"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO230")
- ),
- MTK_PIN(
- PINCTRL_PIN(231, "GPIO231"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO231")
- ),
- MTK_PIN(
- PINCTRL_PIN(232, "GPIO232"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO232")
- ),
- MTK_PIN(
- PINCTRL_PIN(233, "GPIO233"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO233")
- ),
- MTK_PIN(
- PINCTRL_PIN(234, "GPIO234"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO234")
- ),
- MTK_PIN(
- PINCTRL_PIN(235, "GPIO235"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO235")
- ),
- MTK_PIN(
- PINCTRL_PIN(236, "EXT_SDIO3"),
- "A8", "mt7623",
- MTK_EINT_FUNCTION(0, 122),
- MTK_FUNCTION(0, "GPIO236"),
- MTK_FUNCTION(1, "EXT_SDIO3"),
- MTK_FUNCTION(2, "IDDIG")
- ),
- MTK_PIN(
- PINCTRL_PIN(237, "EXT_SDIO2"),
- "D8", "mt7623",
- MTK_EINT_FUNCTION(0, 123),
- MTK_FUNCTION(0, "GPIO237"),
- MTK_FUNCTION(1, "EXT_SDIO2"),
- MTK_FUNCTION(2, "DRV_VBUS")
- ),
- MTK_PIN(
- PINCTRL_PIN(238, "EXT_SDIO1"),
- "D9", "mt7623",
- MTK_EINT_FUNCTION(0, 124),
- MTK_FUNCTION(0, "GPIO238"),
- MTK_FUNCTION(1, "EXT_SDIO1")
- ),
- MTK_PIN(
- PINCTRL_PIN(239, "EXT_SDIO0"),
- "B8", "mt7623",
- MTK_EINT_FUNCTION(0, 125),
- MTK_FUNCTION(0, "GPIO239"),
- MTK_FUNCTION(1, "EXT_SDIO0")
- ),
- MTK_PIN(
- PINCTRL_PIN(240, "EXT_XCS"),
- "C9", "mt7623",
- MTK_EINT_FUNCTION(0, 126),
- MTK_FUNCTION(0, "GPIO240"),
- MTK_FUNCTION(1, "EXT_XCS")
- ),
- MTK_PIN(
- PINCTRL_PIN(241, "EXT_SCK"),
- "C8", "mt7623",
- MTK_EINT_FUNCTION(0, 127),
- MTK_FUNCTION(0, "GPIO241"),
- MTK_FUNCTION(1, "EXT_SCK")
- ),
- MTK_PIN(
- PINCTRL_PIN(242, "URTS2"),
- "G18", "mt7623",
- MTK_EINT_FUNCTION(0, 128),
- MTK_FUNCTION(0, "GPIO242"),
- MTK_FUNCTION(1, "URTS2"),
- MTK_FUNCTION(2, "UTXD3"),
- MTK_FUNCTION(3, "URXD3"),
- MTK_FUNCTION(4, "SCL1")
- ),
- MTK_PIN(
- PINCTRL_PIN(243, "UCTS2"),
- "H19", "mt7623",
- MTK_EINT_FUNCTION(0, 129),
- MTK_FUNCTION(0, "GPIO243"),
- MTK_FUNCTION(1, "UCTS2"),
- MTK_FUNCTION(2, "URXD3"),
- MTK_FUNCTION(3, "UTXD3"),
- MTK_FUNCTION(4, "SDA1")
- ),
- MTK_PIN(
- PINCTRL_PIN(244, "GPIO244"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO244")
- ),
- MTK_PIN(
- PINCTRL_PIN(245, "GPIO245"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO245")
- ),
- MTK_PIN(
- PINCTRL_PIN(246, "GPIO246"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO246")
- ),
- MTK_PIN(
- PINCTRL_PIN(247, "GPIO247"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO247")
- ),
- MTK_PIN(
- PINCTRL_PIN(248, "GPIO248"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO248")
- ),
- MTK_PIN(
- PINCTRL_PIN(249, "GPIO249"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO249")
- ),
- MTK_PIN(
- PINCTRL_PIN(250, "GPIO250"),
- "A15", "mt7623",
- MTK_EINT_FUNCTION(0, 135),
- MTK_FUNCTION(0, "GPIO250"),
- MTK_FUNCTION(1, "TEST_MD7"),
- MTK_FUNCTION(6, "PCIE0_CLKREQ_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(251, "GPIO251"),
- "B15", "mt7623",
- MTK_EINT_FUNCTION(0, 136),
- MTK_FUNCTION(0, "GPIO251"),
- MTK_FUNCTION(1, "TEST_MD6"),
- MTK_FUNCTION(6, "PCIE0_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(252, "GPIO252"),
- "C16", "mt7623",
- MTK_EINT_FUNCTION(0, 137),
- MTK_FUNCTION(0, "GPIO252"),
- MTK_FUNCTION(1, "TEST_MD5"),
- MTK_FUNCTION(6, "PCIE1_CLKREQ_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(253, "GPIO253"),
- "D17", "mt7623",
- MTK_EINT_FUNCTION(0, 138),
- MTK_FUNCTION(0, "GPIO253"),
- MTK_FUNCTION(1, "TEST_MD4"),
- MTK_FUNCTION(6, "PCIE1_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(254, "GPIO254"),
- "D16", "mt7623",
- MTK_EINT_FUNCTION(0, 139),
- MTK_FUNCTION(0, "GPIO254"),
- MTK_FUNCTION(1, "TEST_MD3"),
- MTK_FUNCTION(6, "PCIE2_CLKREQ_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(255, "GPIO255"),
- "C17", "mt7623",
- MTK_EINT_FUNCTION(0, 140),
- MTK_FUNCTION(0, "GPIO255"),
- MTK_FUNCTION(1, "TEST_MD2"),
- MTK_FUNCTION(6, "PCIE2_WAKE_N")
- ),
- MTK_PIN(
- PINCTRL_PIN(256, "GPIO256"),
- "B17", "mt7623",
- MTK_EINT_FUNCTION(0, 141),
- MTK_FUNCTION(0, "GPIO256"),
- MTK_FUNCTION(1, "TEST_MD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(257, "GPIO257"),
- "C15", "mt7623",
- MTK_EINT_FUNCTION(0, 142),
- MTK_FUNCTION(0, "GPIO257"),
- MTK_FUNCTION(1, "TEST_MD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(258, "GPIO258"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO258")
- ),
- MTK_PIN(
- PINCTRL_PIN(259, "GPIO259"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO259")
- ),
- MTK_PIN(
- PINCTRL_PIN(260, "GPIO260"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO260")
- ),
- MTK_PIN(
- PINCTRL_PIN(261, "MSDC1_INS"),
- "AD1", "mt7623",
- MTK_EINT_FUNCTION(0, 146),
- MTK_FUNCTION(0, "GPIO261"),
- MTK_FUNCTION(1, "MSDC1_INS")
- ),
- MTK_PIN(
- PINCTRL_PIN(262, "G2_TXEN"),
- "A23", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO262"),
- MTK_FUNCTION(1, "G2_TXEN")
- ),
- MTK_PIN(
- PINCTRL_PIN(263, "G2_TXD3"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO263"),
- MTK_FUNCTION(1, "G2_TXD3")
- ),
- MTK_PIN(
- PINCTRL_PIN(264, "G2_TXD2"),
- "C24", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO264"),
- MTK_FUNCTION(1, "G2_TXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(265, "G2_TXD1"),
- "B25", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO265"),
- MTK_FUNCTION(1, "G2_TXD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(266, "G2_TXD0"),
- "A24", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO266"),
- MTK_FUNCTION(1, "G2_TXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(267, "G2_TXCLK"),
- "C23", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO267"),
- MTK_FUNCTION(1, "G2_TXC")
- ),
- MTK_PIN(
- PINCTRL_PIN(268, "G2_RXCLK"),
- "B23", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO268"),
- MTK_FUNCTION(1, "G2_RXC")
- ),
- MTK_PIN(
- PINCTRL_PIN(269, "G2_RXD0"),
- "D21", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO269"),
- MTK_FUNCTION(1, "G2_RXD0")
- ),
- MTK_PIN(
- PINCTRL_PIN(270, "G2_RXD1"),
- "B22", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO270"),
- MTK_FUNCTION(1, "G2_RXD1")
- ),
- MTK_PIN(
- PINCTRL_PIN(271, "G2_RXD2"),
- "A22", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO271"),
- MTK_FUNCTION(1, "G2_RXD2")
- ),
- MTK_PIN(
- PINCTRL_PIN(272, "G2_RXD3"),
- "C22", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO272"),
- MTK_FUNCTION(1, "G2_RXD3")
- ),
- MTK_PIN(
- PINCTRL_PIN(273, "GPIO273"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO273")
- ),
- MTK_PIN(
- PINCTRL_PIN(274, "G2_RXDV"),
- "C21", "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO274"),
- MTK_FUNCTION(1, "G2_RXDV")
- ),
- MTK_PIN(
- PINCTRL_PIN(275, "G2_MDC"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO275"),
- MTK_FUNCTION(1, "MDC")
- ),
- MTK_PIN(
- PINCTRL_PIN(276, "G2_MDIO"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO276"),
- MTK_FUNCTION(1, "MDIO")
- ),
- MTK_PIN(
- PINCTRL_PIN(277, "GPIO277"),
- NULL, "mt7623",
- MTK_EINT_FUNCTION(NO_EINT_SUPPORT, NO_EINT_SUPPORT),
- MTK_FUNCTION(0, "GPIO277")
- ),
- MTK_PIN(
- PINCTRL_PIN(278, "JTAG_RESET"),
- "H20", "mt7623",
- MTK_EINT_FUNCTION(0, 147),
- MTK_FUNCTION(0, "GPIO278"),
- MTK_FUNCTION(1, "JTAG_RESET")
- ),
-};
-
-#endif /* __PINCTRL_MTK_MT7623_H */
--
1.9.1
^ permalink raw reply related
* [PATCH v2 01/30] pinctrl: mediatek: Add missing pinctrl bindings for mt7623
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493198774-4478-1-git-send-email-sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
Add missing pinctrl binding these which would be used in
devicetree related files.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
include/dt-bindings/pinctrl/mt7623-pinfunc.h | 30 ++++++++++++++++++++++++----
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/include/dt-bindings/pinctrl/mt7623-pinfunc.h b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
index 2f00bdc..436a87b 100644
--- a/include/dt-bindings/pinctrl/mt7623-pinfunc.h
+++ b/include/dt-bindings/pinctrl/mt7623-pinfunc.h
@@ -185,6 +185,12 @@
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO (MTK_PIN_NO(56) | 1)
#define MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MI (MTK_PIN_NO(56) | 2)
+#define MT7623_PIN_57_SDA1_FUNC_GPIO57 (MTK_PIN_NO(57) | 0)
+#define MT7623_PIN_57_SDA1_FUNC_SDA1 (MTK_PIN_NO(57) | 1)
+
+#define MT7623_PIN_58_SCL1_FUNC_GPIO58 (MTK_PIN_NO(58) | 0)
+#define MT7623_PIN_58_SCL1_FUNC_SCL1 (MTK_PIN_NO(58) | 1)
+
#define MT7623_PIN_60_WB_RSTB_FUNC_GPIO60 (MTK_PIN_NO(60) | 0)
#define MT7623_PIN_60_WB_RSTB_FUNC_WB_RSTB (MTK_PIN_NO(60) | 1)
@@ -244,6 +250,22 @@
#define MT7623_PIN_76_SCL0_FUNC_GPIO76 (MTK_PIN_NO(76) | 0)
#define MT7623_PIN_76_SCL0_FUNC_SCL0 (MTK_PIN_NO(76) | 1)
+#define MT7623_PIN_79_URXD0_FUNC_GPIO79 (MTK_PIN_NO(79) | 0)
+#define MT7623_PIN_79_URXD0_FUNC_URXD0 (MTK_PIN_NO(79) | 1)
+#define MT7623_PIN_79_URXD0_FUNC_UTXD0 (MTK_PIN_NO(79) | 2)
+
+#define MT7623_PIN_80_UTXD0_FUNC_GPIO80 (MTK_PIN_NO(80) | 0)
+#define MT7623_PIN_80_UTXD0_FUNC_UTXD0 (MTK_PIN_NO(80) | 1)
+#define MT7623_PIN_80_UTXD0_FUNC_URXD0 (MTK_PIN_NO(80) | 2)
+
+#define MT7623_PIN_81_URXD1_FUNC_GPIO81 (MTK_PIN_NO(81) | 0)
+#define MT7623_PIN_81_URXD1_FUNC_URXD1 (MTK_PIN_NO(81) | 1)
+#define MT7623_PIN_81_URXD1_FUNC_UTXD1 (MTK_PIN_NO(81) | 2)
+
+#define MT7623_PIN_82_UTXD1_FUNC_GPIO82 (MTK_PIN_NO(82) | 0)
+#define MT7623_PIN_82_UTXD1_FUNC_UTXD1 (MTK_PIN_NO(82) | 1)
+#define MT7623_PIN_82_UTXD1_FUNC_URXD1 (MTK_PIN_NO(82) | 2)
+
#define MT7623_PIN_83_LCM_RST_FUNC_GPIO83 (MTK_PIN_NO(83) | 0)
#define MT7623_PIN_83_LCM_RST_FUNC_LCM_RST (MTK_PIN_NO(83) | 1)
@@ -351,10 +373,10 @@
#define MT7623_PIN_122_GPIO122_FUNC_SDA2 (MTK_PIN_NO(122) | 4)
#define MT7623_PIN_122_GPIO122_FUNC_URXD0 (MTK_PIN_NO(122) | 5)
-#define MT7623_PIN_123_GPIO123_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
-#define MT7623_PIN_123_GPIO123_FUNC_TEST (MTK_PIN_NO(123) | 1)
-#define MT7623_PIN_123_GPIO123_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
-#define MT7623_PIN_123_GPIO123_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
+#define MT7623_PIN_123_HTPLG_FUNC_GPIO123 (MTK_PIN_NO(123) | 0)
+#define MT7623_PIN_123_HTPLG_FUNC_HTPLG (MTK_PIN_NO(123) | 1)
+#define MT7623_PIN_123_HTPLG_FUNC_SCL2 (MTK_PIN_NO(123) | 4)
+#define MT7623_PIN_123_HTPLG_FUNC_UTXD0 (MTK_PIN_NO(123) | 5)
#define MT7623_PIN_124_GPIO124_FUNC_GPIO124 (MTK_PIN_NO(124) | 0)
#define MT7623_PIN_124_GPIO124_FUNC_TEST (MTK_PIN_NO(124) | 1)
--
1.9.1
^ permalink raw reply related
* [PATCH v2 00/30] arm: dts: extend mt7623 support
From: sean.wang at mediatek.com @ 2017-04-26 9:25 UTC (permalink / raw)
To: linux-arm-kernel
From: Sean Wang <sean.wang@mediatek.com>
Changes since v1:
Continue the upstream journey based on the previous John Crispin's good work.
- add fixes for the v1 suggestion
- fix typo in the commit log
- add missing pinctrl bindings for mt7623
- reuse pinctrl driver for mt7623
- enhance existing nodes since the way for binding is changed e.g USB
- add more nodes which already gets support from the latest tree e.g MT7530 DSA
- add the dts file for Bananapi R2 (BPI-R2) board
This series extends the dts files used for booting mt7623 base boards.
Since support for mt7623 was added around v4.6, many new drivers have
been accepted upstream. The contained patches add several of these to
the devicetree.
Additionally the series does a bit of refactoring. Mediatek pointed out
that the evaluation board is infact a reference design and asked the the
evb files be renamed to rfb.
As with all of the current ARM bases MTK silicon, these boards also have
a PMIC. Instead of adding the nodes to all of the dts files, we add an
intermediate dtsi file that contains the required nodes. This allows us
to reduce the size of the top most dts files.
The RFB comes in various versions and asiarf has even done a crowdfunder
to sell them. We should try to reduce the duplication. This series adds
a common dtsi file for these boards. This results in the topmost dts files
only needing to specify the compatible string, MTD nodes and ethernet setup.
John Crispin (14):
arm: dts: mt7623: add clock controller device nodes
arm: dts: mt7623: add subsystem clock controller device nodes
arm: dts: mt7623: add power domain controller device node
arm: dts: mt7623: add clock-frequency to the a7 timer node to
mt7623.dtsi
arm: dts: mt7623: add pinctrl nodes to the mt7623 dtsi file
arm: dts: mt7623: add pmic wrapper nodes to the mt7623 dtsi file
arm: dts: mt7623: add i2c nodes to the mt7623.dtsi file
arm: dts: mt7623: add nand nodes to the mt7623.dtsi file
arm: dts: mt7623: add mmc nodes to the mt7623.dtsi file
arm: dts: mt7623: add usb nodes to the mt7623.dtsi file
arm: dts: mt7623: add mt7623-mt6323.dtsi file
arm: dts: mt7623: cleanup the mt7623n rfb uart nodes
arm: dts: mt7623: enable the usb device on the mt7623n rfb
arm: dts: mt7623: enable the nand device on the mt7623n nand rfb
Sean Wang (16):
pinctrl: mediatek: Add missing pinctrl bindings for mt7623
pinctrl: mediatek: reuse pinctrl driver for mt7623
arm: dts: mt7623: add spi nodes to the mt7623.dtsi file
arm: dts: mt7623: add pwm nodes to the mt7623.dtsi file
arm: dts: mt7623: add ethernet nodes to the mt7623.dtsi file
arm: dts: mt7623: add crypto engine nodes to the mt7623.dtsi file
arm: dts: mt7623: add ir nodes to the mt7623.dtsi file
arm: dts: mt7623: add afe nodes to the mt7623.dtsi file
arm: dts: mt7623: add rng nodes to the mt7623.dtsi file
arm: dts: mt7623: add auxadc nodes to the mt7623.dtsi file
arm: dts: mt7623: add efuse nodes to the mt7623.dtsi file
arm: dts: mt7623: add thermal nodes to the mt7623.dtsi file
arm: dts: mt7623: add Sean as one of authors for mt7623.dtsi files
arm: dts: mt7623: rename mt7623-evb.dts to
arch/arm/boot/dts/mt7623n-rfb.dtsi
dt-bindings: add vendor prefix for bananapi
arm: dts: mt7623: add dts file for Bananapi R2 (BPI-R2) board
Documentation/devicetree/bindings/arm/mediatek.txt | 8 +-
.../devicetree/bindings/pinctrl/pinctrl-mt65xx.txt | 1 -
.../devicetree/bindings/vendor-prefixes.txt | 1 +
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/mt7623-evb.dts | 33 -
arch/arm/boot/dts/mt7623-mt6323.dtsi | 269 +++
arch/arm/boot/dts/mt7623.dtsi | 556 +++++-
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 478 +++++
arch/arm/boot/dts/mt7623n-rfb-nand.dts | 109 ++
arch/arm/boot/dts/mt7623n-rfb.dtsi | 61 +
arch/arm/mach-mediatek/mediatek.c | 4 +-
arch/arm/mach-mediatek/platsmp.c | 2 +-
drivers/pinctrl/mediatek/Kconfig | 9 +-
drivers/pinctrl/mediatek/Makefile | 1 -
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 379 ----
drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h | 1936 --------------------
include/dt-bindings/pinctrl/mt7623-pinfunc.h | 30 +-
17 files changed, 1497 insertions(+), 2383 deletions(-)
delete mode 100644 arch/arm/boot/dts/mt7623-evb.dts
create mode 100644 arch/arm/boot/dts/mt7623-mt6323.dtsi
create mode 100644 arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
create mode 100644 arch/arm/boot/dts/mt7623n-rfb-nand.dts
create mode 100644 arch/arm/boot/dts/mt7623n-rfb.dtsi
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7623.c
delete mode 100644 drivers/pinctrl/mediatek/pinctrl-mtk-mt7623.h
--
1.9.1
^ permalink raw reply
* [PATCH v4 5/7] pinctrl: aramda-37xx: Add irqchip support
From: Gregory CLEMENT @ 2017-04-26 9:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZ=mVXBbVf1iHg8nQ6pYUkvpB+egH+stoMrkD8V_vaYpg@mail.gmail.com>
Hi Linus,
On lun., avril 24 2017, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Wed, Apr 5, 2017 at 5:18 PM, Gregory CLEMENT
> <gregory.clement@free-electrons.com> wrote:
>
>> The Armada 37xx SoCs can handle interrupt through GPIO. However it can
>> only manage the edge ones.
>>
>> The way the interrupt are managed are classical so we can use the generic
>> interrupt chip model.
>>
>> The only unusual "feature" is that many interrupts are connected to the
>> parent interrupt controller. But we do not take advantage of this and use
>> the chained irq with all of them.
>>
>> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
>
> There are some issues with this patch.
>
> First:
> You need to add
> select GPIOLIB_IRQCHIP
> to the Kconfig entry. It's only working in your setup
> because something else is selecting this for you, probably.
It is done in patch 2 "arm64: marvell: enable the Armada 37xx pinctrl
driver".
>
> At all places like this:
>
>> + u32 mask = d->mask;
> (...)
>> + if (on)
>> + val |= mask;
>> + else
>> + val &= ~mask;
>
> Isn't it simpler to just use d->mask directly in the code and skip the local
> variable?
>
> if (on)
> val |= d->mask;
> (...)
Yes sure I cand do it.
>
>> +static void armada_37xx_irq_handler(struct irq_desc *desc)
>> +{
>> + struct gpio_chip *gc = irq_desc_get_handler_data(desc);
>> + struct irq_chip *chip = irq_desc_get_chip(desc);
>> + struct armada_37xx_pinctrl *info = gpiochip_get_data(gc);
>> + struct irq_domain *d = gc->irqdomain;
>> + int i;
>> +
>> + chained_irq_enter(chip, desc);
>> + for (i = 0; i <= d->revmap_size / GPIO_PER_REG; i++) {
>> + u32 status;
>> + unsigned long flags;
>> +
>> + spin_lock_irqsave(&info->irq_lock, flags);
>> + status = readl_relaxed(info->base + IRQ_STATUS + 4 * i);
>> + /* Manage only the interrupt that was enabled */
>> + status &= readl_relaxed(info->base + IRQ_EN + 4 * i);
>> + spin_unlock_irqrestore(&info->irq_lock, flags);
>> + while (status) {
>> + u32 hwirq = ffs(status) - 1;
>> + u32 virq = irq_find_mapping(d, hwirq +
>> + i * GPIO_PER_REG);
>> +
>> + generic_handle_irq(virq);
>> + status &= ~BIT(hwirq);
>> + }
>
> You hae a problem here is a new IRQ appears while you are inside
> of this loop. You need to re-read the status register for each iteration
> (and &= with the IRQ_EN I guess).
If a new IRQ appears during the loop, then the irq handler will be
called again because the cause of this new IRQ won't have been acked
yet. So I think we're fine here.
>
>> +static int armada_37xx_irqchip_register(struct platform_device *pdev,
>> + struct armada_37xx_pinctrl *info)
>> +{
>> + struct device_node *np = info->dev->of_node;
>> + int nrirqs = info->data->nr_pins;
>> + struct gpio_chip *gc = &info->gpio_chip;
>> + struct irq_chip *irqchip = &info->irq_chip;
>> + struct resource res;
>> + int ret = -ENODEV, i, nr_irq_parent;
>> +
>
> This warrants a comment:
> /* Check if we have at least one gpio-controller child node */
>
OK
>> + for_each_child_of_node(info->dev->of_node, np) {
>> + if (of_find_property(np, "gpio-controller", NULL)) {
>> + ret = 0;
>> + break;
>> + }
>
> Rewrite:
>
> if (of_property_read_bool(np, "gpio-controller"))
>
OK
Gregory
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 3/5] dt-bindings: stm32-dma: Add property to handle STM32 DMAMUX
From: Pierre Yves MORDRET @ 2017-04-26 9:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170320213722.oj3ipmslbw2mp27d@rob-hp-laptop>
On 03/20/2017 10:37 PM, Rob Herring wrote:
> On Mon, Mar 13, 2017 at 03:15:59PM +0100, M'boumba Cedric Madianga wrote:
>> This patch adds an optional property needed for STM32 DMA controller
>> addressed via STM32 DMAMUX.
>>
>> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>> ---
>> Documentation/devicetree/bindings/dma/stm32-dma.txt | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/dma/stm32-dma.txt b/Documentation/devicetree/bindings/dma/stm32-dma.txt
>> index 4408af6..7b5e91a 100644
>> --- a/Documentation/devicetree/bindings/dma/stm32-dma.txt
>> +++ b/Documentation/devicetree/bindings/dma/stm32-dma.txt
>> @@ -16,6 +16,9 @@ Optional properties:
>> - resets: Reference to a reset controller asserting the DMA controller
>> - st,mem2mem: boolean; if defined, it indicates that the controller supports
>> memory-to-memory transfer
>> +- st,dmamux: boolean; if defined, it indicates that the controller is behind a
>> + DMA multiplexer. In that case, using dma instances doesn't work for DMA
>> + clients. They have to use dma-router instances.
>
> This should not be needed for the same reason we don't need anything
> like this for chained interrupt controllers.
>
> Also, the compatible string should be specific enough to provide this
> information.
>
> Rob
I don't understand what you're meant here. Our DMAs can work with or
without DMAMUX driver. Driver uses this binding to use it or not.
Py
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
>
^ permalink raw reply
* [PATCH] iommu/arm-smmu-v3: Increase SMMU CMD queue poll timeout
From: Sunil Kovvuri @ 2017-04-26 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170424170518.GU12323@arm.com>
On Mon, Apr 24, 2017 at 10:35 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Mon, Apr 24, 2017 at 10:26:53PM +0530, Sunil Kovvuri wrote:
>> On Mon, Apr 24, 2017 at 9:38 PM, Will Deacon <will.deacon@arm.com> wrote:
>> > On Mon, Apr 24, 2017 at 05:29:36PM +0530, Geetha sowjanya wrote:
>> >> From: Geetha <gakula@cavium.com>
>> >>
>> >> When large memory is being unmapped, huge no of tlb invalidation cmds are
>> >> submitted followed by a SYNC command. This sometimes hits CMD queue full and
>> >> poll on queue drain is being timedout throwing error message 'CMD_SYNC timeout'.
>> >>
>> >> Although there is no functional issue, error message confuses user. Hence increased
>> >> poll timeout to 500us
>> >
>> > Hmm, what are you doing to unmap that much? Is this VFIO teardown? Do you
>> > have 7c6d90e2bb1a ("iommu/io-pgtable-arm: Fix iova_to_phys for block
>> > entries") applied?
>>
>> Yes it's VFIO teardown and again yes the above fix is applied.
>> But i didn't get how above fix is related.
>> TLB invalidation commands are submitted at 'arm_smmu_tlb_inv_range_nosync()'
>> and it's a loop over granule size.
>>
>> 1357 do {
>> 1358 arm_smmu_cmdq_issue_cmd(smmu, &cmd);
>> 1359 cmd.tlbi.addr += granule;
>> 1360 } while (size -= granule);
>>
>> So if invalidation size is big then huge no of invalidation commands
>> will be submitted
>> irrespective of fix that you pointed above, right ?
>
> VFIO has some logic to batch up invalidations, but this didn't work properly
> for us without the fix above. However, I guess you have a huge memory range
> that's mapped with 2M sections or something, so there are still loads of
> entries to invalidate.
>
> I would much prefer it if VFIO could just teardown the whole address space
> so that we could do an invalidate all, but there's a chicken-and-egg problem
> with page accounting iirc.
>
We can definitely look into this from VFIO perspective but for now I am guessing
this patch is fine, as no functionality is being changed.
What do you say ?
Thanks,
Sunil.
^ permalink raw reply
* [PATCH] reset: sti: Use devm_kcalloc() in syscfg_reset_controller_register()
From: Philipp Zabel @ 2017-04-26 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e10a20a2-cfea-5b42-db3a-41b6eb08d7e4@users.sourceforge.net>
On Wed, 2017-04-26 at 10:05 +0200, SF Markus Elfring wrote:
> From: Markus Elfring <elfring@users.sourceforge.net>
> Date: Wed, 26 Apr 2017 09:50:34 +0200
>
> * A multiplication for the size determination of a memory allocation
> indicated that an array data structure should be processed.
> Thus use the corresponding function "devm_kcalloc".
>
> * Replace the specification of a data structure by a pointer dereference
> to make the corresponding size determination a bit safer according to
> the Linux coding style convention.
>
> * Delete the local variable "size" which became unnecessary with
> this refactoring.
>
> Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
> ---
> drivers/reset/sti/reset-syscfg.c | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/reset/sti/reset-syscfg.c b/drivers/reset/sti/reset-syscfg.c
> index 9bd57a5eee72..7e0f2aa55ba7 100644
> --- a/drivers/reset/sti/reset-syscfg.c
> +++ b/drivers/reset/sti/reset-syscfg.c
> @@ -145,16 +145,14 @@ static int syscfg_reset_controller_register(struct device *dev,
> const struct syscfg_reset_controller_data *data)
> {
> struct syscfg_reset_controller *rc;
> - size_t size;
> int i, err;
>
> rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
> if (!rc)
> return -ENOMEM;
>
> - size = sizeof(struct syscfg_reset_channel) * data->nr_channels;
> -
> - rc->channels = devm_kzalloc(dev, size, GFP_KERNEL);
> + rc->channels = devm_kcalloc(dev, data->nr_channels,
> + sizeof(*rc->channels), GFP_KERNEL);
> if (!rc->channels)
> return -ENOMEM;
>
Thank you, I have applied this to the reset/next branch. The same change
could be made in the ti-syscon reset driver.
regards
Philipp
^ permalink raw reply
* [PATCH 2/5] dmaengine: Add STM32 DMAMUX driver
From: Pierre Yves MORDRET @ 2017-04-26 9:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170406064046.GF4094@localhost>
On 04/06/2017 08:40 AM, Vinod Koul wrote:
> On Mon, Mar 13, 2017 at 03:15:58PM +0100, M'boumba Cedric Madianga wrote:
>> This patch implements the STM32 DMAMUX driver
>
> Can you describe the controller here pls
OK. Will be done in V2
>
>>
>> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>> ---
>> drivers/dma/Kconfig | 9 ++
>> drivers/dma/Makefile | 1 +
>> drivers/dma/stm32-dmamux.c | 231 +++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 241 insertions(+)
>> create mode 100644 drivers/dma/stm32-dmamux.c
>>
>> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
>> index fc3435c..6ab80c9 100644
>> --- a/drivers/dma/Kconfig
>> +++ b/drivers/dma/Kconfig
>> @@ -461,6 +461,15 @@ config STM32_DMA
>> If you have a board based on such a MCU and wish to use DMA say Y
>> here.
>>
>> +config STM32_DMAMUX
>> + bool "STMicroelectronics STM32 dma multiplexer support"
>> + depends on STM32_DMA
>
> can you add compile test here so that we can get better compile coverage
OK. Will be done in V2
>
>> + help
>> + Enable support for the on-chip DMA multiplexer on STMicroelectronics
>> + STM32 MCUs.
>> + If you have a board based on such a MCU and wish to use DMAMUX say Y
>> + here.
>> +
>> config S3C24XX_DMAC
>> bool "Samsung S3C24XX DMA support"
>> depends on ARCH_S3C24XX || COMPILE_TEST
>> diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
>> index 0b723e9..449c7a3 100644
>> --- a/drivers/dma/Makefile
>> +++ b/drivers/dma/Makefile
>> @@ -57,6 +57,7 @@ obj-$(CONFIG_RENESAS_DMA) += sh/
>> obj-$(CONFIG_SIRF_DMA) += sirf-dma.o
>> obj-$(CONFIG_STE_DMA40) += ste_dma40.o ste_dma40_ll.o
>> obj-$(CONFIG_STM32_DMA) += stm32-dma.o
>> +obj-$(CONFIG_STM32_DMAMUX) += stm32-dmamux.o
>> obj-$(CONFIG_S3C24XX_DMAC) += s3c24xx-dma.o
>> obj-$(CONFIG_TXX9_DMAC) += txx9dmac.o
>> obj-$(CONFIG_TEGRA20_APB_DMA) += tegra20-apb-dma.o
>> diff --git a/drivers/dma/stm32-dmamux.c b/drivers/dma/stm32-dmamux.c
>> new file mode 100644
>> index 0000000..3003546
>> --- /dev/null
>> +++ b/drivers/dma/stm32-dmamux.c
>> @@ -0,0 +1,231 @@
>> +/*
>> + * DMA Router driver for STM32 DMA MUX
>> + *
>> + * Copyright (C) 2015 M'Boumba Cedric Madianga <cedric.madianga@gmail.com>
>
> we are in '17 now :)
OK. Will be done in V2
>
>> + *
>> + * Based on LPC18xx/43xx DMA MUX and TI DMA XBAR
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/of_device.h>
>> +#include <linux/of_dma.h>
>> +#include <linux/reset.h>
>> +#include <linux/slab.h>
>> +
>> +#define STM32_DMAMUX_CCR(x) (0x4 * (x))
>> +#define STM32_DMAMUX_MAX_CHANNELS 32
>> +#define STM32_DMAMUX_MAX_REQUESTS 255
>> +
>> +struct stm32_dmamux {
>> + u32 chan_id;
>> + u32 request;
>> + bool busy;
>> +};
>> +
>> +struct stm32_dmamux_data {
>> + struct dma_router dmarouter;
>> + struct stm32_dmamux *muxes;
>> + struct clk *clk;
>> + void __iomem *iomem;
>> + u32 dmamux_requests; /* number of DMA requests connected to DMAMUX */
>> + u32 dmamux_channels; /* Number of DMA channels supported */
>> +};
>> +
>> +static inline u32 stm32_dmamux_read(void __iomem *iomem, u32 reg)
>> +{
>> + return readl_relaxed(iomem + reg);
>> +}
>> +
>> +static inline void stm32_dmamux_write(void __iomem *iomem, u32 reg, u32 val)
>> +{
>> + writel_relaxed(val, iomem + reg);
>> +}
>> +
>> +static void stm32_dmamux_free(struct device *dev, void *route_data)
>> +{
>> + struct stm32_dmamux_data *dmamux = dev_get_drvdata(dev);
>> + struct stm32_dmamux *mux = route_data;
>> +
>> + /* Clear dma request for the right channel */
>> + stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id), 0);
>> + clk_disable(dmamux->clk);
>> + mux->busy = false;
>> +
>> + dev_dbg(dev, "Unmapping dma-router%dchan%d (was routed to request%d)\n",
>> + dev->id, mux->chan_id, mux->request);
>> +}
>> +
>> +static void *stm32_dmamux_route_allocate(struct of_phandle_args *dma_spec,
>> + struct of_dma *ofdma)
>> +{
>> + struct platform_device *pdev = of_find_device_by_node(ofdma->of_node);
>> + struct stm32_dmamux_data *dmamux = platform_get_drvdata(pdev);
>> + struct stm32_dmamux *mux;
>> + u32 chan_id;
>> + int ret;
>> +
>> + if (dma_spec->args_count != 4) {
>> + dev_err(&pdev->dev, "invalid number of dma mux args\n");
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + if (dma_spec->args[0] >= dmamux->dmamux_channels) {
>> + dev_err(&pdev->dev, "invalid channel id: %d\n",
>> + dma_spec->args[0]);
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + if (dma_spec->args[1] > dmamux->dmamux_requests) {
>> + dev_err(&pdev->dev, "invalid mux request number: %d\n",
>> + dma_spec->args[1]);
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + /* The of_node_put() will be done in of_dma_router_xlate function */
>> + dma_spec->np = of_parse_phandle(ofdma->of_node, "dma-masters", 0);
>> + if (!dma_spec->np) {
>> + dev_err(&pdev->dev, "can't get dma master\n");
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + chan_id = dma_spec->args[0];
>> + mux = &dmamux->muxes[chan_id];
>> + mux->chan_id = chan_id;
>> + mux->request = dma_spec->args[1];
>> +
>> + if (mux->busy) {
>> + dev_err(&pdev->dev, "dma channel %d busy with request %d\n",
>> + chan_id, mux->request);
>> + return ERR_PTR(-EBUSY);
>> + }
>> +
>> + ret = clk_enable(dmamux->clk);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
>> + return ERR_PTR(ret);
>> + }
>> +
>> + stm32_dmamux_write(dmamux->iomem, STM32_DMAMUX_CCR(mux->chan_id),
>> + mux->request);
>> + mux->busy = true;
>> +
>> + dev_dbg(&pdev->dev, "Mapping dma-router%dchan%d to request%d\n",
>> + pdev->dev.id, mux->chan_id, mux->request);
>> +
>> + return mux;
>> +}
>> +
>> +static int stm32_dmamux_probe(struct platform_device *pdev)
>> +{
>> + struct device_node *dma_node, *node = pdev->dev.of_node;
>> + struct stm32_dmamux_data *dmamux;
>> + struct reset_control *rst;
>> + struct resource *res;
>> + int ret;
>> +
>> + if (!node)
>> + return -ENODEV;
>> +
>> + dmamux = devm_kzalloc(&pdev->dev, sizeof(struct stm32_dmamux_data),
>> + GFP_KERNEL);
>> + if (!dmamux)
>> + return -ENOMEM;
>> +
>> + dma_node = of_parse_phandle(node, "dma-masters", 0);
>> + if (!dma_node) {
>> + dev_err(&pdev->dev, "Can't get DMA master node\n");
>> + return -ENODEV;
>> + }
>> + of_node_put(dma_node);
>> +
>> + ret = of_property_read_u32(node, "dma-channels",
>> + &dmamux->dmamux_channels);
>
> can we have property_xxx calls alone, that way driver is not strictly
> dependent on of
Can you please explain what you are asking for ? Not sure to understand
correctly.
>
>> + if (ret)
>> + dmamux->dmamux_channels = STM32_DMAMUX_MAX_CHANNELS;
>> +
>> + ret = of_property_read_u32(node, "dma-requests",
>> + &dmamux->dmamux_requests);
>> + if (ret)
>> + dmamux->dmamux_requests = STM32_DMAMUX_MAX_REQUESTS;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res)
>> + return -ENODEV;
>> +
>> + dmamux->iomem = devm_ioremap_resource(&pdev->dev, res);
>> + if (!dmamux->iomem)
>> + return -ENOMEM;
>> +
>> + dmamux->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(dmamux->clk)) {
>> + dev_err(&pdev->dev, "Missing controller clock\n");
>> + return PTR_ERR(dmamux->clk);
>> + }
>> + ret = clk_prepare(dmamux->clk);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "clk_prep failed: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + dmamux->muxes = devm_kcalloc(&pdev->dev, dmamux->dmamux_channels,
>> + sizeof(struct stm32_dmamux),
>> + GFP_KERNEL);
>> + if (!dmamux->muxes)
>> + return -ENOMEM;
>> +
>> + rst = devm_reset_control_get(&pdev->dev, NULL);
>> + if (!IS_ERR(rst)) {
>> + ret = clk_enable(dmamux->clk);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
>> + return ret;
>> + }
>> + reset_control_assert(rst);
>> + udelay(2);
>> + reset_control_deassert(rst);
>> + clk_disable(dmamux->clk);
>> + }
>> +
>> + dmamux->dmarouter.dev = &pdev->dev;
>> + dmamux->dmarouter.route_free = stm32_dmamux_free;
>> + platform_set_drvdata(pdev, dmamux);
>> +
>> + ret = of_dma_router_register(node, stm32_dmamux_route_allocate,
>> + &dmamux->dmarouter);
>> + if (ret < 0) {
>> + dev_err(&pdev->dev,
>> + "STM32 DMAMUX DMA OF registration failed %d\n", ret);
>> + return ret;
>> + }
>> +
>> + dev_info(&pdev->dev, "STM32 DMAMUX driver registered\n");
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id stm32_dmamux_match[] = {
>> + { .compatible = "st,stm32-dmamux" },
>> + {},
>> +};
>> +
>> +static struct platform_driver stm32_dmamux_driver = {
>> + .probe = stm32_dmamux_probe,
>> + .driver = {
>> + .name = "stm32-dmamux",
>> + .of_match_table = stm32_dmamux_match,
>> + },
>> +};
>> +
>> +static int __init stm32_dmamux_init(void)
>> +{
>> + return platform_driver_register(&stm32_dmamux_driver);
>> +}
>> +arch_initcall(stm32_dmamux_init);
>
> why not module init, wouldnt defer probe solve the dependencies
>
The reason behind many devices (device_initcall level) rely on DMAs. If
init is deferred DMAMUX driver will be probed twice if dependents rely
on it. This sounds not a good call. This explains arch_initcall level.
^ permalink raw reply
* [PATCH v2] iommu/arm-smmu: Return IOVA in iova_to_phys when SMMU is bypassed
From: Sunil Kovvuri @ 2017-04-26 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493114272-30093-1-git-send-email-sunil.kovvuri@gmail.com>
On Tue, Apr 25, 2017 at 3:27 PM, <sunil.kovvuri@gmail.com> wrote:
> From: Sunil Goutham <sgoutham@cavium.com>
>
> For software initiated address translation, when domain type is
> IOMMU_DOMAIN_IDENTITY i.e SMMU is bypassed, mimic HW behavior
> i.e return the same IOVA as translated address.
>
> This patch is an extension to Will Deacon's patchset
> "Implement SMMU passthrough using the default domain".
>
> Signed-off-by: Sunil Goutham <sgoutham@cavium.com>
> ---
>
> V2
> - As per Will's suggestion applied fix to SMMUv3 driver as well.
>
> drivers/iommu/arm-smmu-v3.c | 3 +++
> drivers/iommu/arm-smmu.c | 3 +++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
> index 05b4592..d412bdd 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -1714,6 +1714,9 @@ arm_smmu_iova_to_phys(struct iommu_domain *domain, dma_addr_t iova)
> struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
> struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops;
>
> + if (domain->type == IOMMU_DOMAIN_IDENTITY)
> + return iova;
> +
> if (!ops)
> return 0;
>
> diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index bfab4f7..81088cd 100644
> --- a/drivers/iommu/arm-smmu.c
> +++ b/drivers/iommu/arm-smmu.c
> @@ -1459,6 +1459,9 @@ static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
> struct arm_smmu_domain *smmu_domain = to_smmu_domain(domain);
> struct io_pgtable_ops *ops= smmu_domain->pgtbl_ops;
>
> + if (domain->type == IOMMU_DOMAIN_IDENTITY)
> + return iova;
> +
> if (!ops)
> return 0;
>
> --
> 2.7.4
>
Will,
if you are okay with the patch, can you please ACK.
Thanks,
Sunil.
^ permalink raw reply
* [PATCH] usb: chipidea: udc: fix NULL pointer dereference if udc_start failed
From: Peter Chen @ 2017-04-26 9:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170426162526.7c8ef827@xhacker>
On Wed, Apr 26, 2017 at 04:25:26PM +0800, Jisheng Zhang wrote:
> On Tue, 25 Apr 2017 17:21:59 +0200
> Stefan Wahren <stefan.wahren@i2se.com> wrote:
>
> > Am 25.04.2017 um 11:20 schrieb Peter Chen:
> > >
> > >>>> diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
> > >>>> index f88e9157fad0..60a786c87c06 100644
> > >>>> --- a/drivers/usb/chipidea/udc.c
> > >>>> +++ b/drivers/usb/chipidea/udc.c
> > >>>> @@ -1984,6 +1984,7 @@ static void udc_id_switch_for_host(struct
> > >>>> ci_hdrc *ci) int ci_hdrc_gadget_init(struct ci_hdrc *ci) {
> > >>>> struct ci_role_driver *rdrv;
> > >>>> + int ret;
> > >>>>
> > >>>> if (!hw_read(ci, CAP_DCCPARAMS, DCCPARAMS_DC))
> > >>>> return -ENXIO;
> > >>>> @@ -1996,7 +1997,10 @@ int ci_hdrc_gadget_init(struct ci_hdrc *ci)
> > >>>> rdrv->stop = udc_id_switch_for_host;
> > >>>> rdrv->irq = udc_irq;
> > >>>> rdrv->name = "gadget";
> > >>>> - ci->roles[CI_ROLE_GADGET] = rdrv;
> > >>>>
> > >>>> - return udc_start(ci);
> > >>>> + ret = udc_start(ci);
> > >>>> + if (!ret)
> > >>>> + ci->roles[CI_ROLE_GADGET] = rdrv;
> > >>>> +
> > >>>> + return ret;
> > >>>> }
> > >>>> --
> > >>> Thanks for fixing it. In fact, we'd better return failure if ret &&
> > >>> ret != -ENXIO at probe, it stands for initialization for host or
> > >>> gadget has failed.
> > >>>
> > >> I got your meaning. I'll cook v2. I don't have preference, since either one can fix the
> > >> issue.
> > >>
> > > Both are needed, you don't need to send this one again. Only a new one, thanks.
> >
> > I'm not sure how easy it is to reproduce the issue.
>
> It's easy to reproduce it (100%) on arm64 platforms after commit
> 1dccb598df549 ("arm64: simplify dma_get_ops"). This commit could
> make all dma related operations failed, then udc_start() would fail
> with -ENOMEM.
>
> On other platforms, it's not easy.
>
> >
> > Shouldn't make a Fixes tag sense at least?
>
> maybe 3f124d233e97 ("usb: chipidea: add role init and destroy APIs"
I will cc stable, thanks.
--
Best Regards,
Peter Chen
^ permalink raw reply
* [1/1] mt7601u: check return value of alloc_skb
From: Kalle Valo @ 2017-04-26 9:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1492930823-17249-1-git-send-email-bianpan2016@163.com>
Pan Bian <bianpan2016@163.com> wrote:
> Function alloc_skb() will return a NULL pointer if there is no enough
> memory. However, in function mt7601u_mcu_msg_alloc(), its return value
> is not validated before it is used. This patch fixes it.
>
> Signed-off-by: Pan Bian <bianpan2016@163.com>
> Acked-by: Jakub Kicinski <kubakici@wp.pl>
Patch applied to wireless-drivers-next.git, thanks.
5fb01e91daf8 mt7601u: check return value of alloc_skb
--
https://patchwork.kernel.org/patch/9694549/
https://wireless.wiki.kernel.org/en/developers/documentation/submittingpatches
^ permalink raw reply
* [patch V2 00/24] cpu/hotplug: Convert get_online_cpus() to a percpu_rwsem
From: Mark Rutland @ 2017-04-26 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170425172838.mr3kyccsdteyjso5@linutronix.de>
On Tue, Apr 25, 2017 at 07:28:38PM +0200, Sebastian Siewior wrote:
> On 2017-04-25 17:10:37 [+0100], Mark Rutland wrote:
> > When we bring the secondary CPU online, we detect an erratum that wasn't
> > present on the boot CPU, and try to enable a static branch we use to
> > track the erratum. The call to static_branch_enable() blows up as above.
>
> this (cpus_set_cap()) seems only to be used used in CPU up part.
>
> > I see that we now have static_branch_disable_cpuslocked(), but we don't
> > have an equivalent for enable. I'm not sure what we should be doing
> > here.
>
> We should introduce static_branch_enable_cpuslocked(). Does this work
> for you (after s/static_branch_enable/static_branch_enable_cpuslocked/
> in cpus_set_cap()) ?:
The patch you linked worked for me, given the below patch for arm64 to
make use of static_branch_enable_cpuslocked().
Catalin/Will, are you happy for this to go via the tip tree with the
other hotplug locking changes?
Thanks,
Mark.
---->8----
>From 03c98baf0a9fcdfb87145bfb3f108d49a721dad6 Mon Sep 17 00:00:00 2001
From: Mark Rutland <mark.rutland@arm.com>
Date: Wed, 26 Apr 2017 09:46:47 +0100
Subject: [PATCH] arm64: cpufeature: use static_branch_enable_cpuslocked()
Recently, the hotplug locking was conveted to use a percpu rwsem. Unlike
the existing {get,put}_online_cpus() logic, this can't nest.
Unfortunately, in arm64's secondary boot path we can end up nesting via
static_branch_enable() in cpus_set_cap() when we detect an erratum.
This leads to a stream of messages as below, where the secondary
attempts to schedule befroe it has been fully onlined. As the CPU
orchsetrating the onlining holds the rswem, this hangs the system.
[ 0.250334] BUG: scheduling while atomic: swapper/1/0/0x00000002
[ 0.250337] Modules linked in:
[ 0.250346] CPU: 1 PID: 0 Comm: swapper/1 Not tainted 4.11.0-rc7-next-20170424 #2
[ 0.250349] Hardware name: ARM Juno development board (r1) (DT)
[ 0.250353] Call trace:
[ 0.250365] [<ffff000008088510>] dump_backtrace+0x0/0x238
[ 0.250371] [<ffff00000808880c>] show_stack+0x14/0x20
[ 0.250377] [<ffff00000839d854>] dump_stack+0x9c/0xc0
[ 0.250384] [<ffff0000080e3540>] __schedule_bug+0x50/0x70
[ 0.250391] [<ffff000008932ecc>] __schedule+0x52c/0x5a8
[ 0.250395] [<ffff000008932f80>] schedule+0x38/0xa0
[ 0.250400] [<ffff000008935e8c>] rwsem_down_read_failed+0xc4/0x108
[ 0.250407] [<ffff0000080fe8e0>] __percpu_down_read+0x100/0x118
[ 0.250414] [<ffff0000080c0b60>] get_online_cpus+0x70/0x78
[ 0.250420] [<ffff0000081749e8>] static_key_enable+0x28/0x48
[ 0.250425] [<ffff00000808de90>] update_cpu_capabilities+0x78/0xf8
[ 0.250430] [<ffff00000808d14c>] update_cpu_errata_workarounds+0x1c/0x28
[ 0.250435] [<ffff00000808e004>] check_local_cpu_capabilities+0xf4/0x128
[ 0.250440] [<ffff00000808e894>] secondary_start_kernel+0x8c/0x118
[ 0.250444] [<000000008093d1b4>] 0x8093d1b4
We only call cpus_set_cap() in the secondary boot path, where we know
that the rwsem is held by the thread orchestrating the onlining. Thus,
we can use the new static_branch_enable_cpuslocked() in cpus_set_cap(),
avoiding the above.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reported-by: Catalin Marinas <catalin.marinas@arm.com>
Suggested-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Suzuki Poulose <suzuki,poulose@arm.com>
---
arch/arm64/include/asm/cpufeature.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index f31c48d..349b5cd 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -145,7 +145,7 @@ static inline void cpus_set_cap(unsigned int num)
num, ARM64_NCAPS);
} else {
__set_bit(num, cpu_hwcaps);
- static_branch_enable(&cpu_hwcap_keys[num]);
+ static_branch_enable_cpuslocked(&cpu_hwcap_keys[num]);
}
}
--
1.9.1
^ permalink raw reply related
* [PATCH v2] usb: chipidea: properly handle host or gadget initialization failure
From: Jisheng Zhang @ 2017-04-26 8:59 UTC (permalink / raw)
To: linux-arm-kernel
If ci_hdrc_host_init() or ci_hdrc_gadget_init() returns error and the
error != -ENXIO, as Peter pointed out, "it stands for initialization
for host or gadget has failed", so we'd better return failure rather
continue.
And before destroying the otg, i.e ci_hdrc_otg_destroy(ci), we should
also check ci->roles[CI_ROLE_GADGET].
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
---
Since v1:
- check ci->roles[CI_ROLE_GADGET] before destroying the otg, suggested
by Peter.
drivers/usb/chipidea/core.c | 29 +++++++++++++++++++++--------
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 79ad8e91632e..0192a26ec0f9 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -821,7 +821,7 @@ static inline void ci_role_destroy(struct ci_hdrc *ci)
{
ci_hdrc_gadget_destroy(ci);
ci_hdrc_host_destroy(ci);
- if (ci->is_otg)
+ if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
ci_hdrc_otg_destroy(ci);
}
@@ -930,27 +930,35 @@ static int ci_hdrc_probe(struct platform_device *pdev)
/* initialize role(s) before the interrupt is requested */
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_HOST) {
ret = ci_hdrc_host_init(ci);
- if (ret)
- dev_info(dev, "doesn't support host\n");
+ if (ret) {
+ if (ret == -ENXIO)
+ dev_info(dev, "doesn't support host\n");
+ else
+ goto deinit_phy;
+ }
}
if (dr_mode == USB_DR_MODE_OTG || dr_mode == USB_DR_MODE_PERIPHERAL) {
ret = ci_hdrc_gadget_init(ci);
- if (ret)
- dev_info(dev, "doesn't support gadget\n");
+ if (ret) {
+ if (ret == -ENXIO)
+ dev_info(dev, "doesn't support gadget\n");
+ else
+ goto deinit_host;
+ }
}
if (!ci->roles[CI_ROLE_HOST] && !ci->roles[CI_ROLE_GADGET]) {
dev_err(dev, "no supported roles\n");
ret = -ENODEV;
- goto deinit_phy;
+ goto deinit_gadget;
}
if (ci->is_otg && ci->roles[CI_ROLE_GADGET]) {
ret = ci_hdrc_otg_init(ci);
if (ret) {
dev_err(dev, "init otg fails, ret = %d\n", ret);
- goto stop;
+ goto deinit_gadget;
}
}
@@ -1013,7 +1021,12 @@ static int ci_hdrc_probe(struct platform_device *pdev)
return 0;
stop:
- ci_role_destroy(ci);
+ if (ci->is_otg && ci->roles[CI_ROLE_GADGET])
+ ci_hdrc_otg_destroy(ci);
+deinit_gadget:
+ ci_hdrc_gadget_destroy(ci);
+deinit_host:
+ ci_hdrc_host_destroy(ci);
deinit_phy:
ci_usb_phy_exit(ci);
ulpi_exit:
--
2.11.0
^ permalink raw reply related
* [PATCH 1/5] dt-bindings: Document the STM32 DMAMUX bindings
From: Pierre Yves MORDRET @ 2017-04-26 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170320213413.4b6uopuilznyr2rl@rob-hp-laptop>
Hi Rob
On 03/20/2017 10:34 PM, Rob Herring wrote:
> On Mon, Mar 13, 2017 at 03:15:57PM +0100, M'boumba Cedric Madianga wrote:
>> This patch adds the documentation of device tree bindings for the STM32
>> DMAMUX.
>>
>> Signed-off-by: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
>> ---
>> .../devicetree/bindings/dma/stm32-dmamux.txt | 57 ++++++++++++++++++++++
>> 1 file changed, 57 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/dma/stm32-dmamux.txt
>>
>> diff --git a/Documentation/devicetree/bindings/dma/stm32-dmamux.txt b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
>> new file mode 100644
>> index 0000000..1039420
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/dma/stm32-dmamux.txt
>> @@ -0,0 +1,57 @@
>> +STM32 DMA MUX (DMA request router)
>> +
>> +Required properties:
>> +- compatible: "st,stm32-dmamux"
>> +- reg: Memory map for accessing module
>> +- #dma-cells: Should be set to <4>.
>> + For more details about the four cells, please see stm32-dma.txt
>> + documentation binding file
>> +- dma-masters: Phandle pointing to the DMA controller
>> +- clocks: Input clock of the DMAMUX instance.
>> +
>> +Optional properties:
>> +- dma-channels : Number of DMA channels supported.
>> +- dma-requests : Number of DMA requests supported.
>> +- resets: Reference to a reset controller asserting the DMA controller
>> +
>> +Example:
>> +
>> +/* DMA controller */
>> +dma2: dma-controller at 40026400 {
>> + compatible = "st,stm32-dma";
>> + reg = <0x40026400 0x400>;
>> + interrupts = <56>,
>> + <57>,
>> + <58>,
>> + <59>,
>> + <60>,
>> + <68>,
>> + <69>,
>> + <70>;
>> + clocks = <&clk_hclk>;
>> + #dma-cells = <4>;
>> + st,mem2mem;
>> + resets = <&rcc 150>;
>> + st,dmamux;
>> + dma-channels = <8>;
>> +};
>> +
>> +/* DMA mux */
>> +dmamux2: dma-router at 40020820 {
>> + compatible = "st,stm32-dmamux";
>> + reg = <0x40020800 0x1c>;
>> + #dma-cells = <4>;
>> + dma-requests = <128>;
>> + dma-masters = <&dma2>;
>
> I think this should be modeled after the interrupt-map property (or
> Stephen Boyd's gpio-map support which additionally allows pass thru of
> cell values). Something like this:
>
> dma-map = <0 41 0 0 &dma2 0 <req> 0 0>,
> <1 42 0 0 &dma2 1 <req> 0 0>;
> dma-map-mask = <0xffffffff 0xffffffff 0 0>;
>
> <req> is the request number on dma2 controller.
>
> This is more generic and would work if you have a single mux with
> multiple DMA controllers.
>
Would you mind to detail a little bit more your thoughts please ?
Are dma-map & dma-map-mask part of an existing bindings ? or need to be
developed ?
I'm a little bit confused where come from values you used.
>> +};
>> +
>> +/* DMA client */
>> +usart1: serial at 40011000 {
>> + compatible = "st,stm32-usart", "st,stm32-uart";
>> + reg = <0x40011000 0x400>;
>> + interrupts = <37>;
>> + clocks = <&clk_pclk2>;
>> + dmas = <&dmamux2 0 41 0x400 0x00>,
>> + <&dmamux2 1 42 0x400 0x00>;
>> + dma-names = "rx", "tx";
>> +};
>> --
>> 1.9.1
>>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
>
>
^ permalink raw reply
* [PATCH/RFC 0/5] arm64: dts: renesas: Break out common board support
From: Simon Horman @ 2017-04-26 8:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdXbe=rkeS+-teg7nqbjULWY0_5pBO1XEzCGdYA4gB57oA@mail.gmail.com>
On Wed, Apr 26, 2017 at 10:11:55AM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> CC Vladimir (which I forgot to CC initially, sorry for that)
>
> On Wed, Apr 26, 2017 at 10:06 AM, Simon Horman <horms@verge.net.au> wrote:
> > On Fri, Apr 21, 2017 at 02:55:16PM +0200, Geert Uytterhoeven wrote:
> >> The Renesas Salvator-X and ULCB development board can be equipped with
> >> either an R-Car H3 or M3-W SiP, which are pin-compatible. All boards
> >> use separate DTBs, but currently there's no sharing of board-specific
> >> devices in DTS.
> >>
> >> This series reduces duplication by extracting common board support into
> >> their own .dtsi files. As the level of support varies across boards and
> >> SoCs, this requires the addition of a few external clocks and
> >> placeholder devices on R-Car M3-W, so the common board support DTS can
> >> refer to them.
> >>
> >> - Patches 1 and 2 add the external audio and PCIe bus clocks on R-Car
> >> M3-W, which are present in r8a7795.dtsi, and used in
> >> r8a7795-salvator-x.dts,
> >> - RFC patch 3 adds placeholders for devices that are not yet supported
> >> and/or tested on R-Car M3-W, but used on R-Car H3,
> >> - RFC patch 4 extracts common Salvator-X board support,
> >> - RFC patch 5 extracts common ULCB board support.
> >>
> >> For R-Car H3 based boards, there are no functional changes.
> >> For R-Car M3-W based boards, some new devices are now described in DT.
> >>
> >> Dependencies:
> >> - renesas-devel-20170420-v4.11-rc7,
> >> - Patches 1 and 2 can be applied as-is,
> >> - Patches 4 and 5 depend on "[PATCH 0/8] arm64: dts: renesas: Break
> >> out R-Car H3 and M3-W SiP"
> >> (http://www.spinics.net/lists/devicetree/msg173820.html).
> >>
> >> DTB changes have been inspected using scripts/dtc/dtx_diff.
> >> This has been tested on Salvator-X (both H3 and M3-W).
> >> This has not been tested on H3ULCB and M3ULCB due to lack of hardware.
> >>
> >> Thanks for your comments!
> >
> > Thanks for tackling this important problem. I have looked over the changes
> > and they seem nice to me. I would, however, be more comfortable applying
> > them if they were rested on the ULCB boards.
>
> tested?
Yes, tested :)
> I've pushed a branch for testing to topic/rcar3-dtsi-sharing in
> git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git.
^ permalink raw reply
* [PATCH] iio: stm32 trigger: Add support for TRGO2 triggers
From: Benjamin Gaignard @ 2017-04-26 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493194662-14501-1-git-send-email-fabrice.gasnier@st.com>
2017-04-26 10:17 GMT+02:00 Fabrice Gasnier <fabrice.gasnier@st.com>:
> Add support for TRGO2 trigger that can be found on STM32F7.
> Add additional master modes supported by TRGO2.
> Register additional "tim[1/8]_trgo2" triggers for timer1 & timer8.
> Detect TRGO2 timer capability (master mode selection 2).
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> .../ABI/testing/sysfs-bus-iio-timer-stm32 | 15 +++
> drivers/iio/trigger/stm32-timer-trigger.c | 113 ++++++++++++++++++---
> include/linux/iio/timer/stm32-timer-trigger.h | 2 +
> include/linux/mfd/stm32-timers.h | 2 +
> 4 files changed, 118 insertions(+), 14 deletions(-)
>
> diff --git a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32 b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
> index 230020e..47647b4 100644
> --- a/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
> +++ b/Documentation/ABI/testing/sysfs-bus-iio-timer-stm32
> @@ -16,6 +16,21 @@ Description:
> - "OC2REF" : OC2REF signal is used as trigger output.
> - "OC3REF" : OC3REF signal is used as trigger output.
> - "OC4REF" : OC4REF signal is used as trigger output.
> + Additional modes (on TRGO2 only):
> + - "OC5REF" : OC5REF signal is used as trigger output.
> + - "OC6REF" : OC6REF signal is used as trigger output.
> + - "compare_pulse_OC4REF":
> + OC4REF rising or falling edges generate pulses.
> + - "compare_pulse_OC6REF":
> + OC6REF rising or falling edges generate pulses.
> + - "compare_pulse_OC4REF_r_or_OC6REF_r":
> + OC4REF or OC6REF rising edges generate pulses.
> + - "compare_pulse_OC4REF_r_or_OC6REF_f":
> + OC4REF rising or OC6REF falling edges generate pulses.
> + - "compare_pulse_OC5REF_r_or_OC6REF_r":
> + OC5REF or OC6REF rising edges generate pulses.
> + - "compare_pulse_OC5REF_r_or_OC6REF_f":
> + OC5REF rising or OC6REF falling edges generate pulses.
>
> What: /sys/bus/iio/devices/triggerX/master_mode
> KernelVersion: 4.11
> diff --git a/drivers/iio/trigger/stm32-timer-trigger.c b/drivers/iio/trigger/stm32-timer-trigger.c
> index 0f1a2cf..a0031b7 100644
> --- a/drivers/iio/trigger/stm32-timer-trigger.c
> +++ b/drivers/iio/trigger/stm32-timer-trigger.c
> @@ -14,19 +14,19 @@
> #include <linux/module.h>
> #include <linux/platform_device.h>
>
> -#define MAX_TRIGGERS 6
> +#define MAX_TRIGGERS 7
> #define MAX_VALIDS 5
>
> /* List the triggers created by each timer */
> static const void *triggers_table[][MAX_TRIGGERS] = {
> - { TIM1_TRGO, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
> + { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
> { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
> { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
> { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
> { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
> { TIM6_TRGO,},
> { TIM7_TRGO,},
> - { TIM8_TRGO, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
> + { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
> { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
> { }, /* timer 10 */
> { }, /* timer 11 */
> @@ -56,9 +56,16 @@ struct stm32_timer_trigger {
> u32 max_arr;
> const void *triggers;
> const void *valids;
> + bool has_trgo2;
> };
>
> +static bool stm32_timer_is_trgo2_name(const char *name)
> +{
> + return !!strstr(name, "trgo2");
> +}
> +
> static int stm32_timer_start(struct stm32_timer_trigger *priv,
> + struct iio_trigger *trig,
> unsigned int frequency)
> {
> unsigned long long prd, div;
> @@ -102,7 +109,12 @@ static int stm32_timer_start(struct stm32_timer_trigger *priv,
> regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
>
> /* Force master mode to update mode */
> - regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
> + if (stm32_timer_is_trgo2_name(trig->name))
> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
> + 0x2 << TIM_CR2_MMS2_SHIFT);
> + else
> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
> + 0x2 << TIM_CR2_MMS_SHIFT);
>
> /* Make sure that registers are updated */
> regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
> @@ -150,7 +162,7 @@ static ssize_t stm32_tt_store_frequency(struct device *dev,
> if (freq == 0) {
> stm32_timer_stop(priv);
> } else {
> - ret = stm32_timer_start(priv, freq);
> + ret = stm32_timer_start(priv, trig, freq);
> if (ret)
> return ret;
> }
> @@ -183,6 +195,9 @@ static IIO_DEV_ATTR_SAMP_FREQ(0660,
> stm32_tt_read_frequency,
> stm32_tt_store_frequency);
>
> +#define MASTER_MODE_MAX 7
> +#define MASTER_MODE2_MAX 15
> +
> static char *master_mode_table[] = {
> "reset",
> "enable",
> @@ -191,7 +206,16 @@ static IIO_DEV_ATTR_SAMP_FREQ(0660,
> "OC1REF",
> "OC2REF",
> "OC3REF",
> - "OC4REF"
> + "OC4REF",
> + /* Master mode selection 2 only */
> + "OC5REF",
> + "OC6REF",
> + "compare_pulse_OC4REF",
> + "compare_pulse_OC6REF",
> + "compare_pulse_OC4REF_r_or_OC6REF_r",
> + "compare_pulse_OC4REF_r_or_OC6REF_f",
> + "compare_pulse_OC5REF_r_or_OC6REF_r",
> + "compare_pulse_OC5REF_r_or_OC6REF_f",
> };
>
> static ssize_t stm32_tt_show_master_mode(struct device *dev,
> @@ -199,10 +223,15 @@ static ssize_t stm32_tt_show_master_mode(struct device *dev,
> char *buf)
> {
> struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
> + struct iio_trigger *trig = to_iio_trigger(dev);
> u32 cr2;
>
> regmap_read(priv->regmap, TIM_CR2, &cr2);
> - cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
> +
> + if (stm32_timer_is_trgo2_name(trig->name))
> + cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
> + else
> + cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
>
> return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
> }
> @@ -212,13 +241,25 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev,
> const char *buf, size_t len)
> {
> struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
> + struct iio_trigger *trig = to_iio_trigger(dev);
> + u32 mask, shift, master_mode_max;
> int i;
>
> - for (i = 0; i < ARRAY_SIZE(master_mode_table); i++) {
> + if (stm32_timer_is_trgo2_name(trig->name)) {
> + mask = TIM_CR2_MMS2;
> + shift = TIM_CR2_MMS2_SHIFT;
> + master_mode_max = MASTER_MODE2_MAX;
> + } else {
> + mask = TIM_CR2_MMS;
> + shift = TIM_CR2_MMS_SHIFT;
> + master_mode_max = MASTER_MODE_MAX;
> + }
> +
> + for (i = 0; i <= master_mode_max; i++) {
> if (!strncmp(master_mode_table[i], buf,
> strlen(master_mode_table[i]))) {
> - regmap_update_bits(priv->regmap, TIM_CR2,
> - TIM_CR2_MMS, i << TIM_CR2_MMS_SHIFT);
> + regmap_update_bits(priv->regmap, TIM_CR2, mask,
> + i << shift);
> /* Make sure that registers are updated */
> regmap_update_bits(priv->regmap, TIM_EGR,
> TIM_EGR_UG, TIM_EGR_UG);
> @@ -229,8 +270,31 @@ static ssize_t stm32_tt_store_master_mode(struct device *dev,
> return -EINVAL;
> }
>
> -static IIO_CONST_ATTR(master_mode_available,
> - "reset enable update compare_pulse OC1REF OC2REF OC3REF OC4REF");
> +static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
> + struct device_attribute *attr,
> + char *buf)
> +{
> + struct iio_trigger *trig = to_iio_trigger(dev);
> + unsigned int i, master_mode_max;
> + size_t len = 0;
> +
> + if (stm32_timer_is_trgo2_name(trig->name))
> + master_mode_max = MASTER_MODE2_MAX;
> + else
> + master_mode_max = MASTER_MODE_MAX;
> +
> + for (i = 0; i <= master_mode_max; i++)
> + len += scnprintf(buf + len, PAGE_SIZE - len,
> + "%s ", master_mode_table[i]);
> +
> + /* replace trailing space by newline */
> + buf[len - 1] = '\n';
> +
> + return len;
> +}
> +
> +static IIO_DEVICE_ATTR(master_mode_available, 0444,
> + stm32_tt_show_master_mode_avail, NULL, 0);
>
> static IIO_DEVICE_ATTR(master_mode, 0660,
> stm32_tt_show_master_mode,
> @@ -240,7 +304,7 @@ static IIO_DEVICE_ATTR(master_mode, 0660,
> static struct attribute *stm32_trigger_attrs[] = {
> &iio_dev_attr_sampling_frequency.dev_attr.attr,
> &iio_dev_attr_master_mode.dev_attr.attr,
> - &iio_const_attr_master_mode_available.dev_attr.attr,
> + &iio_dev_attr_master_mode_available.dev_attr.attr,
> NULL,
> };
>
> @@ -264,6 +328,12 @@ static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
>
> while (cur && *cur) {
> struct iio_trigger *trig;
> + bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
> +
> + if (cur_is_trgo2 && !priv->has_trgo2) {
> + cur++;
> + continue;
> + }
>
> trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
> if (!trig)
> @@ -277,7 +347,7 @@ static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
> * should only be available on trgo trigger which
> * is always the first in the list.
> */
> - if (cur == priv->triggers)
> + if (cur == priv->triggers || cur_is_trgo2)
> trig->dev.groups = stm32_trigger_attr_groups;
>
> iio_trigger_set_drvdata(trig, priv);
> @@ -584,6 +654,20 @@ bool is_stm32_timer_trigger(struct iio_trigger *trig)
> }
> EXPORT_SYMBOL(is_stm32_timer_trigger);
>
> +static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
> +{
> + u32 val;
> +
> + /*
> + * Master mode selection 2 bits can only be written and read back when
> + * timer supports it.
> + */
> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
> + regmap_read(priv->regmap, TIM_CR2, &val);
> + regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
> + priv->has_trgo2 = !!val;
> +}
> +
> static int stm32_timer_trigger_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -614,6 +698,7 @@ static int stm32_timer_trigger_probe(struct platform_device *pdev)
> priv->max_arr = ddata->max_arr;
> priv->triggers = triggers_table[index];
> priv->valids = valids_table[index];
> + stm32_timer_detect_trgo2(priv);
>
> ret = stm32_setup_iio_triggers(priv);
> if (ret)
> diff --git a/include/linux/iio/timer/stm32-timer-trigger.h b/include/linux/iio/timer/stm32-timer-trigger.h
> index 55535ae..fa7d786 100644
> --- a/include/linux/iio/timer/stm32-timer-trigger.h
> +++ b/include/linux/iio/timer/stm32-timer-trigger.h
> @@ -10,6 +10,7 @@
> #define _STM32_TIMER_TRIGGER_H_
>
> #define TIM1_TRGO "tim1_trgo"
> +#define TIM1_TRGO2 "tim1_trgo2"
> #define TIM1_CH1 "tim1_ch1"
> #define TIM1_CH2 "tim1_ch2"
> #define TIM1_CH3 "tim1_ch3"
> @@ -44,6 +45,7 @@
> #define TIM7_TRGO "tim7_trgo"
>
> #define TIM8_TRGO "tim8_trgo"
> +#define TIM8_TRGO2 "tim8_trgo2"
> #define TIM8_CH1 "tim8_ch1"
> #define TIM8_CH2 "tim8_ch2"
> #define TIM8_CH3 "tim8_ch3"
> diff --git a/include/linux/mfd/stm32-timers.h b/include/linux/mfd/stm32-timers.h
> index 4a0abbc..ce7346e 100644
> --- a/include/linux/mfd/stm32-timers.h
> +++ b/include/linux/mfd/stm32-timers.h
> @@ -34,6 +34,7 @@
> #define TIM_CR1_DIR BIT(4) /* Counter Direction */
> #define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> #define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> +#define TIM_CR2_MMS2 GENMASK(23, 20) /* Master mode selection 2 */
> #define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> #define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> #define TIM_DIER_UIE BIT(0) /* Update interrupt */
> @@ -60,6 +61,7 @@
>
> #define MAX_TIM_PSC 0xFFFF
> #define TIM_CR2_MMS_SHIFT 4
> +#define TIM_CR2_MMS2_SHIFT 20
> #define TIM_SMCR_TS_SHIFT 4
> #define TIM_BDTR_BKF_MASK 0xF
> #define TIM_BDTR_BKF_SHIFT 16
> --
> 1.9.1
>
Acked-by: Benjamin Gaiganrd <benjamin.gaignard@linaro.org>
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