* [PATCH v5 1/4] printk/nmi: generic solution for safe printk in NMI
From: Sergey Senozhatsky @ 2017-04-28 1:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170420131154.GL3452@pathway.suse.cz>
On (04/20/17 15:11), Petr Mladek wrote:
[..]
> void printk_nmi_enter(void)
> {
> - this_cpu_or(printk_context, PRINTK_NMI_CONTEXT_MASK);
> + /*
> + * The size of the extra per-CPU buffer is limited. Use it
> + * only when really needed.
> + */
> + if (this_cpu_read(printk_context) & PRINTK_SAFE_CONTEXT_MASK ||
> + raw_spin_is_locked(&logbuf_lock)) {
can we please have && here?
[..]
> diff --git a/lib/nmi_backtrace.c b/lib/nmi_backtrace.c
> index 4e8a30d1c22f..0bc0a3535a8a 100644
> --- a/lib/nmi_backtrace.c
> +++ b/lib/nmi_backtrace.c
> @@ -86,9 +86,11 @@ void nmi_trigger_cpumask_backtrace(const cpumask_t *mask,
>
> bool nmi_cpu_backtrace(struct pt_regs *regs)
> {
> + static arch_spinlock_t lock = __ARCH_SPIN_LOCK_UNLOCKED;
> int cpu = smp_processor_id();
>
> if (cpumask_test_cpu(cpu, to_cpumask(backtrace_mask))) {
> + arch_spin_lock(&lock);
> if (regs && cpu_in_idle(instruction_pointer(regs))) {
> pr_warn("NMI backtrace for cpu %d skipped: idling at pc %#lx\n",
> cpu, instruction_pointer(regs));
> @@ -99,6 +101,7 @@ bool nmi_cpu_backtrace(struct pt_regs *regs)
> else
> dump_stack();
> }
> + arch_spin_unlock(&lock);
> cpumask_clear_cpu(cpu, to_cpumask(backtrace_mask));
> return true;
> }
can the nmi_backtrace part be a patch on its own?
-ss
^ permalink raw reply
* [PATCH] watchdog: bcm281xx: Fix use of uninitialized spinlock.
From: Florian Fainelli @ 2017-04-28 1:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170428010232.19905-1-eric@anholt.net>
On 04/27/2017 06:02 PM, Eric Anholt wrote:
> The bcm_kona_wdt_set_resolution_reg() call takes the spinlock, so
> initialize it earlier. Fixes a warning at boot with lock debugging
> enabled.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Fixes: 6adb730dc208 ("watchdog: bcm281xx: Watchdog Driver")
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
> drivers/watchdog/bcm_kona_wdt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/bcm_kona_wdt.c b/drivers/watchdog/bcm_kona_wdt.c
> index 6fce17d5b9f1..a5775dfd8d5f 100644
> --- a/drivers/watchdog/bcm_kona_wdt.c
> +++ b/drivers/watchdog/bcm_kona_wdt.c
> @@ -304,6 +304,8 @@ static int bcm_kona_wdt_probe(struct platform_device *pdev)
> if (!wdt)
> return -ENOMEM;
>
> + spin_lock_init(&wdt->lock);
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> wdt->base = devm_ioremap_resource(dev, res);
> if (IS_ERR(wdt->base))
> @@ -316,7 +318,6 @@ static int bcm_kona_wdt_probe(struct platform_device *pdev)
> return ret;
> }
>
> - spin_lock_init(&wdt->lock);
> platform_set_drvdata(pdev, wdt);
> watchdog_set_drvdata(&bcm_kona_wdt_wdd, wdt);
> bcm_kona_wdt_wdd.parent = &pdev->dev;
>
--
Florian
^ permalink raw reply
* [PATCH 2/3] ARM: at91: pm: allow selecting standby and suspend modes
From: Yang, Wenyou @ 2017-04-28 1:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170426160419.22401-2-alexandre.belloni@free-electrons.com>
On 2017/4/27 0:04, Alexandre Belloni wrote:
> While we can only select between "standby" and "mem" states for power
> management, the atmel platforms can actually support more modes.
>
> For both standby and mem, allow selecting which mode will be used using the
> atmel.pm_modes kernel parameter.
> By default, keep the current modes.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
> arch/arm/mach-at91/pm.c | 110 +++++++++++++++++++++++++++++++++---------------
> arch/arm/mach-at91/pm.h | 3 +-
> 2 files changed, 78 insertions(+), 35 deletions(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index 1e03f1277f14..d08f032f9d94 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -15,6 +15,7 @@
> #include <linux/of_address.h>
> #include <linux/of.h>
> #include <linux/of_platform.h>
> +#include <linux/parser.h>
> #include <linux/suspend.h>
>
> #include <linux/clk/at91_pmc.h>
> @@ -38,7 +39,17 @@ extern void at91_pinctrl_gpio_suspend(void);
> extern void at91_pinctrl_gpio_resume(void);
> #endif
>
> -static struct at91_pm_data pm_data;
> +static const match_table_t pm_modes __initconst = {
> + { 0, "standby" },
> + { AT91_PM_SLOW_CLOCK, "ulp0" },
> + { AT91_PM_BACKUP, "backup" },
> + { -1, NULL },
> +};
> +
> +static struct at91_pm_data pm_data = {
> + .standby_mode = 0,
> + .suspend_mode = AT91_PM_SLOW_CLOCK,
> +};
>
> #define at91_ramc_read(id, field) \
> __raw_readl(pm_data.ramc[id] + field)
> @@ -68,14 +79,24 @@ static struct at91_pm_bu {
> phys_addr_t resume;
> } *pm_bu;
>
> -static suspend_state_t target_state;
> -
> /*
> * Called after processes are frozen, but before we shutdown devices.
> */
> static int at91_pm_begin(suspend_state_t state)
> {
> - target_state = state;
> + switch (state) {
> + case PM_SUSPEND_MEM:
> + pm_data.mode = pm_data.suspend_mode;
> + break;
> +
> + case PM_SUSPEND_STANDBY:
> + pm_data.mode = pm_data.standby_mode;
> + break;
> +
> + default:
> + pm_data.mode = -1;
> + }
> +
> return 0;
> }
>
> @@ -124,7 +145,7 @@ static int at91_pm_verify_clocks(void)
> */
> int at91_suspend_entering_slow_clock(void)
> {
> - return (target_state == PM_SUSPEND_MEM);
> + return (pm_data.mode >= AT91_PM_SLOW_CLOCK);
> }
> EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
>
> @@ -144,14 +165,6 @@ static int at91_suspend_finish(unsigned long val)
>
> static void at91_pm_suspend(suspend_state_t state)
> {
> - if (pm_data.deepest_state == AT91_PM_BACKUP)
> - if (state == PM_SUSPEND_MEM)
> - pm_data.mode = AT91_PM_BACKUP;
> - else
> - pm_data.mode = AT91_PM_SLOW_CLOCK;
> - else
> - pm_data.mode = (state == PM_SUSPEND_MEM) ? AT91_PM_SLOW_CLOCK : 0;
> -
> if (pm_data.mode == AT91_PM_BACKUP) {
> pm_bu->suspended = 1;
>
> @@ -168,38 +181,37 @@ static void at91_pm_suspend(suspend_state_t state)
> outer_resume();
> }
>
> +/*
> + * STANDBY mode has *all* drivers suspended; ignores irqs not marked as 'wakeup'
> + * event sources; and reduces DRAM power. But otherwise it's identical to
> + * PM_SUSPEND_ON: cpu idle, and nothing fancy done with main or cpu clocks.
> + *
> + * AT91_PM_SLOW_CLOCK is like STANDBY plus slow clock mode, so drivers must
> + * suspend more deeply, the master clock switches to the clk32k and turns off
> + * the main oscillator
> + *
> + * AT91_PM_BACKUP turns off the whole SoC after placing the DDR in self refresh
> + */
> static int at91_pm_enter(suspend_state_t state)
> {
> #ifdef CONFIG_PINCTRL_AT91
> at91_pinctrl_gpio_suspend();
> #endif
> +
> switch (state) {
> - /*
> - * Suspend-to-RAM is like STANDBY plus slow clock mode, so
> - * drivers must suspend more deeply, the master clock switches
> - * to the clk32k and turns off the main oscillator
> - */
> case PM_SUSPEND_MEM:
> + case PM_SUSPEND_STANDBY:
> /*
> * Ensure that clocks are in a valid state.
> */
> - if (!at91_pm_verify_clocks())
> + if ((pm_data.mode >= AT91_PM_SLOW_CLOCK) &&
> + !at91_pm_verify_clocks())
> goto error;
>
> at91_pm_suspend(state);
>
> break;
>
> - /*
> - * STANDBY mode has *all* drivers suspended; ignores irqs not
> - * marked as 'wakeup' event sources; and reduces DRAM power.
> - * But otherwise it's identical to PM_SUSPEND_ON: cpu idle, and
> - * nothing fancy done with main or cpu clocks.
> - */
> - case PM_SUSPEND_STANDBY:
> - at91_pm_suspend(state);
> - break;
> -
> case PM_SUSPEND_ON:
> cpu_do_idle();
> break;
> @@ -210,8 +222,6 @@ static int at91_pm_enter(suspend_state_t state)
> }
>
> error:
> - target_state = PM_SUSPEND_ON;
> -
> #ifdef CONFIG_PINCTRL_AT91
> at91_pinctrl_gpio_resume();
> #endif
> @@ -223,7 +233,6 @@ static int at91_pm_enter(suspend_state_t state)
> */
> static void at91_pm_end(void)
> {
> - target_state = PM_SUSPEND_ON;
> }
>
>
> @@ -494,6 +503,10 @@ static void __init at91_pm_bu_sram_init(void)
> struct device_node *node;
> struct platform_device *pdev = NULL;
>
> + if ((pm_data.standby_mode != AT91_PM_BACKUP) &&
> + (pm_data.suspend_mode != AT91_PM_BACKUP))
> + return;
> +
> pm_bu = NULL;
>
> for_each_compatible_node(node, NULL, "atmel,sama5d2-securam") {
> @@ -571,10 +584,14 @@ static void __init at91_pm_init(void (*pm_idle)(void))
>
> at91_pm_sram_init();
>
> - if (at91_suspend_sram_fn)
> + if (at91_suspend_sram_fn) {
> suspend_set_ops(&at91_pm_ops);
> - else
> + pr_info("AT91: PM: standby: %s, suspend: %s\n",
> + pm_modes[pm_data.standby_mode].pattern,
> + pm_modes[pm_data.suspend_mode].pattern);
> + } else {
> pr_info("AT91: PM not supported, due to no SRAM allocated\n");
> + }
> }
>
> void __init at91rm9200_pm_init(void)
> @@ -607,3 +624,28 @@ void __init sama5d2_pm_init(void)
> at91_pm_bu_sram_init();
> sama5_pm_init();
> }
> +
> +static int __init at91_pm_modes_select(char *str)
> +{
> + char *s;
> + substring_t args[MAX_OPT_ARGS];
> + int standby, suspend;
> +
> + if (!str)
> + return 0;
> +
> + s = strsep(&str, ",");
> + standby = match_token(s, pm_modes, args);
> + if (standby < 0)
> + return 0;
> +
> + suspend = match_token(str, pm_modes, args);
> + if (suspend < 0)
> + return 0;
> +
> + pm_data.standby_mode = standby;
> + pm_data.suspend_mode = suspend;
> +
> + return 0;
> +}
> +early_param("atmel.pm_modes", at91_pm_modes_select);
> diff --git a/arch/arm/mach-at91/pm.h b/arch/arm/mach-at91/pm.h
> index d9c6612ef62f..f95d31496f08 100644
> --- a/arch/arm/mach-at91/pm.h
> +++ b/arch/arm/mach-at91/pm.h
> @@ -33,7 +33,8 @@ struct at91_pm_data {
> unsigned int mode;
> void __iomem *shdwc;
> void __iomem *sfrbu;
> - unsigned int deepest_state;
> + unsigned int standby_mode;
> + unsigned int suspend_mode;
> };
> #endif
>
Best Regards,
Wenyou Yang
^ permalink raw reply
* [PATCH 3/3] ARM: at91: pm: fallback to slowclock when backup mode fails
From: Yang, Wenyou @ 2017-04-28 1:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170426160419.22401-3-alexandre.belloni@free-electrons.com>
On 2017/4/27 0:04, Alexandre Belloni wrote:
> If the backup sram allocation fails, ensure we can suspend by falling back
> to the usual slow clock mode.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Wenyou Yang <wenyou.yang@atmel.com>
> ---
> arch/arm/mach-at91/pm.c | 12 +++++++++---
> 1 file changed, 9 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> index d08f032f9d94..02823d8f3ada 100644
> --- a/arch/arm/mach-at91/pm.c
> +++ b/arch/arm/mach-at91/pm.c
> @@ -519,24 +519,30 @@ static void __init at91_pm_bu_sram_init(void)
>
> if (!pdev) {
> pr_warn("%s: failed to find securam device!\n", __func__);
> - return;
> + goto fallback;
> }
>
> sram_pool = gen_pool_get(&pdev->dev, NULL);
> if (!sram_pool) {
> pr_warn("%s: securam pool unavailable!\n", __func__);
> - return;
> + goto fallback;
> }
>
> pm_bu = (void *)gen_pool_alloc(sram_pool, sizeof(struct at91_pm_bu));
> if (!pm_bu) {
> pr_warn("%s: unable to alloc securam!\n", __func__);
> - return;
> + goto fallback;
> }
>
> pm_bu->suspended = 0;
> pm_bu->canary = virt_to_phys(&canary);
> pm_bu->resume = virt_to_phys(cpu_resume);
> +
> +fallback:
> + if (pm_data.standby_mode == AT91_PM_BACKUP)
> + pm_data.standby_mode = AT91_PM_SLOW_CLOCK;
> + if (pm_data.suspend_mode != AT91_PM_BACKUP)
> + pm_data.suspend_mode = AT91_PM_SLOW_CLOCK;
> }
>
> struct pmc_info {
Best Regards,
Wenyou Yang
^ permalink raw reply
* [PATCH v5 1/4] printk/nmi: generic solution for safe printk in NMI
From: Sergey Senozhatsky @ 2017-04-28 1:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170427121458.2be577cc@gandalf.local.home>
On (04/27/17 12:14), Steven Rostedt wrote:
[..]
> I tried this patch. It's better because I get the end of the trace, but
> I do lose the beginning of it:
>
> ** 196358 printk messages dropped ** [ 102.321182] perf-5981 0.... 12983650us : d_path <-seq_path
many thanks!
so we now drop messages from logbuf, not from per-CPU buffers. that
"queue printk_deferred irq_work on every online CPU when we bypass per-CPU
buffers from NMI" idea *probably* might help here - we need someone to emit
messages from the logbuf while we printk from NMI. there is still a
possibility that we can drop messages, though, since log_store() from NMI
CPU can be much-much faster than call_console_drivers() on other CPU.
-ss
^ permalink raw reply
* Running kexec, kernel gets stuck at "Starting new kernel"
From: Rudici Cazeao @ 2017-04-28 1:50 UTC (permalink / raw)
To: linux-arm-kernel
I am running kexec in consecutive loops on 4 different dual-core arm processors. On 3 of these processors, usually, somewhere between the 500th and the 5000th lopp, the kernel gets stuck at "Starting new kernel". On the remaining processor, kexec is run over and over without running into this issue. And this appears to be pretty consistent. Any ideas?
Also, on rare occasions, the kernel gets stuck at " Uncompressing Linux... done, booting the kernel".
The SoC is Cortex-A9 (ARMv7-A)
The kernel version is 3.0.51-rt75
^ permalink raw reply
* [PATCH] watchdog: bcm281xx: Fix use of uninitialized spinlock.
From: Guenter Roeck @ 2017-04-28 2:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170428010232.19905-1-eric@anholt.net>
On 04/27/2017 06:02 PM, Eric Anholt wrote:
> The bcm_kona_wdt_set_resolution_reg() call takes the spinlock, so
> initialize it earlier. Fixes a warning at boot with lock debugging
> enabled.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
> ---
> drivers/watchdog/bcm_kona_wdt.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/bcm_kona_wdt.c b/drivers/watchdog/bcm_kona_wdt.c
> index 6fce17d5b9f1..a5775dfd8d5f 100644
> --- a/drivers/watchdog/bcm_kona_wdt.c
> +++ b/drivers/watchdog/bcm_kona_wdt.c
> @@ -304,6 +304,8 @@ static int bcm_kona_wdt_probe(struct platform_device *pdev)
> if (!wdt)
> return -ENOMEM;
>
> + spin_lock_init(&wdt->lock);
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> wdt->base = devm_ioremap_resource(dev, res);
> if (IS_ERR(wdt->base))
> @@ -316,7 +318,6 @@ static int bcm_kona_wdt_probe(struct platform_device *pdev)
> return ret;
> }
>
> - spin_lock_init(&wdt->lock);
> platform_set_drvdata(pdev, wdt);
> watchdog_set_drvdata(&bcm_kona_wdt_wdd, wdt);
> bcm_kona_wdt_wdd.parent = &pdev->dev;
>
^ permalink raw reply
* [PATCH v1 0/2] clk: rockchip: Perfect clock description for RK3228
From: Elaine Zhang @ 2017-04-28 2:33 UTC (permalink / raw)
To: linux-arm-kernel
support more cpu freq, and support armcore div setting.
Add some necessary clks ID.
Elaine Zhang (2):
clk: rockchip: fix up the RK3228 clk cpu setting table
clk: rockchip: export rk3228 clocks ID
drivers/clk/rockchip/clk-rk3228.c | 142 +++++++++++++++++++--------------
include/dt-bindings/clock/rk3228-cru.h | 47 +++++++++++
2 files changed, 127 insertions(+), 62 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH v1 1/2] clk: rockchip: fix up the RK3228 clk cpu setting table
From: Elaine Zhang @ 2017-04-28 2:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493346801-23785-1-git-send-email-zhangqing@rock-chips.com>
support more cpu freq, and add armcore div setting.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3228.c | 50 ++++++++++++++++++++++++++-------------
1 file changed, 34 insertions(+), 16 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index db6e5a9e6de6..a6cdf8fc1e75 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -86,25 +86,43 @@ enum rk3228_plls {
#define RK3228_DIV_PCLK_MASK 0x7
#define RK3228_DIV_PCLK_SHIFT 12
-#define RK3228_CLKSEL1(_core_peri_div) \
- { \
- .reg = RK2928_CLKSEL_CON(1), \
- .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
- RK3228_DIV_PERI_SHIFT) \
- }
+#define RK3228_CLKSEL1(_core_aclk_div, _core_peri_div) \
+{ \
+ .reg = RK2928_CLKSEL_CON(1), \
+ .val = HIWORD_UPDATE(_core_peri_div, RK3228_DIV_PERI_MASK, \
+ RK3228_DIV_PERI_SHIFT) | \
+ HIWORD_UPDATE(_core_aclk_div, RK3228_DIV_ACLK_MASK, \
+ RK3228_DIV_ACLK_SHIFT), \
+}
-#define RK3228_CPUCLK_RATE(_prate, _core_peri_div) \
- { \
- .prate = _prate, \
- .divs = { \
- RK3228_CLKSEL1(_core_peri_div), \
- }, \
- }
+#define RK3228_CPUCLK_RATE(_prate, _core_aclk_div, _core_peri_div) \
+{ \
+ .prate = _prate, \
+ .divs = { \
+ RK3228_CLKSEL1(_core_aclk_div, _core_peri_div), \
+ }, \
+}
static struct rockchip_cpuclk_rate_table rk3228_cpuclk_rates[] __initdata = {
- RK3228_CPUCLK_RATE(816000000, 4),
- RK3228_CPUCLK_RATE(600000000, 4),
- RK3228_CPUCLK_RATE(312000000, 4),
+ RK3228_CPUCLK_RATE(1800000000, 1, 7),
+ RK3228_CPUCLK_RATE(1704000000, 1, 7),
+ RK3228_CPUCLK_RATE(1608000000, 1, 7),
+ RK3228_CPUCLK_RATE(1512000000, 1, 7),
+ RK3228_CPUCLK_RATE(1488000000, 1, 5),
+ RK3228_CPUCLK_RATE(1416000000, 1, 5),
+ RK3228_CPUCLK_RATE(1392000000, 1, 5),
+ RK3228_CPUCLK_RATE(1296000000, 1, 5),
+ RK3228_CPUCLK_RATE(1200000000, 1, 5),
+ RK3228_CPUCLK_RATE(1104000000, 1, 5),
+ RK3228_CPUCLK_RATE(1008000000, 1, 5),
+ RK3228_CPUCLK_RATE(912000000, 1, 5),
+ RK3228_CPUCLK_RATE(816000000, 1, 3),
+ RK3228_CPUCLK_RATE(696000000, 1, 3),
+ RK3228_CPUCLK_RATE(600000000, 1, 3),
+ RK3228_CPUCLK_RATE(408000000, 1, 1),
+ RK3228_CPUCLK_RATE(312000000, 1, 1),
+ RK3228_CPUCLK_RATE(216000000, 1, 1),
+ RK3228_CPUCLK_RATE(96000000, 1, 1),
};
static const struct rockchip_cpuclk_reg_data rk3228_cpuclk_data = {
--
1.9.1
^ permalink raw reply related
* [PATCH v1 2/2] clk: rockchip: export rk3228 clocks ID
From: Elaine Zhang @ 2017-04-28 2:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493346801-23785-1-git-send-email-zhangqing@rock-chips.com>
This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3228.c | 92 +++++++++++++++++-----------------
include/dt-bindings/clock/rk3228-cru.h | 47 +++++++++++++++++
2 files changed, 93 insertions(+), 46 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index a6cdf8fc1e75..7ded7d63d53e 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -270,15 +270,15 @@ enum rk3228_plls {
RK2928_CLKGATE_CON(0), 1, GFLAGS),
COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
- GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
+ GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKGATE_CON(6), 0, GFLAGS),
- COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
+ COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
RK2928_CLKGATE_CON(6), 1, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
RK2928_CLKGATE_CON(6), 2, GFLAGS),
- GATE(0, "pclk_cpu", "pclk_bus_src", 0,
+ GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
RK2928_CLKGATE_CON(6), 3, GFLAGS),
GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
RK2928_CLKGATE_CON(6), 4, GFLAGS),
@@ -286,58 +286,58 @@ enum rk3228_plls {
RK2928_CLKGATE_CON(6), 13, GFLAGS),
/* PD_VIDEO */
- COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
+ COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 11, GFLAGS),
- FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
+ FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
RK2928_CLKGATE_CON(4), 4, GFLAGS),
- COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
+ COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 2, GFLAGS),
- FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
+ FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
RK2928_CLKGATE_CON(4), 5, GFLAGS),
- COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
+ COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 3, GFLAGS),
- COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
+ COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 4, GFLAGS),
/* PD_VIO */
- COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
+ COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 0, GFLAGS),
- DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0,
+ DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0,
RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
- COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
+ COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 4, GFLAGS),
MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
- COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0,
+ COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0,
RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 2, GFLAGS),
- COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0,
+ COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(3), 6, GFLAGS),
- COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
+ COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(1), 1, GFLAGS),
- COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0,
+ COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
RK2928_CLKGATE_CON(3), 5, GFLAGS),
GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
RK2928_CLKGATE_CON(3), 7, GFLAGS),
- COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
+ COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
RK2928_CLKGATE_CON(3), 8, GFLAGS),
@@ -372,18 +372,18 @@ enum rk3228_plls {
GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
RK2928_CLKGATE_CON(6), 10, GFLAGS),
- COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0,
+ COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 7, GFLAGS),
- COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0,
+ COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
RK2928_CLKGATE_CON(2), 6, GFLAGS),
- GATE(0, "sclk_hsadc", "ext_hsadc", 0,
+ GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0,
RK2928_CLKGATE_CON(10), 12, GFLAGS),
- COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
+ COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
RK2928_CLKGATE_CON(2), 15, GFLAGS),
@@ -466,9 +466,9 @@ enum rk3228_plls {
GATE(0, "jtag", "ext_jtag", 0,
RK2928_CLKGATE_CON(1), 3, GFLAGS),
- GATE(0, "sclk_otgphy0", "xin24m", 0,
+ GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
RK2928_CLKGATE_CON(1), 5, GFLAGS),
- GATE(0, "sclk_otgphy1", "xin24m", 0,
+ GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
RK2928_CLKGATE_CON(1), 6, GFLAGS),
COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
@@ -544,28 +544,28 @@ enum rk3228_plls {
*/
/* PD_VOP */
- GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
+ GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
- GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
+ GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
- GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
+ GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
- GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
- GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
+ GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
+ GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
- GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
- GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
+ GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
+ GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
- GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
- GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
+ GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
+ GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
/* PD_PERI */
GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
@@ -575,12 +575,12 @@ enum rk3228_plls {
GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
- GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
+ GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
- GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
+ GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
- GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
- GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
+ GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
+ GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
@@ -589,7 +589,7 @@ enum rk3228_plls {
GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
/* PD_GPU */
- GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
+ GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
/* PD_BUS */
@@ -603,16 +603,16 @@ enum rk3228_plls {
GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
- GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
- GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
- GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
+ GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
+ GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
+ GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
- GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
- GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
+ GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
+ GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
@@ -640,13 +640,13 @@ enum rk3228_plls {
GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
- GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
+ GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
- GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
+ GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
- GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
+ GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
- GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
+ GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
/* PD_MMC */
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
index b27e2b1a65e3..56f841c22801 100644
--- a/include/dt-bindings/clock/rk3228-cru.h
+++ b/include/dt-bindings/clock/rk3228-cru.h
@@ -61,6 +61,17 @@
#define SCLK_MAC_TX 130
#define SCLK_MAC_PHY 131
#define SCLK_MAC_OUT 132
+#define SCLK_VDEC_CABAC 133
+#define SCLK_VDEC_CORE 134
+#define SCLK_RGA 135
+#define SCLK_HDCP 136
+#define SCLK_HDMI_CEC 137
+#define SCLK_CRYPTO 138
+#define SCLK_TSP 139
+#define SCLK_HSADC 140
+#define SCLK_WIFI 141
+#define SCLK_OTGPHY0 142
+#define SCLK_OTGPHY1 143
/* dclk gates */
#define DCLK_VOP 190
@@ -68,15 +79,32 @@
/* aclk gates */
#define ACLK_DMAC 194
+#define ACLK_CPU 195
+#define ACLK_VPU_PRE 196
+#define ACLK_RKVDEC_PRE 197
+#define ACLK_RGA_PRE 198
+#define ACLK_IEP_PRE 199
+#define ACLK_HDCP_PRE 200
+#define ACLK_VOP_PRE 201
+#define ACLK_VPU 202
+#define ACLK_RKVDEC 203
+#define ACLK_IEP 204
+#define ACLK_RGA 205
+#define ACLK_HDCP 206
#define ACLK_PERI 210
#define ACLK_VOP 211
#define ACLK_GMAC 212
+#define ACLK_GPU 213
/* pclk gates */
#define PCLK_GPIO0 320
#define PCLK_GPIO1 321
#define PCLK_GPIO2 322
#define PCLK_GPIO3 323
+#define PCLK_VIO_H2P 324
+#define PCLK_HDCP 325
+#define PCLK_EFUSE_1024 326
+#define PCLK_EFUSE_256 327
#define PCLK_GRF 329
#define PCLK_I2C0 332
#define PCLK_I2C1 333
@@ -89,6 +117,7 @@
#define PCLK_TSADC 344
#define PCLK_PWM 350
#define PCLK_TIMER 353
+#define PCLK_CPU 354
#define PCLK_PERI 363
#define PCLK_HDMI_CTRL 364
#define PCLK_HDMI_PHY 365
@@ -104,6 +133,24 @@
#define HCLK_SDMMC 456
#define HCLK_SDIO 457
#define HCLK_EMMC 459
+#define HCLK_CPU 460
+#define HCLK_VPU_PRE 461
+#define HCLK_RKVDEC_PRE 462
+#define HCLK_VIO_PRE 463
+#define HCLK_VPU 464
+#define HCLK_RKVDEC 465
+#define HCLK_VIO 466
+#define HCLK_RGA 467
+#define HCLK_IEP 468
+#define HCLK_VIO_H2P 469
+#define HCLK_HDCP_MMU 470
+#define HCLK_HOST0 471
+#define HCLK_HOST1 472
+#define HCLK_HOST2 473
+#define HCLK_OTG 474
+#define HCLK_TSP 475
+#define HCLK_M_CRYPTO 476
+#define HCLK_S_CRYPTO 477
#define HCLK_PERI 478
#define CLK_NR_CLKS (HCLK_PERI + 1)
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe
From: Ryder Lee @ 2017-04-28 2:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a0vD8s_3R+jS=JdUXX3X05SkCk-mipMA6UxWYQZe6vLUQ@mail.gmail.com>
On Thu, 2017-04-27 at 21:06 +0200, Arnd Bergmann wrote:
> On Wed, Apr 26, 2017 at 10:10 AM, Ryder Lee <ryder.lee@mediatek.com> wrote:
> > Hi
> >
> > On Tue, 2017-04-25 at 14:18 +0200, Arnd Bergmann wrote:
> >> On Sun, Apr 23, 2017 at 10:19 AM, Ryder Lee <ryder.lee@mediatek.com> wrote:
> >> > Add documentation for PCIe host driver available in MT7623
> >> > series SoCs.
> >> >
> >> > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> >> > ---
> >> > .../bindings/pci/mediatek,mt7623-pcie.txt | 153 +++++++++++++++++++++
> >> > 1 file changed, 153 insertions(+)
> >> > create mode 100644 Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
> >> >
> >> > diff --git a/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
> >> > new file mode 100644
> >> > index 0000000..ee93ba2
> >> > --- /dev/null
> >> > +++ b/Documentation/devicetree/bindings/pci/mediatek,mt7623-pcie.txt
> >> > @@ -0,0 +1,153 @@
> >> > +Mediatek MT7623 PCIe controller
> >> > +
> >> > +Required properties:
> >> > +- compatible: Should contain "mediatek,mt7623-pcie".
> >>
> >> Did mediatek license the IP block from someone else or was it
> >> developed in-house? Is there a name and/or version identifier
> >> for the block itself other than identifying it as the one in mt7623?
> >
> > Originally, it license from synopsys. Our designer add a wrapper to hide
> > the DBI detail so that we cannot use them directly. Perhaps I can call
> > it "mediatek,gen2v1-pcie", because we have a plan to upstream a in-house
> > Gen2 IP in the future.
>
> Ok, so this is the same hardware that drivers/pci/dwc/ handles, but
> it needs a separate driver because the wrapper that was added uses
> a completely different register layout, right?
Yes, that's what I mean. At first, I really want to base on
drivers/pci/dwc/ to implement this driver. Eventually I found it hard to
go on, like what I said before.
> Are any of the registers the same at all, e.g. for MSI handling?
No, It doesn't support MSI. All I can do is using the registers that designer provide
to me. The others are inviable for software. So I treat it as different hardware.
Furthermore, we hope that we can put all mediatek drivers together
regardless of in-house IP or lincense IP
We have no particular IP name but just use chip name to call it. So I
will temporarily use "mediatek,gen2v1-pcie" in patch v1.
> >> > +Required properties:
> >> > +- device_type: Must be "pci"
> >> > +- assigned-addresses: Address and size of the port configuration registers
> >> > +- reg: Only the first four bytes are used to refer to the correct bus number
> >> > + and device number.
> >> > +- #address-cells: Must be 3
> >> > +- #size-cells: Must be 2
> >> > +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> >> > + property is sufficient.
> >> > +- clocks: Must contain an entry for each entry in clock-names.
> >> > + See ../clocks/clock-bindings.txt for details.
> >> > +- clock-names: Must include the following entries:
> >> > + - sys_ck
> >> > +- resets: Must contain an entry for each entry in reset-names.
> >> > + See ../reset/reset.txt for details.
> >>
> >> This seems odd: you have a device that is simply identified as "pci"
> >> without any more specific ID, but you require additional properties
> >> (clocks, reset, ...) that are not part of the standard PCI binding.
> >>
> >> Can you clarify how the port devices related to the root device in
> >> this hardware design?
> >
> > I will write clarify like this:
> >
> > PCIe subsys includes one Host/PCI bridge and 3 PCIe MAC port. There
> > are 3 bus master for data access and 1 slave for configuration and
> > status register access. Each port has PIPE interface to PHY and
>
> If I understand this right, then each of the ports in your hardware
> is what we normally drive using the drivers/pci/dwc/ driver framework,
> but your implementation actually made it more PCI standard compliant
> by implementing the normal PCIe host bridge registers for all ports
> combined, something that most others don't.
In my view, it's correct to implement our driver in this way. But I
don't really understand the details about other platforms.
> >> Have you considered moving the nonstandard properties into the host
> >> bridge node and having that device deal with setting up the links
> >> to the other drivers? That way we could use the regular pcie
> >> port driver for the children.
> >>
> >
> > OK, but I still want to use port->reset to catch reset properties in
> > driver.
>
> Do you mean in drivers/pci/pcie/portdrv_pci.c? I see that it
> has a function called pcie_portdrv_slot_reset(), but I don't see
> how that relates to your reset line at the moment. Is this
> something you have submitted in a different series?
>
> Or do you mean in this host driver? The problem I see with
> that approach is that the port device is owned by portdrv_pci,
> so the host bridge driver should not look at the properties of
> the port.
hifsys: syscon at 1a000000 {
compatible = "mediatek,mt7623-hifsys", "syscon";
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
We have a reset controller(hifsys) in our platform. We can just use
devm_reset_control_get() to catch it in the host driver to control port reset.
After much consideration, I will move all nonstandard properties to root
node, let child node cleanable.
> >> > +- reset-names: Must include the following entries:
> >> > + - pcie-reset
> >> > +- num-lanes: Number of lanes to use for this port.
> >> > +- phys: Must contain an entry for each entry in phy-names.
> >> > +- phy-names: Must include an entry for each sub node. Entries are of the form
> >> > + "pcie-phyN": where N ranges from 0 to the value specified for port number.
> >> > + See ../phy/phy-mt7623-pcie.txt for details.
> >>
> >> I think the name should not include the number of the port but rather
> >> be always the same here.
> >>
> >
> > Hmm, I think it's better to keep the name here. It's more readable for
> > user to understand the relationship between port0 and phy0.
>
> No, I would argue that it's confusing for the reader because it
> is different from how most other DT bindings work: In each device
> node, you tend to have a set of properties with well-known names
> that are documented. When your reference is called "pcie-phy1"
> in one node and "pcie-phy2", I would interpret that as both ports
> having two phys each, but only one of them being used.
Okay I will write it more clearly
- phys: list of PHY specifiers (used by generic PHY framework)
- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on
the number of PHYs as specified in *phys* property.
^ permalink raw reply
* [PATCH 1/2] PCI: mediatek: Add Mediatek PCIe host controller support
From: Ryder Lee @ 2017-04-28 2:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a0DjPL8uWuXfCmEwt05SCPJ0yEQTAJmZAPtFDEfsn4a1Q@mail.gmail.com>
Hi,
On Thu, 2017-04-27 at 20:55 +0200, Arnd Bergmann wrote:
> On Wed, Apr 26, 2017 at 10:10 AM, Ryder Lee <ryder.lee@mediatek.com> wrote:
> > On Tue, 2017-04-25 at 14:38 +0200, Arnd Bergmann wrote:
> >> On Sun, Apr 23, 2017 at 10:19 AM, Ryder Lee <ryder.lee@mediatek.com> wrote:
>
> >> > +static int mtk_pcie_enable_ports(struct mtk_pcie *pcie)
> >> > +{
> >> > + struct device *dev = pcie->dev;
> >> > + struct mtk_pcie_port *port, *tmp;
> >> > + int err, linkup = 0;
> >> > +
> >> > + list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
> >> > + err = clk_prepare_enable(port->sys_ck);
> >> > + if (err) {
> >> > + dev_err(dev, "failed to enable port%d clock\n",
> >> > + port->index);
> >> > + continue;
> >> > + }
> >> > +
> >> > + /* assert RC */
> >> > + reset_control_assert(port->reset);
> >> > + /* de-assert RC */
> >> > + reset_control_deassert(port->reset);
> >> > +
> >> > + /* power on PHY */
> >> > + err = phy_power_on(port->phy);
> >> > + if (err) {
> >> > + dev_err(dev, "failed to power on port%d phy\n",
> >> > + port->index);
> >> > + goto err_phy_on;
> >> > + }
> >> > +
> >> > + mtk_pcie_assert_ports(port);
> >> > +
> >>
> >> Similar to the comment I had for the binding, I wonder if it would be
> >> better to keep all the information about the ports in one place and
> >> then just deal with it at the root level.
> >>
> >> Alternatively, we could decide to standardize on the properties
> >> you have added to the pcie port node, but then I would handle
> >> them in the pcieport driver rather than in the host bridge driver.
> >
> > Sorry, I'm not sure what you want me to do here.
> >
> > I could move all clock operation in root level. But we need to keep the
> > reset and PHY operation sequence in the loop, In addition, we could
> > easily free resources if ports link fail.
> >
> > How about moving this function to mtk_pcie_parse_and_add_res()?
>
> That could work, please try it out and see if the code gets better or
> worse. This may depend on what we end up doing with the DT
> properties.
I will try it on next version, and we can continue our discussion on
that series.
> >> > +/*
> >> > + * This IP lacks interrupt status register to check or map INTx from
> >> > + * different devices at the same time.
> >> > + */
> >> > +static int __init mtk_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
> >> > +{
> >> > + struct mtk_pcie *pcie = dev->bus->sysdata;
> >> > + struct mtk_pcie_port *port;
> >> > +
> >> > + list_for_each_entry(port, &pcie->ports, list)
> >> > + if (port->index == slot)
> >> > + return port->irq;
> >> > +
> >> > + return -1;
> >> > +}
> >>
> >> This looks odd, what is it needed for specifically? It looks like
> >> it's broken for devices behind bridges, and the interrupt mapping
> >> should normally come from the interrupt-map property, without
> >> the need for a driver specific map_irq override.
> >
> > Our hardware just has a GIC for each port and lacks interrupt status for
> > host driver to distinguish INTx. So I return port IRQ here.
>
> You should still be able to express this with standard interrupt-map
> DT property, without having to resort to your own map_irq
> callback handler.
>
> In the interrupt-map-mask, you can ignore the interrupt line
> only list the devfn of the root ports for each entry.
Okay, I will fix it.
> >> > +static int mtk_pcie_register_ports(struct mtk_pcie *pcie)
> >> > +{
> >> > + struct pci_bus *bus, *child;
> >> > +
> >> > + bus = pci_scan_root_bus(pcie->dev, 0, &mtk_pcie_ops, pcie,
> >> > + &pcie->resources);
> >>
> >> Can you use the new pci_register_host_bridge() method instead of
> >> pci_scan_root_bus() here?
> >
> > May I know what's difference between pci_scan_root_bus() and using
> > pci_register_host_bridge() directly? What situation should we use it?
> > It seems that just tegra use this new method currently.
>
> We introduced the new function for tegra for now, in the long run
> I would hope we can convert all other drivers to it as well, to make it
> easier to add further parameters.
>
> The new function also has a cleaner way of dealing with the memory
> allocations, similar to how other subsystems work.
Sounds good. I will change to use that.
Thanks!
^ permalink raw reply
* [PATCH v3 7/8] arm64: exception: handle asynchronous SError interrupt
From: Xiongfeng Wang @ 2017-04-28 2:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <58FE328E.7030106@arm.com>
Hi James,
Thanks for your explanation and suggests.
On 2017/4/25 1:14, James Morse wrote:
> Hi Wang Xiongfeng,
>
> On 21/04/17 12:33, Xiongfeng Wang wrote:
>> On 2017/4/20 16:52, James Morse wrote:
>>> On 19/04/17 03:37, Xiongfeng Wang wrote:
>>>> On 2017/4/18 18:51, James Morse wrote:
>>>>> The host expects to receive physical SError Interrupts. The ARM-ARM doesn't
>>>>> describe a way to inject these as they are generated by the CPU.
>>>>>
>>>>> Am I right in thinking you want this to use SError Interrupts as an APEI
>>>>> notification? (This isn't a CPU thing so the RAS spec doesn't cover this use)
>>>>
>>>> Yes, using sei as an APEI notification is one part of my consideration. Another use is for ESB.
>>>> RAS spec 6.5.3 'Example software sequences: Variant: asynchronous External Abort with ESB'
>>>> describes the SEI recovery process when ESB is implemented.
>>>>
>>>> In this situation, SEI is routed to EL3 (SCR_EL3.EA = 1). When an SEI occurs in EL0 and not been taken immediately,
>>>> and then an ESB instruction at SVC entry is executed, SEI is taken to EL3. The ESB at SVC entry is
>>>> used for preventing the error propagating from user space to kernel space. The EL3 SEI handler collects
>>>
>>>> the errors and fills in the APEI table, and then jump to EL2 SEI handler. EL2 SEI handler inject
>>>> an vSEI into EL1 by setting HCR_EL2.VSE = 1, so that when returned to OS, an SEI is pending.
>>>
>>> This step has confused me. How would this work with VHE where the host runs at
>>> EL2 and there is nothing at Host:EL1?
>>
>> RAS spec 6.5.3 'Example software sequences: Variant: asynchronous External Abort with ESB'
>> I don't know whether the step described in the section is designed for guest os or host os or both.
>> Yes, it doesn't work with VHE where the host runs at EL2.
>
> If it uses Virtual SError, it must be for an OS running at EL1, as the code
> running at EL2 (VHE:Linux, firmware or Xen) must set HCR_EL2.AMO to make this work.
>
> I can't find the section you describe in this RAS spec:
> https://developer.arm.com/docs/ddi0587/latest/armreliabilityavailabilityandserviceabilityrasspecificationarmv8forthearmv8aarchitectureprofile
>
I got the RAS spec from my company's ARM account. The document number is PRD03-PRDC-010953 .
>
>>> >From your description I assume you have some firmware resident at EL2.
>
>> Our actual SEI step is planned as follows:
>
> Ah, okay. You can't use Virtual SError at all then, as firmware doesn't own EL2:
> KVM does. KVM will save/restore the HCR_EL2 register as part of its world
> switch. Firmware must not modify the hyp registers behind the hyper-visors back.
>
>
>> Host OS: EL0/EL1 -> EL3 -> EL0/EL1
>
> i.e. While the host was running, so EL3 sees HCR_EL2.AMO clear, and directs the
> SEI to EL1.
>
>> Guest OS: EL0/EL1 -> EL3 -> EL2 -> EL0/EL1
>
> i.e. While the guest was running, so EL3 sees HCR_EL2.AMO set, directs the SEI
> to EL2 where KVM performs the world-switch and returns to host EL1.
>
> Looks sensible.
>
>
>> In guest os situation, we can inject an vSEI and return to where the SEI is taken from.
>
> An SEI from firmware should always end up in the host OS. If a guest was running
> KVM is responsible for doing the world switch to restore host EL1 and return
> there. This should all work today.
>
>
>> But in host os situation, we can't inject an vSEI (if we don't set HCR_EL2.AMO), so we have to jump to EL1 SEI vector.
>
> Because your firmware is at EL3 you have to check PSTATE.A and jump into the
> SError vector in both cases, you just choose if its VBAR_EL2 or VBAR_EL1 based
> on HCR_EL2.AMO.
>
>
>> Then the process following ESB won't be executed becuase SEI is taken to EL3 from the ESB instruction in EL1, and when control
>> is returned to OS, we are in EL1 SEI vector rather than the ESB instruction.
>
> Firmware should set ELR_EL1 so that an eret from the EL1 SError vector takes you
> back to the ESB instruction that took us to EL3 in the first place.
>
>
> There is a problem here mixing SError as the CPU->Software notification of RAS
> errors and as APEI's SEI Software->Software notification that a firmware-first
> error has been handled by EL3.
>
> To elaborate:
> The routine in this patch was something like:
> 1 ESB
> 2 Read DISR_EL1
> 3 If set, branch to the SError handler.
>
> If we have firmware-first ESB will generate an SError as PSTATE.A at EL{1,2}
> doesn't mask SError for EL3. Firmware can then handle the RAS error. With this
> the CPU->Software story is done. Firmware notifying the OS via APEI is a
> different problem.
>
> If the error doesn't need to be notified to the OS via SEI, firmware can return
> to step 1 above with DISR_EL1 clear. The OS may be told via another mechanism
> such as polling or an irq.
>
> If PSTATE.A was clear, firmware can return to the SError vector. If PSTATE.A was
> set and firmware knows this was due to an ESB, it can set DISR_EL1. The problem
> is firmware can't know if the SError was due to an ESB.
Yes, if implicit ESB is not implemented, we can't know if the sError was due to
an ESB unless we only set PSTATE.A when ESB is executed.
>
> The only time we are likely to have PSTATE.A masked is when changing exception
> level. For this we can rely on IESB, so step 1 isn't necessary in the routine
> above. Firmware knows if an SError taken to EL3 is due to an IESB, as the
> ESR_EL3.IESB bit will be set, in this case it can write to DISR_EL1 and return.
>
> In Linux we can use IESB for changes in exception level, and ESB with PSTATE.A
> clear for any other need. (e.g. __switch_to()). Firmware can notify us using SEI
> if we use either of these two patterns. This may not work for other OS (Xen?),
> but this is a problem with using SEI as an APEI notification method.
>
> (Some cleanup of our SError unmasking is needed, I have some patches I will post
> on a branch shortly)
>
>
>> It is ok to just ignore the process following the ESB instruction in el0_sync, because the process will be sent SIGBUS signal.
>
> I don't understand. How will Linux know the process caused an error if we
> neither take an SError nor read DISR_EL1 after an ESB?
>
I think there may be some misunderstanding here. The ESB instruction is placed in kernel_entry
of el0_sync and el0_irq. For the el0_sync, such as an syscall from userspace, after ESB is executed,
we check whether DISR.A is set. If it is not set, we go on to process the syscall. If it is set, we
jump to sError vector and then just eret.
But for el0_irq, after ESB is executed, we check whether DISR.A is set. If it is set, we jump to
(using BL) sError vector, process SEI, return back to irq handler and process irq, and then eret.
>
>> But for el0_irq, the irq process following the ESB may should be executed because the irq is not related to the user process.
>
> If we exit EL0 for an IRQ, and take an SError due to IESB we know the fault was
> due to EL0, not the exception level we entered to process the IRQ.
>
>
>> If we set HCR_EL2.AMO when SCR_EL3.EA is set. We can still inject an vSEI into host OS in EL3.
>
> (from EL3?) Only if the host OS is running at EL1 and isn't using EL2. Firmware
> can't know if we're using EL2 so this can't work.
>
>
>> Physical SError won't be taken to EL2 because SCR_EL3.EA is set. But this may be too racy is
>> not consistent with ARM rules.
>
> EL3 flipping bits in EL2 system registers behind EL2 software's back is going to
> have strange side effects. e.g. some Hypervisor may not change HCR_EL2 when
> switching VM-A to VM-B as the configuration is the same; now the virtual SError
> will be delivered to the wrong VM. (KVM doesn't do this, but Xen might.)
>
>
>>>>> You cant use SError to cover all the possible RAS exceptions. We already have
>>>>> this problem using SEI if PSTATE.A was set and the exception was an imprecise
>>>>> abort from EL2. We can't return to the interrupted context and we can't deliver
>>>>> an SError to EL2 either.
>>>>
>>>> SEI came from EL2 and PSTATE.A is set. Is it the situation where VHE is enabled and CPU is running
>>>> in kernel space. If SEI occurs in kernel space, can we just panic or shutdown.
>>>
>>> firmware-panic? We can do a little better than that:
>>> If the IESB bit is set in the ESR we can behave as if this were an ESB and have
>>> firmware write an appropriate ESR to DISR_EL1 if PSTATE.A is set and the
>>> exception came from EL2.
>>
>> This method may solve the problem I said above.
>> Is IESB a new bit added int ESR in the newest RAS spec?
>
> The latest ARM-ARM (DDI0487B.a) describes it as part of the "RAS Extension in
> ARMv8.2" in section 'A1.7.5 The Reliability, Availability, and Serviceability
> (RAS) Extension'.
>
> Jumping to 'D7.2.28 ESR_ELx, Exception Syndrome Register (ELx)', then page
> D7-2284 for the 'ISS encoding for an SError interrupt', it indicates "the SError
> interrupt was synchronized by the implicit [ESB] and taken immediately"
>
>
> As above, with IESB for changes in exception level, and unmasking PSTATE.A for
> any other use of ESB, Linux can make sure that firmware can always notify us of
> an APEI event using SEI.
>
> Another OS (or even UEFI) may not do the same, so firmware should be prepared
> for ESB to be executed with PSTATE.A masked (i.e, not using IESB). If there is
> no wider firmware-policy for this (reboot, notify a remote CPU), then returning
> to the faulting location and trying to inject SError later is all we can do.
>
>
> Thanks,
>
> James
>
> .
>
Thanks,
Wang Xiongfeng
^ permalink raw reply
* [PATCH] [media] pxa_camera: fix module remove codepath for v4l2 clock
From: Petr Cvek @ 2017-04-28 4:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87efwd1wus.fsf@belgarion.home>
Dne 27.4.2017 v 21:20 Robert Jarzmik napsal(a):
> Petr Cvek <petr.cvek@tul.cz> writes:
>
>> The conversion from soc_camera omitted a correct handling of the clock
>> gating for a sensor. When the pxa_camera driver module was removed it
>> tried to unregister clk, but this caused a similar warning:
>>
>> WARNING: CPU: 0 PID: 6740 at drivers/media/v4l2-core/v4l2-clk.c:278
>> v4l2_clk_unregister(): Refusing to unregister ref-counted 0-0030 clock!
>>
>> The clock was at time still refcounted by the sensor driver. Before
>> the removing of the pxa_camera the clock must be dropped by the sensor
>> driver. This should be triggered by v4l2_async_notifier_unregister() call
>> which removes sensor driver module too, calls unbind() function and then
>> tries to probe sensor driver again. Inside unbind() we can safely
>> unregister the v4l2 clock as the sensor driver got removed. The original
>> v4l2_clk_unregister() should be put inside test as the clock can be
>> already unregistered from unbind(). If there was not any bound sensor
>> the clock is still present.
>>
>> The codepath is practically a copy from the old soc_camera. The bug was
>> tested with a pxa_camera+ov9640 combination during the conversion
>> of the ov9640 from the soc_camera.
>>
>> Signed-off-by: Petr Cvek <petr.cvek@tul.cz>
>
> Yeah, it's way better with this patch, especially the insmod/rmmod/insmod/rmmod
> test.
I will post some other bugfixes (and feature adding) for pxa_camera soon. Do you wish to be CC'd?
P.S. Who is the the maintainer of pxa_camera BTW? Still Guennadi Liakhovetski? Basically pxa_camera is no longer part of the soc_camera and MAINTAINERS file does not exactly specify pxa_camera.c (I'm asking because I will send the patch for ov9640 soc_camera removal too :-D).
Best regards,
Petr
^ permalink raw reply
* [PATCH v2 0/4] Add support for ThunderX2 pmu events using json files
From: Ganapatrao Kulkarni @ 2017-04-28 4:53 UTC (permalink / raw)
To: linux-arm-kernel
Extending json/jevent framework for parsing arm64 event files.
Adding jevents for ThunderX2 implementation defined PMU events.
v2:
- Updated as per Mark Rutland's suggestions.
- added provision for get_cpuid_str to get cpu id string
from associated cpus of pmu core device.
v1: Initial patchset.
Ganapatrao Kulkarni (4):
perf utils: passing pmu as a parameter to function get_cpuid_str
perf tools arm64: Add support for get_cpuid_str function.
perf utils: Add helper function is_pmu_core to detect PMU CORE devices
perf vendor events arm64: Add implementation defined pmu core events
of ThunderX2
tools/perf/arch/arm64/util/Build | 1 +
tools/perf/arch/arm64/util/header.c | 41 ++++++++++++++
tools/perf/arch/powerpc/util/header.c | 3 +-
tools/perf/arch/x86/util/header.c | 4 +-
tools/perf/pmu-events/arch/arm64/mapfile.csv | 14 +++++
.../arm64/thunderx2/implementation-defined.json | 62 ++++++++++++++++++++++
tools/perf/util/header.h | 3 +-
tools/perf/util/pmu.c | 54 ++++++++++++++++---
8 files changed, 171 insertions(+), 11 deletions(-)
create mode 100644 tools/perf/arch/arm64/util/header.c
create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
--
1.8.1.4
^ permalink raw reply
* [PATCH v2 1/4] perf utils: passing pmu as a parameter to function get_cpuid_str
From: Ganapatrao Kulkarni @ 2017-04-28 4:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493355227-31492-1-git-send-email-ganapatrao.kulkarni@cavium.com>
cpuid string will not be same on all CPUs on heterogeneous
platforms like ARM's big.LITTLE, adding provision(using pmu->cpus)
to find cpuid string from associated CPUs of PMU CORE device.
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
| 3 ++-
| 4 +++-
| 3 ++-
tools/perf/util/pmu.c | 10 ++++++----
4 files changed, 13 insertions(+), 7 deletions(-)
--git a/tools/perf/arch/powerpc/util/header.c b/tools/perf/arch/powerpc/util/header.c
index 9aaa6f5..9a70cc1 100644
--- a/tools/perf/arch/powerpc/util/header.c
+++ b/tools/perf/arch/powerpc/util/header.c
@@ -34,10 +34,11 @@
}
char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu)
{
char *bufp;
+ do { if (pmu) {} } while (0);
if (asprintf(&bufp, "%.8lx", mfspr(SPRN_PVR)) < 0)
bufp = NULL;
--git a/tools/perf/arch/x86/util/header.c b/tools/perf/arch/x86/util/header.c
index a74a48d..1e240ca 100644
--- a/tools/perf/arch/x86/util/header.c
+++ b/tools/perf/arch/x86/util/header.c
@@ -65,10 +65,12 @@
}
char *
-get_cpuid_str(void)
+get_cpuid_str(struct perf_pmu *pmu)
{
char *buf = malloc(128);
+ do { if (pmu) {} } while (0);
+
if (__get_cpuid(buf, 128, "%s-%u-%X$") < 0) {
free(buf);
return NULL;
--git a/tools/perf/util/header.h b/tools/perf/util/header.h
index d30109b..6bb14a4 100644
--- a/tools/perf/util/header.h
+++ b/tools/perf/util/header.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include "event.h"
#include "env.h"
+#include "pmu.h"
enum {
HEADER_RESERVED = 0, /* always cleared */
@@ -151,5 +152,5 @@ int perf_event__process_build_id(struct perf_tool *tool,
*/
int get_cpuid(char *buffer, size_t sz);
-char *get_cpuid_str(void);
+char *get_cpuid_str(struct perf_pmu *pmu);
#endif /* __PERF_HEADER_H */
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 12f84dd..c754805 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -504,8 +504,9 @@ static struct cpu_map *pmu_cpumask(const char *name)
* Each architecture should provide a more precise id string that
* can be use to match the architecture's "mapfile".
*/
-char * __weak get_cpuid_str(void)
+char * __weak get_cpuid_str(struct perf_pmu *pmu)
{
+ do { if (pmu) {} } while (0);
return NULL;
}
@@ -514,7 +515,8 @@ char * __weak get_cpuid_str(void)
* to the current running CPU. Then, add all PMU events from that table
* as aliases.
*/
-static void pmu_add_cpu_aliases(struct list_head *head, const char *name)
+static void pmu_add_cpu_aliases(struct list_head *head, const char *name,
+ struct perf_pmu *pmu)
{
int i;
struct pmu_events_map *map;
@@ -526,7 +528,7 @@ static void pmu_add_cpu_aliases(struct list_head *head, const char *name)
if (cpuid)
cpuid = strdup(cpuid);
if (!cpuid)
- cpuid = get_cpuid_str();
+ cpuid = get_cpuid_str(pmu);
if (!cpuid)
return;
@@ -601,12 +603,12 @@ static struct perf_pmu *pmu_lookup(const char *name)
if (pmu_aliases(name, &aliases))
return NULL;
- pmu_add_cpu_aliases(&aliases, name);
pmu = zalloc(sizeof(*pmu));
if (!pmu)
return NULL;
pmu->cpus = pmu_cpumask(name);
+ pmu_add_cpu_aliases(&aliases, name, pmu);
INIT_LIST_HEAD(&pmu->format);
INIT_LIST_HEAD(&pmu->aliases);
--
1.8.1.4
^ permalink raw reply related
* [PATCH v2 2/4] perf tools arm64: Add support for get_cpuid_str function.
From: Ganapatrao Kulkarni @ 2017-04-28 4:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493355227-31492-1-git-send-email-ganapatrao.kulkarni@cavium.com>
function get_cpuid_str returns MIDR string of the first online
cpu from the range of cpus associated with the pmu core device.
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
tools/perf/arch/arm64/util/Build | 1 +
| 41 +++++++++++++++++++++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 tools/perf/arch/arm64/util/header.c
diff --git a/tools/perf/arch/arm64/util/Build b/tools/perf/arch/arm64/util/Build
index cef6fb3..b1ab72d 100644
--- a/tools/perf/arch/arm64/util/Build
+++ b/tools/perf/arch/arm64/util/Build
@@ -1,3 +1,4 @@
+libperf-y += header.o
libperf-$(CONFIG_DWARF) += dwarf-regs.o
libperf-$(CONFIG_LOCAL_LIBUNWIND) += unwind-libunwind.o
--git a/tools/perf/arch/arm64/util/header.c b/tools/perf/arch/arm64/util/header.c
new file mode 100644
index 0000000..d8980a6b
--- /dev/null
+++ b/tools/perf/arch/arm64/util/header.c
@@ -0,0 +1,41 @@
+#include <stdio.h>
+#include <stdlib.h>
+#include "header.h"
+
+#define LINUX_SYS_CPU_DIRECTORY "/sys/devices/system/cpu/"
+#define MIDR "/regs/identification/midr_el1"
+
+char *get_cpuid_str(struct perf_pmu *pmu)
+{
+ char *buf = malloc(128);
+ FILE *file;
+ char *ret = NULL;
+ int cpu;
+ char sys_file[256];
+ struct cpu_map *cpus;
+
+ if (!pmu->cpus)
+ return NULL;
+
+ /* read midr from list of cpus mapped to this pmu */
+ cpus = cpu_map__get(pmu->cpus);
+
+ for (cpu = 0; cpu < cpus->nr; cpu++) {
+ sprintf(sys_file, LINUX_SYS_CPU_DIRECTORY"cpu%d"MIDR,
+ cpus->map[cpu]);
+ file = fopen(sys_file, "r");
+ if (file) {
+ ret = fgets(buf, 128, file);
+ if (ret) {
+ buf[strlen(buf)-1] = '\0';
+ fclose(file);
+ cpu_map__put(cpus);
+ return buf;
+ }
+ fclose(file);
+ }
+ }
+ cpu_map__put(cpus);
+ free(buf);
+ return ret;
+}
--
1.8.1.4
^ permalink raw reply related
* [PATCH v2 3/4] perf utils: Add helper function is_pmu_core to detect PMU CORE devices
From: Ganapatrao Kulkarni @ 2017-04-28 4:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493355227-31492-1-git-send-email-ganapatrao.kulkarni@cavium.com>
On some platforms, PMU core devices sysfs name is not cpu.
Adding function is_pmu_core to detect as core device using
core device specific hints in sysfs.
For arm64 platforms, all core devices have file "cpus" in sysfs.
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
tools/perf/util/pmu.c | 44 ++++++++++++++++++++++++++++++++++++++++----
1 file changed, 40 insertions(+), 4 deletions(-)
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index c754805..48333fe 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -499,6 +499,39 @@ static struct cpu_map *pmu_cpumask(const char *name)
}
/*
+ * PMU CORE devices have different name other than cpu in sysfs on some
+ * platforms. looking for possible sysfs files to identify as core device.
+ */
+static int is_pmu_core(const char *name)
+{
+ struct stat st;
+ char path[PATH_MAX];
+ const char *sysfs = sysfs__mountpoint();
+ const char **template;
+ const char *templates[] = {
+ "%s/bus/event_source/devices/%s/cpus",
+ NULL
+ };
+
+ if (!sysfs)
+ return 0;
+
+ /* Look for cpu sysfs */
+ snprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu", sysfs);
+ if ((stat(path, &st) == 0) &&
+ (strncmp(name, "cpu", strlen("cpu")) == 0))
+ return 1;
+
+ for (template = templates; *template; template++) {
+ snprintf(path, PATH_MAX, *template, sysfs, name);
+ if (stat(path, &st) == 0)
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
* Return the CPU id as a raw string.
*
* Each architecture should provide a more precise id string that
@@ -552,15 +585,18 @@ static void pmu_add_cpu_aliases(struct list_head *head, const char *name,
*/
i = 0;
while (1) {
- const char *pname;
pe = &map->table[i++];
if (!pe->name)
break;
- pname = pe->pmu ? pe->pmu : "cpu";
- if (strncmp(pname, name, strlen(pname)))
- continue;
+ if (!is_pmu_core(name)) {
+ /* check for uncore devices */
+ if (pe->pmu == NULL)
+ continue;
+ if (strncmp(pe->pmu, name, strlen(pe->pmu)))
+ continue;
+ }
/* need type casts to override 'const' */
__perf_pmu__new_alias(head, NULL, (char *)pe->name,
--
1.8.1.4
^ permalink raw reply related
* [PATCH v2 4/4] perf vendor events arm64: Add implementation defined pmu core events of ThunderX2
From: Ganapatrao Kulkarni @ 2017-04-28 4:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493355227-31492-1-git-send-email-ganapatrao.kulkarni@cavium.com>
This is not a full event list, but a short list of useful events.
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
tools/perf/pmu-events/arch/arm64/mapfile.csv | 14 +++++
.../arm64/thunderx2/implementation-defined.json | 62 ++++++++++++++++++++++
2 files changed, 76 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/mapfile.csv
create mode 100644 tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
diff --git a/tools/perf/pmu-events/arch/arm64/mapfile.csv b/tools/perf/pmu-events/arch/arm64/mapfile.csv
new file mode 100644
index 0000000..bc9f798
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/mapfile.csv
@@ -0,0 +1,14 @@
+# Format:
+# MIDR,Version,JSON/file/pathname,Type
+#
+# where
+# MIDR Processor version
+# Version could be used to track version of of JSON file
+# but currently unused.
+# JSON/file/pathname is the path to JSON file, relative
+# to tools/perf/pmu-events/arch/arm64/.
+# Type is core, uncore etc
+#
+#
+#Family-model,Version,Filename,EventType
+0x00000000420f5161,v1,thunderx2,core
diff --git a/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
new file mode 100644
index 0000000..cdb03db
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/thunderx2/implementation-defined.json
@@ -0,0 +1,62 @@
+[
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, read",
+ "EventCode": "0x40",
+ "EventName": "l1d_cache_access_read",
+ "BriefDescription": "l1d cache access, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache access, write ",
+ "EventCode": "0x41",
+ "EventName": "l1d_cache_access_write",
+ "BriefDescription": "l1d cache access, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, read",
+ "EventCode": "0x42",
+ "EventName": "l1d_cache_refill_read",
+ "BriefDescription": "l1d cache refill, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data cache refill, write",
+ "EventCode": "0x43",
+ "EventName": "l1d_cache_refill_write",
+ "BriefDescription": "l1d refill, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, read",
+ "EventCode": "0x4C",
+ "EventName": "l1d_tlb_refill_read",
+ "BriefDescription": "l1d tlb refill, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data TLB refill, write",
+ "EventCode": "0x4D",
+ "EventName": "l1d_tlb_refill_write",
+ "BriefDescription": "l1d tlb refill, write",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, read",
+ "EventCode": "0x4E",
+ "EventName": "l1d_tlb_read",
+ "BriefDescription": "l1d tlb, read",
+ },
+ {
+ "PublicDescription": "Attributable Level 1 data or unified TLB access, write",
+ "EventCode": "0x4F",
+ "EventName": "l1d_tlb_write",
+ "BriefDescription": "l1d tlb, write",
+ },
+ {
+ "PublicDescription": "Bus access, read",
+ "EventCode": "0x60",
+ "EventName": "bus_access_read",
+ "BriefDescription": "Bus access, read",
+ },
+ {
+ "PublicDescription": "Bus access, write",
+ "EventCode": "0x61",
+ "EventName": "bus_access_write",
+ "BriefDescription": "Bus access, write",
+ }
+]
--
1.8.1.4
^ permalink raw reply related
* [PATCH 0/9] ARM: dts: renesas: update PFC node name to pin-controller
From: Simon Horman @ 2017-04-28 5:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdVtMAMEjbEUA+ypwK5V+Sh+mEPs14_rUe0e4--sH=sTjw@mail.gmail.com>
On Wed, Apr 26, 2017 at 01:20:52PM +0200, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Wed, Apr 26, 2017 at 12:05 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > The device trees for Renesas SoCs use either pfc or pin-controller as the
> > node name for the PFC device. This patch is intended to take a step towards
> > unifying the node name used as pin-controller which appears to be the more
> > generic of the two and thus more in keeping with the DT specs.
> >
> > My analysis is that this is a user-visible change to the extent that kernel
> > logs, and sysfs entries change from XXX.pfc and pfc at XXX to
> > XXX.pin-controller and pin-controller at XXX.
> >
> > Boot tested on:
> > r8a73a4/ape6evm
> > r8a7740/armadillo800evb
> > r8a7778/bockw
> > r8a7790/lager
> > r8a7791/koelsch
> > r8a7791/porter
> > r8a7793/gose
> > sh73a9/kzm9g
> >
> > Not tested on (due to lack of hw access):
> > evm2/kzm9d
> > r8a7789/marzen
> >
> > Simon Horman (9):
>
> For the whole series:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have queued these up.
^ permalink raw reply
* [PATCH v2] arm: dts: sun7i-a20-bananapi: name the GPIO lines
From: Oleksij Rempel @ 2017-04-28 5:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZn7-SL5kmGn7Pysz=QiQFBEm8+c6bw=hE5F0CV4ct0RQ@mail.gmail.com>
Am 08.08.2016 um 19:51 schrieb Linus Walleij:
> On Fri, Aug 5, 2016 at 10:06 AM, Oleksij Rempel <linux@rempel-privat.de> wrote:
>
>> This names the GPIO lines on the Banana Pi board in accordance with
>> the A20_Banana_Pi v1.4 Specification.
>>
>> This will make these line names reflect through to userspace
>> so that they can easily be identified and used with the new
>> character device ABI.
>>
>> Some care has been taken to name all lines, not just those used
>> by the external connectors, also lines that are muxed into some
>> other function than GPIO: these are named "[FOO]" so that users
>> can see with lsgpio what all lines are used for.
>>
>> Ps: most of the text was taken from Linus Wallej patch.
>>
>> Cc: devicetree at vger.kernel.org
>> Cc: Linus Walleij <linus.walleij@linaro.org>
>> Cc: linux-arm-kernel at lists.infradead.org
>> Cc: Chen-Yu Tsai <wens@csie.org>
>> Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> Yours,
> Linus Walleij
Hm... i assume this patch was lost. Should i resend it?
--
Regards,
Oleksij
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 213 bytes
Desc: OpenPGP digital signature
URL: <http://lists.infradead.org/pipermail/linux-arm-kernel/attachments/20170428/8543b817/attachment.sig>
^ permalink raw reply
* [PATCH v2 pci] PCI/MSI: pci-xgene-msi: Enable MSI support in ACPI boot for X-Gene v1
From: Jon Masters @ 2017-04-28 5:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493340847-25720-1-git-send-email-kdinh@apm.com>
On 04/27/2017 08:54 PM, Khuong Dinh wrote:
> From: Khuong Dinh <kdinh@apm.com>
>
> This patch makes pci-xgene-msi driver ACPI-aware and provides
> MSI capability for X-Gene v1 PCIe controllers in ACPI boot mode.
>
> Signed-off-by: Khuong Dinh <kdinh@apm.com>
> Signed-off-by: Duc Dang <dhdang@apm.com>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Thanks. Currently testing. Will review and followup shortly.
Jon.
--
Computer Architect | Sent from my Fedora powered laptop
^ permalink raw reply
* [PATCH] [media] pxa_camera: fix module remove codepath for v4l2 clock
From: Robert Jarzmik @ 2017-04-28 6:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c95ef700-d34d-5aa2-ef92-ad1aa7dd5a0d@tul.cz>
Petr Cvek <petr.cvek@tul.cz> writes:
> I will post some other bugfixes (and feature adding) for pxa_camera soon. Do you wish to be CC'd?
>
> P.S. Who is the the maintainer of pxa_camera BTW? Still Guennadi Liakhovetski?
Euh no, that's me.
I had submitted a patch for that here :
https://patchwork.kernel.org/patch/9316499
Hans, do you want to pick it up ?
Cheers.
--
Robert
^ permalink raw reply
* [PATCH v1 2/2] clk: rockchip: export rk3228 clocks ID
From: Heiko Stuebner @ 2017-04-28 6:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493346801-23785-3-git-send-email-zhangqing@rock-chips.com>
Hi Elaine,
Am Freitag, 28. April 2017, 10:33:21 CEST schrieb Elaine Zhang:
> This patch exports related BUS/VPU/RGA/HDCP/IEP/TSP/WIFI/
> VIO/USB/EFUSE/GPU/CRYPTO clocks for dts reference.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
As always, please separate this into two patches with one adding the
clock-ids to the rk3228-cru.h and a second patch then doing the
assignment in clk-rk3228.c
Thanks
Heiko
> ---
> drivers/clk/rockchip/clk-rk3228.c | 92 +++++++++++++++++-----------------
> include/dt-bindings/clock/rk3228-cru.h | 47 +++++++++++++++++
> 2 files changed, 93 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
> index a6cdf8fc1e75..7ded7d63d53e 100644
> --- a/drivers/clk/rockchip/clk-rk3228.c
> +++ b/drivers/clk/rockchip/clk-rk3228.c
> @@ -270,15 +270,15 @@ enum rk3228_plls {
> RK2928_CLKGATE_CON(0), 1, GFLAGS),
> COMPOSITE_NOGATE(0, "aclk_cpu_src", mux_aclk_cpu_src_p, 0,
> RK2928_CLKSEL_CON(0), 13, 2, MFLAGS, 8, 5, DFLAGS),
> - GATE(ARMCLK, "aclk_cpu", "aclk_cpu_src", 0,
> + GATE(ACLK_CPU, "aclk_cpu", "aclk_cpu_src", 0,
> RK2928_CLKGATE_CON(6), 0, GFLAGS),
> - COMPOSITE_NOMUX(0, "hclk_cpu", "aclk_cpu_src", 0,
> + COMPOSITE_NOMUX(HCLK_CPU, "hclk_cpu", "aclk_cpu_src", 0,
> RK2928_CLKSEL_CON(1), 8, 2, DFLAGS,
> RK2928_CLKGATE_CON(6), 1, GFLAGS),
> COMPOSITE_NOMUX(0, "pclk_bus_src", "aclk_cpu_src", 0,
> RK2928_CLKSEL_CON(1), 12, 3, DFLAGS,
> RK2928_CLKGATE_CON(6), 2, GFLAGS),
> - GATE(0, "pclk_cpu", "pclk_bus_src", 0,
> + GATE(PCLK_CPU, "pclk_cpu", "pclk_bus_src", 0,
> RK2928_CLKGATE_CON(6), 3, GFLAGS),
> GATE(0, "pclk_phy_pre", "pclk_bus_src", 0,
> RK2928_CLKGATE_CON(6), 4, GFLAGS),
> @@ -286,58 +286,58 @@ enum rk3228_plls {
> RK2928_CLKGATE_CON(6), 13, GFLAGS),
>
> /* PD_VIDEO */
> - COMPOSITE(0, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
> + COMPOSITE(ACLK_VPU_PRE, "aclk_vpu_pre", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(32), 5, 2, MFLAGS, 0, 5, DFLAGS,
> RK2928_CLKGATE_CON(3), 11, GFLAGS),
> - FACTOR_GATE(0, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
> + FACTOR_GATE(HCLK_VPU_PRE, "hclk_vpu_pre", "aclk_vpu_pre", 0, 1, 4,
> RK2928_CLKGATE_CON(4), 4, GFLAGS),
>
> - COMPOSITE(0, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
> + COMPOSITE(ACLK_RKVDEC_PRE, "aclk_rkvdec_pre", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(28), 6, 2, MFLAGS, 0, 5, DFLAGS,
> RK2928_CLKGATE_CON(3), 2, GFLAGS),
> - FACTOR_GATE(0, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
> + FACTOR_GATE(HCLK_RKVDEC_PRE, "hclk_rkvdec_pre", "aclk_rkvdec_pre", 0, 1, 4,
> RK2928_CLKGATE_CON(4), 5, GFLAGS),
>
> - COMPOSITE(0, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
> + COMPOSITE(SCLK_VDEC_CABAC, "sclk_vdec_cabac", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(28), 14, 2, MFLAGS, 8, 5, DFLAGS,
> RK2928_CLKGATE_CON(3), 3, GFLAGS),
>
> - COMPOSITE(0, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
> + COMPOSITE(SCLK_VDEC_CORE, "sclk_vdec_core", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(34), 13, 2, MFLAGS, 8, 5, DFLAGS,
> RK2928_CLKGATE_CON(3), 4, GFLAGS),
>
> /* PD_VIO */
> - COMPOSITE(0, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
> + COMPOSITE(ACLK_IEP_PRE, "aclk_iep_pre", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(31), 5, 2, MFLAGS, 0, 5, DFLAGS,
> RK2928_CLKGATE_CON(3), 0, GFLAGS),
> - DIV(0, "hclk_vio_pre", "aclk_iep_pre", 0,
> + DIV(HCLK_VIO_PRE, "hclk_vio_pre", "aclk_iep_pre", 0,
> RK2928_CLKSEL_CON(2), 0, 5, DFLAGS),
>
> - COMPOSITE(0, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
> + COMPOSITE(ACLK_HDCP_PRE, "aclk_hdcp_pre", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(31), 13, 2, MFLAGS, 8, 5, DFLAGS,
> RK2928_CLKGATE_CON(1), 4, GFLAGS),
>
> MUX(0, "sclk_rga_src", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(33), 13, 2, MFLAGS),
> - COMPOSITE_NOMUX(0, "aclk_rga_pre", "sclk_rga_src", 0,
> + COMPOSITE_NOMUX(ACLK_RGA_PRE, "aclk_rga_pre", "sclk_rga_src", 0,
> RK2928_CLKSEL_CON(33), 8, 5, DFLAGS,
> RK2928_CLKGATE_CON(1), 2, GFLAGS),
> - COMPOSITE(0, "sclk_rga", mux_sclk_rga_p, 0,
> + COMPOSITE(SCLK_RGA, "sclk_rga", mux_sclk_rga_p, 0,
> RK2928_CLKSEL_CON(22), 5, 2, MFLAGS, 0, 5, DFLAGS,
> RK2928_CLKGATE_CON(3), 6, GFLAGS),
>
> - COMPOSITE(0, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
> + COMPOSITE(ACLK_VOP_PRE, "aclk_vop_pre", mux_pll_src_4plls_p, 0,
> RK2928_CLKSEL_CON(33), 5, 2, MFLAGS, 0, 5, DFLAGS,
> RK2928_CLKGATE_CON(1), 1, GFLAGS),
>
> - COMPOSITE(0, "sclk_hdcp", mux_pll_src_3plls_p, 0,
> + COMPOSITE(SCLK_HDCP, "sclk_hdcp", mux_pll_src_3plls_p, 0,
> RK2928_CLKSEL_CON(23), 14, 2, MFLAGS, 8, 6, DFLAGS,
> RK2928_CLKGATE_CON(3), 5, GFLAGS),
>
> GATE(SCLK_HDMI_HDCP, "sclk_hdmi_hdcp", "xin24m", 0,
> RK2928_CLKGATE_CON(3), 7, GFLAGS),
>
> - COMPOSITE(0, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
> + COMPOSITE(SCLK_HDMI_CEC, "sclk_hdmi_cec", mux_sclk_hdmi_cec_p, 0,
> RK2928_CLKSEL_CON(21), 14, 2, MFLAGS, 0, 14, DFLAGS,
> RK2928_CLKGATE_CON(3), 8, GFLAGS),
>
> @@ -372,18 +372,18 @@ enum rk3228_plls {
> GATE(SCLK_TIMER5, "sclk_timer5", "xin24m", 0,
> RK2928_CLKGATE_CON(6), 10, GFLAGS),
>
> - COMPOSITE(0, "sclk_crypto", mux_pll_src_2plls_p, 0,
> + COMPOSITE(SCLK_CRYPTO, "sclk_crypto", mux_pll_src_2plls_p, 0,
> RK2928_CLKSEL_CON(24), 5, 1, MFLAGS, 0, 5, DFLAGS,
> RK2928_CLKGATE_CON(2), 7, GFLAGS),
>
> - COMPOSITE(0, "sclk_tsp", mux_pll_src_2plls_p, 0,
> + COMPOSITE(SCLK_TSP, "sclk_tsp", mux_pll_src_2plls_p, 0,
> RK2928_CLKSEL_CON(22), 15, 1, MFLAGS, 8, 5, DFLAGS,
> RK2928_CLKGATE_CON(2), 6, GFLAGS),
>
> - GATE(0, "sclk_hsadc", "ext_hsadc", 0,
> + GATE(SCLK_HSADC, "sclk_hsadc", "ext_hsadc", 0,
> RK2928_CLKGATE_CON(10), 12, GFLAGS),
>
> - COMPOSITE(0, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
> + COMPOSITE(SCLK_WIFI, "sclk_wifi", mux_pll_src_cpll_gpll_usb480m_p, 0,
> RK2928_CLKSEL_CON(23), 5, 2, MFLAGS, 0, 6, DFLAGS,
> RK2928_CLKGATE_CON(2), 15, GFLAGS),
>
> @@ -466,9 +466,9 @@ enum rk3228_plls {
> GATE(0, "jtag", "ext_jtag", 0,
> RK2928_CLKGATE_CON(1), 3, GFLAGS),
>
> - GATE(0, "sclk_otgphy0", "xin24m", 0,
> + GATE(SCLK_OTGPHY0, "sclk_otgphy0", "xin24m", 0,
> RK2928_CLKGATE_CON(1), 5, GFLAGS),
> - GATE(0, "sclk_otgphy1", "xin24m", 0,
> + GATE(SCLK_OTGPHY1, "sclk_otgphy1", "xin24m", 0,
> RK2928_CLKGATE_CON(1), 6, GFLAGS),
>
> COMPOSITE_NOMUX(SCLK_TSADC, "sclk_tsadc", "xin24m", 0,
> @@ -544,28 +544,28 @@ enum rk3228_plls {
> */
>
> /* PD_VOP */
> - GATE(0, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
> + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 0, GFLAGS),
> GATE(0, "aclk_rga_noc", "aclk_rga_pre", 0, RK2928_CLKGATE_CON(13), 11, GFLAGS),
> - GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
> + GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
> GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
>
> GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
> GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
>
> - GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
> + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
> GATE(0, "aclk_hdcp_noc", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(13), 10, GFLAGS),
>
> - GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
> - GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
> + GATE(HCLK_RGA, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
> + GATE(HCLK_IEP, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
> GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
> GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
> GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
> GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),
> - GATE(0, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
> - GATE(0, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
> + GATE(HCLK_VIO_H2P, "hclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 7, GFLAGS),
> + GATE(HCLK_HDCP_MMU, "hclk_hdcp_mmu", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 12, GFLAGS),
> GATE(PCLK_HDMI_CTRL, "pclk_hdmi_ctrl", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 6, GFLAGS),
> - GATE(0, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
> - GATE(0, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
> + GATE(PCLK_VIO_H2P, "pclk_vio_h2p", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 8, GFLAGS),
> + GATE(PCLK_HDCP, "pclk_hdcp", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(14), 11, GFLAGS),
>
> /* PD_PERI */
> GATE(0, "aclk_peri_noc", "aclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 0, GFLAGS),
> @@ -575,12 +575,12 @@ enum rk3228_plls {
> GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 1, GFLAGS),
> GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 2, GFLAGS),
> GATE(HCLK_NANDC, "hclk_nandc", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 3, GFLAGS),
> - GATE(0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
> + GATE(HCLK_HOST0, "hclk_host0", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 6, GFLAGS),
> GATE(0, "hclk_host0_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 7, GFLAGS),
> - GATE(0, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
> + GATE(HCLK_HOST1, "hclk_host1", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 8, GFLAGS),
> GATE(0, "hclk_host1_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 9, GFLAGS),
> - GATE(0, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
> - GATE(0, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
> + GATE(HCLK_HOST2, "hclk_host2", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 10, GFLAGS),
> + GATE(HCLK_OTG, "hclk_otg", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 12, GFLAGS),
> GATE(0, "hclk_otg_pmu", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 13, GFLAGS),
> GATE(0, "hclk_host2_arb", "hclk_peri", 0, RK2928_CLKGATE_CON(11), 14, GFLAGS),
> GATE(0, "hclk_peri_noc", "hclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 1, GFLAGS),
> @@ -589,7 +589,7 @@ enum rk3228_plls {
> GATE(0, "pclk_peri_noc", "pclk_peri", CLK_IGNORE_UNUSED, RK2928_CLKGATE_CON(12), 2, GFLAGS),
>
> /* PD_GPU */
> - GATE(0, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
> + GATE(ACLK_GPU, "aclk_gpu", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 14, GFLAGS),
> GATE(0, "aclk_gpu_noc", "aclk_gpu_pre", 0, RK2928_CLKGATE_CON(13), 15, GFLAGS),
>
> /* PD_BUS */
> @@ -603,16 +603,16 @@ enum rk3228_plls {
> GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 8, GFLAGS),
> GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 9, GFLAGS),
> GATE(HCLK_SPDIF_8CH, "hclk_spdif_8ch", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 10, GFLAGS),
> - GATE(0, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
> - GATE(0, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
> - GATE(0, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
> + GATE(HCLK_TSP, "hclk_tsp", "hclk_cpu", 0, RK2928_CLKGATE_CON(10), 11, GFLAGS),
> + GATE(HCLK_M_CRYPTO, "hclk_crypto_mst", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 11, GFLAGS),
> + GATE(HCLK_S_CRYPTO, "hclk_crypto_slv", "hclk_cpu", 0, RK2928_CLKGATE_CON(8), 12, GFLAGS),
>
> GATE(0, "pclk_ddrupctl", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 4, GFLAGS),
> GATE(0, "pclk_ddrmon", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(8), 6, GFLAGS),
> GATE(0, "pclk_msch_noc", "pclk_ddr_pre", 0, RK2928_CLKGATE_CON(10), 2, GFLAGS),
>
> - GATE(0, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
> - GATE(0, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
> + GATE(PCLK_EFUSE_1024, "pclk_efuse_1024", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 13, GFLAGS),
> + GATE(PCLK_EFUSE_256, "pclk_efuse_256", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 14, GFLAGS),
> GATE(PCLK_I2C0, "pclk_i2c0", "pclk_cpu", 0, RK2928_CLKGATE_CON(8), 15, GFLAGS),
> GATE(PCLK_I2C1, "pclk_i2c1", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 0, GFLAGS),
> GATE(PCLK_I2C2, "pclk_i2c2", "pclk_cpu", 0, RK2928_CLKGATE_CON(9), 1, GFLAGS),
> @@ -640,13 +640,13 @@ enum rk3228_plls {
> GATE(0, "pclk_vdacphy", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 8, GFLAGS),
> GATE(0, "pclk_phy_noc", "pclk_phy_pre", 0, RK2928_CLKGATE_CON(10), 9, GFLAGS),
>
> - GATE(0, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
> + GATE(ACLK_VPU, "aclk_vpu", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 0, GFLAGS),
> GATE(0, "aclk_vpu_noc", "aclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 4, GFLAGS),
> - GATE(0, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
> + GATE(ACLK_RKVDEC, "aclk_rkvdec", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 2, GFLAGS),
> GATE(0, "aclk_rkvdec_noc", "aclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 6, GFLAGS),
> - GATE(0, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
> + GATE(HCLK_VPU, "hclk_vpu", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 1, GFLAGS),
> GATE(0, "hclk_vpu_noc", "hclk_vpu_pre", 0, RK2928_CLKGATE_CON(15), 5, GFLAGS),
> - GATE(0, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
> + GATE(HCLK_RKVDEC, "hclk_rkvdec", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 3, GFLAGS),
> GATE(0, "hclk_rkvdec_noc", "hclk_rkvdec_pre", 0, RK2928_CLKGATE_CON(15), 7, GFLAGS),
>
> /* PD_MMC */
> diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h
> index b27e2b1a65e3..56f841c22801 100644
> --- a/include/dt-bindings/clock/rk3228-cru.h
> +++ b/include/dt-bindings/clock/rk3228-cru.h
> @@ -61,6 +61,17 @@
> #define SCLK_MAC_TX 130
> #define SCLK_MAC_PHY 131
> #define SCLK_MAC_OUT 132
> +#define SCLK_VDEC_CABAC 133
> +#define SCLK_VDEC_CORE 134
> +#define SCLK_RGA 135
> +#define SCLK_HDCP 136
> +#define SCLK_HDMI_CEC 137
> +#define SCLK_CRYPTO 138
> +#define SCLK_TSP 139
> +#define SCLK_HSADC 140
> +#define SCLK_WIFI 141
> +#define SCLK_OTGPHY0 142
> +#define SCLK_OTGPHY1 143
>
> /* dclk gates */
> #define DCLK_VOP 190
> @@ -68,15 +79,32 @@
>
> /* aclk gates */
> #define ACLK_DMAC 194
> +#define ACLK_CPU 195
> +#define ACLK_VPU_PRE 196
> +#define ACLK_RKVDEC_PRE 197
> +#define ACLK_RGA_PRE 198
> +#define ACLK_IEP_PRE 199
> +#define ACLK_HDCP_PRE 200
> +#define ACLK_VOP_PRE 201
> +#define ACLK_VPU 202
> +#define ACLK_RKVDEC 203
> +#define ACLK_IEP 204
> +#define ACLK_RGA 205
> +#define ACLK_HDCP 206
> #define ACLK_PERI 210
> #define ACLK_VOP 211
> #define ACLK_GMAC 212
> +#define ACLK_GPU 213
>
> /* pclk gates */
> #define PCLK_GPIO0 320
> #define PCLK_GPIO1 321
> #define PCLK_GPIO2 322
> #define PCLK_GPIO3 323
> +#define PCLK_VIO_H2P 324
> +#define PCLK_HDCP 325
> +#define PCLK_EFUSE_1024 326
> +#define PCLK_EFUSE_256 327
> #define PCLK_GRF 329
> #define PCLK_I2C0 332
> #define PCLK_I2C1 333
> @@ -89,6 +117,7 @@
> #define PCLK_TSADC 344
> #define PCLK_PWM 350
> #define PCLK_TIMER 353
> +#define PCLK_CPU 354
> #define PCLK_PERI 363
> #define PCLK_HDMI_CTRL 364
> #define PCLK_HDMI_PHY 365
> @@ -104,6 +133,24 @@
> #define HCLK_SDMMC 456
> #define HCLK_SDIO 457
> #define HCLK_EMMC 459
> +#define HCLK_CPU 460
> +#define HCLK_VPU_PRE 461
> +#define HCLK_RKVDEC_PRE 462
> +#define HCLK_VIO_PRE 463
> +#define HCLK_VPU 464
> +#define HCLK_RKVDEC 465
> +#define HCLK_VIO 466
> +#define HCLK_RGA 467
> +#define HCLK_IEP 468
> +#define HCLK_VIO_H2P 469
> +#define HCLK_HDCP_MMU 470
> +#define HCLK_HOST0 471
> +#define HCLK_HOST1 472
> +#define HCLK_HOST2 473
> +#define HCLK_OTG 474
> +#define HCLK_TSP 475
> +#define HCLK_M_CRYPTO 476
> +#define HCLK_S_CRYPTO 477
> #define HCLK_PERI 478
>
> #define CLK_NR_CLKS (HCLK_PERI + 1)
>
^ permalink raw reply
* [PATCH v8 1/4] syscalls: Verify address limit before returning to user-mode
From: Ingo Molnar @ 2017-04-28 6:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJcbSZENjCgn3TNDGzCBBSOXMvbTX8mBO7Trugdb5VRzhxwmHg@mail.gmail.com>
* Thomas Garnier <thgarnie@google.com> wrote:
> > BTW., a further simplification would be:
> >
> > #ifndef ADDR_LIMIT_CHECK_PRE
> > # define ADDR_LIMIT_CHECK_PRE ...
> > #endif
> >
> > This way architectures could override this generic functionality simply by
> > defining the helpers. Architectures that don't do that get the generic version.
>
> I don't think architectures need to do that. The optimizations are
> embedding the checks on their architecture-specific code to make it
> faster and remove the size impact. The pre/post is fine for the rest.
Indeed, only the generic code needs to turn off that code - architectures will
place these callbacks elsewhere.
Thanks,
Ingo
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox