* [PATCH 2/2] [PATCH 2/2] iio: adc: sun4i-gpadc-iio: Fix module autoload when OF devices are registered
From: Eduardo Molinas @ 2017-05-01 22:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170501224559.21028-1-edu.molinas@gmail.com>
If the driver is built as a module, it won't be autloaded if the devices
are registered via OF code because the OF device table
entries are not exported as aliases
Before the patch:
$ modinfo drivers/iio/adc/sun4i-gpadc-iio.ko | grep alias
alias: platform:sun6i-a31-gpadc-iio
alias: platform:sun5i-a13-gpadc-iio
alias: platform:sun4i-a10-gpadc-iio
After the patch:
$ modinfo drivers/iio/adc/sun4i-gpadc-iio.ko | grep alias
alias: of:N*T*Callwinner,sun8i-a33-thsC*
alias: of:N*T*Callwinner,sun8i-a33-ths
alias: platform:sun6i-a31-gpadc-iio
alias: platform:sun5i-a13-gpadc-iio
alias: platform:sun4i-a10-gpadc-iio
Signed-off-by: Eduardo Molinas <edu.molinas@gmail.com>
---
---
drivers/iio/adc/sun4i-gpadc-iio.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc-iio.c
index c3d7ba100a48..1c83b45043bf 100644
--- a/drivers/iio/adc/sun4i-gpadc-iio.c
+++ b/drivers/iio/adc/sun4i-gpadc-iio.c
@@ -712,6 +712,7 @@ static struct platform_driver sun4i_gpadc_driver = {
.probe = sun4i_gpadc_probe,
.remove = sun4i_gpadc_remove,
};
+MODULE_DEVICE_TABLE(of, sun4i_gpadc_of_id);
module_platform_driver(sun4i_gpadc_driver);
--
2.11.0
^ permalink raw reply related
* [PATCH 0/2] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
From: Casey Leedom @ 2017-05-01 23:13 UTC (permalink / raw)
To: linux-arm-kernel
Some devices have problems with Transaction Layer Packets with the Relaxed
Ordering Attribute set. This patch set adds a new PCIe Device Flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known
devices with Relaxed Ordering issues, and a use of this new flag by the
cxgb4 driver to avoid using Relaxed Ordering with problematic Root Complex
Ports.
It's been years since I've submitted kernel.org patches, I appolgise for the
almost certain submission errors.
Casey Leedom (2):
PCI: Add new PCIe Fabric End Node flag,
PCI_DEV_FLAGS_NO_RELAXED_ORDERING
net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 +++++++++++
drivers/net/ethernet/chelsio/cxgb4/sge.c | 5 ++--
drivers/pci/quirks.c | 38 +++++++++++++++++++++++++
include/linux/pci.h | 2 ++
5 files changed, 61 insertions(+), 2 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH 1/2] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING
From: Casey Leedom @ 2017-05-01 23:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1493678834.git.leedom@chelsio.com>
The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
Ordering Attribute should not be used on Transaction Layer Packets destined
for the PCIe End Node so flagged. Initially flagged this way are Intel
E5-26xx Root Complex Ports which suffer from a Flow Control Credit
Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
---
drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++
include/linux/pci.h | 2 ++
2 files changed, 40 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index f754453..4ae78b3 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3979,6 +3979,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev)
quirk_tw686x_class);
/*
+ * Some devices have problems with Transaction Layer Packets with the Relaxed
+ * Ordering Attribute set. Such devices should mark themselves and other
+ * Device Drivers should check before sending TLPs with RO set.
+ */
+static void quirk_relaxedordering_disable(struct pci_dev *dev)
+{
+ dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
+}
+
+/*
+ * Intel E5-26xx Root Complex has a Flow Control Credit issue which can
+ * cause performance problems with Upstream Transaction Layer Packets with
+ * Relaxed Ordering set.
+ */
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
+ quirk_relaxedordering_disable);
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
+ quirk_relaxedordering_disable);
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
+ quirk_relaxedordering_disable);
+
+/*
+ * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
+ * where Upstream Transaction Layer Packets with the Relaxed Ordering
+ * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
+ * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
+ * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
+ * November 10, 2010). As a result, on this platform we can't use Relaxed
+ * Ordering for Upstream TLPs.
+ */
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1022, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
+ quirk_relaxedordering_disable);
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1022, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
+ quirk_relaxedordering_disable);
+DECLARE_PCI_FIXUP_CLASS_EARLY(0x1022, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
+ quirk_relaxedordering_disable);
+
+/*
* Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
* values for the Attribute as were supplied in the header of the
* corresponding Request, except as explicitly allowed when IDO is used."
diff --git a/include/linux/pci.h b/include/linux/pci.h
index eb3da1a..6764f66 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -178,6 +178,8 @@ enum pci_dev_flags {
PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
/* Get VPD from function 0 VPD */
PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
+ /* Don't use Relaxed Ordering for TLPs directed@this device */
+ PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 9),
};
enum pci_irq_reroute_variant {
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
From: Casey Leedom @ 2017-05-01 23:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1493678834.git.leedom@chelsio.com>
cxgb4 Ethernet driver now queries Root Complex Port to determine if it can
send TLPs to it with the Relaxed Ordering Attribute set.
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 +++++++++++++++++
drivers/net/ethernet/chelsio/cxgb4/sge.c | 5 +++--
3 files changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
index 163543b..46d61b1 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4.h
@@ -512,6 +512,7 @@ enum { /* adapter flags */
USING_SOFT_PARAMS = (1 << 6),
MASTER_PF = (1 << 7),
FW_OFLD_CONN = (1 << 9),
+ ROOT_NO_RELAXED_ORDERING = (1 << 10),
};
enum {
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index afb0967..510c020 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -4636,6 +4636,7 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
#ifdef CONFIG_PCI_IOV
u32 v, port_vec;
#endif
+ struct pci_dev *root;
printk_once(KERN_INFO "%s - version %s\n", DRV_DESC, DRV_VERSION);
@@ -4734,6 +4735,22 @@ static int init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
adapter->msg_enable = DFLT_MSG_ENABLE;
memset(adapter->chan_map, 0xff, sizeof(adapter->chan_map));
+ /* If possible, we use PCIe Relaxed Ordering Attribute to deliver
+ * Ingress Packet Data to Free List Buffers in order to allow for
+ * chipset performance optimizations between the Root Complex and
+ * Memory Controllers. (Messages to the associated Ingress Queue
+ * notifying new Packet Placement in the Free Lists Buffers will be
+ * send without the Relaxed Ordering Attribute thus guaranteing that
+ * all preceding PCIe Transaction Layer Packets will be processed
+ * first.) But some Root Complexes have various issues with Upstream
+ * Transaction Layer Packets with the Relaxed Ordering Attribute set.
+ * So we check our Root Complex to see if it's flaged with advice
+ * against using Relaxed Ordering.
+ */
+ root = pci_find_pcie_root_port(adapter->pdev);
+ if (root && (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING))
+ adapter->flags |= ROOT_NO_RELAXED_ORDERING;
+
spin_lock_init(&adapter->stats_lock);
spin_lock_init(&adapter->tid_release_lock);
spin_lock_init(&adapter->win0_lock);
diff --git a/drivers/net/ethernet/chelsio/cxgb4/sge.c b/drivers/net/ethernet/chelsio/cxgb4/sge.c
index f05f0d4..ac229a3 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/sge.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/sge.c
@@ -2571,6 +2571,7 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
struct fw_iq_cmd c;
struct sge *s = &adap->sge;
struct port_info *pi = netdev_priv(dev);
+ int relaxed = !(adap->flags & ROOT_NO_RELAXED_ORDERING);
/* Size needs to be multiple of 16, including status entry. */
iq->size = roundup(iq->size, 16);
@@ -2624,8 +2625,8 @@ int t4_sge_alloc_rxq(struct adapter *adap, struct sge_rspq *iq, bool fwevtq,
flsz = fl->size / 8 + s->stat_len / sizeof(struct tx_desc);
c.iqns_to_fl0congen |= htonl(FW_IQ_CMD_FL0PACKEN_F |
- FW_IQ_CMD_FL0FETCHRO_F |
- FW_IQ_CMD_FL0DATARO_F |
+ FW_IQ_CMD_FL0FETCHRO_V(relaxed) |
+ FW_IQ_CMD_FL0DATARO_V(relaxed) |
FW_IQ_CMD_FL0PADEN_F);
if (cong >= 0)
c.iqns_to_fl0congen |=
--
1.9.1
^ permalink raw reply related
* [PATCH] mtd: nand: tango: Export OF device ID table as module aliases
From: Brian Norris @ 2017-05-01 23:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170501203015.7275-1-andresgalacho@gmail.com>
On Mon, May 01, 2017 at 04:30:15PM -0400, Andres Galacho wrote:
> The device table is required to load modules based on
> modaliases. After adding MODULE_DEVICE_TABLE, below entries
> for example will be added to module.alias:
> alias: of:N*T*Csigma,smp8758-nandC*
> alias: of:N*T*Csigma,smp8758-nand
>
> Signed-off-by: Andres Galacho <andresgalacho@gmail.com>
Acked-by: Brian Norris <computersforpeace@gmail.com>
^ permalink raw reply
* [PATCH 0/2] Add new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
From: Ding Tianhong @ 2017-05-02 0:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1493678834.git.leedom@chelsio.com>
Hi Casey:
This solution looks good to me, I will test this for ixgbe.:)
Thanks
Ding
On 2017/5/2 7:13, Casey Leedom wrote:
> Some devices have problems with Transaction Layer Packets with the Relaxed
> Ordering Attribute set. This patch set adds a new PCIe Device Flag,
> PCI_DEV_FLAGS_NO_RELAXED_ORDERING, a set of PCI Quirks to catch some known
> devices with Relaxed Ordering issues, and a use of this new flag by the
> cxgb4 driver to avoid using Relaxed Ordering with problematic Root Complex
> Ports.
>
> It's been years since I've submitted kernel.org patches, I appolgise for the
> almost certain submission errors.
>
> Casey Leedom (2):
> PCI: Add new PCIe Fabric End Node flag,
> PCI_DEV_FLAGS_NO_RELAXED_ORDERING
> net/cxgb4: Use new PCI_DEV_FLAGS_NO_RELAXED_ORDERING flag
>
> drivers/net/ethernet/chelsio/cxgb4/cxgb4.h | 1 +
> drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 17 +++++++++++
> drivers/net/ethernet/chelsio/cxgb4/sge.c | 5 ++--
> drivers/pci/quirks.c | 38 +++++++++++++++++++++++++
> include/linux/pci.h | 2 ++
> 5 files changed, 61 insertions(+), 2 deletions(-)
>
^ permalink raw reply
* [PATCH 2/2] [PATCH 2/2] iio: adc: sun4i-gpadc-iio: Fix module autoload when OF devices are registered
From: Chen-Yu Tsai @ 2017-05-02 2:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170501224559.21028-2-edu.molinas@gmail.com>
On Tue, May 2, 2017 at 6:45 AM, Eduardo Molinas <edu.molinas@gmail.com> wrote:
> If the driver is built as a module, it won't be autloaded if the devices
> are registered via OF code because the OF device table
> entries are not exported as aliases
>
> Before the patch:
> $ modinfo drivers/iio/adc/sun4i-gpadc-iio.ko | grep alias
> alias: platform:sun6i-a31-gpadc-iio
> alias: platform:sun5i-a13-gpadc-iio
> alias: platform:sun4i-a10-gpadc-iio
>
> After the patch:
> $ modinfo drivers/iio/adc/sun4i-gpadc-iio.ko | grep alias
> alias: of:N*T*Callwinner,sun8i-a33-thsC*
> alias: of:N*T*Callwinner,sun8i-a33-ths
> alias: platform:sun6i-a31-gpadc-iio
> alias: platform:sun5i-a13-gpadc-iio
> alias: platform:sun4i-a10-gpadc-iio
>
> Signed-off-by: Eduardo Molinas <edu.molinas@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Can we merge this as a fix for 4.12?
^ permalink raw reply
* [PATCH 1/2] [PATCH 1/2] iio: adc: sun4i-gpadc-iio: Fix module autoload when PLATFORM devices are registered
From: Chen-Yu Tsai @ 2017-05-02 2:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170501224559.21028-1-edu.molinas@gmail.com>
On Tue, May 2, 2017 at 6:45 AM, Eduardo Molinas <edu.molinas@gmail.com> wrote:
> If the driver is built as a module, it won't be autloaded if the devices
> are registered via PLATFORM code because the PLATFORM device table
> entries are not exported as aliases
>
> Before the patch:
> $ modinfo drivers/iio/adc/sun4i-gpadc-iio.ko | grep alias
> $
>
> After th patch:
^^ the
> $ modinfo drivers/iio/adc/sun4i-gpadc-iio.ko | grep alias
> alias: platform:sun6i-a31-gpadc-iio
> alias: platform:sun5i-a13-gpadc-iio
> alias: platform:sun4i-a10-gpadc-iio
>
> Signed-off-by: Eduardo Molinas <edu.molinas@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Can we merge this as a fix for 4.12?
^ permalink raw reply
* [v6,10/23] drivers/fsi: Add device read/write/peek API
From: Brad Bishop @ 2017-05-02 5:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170410194706.64280-11-cbostic@linux.vnet.ibm.com>
> On Apr 10, 2017, at 3:46 PM, Christopher Bostic <cbostic@linux.vnet.ibm.com> wrote:
>
> From: Jeremy Kerr <jk@ozlabs.org>
>
> This change introduces the fsi device API: simple read, write and peek
> accessors for the devices' address spaces.
>
> Includes contributions from Chris Bostic <cbostic@linux.vnet.ibm.com>
> and Edward A. James <eajames@us.ibm.com>.
>
> Signed-off-by: Edward A. James <eajames@us.ibm.com>
> Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
> Signed-off-by: Chris Bostic <cbostic@linux.vnet.ibm.com>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/fsi/fsi-core.c | 33 +++++++++++++++++++++++++++++++++
> include/linux/fsi.h | 7 ++++++-
> 2 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c
> index a8faa89..4da0b030 100644
> --- a/drivers/fsi/fsi-core.c
> +++ b/drivers/fsi/fsi-core.c
> @@ -32,6 +32,8 @@
> #define FSI_SLAVE_CONF_CRC_MASK 0x0000000f
> #define FSI_SLAVE_CONF_DATA_BITS 28
>
> +#define FSI_PEEK_BASE 0x410
> +
> static const int engine_page_size = 0x400;
>
> #define FSI_SLAVE_BASE 0x800
> @@ -73,9 +75,40 @@ static int fsi_master_read(struct fsi_master *master, int link,
> uint8_t slave_id, uint32_t addr, void *val, size_t size);
> static int fsi_master_write(struct fsi_master *master, int link,
> uint8_t slave_id, uint32_t addr, const void *val, size_t size);
> +static int fsi_slave_read(struct fsi_slave *slave, uint32_t addr,
> + void *val, size_t size);
> +static int fsi_slave_write(struct fsi_slave *slave, uint32_t addr,
> + const void *val, size_t size);
>
> /* FSI endpoint-device support */
>
> +int fsi_device_read(struct fsi_device *dev, uint32_t addr, void *val,
> + size_t size)
> +{
> + if (addr > dev->size || size > dev->size || addr > dev->size - size)
> + return -EINVAL;
> +
> + return fsi_slave_read(dev->slave, dev->addr + addr, val, size);
> +}
> +EXPORT_SYMBOL_GPL(fsi_device_read);
> +
> +int fsi_device_write(struct fsi_device *dev, uint32_t addr, const void *val,
> + size_t size)
> +{
> + if (addr > dev->size || size > dev->size || addr > dev->size - size)
> + return -EINVAL;
> +
> + return fsi_slave_write(dev->slave, dev->addr + addr, val, size);
> +}
> +EXPORT_SYMBOL_GPL(fsi_device_write);
> +
> +int fsi_device_peek(struct fsi_device *dev, void *val)
> +{
> + uint32_t addr = FSI_PEEK_BASE + ((dev->unit - 2) * sizeof(uint32_t));
> +
> + return fsi_slave_read(dev->slave, addr, val, sizeof(uint32_t));
> +}
> +
> static void fsi_device_release(struct device *_device)
> {
> struct fsi_device *device = to_fsi_dev(_device);
> diff --git a/include/linux/fsi.h b/include/linux/fsi.h
> index efa55ba..66bce48 100644
> --- a/include/linux/fsi.h
> +++ b/include/linux/fsi.h
> @@ -27,6 +27,12 @@ struct fsi_device {
> uint32_t size;
> };
>
> +extern int fsi_device_read(struct fsi_device *dev, uint32_t addr,
> + void *val, size_t size);
> +extern int fsi_device_write(struct fsi_device *dev, uint32_t addr,
> + const void *val, size_t size);
> +extern int fsi_device_peek(struct fsi_device *dev, void *val);
> +
> struct fsi_device_id {
> u8 engine_type;
> u8 version;
> @@ -40,7 +46,6 @@ struct fsi_device_id {
> #define FSI_DEVICE_VERSIONED(t, v) \
> .engine_type = (t), .version = (v),
>
> -
> struct fsi_driver {
> struct device_driver drv;
> const struct fsi_device_id *id_table;
I wrote a driver using this API. It seems to be suitable enough.
Acked-by: Brad Bishop <bradleyb@fuzziesquirrel.com>
^ permalink raw reply
* [PATCH v4 3/3] USB3/DWC3: Enable undefined length INCR burst type
From: Jerry Huang @ 2017-05-02 6:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87tw71xthj.fsf@linux.intel.com>
> -----Original Message-----
> From: Felipe Balbi [mailto:balbi at kernel.org]
> Sent: Friday, March 10, 2017 7:27 PM
> To: Jerry Huang <jerry.huang@nxp.com>; robh+dt at kernel.org;
> mark.rutland at arm.com; catalin.marinas at arm.com
> Cc: linux-usb at vger.kernel.org; linux-kernel at vger.kernel.org;
> devicetree at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Rajesh
> Bhagat <rajesh.bhagat@nxp.com>
> Subject: RE: [PATCH v4 3/3] USB3/DWC3: Enable undefined length INCR burst
> type
>
>
> Hi,
>
> Jerry Huang <jerry.huang@nxp.com> writes:
> >> >> --
> >> >> 1.7.9.5
> >> > Hi, Balbi and all guys,
> >> > Any comment for these patches? Can they be accepted?
> >>
> >> Rob had comments which you didn't reply yet. I cannot take this
> >> patchset yet ;-)
> >>
> > Balbi,
> >
> > I look into his mail again, which was based v3, and I replied it.
> >
> > He had different understanding for undefined length burst mode.
> >
> > It seems he think for this mode, just setting bit[0] (INCRBrstEna) and
> > don't need to set other field.
> >
> > However, according to the DWC USB3.0 controller databook, when it is
> > undefined length INCR burst mode, we still need to set one max burst
> > type, such as INCR8, which means controller will use any length less
> > than or equal to this INCR8.
>
> Rob, do you agree with the patch now?
>
> --
> balbi
Hi, Balbi,
Any comment for these patches? Or any chance to merge them?
^ permalink raw reply
* [PATCH v6 07/23] drivers/fsi: Implement slave initialisation
From: Joel Stanley @ 2017-05-02 6:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170410194706.64280-8-cbostic@linux.vnet.ibm.com>
On Tue, Apr 11, 2017 at 5:16 AM, Christopher Bostic
<cbostic@linux.vnet.ibm.com> wrote:
> From: Jeremy Kerr <jk@ozlabs.org>
>
> Implement fsi_slave_init: if we can read a chip ID, create fsi_slave
> devices and register with the driver core.
>
> Includes changes from Chris Bostic <cbostic@linux.vnet.ibm.com>.
>
> Signed-off-by: Jeremy Kerr <jk@ozlabs.org>
> Signed-off-by: Chris Bostic <cbostic@linux.vnet.ibm.com>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
> drivers/fsi/fsi-core.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 64 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/fsi/fsi-core.c b/drivers/fsi/fsi-core.c
> index 6e1cfdf..c705ca2 100644
> --- a/drivers/fsi/fsi-core.c
> +++ b/drivers/fsi/fsi-core.c
> @@ -17,9 +17,12 @@
> #include <linux/fsi.h>
> #include <linux/idr.h>
> #include <linux/module.h>
> +#include <linux/slab.h>
>
> #include "fsi-master.h"
>
> +#define FSI_SLAVE_SIZE_23b 0x800000
> +
> static DEFINE_IDA(master_ida);
>
> struct fsi_slave {
> @@ -114,11 +117,70 @@ static int fsi_slave_write(struct fsi_slave *slave, uint32_t addr,
> addr, val, size);
> }
>
> +static void fsi_slave_release(struct device *dev)
> +{
> + struct fsi_slave *slave = to_fsi_slave(dev);
> +
> + kfree(slave);
> +}
> +
> static int fsi_slave_init(struct fsi_master *master, int link, uint8_t id)
> {
> - /* todo: initialise slave device, perform engine scan */
> + struct fsi_slave *slave;
> + uint32_t chip_id;
> + uint8_t crc;
> + int rc;
> +
> + /* Currently, we only support single slaves on a link, and use the
> + * full 23-bit address range
> + */
> + if (id != 0)
> + return -EINVAL;
> +
> + rc = fsi_master_read(master, link, id, 0, &chip_id, sizeof(chip_id));
> + if (rc) {
> + dev_warn(&master->dev, "can't read slave %02x:%02x %d\n",
> + link, id, rc);
When I boot a system with this driver loaded, I get his warning:
[ 9.740000] usbhid: USB HID core driver
[ 9.840000] fsi0: can't read slave 00:00 -5
[ 9.840000] NET: Registered protocol family 10
Two things:
There's a space in front of "fsi0".
This warning isn't useful at that point. The slave is not readable as
the FSI master is not present (the P9 hasn't been turned on). Can we
avoid printing the warning at boot?
Cheers,
Joel
> + return -ENODEV;
> + }
> + chip_id = be32_to_cpu(chip_id);
> +
> + crc = fsi_crc4(0, chip_id, 32);
> + if (crc) {
> + dev_warn(&master->dev, "slave %02x:%02x invalid chip id CRC!\n",
> + link, id);
> + return -EIO;
> + }
> +
> + dev_info(&master->dev, "fsi: found chip %08x at %02x:%02x:%02x\n",
> + chip_id, master->idx, link, id);
> +
> + /* We can communicate with a slave; create the slave device and
> + * register.
> + */
> + slave = kzalloc(sizeof(*slave), GFP_KERNEL);
> + if (!slave)
> + return -ENOMEM;
> +
> + slave->master = master;
> + slave->dev.parent = &master->dev;
> + slave->dev.release = fsi_slave_release;
> + slave->link = link;
> + slave->id = id;
> + slave->size = FSI_SLAVE_SIZE_23b;
> +
> + dev_set_name(&slave->dev, "slave@%02x:%02x", link, id);
> + rc = device_register(&slave->dev);
> + if (rc < 0) {
> + dev_warn(&master->dev, "failed to create slave device: %d\n",
> + rc);
> + put_device(&slave->dev);
> + return rc;
> + }
> +
> + /* todo: perform engine scan */
>
> - return -ENODEV;
> + return rc;
> }
>
> /* FSI master support */
> --
> 1.8.2.2
>
^ permalink raw reply
* [PATCH 2/3] iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
From: Geetha Akula @ 2017-05-02 6:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170427170030.GF1890@arm.com>
Hi Will,
SMMU_IIDR register is broken on T99, that the reason we are using MIDR.
If using MIDR is not accepted, can we enable errata based on SMMU resource size?
some thing like below.
static bool page0_reg_only = false;
+static unsigned long arm_smmu_resource_size(void)
+{
+ if (page0_reg_only)
+ return SZ_64K;
+ else
+ return SZ_128K;
+}
+
static int arm_smmu_device_probe(struct platform_device *pdev)
{
int irq, ret;
@@ -2674,7 +2692,13 @@ static int arm_smmu_device_probe(struct
platform_device *pdev)
/* Base address */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ /*
+ * Setting page0_reg_only flag, for Cavium CN99xx implementations
+ * which doesn't support the page 1 SMMU register space.
+ */
+ if (resource_size(res) == SZ_64K)
+ page0_reg_only = true;
- if (resource_size(res) + 1 < SZ_128K) {
+ if (resource_size(res) + 1 < arm_smmu_resource_size()) {
dev_err(dev, "MMIO region too small (%pr)\n", res);
return -EINVAL;
}
Thank you,
Geetha.
On Thu, Apr 27, 2017 at 10:30 PM, Will Deacon <will.deacon@arm.com> wrote:
> On Thu, Apr 27, 2017 at 05:42:37PM +0100, Mark Rutland wrote:
>> On Thu, Apr 27, 2017 at 05:16:23PM +0530, Geetha sowjanya wrote:
>> > + /*
>> > + * Override the size, for Cavium CN99xx implementations
>> > + * which doesn't support the page 1 SMMU register space.
>> > + */
>> > + cpu_model = read_cpuid_id() & MIDR_CPU_MODEL_MASK;
>> > + if (cpu_model == MIDR_THUNDERX_99XX ||
>> > + cpu_model == MIDR_BRCM_VULCAN)
>> > + size = SZ_64K;
>>
>> If you're trying to identify an SMMU erratum, identify the SMMU, not the
>> CPU it happens to be paired with this time.
>>
>> There are ID registers in the SMMU you can use to do so.
>>
>> NAK to using the CPU ID here.
>
> Agreed. I had some off-list discussion with Geetha where we agreed to use
> the "silicon ID", which I assumed was the SMMU IIDR register.
>
> Will
^ permalink raw reply
* [BUG] crash when removing sun4i_gpadc_iio module
From: Corentin Labbe @ 2017-05-02 6:46 UTC (permalink / raw)
To: linux-arm-kernel
Hello
When inserting sun4i_gpadc_iio I got the following error in dmesg:
[79961.039826] thermal thermal_zone0: failed to read out thermal zone (-110)
Then removing the module cause an oops:
[80105.370937] Unable to handle kernel paging request at virtual address bf0ad1d0
[80105.370958] pgd = c0004000
[80105.370968] [bf0ad1d0] *pgd=6e470811, *pte=00000000, *ppte=00000000
[80105.371009] Internal error: Oops: 80000007 [#1] PREEMPT SMP ARM
[80105.376940] Modules linked in: algif_aead ccm gcm algif_rng crypto_user algif_skcipher algif_hash af_alg ghash_generic aes_arm_bs axp20x_ac_power axp20x_usb_power axp20x_adc gpio_axp209 nvmem_sunxi_sid sun4i_ss sun4i_dma virt_dma [last unloaded: sun4i_gpadc_iio]
[80105.400199] CPU: 0 PID: 14663 Comm: kworker/0:0 Tainted: G W 4.11.0-rc8-next-20170428+ #96
[80105.409581] Hardware name: Allwinner sun7i (A20) Family
[80105.414821] Workqueue: events_freezable thermal_zone_device_check
[80105.420915] task: ee7d2880 task.stack: ea4fa000
[80105.425447] PC is at 0xbf0ad1d0
[80105.428594] LR is at arch_timer_read_counter_long+0x14/0x18
[80105.434166] pc : [<bf0ad1d0>] lr : [<c010eab8>] psr: 60070013
sp : ea4fbea8 ip : ee7d2e00 fp : 00000001
[80105.445630] r10: ea4fbed4 r9 : 0000007b r8 : 00000000
[80105.450852] r7 : ee7ffc14 r6 : ee7ff800 r5 : c09e2260 r4 : 0000005a
[80105.457373] r3 : c058e3d4 r2 : fac81000 r1 : 000001bf r0 : 00005dbf
[80105.463897] Flags: nZCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
[80105.471025] Control: 10c5387d Table: 66c9c06a DAC: 00000051
[80105.476766] Process kworker/0:0 (pid: 14663, stack limit = 0xea4fa210)
[80105.483288] Stack: (0xea4fbea8 to 0xea4fc000)
[80105.487648] bea0: 00000001 00000010 ee7ffbc0 ea4fbefc ef26dad4 ef7c2500
[80105.495821] bec0: ea4fbf28 00000000 00000000 bf0ad7e0 00000001 c070e80c c055d600 ef26d800
[80105.503994] bee0: ea4fbefc c055d614 00000000 ef26d800 ef7bef00 c055b040 ea4fbf28 ef26db20
[80105.512167] bf00: ef26db20 edf65680 ef7bef00 c013b374 00000001 00000000 c013b304 c013b798
[80105.520340] bf20: 00000000 00000000 c12624a4 c0dcdf20 00000000 c09c0e10 c0c04900 ef7bef00
[80105.528512] bf40: edf65698 00000008 c0c04900 ef7bef34 ea4fa000 ef7bef00 edf65680 c013b6f8
[80105.536685] bf60: ef7bf09c 00000000 edf65680 edf65380 00000000 e6c90700 edf65680 c013b6c0
[80105.544858] bf80: edf653b8 edf91e84 00000000 c01415c0 e6c90700 c0141484 00000000 00000000
[80105.553030] bfa0: 00000000 00000000 00000000 c01079b8 00000000 00000000 00000000 00000000
[80105.561202] bfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[80105.569374] bfe0: 00000000 00000000 00000000 00000000 00000013 00000000 6fffd861 6fffdc61
[80105.577558] [<c010eab8>] (arch_timer_read_counter_long) from [<00000010>] (0x10)
[80105.584952] Code: bad PC value
[80105.588283] ---[ end trace ff84d9d449c6a5b5 ]---
Regards
Corentin Labbe
^ permalink raw reply
* [PATCH 1/2] PCI: Add new PCIe Fabric End Node flag, PCI_DEV_FLAGS_NO_RELAXED_ORDERING
From: Ding Tianhong @ 2017-05-02 6:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <758d0e431c732fe133e7b0e660bde5fc1beccdba.1493678834.git.leedom@chelsio.com>
hi, Casey:
On 2017/5/2 7:13, Casey Leedom wrote:
> The new flag PCI_DEV_FLAGS_NO_RELAXED_ORDERING indicates that the Relaxed
> Ordering Attribute should not be used on Transaction Layer Packets destined
> for the PCIe End Node so flagged. Initially flagged this way are Intel
> E5-26xx Root Complex Ports which suffer from a Flow Control Credit
> Performance Problem and AMD A1100 ARM ("SEATTLE") Root Complex Ports which
> don't obey PCIe 3.0 ordering rules which can lead to Data Corruption.
> ---
> drivers/pci/quirks.c | 38 ++++++++++++++++++++++++++++++++++++++
> include/linux/pci.h | 2 ++
> 2 files changed, 40 insertions(+)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index f754453..4ae78b3 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -3979,6 +3979,44 @@ static void quirk_tw686x_class(struct pci_dev *pdev)
> quirk_tw686x_class);
>
> /*
> + * Some devices have problems with Transaction Layer Packets with the Relaxed
> + * Ordering Attribute set. Such devices should mark themselves and other
> + * Device Drivers should check before sending TLPs with RO set.
> + */
> +static void quirk_relaxedordering_disable(struct pci_dev *dev)
> +{
> + dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
> +}
> +
> +/*
> + * Intel E5-26xx Root Complex has a Flow Control Credit issue which can
> + * cause performance problems with Upstream Transaction Layer Packets with
> + * Relaxed Ordering set.
> + */
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
> + quirk_relaxedordering_disable);
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
> + quirk_relaxedordering_disable);
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x8086, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
> + quirk_relaxedordering_disable);
> +
> +/*
> + * The AMD ARM A1100 (AKA "SEATTLE") SoC has a bug in its PCIe Root Complex
> + * where Upstream Transaction Layer Packets with the Relaxed Ordering
> + * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering
> + * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules
> + * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0
> + * November 10, 2010). As a result, on this platform we can't use Relaxed
> + * Ordering for Upstream TLPs.
> + */
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x1022, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
> + quirk_relaxedordering_disable);
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x1022, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
> + quirk_relaxedordering_disable);
> +DECLARE_PCI_FIXUP_CLASS_EARLY(0x1022, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
> + quirk_relaxedordering_disable);
> +
> +/*
> * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
> * values for the Attribute as were supplied in the header of the
> * corresponding Request, except as explicitly allowed when IDO is used."
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index eb3da1a..6764f66 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -178,6 +178,8 @@ enum pci_dev_flags {
> PCI_DEV_FLAGS_NO_PM_RESET = (__force pci_dev_flags_t) (1 << 7),
> /* Get VPD from function 0 VPD */
> PCI_DEV_FLAGS_VPD_REF_F0 = (__force pci_dev_flags_t) (1 << 8),
> + /* Don't use Relaxed Ordering for TLPs directed at this device */
> + PCI_DEV_FLAGS_NO_RELAXED_ORDERING = (__force pci_dev_flags_t) (1 << 9),
> };
What about add a new general func to check the RO for several drivers to use them ?
just like:
#define pci_dev_support_relaxed_ordering(struct pci_dev *root) \
(!(root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING))
Thanks
Ding
>
> enum pci_irq_reroute_variant {
>
^ permalink raw reply
* [PATCH v1 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe
From: Ryder Lee @ 2017-05-02 7:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170428210924.y6xdv4trqbmyn5me@rob-hp-laptop>
On Fri, 2017-04-28 at 16:09 -0500, Rob Herring wrote:
> On Fri, Apr 28, 2017 at 05:10:34PM +0800, Ryder Lee wrote:
> > Add binding document for Mediatek PCIe Gen2 v1 host controller driver.
> >
> > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> > ---
> > .../bindings/pci/mediatek,gen2v1-pcie.txt | 174 +++++++++++++++++++++
> > 1 file changed, 174 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> >
> > diff --git a/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > new file mode 100644
> > index 0000000..545d8cf
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/pci/mediatek,gen2v1-pcie.txt
> > @@ -0,0 +1,174 @@
> > +Mediatek Gen2 V1 PCIe controller
> > +
> > +PCIe subsys supports single root complex (RC) with 3 Root Ports. Each root
> > +ports supports a Gen2 1-lane Link. It includes one Host/PCI bridge and 3
> > +PCIe MAC. Each port has PIPE interface to PHY. There are 3 bus master for
> > +data access and 1 bus slave for Configuration and Status Register access.
> > +
> > +This controller is available on MT7623 series SoCs.
> > +
> > +Required properties:
> > +- compatible: Should contain "mediatek,gen2v1-pcie".
> > +- device_type: Must be "pci"
> > +- reg: Base addresses and lengths of the PCIe controller.
> > +- #address-cells: Address representation for root ports (must be 3)
> > + - cell 0 specifies the bus and device numbers of the root port:
> > + [23:16]: bus number
> > + [15:11]: device number
> > + - cell 1 denotes the upper 32 address bits and should be 0
> > + - cell 2 contains the lower 32 address bits and is used to translate to the
> > + CPU address space
>
> This is all standard PCI bus binding. You don't need to define it here.
> "must be 3" is sufficient.
Okay.
> > +- #size-cells: Size representation for root ports (must be 2)
> > +- #interrupt-cells: Size representation for interrupts (must be 1)
> > +- interrupts: Three interrupt outputs of the controller. Must contain an
> > + entry for each entry in the interrupt-names property.
>
> Where's interrupt-names?
I will add it.
> > +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> > + Please refer to the standard PCI bus binding document for a more detailed
> > + explanation.
> > +- clocks: Must contain an entry for each entry in clock-names.
> > + See ../clocks/clock-bindings.txt for details.
> > +- clock-names: Must include the following entries:
> > + - free_ck :for reference clock of PCIe subsys
> > + - sys_ck0 :for clock of Port0 MAC
> > + - sys_ck1 :for clock of Port1 MAC
> > + - sys_ck2 :for clock of Port2 MAC
> > +- resets: Must contain an entry for each entry in reset-names.
> > + See ../reset/reset.txt for details.
> > +- reset-names: Must include the following entries:
> > + - pcie-rst0 :port0 reset
> > + - pcie-rst1 :port1 reset
> > + - pcie-rst2 :port2 reset
> > +- phys: list of PHY specifiers (used by generic PHY framework)
> > +- phy-names : must be "pcie-phy0", "pcie-phy1", "pcie-phyN".. based on the
> > + number of PHYs as specified in *phys* property.
> > +- power-domains: A phandle and power domain specifier pair to the power domain
> > + which is responsible for collapsing and restoring power to the peripheral
> > +- bus-range: Range of bus numbers associated with this controller
> > +- ranges: Describes the translation of addresses for root ports and standard
> > + PCI regions. The entries must be 6 cells each, where the first three cells
> > + correspond to the address as described for the #address-cells property
> > + above, the fourth cell is the physical CPU address to translate to and the
> > + fifth and six cells are as described for the #size-cells property above.
>
> Don't need to define what ranges is here, just what the entries should
> be:
Okay.
> > + - The first three entries are expected to translate the addresses for the root
> > + port registers, which are referenced by the assigned-addresses property of
> > + the root port nodes (see below).
> > + - The remaining entries setup the mapping for the standard I/O and memory
> > + regions.
> > + Please refer to the standard PCI bus binding document for a more detailed
> > + explanation.
> > +
> > +In addition, the device tree node must have sub-nodes describing each
> > +PCIe port interface, having the following mandatory properties:
> > +
> > +Required properties:
> > +- device_type: Must be "pci"
> > +- assigned-addresses: Address and size of the port configuration registers
> > +- reg: Only the first four bytes are used to refer to the correct bus number
> > + and device number.
> > +- #address-cells: Must be 3
> > +- #size-cells: Must be 2
> > +- #interrupt-cells: Size representation for interrupts (must be 1)
> > +- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties
> > + Please refer to the standard PCI bus binding document for a more detailed
> > + explanation.
> > +- ranges: Sub-ranges distributed from the PCIe controller node. An empty
> > + property is sufficient.
> > +- num-lanes: Number of lanes to use for this port.
> > +
> > +Examples:
> > +
> > +SoC dtsi:
>
> Don't show the board vs. SoC split in examples. And drop all the status
> properties.
Okay i will drop it all.
> > +
> > + hifsys: syscon at 1a000000 {
> > + compatible = "mediatek,mt7623-hifsys", "syscon";
> > + reg = <0 0x1a000000 0 0x1000>;
> > + #clock-cells = <1>;
> > + #reset-cells = <1>;
> > + };
> > +
> > + pcie: pcie-controller at 1a140000 {
> > + compatible = "mediatek,gen2v1-pcie";
> > + device_type = "pci";
> > + reg = <0 0x1a140000 0 0x1000>; /* PCIe shared registers */
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
> > + <GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-map-mask = <0xf800 0 0 0>;
> > + interrupt-map = <0x0000 0 0 0 &gic GIC_SPI 193 IRQ_TYPE_NONE>,
> > + <0x0800 0 0 0 &gic GIC_SPI 194 IRQ_TYPE_NONE>,
> > + <0x1000 0 0 0 &gic GIC_SPI 195 IRQ_TYPE_NONE>;
> > + clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
> > + <&hifsys CLK_HIFSYS_PCIE0>,
> > + <&hifsys CLK_HIFSYS_PCIE1>,
> > + <&hifsys CLK_HIFSYS_PCIE2>;
> > + clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
> > + resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
> > + <&hifsys MT2701_HIFSYS_PCIE1_RST>,
> > + <&hifsys MT2701_HIFSYS_PCIE2_RST>;
> > + reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
> > + phys = <&pcie0_phy>, <&pcie1_phy>, <&pcie2_phy>;
> > + phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
> > + power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
> > + bus-range = <0x00 0xff>;
> > + ranges = <0x82000000 0 0x1a142000 0 0x1a142000 0 0x1000 /* Port0 registers */
> > + 0x82000000 0 0x1a143000 0 0x1a143000 0 0x1000 /* Port1 registers */
> > + 0x82000000 0 0x1a144000 0 0x1a144000 0 0x1000 /* Port2 registers */
> > + 0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000 /* I/O space */
> > + 0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */
> > + status = "disabled";
> > +
> > + pcie at 1,0 {
> > + device_type = "pci";
> > + assigned-addresses = <0x82000000 0 0x1a142000 0 0x1000>;
> > + reg = <0x0000 0 0 0 0>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0>;
> > + interrupt-map = <0 0 0 0 &gic GIC_SPI 193 IRQ_TYPE_NONE>;
> > + ranges;
> > + num-lanes = <1>;
> > + status = "disabled";
> > + };
> > +
> > + pcie at 2,0 {
> > + device_type = "pci";
> > + assigned-addresses = <0x82000800 0 0x1a143000 0 0x1000>;
> > + reg = <0x0800 0 0 0 0>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0>;
> > + interrupt-map = <0 0 0 0 &gic GIC_SPI 194 IRQ_TYPE_NONE>;
> > + ranges;
> > + num-lanes = <1>;
> > + status = "disabled";
> > + };
> > +
> > + pcie at 3,0 {
> > + device_type = "pci";
> > + assigned-addresses = <0x82001000 0 0x1a144000 0 0x1000>;
> > + reg = <0x1000 0 0 0 0>;
> > + #address-cells = <3>;
> > + #size-cells = <2>;
> > + #interrupt-cells = <1>;
> > + interrupt-map-mask = <0 0 0 0>;
> > + interrupt-map = <0 0 0 0 &gic GIC_SPI 195 IRQ_TYPE_NONE>;
> > + ranges;
> > + num-lanes = <1>;
> > + status = "disabled";
> > + };
> > + };
> > +
> > +Board dts:
> > +
> > + &pcie {
> > + status = "okay";
> > +
> > + pcie at 1,0 {
> > + status = "okay";
> > + };
> > + };
> > --
> > 1.9.1
Thanks for your review.
^ permalink raw reply
* [PATCH 2/2] dt-bindings: phy: Add documentation for Mediatek PCIe PHY
From: Ryder Lee @ 2017-05-02 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170428175200.laakck7ill2lxtxc@rob-hp-laptop>
On Fri, 2017-04-28 at 12:52 -0500, Rob Herring wrote:
> On Sun, Apr 23, 2017 at 04:17:33PM +0800, Ryder Lee wrote:
> > Add documentation for PCIe PHY available in MT7623 series SoCs.
> >
> > Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> > ---
> > .../devicetree/bindings/phy/phy-mt7623-pcie.txt | 67 ++++++++++++++++++++++
> > 1 file changed, 67 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt
> >
> > diff --git a/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt
> > new file mode 100644
> > index 0000000..27a9253
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/phy/phy-mt7623-pcie.txt
> > @@ -0,0 +1,67 @@
> > +Mediatek MT7623 PCIe PHY
> > +-----------------------
> > +
> > +Required properties:
> > + - compatible: Should contain "mediatek,mt7623-pcie-phy"
> > + - #phy-cells: must be 0
> > + - clocks: Must contain an entry in clock-names.
> > + See ../clocks/clock-bindings.txt for details.
> > + - clock-names: Must be "refclk"
> > + - resets: Must contain an entry in reset-names.
> > + See ../reset/reset.txt for details.
> > + - reset-names: Must be "phy"
> > +
> > +Optional properties:
> > + - phy-switch: The PHY on PCIe port2 is shared with USB u3phy2. If you
> > + want to enable port2, you should contain it.
>
> Need to state what the value is (i.e. a phandle to ?). Also needs a
> vendor prefix.
I will correct it.
> > +
> > +Example:
> > +
> > + pcie0_phy: pciephy at 1a149000 {
>
> pcie-phy at ...
Okay.
> > + compatible = "mediatek,mt7623-pcie-phy";
> > + reg = <0 0x1a149000 0 0x1000>;
> > + clocks = <&clk26m>;
> > + clock-names = "pciephya_ref";
> > + #phy-cells = <0>;
> > + status = "disabled";
>
> Don't show status in examples.
I will drop it all.
> > + };
> > +
> > + pcie1_phy: pciephy at 1a14a000 {
> > + compatible = "mediatek,mt7623-pcie-phy";
> > + reg = <0 0x1a14a000 0 0x1000>;
> > + clocks = <&clk26m>;
> > + clock-names = "pciephya_ref";
> > + #phy-cells = <0>;
> > + status = "disabled";
> > + };
> > +
> > + pcie2_phy: pciephy at 1a244000 {
> > + compatible = "mediatek,mt7623-pcie-phy";
> > + reg = <0 0x1a244000 0 0x1000>;
> > + clocks = <&clk26m>;
> > + clock-names = "pciephya_ref";
> > + #phy-cells = <0>;
> > +
> > + phy-switch = <&hifsys>;
> > + status = "disabled";
> > + };
> > +
> > +Specifying phy control of devices
> > +---------------------------------
> > +
> > +Device nodes should specify the configuration required in their "phys"
> > +property, containing a phandle to the phy node and phy-names.
> > +
> > +Example:
> > +
> > +#include <dt-bindings/phy/phy.h>
> > +
> > +pcie: pcie at 1a140000 {
> > + ...
> > + pcie at 1,0 {
> > + ...
> > + phys = <&pcie0_phy>;
> > + phy-names = "pcie-phy0";
> > + }
> > + ...
> > +};
Thanks for your reviews.
> > --
> > 1.9.1
> >
^ permalink raw reply
* FW: [PATCH 2/2] dt-bindings: pcie: Add documentation for Mediatek PCIe
From: Ryder Lee @ 2017-05-02 7:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4BAFE512E7223A4B91F29C40AC7A579616B5155E@MTKMBS05N1.mediatek.inc>
Hi Arnd,
> 2017-04-28 19:41 GMT+08:00 Arnd Bergmann <arnd@arndb.de>:
>
> On Fri, Apr 28, 2017 at 4:46 AM, Ryder Lee
> <ryder.lee@mediatek.com> wrote:
> > On Thu, 2017-04-27 at 21:06 +0200, Arnd Bergmann wrote:
> >> On Wed, Apr 26, 2017 at 10:10 AM, Ryder Lee
> <ryder.lee@mediatek.com> wrote:
> >> > On Tue, 2017-04-25 at 14:18 +0200, Arnd Bergmann wrote:
> >> >> On Sun, Apr 23, 2017 at 10:19 AM, Ryder Lee
> <ryder.lee@mediatek.com> wrote:
> >> Are any of the registers the same at all, e.g. for MSI
> handling?
> >
> > No, It doesn't support MSI. All I can do is using the
> registers that designer provide to me. The others are inviable
> for software. So I treat it as different hardware.
> Furthermore, we hope that we can put all mediatek drivers
> together regardless of in-house IP or lincense IP
> >
> > We have no particular IP name but just use chip name to call
> it. So I will temporarily use "mediatek,gen2v1-pcie" in patch
> v1.
>
> I think using the chip name as in the first version of your
> patch name is better then, in particular since the 'gen2v1'
> would not be an actual version number but just say which
> variant got merged into mainline first.
Okay, i will correct it.
> A related question would be on how general we want the binding
> to be.
> Your binding text starts out by describing that there are
> three root ports and what their capabilities are.
>
> If you think there might be other (existing or future) chips
> that use the same binding and driver, then being a little more
> abstract could help in the long run.
Thanks for reminding me. If we decide to use the same driver in the
future, we will have a internal discussion about it.
Ryder.
^ permalink raw reply
* [PATCH] irqchip/armada-370-xp: Enable MSI-X support
From: Stefan Roese @ 2017-05-02 7:26 UTC (permalink / raw)
To: linux-arm-kernel
Armada XP does not only support MSI, but also MSI-X. This patch sets
the MSI_FLAG_PCI_MSIX flag in the interrupt controller driver which
is the only change necessary to enable MSI-X support on this SoC. As
the Linux PCI MSI-X infrastructure takes care of writing the data and
address structures into the BAR specified by the MSI-X controller.
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>
Cc: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Gregory CLEMENT <gregory.clement@free-electrons.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
---
drivers/irqchip/irq-armada-370-xp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 33982cbd8a57..b17039ed8735 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -124,7 +124,7 @@ static struct irq_chip armada_370_xp_msi_irq_chip = {
static struct msi_domain_info armada_370_xp_msi_domain_info = {
.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
- MSI_FLAG_MULTI_PCI_MSI),
+ MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_PCI_MSIX),
.chip = &armada_370_xp_msi_irq_chip,
};
--
2.12.2
^ permalink raw reply related
* [PATCH] arm64: KVM: Fix decoding of Rt/Rt2 when trapping AArch32 CP accesses
From: Christoffer Dall @ 2017-05-02 7:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170427180648.25159-1-marc.zyngier@arm.com>
On Thu, Apr 27, 2017 at 07:06:48PM +0100, Marc Zyngier wrote:
> Our 32bit CP14/15 handling inherited some of the ARMv7 code for handling
> the trapped system registers, completely missing the fact that the
> fields for Rt and Rt2 are now 5 bit wide, and not 4...
>
> Let's fix it, and provide an accessor for the most common Rt case.
>
> Cc: stable at vger.kernel.org
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Aplied to kvmarm/queue.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH v3 0/4] make some special clk as critical_clocks
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: linux-arm-kernel
change in V3:
reword the commit message,explain why the specific clocks are need to be critical.
change in v2:
fix up some clks which have their own driver, not need to set as critical clocks
Elaine Zhang (4):
clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock
clk: rockchip: rk3228: make noc and some special clk as
critical_clocks
clk: rockchip: rk3288: make noc and some special clk as
critical_clocks
clk: rockchip: rk3368: make some special clk as critical_clocks
drivers/clk/rockchip/clk-rk3036.c | 1 +
drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
drivers/clk/rockchip/clk-rk3288.c | 14 ++++++++++----
drivers/clk/rockchip/clk-rk3368.c | 5 ++++-
4 files changed, 44 insertions(+), 6 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH v3 1/4] clk: rockchip: rk3036: make pclk_ddrupctl as critical_clock
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493710446-7203-1-git-send-email-zhangqing@rock-chips.com>
No driver to handle this clk, Chip design requirements for this clock to always on,
The new document will update the description of this clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3036.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/rockchip/clk-rk3036.c b/drivers/clk/rockchip/clk-rk3036.c
index 924f560dcf80..e97bee585b2f 100644
--- a/drivers/clk/rockchip/clk-rk3036.c
+++ b/drivers/clk/rockchip/clk-rk3036.c
@@ -436,6 +436,7 @@ enum rk3036_plls {
"aclk_peri",
"hclk_peri",
"pclk_peri",
+ "pclk_ddrupctl",
};
static void __init rk3036_clk_init(struct device_node *np)
--
1.9.1
^ permalink raw reply related
* [PATCH v3 2/4] clk: rockchip: rk3228: make noc and some special clk as critical_clocks
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493710446-7203-1-git-send-email-zhangqing@rock-chips.com>
The jtag\bus\peri\initmem\rom\stimer\phy clks no driver to handle them.
But this clks need enable,so make it as critical.
The ddrupctl\ddrmon\ddrphy clks no driver to handle them,
Chip design requirements for these clock to always on,
The new document will update the description of these clock.
The hclk_otg_pmu is Chip design defect, must be always on,
The new document will update the description of this clock.
All these non-noc\non-arbi clocks,IC suggest always on,
Because it's have some order limitation, between the NOC clock switch and bus IDLE(or pd on/off).
The software is not very good to slove this constraint.
Always on these clocks, has no effect on the system power consumption.
The new document will update the description of these clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3228.c | 30 +++++++++++++++++++++++++++++-
1 file changed, 29 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index db6e5a9e6de6..4d3203f887e2 100644
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -445,7 +445,7 @@ enum rk3228_plls {
RK2928_CLKGATE_CON(2), 12, GFLAGS,
&rk3228_spdif_fracmux),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK2928_CLKGATE_CON(1), 3, GFLAGS),
GATE(0, "sclk_otgphy0", "xin24m", 0,
@@ -644,9 +644,37 @@ enum rk3228_plls {
static const char *const rk3228_critical_clocks[] __initconst = {
"aclk_cpu",
+ "pclk_cpu",
+ "hclk_cpu",
"aclk_peri",
"hclk_peri",
"pclk_peri",
+ "aclk_rga_noc",
+ "aclk_iep_noc",
+ "aclk_vop_noc",
+ "aclk_hdcp_noc",
+ "hclk_vio_ahb_arbi",
+ "hclk_vio_noc",
+ "hclk_vop_noc",
+ "hclk_host0_arb",
+ "hclk_host1_arb",
+ "hclk_host2_arb",
+ "hclk_otg_pmu",
+ "aclk_gpu_noc",
+ "sclk_initmem_mbist",
+ "aclk_initmem",
+ "hclk_rom",
+ "pclk_ddrupctl",
+ "pclk_ddrmon",
+ "pclk_msch_noc",
+ "pclk_stimer",
+ "pclk_ddrphy",
+ "pclk_acodecphy",
+ "pclk_phy_noc",
+ "aclk_vpu_noc",
+ "aclk_rkvdec_noc",
+ "hclk_vpu_noc",
+ "hclk_rkvdec_noc",
};
static void __init rk3228_clk_init(struct device_node *np)
--
1.9.1
^ permalink raw reply related
* [PATCH v3 3/4] clk: rockchip: rk3288: make noc and some special clk as critical_clocks
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493710446-7203-1-git-send-email-zhangqing@rock-chips.com>
The atclk\dbg\jtag\xin12m\pclk_core clks no driver to handle them.
But this clks need enable,so make it as critical.
The ddrupctl0\ddrupctl1\publ0\publ1 clks no driver to handle them,
Chip design requirements for these clock to always on,
The new document will update the description of these clock.
The pmu_hclk_otg0 is Chip design defect, must be always on,
The new document will update the description of this clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3288.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rk3288.c b/drivers/clk/rockchip/clk-rk3288.c
index 68ba7d4105e7..450de24a1b42 100644
--- a/drivers/clk/rockchip/clk-rk3288.c
+++ b/drivers/clk/rockchip/clk-rk3288.c
@@ -292,13 +292,13 @@ enum rk3288_plls {
COMPOSITE_NOMUX(0, "aclk_core_mp", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(0), 4, 4, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 6, GFLAGS),
- COMPOSITE_NOMUX(0, "atclk", "armclk", 0,
+ COMPOSITE_NOMUX(0, "atclk", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 4, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 7, GFLAGS),
COMPOSITE_NOMUX(0, "pclk_dbg_pre", "armclk", CLK_IGNORE_UNUSED,
RK3288_CLKSEL_CON(37), 9, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
RK3288_CLKGATE_CON(12), 8, GFLAGS),
- GATE(0, "pclk_dbg", "pclk_dbg_pre", 0,
+ GATE(0, "pclk_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(12), 9, GFLAGS),
GATE(0, "cs_dbg", "pclk_dbg_pre", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(12), 10, GFLAGS),
@@ -626,7 +626,7 @@ enum rk3288_plls {
INVERTER(SCLK_HSADC, "sclk_hsadc", "sclk_hsadc_out",
RK3288_CLKSEL_CON(22), 7, IFLAGS),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(4), 14, GFLAGS),
COMPOSITE_NODIV(SCLK_USBPHY480M_SRC, "usbphy480m_src", mux_usbphy480m_p, 0,
@@ -635,7 +635,7 @@ enum rk3288_plls {
COMPOSITE_NODIV(SCLK_HSICPHY480M, "sclk_hsicphy480m", mux_hsicphy480m_p, 0,
RK3288_CLKSEL_CON(29), 0, 2, MFLAGS,
RK3288_CLKGATE_CON(3), 6, GFLAGS),
- GATE(0, "hsicphy12m_xin12m", "xin12m", 0,
+ GATE(0, "hsicphy12m_xin12m", "xin12m", CLK_IGNORE_UNUSED,
RK3288_CLKGATE_CON(13), 9, GFLAGS),
DIV(0, "hsicphy12m_usbphy", "sclk_hsicphy480m", 0,
RK3288_CLKSEL_CON(11), 8, 6, DFLAGS),
@@ -816,6 +816,12 @@ enum rk3288_plls {
"pclk_alive_niu",
"pclk_pd_pmu",
"pclk_pmu_niu",
+ "pclk_core_niu",
+ "pclk_ddrupctl0",
+ "pclk_publ0",
+ "pclk_ddrupctl1",
+ "pclk_publ1",
+ "pmu_hclk_otg0",
};
static void __iomem *rk3288_cru_base;
--
1.9.1
^ permalink raw reply related
* [PATCH v3 4/4] clk: rockchip: rk3368: make some special clk as critical_clocks
From: Elaine Zhang @ 2017-05-02 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493710446-7203-1-git-send-email-zhangqing@rock-chips.com>
The jtag clk no driver to handle them.
But this clk need enable,so make it as critical.
The ddrphy\ddrupctl clks no driver to handle them,
Chip design requirements for these clock to always on,
The new document will update the description of these clock.
The pmu_hclk_otg0 is Chip design defect, must be always on,
The new document will update the description of this clock.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
---
drivers/clk/rockchip/clk-rk3368.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/rockchip/clk-rk3368.c b/drivers/clk/rockchip/clk-rk3368.c
index 6cb474c593e7..b38343f9177c 100644
--- a/drivers/clk/rockchip/clk-rk3368.c
+++ b/drivers/clk/rockchip/clk-rk3368.c
@@ -638,7 +638,7 @@ enum rk3368_plls {
GATE(SCLK_MAC_TX, "sclk_mac_tx", "mac_clk", 0,
RK3368_CLKGATE_CON(7), 5, GFLAGS),
- GATE(0, "jtag", "ext_jtag", 0,
+ GATE(0, "jtag", "ext_jtag", CLK_IGNORE_UNUSED,
RK3368_CLKGATE_CON(7), 0, GFLAGS),
COMPOSITE_NODIV(0, "hsic_usbphy_480m", mux_hsic_usbphy480m_p, 0,
@@ -858,6 +858,9 @@ enum rk3368_plls {
*/
"pclk_pwm1",
"pclk_pd_pmu",
+ "pclk_ddrphy",
+ "pclk_ddrupctl",
+ "pmu_hclk_otg0",
};
static void __init rk3368_clk_init(struct device_node *np)
--
1.9.1
^ permalink raw reply related
* [PATCH v3 1/2] ASoC: stm32: add bindings for SAI
From: Olivier MOYSAN @ 2017-05-02 7:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170428205358.fxjqaki44xqim4ta@rob-hp-laptop>
Hello Rob,
On 04/28/2017 10:53 PM, Rob Herring wrote:
> On Mon, Apr 10, 2017 at 05:19:55PM +0200, olivier moysan wrote:
>> This patch adds documentation of device tree bindings for the
>> STM32 SAI ASoC driver.
>>
>> Signed-off-by: olivier moysan <olivier.moysan@st.com>
>> ---
>> .../devicetree/bindings/sound/st,stm32-sai.txt | 89 ++++++++++++++++++++++
>> 1 file changed, 89 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/sound/st,stm32-sai.txt
>>
>> diff --git a/Documentation/devicetree/bindings/sound/st,stm32-sai.txt b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt
>> new file mode 100644
>> index 0000000..c59a3d7
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/sound/st,stm32-sai.txt
>> @@ -0,0 +1,89 @@
>> +STMicroelectronics STM32 Serial Audio Interface (SAI).
>
> [...]
>
>> + sai1b: audio-controller at 40015824 {
>> + #sound-dai-cells = <0>;
>> + compatible = "st,stm32-sai-sub-b";
>> + reg = <0x40015824 0x1C>;
>> + clocks = <&rcc 1 CLK_SAI2>;
>> + clock-names = "sai_ck";
>> + dmas = <&dma2 5 0 0x400 0x0>;
>> + dma-names = "tx";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_sai1b>;
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + sai1b_port: port at 0 {
>> + reg = <0>;
>> + cpu_endpoint: endpoint {
>> + remote-endpoint = <&codec_endpoint>;
>> + audio-graph-card,format = "i2s";
>> + audio-graph-card,bitclock-master = <&codec_endpoint>;
>> + audio-graph-card,frame-master = <&codec_endpoint>;
>
> These property names are wrong.
>
I have taken into account this comment (and previous ones).
They will be included in next update of this patch set.
>> + };
>> + };
>> + };
>> + };
>> +};
>> +
>> +audio-codec {
>> + codec_port: port {
>> + codec_endpoint: endpoint {
>> + remote-endpoint = <&cpu_endpoint>;
>> + };
>> + };
>> +};
>> --
>> 1.9.1
>>
Best regards
Olivier
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox