* [PATCH/RFT v4 renesas-devel] ARM: dts: silk: Enable UHS-I SDR-50
From: Simon Horman @ 2017-05-02 8:43 UTC (permalink / raw)
To: linux-arm-kernel
Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI1.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
* Prepared on top of renesas-devel-20170501-v4.11
* Compile tested only; no access to silk board
v4
* Use sdhi1_pins_uhs rather than sdhi0_pins_uhs
v3
* Added missing pinctrl-1 to sdhi0
v2
* Correct mangled addition of sdhi*_pins
---
arch/arm/boot/dts/r8a7794-silk.dts | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 4cb5278d104d..824a5bfb2151 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -196,6 +196,13 @@
sdhi1_pins: sd1 {
groups = "sdhi1_data4", "sdhi1_ctrl";
function = "sdhi1";
+ power-source = <3300>;
+ };
+
+ sdhi1_pins_uhs: sd1_uhs {
+ groups = "sdhi1_data4", "sdhi1_ctrl";
+ function = "sdhi1";
+ power-source = <1800>;
};
qspi_pins: qspi {
@@ -338,11 +345,13 @@
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
- pinctrl-names = "default";
+ pinctrl-1 = <&sdhi1_pins_uhs>;
+ pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
+ sd-uhs-sdr50;
status = "okay";
};
--
2.1.4
^ permalink raw reply related
* [PATCH/RFT v4 renesas-devel] ARM: dts: silk: Enable UHS-I SDR-50
From: Wolfram Sang @ 2017-05-02 8:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493714605-4123-1-git-send-email-horms+renesas@verge.net.au>
On Tue, May 02, 2017 at 10:43:25AM +0200, Simon Horman wrote:
> Add the "1v8" pinctrl state and sd-uhs-sdr50 property to SDHI1.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Looks good, but I also can't test.
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^ permalink raw reply
* linux-next: build failure after merge of the drm-misc tree
From: Arnd Bergmann @ 2017-05-02 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170502184132.2c1b0299@canb.auug.org.au>
On Tue, May 2, 2017 at 10:41 AM, Stephen Rothwell <sfr@canb.auug.org.au> wrote:
> Hi Daniel,
>
> On Tue, 2 May 2017 10:25:18 +0200 Daniel Vetter <daniel@ffwll.ch> wrote:
>>
>> Since this is an all-new driver it might be best to stagger the pull
>> requests and merge the new tee subsystem (or whatever it is) after drm?
>>
>> Not sure what to best do here ...
>
> This will merge via Dave, so Dave just needs to let Linus know that a
> fix up is needed when this merges with the arm-soc stuff in Linus' tree.
The TEE subsystem is currently on a separate branch by itself in arm-soc,
so we could easily delay that until DRM is in, and point out the resolution
here.
Arnd
^ permalink raw reply
* [PATCH 2/2] cpufreq: scpi: use new scpi_ops functions to remove duplicate code
From: Sudeep Holla @ 2017-05-02 8:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1644626.pZFp7GD5Yb@aspire.rjw.lan>
On 28/04/17 22:34, Rafael J. Wysocki wrote:
> On Friday, April 28, 2017 02:54:56 PM Viresh Kumar wrote:
>> On 28-04-17, 10:21, Sudeep Holla wrote:
>>> scpi_ops now provide APIs to get the transition_latency and to add
>>> OPPs to the devices making those logic redundant here.
>>>
>>> This patch makes use of those APIs and removes the redunant code in
>>> this driver.
>>>
>>> Cc: "Rafael J. Wysocki" <rjw@rjwysocki.net>
>>> Cc: Viresh Kumar <viresh.kumar@linaro.org>
>>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
>>> ---
>>> drivers/cpufreq/scpi-cpufreq.c | 38 ++++++--------------------------------
>>> 1 file changed, 6 insertions(+), 32 deletions(-)
>>
>> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
>>
>>
>
> OK
>
> Sudeep, please route this through ARM.
Sure, thanks.
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH 0/3 v2] xen: Implement EFI reset_system callback
From: Julien Grall @ 2017-05-02 9:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170424175839.5262-1-julien.grall@arm.com>
Hi all,
It looks like the series has fully been acked, can someone merge this
into xentip?
Cheers,
On 04/24/2017 06:58 PM, Julien Grall wrote:
> Hi all,
>
> This small patch series implements EFI reset_system callback when using EFI
> Xen. Without this, it will not be possible to reboot/power off ARM64 DOM0
> when using ACPI.
>
> Cheers,
>
> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
> Cc: Juergen Gross <jgross@suse.com>
>
> Julien Grall (3):
> xen: Export xen_reboot
> arm/xen: Consolidate calls to shutdown hypercall in a single helper
> xen: Implement EFI reset_system callback
>
> arch/arm/xen/efi.c | 2 +-
> arch/arm/xen/enlighten.c | 16 ++++++++++------
> arch/x86/xen/efi.c | 2 +-
> arch/x86/xen/enlighten.c | 2 +-
> drivers/xen/efi.c | 18 ++++++++++++++++++
> include/xen/xen-ops.h | 5 +++++
> 6 files changed, 36 insertions(+), 9 deletions(-)
>
--
Julien Grall
^ permalink raw reply
* [PATCH 2/5] mtd: nand: gpmi: add i.MX 7 SoC support
From: Boris Brezillon @ 2017-05-02 9:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+EcR20FCPSec+ihTMA=SGwogd7p5tsnECCp3CR-Nv6fUciK4g@mail.gmail.com>
Hi Han,
On Fri, 21 Apr 2017 13:29:16 -0500
Han Xu <xhnjupt@gmail.com> wrote:
> >>
> >>>>> But then, adding the type would only require 2-3 lines of change if I
> >>>>> add it to the GPMI_IS_MX6 macro...
> >>>>
> >>>> Then at least add a comment because using type = IMX6SX right under
> >>>> gpmi_data_mx7d can trigger some head-scratching. And put my R-B on V2.
> >>>
> >>> FWIW, I mentioned it in the commit message.
> >>>
> >>> I think rather then adding a comment it is cleaner to just add IS_IMX7D
> >>> and add it to the GPMI_IS_MX6 macro. That does not need a comment since
> >>> it implicitly says we have a i.MX 7 but treat it like i.MX 6 and it is a
> >>> rather small change. Does that sound acceptable?
> >>
> >> Sure, that's even better, thanks.
> >>
> >> btw isn't there some single-core mx7 (mx7s ?) , maybe we should just go
> >> with mx7 (without the d suffix). I dunno if it has GPMI NAND though, so
> >> maybe mx7d is the right thing to do here ...
> >>
> >
> > There is a Solo version yes, and it has GPMI NAND too. However, almost
> > all i.MX 7 IPs have been named imx7d by NXP for some reason (including
> > compatible strings, see grep -r -e imx7 Documentation/), so I thought I
> > stay consistent here...
>
> Hi Guys,
>
> Yes, there should be a i.MX7 Solo version with one core fused out. IMO, can
> we use QUIRK to distinguish them rather than SoC name. I know I also sent
> some patch set with SoC Name but I prefer to use QUIRK now.
Not sure what this means. Are you okay with Stefan's v2?
Regards,
Boris
^ permalink raw reply
* [PATCH v7 5/7] coresight: add support for CPU debug module
From: Leo Yan @ 2017-05-02 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493713805-26920-6-git-send-email-leo.yan@linaro.org>
On Tue, May 02, 2017 at 04:30:03PM +0800, Leo Yan wrote:
[...]
> +static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
> +{
> + u32 edprcr;
> +
> +try_again:
> +
> + /*
> + * Send request to power management controller and assert
> + * DBGPWRUPREQ signal; if power management controller has
> + * sane implementation, it should enable CPU power domain
> + * in case CPU is in low power state.
> + */
> + edprcr = readl_relaxed(drvdata->base + EDPRCR);
> + edprcr |= EDPRCR_COREPURQ;
> + writel_relaxed(edprcr, drvdata->base + EDPRCR);
> +
> + /* Wait for CPU to be powered up (timeout~=32ms) */
> + if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR,
> + drvdata->edprsr, (drvdata->edprsr & EDPRSR_PU),
> + DEBUG_WAIT_SLEEP, DEBUG_WAIT_TIMEOUT)) {
> + /*
> + * Unfortunately the CPU cannot be powered up, so return
> + * back and later has no permission to access other
> + * registers. For this case, should disable CPU low power
> + * states to ensure CPU power domain is enabled!
> + */
> + pr_err("%s: power up request for CPU%d failed\n",
> + __func__, drvdata->cpu);
> + return;
> + }
> +
> + /*
> + * At this point the CPU is powered up, so set the no powerdown
> + * request bit so we don't lose power and emulate power down.
> + */
> + edprcr = readl_relaxed(drvdata->base + EDPRCR);
> + edprcr |= EDPRCR_COREPURQ | EDPRCR_CORENPDRQ;
> + writel_relaxed(edprcr, drvdata->base + EDPRCR);
> +
> + drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR);
> +
> + /* The core power domain got switched off on use, try again */
> + if (unlikely(!drvdata->edprsr & EDPRSR_PU))
Here have error introduced by operator priority. Should change to
if (unlikely(!(drvdata->edprsr & EDPRSR_PU)))
Will send new version soon for this fixing.
> + goto try_again;
> +}
[...]
Thanks,
Leo Yan
^ permalink raw reply
* [PATCH/RFT renesas-devel] arm64: dts: ulcb: Enable NFS root
From: Simon Horman @ 2017-05-02 9:24 UTC (permalink / raw)
To: linux-arm-kernel
Enable NFS root on the r8a7795/h3ulcb and r8a7796/m3ulcb
as per:
* commit b2407c566ba29215 ("arm64: dts: r8a7795: enable nfs root on Salvator-X board").
* commit 742a9dfb90f0 ("arm64: dts: r8a7796: salvator-x: Enable NFS root")
Also set ignore_loglevel rw as boot args as is the case for the boards
for the boards for other Renesas ARM/ARM64 based SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
* Compile tested only due to lack of hardware access
* Based on renesas-devel-20170502-v4.11
---
arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 2bc7ceb2efa4..7669b282bde2 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -21,6 +21,7 @@
};
chosen {
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
--
2.1.4
^ permalink raw reply related
* [PATCH/RFT renesas-devel] arm64: dts: ulcb: Enable NFS root
From: Geert Uytterhoeven @ 2017-05-02 9:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493717048-10740-1-git-send-email-horms+renesas@verge.net.au>
Hi Simon,
On Tue, May 2, 2017 at 11:24 AM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Enable NFS root on the r8a7795/h3ulcb and r8a7796/m3ulcb
> as per:
> * commit b2407c566ba29215 ("arm64: dts: r8a7795: enable nfs root on Salvator-X board").
> * commit 742a9dfb90f0 ("arm64: dts: r8a7796: salvator-x: Enable NFS root")
>
> Also set ignore_loglevel rw as boot args as is the case for the boards
> for the boards for other Renesas ARM/ARM64 based SoCs.
s/for the boards//
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 0/3 v2] xen: Implement EFI reset_system callback
From: Juergen Gross @ 2017-05-02 9:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <33472949-4748-f03e-cae9-65bd5f54c2f7@arm.com>
On 02/05/17 11:08, Julien Grall wrote:
> Hi all,
>
> It looks like the series has fully been acked, can someone merge this
> into xentip?
As I already wrote: patch 1 doesn't apply any longer.
As there were other conflicts between xentip and Linus' tree I'm doing
a rebase of for-linus-4.12 right now, so I can do the rebase of this
patch for you.
Juergen
>
> Cheers,
>
> On 04/24/2017 06:58 PM, Julien Grall wrote:
>> Hi all,
>>
>> This small patch series implements EFI reset_system callback when
>> using EFI
>> Xen. Without this, it will not be possible to reboot/power off ARM64 DOM0
>> when using ACPI.
>>
>> Cheers,
>>
>> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
>> Cc: Juergen Gross <jgross@suse.com>
>>
>> Julien Grall (3):
>> xen: Export xen_reboot
>> arm/xen: Consolidate calls to shutdown hypercall in a single helper
>> xen: Implement EFI reset_system callback
>>
>> arch/arm/xen/efi.c | 2 +-
>> arch/arm/xen/enlighten.c | 16 ++++++++++------
>> arch/x86/xen/efi.c | 2 +-
>> arch/x86/xen/enlighten.c | 2 +-
>> drivers/xen/efi.c | 18 ++++++++++++++++++
>> include/xen/xen-ops.h | 5 +++++
>> 6 files changed, 36 insertions(+), 9 deletions(-)
>>
>
^ permalink raw reply
* linux-next: build failure after merge of the drm-misc tree
From: Daniel Vetter @ 2017-05-02 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a0AqL1nZrmaBaHNJ0Nfji72Lm44DPPSoKzGFbd4FcQHFw@mail.gmail.com>
On Tue, May 2, 2017 at 10:55 AM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tue, May 2, 2017 at 10:41 AM, Stephen Rothwell <sfr@canb.auug.org.au> wrote:
>> Hi Daniel,
>>
>> On Tue, 2 May 2017 10:25:18 +0200 Daniel Vetter <daniel@ffwll.ch> wrote:
>>>
>>> Since this is an all-new driver it might be best to stagger the pull
>>> requests and merge the new tee subsystem (or whatever it is) after drm?
>>>
>>> Not sure what to best do here ...
>>
>> This will merge via Dave, so Dave just needs to let Linus know that a
>> fix up is needed when this merges with the arm-soc stuff in Linus' tree.
>
> The TEE subsystem is currently on a separate branch by itself in arm-soc,
> so we could easily delay that until DRM is in, and point out the resolution
> here.
Dave is somewhere without mail, but I chatted with him quickly and he
agrees this seems simplest. drm-next main pull should go out somewhere
tomorrow he said.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply
* [PATCH] kdump test comments:
From: yanjiang.jin at windriver.com @ 2017-05-02 9:47 UTC (permalink / raw)
To: linux-arm-kernel
From: Yanjiang Jin <yanjiang.jin@windriver.com>
1. Execute a kdump test on a "Freescale LayerScape LS1021E, Version: 2.0 board";
2. I think may all "proc-v7-3level" CPUs need this patch, but I only validated it on LS1021, so still use
#ifdef CONFIG_SOC_LS1021A
to wrap this change;
3. Append "crashkernel=128M at 2560M" in UBoot's command line;
4. Use uImage as kdump's first kernel and capture kernel, but ls1021A doesn't define LOADADDR now,
so add below code in "arch/arm/boot/Makefile" temporarily to build an uImage:
+ifeq ($(CONFIG_SOC_LS1021A), y)
+LOADADDR=0x80008000
+endif
+
Yanjiang Jin (1):
arm: proc-v7-3level.S: SOC_LS1021A: clear TTBCR.T1SZ
arch/arm/mm/proc-v7-3level.S | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH] arm: proc-v7-3level.S: SOC_LS1021A: clear TTBCR.T1SZ
From: yanjiang.jin at windriver.com @ 2017-05-02 9:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170502094718.188172-1-yanjiang.jin@windriver.com>
From: Yanjiang Jin <yanjiang.jin@windriver.com>
The macro "v7_ttb_setup" will set "TTBCR.T1SZ" only when
"PHYS_OFFSET <= PAGE_OFFSET".
But if we load the second kernel during kdump boot, PHYS_OFFSET may be
greater than PAGE_OFFSET, we don't want to set this bit, but TTBCR.T1SZ
is still not zero since the first kernel's value is reserved.
In this circumstance, the second kernel would hang once the MMU is enabled.
Signed-off-by: Yanjiang Jin <yanjiang.jin@windriver.com>
---
arch/arm/mm/proc-v7-3level.S | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 5e5720e..b6ca5eb 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -140,12 +140,16 @@ ENDPROC(cpu_v7_set_pte_ext)
* otherwise booting secondary CPUs would end up using TTBR1 for the
* identity mapping set up in TTBR0.
*/
- orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ
- mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
+
+#ifdef CONFIG_SOC_LS1021A
+ bic \tmp, \tmp, #TTBR1_SIZE @ clear TTBCR.T1SZ first
+#endif
+ orrls \tmp, \tmp, #TTBR1_SIZE @ TTBCR.T1SZ
+ mcr p15, 0, \tmp, c2, c0, 2 @ TTBCR
mov \tmp, \ttbr1, lsr #20
mov \ttbr1, \ttbr1, lsl #12
addls \ttbr1, \ttbr1, #TTBR1_OFFSET
- mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
+ mcrr p15, 1, \ttbr1, \tmp, c2 @ load TTBR1
.endm
/*
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 0/2] net: ixgbe: disable relaxed ordering at runtime
From: Gabriele Paoloni @ 2017-05-02 9:59 UTC (permalink / raw)
To: linux-arm-kernel
From: gabriele paoloni <gabriele.paoloni@huawei.com>
This patchset is based on Casey's patchset:
https://www.spinics.net/lists/arm-kernel/msg578927.html
It is a proposal to convert the ixgbe driver to disable RO at runtime
depending on the root port flags.
TODO: Casey's patchset above add quirks to disable RO only for Intel
E5-26xx and AMD ARM A1100, whereas currently the Intel ixgbe driver
disable RO by default. Therefore there may be some other host quirks
to be added in drivers/pci/quirks....
gabriele paoloni (2):
net: revert commit 1a8b6d76dc5b
net: ixgbe: disable RO depending on the root port flags
arch/Kconfig | 3 ---
arch/sparc/Kconfig | 1 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 35 ++++++++++++++-----------
3 files changed, 20 insertions(+), 19 deletions(-)
--
2.7.4
^ permalink raw reply
* [RFC PATCH 1/2] net: revert commit 1a8b6d76dc5b
From: Gabriele Paoloni @ 2017-05-02 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719166-9036-1-git-send-email-gabriele.paoloni@huawei.com>
From: gabriele paoloni <gabriele.paoloni@huawei.com>
commit 1a8b6d76dc5b was introducing relaxed ordering as global
symbol. This does not make sense as relaxed ordering support
depends on the PCIe EP and on the Root Complex (therefore it is
not related to the CPU architecture)
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
arch/Kconfig | 3 ---
arch/sparc/Kconfig | 1 -
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 2 +-
3 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/arch/Kconfig b/arch/Kconfig
index c4d6833..c0b118d 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -851,7 +851,4 @@ config STRICT_MODULE_RWX
and non-text memory will be made non-executable. This provides
protection against certain security exploits (e.g. writing to text)
-config ARCH_WANT_RELAX_ORDER
- bool
-
source "kernel/gcov/Kconfig"
diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig
index ed96869..3f47142 100644
--- a/arch/sparc/Kconfig
+++ b/arch/sparc/Kconfig
@@ -43,7 +43,6 @@ config SPARC
select ARCH_HAS_SG_CHAIN
select CPU_NO_EFFICIENT_FFS
select LOCKDEP_SMALL if LOCKDEP
- select ARCH_WANT_RELAX_ORDER
config SPARC32
def_bool !64BIT
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index c38d50c..094e1d6 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -350,7 +350,7 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
}
IXGBE_WRITE_FLUSH(hw);
-#ifndef CONFIG_ARCH_WANT_RELAX_ORDER
+#ifndef CONFIG_SPARC
/* Disable relaxed ordering */
for (i = 0; i < hw->mac.max_tx_queues; i++) {
u32 regval;
--
2.7.4
^ permalink raw reply related
* [RFC PATCH 2/2] net: ixgbe: disable RO depending on the root port flags
From: Gabriele Paoloni @ 2017-05-02 9:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719166-9036-1-git-send-email-gabriele.paoloni@huawei.com>
From: gabriele paoloni <gabriele.paoloni@huawei.com>
Intel ixgbe drivers currently disable relaxed ordering at
compilation time depending on the host architecture. This is wrong
as RO support depends either on the root complex implementation
and/or on the EP itself and/or both.
This patch checks at runtime the root port flag
PCI_DEV_FLAGS_NO_RELAXED_ORDERING to be set in order to disable RO.
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
---
drivers/net/ethernet/intel/ixgbe/ixgbe_common.c | 35 ++++++++++++++-----------
1 file changed, 20 insertions(+), 15 deletions(-)
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
index 094e1d6..597cb7b 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_common.c
@@ -342,6 +342,8 @@ s32 ixgbe_start_hw_generic(struct ixgbe_hw *hw)
s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
{
u32 i;
+ struct pci_dev *root;
+ struct ixgbe_adapter *adapter;
/* Clear the rate limiters */
for (i = 0; i < hw->mac.max_tx_queues; i++) {
@@ -350,25 +352,28 @@ s32 ixgbe_start_hw_gen2(struct ixgbe_hw *hw)
}
IXGBE_WRITE_FLUSH(hw);
-#ifndef CONFIG_SPARC
- /* Disable relaxed ordering */
- for (i = 0; i < hw->mac.max_tx_queues; i++) {
- u32 regval;
+ adapter = container_of(hw, struct ixgbe_adapter, hw);
+ root = pci_find_pcie_root_port(adapter->pdev);
- regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
- regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
- IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
- }
+ if (root && (root->dev_flags & PCI_DEV_FLAGS_NO_RELAXED_ORDERING)) {
+ /* Disable relaxed ordering */
+ for (i = 0; i < hw->mac.max_tx_queues; i++) {
+ u32 regval;
- for (i = 0; i < hw->mac.max_rx_queues; i++) {
- u32 regval;
+ regval = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(i));
+ regval &= ~IXGBE_DCA_TXCTRL_DESC_WRO_EN;
+ IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(i), regval);
+ }
+
+ for (i = 0; i < hw->mac.max_rx_queues; i++) {
+ u32 regval;
- regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
- regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
- IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
- IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
+ regval = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
+ regval &= ~(IXGBE_DCA_RXCTRL_DATA_WRO_EN |
+ IXGBE_DCA_RXCTRL_HEAD_WRO_EN);
+ IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(i), regval);
+ }
}
-#endif
return 0;
}
--
2.7.4
^ permalink raw reply related
* [PATCH v8 0/7] coresight: enable debug module
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
ARMv8 architecture reference manual (ARM DDI 0487A.k) Chapter H7 "The
Sample-based Profiling Extension" has description for sampling
registers, we can utilize these registers to check program counter
value with combined CPU exception level, secure state, etc. So this is
helpful for CPU lockup bugs, e.g. if one CPU has run into infinite loop
with IRQ disabled; the 'hang' CPU cannot switch context and handle any
interrupt, so it cannot handle SMP call for stack dump, etc.
This patch series is to enable coresight debug module with sample-based
registers and register call back notifier for PCSR register dumping
when panic happens, so we can see below dumping info for panic; and
this patch series has considered the conditions for access permission
for debug registers self, so this can avoid access debug registers when
CPU power domain is off; the driver also try to figure out the CPU is
in secure or non-secure state.
Patch 0001 is to document the dt binding; patch 0002 is to document
boot parameters used in kernel command line and add one detailed
document to describe the Coresight debug module implementation, the
clock and power domain impaction on the driver, some examples for
usage.
Patch 0003 is used to fix the func of_get_coresight_platform_data()
doesn't properly drop the reference to the CPU node pointer; and
patch 0004 is refactor to add new function of_coresight_get_cpu().
Patch 0005 is the driver for CPU debug module.
Patch 0006 in this series are to enable debug unit on 96boards Hikey,
Patch 0007 is to enable debug on 96boards DB410c. Have verified on both
two boards.
We can enable debugging with two methods, adding parameters into kernel
command line for build-in module:
coresight_cpu_debug.enable=1
Or we can wait the system has booted up to use debugfs nodes to enable
debugging:
# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
As result we can get below log after input command:
echo c > /proc/sysrq-trigger:
ARM external debug module:
CPU[0]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff00000808eb54>] handle_IPI+0xe4/0x150
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
CPU[1]:
EDPRSR: 0000000b (Power:On DLK:Unlock)
EDPCSR: [<ffff0000087a64c0>] debug_notifier_call+0x108/0x288
EDCIDSR: 00000000
EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
[...]
Changes from v7:
* Fix operator priority bug.
* Minor sequence adjustment for function debug_func_exit().
Changes from v6:
* According to Suzuki and Mathieu suggestions, refined debug module
driver to install panic notifier when insmod module; refined function
debug_force_cpu_powered_up() for CPU power state checking; some minor
fixing for output log, adding comments for memory barrier, code
alignment.
Changes from v5:
* According to Suzuki and Mathieu suggestions, refined debug module
driver to drop unused structure members, refactored initialization
code to distinguish hardware implementation features, refactored
flow for forcing CPU powered up, supported pm_runtime operations.
* Added one new doc file: Documentation/trace/coresight-cpu-debug.txt,
which is used to describe detailed info for implementation, clock
and power domain impaction on debug module, and exmaples for common
usage.
* Removed "idle constraints" from debug driver.
Changes from v4:
* This version is mainly credit to ARM colleagues many contribution
ideas for better quality (Thanks a lot Suzuki, Mike and Sudeep!).
* According to Suzuki suggestion, refined debug module driver to avoid
memory leak for drvdata struct, handle PCSAMPLE_MODE=1, use flag
drvdata.pc_has_offset to indicate if PCSR has offset, minor fixes.
* According to Mathieu suggestion, refined dt binding description.
* Changed driver to support module mode;
* According to Mike suggestion and very appreciate the pseudo code,
added support to force CPU powered up with register EDPRCR;
* According to discussions, added command line and debugfs nodes to
support enabling debugging for boot time, or later can dynamically
enable/disable debugging by debugfs.
* According to Rob Herring suggestion, one minor fixes in DT binding.
* According to Stephen Boyd suggestion, add const quality to structure
device_node. And used use of_cpu_device_node_get() to replace
of_get_cpu_node() in patch 0003.
Changes from v3:
* Added Suzuki K Poulose's patch to fix issue for the func
of_get_coresight_platform_data() doesn't properly drop the reference
to the CPU node pointer.
* According to Suzuki suggestion, added code to handl the corner case
for ARMv8 CPU with aarch32 mode.
* According to Suzuki suggestion, changed compatible string to
"arm,coresight-cpu-debug".
* According to Mathieu suggestion, added "power-domains" as optional
properties.
Changes from v2:
* According to Mathieu Poirier suggestion, applied some minor fixes.
* Added two extra patches for enabling debug module on Hikey.
Changes from v1:
* According to Mike Leach suggestion, removed the binding for debug
module clocks which have been directly provided by CPU clocks.
* According to Mathieu Poirier suggestion, added function
of_coresight_get_cpu() and some minor refactors for debug module
driver.
Changes from RFC:
* According to Mike Leach suggestion, added check for EDPRSR to avoid
lockup; added supporting EDVIDSR and EDCIDSR registers.
* According to Mark Rutland and Mathieu Poirier suggestion, rewrote
the documentation for DT binding.
* According to Mark and Mathieu suggestion, refined debug driver.
Leo Yan (6):
coresight: bindings for CPU debug module
doc: Add documentation for Coresight CPU debug
coresight: refactor with function of_coresight_get_cpu
coresight: add support for CPU debug module
arm64: dts: hi6220: register debug module
arm64: dts: qcom: msm8916: Add debug unit
Suzuki K Poulose (1):
coresight: of_get_coresight_platform_data: Add missing of_node_put
Documentation/admin-guide/kernel-parameters.txt | 7 +
.../bindings/arm/coresight-cpu-debug.txt | 49 ++
Documentation/trace/coresight-cpu-debug.txt | 174 ++++++
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 64 ++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 +
drivers/hwtracing/coresight/Kconfig | 14 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-cpu-debug.c | 670 +++++++++++++++++++++
drivers/hwtracing/coresight/of_coresight.c | 40 +-
include/linux/coresight.h | 2 +
10 files changed, 1041 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
create mode 100644 Documentation/trace/coresight-cpu-debug.txt
create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c
--
2.7.4
^ permalink raw reply
* [PATCH v8 1/7] coresight: bindings for CPU debug module
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org>
According to ARMv8 architecture reference manual (ARM DDI 0487A.k)
Chapter 'Part H: External debug', the CPU can integrate debug module
and it can support self-hosted debug and external debug. Especially
for supporting self-hosted debug, this means the program can access
the debug module from mmio region; and usually the mmio region is
integrated with coresight.
So add document for binding debug component, includes binding to APB
clock; and also need specify the CPU node which the debug module is
dedicated to specific CPU.
Suggested-by: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
.../bindings/arm/coresight-cpu-debug.txt | 49 ++++++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
new file mode 100644
index 0000000..2982912
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
@@ -0,0 +1,49 @@
+* CoreSight CPU Debug Component:
+
+CoreSight CPU debug component are compliant with the ARMv8 architecture
+reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
+external debug module is mainly used for two modes: self-hosted debug and
+external debug, and it can be accessed from mmio region from Coresight
+and eventually the debug module connects with CPU for debugging. And the
+debug module provides sample-based profiling extension, which can be used
+to sample CPU program counter, secure state and exception level, etc;
+usually every CPU has one dedicated debug module to be connected.
+
+Required properties:
+
+- compatible : should be "arm,coresight-cpu-debug"; supplemented with
+ "arm,primecell" since this driver is using the AMBA bus
+ interface.
+
+- reg : physical base address and length of the register set.
+
+- clocks : the clock associated to this component.
+
+- clock-names : the name of the clock referenced by the code. Since we are
+ using the AMBA framework, the name of the clock providing
+ the interconnect should be "apb_pclk" and the clock is
+ mandatory. The interface between the debug logic and the
+ processor core is clocked by the internal CPU clock, so it
+ is enabled with CPU clock by default.
+
+- cpu : the CPU phandle the debug module is affined to. When omitted
+ the module is considered to belong to CPU0.
+
+Optional properties:
+
+- power-domains: a phandle to the debug power domain. We use "power-domains"
+ binding to turn on the debug logic if it has own dedicated
+ power domain and if necessary to use "cpuidle.off=1" or
+ "nohlt" in the kernel command line or sysfs node to
+ constrain idle states to ensure registers in the CPU power
+ domain are accessible.
+
+Example:
+
+ debug at f6590000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6590000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH v8 2/7] doc: Add documentation for Coresight CPU debug
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org>
Update kernel-parameters.txt to add new parameter:
coresight_cpu_debug.enable is a knob to enable debugging at boot time.
Add detailed documentation, which contains the implementation, Mike
Leach excellent summary for "clock and power domain". At the end some
examples on how to enable the debugging functionality are provided.
Suggested-by: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
Documentation/admin-guide/kernel-parameters.txt | 7 +
Documentation/trace/coresight-cpu-debug.txt | 174 ++++++++++++++++++++++++
2 files changed, 181 insertions(+)
create mode 100644 Documentation/trace/coresight-cpu-debug.txt
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index facc20a..cf90146 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -650,6 +650,13 @@
/proc/<pid>/coredump_filter.
See also Documentation/filesystems/proc.txt.
+ coresight_cpu_debug.enable
+ [ARM,ARM64]
+ Format: <bool>
+ Enable/disable the CPU sampling based debugging.
+ 0: default value, disable debugging
+ 1: enable debugging at boot time
+
cpuidle.off=1 [CPU_IDLE]
disable the cpuidle sub-system
diff --git a/Documentation/trace/coresight-cpu-debug.txt b/Documentation/trace/coresight-cpu-debug.txt
new file mode 100644
index 0000000..0426d50
--- /dev/null
+++ b/Documentation/trace/coresight-cpu-debug.txt
@@ -0,0 +1,174 @@
+ Coresight CPU Debug Module
+ ==========================
+
+ Author: Leo Yan <leo.yan@linaro.org>
+ Date: April 5th, 2017
+
+Introduction
+------------
+
+Coresight CPU debug module is defined in ARMv8-a architecture reference manual
+(ARM DDI 0487A.k) Chapter 'Part H: External debug', the CPU can integrate
+debug module and it is mainly used for two modes: self-hosted debug and
+external debug. Usually the external debug mode is well known as the external
+debugger connects with SoC from JTAG port; on the other hand the program can
+explore debugging method which rely on self-hosted debug mode, this document
+is to focus on this part.
+
+The debug module provides sample-based profiling extension, which can be used
+to sample CPU program counter, secure state and exception level, etc; usually
+every CPU has one dedicated debug module to be connected. Based on self-hosted
+debug mechanism, Linux kernel can access these related registers from mmio
+region when the kernel panic happens. The callback notifier for kernel panic
+will dump related registers for every CPU; finally this is good for assistant
+analysis for panic.
+
+
+Implementation
+--------------
+
+- During driver registration, use EDDEVID and EDDEVID1 two device ID
+ registers to decide if sample-based profiling is implemented or not. On some
+ platforms this hardware feature is fully or partialy implemented; and if
+ this feature is not supported then registration will fail.
+
+- When write this doc, the debug driver mainly relies on three sampling
+ registers. The kernel panic callback notifier gathers info from EDPCSR
+ EDVIDSR and EDCIDSR; from EDPCSR we can get program counter, EDVIDSR has
+ information for secure state, exception level, bit width, etc; EDCIDSR is
+ context ID value which contains the sampled value of CONTEXTIDR_EL1.
+
+- The driver supports CPU running mode with either AArch64 or AArch32. The
+ registers naming convention is a bit different between them, AArch64 uses
+ 'ED' for register prefix (ARM DDI 0487A.k, chapter H9.1) and AArch32 uses
+ 'DBG' as prefix (ARM DDI 0487A.k, chapter G5.1). The driver is unified to
+ use AArch64 naming convention.
+
+- ARMv8-a (ARM DDI 0487A.k) and ARMv7-a (ARM DDI 0406C.b) have different
+ register bits definition. So the driver consolidates two difference:
+
+ If PCSROffset=0b0000, on ARMv8-a the feature of EDPCSR is not implemented;
+ but ARMv7-a defines "PCSR samples are offset by a value that depends on the
+ instruction set state". For ARMv7-a, the driver checks furthermore if CPU
+ runs with ARM or thumb instruction set and calibrate PCSR value, the
+ detailed description for offset is in ARMv7-a ARM (ARM DDI 0406C.b) chapter
+ C11.11.34 "DBGPCSR, Program Counter Sampling Register".
+
+ If PCSROffset=0b0010, ARMv8-a defines "EDPCSR implemented, and samples have
+ no offset applied and do not sample the instruction set state in AArch32
+ state". So on ARMv8 if EDDEVID1.PCSROffset is 0b0010 and the CPU operates
+ in AArch32 state, EDPCSR is not sampled; when the CPU operates in AArch64
+ state EDPCSR is sampled and no offset are applied.
+
+
+Clock and power domain
+----------------------
+
+Before accessing debug registers, we should ensure the clock and power domain
+have been enabled properly. In ARMv8-a ARM (ARM DDI 0487A.k) chapter 'H9.1
+Debug registers', the debug registers are spread into two domains: the debug
+domain and the CPU domain.
+
+ +---------------+
+ | |
+ | |
+ +----------+--+ |
+ dbg_clk -->| |**| |<-- cpu_clk
+ | Debug |**| CPU |
+ dbg_pd -->| |**| |<-- cpu_pd
+ +----------+--+ |
+ | |
+ | |
+ +---------------+
+
+For debug domain, the user uses DT binding "clocks" and "power-domains" to
+specify the corresponding clock source and power supply for the debug logic.
+The driver calls the pm_runtime_{put|get} operations as needed to handle the
+debug power domain.
+
+For CPU domain, the different SoC designs have different power management
+schemes and finally this heavily impacts external debug module. So we can
+divide into below cases:
+
+- On systems with a sane power controller which can behave correctly with
+ respect to CPU power domain, the CPU power domain can be controlled by
+ register EDPRCR in driver. The driver firstly writes bit EDPRCR.COREPURQ
+ to power up the CPU, and then writes bit EDPRCR.CORENPDRQ for emulation
+ of CPU power down. As result, this can ensure the CPU power domain is
+ powered on properly during the period when access debug related registers;
+
+- Some designs will power down an entire cluster if all CPUs on the cluster
+ are powered down - including the parts of the debug registers that should
+ remain powered in the debug power domain. The bits in EDPRCR are not
+ respected in these cases, so these designs do not support debug over
+ power down in the way that the CoreSight / Debug designers anticipated.
+ This means that even checking EDPRSR has the potential to cause a bus hang
+ if the target register is unpowered.
+
+ In this case, accessing to the debug registers while they are not powered
+ is a recipe for disaster; so we need preventing CPU low power states at boot
+ time or when user enable module at the run time. Please see chapter
+ "How to use the module" for detailed usage info for this.
+
+
+Device Tree Bindings
+--------------------
+
+See Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt for details.
+
+
+How to use the module
+---------------------
+
+If you want to enable debugging functionality@boot time, you can add
+"coresight_cpu_debug.enable=1" to the kernel command line parameter.
+
+The driver also can work as module, so can enable the debugging when insmod
+module:
+# insmod coresight_cpu_debug.ko debug=1
+
+When boot time or insmod module you have not enabled the debugging, the driver
+uses the debugfs file system to provide a knob to dynamically enable or disable
+debugging:
+
+To enable it, write a '1' into /sys/kernel/debug/coresight_cpu_debug/enable:
+# echo 1 > /sys/kernel/debug/coresight_cpu_debug/enable
+
+To disable it, write a '0' into /sys/kernel/debug/coresight_cpu_debug/enable:
+# echo 0 > /sys/kernel/debug/coresight_cpu_debug/enable
+
+As explained in chapter "Clock and power domain", if you are working on one
+platform which has idle states to power off debug logic and the power
+controller cannot work well for the request from EDPRCR, then you should
+firstly constraint CPU idle states before enable CPU debugging feature; so can
+ensure the accessing to debug logic.
+
+If you want to limit idle states at boot time, you can use "nohlt" or
+"cpuidle.off=1" in the kernel command line.
+
+At the runtime you can disable idle states with below methods:
+
+Set latency request to /dev/cpu_dma_latency to disable all CPUs specific idle
+states (if latency = 0uS then disable all idle states):
+# echo "what_ever_latency_you_need_in_uS" > /dev/cpu_dma_latency
+
+Disable specific CPU's specific idle state:
+# echo 1 > /sys/devices/system/cpu/cpu$cpu/cpuidle/state$state/disable
+
+
+Output format
+-------------
+
+Here is an example of the debugging output format:
+
+ARM external debug module:
+CPU[0]:
+ EDPRSR: 0000000b (Power:On DLK:Unlock)
+ EDPCSR: [<ffff00000808eb54>] handle_IPI+0xe4/0x150
+ EDCIDSR: 00000000
+ EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
+CPU[1]:
+ EDPRSR: 0000000b (Power:On DLK:Unlock)
+ EDPCSR: [<ffff0000087a64c0>] debug_notifier_call+0x108/0x288
+ EDCIDSR: 00000000
+ EDVIDSR: 90000000 (State:Non-secure Mode:EL1/0 Width:64bits VMID:0)
--
2.7.4
^ permalink raw reply related
* [PATCH v8 3/7] coresight: of_get_coresight_platform_data: Add missing of_node_put
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org>
From: Suzuki K Poulose <suzuki.poulose@arm.com>
The of_get_coresight_platform_data iterates over the possible CPU nodes
to find a given cpu phandle. However it does not drop the reference
to the node pointer returned by the of_get_coresight_platform_data.
This patch also introduces another minor fix is to use
of_cpu_device_node_get() to replace of_get_cpu_node().
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[Leo: minor tweaks for of_get_coresight_platform_data]
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
drivers/hwtracing/coresight/of_coresight.c | 17 ++++++++++-------
1 file changed, 10 insertions(+), 7 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c
index 859ad49..de7e8ce 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -108,7 +108,8 @@ struct coresight_platform_data *of_get_coresight_platform_data(
struct coresight_platform_data *pdata;
struct of_endpoint endpoint, rendpoint;
struct device *rdev;
- struct device_node *dn;
+ bool found;
+ struct device_node *dn, *np;
struct device_node *ep = NULL;
struct device_node *rparent = NULL;
struct device_node *rport = NULL;
@@ -175,17 +176,19 @@ struct coresight_platform_data *of_get_coresight_platform_data(
} while (ep);
}
- /* Affinity defaults to CPU0 */
- pdata->cpu = 0;
dn = of_parse_phandle(node, "cpu", 0);
- for (cpu = 0; dn && cpu < nr_cpu_ids; cpu++) {
- if (dn == of_get_cpu_node(cpu, NULL)) {
- pdata->cpu = cpu;
+ for_each_possible_cpu(cpu) {
+ np = of_cpu_device_node_get(cpu);
+ found = (dn == np);
+ of_node_put(np);
+ if (found)
break;
- }
}
of_node_put(dn);
+ /* Affinity to CPU0 if no cpu nodes are found */
+ pdata->cpu = found ? cpu : 0;
+
return pdata;
}
EXPORT_SYMBOL_GPL(of_get_coresight_platform_data);
--
2.7.4
^ permalink raw reply related
* [PATCH v8 4/7] coresight: refactor with function of_coresight_get_cpu
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org>
This is refactor to add function of_coresight_get_cpu(), so it's used to
retrieve CPU id for coresight component. Finally can use it as a common
function for multiple places.
Suggested-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
drivers/hwtracing/coresight/of_coresight.c | 43 +++++++++++++++++++-----------
include/linux/coresight.h | 2 ++
2 files changed, 30 insertions(+), 15 deletions(-)
diff --git a/drivers/hwtracing/coresight/of_coresight.c b/drivers/hwtracing/coresight/of_coresight.c
index de7e8ce..46eec0f 100644
--- a/drivers/hwtracing/coresight/of_coresight.c
+++ b/drivers/hwtracing/coresight/of_coresight.c
@@ -101,15 +101,39 @@ static int of_coresight_alloc_memory(struct device *dev,
return 0;
}
+int of_coresight_get_cpu(const struct device_node *node)
+{
+ int cpu;
+ bool found;
+ struct device_node *dn, *np;
+
+ dn = of_parse_phandle(node, "cpu", 0);
+
+ /* Affinity defaults to CPU0 */
+ if (!dn)
+ return 0;
+
+ for_each_possible_cpu(cpu) {
+ np = of_cpu_device_node_get(cpu);
+ found = (dn == np);
+ of_node_put(np);
+ if (found)
+ break;
+ }
+ of_node_put(dn);
+
+ /* Affinity to CPU0 if no cpu nodes are found */
+ return found ? cpu : 0;
+}
+EXPORT_SYMBOL_GPL(of_coresight_get_cpu);
+
struct coresight_platform_data *of_get_coresight_platform_data(
struct device *dev, const struct device_node *node)
{
- int i = 0, ret = 0, cpu;
+ int i = 0, ret = 0;
struct coresight_platform_data *pdata;
struct of_endpoint endpoint, rendpoint;
struct device *rdev;
- bool found;
- struct device_node *dn, *np;
struct device_node *ep = NULL;
struct device_node *rparent = NULL;
struct device_node *rport = NULL;
@@ -176,18 +200,7 @@ struct coresight_platform_data *of_get_coresight_platform_data(
} while (ep);
}
- dn = of_parse_phandle(node, "cpu", 0);
- for_each_possible_cpu(cpu) {
- np = of_cpu_device_node_get(cpu);
- found = (dn == np);
- of_node_put(np);
- if (found)
- break;
- }
- of_node_put(dn);
-
- /* Affinity to CPU0 if no cpu nodes are found */
- pdata->cpu = found ? cpu : 0;
+ pdata->cpu = of_coresight_get_cpu(node);
return pdata;
}
diff --git a/include/linux/coresight.h b/include/linux/coresight.h
index 769f2c8..4915254 100644
--- a/include/linux/coresight.h
+++ b/include/linux/coresight.h
@@ -263,9 +263,11 @@ static inline int coresight_timeout(void __iomem *addr, u32 offset,
#endif
#ifdef CONFIG_OF
+extern int of_coresight_get_cpu(const struct device_node *node);
extern struct coresight_platform_data *of_get_coresight_platform_data(
struct device *dev, const struct device_node *node);
#else
+static inline int of_coresight_get_cpu(const struct device_node *node) { return 0; }
static inline struct coresight_platform_data *of_get_coresight_platform_data(
struct device *dev, const struct device_node *node) { return NULL; }
#endif
--
2.7.4
^ permalink raw reply related
* [PATCH v8 5/7] coresight: add support for CPU debug module
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org>
Coresight includes debug module and usually the module connects with CPU
debug logic. ARMv8 architecture reference manual (ARM DDI 0487A.k) has
description for related info in "Part H: External Debug".
Chapter H7 "The Sample-based Profiling Extension" introduces several
sampling registers, e.g. we can check program counter value with
combined CPU exception level, secure state, etc. So this is helpful for
analysis CPU lockup scenarios, e.g. if one CPU has run into infinite
loop with IRQ disabled. In this case the CPU cannot switch context and
handle any interrupt (including IPIs), as the result it cannot handle
SMP call for stack dump.
This patch is to enable coresight debug module, so firstly this driver
is to bind apb clock for debug module and this is to ensure the debug
module can be accessed from program or external debugger. And the driver
uses sample-based registers for debug purpose, e.g. when system triggers
panic, the driver will dump program counter and combined context
registers (EDCIDSR, EDVIDSR); by parsing context registers so can
quickly get to know CPU secure state, exception level, etc.
Some of the debug module registers are located in CPU power domain, so
this requires the CPU power domain stays on when access related debug
registers, but the power management for CPU power domain is quite
dependent on SoC integration for power management. For the platforms
which with sane power controller implementations, this driver follows
the method to set EDPRCR to try to pull the CPU out of low power state
and then set 'no power down request' bit so the CPU has no chance to
lose power.
If the SoC has not followed up this design well for power management
controller, the user should use the command line parameter or sysfs
to constrain all or partial idle states to ensure the CPU power
domain is enabled and access coresight CPU debug component safely.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
drivers/hwtracing/coresight/Kconfig | 14 +
drivers/hwtracing/coresight/Makefile | 1 +
drivers/hwtracing/coresight/coresight-cpu-debug.c | 670 ++++++++++++++++++++++
3 files changed, 685 insertions(+)
create mode 100644 drivers/hwtracing/coresight/coresight-cpu-debug.c
diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
index 130cb21..8d55d6d 100644
--- a/drivers/hwtracing/coresight/Kconfig
+++ b/drivers/hwtracing/coresight/Kconfig
@@ -89,4 +89,18 @@ config CORESIGHT_STM
logging useful software events or data coming from various entities
in the system, possibly running different OSs
+config CORESIGHT_CPU_DEBUG
+ tristate "CoreSight CPU Debug driver"
+ depends on ARM || ARM64
+ depends on DEBUG_FS
+ help
+ This driver provides support for coresight debugging module. This
+ is primarily used to dump sample-based profiling registers when
+ system triggers panic, the driver will parse context registers so
+ can quickly get to know program counter (PC), secure state,
+ exception level, etc. Before use debugging functionality, platform
+ needs to ensure the clock domain and power domain are enabled
+ properly, please refer Documentation/trace/coresight-cpu-debug.txt
+ for detailed description and the example for usage.
+
endif
diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
index af480d9..433d590 100644
--- a/drivers/hwtracing/coresight/Makefile
+++ b/drivers/hwtracing/coresight/Makefile
@@ -16,3 +16,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
coresight-etm4x-sysfs.o
obj-$(CONFIG_CORESIGHT_QCOM_REPLICATOR) += coresight-replicator-qcom.o
obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
+obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
diff --git a/drivers/hwtracing/coresight/coresight-cpu-debug.c b/drivers/hwtracing/coresight/coresight-cpu-debug.c
new file mode 100644
index 0000000..b77456d
--- /dev/null
+++ b/drivers/hwtracing/coresight/coresight-cpu-debug.c
@@ -0,0 +1,670 @@
+/*
+ * Copyright (c) 2017 Linaro Limited. All rights reserved.
+ *
+ * Author: Leo Yan <leo.yan@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/amba/bus.h>
+#include <linux/coresight.h>
+#include <linux/cpu.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pm_qos.h>
+#include <linux/slab.h>
+#include <linux/smp.h>
+#include <linux/types.h>
+#include <linux/uaccess.h>
+
+#include "coresight-priv.h"
+
+#define EDPCSR 0x0A0
+#define EDCIDSR 0x0A4
+#define EDVIDSR 0x0A8
+#define EDPCSR_HI 0x0AC
+#define EDOSLAR 0x300
+#define EDPRCR 0x310
+#define EDPRSR 0x314
+#define EDDEVID1 0xFC4
+#define EDDEVID 0xFC8
+
+#define EDPCSR_PROHIBITED 0xFFFFFFFF
+
+/* bits definition for EDPCSR */
+#define EDPCSR_THUMB BIT(0)
+#define EDPCSR_ARM_INST_MASK GENMASK(31, 2)
+#define EDPCSR_THUMB_INST_MASK GENMASK(31, 1)
+
+/* bits definition for EDPRCR */
+#define EDPRCR_COREPURQ BIT(3)
+#define EDPRCR_CORENPDRQ BIT(0)
+
+/* bits definition for EDPRSR */
+#define EDPRSR_DLK BIT(6)
+#define EDPRSR_PU BIT(0)
+
+/* bits definition for EDVIDSR */
+#define EDVIDSR_NS BIT(31)
+#define EDVIDSR_E2 BIT(30)
+#define EDVIDSR_E3 BIT(29)
+#define EDVIDSR_HV BIT(28)
+#define EDVIDSR_VMID GENMASK(7, 0)
+
+/*
+ * bits definition for EDDEVID1:PSCROffset
+ *
+ * NOTE: armv8 and armv7 have different definition for the register,
+ * so consolidate the bits definition as below:
+ *
+ * 0b0000 - Sample offset applies based on the instruction state, we
+ * rely on EDDEVID to check if EDPCSR is implemented or not
+ * 0b0001 - No offset applies.
+ * 0b0010 - No offset applies, but do not use in AArch32 mode
+ *
+ */
+#define EDDEVID1_PCSR_OFFSET_MASK GENMASK(3, 0)
+#define EDDEVID1_PCSR_OFFSET_INS_SET (0x0)
+#define EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32 (0x2)
+
+/* bits definition for EDDEVID */
+#define EDDEVID_PCSAMPLE_MODE GENMASK(3, 0)
+#define EDDEVID_IMPL_EDPCSR (0x1)
+#define EDDEVID_IMPL_EDPCSR_EDCIDSR (0x2)
+#define EDDEVID_IMPL_FULL (0x3)
+
+#define DEBUG_WAIT_SLEEP 1000
+#define DEBUG_WAIT_TIMEOUT 32000
+
+struct debug_drvdata {
+ void __iomem *base;
+ struct device *dev;
+ int cpu;
+
+ bool edpcsr_present;
+ bool edcidsr_present;
+ bool edvidsr_present;
+ bool pc_has_offset;
+
+ u32 edpcsr;
+ u32 edpcsr_hi;
+ u32 edprsr;
+ u32 edvidsr;
+ u32 edcidsr;
+};
+
+static DEFINE_MUTEX(debug_lock);
+static DEFINE_PER_CPU(struct debug_drvdata *, debug_drvdata);
+static int debug_count;
+static struct dentry *debug_debugfs_dir;
+
+static bool debug_enable;
+module_param_named(enable, debug_enable, bool, 0600);
+MODULE_PARM_DESC(enable, "Knob to enable debug functionality "
+ "(default is 0, which means is disabled by default)");
+
+static void debug_os_unlock(struct debug_drvdata *drvdata)
+{
+ /* Unlocks the debug registers */
+ writel_relaxed(0x0, drvdata->base + EDOSLAR);
+
+ /* Make sure the registers are unlocked before accessing */
+ wmb();
+}
+
+/*
+ * According to ARM DDI 0487A.k, before access external debug
+ * registers should firstly check the access permission; if any
+ * below condition has been met then cannot access debug
+ * registers to avoid lockup issue:
+ *
+ * - CPU power domain is powered off;
+ * - The OS Double Lock is locked;
+ *
+ * By checking EDPRSR can get to know if meet these conditions.
+ */
+static bool debug_access_permitted(struct debug_drvdata *drvdata)
+{
+ /* CPU is powered off */
+ if (!(drvdata->edprsr & EDPRSR_PU))
+ return false;
+
+ /* The OS Double Lock is locked */
+ if (drvdata->edprsr & EDPRSR_DLK)
+ return false;
+
+ return true;
+}
+
+static void debug_force_cpu_powered_up(struct debug_drvdata *drvdata)
+{
+ u32 edprcr;
+
+try_again:
+
+ /*
+ * Send request to power management controller and assert
+ * DBGPWRUPREQ signal; if power management controller has
+ * sane implementation, it should enable CPU power domain
+ * in case CPU is in low power state.
+ */
+ edprcr = readl_relaxed(drvdata->base + EDPRCR);
+ edprcr |= EDPRCR_COREPURQ;
+ writel_relaxed(edprcr, drvdata->base + EDPRCR);
+
+ /* Wait for CPU to be powered up (timeout~=32ms) */
+ if (readx_poll_timeout_atomic(readl_relaxed, drvdata->base + EDPRSR,
+ drvdata->edprsr, (drvdata->edprsr & EDPRSR_PU),
+ DEBUG_WAIT_SLEEP, DEBUG_WAIT_TIMEOUT)) {
+ /*
+ * Unfortunately the CPU cannot be powered up, so return
+ * back and later has no permission to access other
+ * registers. For this case, should disable CPU low power
+ * states to ensure CPU power domain is enabled!
+ */
+ pr_err("%s: power up request for CPU%d failed\n",
+ __func__, drvdata->cpu);
+ return;
+ }
+
+ /*
+ * At this point the CPU is powered up, so set the no powerdown
+ * request bit so we don't lose power and emulate power down.
+ */
+ edprcr = readl_relaxed(drvdata->base + EDPRCR);
+ edprcr |= EDPRCR_COREPURQ | EDPRCR_CORENPDRQ;
+ writel_relaxed(edprcr, drvdata->base + EDPRCR);
+
+ drvdata->edprsr = readl_relaxed(drvdata->base + EDPRSR);
+
+ /* The core power domain got switched off on use, try again */
+ if (unlikely(!(drvdata->edprsr & EDPRSR_PU)))
+ goto try_again;
+}
+
+static void debug_read_regs(struct debug_drvdata *drvdata)
+{
+ u32 save_edprcr;
+
+ CS_UNLOCK(drvdata->base);
+
+ /* Unlock os lock */
+ debug_os_unlock(drvdata);
+
+ /* Save EDPRCR register */
+ save_edprcr = readl_relaxed(drvdata->base + EDPRCR);
+
+ /*
+ * Ensure CPU power domain is enabled to let registers
+ * are accessiable.
+ */
+ debug_force_cpu_powered_up(drvdata);
+
+ if (!debug_access_permitted(drvdata))
+ goto out;
+
+ drvdata->edpcsr = readl_relaxed(drvdata->base + EDPCSR);
+
+ /*
+ * As described in ARM DDI 0487A.k, if the processing
+ * element (PE) is in debug state, or sample-based
+ * profiling is prohibited, EDPCSR reads as 0xFFFFFFFF;
+ * EDCIDSR, EDVIDSR and EDPCSR_HI registers also become
+ * UNKNOWN state. So directly bail out for this case.
+ */
+ if (drvdata->edpcsr == EDPCSR_PROHIBITED)
+ goto out;
+
+ /*
+ * A read of the EDPCSR normally has the side-effect of
+ * indirectly writing to EDCIDSR, EDVIDSR and EDPCSR_HI;
+ * at this point it's safe to read value from them.
+ */
+ if (IS_ENABLED(CONFIG_64BIT))
+ drvdata->edpcsr_hi = readl_relaxed(drvdata->base + EDPCSR_HI);
+
+ if (drvdata->edcidsr_present)
+ drvdata->edcidsr = readl_relaxed(drvdata->base + EDCIDSR);
+
+ if (drvdata->edvidsr_present)
+ drvdata->edvidsr = readl_relaxed(drvdata->base + EDVIDSR);
+
+out:
+ /* Restore EDPRCR register */
+ writel_relaxed(save_edprcr, drvdata->base + EDPRCR);
+
+ CS_LOCK(drvdata->base);
+}
+
+static unsigned long debug_adjust_pc(struct debug_drvdata *drvdata)
+{
+ unsigned long arm_inst_offset = 0, thumb_inst_offset = 0;
+ unsigned long pc;
+
+ if (IS_ENABLED(CONFIG_64BIT))
+ return (unsigned long)drvdata->edpcsr_hi << 32 |
+ (unsigned long)drvdata->edpcsr;
+
+ pc = (unsigned long)drvdata->edpcsr;
+
+ if (drvdata->pc_has_offset) {
+ arm_inst_offset = 8;
+ thumb_inst_offset = 4;
+ }
+
+ /* Handle thumb instruction */
+ if (pc & EDPCSR_THUMB) {
+ pc = (pc & EDPCSR_THUMB_INST_MASK) - thumb_inst_offset;
+ return pc;
+ }
+
+ /*
+ * Handle arm instruction offset, if the arm instruction
+ * is not 4 byte alignment then it's possible the case
+ * for implementation defined; keep original value for this
+ * case and print info for notice.
+ */
+ if (pc & BIT(1))
+ pr_emerg("Instruction offset is implementation defined\n");
+ else
+ pc = (pc & EDPCSR_ARM_INST_MASK) - arm_inst_offset;
+
+ return pc;
+}
+
+static void debug_dump_regs(struct debug_drvdata *drvdata)
+{
+ unsigned long pc;
+
+ pr_emerg("\tEDPRSR: %08x (Power:%s DLK:%s)\n", drvdata->edprsr,
+ drvdata->edprsr & EDPRSR_PU ? "On" : "Off",
+ drvdata->edprsr & EDPRSR_DLK ? "Lock" : "Unlock");
+
+ if (!debug_access_permitted(drvdata)) {
+ pr_emerg("No permission to access debug registers!\n");
+ return;
+ }
+
+ if (drvdata->edpcsr == EDPCSR_PROHIBITED) {
+ pr_emerg("CPU is in Debug state or profiling is prohibited!\n");
+ return;
+ }
+
+ pc = debug_adjust_pc(drvdata);
+ pr_emerg("\tEDPCSR: [<%p>] %pS\n", (void *)pc, (void *)pc);
+
+ if (drvdata->edcidsr_present)
+ pr_emerg("\tEDCIDSR: %08x\n", drvdata->edcidsr);
+
+ if (drvdata->edvidsr_present)
+ pr_emerg("\tEDVIDSR: %08x (State:%s Mode:%s Width:%dbits VMID:%x)\n",
+ drvdata->edvidsr,
+ drvdata->edvidsr & EDVIDSR_NS ? "Non-secure" : "Secure",
+ drvdata->edvidsr & EDVIDSR_E3 ? "EL3" :
+ (drvdata->edvidsr & EDVIDSR_E2 ? "EL2" : "EL1/0"),
+ drvdata->edvidsr & EDVIDSR_HV ? 64 : 32,
+ drvdata->edvidsr & (u32)EDVIDSR_VMID);
+}
+
+static void debug_init_arch_data(void *info)
+{
+ struct debug_drvdata *drvdata = info;
+ u32 mode, pcsr_offset;
+ u32 eddevid, eddevid1;
+
+ CS_UNLOCK(drvdata->base);
+
+ /* Read device info */
+ eddevid = readl_relaxed(drvdata->base + EDDEVID);
+ eddevid1 = readl_relaxed(drvdata->base + EDDEVID1);
+
+ CS_LOCK(drvdata->base);
+
+ /* Parse implementation feature */
+ mode = eddevid & EDDEVID_PCSAMPLE_MODE;
+ pcsr_offset = eddevid1 & EDDEVID1_PCSR_OFFSET_MASK;
+
+ drvdata->edpcsr_present = false;
+ drvdata->edcidsr_present = false;
+ drvdata->edvidsr_present = false;
+ drvdata->pc_has_offset = false;
+
+ switch (mode) {
+ case EDDEVID_IMPL_FULL:
+ drvdata->edvidsr_present = true;
+ /* Fall through */
+ case EDDEVID_IMPL_EDPCSR_EDCIDSR:
+ drvdata->edcidsr_present = true;
+ /* Fall through */
+ case EDDEVID_IMPL_EDPCSR:
+ /*
+ * In ARM DDI 0487A.k, the EDDEVID1.PCSROffset is used to
+ * define if has the offset for PC sampling value; if read
+ * back EDDEVID1.PCSROffset == 0x2, then this means the debug
+ * module does not sample the instruction set state when
+ * armv8 CPU in AArch32 state.
+ */
+ drvdata->edpcsr_present =
+ ((IS_ENABLED(CONFIG_64BIT) && pcsr_offset != 0) ||
+ (pcsr_offset != EDDEVID1_PCSR_NO_OFFSET_DIS_AARCH32));
+
+ drvdata->pc_has_offset =
+ (pcsr_offset == EDDEVID1_PCSR_OFFSET_INS_SET);
+ break;
+ default:
+ break;
+ }
+}
+
+/*
+ * Dump out information on panic.
+ */
+static int debug_notifier_call(struct notifier_block *self,
+ unsigned long v, void *p)
+{
+ int cpu;
+ struct debug_drvdata *drvdata;
+
+ mutex_lock(&debug_lock);
+
+ /* Bail out if the functionality is disabled */
+ if (!debug_enable)
+ goto skip_dump;
+
+ pr_emerg("ARM external debug module:\n");
+
+ for_each_possible_cpu(cpu) {
+ drvdata = per_cpu(debug_drvdata, cpu);
+ if (!drvdata)
+ continue;
+
+ pr_emerg("CPU[%d]:\n", drvdata->cpu);
+
+ debug_read_regs(drvdata);
+ debug_dump_regs(drvdata);
+ }
+
+skip_dump:
+ mutex_unlock(&debug_lock);
+ return 0;
+}
+
+static struct notifier_block debug_notifier = {
+ .notifier_call = debug_notifier_call,
+};
+
+static int debug_enable_func(void)
+{
+ struct debug_drvdata *drvdata;
+ int cpu, ret = 0;
+
+ for_each_possible_cpu(cpu) {
+ drvdata = per_cpu(debug_drvdata, cpu);
+ if (!drvdata)
+ continue;
+
+ ret = pm_runtime_get_sync(drvdata->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(drvdata->dev);
+ goto err;
+ }
+ }
+
+err:
+ return ret;
+}
+
+static int debug_disable_func(void)
+{
+ struct debug_drvdata *drvdata;
+ int cpu, ret = 0;
+
+ for_each_possible_cpu(cpu) {
+ drvdata = per_cpu(debug_drvdata, cpu);
+ if (!drvdata)
+ continue;
+
+ ret = pm_runtime_put(drvdata->dev);
+ if (ret < 0)
+ goto err;
+ }
+
+err:
+ return ret;
+}
+
+static ssize_t debug_func_knob_write(struct file *f,
+ const char __user *buf, size_t count, loff_t *ppos)
+{
+ u8 val;
+ int ret;
+
+ ret = kstrtou8_from_user(buf, count, 2, &val);
+ if (ret)
+ return ret;
+
+ mutex_lock(&debug_lock);
+
+ if (val == debug_enable)
+ goto out;
+
+ if (val)
+ ret = debug_enable_func();
+ else
+ ret = debug_disable_func();
+
+ if (ret) {
+ pr_err("%s: unable to %s debug function: %d\n",
+ __func__, val ? "enable" : "disable", ret);
+ goto err;
+ }
+
+ debug_enable = val;
+out:
+ ret = count;
+err:
+ mutex_unlock(&debug_lock);
+ return ret;
+}
+
+static ssize_t debug_func_knob_read(struct file *f,
+ char __user *ubuf, size_t count, loff_t *ppos)
+{
+ ssize_t ret;
+ char buf[3];
+
+ mutex_lock(&debug_lock);
+
+ snprintf(buf, sizeof(buf), "%d\n", debug_enable);
+ ret = simple_read_from_buffer(ubuf, count, ppos, buf, sizeof(buf));
+
+ mutex_unlock(&debug_lock);
+ return ret;
+}
+
+static const struct file_operations debug_func_knob_fops = {
+ .open = simple_open,
+ .read = debug_func_knob_read,
+ .write = debug_func_knob_write,
+};
+
+static int debug_func_init(void)
+{
+ struct dentry *file;
+ int ret;
+
+ /* Create debugfs node */
+ debug_debugfs_dir = debugfs_create_dir("coresight_cpu_debug", NULL);
+ if (!debug_debugfs_dir) {
+ pr_err("%s: unable to create debugfs directory\n", __func__);
+ return -ENOMEM;
+ }
+
+ file = debugfs_create_file("enable", 0644, debug_debugfs_dir, NULL,
+ &debug_func_knob_fops);
+ if (!file) {
+ pr_err("%s: unable to create enable knob file\n", __func__);
+ ret = -ENOMEM;
+ goto err;
+ }
+
+ /* Register function to be called for panic */
+ ret = atomic_notifier_chain_register(&panic_notifier_list,
+ &debug_notifier);
+ if (ret) {
+ pr_err("%s: unable to register notifier: %d\n",
+ __func__, ret);
+ goto err;
+ }
+
+ return 0;
+
+err:
+ debugfs_remove_recursive(debug_debugfs_dir);
+ return ret;
+}
+
+static void debug_func_exit(void)
+{
+ atomic_notifier_chain_unregister(&panic_notifier_list,
+ &debug_notifier);
+ debugfs_remove_recursive(debug_debugfs_dir);
+}
+
+static int debug_probe(struct amba_device *adev, const struct amba_id *id)
+{
+ void __iomem *base;
+ struct device *dev = &adev->dev;
+ struct debug_drvdata *drvdata;
+ struct resource *res = &adev->res;
+ struct device_node *np = adev->dev.of_node;
+ int ret;
+
+ drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
+ if (!drvdata)
+ return -ENOMEM;
+
+ drvdata->cpu = np ? of_coresight_get_cpu(np) : 0;
+ if (per_cpu(debug_drvdata, drvdata->cpu)) {
+ dev_err(dev, "CPU%d drvdata has been initialized, "
+ "may be caused by binding wrong CPU node in the DT\n",
+ drvdata->cpu);
+ return -EBUSY;
+ }
+
+ drvdata->dev = &adev->dev;
+ amba_set_drvdata(adev, drvdata);
+
+ /* Validity for the resource is already checked by the AMBA core */
+ base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ drvdata->base = base;
+
+ get_online_cpus();
+ per_cpu(debug_drvdata, drvdata->cpu) = drvdata;
+ ret = smp_call_function_single(drvdata->cpu, debug_init_arch_data,
+ drvdata, 1);
+ put_online_cpus();
+
+ if (ret) {
+ dev_err(dev, "CPU%d debug arch init failed\n", drvdata->cpu);
+ goto err;
+ }
+
+ if (!drvdata->edpcsr_present) {
+ dev_err(dev, "CPU%d sample-based profiling isn't implemented\n",
+ drvdata->cpu);
+ ret = -ENXIO;
+ goto err;
+ }
+
+ if (!debug_count++) {
+ ret = debug_func_init();
+ if (ret)
+ goto err_func_init;
+ }
+
+ mutex_lock(&debug_lock);
+ if (!debug_enable)
+ pm_runtime_put(dev);
+ mutex_unlock(&debug_lock);
+
+ dev_info(dev, "Coresight debug-CPU%d initialized\n", drvdata->cpu);
+ return 0;
+
+err_func_init:
+ debug_count--;
+err:
+ per_cpu(debug_drvdata, drvdata->cpu) = NULL;
+ return ret;
+}
+
+static int debug_remove(struct amba_device *adev)
+{
+ struct device *dev = &adev->dev;
+ struct debug_drvdata *drvdata = amba_get_drvdata(adev);
+
+ per_cpu(debug_drvdata, drvdata->cpu) = NULL;
+
+ mutex_lock(&debug_lock);
+ if (debug_enable)
+ pm_runtime_put(dev);
+ mutex_unlock(&debug_lock);
+
+ if (!--debug_count)
+ debug_func_exit();
+
+ return 0;
+}
+
+static struct amba_id debug_ids[] = {
+ { /* Debug for Cortex-A53 */
+ .id = 0x000bbd03,
+ .mask = 0x000fffff,
+ },
+ { /* Debug for Cortex-A57 */
+ .id = 0x000bbd07,
+ .mask = 0x000fffff,
+ },
+ { /* Debug for Cortex-A72 */
+ .id = 0x000bbd08,
+ .mask = 0x000fffff,
+ },
+ { 0, 0 },
+};
+
+static struct amba_driver debug_driver = {
+ .drv = {
+ .name = "coresight-cpu-debug",
+ .suppress_bind_attrs = true,
+ },
+ .probe = debug_probe,
+ .remove = debug_remove,
+ .id_table = debug_ids,
+};
+
+module_amba_driver(debug_driver);
+
+MODULE_AUTHOR("Leo Yan <leo.yan@linaro.org>");
+MODULE_DESCRIPTION("ARM Coresight CPU Debug Driver");
+MODULE_LICENSE("GPL");
--
2.7.4
^ permalink raw reply related
* [PATCH v8 6/7] arm64: dts: hi6220: register debug module
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org>
Bind debug module driver for Hi6220.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 64 +++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 470461d..467aa15 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -913,5 +913,69 @@
};
};
};
+
+ debug at f6590000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6590000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+
+ debug at f6592000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6592000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu1>;
+ };
+
+ debug at f6594000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6594000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu2>;
+ };
+
+ debug at f6596000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf6596000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu3>;
+ };
+
+ debug at f65d0000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d0000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu4>;
+ };
+
+ debug at f65d2000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d2000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu5>;
+ };
+
+ debug at f65d4000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d4000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu6>;
+ };
+
+ debug at f65d6000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0 0xf65d6000 0 0x1000>;
+ clocks = <&sys_ctrl HI6220_DAPB_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu7>;
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v8 7/7] arm64: dts: qcom: msm8916: Add debug unit
From: Leo Yan @ 2017-05-02 10:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1493719717-27698-1-git-send-email-leo.yan@linaro.org>
Add debug unit on Qualcomm msm8916 based platforms, including the
DragonBoard 410c board.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 68a8e67..3af814b 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1104,6 +1104,38 @@
};
};
+ debug at 850000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x850000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU0>;
+ };
+
+ debug at 852000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x852000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU1>;
+ };
+
+ debug at 854000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x854000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU2>;
+ };
+
+ debug at 856000 {
+ compatible = "arm,coresight-cpu-debug","arm,primecell";
+ reg = <0x856000 0x1000>;
+ clocks = <&rpmcc RPM_QDSS_CLK>;
+ clock-names = "apb_pclk";
+ cpu = <&CPU3>;
+ };
+
etm at 85c000 {
compatible = "arm,coresight-etm4x", "arm,primecell";
reg = <0x85c000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 0/3 v2] xen: Implement EFI reset_system callback
From: Juergen Gross @ 2017-05-02 10:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20170424175839.5262-1-julien.grall@arm.com>
On 24/04/17 19:58, Julien Grall wrote:
> Hi all,
>
> This small patch series implements EFI reset_system callback when using EFI
> Xen. Without this, it will not be possible to reboot/power off ARM64 DOM0
> when using ACPI.
>
> Cheers,
>
> Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
> Cc: Juergen Gross <jgross@suse.com>
Series rebased and pushed to xen/tip for-linus-4.12b
Juergen
^ permalink raw reply
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