* [PATCH V4 4/5] dmaengine: qcom_hidma: Add support for the new revision
From: Sinan Kaya @ 2017-12-01 2:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512096776-22883-1-git-send-email-okaya@codeaurora.org>
Add support for probing the newer HW and also organize MSI capable hardware
into an array for maintenance reasons.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma.c | 34 +++++++++++++---------------------
1 file changed, 13 insertions(+), 21 deletions(-)
diff --git a/drivers/dma/qcom/hidma.c b/drivers/dma/qcom/hidma.c
index e366985..c146c6d 100644
--- a/drivers/dma/qcom/hidma.c
+++ b/drivers/dma/qcom/hidma.c
@@ -50,6 +50,7 @@
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/of_dma.h>
+#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/delay.h>
#include <linux/acpi.h>
@@ -104,6 +105,9 @@ static void hidma_free(struct hidma_dev *dmadev)
module_param(nr_desc_prm, uint, 0644);
MODULE_PARM_DESC(nr_desc_prm, "number of descriptors (default: 0)");
+enum hidma_cap {
+ HIDMA_MSI_CAP = 1,
+};
/* process completed descriptors */
static void hidma_process_completed(struct hidma_chan *mchan)
@@ -736,25 +740,12 @@ static int hidma_request_msi(struct hidma_dev *dmadev,
#endif
}
-static bool hidma_msi_capable(struct device *dev)
+static bool hidma_test_capability(struct device *dev, enum hidma_cap test_cap)
{
- struct acpi_device *adev = ACPI_COMPANION(dev);
- const char *of_compat;
- int ret = -EINVAL;
-
- if (!adev || acpi_disabled) {
- ret = device_property_read_string(dev, "compatible",
- &of_compat);
- if (ret)
- return false;
+ enum hidma_cap cap;
- ret = strcmp(of_compat, "qcom,hidma-1.1");
- } else {
-#ifdef CONFIG_ACPI
- ret = strcmp(acpi_device_hid(adev), "QCOM8062");
-#endif
- }
- return ret == 0;
+ cap = (enum hidma_cap) device_get_match_data(dev);
+ return cap ? ((cap & test_cap) > 0) : 0;
}
static int hidma_probe(struct platform_device *pdev)
@@ -834,8 +825,7 @@ static int hidma_probe(struct platform_device *pdev)
* Determine the MSI capability of the platform. Old HW doesn't
* support MSI.
*/
- msi = hidma_msi_capable(&pdev->dev);
-
+ msi = hidma_test_capability(&pdev->dev, HIDMA_MSI_CAP);
device_property_read_u32(&pdev->dev, "desc-count",
&dmadev->nr_descriptors);
@@ -953,7 +943,8 @@ static int hidma_remove(struct platform_device *pdev)
#if IS_ENABLED(CONFIG_ACPI)
static const struct acpi_device_id hidma_acpi_ids[] = {
{"QCOM8061"},
- {"QCOM8062"},
+ {"QCOM8062", HIDMA_MSI_CAP},
+ {"QCOM8063", HIDMA_MSI_CAP},
{},
};
MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
@@ -961,7 +952,8 @@ static int hidma_remove(struct platform_device *pdev)
static const struct of_device_id hidma_match[] = {
{.compatible = "qcom,hidma-1.0",},
- {.compatible = "qcom,hidma-1.1",},
+ {.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),},
+ {.compatible = "qcom,hidma-1.2", .data = (void *)(HIDMA_MSI_CAP),},
{},
};
MODULE_DEVICE_TABLE(of, hidma_match);
--
1.9.1
^ permalink raw reply related
* [PATCH V4 5/5] dmaengine: qcom_hidma: Add identity register support
From: Sinan Kaya @ 2017-12-01 2:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512096776-22883-1-git-send-email-okaya@codeaurora.org>
The location for destination event channel register has been relocated from
offset 0x28 to 0x40. Update the code accordingly.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/drivers/dma/qcom/hidma.c b/drivers/dma/qcom/hidma.c
index c146c6d..963cc52 100644
--- a/drivers/dma/qcom/hidma.c
+++ b/drivers/dma/qcom/hidma.c
@@ -107,6 +107,7 @@ static void hidma_free(struct hidma_dev *dmadev)
enum hidma_cap {
HIDMA_MSI_CAP = 1,
+ HIDMA_IDENTITY_CAP,
};
/* process completed descriptors */
@@ -838,7 +839,10 @@ static int hidma_probe(struct platform_device *pdev)
if (!dmadev->nr_descriptors)
dmadev->nr_descriptors = HIDMA_NR_DEFAULT_DESC;
- dmadev->chidx = readl(dmadev->dev_trca + 0x28);
+ if (hidma_test_capability(&pdev->dev, HIDMA_IDENTITY_CAP))
+ dmadev->chidx = readl(dmadev->dev_trca + 0x40);
+ else
+ dmadev->chidx = readl(dmadev->dev_trca + 0x28);
/* Set DMA mask to 64 bits. */
rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
@@ -944,7 +948,7 @@ static int hidma_remove(struct platform_device *pdev)
static const struct acpi_device_id hidma_acpi_ids[] = {
{"QCOM8061"},
{"QCOM8062", HIDMA_MSI_CAP},
- {"QCOM8063", HIDMA_MSI_CAP},
+ {"QCOM8063", (HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP)},
{},
};
MODULE_DEVICE_TABLE(acpi, hidma_acpi_ids);
@@ -953,7 +957,8 @@ static int hidma_remove(struct platform_device *pdev)
static const struct of_device_id hidma_match[] = {
{.compatible = "qcom,hidma-1.0",},
{.compatible = "qcom,hidma-1.1", .data = (void *)(HIDMA_MSI_CAP),},
- {.compatible = "qcom,hidma-1.2", .data = (void *)(HIDMA_MSI_CAP),},
+ {.compatible = "qcom,hidma-1.2",
+ .data = (void *)(HIDMA_MSI_CAP | HIDMA_IDENTITY_CAP),},
{},
};
MODULE_DEVICE_TABLE(of, hidma_match);
--
1.9.1
^ permalink raw reply related
* 答复: 答复: [PATCH v5 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs
From: liwei (CM) @ 2017-12-01 3:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a37yYDQZpZxmunCdSO83qkqywTME5Xo0k56nWEs2k+=dg@mail.gmail.com>
Hi, Arnd
Sorry to bother you, some questions about this patch will trouble you to give some advice:
+ ufs: ufs at ff3b0000 {
+ compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3b0000 0x0 0x1000>,
+ <0x0 0xff3b1000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+ clock-names = "clk_ref", "clk_phy";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ /* offset: 0x84; bit: 7 */
+ resets = <&crg_rst 0x84 12>,
+ <&crg_rst 0x84 7>;
+ reset-names = "rst", "assert";
+ };
1. our UFS host soc implementation can be divided into two parts: UFS controller and related peripheral circuit, that "HCI standard"<-> UFS controller, "UFS SYS CTRL"<-> related peripheral circuit, and PHY is part of the peripheral circuit. So the "UFS SYS CTRL" area does not correspond completely to what Qualcomm have described as their PHY implementation. In fact, we do not have an independent register space to control the PHY.
2. From our soc chip colleague, "rst", "assert" is not generic and related with our soc implementation. In fact?it is not just a rst and assert of the UFS controller, but for the entire UFS IP ,so I don't think it's very helpful for others.
I think the above places will be reserved, do you have any better advices.
Thank you very much.
-----????-----
???: liwei (CM)
????: 2017?10?31? 20:35
???: 'Arnd Bergmann'
??: Rob Herring; Mark Rutland; xuwei (O); Catalin Marinas; Will Deacon; Vinayak Holikatti; James E.J. Bottomley; Martin K. Petersen; Kevin Hilman; Gregory CLEMENT; Thomas Petazzoni; Masahiro Yamada; Riku Voipio; Thierry Reding; Krzysztof Kozlowski; Eric Anholt; DTML; Linux Kernel Mailing List; Linux ARM; linux-scsi; Guodong Xu; Fengbaopeng (kevin, Kirin Solution Dept); lihuan (Z); wangyupeng (A); zangleigang
??: ??: ??: [PATCH v5 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs
Hi, Arnd
Thank you for your reply.
-----????-----
???: arndbergmann at gmail.com [mailto:arndbergmann at gmail.com] ?? Arnd Bergmann
????: 2017?10?30? 23:22
???: liwei (CM)
??: Rob Herring; Mark Rutland; xuwei (O); Catalin Marinas; Will Deacon; Vinayak Holikatti; James E.J. Bottomley; Martin K. Petersen; Kevin Hilman; Gregory CLEMENT; Thomas Petazzoni; Masahiro Yamada; Riku Voipio; Thierry Reding; Krzysztof Kozlowski; Eric Anholt; DTML; Linux Kernel Mailing List; Linux ARM; linux-scsi; Guodong Xu; Fengbaopeng (kevin, Kirin Solution Dept); lihuan (Z); wangyupeng (A)
??: Re: ??: [PATCH v5 2/5] dt-bindings: scsi: ufs: add document for hisi-ufs
On Tue, Oct 24, 2017 at 11:06 AM, liwei (CM) <liwei213@huawei.com> wrote:
> what's your opinion about my explanation and revision method?
> I am looking forward to your reply, thanks!
Sorry for the delay, I was travelling last week.
> ???: arndbergmann at gmail.com [mailto:arndbergmann at gmail.com] ?? Arnd
> Bergmann On Fri, Oct 20, 2017 at 10:52 AM, Li Wei <liwei213@huawei.com> wrote:
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/ufs/ufs-hisi.txt
>> @@ -0,0 +1,46 @@
>> +* Hisilicon Universal Flash Storage (UFS) Host Controller
>> +
>> +UFS nodes are defined to describe on-chip UFS hardware macro.
>> +Each UFS Host Controller should have its own node.
>> +
>> +Required properties:
>> +- compatible : compatible list, contains one of the following -
>> + "hisilicon,hi3660-ufs" for hisi ufs host controller
>> + present on Hi3660 chipset.
One more thing I just noticed: you don't describe the device as compatible with the ufshcd spec as defined in the generic binding. Shouldn't we have both compatible strings listed here?
Ok, I will fix it in patch v6;
> In particular, I wonder if what you describe as the "UFS SYS CTRL"
> area corresponds to what Qualcomm have described as their PHY implementation. It certainly seems to driver some of the properties that would normally be associated with a PHY.
>
> Liwei:Yes, a part of "UFS SYS CTRL" is associated with a PHY, but from our chip colleague that we assure "UFS SYS CTRL" is associated with clk/reset/power on/power off and so on.
> In fact, in addition to the controller itself, the controller related periphery are all in this area. So it's not appropriate to put this into a separate phy node.
I'm not sure I understand here. Do you mean the reset handle is for resetting the PHY rather than the UFS HCD?
Maybe my description is not clear enough, our UFS host soc implementation can be divided into two parts: UFS controller and related peripheral circuit, that "HCI standard"<-> UFS controller, "UFS SYS CTRL"<-> related peripheral circuit, and PHY is part of the peripheral circuit. So the "UFS SYS CTRL" area does not correspond completely to what Qualcomm have described as their PHY implementation.
The root reason is that our UFS host had not divided into UFS controller and PHY?
> > For the "clock-names" property, you specify "clk_ref", which I assume is the same as what Qualcomm call "ref_clk". I'd suggest you use the existing name and add that as the default name in the ufshcd-pltfrm.txt binding document.
>
> Liwei:" ref_clk " is already in the ufshcd-pltfrm.txt binding
> document, and parse in ufshcd.c, so we will replace "clk_ref" with
> "ref_clk". I will fix it in patch v6;
ok
> > The "clk_phy" property appears to be related to the PHY, so it might be better to have a separate phy node with either just the clk, or with the clk plus the "UFS SYS CTRL" register area, whichever matches your hardware better, and then use teh "phys/phy-names" property to refer to that.
>
> Liwei: OK, I will add a separate phy node and fix it in patch v6;
Thanks.
>> The reset handling you describe here (both resets and reset-gpios) appears to be completely generic, so I'd suggest adding those to ufshcd-pltfrm.txt instead of your own binding, to ensure that future drivers use the same identifiers.
>
> Liwei: From our soc chip colleague, reset include "rst", "assert" is
> not generic and related with our soc implementation, you can see
> ufs_hisi_soc_init() in drivers/scsi/ufs/ufs-hisi.c, the position of
> rst and assert is very special, it's hard to put it in a generic
> process;
It seems odd that the ability to reset a device is specific to your implementation. What I meant is that other implementations may also require a reset, so describing the way you refer to this into the generic binding would be helpful, to prevent others from adding another incompatible way to do the same thing.
A lot of generic bindings have a reference to a reset controller that if present needs to be used before first accessing the device itself.
I mean our reset process is really special, but there is no parse of this "reset" in generic driver code like ufshcd.c or ufshcd-pltfrm.c; Even if I add those to ufshcd-pltfrm.txt and implement the common parsing code, but our special requirements are difficult to satisfy; What do you think about if I put all the implementations of reset in our driver code, and remove "reset" property here?
> reset-gpios is used to solve a defect of the SOC chip reset function
> and it is not generic , but our chip has been updated, so this is no
> longer needed, and I will remove it in the patch v6;
Ok.
Arnd
^ permalink raw reply
* [PATCH v2] usb: xhci: allow imod-interval to be configurable
From: Chunfeng Yun @ 2017-12-01 3:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1511970775-11103-1-git-send-email-awallis@codeaurora.org>
Hi,
On Wed, 2017-11-29 at 10:52 -0500, Adam Wallis wrote:
> The xHCI driver currently has the IMOD set to 160, which
> translates to an IMOD interval of 40,000ns (160 * 250)ns
>
> Commit 0cbd4b34cda9 ("xhci: mediatek: support MTK xHCI host controller")
> introduced a QUIRK for the MTK platform to adjust this interval to 20,
> which translates to an IMOD interval of 5,000ns (20 * 250)ns. This is
> due to the fact that the MTK controller IMOD interval is 8 times
> as much as defined in xHCI spec.
>
> Instead of adding more quirk bits for additional platforms, this patch
> introduces the ability for vendors to set the IMOD_INTERVAL as is
> optimal for their platform. By using device_property_read_u32() on
> "imod-interval", the IMOD INTERVAL can be specified in nano seconds. If
> no interval is specified, the default of 40,000ns (IMOD=160) will be
> used.
>
> No bounds checking has been implemented due to the fact that a vendor
> may have violated the spec and would need to specify a value outside of
> the max 8,000 IRQs/second limit specified in the xHCI spec.
>
> Backwards compatibility is maintained for MTK_HOSTS through the quirk
> bit, however, imod_interval should be pushed into device tree at a
> future point and this quirk should be removed from xhci_plat_probe
>
> Signed-off-by: Adam Wallis <awallis@codeaurora.org>
> ---
> changes from v1:
> * Removed device_property_read_u32() per suggestion from greg k-h
> * Used ER_IRQ_INTERVAL_MASK in place of (u16) cast
>
> Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
> drivers/usb/host/xhci-plat.c | 13 +++++++++++++
> drivers/usb/host/xhci.c | 7 ++-----
> drivers/usb/host/xhci.h | 2 ++
> 4 files changed, 18 insertions(+), 5 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> index ae6e484..3998459 100644
> --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
> +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
> @@ -29,6 +29,7 @@ Optional properties:
> - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
> - usb3-lpm-capable: determines if platform is USB3 LPM capable
> - quirk-broken-port-ped: set if the controller has broken port disable mechanism
> + - imod-interval: IMOD_INTERVAL in nano-seconds. Default is 40000
>
> Example:
> usb at f0931000 {
> diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
> index 09f164f..3c63de1 100644
> --- a/drivers/usb/host/xhci-plat.c
> +++ b/drivers/usb/host/xhci-plat.c
> @@ -23,6 +23,7 @@
> #include "xhci-plat.h"
> #include "xhci-mvebu.h"
> #include "xhci-rcar.h"
> +#include "xhci-mtk.h"
Needn't it, MTK makes use of xhci-mtk.c but not xhci-plat.c
>
> static struct hc_driver __read_mostly xhci_plat_hc_driver;
>
> @@ -269,6 +270,18 @@ static int xhci_plat_probe(struct platform_device *pdev)
> if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
> xhci->quirks |= XHCI_BROKEN_PORT_PED;
>
> + /*
> + * imod_interval is the interrupt modulation value in nanoseconds.
> + * The increment interval is 8 times as much as that defined in
> + * the xHCI spec on MTK's controller. This quirk check exists to provide
> + * backwards compatibility, however, this should be pushed into
> + * the device tree files at some point in the future and
> + * checking the quirk should be removed from xhci_plat_probe.
> + */
> + xhci->imod_interval = xhci->quirks & XHCI_MTK_HOST ? 5000 : 40000;
Can be moved into xhci-mtk.c for MTK quirk, like as following:
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 2d473e0..a03451b 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -699,6 +699,13 @@ static int xhci_mtk_probe(struct platform_device *pdev)
goto power_off_phys;
}
+ /*
+ * the increment interval is 8 times as much as that defined
+ * in xHCI spec on MTK's controller
+ */
+ xhci->imod_interval = 5000;
+ device_property_read_u32(dev, "imod-interval", &xhci->imod_interval);
+
ret = usb_add_hcd(hcd, irq, IRQF_SHARED);
if (ret)
goto put_usb3_hcd;
Thanks
> +
> + device_property_read_u32(sysdev, "imod-interval", &xhci->imod_interval);
> +
> hcd->usb_phy = devm_usb_get_phy_by_phandle(sysdev, "usb-phy", 0);
> if (IS_ERR(hcd->usb_phy)) {
> ret = PTR_ERR(hcd->usb_phy);
> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
> index 2424d30..0b7755b 100644
> --- a/drivers/usb/host/xhci.c
> +++ b/drivers/usb/host/xhci.c
> @@ -586,11 +586,8 @@ int xhci_run(struct usb_hcd *hcd)
> "// Set the interrupt modulation register");
> temp = readl(&xhci->ir_set->irq_control);
> temp &= ~ER_IRQ_INTERVAL_MASK;
> - /*
> - * the increment interval is 8 times as much as that defined
> - * in xHCI spec on MTK's controller
> - */
> - temp |= (u32) ((xhci->quirks & XHCI_MTK_HOST) ? 20 : 160);
> + temp |= (xhci->imod_interval / 250) & ER_IRQ_INTERVAL_MASK;
> +
> writel(temp, &xhci->ir_set->irq_control);
>
> /* Set the HCD state before we enable the irqs */
> diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
> index 99a014a..2a4177b 100644
> --- a/drivers/usb/host/xhci.h
> +++ b/drivers/usb/host/xhci.h
> @@ -1717,6 +1717,8 @@ struct xhci_hcd {
> u8 max_interrupters;
> u8 max_ports;
> u8 isoc_threshold;
> + /* imod_interval in ns (I * 250ns) */
> + u32 imod_interval;
> int event_ring_max;
> /* 4KB min, 128MB max */
> int page_size;
^ permalink raw reply related
* [PATCH] arm: kernel: utilize hrtimer based broadcast
From: Alison Wang @ 2017-12-01 3:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.11.1601051039320.3689@nanos>
Hi, Russell,
> On Sat, 2 Jan 2016, Russell King - ARM Linux wrote:
> > On Tue, Dec 29, 2015 at 02:54:10PM +0100, Thomas Gleixner wrote:
> > > I have no real opinion about that patch. It does no harm to
> > > unconditionally setup the hrtimer based broadcast even if it's never
> used.
> > >
> > > Up to the arch maintainer to decide.
> >
> > That's really not fair to keep shovelling these kinds of decisions
> > onto architecture maintainers without any kind of explanation about
> > how an architecture maintainer should make such a decision.
> >
> > Do I roll a 6-face dice, and if it gives an odd number, I apply this
> > patch, otherwise I reject it?
> >
> > Is there a technical basis for making the decision? If so, please
> > explain what the technical arguments are against having or not having
> > this change.
>
> The hrtimer based broadcast device is used when you have per cpu timers
> which stop in deeper power states, but you have no other timer hardware on
> the chip which can backup the per cpu timer in deep power states. The
> trick is that it emulates a timer hardware via a hrtimer and then tells
> the cpu idle code not to go into deep power states on the cpu which owns
> that hrtimer. All other cpus can go as deep as they want and still get
> woken up.
>
> The only downside of adding this unconditionally is extra code in case
> that it is not needed on a particular platform.
>
> Hope that helps.
>
[Alison Wang] What's your opinion about this explanation? Is this patch acceptable?
Best Regards,
Alison Wang
^ permalink raw reply
* [PATCH v3 8/9] pwm: pwm-omap-dmtimer: Adapt driver to utilize dmtimer pdata ops
From: Keerthy @ 2017-12-01 4:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7bfa0a0d-27f6-3797-f96b-eeb975158f78@ti.com>
On Friday 01 December 2017 04:49 AM, Grygorii Strashko wrote:
>
>
> On 11/30/2017 03:36 AM, Keerthy wrote:
>>
>>
>> On Tuesday 28 November 2017 11:57 PM, Strashko, Grygorii wrote:
>>>
>>>
>>> On 11/15/2017 10:23 PM, Keerthy wrote:
>>>> Adapt driver to utilize dmtimer pdata ops instead of pdata-quirks.
>>>>
>>>> Signed-off-by: Keerthy <j-keerthy@ti.com>
>>>> ---
>>>>
>>>> Changes in v3:
>>>>
>>>> ??? * Used of_find_platdata_by_node function to fetch platform
>>>> ????? data for timer node.
>>>>
>>>> ?? drivers/pwm/pwm-omap-dmtimer.c | 39
>>>> ++++++++++++++++++++++-----------------
>>>> ?? 1 file changed, 22 insertions(+), 17 deletions(-)
>>>>
>>>> diff --git a/drivers/pwm/pwm-omap-dmtimer.c
>>>> b/drivers/pwm/pwm-omap-dmtimer.c
>>>> index 5ad42f3..2caf46b 100644
>>>> --- a/drivers/pwm/pwm-omap-dmtimer.c
>>>> +++ b/drivers/pwm/pwm-omap-dmtimer.c
>>>> @@ -23,6 +23,7 @@
>>>> ?? #include <linux/mutex.h>
>>>> ?? #include <linux/of.h>
>>>> ?? #include <linux/of_platform.h>
>>>> +#include <linux/platform_data/dmtimer-omap.h>
>>>> ?? #include <linux/platform_data/pwm_omap_dmtimer.h>
>>>> ?? #include <linux/platform_device.h>
>>>> ?? #include <linux/pm_runtime.h>
>>>> @@ -37,7 +38,7 @@ struct pwm_omap_dmtimer_chip {
>>>> ?????? struct pwm_chip chip;
>>>> ?????? struct mutex mutex;
>>>> ?????? pwm_omap_dmtimer *dm_timer;
>>>> -??? struct pwm_omap_dmtimer_pdata *pdata;
>>>> +??? struct omap_dm_timer_ops *pdata;
>>>> ?????? struct platform_device *dm_timer_pdev;
>>>> ?? };
>>>> ?? @@ -242,19 +243,33 @@ static int pwm_omap_dmtimer_probe(struct
>>>> platform_device *pdev)
>>>> ?? {
>>>> ?????? struct device_node *np = pdev->dev.of_node;
>>>> ?????? struct device_node *timer;
>>>> +??? struct platform_device *timer_pdev;
>>>> ?????? struct pwm_omap_dmtimer_chip *omap;
>>>> -??? struct pwm_omap_dmtimer_pdata *pdata;
>>>> +??? struct dmtimer_platform_data *timer_pdata;
>>>> +??? struct omap_dm_timer_ops *pdata;
>>>> ?????? pwm_omap_dmtimer *dm_timer;
>>>> ?????? u32 v;
>>>> ?????? int status;
>>>> ?? -??? pdata = dev_get_platdata(&pdev->dev);
>>>> -??? if (!pdata) {
>>>> -??????? dev_err(&pdev->dev, "Missing dmtimer platform data\n");
>>>> +??? timer = of_parse_phandle(np, "ti,timers", 0);
>>>> +??? if (!timer)
>>>> +??????? return -ENODEV;
>>>> +
>>>> +??? timer_pdev = of_find_device_by_node(timer);
>>>> +??? if (!timer_pdev) {
>>>> +??????? dev_err(&pdev->dev, "Unable to find Timer pdev\n");
>>>> +??????? return -ENODEV;
>>>> +??? }
>>>> +
>>>> +??? timer_pdata = of_find_platdata_by_node(timer);
>>>> +??? if (!timer_pdata) {
>>>> +??????? dev_err(&pdev->dev, "dmtimer pdata structure NULL\n");
>>>> ?????????? return -EINVAL;
>>>> ?????? }
>>>
>>> Huh. I think It might be better if you add smth. like
>>>
>>> struct omap_dm_timer *dm_timer = of_omap_dm_timer_get(parent_np,
>>> "ti,timers", idx);
>>>
>>> struct omap_dm_timer_ops *pdata = omap_dm_timer_get_ops(dm_timer);
>>>
>>> so all DT and platdata implementation details will be hidden.
>>
>> Grygorii,
>>
>> This driver is already fetching:
>>
>> omap->dm_timer_pdev = of_find_device_by_node(timer);
>>
>> It stores dm_timer_pdev in struct pwm_omap_dmtimer_chip.
>> So we already need:
>> timer = of_parse_phandle(np, "ti,timers", 0);
>> and
>> omap->dm_timer_pdev = of_find_device_by_node(timer);
>>
>> So why not just do:
>>
>> struct omap_dm_timer_ops *pdata =
>> omap_dm_timer_get_ops(omap->dm_timer_pdev);
>
> if you dont want to do additional optimizations as part of migration
> might be
> dev_get_platdata(&omap->dm_timer_pdev->dev);
>
> would be enough.
That is pretty much what i want to do with the migration series.
>
> But, again, PWM driver don't need to know so many details about
> DM timer implementation and internal structure as consumer.
Totally understand that. I will follow up with more clean ups once the
code is migrated. Hope that is a reasonable approach.
>
^ permalink raw reply
* [PATCH v4 0/8] omap: dmtimer: Move driver out of plat-omap
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
The series moves dmtimer out of plat-omap to drivers/clocksource.
The series also does a bunch of changes to pwm-omap-dmtimer code
to adapt to the driver migration and clean up plat specific
pdata-quirks and use the dmtimer platform data.
Boot tested on DRA7-EVM and AM437X-GP-EVM.
Compile tested omap1_defconfig.
This is based on top of linux-next branch.
Changes from v3:
* Reverted to v2 approach of using dev_get_platdata to fetch dmtimer ops.
Changes from V2:
* Wrapped the inline functions in header file under OMAP2PLUS
* Added a new of helper function to fetch plat_data from of node.
Keerthy (8):
clocksource: dmtimer: Remove all the exports
arm: omap: timer: Wrap the inline functions under OMAP2PLUS define
arm: omap: Move dmtimer.h out of plat-omap
arm: OMAP: Move dmtimer driver out of plat-omap to drivers under
clocksource
dmtimer: Add timer ops to the platform data structure
clocksource: dmtimer: Populate the timer ops to the pdata
pwm: pwm-omap-dmtimer: Adapt driver to utilize dmtimer pdata ops
arm: omap: pdata-quirks: Remove unused timer pdata
arch/arm/mach-omap1/pm.c | 2 +-
arch/arm/mach-omap1/timer.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 2 +-
arch/arm/mach-omap2/pdata-quirks.c | 32 -------------
arch/arm/mach-omap2/timer.c | 2 +-
arch/arm/plat-omap/Kconfig | 6 ---
arch/arm/plat-omap/Makefile | 1 -
drivers/clocksource/Kconfig | 6 +++
drivers/clocksource/Makefile | 1 +
.../plat-omap => drivers/clocksource}/dmtimer.c | 54 +++++++++++-----------
drivers/pwm/pwm-omap-dmtimer.c | 39 +++++++++-------
.../include/plat => include/clocksource}/dmtimer.h | 8 +++-
include/linux/platform_data/dmtimer-omap.h | 38 +++++++++++++++
20 files changed, 111 insertions(+), 96 deletions(-)
rename {arch/arm/plat-omap => drivers/clocksource}/dmtimer.c (95%)
rename {arch/arm/plat-omap/include/plat => include/clocksource}/dmtimer.h (97%)
--
1.9.1
^ permalink raw reply
* [PATCH v4 1/8] clocksource: dmtimer: Remove all the exports
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
Remove all the unwanted exports from the driver
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
Changes in v3:
* Added Sebastian's Reviewed-by.
Changes in v2:
* No code changes in this v2 version. Only enhanced patch
statistics for renames.
arch/arm/plat-omap/dmtimer.c | 27 ---------------------------
1 file changed, 27 deletions(-)
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index d443e48..72565fc 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -302,7 +302,6 @@ struct omap_dm_timer *omap_dm_timer_request(void)
{
return _omap_dm_timer_request(REQUEST_ANY, NULL);
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request);
struct omap_dm_timer *omap_dm_timer_request_specific(int id)
{
@@ -315,7 +314,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
return _omap_dm_timer_request(REQUEST_BY_ID, &id);
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request_specific);
/**
* omap_dm_timer_request_by_cap - Request a timer by capability
@@ -330,7 +328,6 @@ struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
{
return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_cap);
/**
* omap_dm_timer_request_by_node - Request a timer by device-tree node
@@ -346,7 +343,6 @@ struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
return _omap_dm_timer_request(REQUEST_BY_NODE, np);
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_request_by_node);
int omap_dm_timer_free(struct omap_dm_timer *timer)
{
@@ -359,7 +355,6 @@ int omap_dm_timer_free(struct omap_dm_timer *timer)
timer->reserved = 0;
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_free);
void omap_dm_timer_enable(struct omap_dm_timer *timer)
{
@@ -379,13 +374,11 @@ void omap_dm_timer_enable(struct omap_dm_timer *timer)
}
}
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_enable);
void omap_dm_timer_disable(struct omap_dm_timer *timer)
{
pm_runtime_put_sync(&timer->pdev->dev);
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_disable);
int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
{
@@ -393,7 +386,6 @@ int omap_dm_timer_get_irq(struct omap_dm_timer *timer)
return timer->irq;
return -EINVAL;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_get_irq);
#if defined(CONFIG_ARCH_OMAP1)
#include <mach/hardware.h>
@@ -429,7 +421,6 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
return inputmask;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
#else
@@ -439,7 +430,6 @@ struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
return timer->fclk;
return NULL;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_get_fclk);
__u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
{
@@ -447,7 +437,6 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_modify_idlect_mask);
#endif
@@ -461,7 +450,6 @@ int omap_dm_timer_trigger(struct omap_dm_timer *timer)
omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_trigger);
int omap_dm_timer_start(struct omap_dm_timer *timer)
{
@@ -482,7 +470,6 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
timer->context.tclr = l;
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_start);
int omap_dm_timer_stop(struct omap_dm_timer *timer)
{
@@ -506,7 +493,6 @@ int omap_dm_timer_stop(struct omap_dm_timer *timer)
omap_dm_timer_disable(timer);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_stop);
int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
{
@@ -569,7 +555,6 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
return ret;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_source);
int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
unsigned int load)
@@ -595,7 +580,6 @@ int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
omap_dm_timer_disable(timer);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_load);
/* Optimized set_load which removes costly spin wait in timer_start */
int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
@@ -625,7 +609,6 @@ int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
timer->context.tcrr = load;
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_load_start);
int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
unsigned int match)
@@ -650,7 +633,6 @@ int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
omap_dm_timer_disable(timer);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_match);
int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
int toggle, int trigger)
@@ -676,7 +658,6 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
omap_dm_timer_disable(timer);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_pwm);
int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
{
@@ -699,7 +680,6 @@ int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
omap_dm_timer_disable(timer);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_prescaler);
int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
unsigned int value)
@@ -716,7 +696,6 @@ int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
omap_dm_timer_disable(timer);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_enable);
/**
* omap_dm_timer_set_int_disable - disable timer interrupts
@@ -747,7 +726,6 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
omap_dm_timer_disable(timer);
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_set_int_disable);
unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
{
@@ -762,7 +740,6 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
return l;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_read_status);
int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
{
@@ -773,7 +750,6 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_write_status);
unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
{
@@ -784,7 +760,6 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
return __omap_dm_timer_read_counter(timer, timer->posted);
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_read_counter);
int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
{
@@ -799,7 +774,6 @@ int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
timer->context.tcrr = value;
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timer_write_counter);
int omap_dm_timers_active(void)
{
@@ -816,7 +790,6 @@ int omap_dm_timers_active(void)
}
return 0;
}
-EXPORT_SYMBOL_GPL(omap_dm_timers_active);
static const struct of_device_id omap_timer_match[];
--
1.9.1
^ permalink raw reply related
* [PATCH v4 2/8] arm: omap: timer: Wrap the inline functions under OMAP2PLUS define
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
Wrap the inline functions under OMAP2PLUS/OMAP1 defines.
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
arch/arm/plat-omap/include/plat/dmtimer.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index dd79f30..862ad62 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -276,6 +276,12 @@ struct omap_dm_timer {
#define OMAP_TIMER_TICK_INT_MASK_COUNT_REG \
(_OMAP_TIMER_TICK_INT_MASK_COUNT_OFFSET | (WP_TOWR << WPSHIFT))
+/*
+ * The below are inlined to optimize code size for system timers. Other code
+ * should not need these@all, see
+ * include/linux/platform_data/pwm_omap_dmtimer.h
+ */
+#if defined(CONFIG_ARCH_OMAP1) || defined(CONFIG_ARCH_OMAP2PLUS)
static inline u32 __omap_dm_timer_read(struct omap_dm_timer *timer, u32 reg,
int posted)
{
@@ -414,5 +420,5 @@ static inline void __omap_dm_timer_write_status(struct omap_dm_timer *timer,
{
writel_relaxed(value, timer->irq_stat);
}
-
+#endif /* CONFIG_ARCH_OMAP1 || CONFIG_ARCH_OMAP2PLUS */
#endif /* __ASM_ARCH_DMTIMER_H */
--
1.9.1
^ permalink raw reply related
* [PATCH v4 3/8] arm: omap: Move dmtimer.h out of plat-omap
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
The header file is currently under plat-omap directory
under arch/omap. Move this out to an accessible place.
No Code changes done to the header file.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
Changes in v3:
* Added Sebastian's Reviewed-by.
Changes in v2:
* No code changes in this v2 version. Only enhanced patch
statistics for renames.
arch/arm/mach-omap1/pm.c | 2 +-
arch/arm/mach-omap1/timer.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 +-
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 2 +-
arch/arm/mach-omap2/pdata-quirks.c | 2 +-
arch/arm/mach-omap2/timer.c | 2 +-
arch/arm/plat-omap/dmtimer.c | 2 +-
{arch/arm/plat-omap/include/plat => include/clocksource}/dmtimer.h | 0
14 files changed, 13 insertions(+), 13 deletions(-)
rename {arch/arm/plat-omap/include/plat => include/clocksource}/dmtimer.h (100%)
diff --git a/arch/arm/mach-omap1/pm.c b/arch/arm/mach-omap1/pm.c
index f1135bf..a07d47cf 100644
--- a/arch/arm/mach-omap1/pm.c
+++ b/arch/arm/mach-omap1/pm.c
@@ -55,7 +55,7 @@
#include <mach/tc.h>
#include <mach/mux.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index 8fb1ec6..7c057ab 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -27,7 +27,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "soc.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 1a15a34..45c1043 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -16,7 +16,7 @@
#include <linux/i2c-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 3801850..892ca58 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -18,7 +18,7 @@
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "omap_hwmod.h"
#include "l3_2xxx.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index beec4cd..82b51c0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -11,7 +11,7 @@
#include <linux/platform_data/gpio-omap.h>
#include <linux/omap-dma.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 52c9d58..310aef5 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -25,7 +25,7 @@
#include "l4_3xxx.h"
#include <linux/platform_data/asoc-ti-mcbsp.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "soc.h"
#include "omap_hwmod.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c477096..22e0e38 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,7 +30,7 @@
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
index 988e7ea..530334e 100644
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
@@ -26,7 +26,7 @@
#include <linux/omap-dma.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
index d05e553d..adabdef 100644
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
@@ -26,7 +26,7 @@
#include <linux/omap-dma.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "omap_hwmod.h"
#include "omap_hwmod_common_data.h"
diff --git a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
index 77a515b..d05dd2d 100644
--- a/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_81xx_data.c
@@ -18,7 +18,7 @@
#include <linux/platform_data/gpio-omap.h>
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/spi-omap2-mcspi.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "omap_hwmod_common_data.h"
#include "cm81xx.h"
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 6b433fc..ad9df86 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -27,7 +27,7 @@
#include <linux/platform_data/pwm_omap_dmtimer.h>
#include <linux/platform_data/media/ir-rx51.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
#include "common.h"
#include "common-board-devices.h"
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index ece09c9..31c1b01 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -26,6 +26,7 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
+#include <clocksource/dmtimer.h>
#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
@@ -49,7 +50,6 @@
#include "omap_hwmod.h"
#include "omap_device.h"
#include <plat/counter-32k.h>
-#include <plat/dmtimer.h>
#include "omap-pm.h"
#include "soc.h"
diff --git a/arch/arm/plat-omap/dmtimer.c b/arch/arm/plat-omap/dmtimer.c
index 72565fc..afe1dc9 100644
--- a/arch/arm/plat-omap/dmtimer.c
+++ b/arch/arm/plat-omap/dmtimer.c
@@ -47,7 +47,7 @@
#include <linux/platform_device.h>
#include <linux/platform_data/dmtimer-omap.h>
-#include <plat/dmtimer.h>
+#include <clocksource/dmtimer.h>
static u32 omap_reserved_systimers;
static LIST_HEAD(omap_timer_list);
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/include/clocksource/dmtimer.h
similarity index 100%
rename from arch/arm/plat-omap/include/plat/dmtimer.h
rename to include/clocksource/dmtimer.h
--
1.9.1
^ permalink raw reply related
* [PATCH v4 4/8] arm: OMAP: Move dmtimer driver out of plat-omap to drivers under clocksource
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
Move the dmtimer driver out of plat-omap to clocksource.
So that non-omap devices also could use this.
No Code changes done to the driver file.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
Changes in v3:
* Added Sebastian's Reviewed-by.
Changes in v2:
* No code changes in this v2 version. Only enhanced patch
statistics for renames.
arch/arm/plat-omap/Kconfig | 6 ------
arch/arm/plat-omap/Makefile | 1 -
drivers/clocksource/Kconfig | 6 ++++++
drivers/clocksource/Makefile | 1 +
{arch/arm/plat-omap => drivers/clocksource}/dmtimer.c | 0
5 files changed, 7 insertions(+), 7 deletions(-)
rename {arch/arm/plat-omap => drivers/clocksource}/dmtimer.c (100%)
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index 7276afe..afc1a1d 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -106,12 +106,6 @@ config OMAP3_L2_AUX_SECURE_SERVICE_SET_ID
help
PPA routine service ID for setting L2 auxiliary control register.
-config OMAP_DM_TIMER
- bool "Use dual-mode timer"
- depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
- help
- Select this option if you want to use OMAP Dual-Mode timers.
-
config OMAP_SERIAL_WAKE
bool "Enable wake-up events for serial ports"
depends on ARCH_OMAP1 && OMAP_MUX
diff --git a/arch/arm/plat-omap/Makefile b/arch/arm/plat-omap/Makefile
index 47e1867..7215ada 100644
--- a/arch/arm/plat-omap/Makefile
+++ b/arch/arm/plat-omap/Makefile
@@ -9,5 +9,4 @@ obj-y := sram.o dma.o counter_32k.o
# omap_device support (OMAP2+ only at the moment)
-obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_OMAP_DEBUG_LEDS) += debug-leds.o
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index c729a88..4da66cf 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -46,6 +46,12 @@ config DIGICOLOR_TIMER
help
Enables the support for the digicolor timer driver.
+config OMAP_DM_TIMER
+ bool "Use dual-mode timer"
+ depends on ARCH_OMAP16XX || ARCH_OMAP2PLUS
+ help
+ Select this option if you want to use Dual-Mode timers.
+
config DW_APB_TIMER
bool "DW APB timer driver" if COMPILE_TEST
help
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 72711f1..b077076 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_EM_TIMER_STI) += em_sti.o
obj-$(CONFIG_CLKBLD_I8253) += i8253.o
obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o
+obj-$(CONFIG_OMAP_DM_TIMER) += dmtimer.o
obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o
obj-$(CONFIG_DW_APB_TIMER_OF) += dw_apb_timer_of.o
obj-$(CONFIG_FTTMR010_TIMER) += timer-fttmr010.o
diff --git a/arch/arm/plat-omap/dmtimer.c b/drivers/clocksource/dmtimer.c
similarity index 100%
rename from arch/arm/plat-omap/dmtimer.c
rename to drivers/clocksource/dmtimer.c
--
1.9.1
^ permalink raw reply related
* [PATCH v4 5/8] dmtimer: Add timer ops to the platform data structure
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
Add timer ops to the platform data structure
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
Changes in v3:
* Added Sebastian's Reviewed-by.
Changes in v2:
* No code changes in this v2 version. Only enhanced patch
statistics for renames.
include/linux/platform_data/dmtimer-omap.h | 38 ++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/include/linux/platform_data/dmtimer-omap.h b/include/linux/platform_data/dmtimer-omap.h
index a19b78d..a3e1794 100644
--- a/include/linux/platform_data/dmtimer-omap.h
+++ b/include/linux/platform_data/dmtimer-omap.h
@@ -20,12 +20,50 @@
#ifndef __PLATFORM_DATA_DMTIMER_OMAP_H__
#define __PLATFORM_DATA_DMTIMER_OMAP_H__
+struct omap_dm_timer_ops {
+ struct omap_dm_timer *(*request_by_node)(struct device_node *np);
+ struct omap_dm_timer *(*request_specific)(int timer_id);
+ struct omap_dm_timer *(*request)(void);
+
+ int (*free)(struct omap_dm_timer *timer);
+
+ void (*enable)(struct omap_dm_timer *timer);
+ void (*disable)(struct omap_dm_timer *timer);
+
+ int (*get_irq)(struct omap_dm_timer *timer);
+ int (*set_int_enable)(struct omap_dm_timer *timer,
+ unsigned int value);
+ int (*set_int_disable)(struct omap_dm_timer *timer, u32 mask);
+
+ struct clk *(*get_fclk)(struct omap_dm_timer *timer);
+
+ int (*start)(struct omap_dm_timer *timer);
+ int (*stop)(struct omap_dm_timer *timer);
+ int (*set_source)(struct omap_dm_timer *timer, int source);
+
+ int (*set_load)(struct omap_dm_timer *timer, int autoreload,
+ unsigned int value);
+ int (*set_match)(struct omap_dm_timer *timer, int enable,
+ unsigned int match);
+ int (*set_pwm)(struct omap_dm_timer *timer, int def_on,
+ int toggle, int trigger);
+ int (*set_prescaler)(struct omap_dm_timer *timer, int prescaler);
+
+ unsigned int (*read_counter)(struct omap_dm_timer *timer);
+ int (*write_counter)(struct omap_dm_timer *timer,
+ unsigned int value);
+ unsigned int (*read_status)(struct omap_dm_timer *timer);
+ int (*write_status)(struct omap_dm_timer *timer,
+ unsigned int value);
+};
+
struct dmtimer_platform_data {
/* set_timer_src - Only used for OMAP1 devices */
int (*set_timer_src)(struct platform_device *pdev, int source);
u32 timer_capability;
u32 timer_errata;
int (*get_context_loss_count)(struct device *);
+ struct omap_dm_timer_ops *timer_ops;
};
#endif /* __PLATFORM_DATA_DMTIMER_OMAP_H__ */
--
1.9.1
^ permalink raw reply related
* [PATCH v4 6/8] clocksource: dmtimer: Populate the timer ops to the pdata
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
Add the timer ops to the platform data
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
Changes in v3:
* Added Sebastian's Reviewed-by.
Changes in v2:
* No code changes in this v2 version. Only enhanced patch
statistics for renames.
drivers/clocksource/dmtimer.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/clocksource/dmtimer.c b/drivers/clocksource/dmtimer.c
index afe1dc9..1cbd954 100644
--- a/drivers/clocksource/dmtimer.c
+++ b/drivers/clocksource/dmtimer.c
@@ -922,8 +922,33 @@ static int omap_dm_timer_remove(struct platform_device *pdev)
return ret;
}
+static struct omap_dm_timer_ops dmtimer_ops = {
+ .request_by_node = omap_dm_timer_request_by_node,
+ .request_specific = omap_dm_timer_request_specific,
+ .request = omap_dm_timer_request,
+ .set_source = omap_dm_timer_set_source,
+ .get_irq = omap_dm_timer_get_irq,
+ .set_int_enable = omap_dm_timer_set_int_enable,
+ .set_int_disable = omap_dm_timer_set_int_disable,
+ .free = omap_dm_timer_free,
+ .enable = omap_dm_timer_enable,
+ .disable = omap_dm_timer_disable,
+ .get_fclk = omap_dm_timer_get_fclk,
+ .start = omap_dm_timer_start,
+ .stop = omap_dm_timer_stop,
+ .set_load = omap_dm_timer_set_load,
+ .set_match = omap_dm_timer_set_match,
+ .set_pwm = omap_dm_timer_set_pwm,
+ .set_prescaler = omap_dm_timer_set_prescaler,
+ .read_counter = omap_dm_timer_read_counter,
+ .write_counter = omap_dm_timer_write_counter,
+ .read_status = omap_dm_timer_read_status,
+ .write_status = omap_dm_timer_write_status,
+};
+
static const struct dmtimer_platform_data omap3plus_pdata = {
.timer_errata = OMAP_TIMER_ERRATA_I103_I767,
+ .timer_ops = &dmtimer_ops,
};
static const struct of_device_id omap_timer_match[] = {
--
1.9.1
^ permalink raw reply related
* [PATCH v4 7/8] pwm: pwm-omap-dmtimer: Adapt driver to utilize dmtimer pdata ops
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
Adapt driver to utilize dmtimer pdata ops instead of pdata-quirks.
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
Changes in v4:
* Switched to dev_get_platdata.
Changes in v3:
* Used of_find_platdata_by_node function to fetch platform
data for timer node.
drivers/pwm/pwm-omap-dmtimer.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/drivers/pwm/pwm-omap-dmtimer.c b/drivers/pwm/pwm-omap-dmtimer.c
index 5ad42f3..3b27aff 100644
--- a/drivers/pwm/pwm-omap-dmtimer.c
+++ b/drivers/pwm/pwm-omap-dmtimer.c
@@ -23,6 +23,7 @@
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/of_platform.h>
+#include <linux/platform_data/dmtimer-omap.h>
#include <linux/platform_data/pwm_omap_dmtimer.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
@@ -37,7 +38,7 @@ struct pwm_omap_dmtimer_chip {
struct pwm_chip chip;
struct mutex mutex;
pwm_omap_dmtimer *dm_timer;
- struct pwm_omap_dmtimer_pdata *pdata;
+ struct omap_dm_timer_ops *pdata;
struct platform_device *dm_timer_pdev;
};
@@ -242,19 +243,33 @@ static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct device_node *timer;
+ struct platform_device *timer_pdev;
struct pwm_omap_dmtimer_chip *omap;
- struct pwm_omap_dmtimer_pdata *pdata;
+ struct dmtimer_platform_data *timer_pdata;
+ struct omap_dm_timer_ops *pdata;
pwm_omap_dmtimer *dm_timer;
u32 v;
int status;
- pdata = dev_get_platdata(&pdev->dev);
- if (!pdata) {
- dev_err(&pdev->dev, "Missing dmtimer platform data\n");
+ timer = of_parse_phandle(np, "ti,timers", 0);
+ if (!timer)
+ return -ENODEV;
+
+ timer_pdev = of_find_device_by_node(timer);
+ if (!timer_pdev) {
+ dev_err(&pdev->dev, "Unable to find Timer pdev\n");
+ return -ENODEV;
+ }
+
+ timer_pdata = dev_get_platdata(&timer_pdev->dev);
+ if (!timer_pdata) {
+ dev_err(&pdev->dev, "dmtimer pdata structure NULL\n");
return -EINVAL;
}
- if (!pdata->request_by_node ||
+ pdata = timer_pdata->timer_ops;
+
+ if (!pdata || !pdata->request_by_node ||
!pdata->free ||
!pdata->enable ||
!pdata->disable ||
@@ -270,10 +285,6 @@ static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
return -EINVAL;
}
- timer = of_parse_phandle(np, "ti,timers", 0);
- if (!timer)
- return -ENODEV;
-
if (!of_get_property(timer, "ti,timer-pwm", NULL)) {
dev_err(&pdev->dev, "Missing ti,timer-pwm capability\n");
return -ENODEV;
@@ -291,13 +302,7 @@ static int pwm_omap_dmtimer_probe(struct platform_device *pdev)
omap->pdata = pdata;
omap->dm_timer = dm_timer;
-
- omap->dm_timer_pdev = of_find_device_by_node(timer);
- if (!omap->dm_timer_pdev) {
- dev_err(&pdev->dev, "Unable to find timer pdev\n");
- omap->pdata->free(dm_timer);
- return -EINVAL;
- }
+ omap->dm_timer_pdev = timer_pdev;
/*
* Ensure that the timer is stopped before we allow PWM core to call
--
1.9.1
^ permalink raw reply related
* [PATCH v4 8/8] arm: omap: pdata-quirks: Remove unused timer pdata
From: Keerthy @ 2017-12-01 5:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512105397-2544-1-git-send-email-j-keerthy@ti.com>
Remove unused timer pdata.
Signed-off-by: Keerthy <j-keerthy@ti.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.co.uk>
---
Changes in v3:
* Added Sebastian's Reviewed-by.
Changes in v2:
* No code changes in this v2 version. Only enhanced patch
statistics for renames.
arch/arm/mach-omap2/pdata-quirks.c | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index ad9df86..e7d7fc7 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -24,10 +24,8 @@
#include <linux/platform_data/hsmmc-omap.h>
#include <linux/platform_data/iommu-omap.h>
#include <linux/platform_data/wkup_m3.h>
-#include <linux/platform_data/pwm_omap_dmtimer.h>
#include <linux/platform_data/media/ir-rx51.h>
#include <linux/platform_data/asoc-ti-mcbsp.h>
-#include <clocksource/dmtimer.h>
#include "common.h"
#include "common-board-devices.h"
@@ -477,33 +475,6 @@ void omap_auxdata_legacy_init(struct device *dev)
dev->platform_data = &twl_gpio_auxdata;
}
-/* Dual mode timer PWM callbacks platdata */
-#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
-static struct pwm_omap_dmtimer_pdata pwm_dmtimer_pdata = {
- .request_by_node = omap_dm_timer_request_by_node,
- .request_specific = omap_dm_timer_request_specific,
- .request = omap_dm_timer_request,
- .set_source = omap_dm_timer_set_source,
- .get_irq = omap_dm_timer_get_irq,
- .set_int_enable = omap_dm_timer_set_int_enable,
- .set_int_disable = omap_dm_timer_set_int_disable,
- .free = omap_dm_timer_free,
- .enable = omap_dm_timer_enable,
- .disable = omap_dm_timer_disable,
- .get_fclk = omap_dm_timer_get_fclk,
- .start = omap_dm_timer_start,
- .stop = omap_dm_timer_stop,
- .set_load = omap_dm_timer_set_load,
- .set_match = omap_dm_timer_set_match,
- .set_pwm = omap_dm_timer_set_pwm,
- .set_prescaler = omap_dm_timer_set_prescaler,
- .read_counter = omap_dm_timer_read_counter,
- .write_counter = omap_dm_timer_write_counter,
- .read_status = omap_dm_timer_read_status,
- .write_status = omap_dm_timer_write_status,
-};
-#endif
-
static struct ir_rx51_platform_data __maybe_unused rx51_ir_data = {
.set_max_mpu_wakeup_lat = omap_pm_set_max_mpu_wakeup_lat,
};
@@ -572,9 +543,6 @@ static void __init omap3_mcbsp_init(void) {}
OF_DEV_AUXDATA("ti,am4372-wkup-m3", 0x44d00000, "44d00000.wkup_m3",
&wkup_m3_data),
#endif
-#if IS_ENABLED(CONFIG_OMAP_DM_TIMER)
- OF_DEV_AUXDATA("ti,omap-dmtimer-pwm", 0, NULL, &pwm_dmtimer_pdata),
-#endif
#if defined(CONFIG_ARCH_OMAP4) || defined(CONFIG_SOC_OMAP5)
OF_DEV_AUXDATA("ti,omap4-iommu", 0x4a066000, "4a066000.mmu",
&omap4_iommu_pdata),
--
1.9.1
^ permalink raw reply related
* [PATCH] arm64: dts: msm8916: Correct ipc references for smsm
From: Bjorn Andersson @ 2017-12-01 5:27 UTC (permalink / raw)
To: linux-arm-kernel
SMSM is not symmetrical, the incoming bits from WCNSS are available at
index 6, but the outgoing host id for WCNSS is 3. Further more, upstream
references the base of APCS (in contrast to downstream), so the register
offset of 8 must be included.
Fixes: 1fb47e0a9ba4 ("arm64: dts: qcom: msm8916: Add smsm and smp2p nodes")
Cc: stable at vger.kernel.org
Reported-by: Ramon Fried <rfried@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 9fb317853a5c..a8e1e3b4562c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1437,8 +1437,8 @@
#address-cells = <1>;
#size-cells = <0>;
- qcom,ipc-1 = <&apcs 0 13>;
- qcom,ipc-6 = <&apcs 0 19>;
+ qcom,ipc-1 = <&apcs 8 13>;
+ qcom,ipc-3 = <&apcs 8 19>;
apps_smsm: apps at 0 {
reg = <0>;
--
2.15.0
^ permalink raw reply related
* [PATCH v2 00/27] Improve DE2 support
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
Current DE2 driver is very basic and uses a lot of magic constants since
there is no documentation and knowledge about it was limited at the time.
With studying BSP source code, deeper knowledge was gained which allows
to improve mainline driver considerably.
At the beginning of this series, some code refactoring is done as well
as adding some checks (patches 1-15).
Further patches add multi-plane support with HW scaling and all possible
RGB formats (patches 16-21).
At last, support for YUV formats is added (patches 22-26).
At the end, I included patch which puts lowest plane before second lowest.
This should help testing VI planes when mixer has configuration 1 VI plane
and 1 or more UI planes (most SoCs except V3s).
This code was developed on H3, but it should work on every SoC if correct
configuration structure is provided.
H3 code can be found here:
https://github.com/jernejsk/linux-1/commits/de2_impr_for_next
Best regards,
Jernej
Changes from v1:
- Split two patches to multiple smaller ones and better explain why those
changes are needed and added fixes tag where appropriate.
- channel parameters represents HW better (layer id -> channel, overlay)
- add kerneldoc to configuration structure
- nicer code style in atomic_check functions
- changed WARN() to DRM_WARN() in csc code
- split common scaler file to separate ui and vi scaler files
- move channel specific code out of mixer code to sun8i_ui_layer.c and
sun8i_vi_layer.c
- defined macros for min and max supported scaler factor for each type
of scaler
Jernej Skrabec (27):
drm/sun4i: Fix format mask in DE2 driver
drm/sun4i: Rename DE2 RGB format macros
drm/sun4i: Remove setting alpha mode in DE2 driver
drm/sun4i: Fix debug message in DE2
drm/sun4i: Remove setting default values in DE2 driver
drm/sun4i: Explain color macro in DE2 driver
drm/sun4i: Set blending mode for all channels (DE2)
drm/sun4i: Rename some macros in DE2 driver
drm/sun4i: Rework enabling plane in DE2 driver
drm/sun4i: Start using layer id in DE2 driver
drm/sun4i: Add constraints checking to DE2 driver
drm/sun4i: Use values calculated by atomic check
drm/sun4i: Move line width setting in DE2
drm/sun4i: Move channel size related code in DE2
drm/sun4i: Move interlace related code in DE2
drm/sun4i: Add multi plane support to DE2 driver
drm/sun4i: Add support for all HW supported DE2 RGB formats
drm/sun4i: Reorganize UI layer code in DE2
drm/sun4i: Add support for DE2 VI planes
drm/sun4i: Add scaler configuration to DE2 mixers
drm/sun4i: Add support for HW scaling to DE2
drm/sun4i: Add CCSC property to DE2 configuration
drm/sun4i: Add DE2 CSC library
drm/sun4i: Add DE2 definitions for YUV formats
drm/sun4i: Expand DE2 scaler lib with YUV support
drm/sun4i: Wire in DE2 YUV support
[DO NOT MERGE]drm/sun4i: Change zpos of bottom VI plane
drivers/gpu/drm/sun4i/Makefile | 4 +-
drivers/gpu/drm/sun4i/sun8i_csc.c | 93 +++
drivers/gpu/drm/sun4i/sun8i_csc.h | 36 ++
drivers/gpu/drm/sun4i/sun8i_layer.c | 134 -----
drivers/gpu/drm/sun4i/sun8i_layer.h | 36 --
drivers/gpu/drm/sun4i/sun8i_mixer.c | 496 +++++++++-------
drivers/gpu/drm/sun4i/sun8i_mixer.h | 123 ++--
drivers/gpu/drm/sun4i/sun8i_ui_layer.c | 351 ++++++++++++
drivers/gpu/drm/sun4i/sun8i_ui_layer.h | 63 +++
drivers/gpu/drm/sun4i/sun8i_ui_scaler.c | 172 ++++++
drivers/gpu/drm/sun4i/sun8i_ui_scaler.h | 49 ++
drivers/gpu/drm/sun4i/sun8i_vi_layer.c | 389 +++++++++++++
drivers/gpu/drm/sun4i/sun8i_vi_layer.h | 51 ++
drivers/gpu/drm/sun4i/sun8i_vi_scaler.c | 971 ++++++++++++++++++++++++++++++++
drivers/gpu/drm/sun4i/sun8i_vi_scaler.h | 58 ++
15 files changed, 2595 insertions(+), 431 deletions(-)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_csc.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_csc.h
delete mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.c
delete mode 100644 drivers/gpu/drm/sun4i/sun8i_layer.h
create mode 100644 drivers/gpu/drm/sun4i/sun8i_ui_layer.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_ui_layer.h
create mode 100644 drivers/gpu/drm/sun4i/sun8i_ui_scaler.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_ui_scaler.h
create mode 100644 drivers/gpu/drm/sun4i/sun8i_vi_layer.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_vi_layer.h
create mode 100644 drivers/gpu/drm/sun4i/sun8i_vi_scaler.c
create mode 100644 drivers/gpu/drm/sun4i/sun8i_vi_scaler.h
--
2.15.1
^ permalink raw reply
* [PATCH v2 01/27] drm/sun4i: Fix format mask in DE2 driver
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
Format mask is one bit too short. Fix it.
Fixes: 9d75b8c0b999 (drm/sun4i: add support for Allwinner DE2 mixers)
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 4785ac090b8c..c142fbb8661e 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -80,7 +80,7 @@
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN BIT(0)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK GENMASK(11, 8)
+#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_DEF (1 << 1)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_ARGB8888 (0 << 8)
--
2.15.1
^ permalink raw reply related
* [PATCH v2 02/27] drm/sun4i: Rename DE2 RGB format macros
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
Current RGB formats macros are actually not specific to UI planes.
Rename it to something more universal and introduce shift macro.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 7 ++++---
drivers/gpu/drm/sun4i/sun8i_mixer.h | 8 +++++---
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index cb193c5f1686..b9c48c60131f 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -71,15 +71,15 @@ static int sun8i_mixer_drm_format_to_layer(struct drm_plane *plane,
{
switch (format) {
case DRM_FORMAT_ARGB8888:
- *mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_ARGB8888;
+ *mode = SUN8I_MIXER_FBFMT_ARGB8888;
break;
case DRM_FORMAT_XRGB8888:
- *mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_XRGB8888;
+ *mode = SUN8I_MIXER_FBFMT_XRGB8888;
break;
case DRM_FORMAT_RGB888:
- *mode = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888;
+ *mode = SUN8I_MIXER_FBFMT_RGB888;
break;
default:
@@ -173,6 +173,7 @@ int sun8i_mixer_update_layer_formats(struct sun8i_mixer *mixer,
return ret;
}
+ val <<= SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET;
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val);
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index c142fbb8661e..82c3416fbf3a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -81,13 +81,15 @@
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN BIT(0)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK GENMASK(2, 1)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
+#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET 8
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_DEF (1 << 1)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_ARGB8888 (0 << 8)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_XRGB8888 (4 << 8)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_RGB888 (8 << 8)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF (0xff << 24)
+#define SUN8I_MIXER_FBFMT_ARGB8888 0
+#define SUN8I_MIXER_FBFMT_XRGB8888 4
+#define SUN8I_MIXER_FBFMT_RGB888 8
+
/*
* These sub-engines are still unknown now, the EN registers are here only to
* be used to disable these sub-engines.
--
2.15.1
^ permalink raw reply related
* [PATCH v2 03/27] drm/sun4i: Remove setting alpha mode in DE2 driver
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
Current code sets alpha mode to global alpha mode and global alpha
value to 0xff which is totaly opaque. That is not needed for two
reasons:
- only one plane is active and thus it can be blended only with
background, which is black,
- it will hinder proper blending when more than one plane is supported
Default mode (0) considers pixel alpha value or 0xff if pixel has
no alpha information. Global alpha value is ignored in this case.
Because of that, just remove the code.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 10 ----------
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 --
2 files changed, 12 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index b9c48c60131f..d3dee6131209 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -54,16 +54,6 @@ void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer,
regmap_update_bits(mixer->engine.regs,
SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val);
-
- /* Set the alpha configuration */
- regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_DEF);
- regmap_update_bits(mixer->engine.regs,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR(chan, layer),
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK,
- SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF);
}
static int sun8i_mixer_drm_format_to_layer(struct drm_plane *plane,
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 82c3416fbf3a..a7fe013c1d4a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -83,8 +83,6 @@
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK GENMASK(12, 8)
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET 8
#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK GENMASK(31, 24)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_DEF (1 << 1)
-#define SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_DEF (0xff << 24)
#define SUN8I_MIXER_FBFMT_ARGB8888 0
#define SUN8I_MIXER_FBFMT_XRGB8888 4
--
2.15.1
^ permalink raw reply related
* [PATCH v2 04/27] drm/sun4i: Fix debug message in DE2
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
Debug message would print "Enabling" even when disabling plane.
Fix it.
Fixes: 9d75b8c0b999 (drm/sun4i: add support for Allwinner DE2 mixers)
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index d3dee6131209..b947ee2e4fe4 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -44,7 +44,8 @@ void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer,
/* Currently the first UI channel is used */
int chan = mixer->cfg->vi_num;
- DRM_DEBUG_DRIVER("Enabling layer %d in channel %d\n", layer, chan);
+ DRM_DEBUG_DRIVER("%sabling layer %d in channel %d\n",
+ enable ? "En" : "Dis", layer, chan);
if (enable)
val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN;
--
2.15.1
^ permalink raw reply related
* [PATCH v2 05/27] drm/sun4i: Remove setting default values in DE2 driver
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
Premultiply and color key control registers are already set to zero by
initialization code few lines above. Furthermore, it seems that
colorkeying doesn't really work. It's not used in BSP driver and
experiments with it all failed.
Just remove the code.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 4 ----
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 --
2 files changed, 6 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index b947ee2e4fe4..f4a7fa0ba7ad 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -320,14 +320,10 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
/* Initialize blender */
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_FCOLOR_CTL,
SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF);
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PREMULTIPLY,
- SUN8I_MIXER_BLEND_PREMULTIPLY_DEF);
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR,
SUN8I_MIXER_BLEND_BKCOLOR_DEF);
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(0),
SUN8I_MIXER_BLEND_MODE_DEF);
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_CK_CTL,
- SUN8I_MIXER_BLEND_CK_CTL_DEF);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index a7fe013c1d4a..db005a4bca43 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -48,10 +48,8 @@
/* The following numbers are some still unknown magic numbers */
#define SUN8I_MIXER_BLEND_ATTR_FCOLOR_DEF 0xff000000
#define SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF 0x00000101
-#define SUN8I_MIXER_BLEND_PREMULTIPLY_DEF 0x0
#define SUN8I_MIXER_BLEND_BKCOLOR_DEF 0xff000000
#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
-#define SUN8I_MIXER_BLEND_CK_CTL_DEF 0x0
#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
--
2.15.1
^ permalink raw reply related
* [PATCH v2 06/27] drm/sun4i: Explain color macro in DE2 driver
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
Color attribute have same format troughout the whole driver.
Rename macro, add comment with simple explanation and remove redundant
definitions.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 8 +++++---
drivers/gpu/drm/sun4i/sun8i_mixer.h | 4 ++--
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index f4a7fa0ba7ad..5144e6d0ac56 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -317,17 +317,19 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL,
SUN8I_MIXER_GLOBAL_CTL_RT_EN);
+ /* Set background color to black */
+ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR,
+ SUN8I_MIXER_BLEND_COLOR_BLACK);
+
/* Initialize blender */
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_FCOLOR_CTL,
SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF);
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR,
- SUN8I_MIXER_BLEND_BKCOLOR_DEF);
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(0),
SUN8I_MIXER_BLEND_MODE_DEF);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
- SUN8I_MIXER_BLEND_ATTR_FCOLOR_DEF);
+ SUN8I_MIXER_BLEND_COLOR_BLACK);
/* Select the first UI channel */
DRM_DEBUG_DRIVER("Selecting channel %d (first UI channel)\n",
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index db005a4bca43..9b50733298b8 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -45,10 +45,10 @@
#define SUN8I_MIXER_BLEND_CK_MIN(x) (0x10e0 + 0x04 * (x))
#define SUN8I_MIXER_BLEND_OUTCTL 0x10fc
+/* colors are always in AARRGGBB format */
+#define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
/* The following numbers are some still unknown magic numbers */
-#define SUN8I_MIXER_BLEND_ATTR_FCOLOR_DEF 0xff000000
#define SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF 0x00000101
-#define SUN8I_MIXER_BLEND_BKCOLOR_DEF 0xff000000
#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
--
2.15.1
^ permalink raw reply related
* [PATCH v2 07/27] drm/sun4i: Set blending mode for all channels (DE2)
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
BSP driver always sets blend mode for all channels, no matter if they
are really used or not. Do the same here.
The exact meaning of the value is not exactly known, but BSP driver
mentions "SRC OVER" and by digging through code some more info can be
found.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 5144e6d0ac56..23659ce1cf27 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -239,6 +239,7 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
struct sun8i_mixer *mixer;
struct resource *res;
void __iomem *regs;
+ int plane_cnt;
int i, ret;
/*
@@ -324,8 +325,6 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
/* Initialize blender */
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_FCOLOR_CTL,
SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF);
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(0),
- SUN8I_MIXER_BLEND_MODE_DEF);
regmap_write(mixer->engine.regs,
SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
@@ -337,6 +336,11 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ROUTE,
mixer->cfg->vi_num);
+ plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num;
+ for (i = 0; i < plane_cnt; i++)
+ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_MODE(i),
+ SUN8I_MIXER_BLEND_MODE_DEF);
+
return 0;
err_disable_bus_clk:
--
2.15.1
^ permalink raw reply related
* [PATCH v2 08/27] drm/sun4i: Rename some macros in DE2 driver
From: Jernej Skrabec @ 2017-12-01 6:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201060550.10392-1-jernej.skrabec@siol.net>
Now that some knowledge of DE2 is gained, rename or add some macros to
make code more readable.
Max channel macro is removed, since it is not used and it is not clear
if it has right value. Structures in BSP driver shows possibility of 5
channels maximum although there is no SoC with such configuration.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 5 +++--
drivers/gpu/drm/sun4i/sun8i_mixer.h | 13 ++++++-------
2 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 23659ce1cf27..c7d4ccd605e0 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -323,8 +323,9 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
SUN8I_MIXER_BLEND_COLOR_BLACK);
/* Initialize blender */
- regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_FCOLOR_CTL,
- SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF);
+ regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL,
+ SUN8I_MIXER_BLEND_PIPE_CTL_EN(0) |
+ SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0));
regmap_write(mixer->engine.regs,
SUN8I_MIXER_BLEND_ATTR_FCOLOR(0),
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index 9b50733298b8..76f0b2bd91e2 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -16,8 +16,6 @@
#include "sunxi_engine.h"
-#define SUN8I_MIXER_MAX_CHAN_COUNT 4
-
#define SUN8I_MIXER_SIZE(w, h) (((h) - 1) << 16 | ((w) - 1))
#define SUN8I_MIXER_COORD(x, y) ((y) << 16 | (x))
@@ -26,14 +24,14 @@
#define SUN8I_MIXER_GLOBAL_DBUFF 0x8
#define SUN8I_MIXER_GLOBAL_SIZE 0xc
-#define SUN8I_MIXER_GLOBAL_CTL_RT_EN 0x1
+#define SUN8I_MIXER_GLOBAL_CTL_RT_EN BIT(0)
-#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE 0x1
+#define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE BIT(0)
-#define SUN8I_MIXER_BLEND_FCOLOR_CTL 0x1000
+#define SUN8I_MIXER_BLEND_PIPE_CTL 0x1000
#define SUN8I_MIXER_BLEND_ATTR_FCOLOR(x) (0x1004 + 0x10 * (x) + 0x0)
#define SUN8I_MIXER_BLEND_ATTR_INSIZE(x) (0x1004 + 0x10 * (x) + 0x4)
-#define SUN8I_MIXER_BLEND_ATTR_OFFSET(x) (0x1004 + 0x10 * (x) + 0x8)
+#define SUN8I_MIXER_BLEND_ATTR_COORD(x) (0x1004 + 0x10 * (x) + 0x8)
#define SUN8I_MIXER_BLEND_ROUTE 0x1080
#define SUN8I_MIXER_BLEND_PREMULTIPLY 0x1084
#define SUN8I_MIXER_BLEND_BKCOLOR 0x1088
@@ -45,10 +43,11 @@
#define SUN8I_MIXER_BLEND_CK_MIN(x) (0x10e0 + 0x04 * (x))
#define SUN8I_MIXER_BLEND_OUTCTL 0x10fc
+#define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
+#define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe) BIT(pipe)
/* colors are always in AARRGGBB format */
#define SUN8I_MIXER_BLEND_COLOR_BLACK 0xff000000
/* The following numbers are some still unknown magic numbers */
-#define SUN8I_MIXER_BLEND_FCOLOR_CTL_DEF 0x00000101
#define SUN8I_MIXER_BLEND_MODE_DEF 0x03010301
#define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
--
2.15.1
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