* [PATCH 0/5] crypto: arm64 - disable NEON across scatterwalk API calls
From: Ard Biesheuvel @ 2017-12-04 9:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171202135952.GX3326@worktop>
On 2 December 2017 at 13:59, Peter Zijlstra <peterz@infradead.org> wrote:
> On Sat, Dec 02, 2017 at 11:15:14AM +0000, Ard Biesheuvel wrote:
>> On 2 December 2017 at 09:11, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>
>> > They consume the entire input in a single go, yes. But making it more
>> > granular than that is going to hurt performance, unless we introduce
>> > some kind of kernel_neon_yield(), which does a end+begin but only if
>> > the task is being scheduled out.
>> >
>> > For example, the SHA256 keeps 256 bytes of round constants in NEON
>> > registers, and reloading those from memory for each 64 byte block of
>> > input is going to be noticeable. The same applies to the AES code
>> > (although the numbers are slightly different)
>>
>> Something like below should do the trick I think (apologies for the
>> patch soup). I.e., check TIF_NEED_RESCHED at a point where only very
>> few NEON registers are live, and preserve/restore the live registers
>> across calls to kernel_neon_end + kernel_neon_begin. Would that work
>> for RT?
>
> Probably yes. The important point is that preempt latencies (and thus by
> extension NEON regions) are bounded and preferably small.
>
> Unbounded stuff (like depends on the amount of data fed) are a complete
> no-no for RT since then you cannot make predictions on how long things
> will take.
>
OK, that makes sense. But I do wonder what the parameters should be here.
For instance, the AES instructions on ARMv8 operate at <1 cycle per
byte, and so checking the TIF_NEED_RESCHED flag for every iteration of
the inner loop (i.e., every 64 bytes ~ 64 cycles) is clearly going to
be noticeable, and is probably overkill. The pure NEON version (which
is instantiated from the same block mode wrappers) uses ~25 cycles per
byte, and the bit sliced NEON version runs at ~20 cycles per byte but
can only operate at 8 blocks (128 bytes) at a time.
So rather than simply polling the bit@each iteration of the inner
loop in each algorithm, I'd prefer to aim for a ballpark number of
cycles to execute, in the order 1000 - 2000. Would that be OK or too
coarse?
^ permalink raw reply
* [PATCH] ARM64: dts: meson-gx: fix UART pclk clock name
From: Neil Armstrong @ 2017-12-04 9:04 UTC (permalink / raw)
To: linux-arm-kernel
The clock-names for pclk was wrongly set to "core", but the bindings
specifies "pclk".
This was not cathed until the legacy non-documented bindings were removed.
Reported-by: Andreas F?rber <afaerber@suse.de>
Fixes: f72d6f6037b7 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 4 ++--
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 +++---
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index ead895a..1fb8b9d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -753,12 +753,12 @@
&uart_B {
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
- clock-names = "xtal", "core", "baud";
+ clock-names = "xtal", "pclk", "baud";
};
&uart_C {
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
- clock-names = "xtal", "core", "baud";
+ clock-names = "xtal", "pclk", "baud";
};
&vpu {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index 8ed981f..6524b89 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -688,7 +688,7 @@
&uart_A {
clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
- clock-names = "xtal", "core", "baud";
+ clock-names = "xtal", "pclk", "baud";
};
&uart_AO {
@@ -703,12 +703,12 @@
&uart_B {
clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
- clock-names = "xtal", "core", "baud";
+ clock-names = "xtal", "pclk", "baud";
};
&uart_C {
clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
- clock-names = "xtal", "core", "baud";
+ clock-names = "xtal", "pclk", "baud";
};
&vpu {
--
2.7.4
^ permalink raw reply related
* [PATCH v4 08/10] mfd: axp20x: add pinctrl cell for AXP813
From: Lee Jones @ 2017-12-04 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZJ3gDqnLVW0NZMJiF7qRJSu-0Usys0tKfT-aep4bRxjg@mail.gmail.com>
On Sat, 02 Dec 2017, Linus Walleij wrote:
> On Fri, Dec 1, 2017 at 2:44 PM, Quentin Schulz
> <quentin.schulz@free-electrons.com> wrote:
>
> > As GPIO/pinctrl driver now supports AXP813, add a cell for it.
> >
> > Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
> > Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
>
> Acked-by: Linus Walleij <linus.walleij@linaro.org>
>
> It doesn't seem to have any dependencies so I guess Lee can simply
> apply this separately.
Yup! Although, I'd prefer to wait for the other patches in the set to
be applied. In the mean time:
For my own reference:
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH 6/6] ARM: configs: keystone_defconfig: Enable few peripheral drivers
From: Vignesh R @ 2017-12-04 9:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fb0c662b-d462-c663-7cf0-443ace3565ba@oracle.com>
Hi,
On Sunday 03 December 2017 09:30 AM, santosh.shilimkar at oracle.com wrote:
> On 11/22/17 11:51 PM, Vignesh R wrote:
>> Enable drivers for QSPI, LEDS, gpio-decoder that are present on 66AK2G
>> EVM
>> and 66AK2G ICE boards.
>>
>> Signed-off-by: Vignesh R <vigneshr@ti.com>
>> ---
> Please submit a patch also to enable all these peripherals
> in multi-v7 config. Just enable all remainder
> options enabled in keystone config also in multi-v7.
K2 Platforms don't boot out of multi_v7_defconfig by default, because K2
platforms require CONFIG_ARM_LPAE(which is disabled in multi-v7).
If the intention is to just have all drivers enabled in
keystone_defconfig to be added to multi_v7, I can prepare a patch for
that and test with local patch to enable LPAE.
>
> Am pushing this series to next now.
>
Thanks!
--
Regards
Vignesh
^ permalink raw reply
* [PATCH v6 13/13] ASoC: stm32: add DFSDM DAI support
From: Arnaud Pouliquen @ 2017-12-04 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171202150952.1b5f3bfd@archlinux>
On 12/02/2017 04:09 PM, Jonathan Cameron wrote:
> On Fri, 1 Dec 2017 18:40:20 +0100
> Arnaud Pouliquen <arnaud.pouliquen@st.com> wrote:
>
>> Add driver to handle DAI interface for PDM microphones connected
>> to Digital Filter for Sigma Delta Modulators IP.
>>
>> Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@st.com>
>
> include tied up with the move of that enum in the earlier patch.
> Other than that the IIO stuff looks fine to me.
>
> Mark, given this set is moderately invasive on the IIO side and
> should just drop in cleanly on the sound side of things, either
> I could take it via IIO or one of us can do an immutable branch
> and we take it through both trees.
Don't know if you saw the reply from Mark on V5:
"This is basically fine, if someone could send me a pull request and the
relevant patches when the IIO stuff is sorted out I'll give it a final
check and apply then."
>
> Don't mind which but if I'm either taking the series or doing
> an immutable branch I'll obviously be waiting on your review!
>
> Also need time for Rob to check the updating bindings.
>
> Anyhow, it's coming together reasonably nicely in the end.
> Good work Arnaud!
Thanks! it will be a good achievement for me, not trivial this
peripheral to integrate :)
I'm waiting Rob's ack or remarks on patch 12/13 to send the next version.
Thanks and Regards
Arnaud
>
> Jonathan
>> ---
>> V5 to V6 update:
>>? fix build warning
>>?
>>? sound/soc/stm/Kconfig??????? |? 11 ++
>>? sound/soc/stm/Makefile?????? |?? 3 +
>>? sound/soc/stm/stm32_adfsdm.c | 386 +++++++++++++++++++++++++++++++++++++++++++
>>? 3 files changed, 400 insertions(+)
>>? create mode 100644 sound/soc/stm/stm32_adfsdm.c
>>
>> diff --git a/sound/soc/stm/Kconfig b/sound/soc/stm/Kconfig
>> index 3398e6c..a78f770 100644
>> --- a/sound/soc/stm/Kconfig
>> +++ b/sound/soc/stm/Kconfig
>> @@ -28,4 +28,15 @@ config SND_SOC_STM32_SPDIFRX
>>??????? help
>>????????? Say Y if you want to enable S/PDIF capture for STM32
>>?
>> +config SND_SOC_STM32_DFSDM
>> +???? tristate "SoC Audio support for STM32 DFSDM"
>> +???? depends on (ARCH_STM32 && OF && STM32_DFSDM_ADC) || COMPILE_TEST
>> +???? depends on SND_SOC
>> +???? select SND_SOC_GENERIC_DMAENGINE_PCM
>> +???? select SND_SOC_DMIC
>> +???? select IIO_BUFFER_CB
>> +???? help
>> +?????? Select this option to enable the STM32 Digital Filter
>> +?????? for Sigma Delta Modulators (DFSDM) driver used
>> +?????? in various STM32 series for digital microphone capture.
>>? endmenu
>> diff --git a/sound/soc/stm/Makefile b/sound/soc/stm/Makefile
>> index 4ed22e6..53e90e6 100644
>> --- a/sound/soc/stm/Makefile
>> +++ b/sound/soc/stm/Makefile
>> @@ -12,3 +12,6 @@ obj-$(CONFIG_SND_SOC_STM32_I2S) += snd-soc-stm32-i2s.o
>>? # SPDIFRX
>>? snd-soc-stm32-spdifrx-objs := stm32_spdifrx.o
>>? obj-$(CONFIG_SND_SOC_STM32_SPDIFRX) += snd-soc-stm32-spdifrx.o
>> +
>> +#DFSDM
>> +obj-$(CONFIG_SND_SOC_STM32_DFSDM) += stm32_adfsdm.o
>> diff --git a/sound/soc/stm/stm32_adfsdm.c b/sound/soc/stm/stm32_adfsdm.c
>> new file mode 100644
>> index 0000000..890ec24
>> --- /dev/null
>> +++ b/sound/soc/stm/stm32_adfsdm.c
>> @@ -0,0 +1,386 @@
>> +/*
>> + * This file is part of STM32 DFSDM ASoC DAI driver
>> + *
>> + * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
>> + * Authors: Arnaud Pouliquen <arnaud.pouliquen@st.com>
>> + *????????? Olivier Moysan <olivier.moysan@st.com>
>> + *
>> + * License terms: GPL V2.0.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms of the GNU General Public License version 2 as published by
>> + * the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful, but
>> + * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
>> + * or FITNESS FOR A PARTICULAR PURPOSE.
>> + * See the GNU General Public License for more details.
>> + *
>> + * You should have received a copy of the GNU General Public License along with
>> + * this program. If not, see <http://www.gnu.org/licenses/>.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/module.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/slab.h>
>> +
>> +#include <linux/iio/iio.h>
>
> I missed this before but a consumer should not need to include iio.h.
> I would guess it was about that enum that I want you to move to types.h?
>
>> +#include <linux/iio/consumer.h>
>> +#include <linux/iio/adc/stm32-dfsdm-adc.h>
>> +
>> +#include <sound/pcm.h>
>> +#include <sound/soc.h>
>> +
>> +#define STM32_ADFSDM_DRV_NAME "stm32-adfsdm"
>> +
>> +#define DFSDM_MAX_PERIOD_SIZE??????? (PAGE_SIZE / 2)
>> +#define DFSDM_MAX_PERIODS??? 6
>> +
>> +struct stm32_adfsdm_priv {
>> +???? struct snd_soc_dai_driver dai_drv;
>> +???? struct snd_pcm_substream *substream;
>> +???? struct device *dev;
>> +
>> +???? /* IIO */
>> +???? struct iio_channel *iio_ch;
>> +???? struct iio_cb_buffer *iio_cb;
>> +???? bool iio_active;
>> +
>> +???? /* PCM buffer */
>> +???? unsigned char *pcm_buff;
>> +???? unsigned int pos;
>> +???? bool allocated;
>> +};
>> +
>> +struct stm32_adfsdm_data {
>> +???? unsigned int rate;????? /* SNDRV_PCM_RATE value */
>> +???? unsigned int freq;????? /* frequency in Hz */
>> +};
>> +
>> +static const struct snd_pcm_hardware stm32_adfsdm_pcm_hw = {
>> +???? .info = SNDRV_PCM_INFO_INTERLEAVED | SNDRV_PCM_INFO_BLOCK_TRANSFER |
>> +???????? SNDRV_PCM_INFO_PAUSE,
>> +???? .formats = SNDRV_PCM_FMTBIT_S32_LE,
>> +
>> +???? .rate_min = 8000,
>> +???? .rate_max = 32000,
>> +
>> +???? .channels_min = 1,
>> +???? .channels_max = 1,
>> +
>> +???? .periods_min = 2,
>> +???? .periods_max = DFSDM_MAX_PERIODS,
>> +
>> +???? .period_bytes_max = DFSDM_MAX_PERIOD_SIZE,
>> +???? .buffer_bytes_max = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE
>> +};
>> +
>> +static void stm32_adfsdm_shutdown(struct snd_pcm_substream *substream,
>> +?????????????????????????????? struct snd_soc_dai *dai)
>> +{
>> +???? struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
>> +
>> +???? if (priv->iio_active) {
>> +???????????? iio_channel_stop_all_cb(priv->iio_cb);
>> +???????????? priv->iio_active = false;
>> +???? }
>> +}
>> +
>> +static int stm32_adfsdm_dai_prepare(struct snd_pcm_substream *substream,
>> +???????????????????????????????? struct snd_soc_dai *dai)
>> +{
>> +???? struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
>> +???? int ret;
>> +
>> +???? ret = iio_write_channel_attribute(priv->iio_ch,
>> +?????????????????????????????????????? substream->runtime->rate, 0,
>> +?????????????????????????????????????? IIO_CHAN_INFO_SAMP_FREQ);
>> +???? if (ret < 0) {
>> +???????????? dev_err(dai->dev, "%s: Failed to set %d sampling rate\n",
>> +???????????????????? __func__, substream->runtime->rate);
>> +???????????? return ret;
>> +???? }
>> +
>> +???? if (!priv->iio_active) {
>> +???????????? ret = iio_channel_start_all_cb(priv->iio_cb);
>> +???????????? if (!ret)
>> +???????????????????? priv->iio_active = true;
>> +???????????? else
>> +???????????????????? dev_err(dai->dev, "%s: IIO channel start failed (%d)\n",
>> +???????????????????????????? __func__, ret);
>> +???? }
>> +
>> +???? return ret;
>> +}
>> +
>> +static int stm32_adfsdm_set_sysclk(struct snd_soc_dai *dai, int clk_id,
>> +??????????????????????????????? unsigned int freq, int dir)
>> +{
>> +???? struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(dai);
>> +???? ssize_t size;
>> +
>> +???? dev_dbg(dai->dev, "%s: Enter for freq %d\n", __func__, freq);
>> +
>> +???? /* Set IIO frequency if CODEC is master as clock comes from SPI_IN*/
>> +???? if (dir == SND_SOC_CLOCK_IN) {
>> +???????????? char str_freq[10];
>> +
>> +???????????? snprintf(str_freq, sizeof(str_freq), "%d\n", freq);
>> +???????????? size = iio_write_channel_ext_info(priv->iio_ch, "spi_clk_freq",
>> +?????????????????????????????????????????????? str_freq, sizeof(str_freq));
>> +???????????? if (size != sizeof(str_freq)) {
>> +???????????????????? dev_err(dai->dev, "%s: Failed to set SPI clock\n",
>> +???????????????????????????? __func__);
>> +???????????????????? return -EINVAL;
>> +???????????? }
>> +???? }
>> +???? return 0;
>> +}
>> +
>> +static const struct snd_soc_dai_ops stm32_adfsdm_dai_ops = {
>> +???? .shutdown = stm32_adfsdm_shutdown,
>> +???? .prepare = stm32_adfsdm_dai_prepare,
>> +???? .set_sysclk = stm32_adfsdm_set_sysclk,
>> +};
>> +
>> +static const struct snd_soc_dai_driver stm32_adfsdm_dai = {
>> +???? .capture = {
>> +???????????????? .channels_min = 1,
>> +???????????????? .channels_max = 1,
>> +???????????????? .formats = SNDRV_PCM_FMTBIT_S32_LE,
>> +???????????????? .rates = (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |
>> +?????????????????????????? SNDRV_PCM_RATE_32000),
>> +???????????????? },
>> +???? .ops = &stm32_adfsdm_dai_ops,
>> +};
>> +
>> +static const struct snd_soc_component_driver stm32_adfsdm_dai_component = {
>> +???? .name = "stm32_dfsdm_audio",
>> +};
>> +
>> +static int stm32_afsdm_pcm_cb(const void *data, size_t size, void *private)
>> +{
>> +???? struct stm32_adfsdm_priv *priv = private;
>> +???? struct snd_soc_pcm_runtime *rtd = priv->substream->private_data;
>> +???? u8 *pcm_buff = priv->pcm_buff;
>> +???? u8 *src_buff = (u8 *)data;
>> +???? unsigned int buff_size = snd_pcm_lib_buffer_bytes(priv->substream);
>> +???? unsigned int period_size = snd_pcm_lib_period_bytes(priv->substream);
>> +???? unsigned int old_pos = priv->pos;
>> +???? unsigned int cur_size = size;
>> +
>> +???? dev_dbg(rtd->dev, "%s: buff_add :%p, pos = %d, size = %lu\n",
>> +???????????? __func__, &pcm_buff[priv->pos], priv->pos, size);
>> +
>> +???? if ((priv->pos + size) > buff_size) {
>> +???????????? memcpy(&pcm_buff[priv->pos], src_buff, buff_size - priv->pos);
>> +???????????? cur_size -= buff_size - priv->pos;
>> +???????????? priv->pos = 0;
>> +???? }
>> +
>> +???? memcpy(&pcm_buff[priv->pos], &src_buff[size - cur_size], cur_size);
>> +???? priv->pos = (priv->pos + cur_size) % buff_size;
>> +
>> +???? if (cur_size != size || (old_pos && (old_pos % period_size < size)))
>> +???????????? snd_pcm_period_elapsed(priv->substream);
>> +
>> +???? return 0;
>> +}
>> +
>> +static int stm32_adfsdm_trigger(struct snd_pcm_substream *substream, int cmd)
>> +{
>> +???? struct snd_soc_pcm_runtime *rtd = substream->private_data;
>> +???? struct stm32_adfsdm_priv *priv =
>> +???????????? snd_soc_dai_get_drvdata(rtd->cpu_dai);
>> +
>> +???? switch (cmd) {
>> +???? case SNDRV_PCM_TRIGGER_START:
>> +???? case SNDRV_PCM_TRIGGER_RESUME:
>> +???????????? priv->pos = 0;
>> +???????????? return stm32_dfsdm_get_buff_cb(priv->iio_ch->indio_dev,
>> +???????????????????????????????????? stm32_afsdm_pcm_cb, priv);
>> +???? case SNDRV_PCM_TRIGGER_SUSPEND:
>> +???? case SNDRV_PCM_TRIGGER_STOP:
>> +???????????? return stm32_dfsdm_release_buff_cb(priv->iio_ch->indio_dev);
>> +???? default:
>> +???????????? return -EINVAL;
>> +???? }
>> +
>> +???? return 0;
>> +}
>> +
>> +static int stm32_adfsdm_pcm_open(struct snd_pcm_substream *substream)
>> +{
>> +???? struct snd_soc_pcm_runtime *rtd = substream->private_data;
>> +???? struct stm32_adfsdm_priv *priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
>> +???? int ret;
>> +
>> +???? ret =? snd_soc_set_runtime_hwparams(substream, &stm32_adfsdm_pcm_hw);
>> +???? if (!ret)
>> +???????????? priv->substream = substream;
>> +
>> +???? return ret;
>> +}
>> +
>> +static int stm32_adfsdm_pcm_close(struct snd_pcm_substream *substream)
>> +{
>> +???? struct snd_soc_pcm_runtime *rtd = substream->private_data;
>> +???? struct stm32_adfsdm_priv *priv =
>> +???????????? snd_soc_dai_get_drvdata(rtd->cpu_dai);
>> +
>> +???? snd_pcm_lib_free_pages(substream);
>> +???? priv->substream = NULL;
>> +
>> +???? return 0;
>> +}
>> +
>> +static snd_pcm_uframes_t stm32_adfsdm_pcm_pointer(
>> +???????????????????????????????????????? struct snd_pcm_substream *substream)
>> +{
>> +???? struct snd_soc_pcm_runtime *rtd = substream->private_data;
>> +???? struct stm32_adfsdm_priv *priv =
>> +???????????? snd_soc_dai_get_drvdata(rtd->cpu_dai);
>> +
>> +???? return bytes_to_frames(substream->runtime, priv->pos);
>> +}
>> +
>> +static int stm32_adfsdm_pcm_hw_params(struct snd_pcm_substream *substream,
>> +?????????????????????????????????? struct snd_pcm_hw_params *params)
>> +{
>> +???? struct snd_soc_pcm_runtime *rtd = substream->private_data;
>> +???? struct stm32_adfsdm_priv *priv =
>> +???????????? snd_soc_dai_get_drvdata(rtd->cpu_dai);
>> +???? int ret;
>> +
>> +???? ret =? snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(params));
>> +???? if (ret < 0)
>> +???????????? return ret;
>> +???? priv->pcm_buff = substream->runtime->dma_area;
>> +
>> +???? return iio_channel_cb_set_buffer_watermark(priv->iio_cb,
>> +??????????????????????????????????????????????? params_period_size(params));
>> +}
>> +
>> +static int stm32_adfsdm_pcm_hw_free(struct snd_pcm_substream *substream)
>> +{
>> +???? snd_pcm_lib_free_pages(substream);
>> +
>> +???? return 0;
>> +}
>> +
>> +static struct snd_pcm_ops stm32_adfsdm_pcm_ops = {
>> +???? .open?????????? = stm32_adfsdm_pcm_open,
>> +???? .close????????? = stm32_adfsdm_pcm_close,
>> +???? .hw_params????? = stm32_adfsdm_pcm_hw_params,
>> +???? .hw_free??????? = stm32_adfsdm_pcm_hw_free,
>> +???? .trigger??????? = stm32_adfsdm_trigger,
>> +???? .pointer??????? = stm32_adfsdm_pcm_pointer,
>> +};
>> +
>> +static int stm32_adfsdm_pcm_new(struct snd_soc_pcm_runtime *rtd)
>> +{
>> +???? struct snd_pcm *pcm = rtd->pcm;
>> +???? struct stm32_adfsdm_priv *priv =
>> +???????????? snd_soc_dai_get_drvdata(rtd->cpu_dai);
>> +???? unsigned int size = DFSDM_MAX_PERIODS * DFSDM_MAX_PERIOD_SIZE;
>> +???? int ret;
>> +
>> +???? /*
>> +????? * FIXME :
>> +????? * A platform as been registered per DAI.
>> +????? * In soc_new_pcm function, pcm_new callback is called for each
>> +????? * component of the sound card. So if n dai links are created this
>> +????? * function is called n times.
>> +????? */
>> +???? if (priv->allocated)
>> +???????????? return 0;
>> +
>> +???? ret = snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
>> +???????????????????????????????????????????????? priv->dev, size, size);
>> +???? if (!ret)
>> +???????????? priv->allocated = true;
>> +
>> +???? return ret;
>> +}
>> +
>> +static void stm32_adfsdm_pcm_free(struct snd_pcm *pcm)
>> +{
>> +???? struct snd_pcm_substream *substream;
>> +???? struct snd_soc_pcm_runtime *rtd;
>> +???? struct stm32_adfsdm_priv *priv;
>> +
>> +???? substream = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream;
>> +???? if (substream) {
>> +???????????? rtd = substream->private_data;
>> +???????????? priv = snd_soc_dai_get_drvdata(rtd->cpu_dai);
>> +
>> +???????????? snd_pcm_lib_preallocate_free_for_all(pcm);
>> +???????????? priv->allocated = false;
>> +???? }
>> +}
>> +
>> +static struct snd_soc_platform_driver stm32_adfsdm_soc_platform = {
>> +???? .ops??????????? = &stm32_adfsdm_pcm_ops,
>> +???? .pcm_new??????? = stm32_adfsdm_pcm_new,
>> +???? .pcm_free?????? = stm32_adfsdm_pcm_free,
>> +};
>> +
>> +static const struct of_device_id stm32_adfsdm_of_match[] = {
>> +???? {.compatible = "st,stm32h7-dfsdm-dai"},
>> +???? {}
>> +};
>> +MODULE_DEVICE_TABLE(of, stm32_adfsdm_of_match);
>> +
>> +static int stm32_adfsdm_probe(struct platform_device *pdev)
>> +{
>> +???? struct stm32_adfsdm_priv *priv;
>> +???? int ret;
>> +
>> +???? priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
>> +???? if (!priv)
>> +???????????? return -ENOMEM;
>> +
>> +???? priv->dev = &pdev->dev;
>> +???? priv->dai_drv = stm32_adfsdm_dai;
>> +
>> +???? dev_set_drvdata(&pdev->dev, priv);
>> +
>> +???? ret = devm_snd_soc_register_component(&pdev->dev,
>> +?????????????????????????????????????????? &stm32_adfsdm_dai_component,
>> +?????????????????????????????????????????? &priv->dai_drv, 1);
>> +???? if (ret < 0)
>> +???????????? return ret;
>> +
>> +???? /* Associate iio channel */
>> +???? priv->iio_ch? = devm_iio_channel_get_all(&pdev->dev);
>> +???? if (IS_ERR(priv->iio_ch))
>> +???????????? return PTR_ERR(priv->iio_ch);
>> +
>> +???? priv->iio_cb = iio_channel_get_all_cb(&pdev->dev, NULL, NULL);
>> +???? if (IS_ERR(priv->iio_cb))
>> +???????????? return PTR_ERR(priv->iio_ch);
>> +
>> +???? ret = devm_snd_soc_register_platform(&pdev->dev,
>> +????????????????????????????????????????? &stm32_adfsdm_soc_platform);
>> +???? if (ret < 0)
>> +???????????? dev_err(&pdev->dev, "%s: Failed to register PCM platform\n",
>> +???????????????????? __func__);
>> +
>> +???? return ret;
>> +}
>> +
>> +static struct platform_driver stm32_adfsdm_driver = {
>> +???? .driver = {
>> +??????????????? .name = STM32_ADFSDM_DRV_NAME,
>> +??????????????? .of_match_table = stm32_adfsdm_of_match,
>> +??????????????? },
>> +???? .probe = stm32_adfsdm_probe,
>> +};
>> +
>> +module_platform_driver(stm32_adfsdm_driver);
>> +
>> +MODULE_DESCRIPTION("stm32 DFSDM DAI driver");
>> +MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_ALIAS("platform:" STM32_ADFSDM_DRV_NAME);
>
^ permalink raw reply
* [PATCH v3] usb: xhci: allow imod-interval to be configurable
From: Mathias Nyman @ 2017-12-04 8:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512271374.17567.164.camel@mhfsdcap03>
On 03.12.2017 05:22, Chunfeng Yun wrote:
> On Fri, 2017-12-01 at 10:44 -0500, Adam Wallis wrote:
>> The xHCI driver currently has the IMOD set to 160, which
>> translates to an IMOD interval of 40,000ns (160 * 250)ns
>>
>> Commit 0cbd4b34cda9 ("xhci: mediatek: support MTK xHCI host controller")
>> introduced a QUIRK for the MTK platform to adjust this interval to 20,
>> which translates to an IMOD interval of 5,000ns (20 * 250)ns. This is
>> due to the fact that the MTK controller IMOD interval is 8 times
>> as much as defined in xHCI spec.
>>
>> Instead of adding more quirk bits for additional platforms, this patch
>> introduces the ability for vendors to set the IMOD_INTERVAL as is
>> optimal for their platform. By using device_property_read_u32() on
>> "imod-interval", the IMOD INTERVAL can be specified in nano seconds. If
>> no interval is specified, the default of 40,000ns (IMOD=160) will be
>> used.
>>
>> No bounds checking has been implemented due to the fact that a vendor
>> may have violated the spec and would need to specify a value outside of
>> the max 8,000 IRQs/second limit specified in the xHCI spec.
>>
>> Signed-off-by: Adam Wallis <awallis@codeaurora.org>
>> ---
>> changes from v2:
>> * Added PCI default value [Mathias]
>> * Removed xhci-mtk.h from xhci-plat.c [Chunfeng Yun]
>> * Removed MTK quirk from xhci-plat and moved logic to xhci-mtk [Chunfeng]
>> * Updated bindings Documentation to use proper units [Rob Herring]
>> * Added imod-interval description and example to MTK binding documentation
>> changes from v1:
>> * Removed device_property_read_u32() per suggestion from greg k-h
>> * Used ER_IRQ_INTERVAL_MASK in place of (u16) cast
>>
>> Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt | 2 ++
>> Documentation/devicetree/bindings/usb/usb-xhci.txt | 1 +
>> drivers/usb/host/xhci-mtk.c | 9 +++++++++
>> drivers/usb/host/xhci-pci.c | 3 +++
>> drivers/usb/host/xhci-plat.c | 4 ++++
>> drivers/usb/host/xhci.c | 7 ++-----
>> drivers/usb/host/xhci.h | 2 ++
>> 7 files changed, 23 insertions(+), 5 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
>> index 3059596..45bbf18 100644
>> --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
>> +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.txt
>> @@ -46,6 +46,7 @@ Optional properties:
>> - pinctrl-names : a pinctrl state named "default" must be defined
>> - pinctrl-0 : pin control group
>> See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
>> + - imod-interval: Default interval is 5000ns
> I think, as Rob suggested before, recommend to have a unit suffix
> appended to the property name.
> s/imod-interval/imod-interval-ns
>
>>
>> Example:
>> usb30: usb at 11270000 {
>> @@ -66,6 +67,7 @@ usb30: usb at 11270000 {
>> usb3-lpm-capable;
>> mediatek,syscon-wakeup = <&pericfg>;
>> mediatek,wakeup-src = <1>;
>> + imod-interval = <10000>;
>> };
>>
>> 2nd: dual-role mode with xHCI driver
>> diff --git a/Documentation/devicetree/bindings/usb/usb-xhci.txt b/Documentation/devicetree/bindings/usb/usb-xhci.txt
>> index ae6e484..89b68f1 100644
>> --- a/Documentation/devicetree/bindings/usb/usb-xhci.txt
>> +++ b/Documentation/devicetree/bindings/usb/usb-xhci.txt
>> @@ -29,6 +29,7 @@ Optional properties:
>> - usb2-lpm-disable: indicate if we don't want to enable USB2 HW LPM
>> - usb3-lpm-capable: determines if platform is USB3 LPM capable
>> - quirk-broken-port-ped: set if the controller has broken port disable mechanism
>> + - imod-interval: Default interval is 40000ns
>>
>> Example:
>> usb at f0931000 {
>> diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
>> index b62a1d2..278ea3b 100644
>> --- a/drivers/usb/host/xhci-mtk.c
>> +++ b/drivers/usb/host/xhci-mtk.c
>> @@ -674,6 +674,15 @@ static int xhci_mtk_probe(struct platform_device *pdev)
>>
>> xhci = hcd_to_xhci(hcd);
>> xhci->main_hcd = hcd;
>> +
>> + /*
>> + * imod_interval is the interrupt modulation value in nanoseconds.
>> + * The increment interval is 8 times as much as that defined in
>> + * the xHCI spec on MTK's controller.
>> + */
>> + xhci->imod_interval = 5000;
>> + device_property_read_u32(dev, "imod-interval", &xhci->imod_interval);
>> +
>> xhci->shared_hcd = usb_create_shared_hcd(driver, dev,
>> dev_name(dev), hcd);
>> if (!xhci->shared_hcd) {
>> diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
>> index 7ef1274..efbe57b 100644
>> --- a/drivers/usb/host/xhci-pci.c
>> +++ b/drivers/usb/host/xhci-pci.c
>> @@ -234,6 +234,9 @@ static int xhci_pci_setup(struct usb_hcd *hcd)
>> if (!xhci->sbrn)
>> pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
>>
>> + /* imod_interval is the interrupt modulation value in nanoseconds. */
>> + xhci->imod_interval = 40000;
>> +
>> retval = xhci_gen_setup(hcd, xhci_pci_quirks);
>> if (retval)
>> return retval;
>> diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
>> index 09f164f..b78be87 100644
>> --- a/drivers/usb/host/xhci-plat.c
>> +++ b/drivers/usb/host/xhci-plat.c
>> @@ -269,6 +269,10 @@ static int xhci_plat_probe(struct platform_device *pdev)
>> if (device_property_read_bool(&pdev->dev, "quirk-broken-port-ped"))
>> xhci->quirks |= XHCI_BROKEN_PORT_PED;
>>
>> + /* imod_interval is the interrupt modulation value in nanoseconds. */
>> + xhci->imod_interval = 40000;
>> + device_property_read_u32(sysdev, "imod-interval", &xhci->imod_interval);
>> +
>> hcd->usb_phy = devm_usb_get_phy_by_phandle(sysdev, "usb-phy", 0);
>> if (IS_ERR(hcd->usb_phy)) {
>> ret = PTR_ERR(hcd->usb_phy);
>> diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
>> index 2424d30..0b7755b 100644
>> --- a/drivers/usb/host/xhci.c
>> +++ b/drivers/usb/host/xhci.c
>> @@ -586,11 +586,8 @@ int xhci_run(struct usb_hcd *hcd)
>> "// Set the interrupt modulation register");
Just noticed the driver has all the time incorrectly used the word "modulation" instead
of "moderation".
If you do the bindings change that Chunfeng pointed out above could you also change
the "modulation" to "moderation" in this patch.
Don't worry about changing the old ones. There's a cleanup patch on its way that
will remove most of them anyway.
Otherwise the xhci parts look good to me.
-Mathias
^ permalink raw reply
* [PATCH v5.1 1/2] ARM64: dts: meson-gx: use stable UART bindings with correct gate clock
From: Neil Armstrong @ 2017-12-04 8:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <61a59a32-a812-cc88-79f9-02c13f1901d7@suse.de>
On 04/12/2017 01:16, Andreas F?rber wrote:
> Am 03.12.2017 um 15:15 schrieb Andreas F?rber:
>> Hi,
>>
>> Am 21.06.2017 um 16:42 schrieb Neil Armstrong:
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
>>> index 17d3efd..ea53cc2 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
>>> @@ -682,6 +682,31 @@
>>> clocks = <&clkc CLKID_SPI>;
>>> };
>>>
>>> +&uart_A {
>>> + clocks = <&xtal>, <&clkc CLKID_UART0>, <&xtal>;
>>> + clock-names = "xtal", "pclk", "baud";
>>> +};
>>> +
>>> +&uart_AO {
>>> + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
>>> + clock-names = "xtal", "pclk", "baud";
>>> +};
>>> +
>>> +&uart_AO_B {
>>> + clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
>>> + clock-names = "xtal", "pclk", "baud";
>>> +};
>>> +
>>> +&uart_B {
>>> + clocks = <&xtal>, <&clkc CLKID_UART1>, <&xtal>;
>>> + clock-names = "xtal", "core", "baud";
>>
>> Looking at the meson_uart driver, it only looks for a "pclk" clock,
>> never for "core", and the only unnamed clock used should be the first.
>>
>> There is no bindings documentation for "core", so I assume this was an
>> oversight and should be "pclk" everywhere?
>>
>>> +};
>>> +
>>> +&uart_C {
>>> + clocks = <&xtal>, <&clkc CLKID_UART2>, <&xtal>;
>>> + clock-names = "xtal", "core", "baud";
>>> +};
>>
>> The issue I'm facing is that uart_C on NanoPi K2 is not working in
>> 4.14.1. To my surprise it appears to be probing okay though.
>
> In 4.14 the serial driver checks for the legacy compatible and if
> present (even alongside the new compatible) always takes the legacy code
> path, using only the first clock, thus not tripping over "core" and not
> enabling the "pclk" if supplied.
I only used UART_A, this explains a lot.
>
> This was changed for v4.15-rc1, so we should start seeing errors for
> missing "pclk" clocks.
>
>> Sadly just overwriting the clock-names property via overlay does not fix
>> my issue. Any ideas?
You need to rebind the devices.
>
> For reference here's my latest overlay, overriding compatible, too:
> https://github.com/afaerber/dt-overlays/blob/master/meson-gxbb-nanopi-k2%2Barpi600%2Bnucleo-lrwan1.dts
>
> Regards,
> Andreas
>
Wow I must have been very tired when pushing this....
Thanks for spotting this.
I'll send a fix asap.
Neil
^ permalink raw reply
* [PATCH] ARM: dts: sunxi: Convert to CCU index macros for HDMI controller
From: Chen-Yu Tsai @ 2017-12-04 8:44 UTC (permalink / raw)
To: linux-arm-kernel
When the HDMI controller device node was added, the needed PLL clock
macros were not exported. A separate patch addresses that, but it is
merged through a different tree.
Now that both patches are in mainline proper, we can convert the raw
numbers to proper macros.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
---
This is the remain bits of the HDMI series, converting raw index
numbers in the device tree to ccu macros. This is a fix for 4.15.
I've put all the platforms in one patch, though we should have done
sun5i for the previous release.
---
arch/arm/boot/dts/sun4i-a10.dtsi | 4 ++--
arch/arm/boot/dts/sun5i-a10s.dtsi | 4 ++--
arch/arm/boot/dts/sun6i-a31.dtsi | 4 ++--
arch/arm/boot/dts/sun7i-a20.dtsi | 4 ++--
4 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index b91300d49a31..5840f5c75c3b 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -502,8 +502,8 @@
reg = <0x01c16000 0x1000>;
interrupts = <58>;
clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
- <&ccu 9>,
- <&ccu 18>;
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "pll-0", "pll-1";
dmas = <&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_NORMAL 16>,
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 6ae4d95e230e..316cb8b2945b 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -82,8 +82,8 @@
reg = <0x01c16000 0x1000>;
interrupts = <58>;
clocks = <&ccu CLK_AHB_HDMI>, <&ccu CLK_HDMI>,
- <&ccu 9>,
- <&ccu 16>;
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "pll-0", "pll-1";
dmas = <&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_NORMAL 16>,
diff --git a/arch/arm/boot/dts/sun6i-a31.dtsi b/arch/arm/boot/dts/sun6i-a31.dtsi
index 8bfa12b548e0..72d3fe44ecaf 100644
--- a/arch/arm/boot/dts/sun6i-a31.dtsi
+++ b/arch/arm/boot/dts/sun6i-a31.dtsi
@@ -429,8 +429,8 @@
interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB1_HDMI>, <&ccu CLK_HDMI>,
<&ccu CLK_HDMI_DDC>,
- <&ccu 7>,
- <&ccu 13>;
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "ddc", "pll-0", "pll-1";
resets = <&ccu RST_AHB1_HDMI>;
reset-names = "ahb";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 68dfa82544fc..59655e42e4b0 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -581,8 +581,8 @@
reg = <0x01c16000 0x1000>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ccu CLK_AHB_HDMI0>, <&ccu CLK_HDMI>,
- <&ccu 9>,
- <&ccu 18>;
+ <&ccu CLK_PLL_VIDEO0_2X>,
+ <&ccu CLK_PLL_VIDEO1_2X>;
clock-names = "ahb", "mod", "pll-0", "pll-1";
dmas = <&dma SUN4I_DMA_NORMAL 16>,
<&dma SUN4I_DMA_NORMAL 16>,
--
2.15.0
^ permalink raw reply related
* [PATCH 2/6] cpufreq: ARM: sort the Kconfig menu
From: Viresh Kumar @ 2017-12-04 8:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201112508.14121-3-gregory.clement@free-electrons.com>
On 01-12-17, 12:25, Gregory CLEMENT wrote:
> +config ARM_VEXPRESS_SPC_CPUFREQ
> + tristate "Versatile Express SPC based CPUfreq driver"
> + depends on ARM_BIG_LITTLE_CPUFREQ && ARCH_VEXPRESS_SPC
> + help
> + This add the CPUfreq driver support for Versatile Express
> + big.LITTLE platforms using SPC for power management.
> +
> +config ARM_SCPI_CPUFREQ
The order of above two must be reversed ?
--
viresh
^ permalink raw reply
* [PATCH v2 0/4] ARM: dts: renesas: Convert to named i2c-gpio bindings
From: Simon Horman @ 2017-12-04 8:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201110908.u7xjrt7xmlqgigvy@ninjato>
On Fri, Dec 01, 2017 at 12:09:08PM +0100, Wolfram Sang wrote:
> On Fri, Dec 01, 2017 at 09:18:55AM +0100, Simon Horman wrote:
> > On Thu, Nov 30, 2017 at 01:57:22PM +0100, Geert Uytterhoeven wrote:
> > > Hi Simon, Magnus,
> > >
> > > Commits 7d29f509d2cfd807 ("dt-bindings: i2c: i2c-gpio: Add support for
> > > named gpios") and 05c74778858d7d99 ("i2c: gpio: Add support for named
> > > gpios in DT") introduced named i2c-gpio DT bindings, and deprecated the
> > > more error-prone unnamed variant.
> > >
> > > This patch series switches all Renesas boards to the new bindings, and
> > > adds the missing GPIO_OPEN_DRAIN I/O flags, which were implicitly
> > > assumed before. The latter gets rid of messages like:
> > >
> > > gpio-208 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
> > > gpio-91 (?): enforced open drain please flag it properly in DT/ACPI DSDT/board file
> > >
> > > Patch 1 was extracted from series "[PATCH/RFC 0/3] i2c: gpio: Add
> > > support for named gpios in DT", hence the v2. All other patches are
> > > new.
> > >
> > > Note that after this series is applied, the i2c-gpio buses are no longer
> > > detected when booting new DTBs on old (v4.14 and older) kernels, which
> > > should not be an issue. Booting old DTBs on new kernels is not
> > > affected.
> > >
> > > Thanks for applying!
> >
> > Thanks, applied.
>
> Phew, you guys are fast. For the record:
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Thanks, I'll see about adding your tag.
^ permalink raw reply
* [PATCH 3/9] ASoC: sun8i-codec: Add quirk to specify aif1_lrck_div value
From: Chen-Yu Tsai @ 2017-12-04 8:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65KMosNgkCa5Ddmf_T--8-BeLLjdqrdX3wb4H+kbudLjA@mail.gmail.com>
On Mon, Dec 4, 2017 at 3:38 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Mon, Dec 4, 2017 at 4:41 AM, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>> LRCK divider for A64 differs from A33, so add a quirk to support that.
>>
>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>> ---
>> sound/soc/sunxi/sun8i-codec.c | 38 ++++++++++++++++++++++++++++++++------
>> 1 file changed, 32 insertions(+), 6 deletions(-)
>>
>> diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
>> index 3dd183be08a4..054201d1de03 100644
>> --- a/sound/soc/sunxi/sun8i-codec.c
>> +++ b/sound/soc/sunxi/sun8i-codec.c
>> @@ -24,6 +24,7 @@
>> #include <linux/io.h>
>> #include <linux/pm_runtime.h>
>> #include <linux/regmap.h>
>> +#include <linux/of_device.h>
>
> Please keep them sorted in alphabetical order.
>
>>
>> #include <sound/pcm_params.h>
>> #include <sound/soc.h>
>> @@ -75,11 +76,22 @@
>> #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
>> #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
>>
>> +/*
>> + * struct sun8i_codec_quirks - Differences between SoC variants.
>> + *
>> + * @aif1_lrck_div: LRCK divider
>> + */
>> +struct sun8i_codec_quirks {
>> + unsigned int aif1_lrck_div;
>> +};
>> +
>> +
>> struct sun8i_codec {
>> - struct device *dev;
>> - struct regmap *regmap;
>> - struct clk *clk_module;
>> - struct clk *clk_bus;
>> + struct device *dev;
>> + struct regmap *regmap;
>> + struct clk *clk_module;
>> + struct clk *clk_bus;
>> + const struct sun8i_codec_quirks *variant;
>> };
>>
>> static int sun8i_codec_runtime_resume(struct device *dev)
>> @@ -305,7 +317,7 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
>>
>> regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
>> SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
>> - SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
>> + scodec->variant->aif1_lrck_div);
>
> Hard coding a fixed divider is generally a bad idea.
> You adding another fixed value for this is evidence of this.
>
> The BCK:LRCK divider is equal to sample width * 2. You should
> have that instead.
>
> Also I see no evidence that either the I2S controller (see my
> comment on patch 1) or the codec is limited to a certain sample
> width in hardware, other than your claims, which are vague at
> best.
>
> The user manual for both the A33 and A64 list many possible
> widths and dividers. If the user manual is wrong, please provide
> solid evidence proving it wrong.
>
> Either way this series will not be accepted in its current form.
So following up on the discussion on IRC, please add the relevant
information to the commit messages:
- Why is this hard-coded value needed? i.e. does it not work with
standard values generated by the framework from the format value?
This is the most important part. This might also include:
* What you have done to test the non-working values
Other things worth mentioning:
- Where the hard-coded values came from?
- Why a special quirk is needed, instead of say, limiting the
supported format to SNDRV_PCM_FMTBIT_S32_LE, which produces
the correct wss and lrck_div values
- Anything else you think is relevant to the patch or hardware
You should also leave a comment explaining why the quirk is needed
just before the code where you handle the quirks. Otherwise it makes
little sense to people that don't have the context about this.
Regards
ChenYu
>
> ChenYu
>
>>
>> sample_rate = sun8i_codec_get_hw_rate(params);
>> if (sample_rate < 0)
>> @@ -440,6 +452,10 @@ static const struct regmap_config sun8i_codec_regmap_config = {
>> .cache_type = REGCACHE_FLAT,
>> };
>>
>> +static const struct sun8i_codec_quirks sun8i_a33_codec_quirks = {
>> + .aif1_lrck_div = SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16,
>> +};
>> +
>> static int sun8i_codec_probe(struct platform_device *pdev)
>> {
>> struct resource *res_base;
>> @@ -453,6 +469,13 @@ static int sun8i_codec_probe(struct platform_device *pdev)
>>
>> scodec->dev = &pdev->dev;
>>
>> + scodec->variant = of_device_get_match_data(&pdev->dev);
>> + if (!scodec->variant) {
>> + dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
>> + return -ENODEV;
>> + }
>> +
>> +
>> scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
>> if (IS_ERR(scodec->clk_module)) {
>> dev_err(&pdev->dev, "Failed to get the module clock\n");
>> @@ -524,7 +547,10 @@ static int sun8i_codec_remove(struct platform_device *pdev)
>> }
>>
>> static const struct of_device_id sun8i_codec_of_match[] = {
>> - { .compatible = "allwinner,sun8i-a33-codec" },
>> + {
>> + .compatible = "allwinner,sun8i-a33-codec",
>> + .data = &sun8i_a33_codec_quirks,
>> + },
>> {}
>> };
>> MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
>> --
>> 2.15.0
>>
^ permalink raw reply
* [PATCH 2/2] arm64: dts: renesas: v3msk: add EtherAVB support
From: Geert Uytterhoeven @ 2017-12-04 8:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171124210317.285946395@cogentembedded.com>
On Fri, Nov 24, 2017 at 9:59 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Define the V3M Starter Kit board dependent part of the EtherAVB
> device node.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] arm: dts: uniphier: add efuse node for UniPhier 32bit SoC
From: Keiji Hayashibara @ 2017-12-04 8:12 UTC (permalink / raw)
To: linux-arm-kernel
Add efuse node for UniPhier LD4, Pro4, sLD8, Pro5 and PXs2.
This efuse node is included in soc-glue.
Signed-off-by: Keiji Hayashibara <hayashibara.keiji@socionext.com>
---
arch/arm/boot/dts/uniphier-ld4.dtsi | 18 ++++++++++++++++++
arch/arm/boot/dts/uniphier-pro4.dtsi | 23 +++++++++++++++++++++++
arch/arm/boot/dts/uniphier-pro5.dtsi | 33 +++++++++++++++++++++++++++++++++
arch/arm/boot/dts/uniphier-pxs2.dtsi | 18 ++++++++++++++++++
arch/arm/boot/dts/uniphier-sld8.dtsi | 18 ++++++++++++++++++
5 files changed, 110 insertions(+)
diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi
index 01fc3e1..6883f3b 100644
--- a/arch/arm/boot/dts/uniphier-ld4.dtsi
+++ b/arch/arm/boot/dts/uniphier-ld4.dtsi
@@ -273,6 +273,24 @@
};
};
+ soc-glue at 5f900000 {
+ compatible = "socionext,uniphier-ld4-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse at 100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse at 130 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x130 0x8>;
+ };
+ };
+
timer at 60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi
index 7955c3a..150726b 100644
--- a/arch/arm/boot/dts/uniphier-pro4.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro4.dtsi
@@ -294,6 +294,29 @@
};
};
+ soc-glue at 5f900000 {
+ compatible = "socionext,uniphier-pro4-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse at 100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse at 130 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x130 0x8>;
+ };
+
+ efuse at 200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x14>;
+ };
+ };
+
aidet: aidet at 5fc20000 {
compatible = "socionext,uniphier-pro4-aidet";
reg = <0x5fc20000 0x200>;
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 6589b8a..f291dd6 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -355,6 +355,39 @@
};
};
+ soc-glue at 5f900000 {
+ compatible = "socionext,uniphier-pro5-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse at 100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse at 130 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x130 0x8>;
+ };
+
+ efuse at 200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x28>;
+ };
+
+ efuse at 300 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x300 0x14>;
+ };
+
+ efuse at 400 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x400 0x8>;
+ };
+ };
+
aidet: aidet at 5fc20000 {
compatible = "socionext,uniphier-pro5-aidet";
reg = <0x5fc20000 0x200>;
diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi
index d82d6d8..8e54e87 100644
--- a/arch/arm/boot/dts/uniphier-pxs2.dtsi
+++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi
@@ -375,6 +375,24 @@
};
};
+ soc-glue at 5f900000 {
+ compatible = "socionext,uniphier-pxs2-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse at 100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse at 200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x58>;
+ };
+ };
+
aidet: aidet at 5fc20000 {
compatible = "socionext,uniphier-pxs2-aidet";
reg = <0x5fc20000 0x200>;
diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi
index 7188536..afafe7c 100644
--- a/arch/arm/boot/dts/uniphier-sld8.dtsi
+++ b/arch/arm/boot/dts/uniphier-sld8.dtsi
@@ -277,6 +277,24 @@
};
};
+ soc-glue at 5f900000 {
+ compatible = "socionext,uniphier-sld8-soc-glue-debug",
+ "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x5f900000 0x2000>;
+
+ efuse at 100 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x100 0x28>;
+ };
+
+ efuse at 200 {
+ compatible = "socionext,uniphier-efuse";
+ reg = <0x200 0x14>;
+ };
+ };
+
timer at 60000200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x60000200 0x20>;
--
2.7.4
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: renesas: initial V3MSK board device tree
From: Geert Uytterhoeven @ 2017-12-04 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171124210313.219761525@cogentembedded.com>
On Fri, Nov 24, 2017 at 9:59 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add the initial device tree for the V3M Starter Kit board.
> The board has 1 debug serial port (SCIF0); include support for it,
> so that the serial console can work.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v4 02/10] pinctrl: axp209: add pinctrl features
From: Quentin Schulz @ 2017-12-04 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201155702.irfox7vf3kfjvpjx@flea.lan>
Hi Maxime,
On 01/12/2017 16:57, Maxime Ripard wrote:
> On Fri, Dec 01, 2017 at 02:44:43PM +0100, Quentin Schulz wrote:
>> +static void axp20x_gpio_set(struct gpio_chip *chip, unsigned offset,
>> + int value)
>> +{
>
> checkpatch output:
> WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
>
>> +static int axp20x_pmx_set_mux(struct pinctrl_dev *pctldev,
>> + unsigned int function, unsigned int group)
>> +{
>> + struct axp20x_gpio *gpio = pinctrl_dev_get_drvdata(pctldev);
>> + unsigned int mask;
>> +
>> + /* Every pin supports GPIO_OUT and GPIO_IN functions */
>> + if (function <= AXP20X_FUNC_GPIO_IN)
>> + return axp20x_pmx_set(pctldev, group,
>> + gpio->funcs[function].muxval);
>> +
>> + if (function == AXP20X_FUNC_LDO)
>> + mask = gpio->desc->ldo_mask;
>> + else
>> + mask = gpio->desc->adc_mask;
>
> What is the point of this test...
>
>> + if (!(BIT(group) & mask))
>> + return -EINVAL;
>> +
>> + /*
>> + * We let the regulator framework handle the LDO muxing as muxing bits
>> + * are basically also regulators on/off bits. It's better not to enforce
>> + * any state of the regulator when selecting LDO mux so that we don't
>> + * interfere with the regulator driver.
>> + */
>> + if (function == AXP20X_FUNC_LDO)
>> + return 0;
>
> ... if you know that you're not going to do anything with one of the
> outcomes. It would be better to just move that part above, instead of
> doing the same test twice.
>
Return value is different. In one case, it is an error to request "ldo"
for a pin that does not support it. In the other case, the ldo request
is valid but nothing's done on driver side.
Both cases are handled differently by the core:
http://elixir.free-electrons.com/linux/latest/source/drivers/pinctrl/pinmux.c#L439
I think that's the behavior we're expecting from this driver.
Or maybe you're asking to do:
+ if (function == AXP20X_FUNC_LDO) {
+ if (!(BIT(group) & gpio->desc->ldo_mask))
+ return -EINVAL;
+ return 0;
+ } else if (!(BIT(group) & gpio->desc->adc_mask)) {
+ return -EINVAL;
+ }
?
Thanks,
Quentin
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH 0/4] Move DP phy switch to PHY driver
From: Heiko Stübner @ 2017-12-04 7:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8042d73f-c1de-da41-9066-2377de1f521c@rock-chips.com>
Hi Chris,
Am Montag, 4. Dezember 2017, 10:47:08 CET schrieb Chris Zhong:
> On 2017?12?02? 05:58, Heiko Stuebner wrote:
> > Am Freitag, 1. Dezember 2017, 13:42:46 CET schrieb Doug Anderson:
> >> Hi,
> >>
> >> On Wed, Nov 29, 2017 at 6:27 PM, Chris Zhong <zyw@rock-chips.com> wrote:
> >>> Hi Doug
> >>>
> >>> Thank you for mentioning this patch.
> >>>
> >>> I think the focus of the discussion is: can we put the grf control bit
> >>> to
> >>> dts.
> >>>
> >>> The RK3399 has 2 Type-C phy, but only one DP controller, this
> >>> "uphy_dp_sel"
> >>>
> >>> can help to switch these 2 phy. So I think this bit can be considered as
> >>> a
> >>> part of
> >>>
> >>> Type-C phy, these 2 phy have different bits, just similar to other bits
> >>> (such as "pipe-status").
> >>>
> >>> Put them to DTS file might be a accepted practice.
> >>
> >> I guess the first step would be finding the person to make a decision.
> >> Is that Heiko? Olof? Kishon? Rob?. As I see it there are a few
> >> options:
> >>
> >> 1. Land this series as-is. This makes the new bit work just like all
> >> the other ones next to it. If anyone happens to try to use an old
> >> device tree on a new kernel they'll break. Seems rather unlikely
> >> given that the whole type C PHY is not really fully functional
> >> upstream, but technically this is a no-no from a device tree
> >> perspective.
> >>
> >> 2. Change the series to make this property optional. If it's not
> >> there then the code behaves like it always did. This would address
> >> the "compatibility" problem but likely wouldn't actually help any real
> >> people, and it would be extra work.
> >>
> >> 3. Redo the driver to deprecate all the old offsets / bits and just
> >> put the table in the driver, keyed off the compatible string and base
> >> address if the IO memory.
> >>
> >>
> >> I can't make this decision. It's up to those folks who would be
> >> landing the patch and I'd be happy with any of them. What I'm less
> >> happy with, however, is the indecision preventing forward progress.
> >> We should pick one of the above things and land it. My own personal
> >> bias is #1: just land the series. No real people will be hurt and
> >> it's just adding another property that matches the ones next to it.
> >
> > I'd second that #1 . That whole type-c phy thingy never fully worked in
> > the past (some for the never used dp output), so personally I don't have
> > issues with going that route.
> >
> >> From a long term perspective (AKA how I'd write the next driver like
> >>
> >> this) I personally lean towards to "tables in the driver, not in the
> >> device tree" but quite honestly I'm happy to take whatever direction
> >> the maintainers give.
> >
> > It looks like we're in agreement here :-) . GRF stuff should not leak into
> > the devicetree, as it causes endless headaches later. But I guess we'll
> > need to live with the ones that happened so far.
>
> So, the first step is: move all the private property of tcphy to
> drivers/phy/rockchip/phy-rockchip-typec.c.
> Second step: new a member: uphy-dp-sel.
> In my mind, we should have discussed these properties before, and then I
> moved them all into DTS.
Actually, I was agreeing with Doug, that we probably don't need to rework the
type-c phy driver. As most properties for it are in the devicetree right now
we'll need to support them for backwards-compatiblity anyway.
And yes, there probably was discussion over dts vs. driver-table when the
type-c driver was introduced, but I either missed it or wasn't firm enough
back then ;-) .
Hence the "we'll need to live with it" for the type-c phy, but should not
do similar things in future drivers.
Heiko
^ permalink raw reply
* [PATCH 3/9] ASoC: sun8i-codec: Add quirk to specify aif1_lrck_div value
From: Chen-Yu Tsai @ 2017-12-04 7:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171203204157.20829-4-anarsoul@gmail.com>
On Mon, Dec 4, 2017 at 4:41 AM, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
> LRCK divider for A64 differs from A33, so add a quirk to support that.
>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
> sound/soc/sunxi/sun8i-codec.c | 38 ++++++++++++++++++++++++++++++++------
> 1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
> index 3dd183be08a4..054201d1de03 100644
> --- a/sound/soc/sunxi/sun8i-codec.c
> +++ b/sound/soc/sunxi/sun8i-codec.c
> @@ -24,6 +24,7 @@
> #include <linux/io.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> +#include <linux/of_device.h>
Please keep them sorted in alphabetical order.
>
> #include <sound/pcm_params.h>
> #include <sound/soc.h>
> @@ -75,11 +76,22 @@
> #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
> #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
>
> +/*
> + * struct sun8i_codec_quirks - Differences between SoC variants.
> + *
> + * @aif1_lrck_div: LRCK divider
> + */
> +struct sun8i_codec_quirks {
> + unsigned int aif1_lrck_div;
> +};
> +
> +
> struct sun8i_codec {
> - struct device *dev;
> - struct regmap *regmap;
> - struct clk *clk_module;
> - struct clk *clk_bus;
> + struct device *dev;
> + struct regmap *regmap;
> + struct clk *clk_module;
> + struct clk *clk_bus;
> + const struct sun8i_codec_quirks *variant;
> };
>
> static int sun8i_codec_runtime_resume(struct device *dev)
> @@ -305,7 +317,7 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
>
> regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
> SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
> - SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
> + scodec->variant->aif1_lrck_div);
Hard coding a fixed divider is generally a bad idea.
You adding another fixed value for this is evidence of this.
The BCK:LRCK divider is equal to sample width * 2. You should
have that instead.
Also I see no evidence that either the I2S controller (see my
comment on patch 1) or the codec is limited to a certain sample
width in hardware, other than your claims, which are vague at
best.
The user manual for both the A33 and A64 list many possible
widths and dividers. If the user manual is wrong, please provide
solid evidence proving it wrong.
Either way this series will not be accepted in its current form.
ChenYu
>
> sample_rate = sun8i_codec_get_hw_rate(params);
> if (sample_rate < 0)
> @@ -440,6 +452,10 @@ static const struct regmap_config sun8i_codec_regmap_config = {
> .cache_type = REGCACHE_FLAT,
> };
>
> +static const struct sun8i_codec_quirks sun8i_a33_codec_quirks = {
> + .aif1_lrck_div = SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16,
> +};
> +
> static int sun8i_codec_probe(struct platform_device *pdev)
> {
> struct resource *res_base;
> @@ -453,6 +469,13 @@ static int sun8i_codec_probe(struct platform_device *pdev)
>
> scodec->dev = &pdev->dev;
>
> + scodec->variant = of_device_get_match_data(&pdev->dev);
> + if (!scodec->variant) {
> + dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
> + return -ENODEV;
> + }
> +
> +
> scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
> if (IS_ERR(scodec->clk_module)) {
> dev_err(&pdev->dev, "Failed to get the module clock\n");
> @@ -524,7 +547,10 @@ static int sun8i_codec_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id sun8i_codec_of_match[] = {
> - { .compatible = "allwinner,sun8i-a33-codec" },
> + {
> + .compatible = "allwinner,sun8i-a33-codec",
> + .data = &sun8i_a33_codec_quirks,
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
> --
> 2.15.0
>
^ permalink raw reply
* [PATCH 2/9] ASoC: sun4i-i2s: Add compatibility with A64 codec I2S
From: Vasily Khoruzhick @ 2017-12-04 7:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAEKpxBmHhZ+2WNXJEPbQFS6KeKsqRrZeNodRnu1M5yLc15DerA@mail.gmail.com>
I'd keep it sun50i_a64_acodec_i2s, since other 3 I2S modules aren't
compatible with this one, but similar to H3.
On Sun, Dec 3, 2017 at 10:42 PM, Code Kipper <codekipper@gmail.com> wrote:
> On 3 December 2017 at 21:41, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
>> From: Marcus Cooper <codekipper@gmail.com>
>>
>> The I2S block used for the audio codec in the A64 is very similar
>> to what is used by the A10(sun4i) devices. However, its TX FIFO is
>> located at a different address.
>>
>> [vasilykh: - added fixed_wss and wss_value to A64 quirks,
>> - changed compatible to 'allwinner,sun50i-a64-acodec-i2s,
>> since A64 has 3 more I2S blocks that are not compatible
>> with audio codec I2S]
>>
>> Signed-off-by: Marcus Cooper <codekipper@gmail.com>
>> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
>> ---
>> .../devicetree/bindings/sound/sun4i-i2s.txt | 2 ++
>> sound/soc/sunxi/sun4i-i2s.c | 23 ++++++++++++++++++++++
>> 2 files changed, 25 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>> index 05d7135a8d2f..ab86f266962a 100644
>> --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>> +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
>> @@ -9,6 +9,7 @@ Required properties:
>> - "allwinner,sun4i-a10-i2s"
>> - "allwinner,sun6i-a31-i2s"
>> - "allwinner,sun8i-h3-i2s"
>> + - "allwinner,sun50i-a64-acodec-i2s"
>> - reg: physical base address of the controller and length of memory mapped
>> region.
>> - interrupts: should contain the I2S interrupt.
>> @@ -24,6 +25,7 @@ Required properties:
>> Required properties for the following compatibles:
>> - "allwinner,sun6i-a31-i2s"
>> - "allwinner,sun8i-h3-i2s"
>> + - "allwinner,sun50i-a64-acodec-i2s"
> I would keep the compatible format the same. ie.
> allwinner,sun50i-a64-i2s. The A33 for example uses the sun6i-a31-i2s
> for it's dai.
>
>> - resets: phandle to the reset line for this codec
>>
>> Example:
>> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
>> index 54c16eb64713..2c060e015725 100644
>> --- a/sound/soc/sunxi/sun4i-i2s.c
>> +++ b/sound/soc/sunxi/sun4i-i2s.c
>> @@ -942,6 +942,25 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
>> .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
>> };
>>
>> +static const struct sun4i_i2s_quirks sun50i_a64_acodec_i2s_quirks = {
> ditto
>> + .has_reset = true,
>> + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
>> + .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
>> + .has_slave_select_bit = true,
>> + .fixed_wss = true,
>> + .wss_value = 3,
>> + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
>> + .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
>> + .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
>> + .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
>> + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
>> + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
>> + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
>> + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
>> + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
>> + .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
>> +};
>> +
>> static int sun4i_i2s_init_regmap_fields(struct device *dev,
>> struct sun4i_i2s *i2s)
>> {
>> @@ -1146,6 +1165,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
>> .compatible = "allwinner,sun8i-h3-i2s",
>> .data = &sun8i_h3_i2s_quirks,
>> },
>> + {
>> + .compatible = "allwinner,sun50i-a64-acodec-i2s",
>> + .data = &sun50i_a64_acodec_i2s_quirks,
> ditto
> BR,
> CK
>> + },
>> {}
>> };
>> MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
>> --
>> 2.15.0
>>
^ permalink raw reply
* [PATCH] staging: vc04_services: Fix trivial style issues
From: Greg Kroah-Hartman @ 2017-12-04 7:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <30cc7b48def470f1bec8d8d255044f4f220531ee.1512368114.git.sky@genki.is>
On Mon, Dec 04, 2017 at 01:17:36AM -0500, Genki Sky wrote:
> In bcm2835-camera, handle the following checkpatch.pl types:
> - EMBEDDED_FUNCTION_NAME
> - MULTILINE_DEREFERENCE
> - SPLIT_STRING
>
> [ note: this is for Task 10 of http://eudyptula-challenge.org/ ]
>
> Signed-off-by: Genki Sky <sky@genki.is>
> ---
> .../vc04_services/bcm2835-camera/bcm2835-camera.c | 23 +++++++++-------------
> .../vc04_services/bcm2835-camera/mmal-vchiq.c | 7 +++----
> 2 files changed, 12 insertions(+), 18 deletions(-)
Hi,
This is the friendly patch-bot of Greg Kroah-Hartman. You have sent him
a patch that has triggered this response. He used to manually respond
to these common problems, but in order to save his sanity (he kept
writing the same thing over and over, yet to different people), I was
created. Hopefully you will not take offence and will fix the problem
in your patch and resubmit it so that it can be accepted into the Linux
kernel tree.
You are receiving this message because of the following common error(s)
as indicated below:
- Your patch did many different things all at once, making it difficult
to review. All Linux kernel patches need to only do one thing at a
time. If you need to do multiple things (such as clean up all coding
style issues in a file/driver), do it in a sequence of patches, each
one doing only one thing. This will make it easier to review the
patches to ensure that they are correct, and to help alleviate any
merge issues that larger patches can cause.
If you wish to discuss this problem further, or you have questions about
how to resolve this issue, please feel free to respond to this email and
Greg will reply once he has dug out from the pending patches received
from other developers.
thanks,
greg k-h's patch email bot
^ permalink raw reply
* [PATCH 3/9] ASoC: sun8i-codec: Add quirk to specify aif1_lrck_div value
From: Code Kipper @ 2017-12-04 7:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171203204157.20829-4-anarsoul@gmail.com>
On 3 December 2017 at 21:41, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
> LRCK divider for A64 differs from A33, so add a quirk to support that.
>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
> sound/soc/sunxi/sun8i-codec.c | 38 ++++++++++++++++++++++++++++++++------
> 1 file changed, 32 insertions(+), 6 deletions(-)
>
> diff --git a/sound/soc/sunxi/sun8i-codec.c b/sound/soc/sunxi/sun8i-codec.c
> index 3dd183be08a4..054201d1de03 100644
> --- a/sound/soc/sunxi/sun8i-codec.c
> +++ b/sound/soc/sunxi/sun8i-codec.c
> @@ -24,6 +24,7 @@
> #include <linux/io.h>
> #include <linux/pm_runtime.h>
> #include <linux/regmap.h>
> +#include <linux/of_device.h>
>
> #include <sound/pcm_params.h>
> #include <sound/soc.h>
> @@ -75,11 +76,22 @@
> #define SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK GENMASK(8, 6)
> #define SUN8I_AIF1CLK_CTRL_AIF1_BCLK_DIV_MASK GENMASK(12, 9)
>
> +/*
> + * struct sun8i_codec_quirks - Differences between SoC variants.
> + *
> + * @aif1_lrck_div: LRCK divider
> + */
> +struct sun8i_codec_quirks {
> + unsigned int aif1_lrck_div;
> +};
> +
> +
Extra line
> struct sun8i_codec {
> - struct device *dev;
> - struct regmap *regmap;
> - struct clk *clk_module;
> - struct clk *clk_bus;
> + struct device *dev;
> + struct regmap *regmap;
> + struct clk *clk_module;
> + struct clk *clk_bus;
> + const struct sun8i_codec_quirks *variant;
> };
>
> static int sun8i_codec_runtime_resume(struct device *dev)
> @@ -305,7 +317,7 @@ static int sun8i_codec_hw_params(struct snd_pcm_substream *substream,
>
> regmap_update_bits(scodec->regmap, SUN8I_AIF1CLK_CTRL,
> SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_MASK,
> - SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16);
> + scodec->variant->aif1_lrck_div);
>
> sample_rate = sun8i_codec_get_hw_rate(params);
> if (sample_rate < 0)
> @@ -440,6 +452,10 @@ static const struct regmap_config sun8i_codec_regmap_config = {
> .cache_type = REGCACHE_FLAT,
> };
>
> +static const struct sun8i_codec_quirks sun8i_a33_codec_quirks = {
> + .aif1_lrck_div = SUN8I_AIF1CLK_CTRL_AIF1_LRCK_DIV_16,
> +};
> +
> static int sun8i_codec_probe(struct platform_device *pdev)
> {
> struct resource *res_base;
> @@ -453,6 +469,13 @@ static int sun8i_codec_probe(struct platform_device *pdev)
>
> scodec->dev = &pdev->dev;
>
> + scodec->variant = of_device_get_match_data(&pdev->dev);
> + if (!scodec->variant) {
> + dev_err(&pdev->dev, "Failed to determine the quirks to use\n");
> + return -ENODEV;
> + }
> +
> +
ditto
> scodec->clk_module = devm_clk_get(&pdev->dev, "mod");
> if (IS_ERR(scodec->clk_module)) {
> dev_err(&pdev->dev, "Failed to get the module clock\n");
> @@ -524,7 +547,10 @@ static int sun8i_codec_remove(struct platform_device *pdev)
> }
>
> static const struct of_device_id sun8i_codec_of_match[] = {
> - { .compatible = "allwinner,sun8i-a33-codec" },
> + {
> + .compatible = "allwinner,sun8i-a33-codec",
> + .data = &sun8i_a33_codec_quirks,
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, sun8i_codec_of_match);
> --
> 2.15.0
>
^ permalink raw reply
* [PATCH v6 2/2] media: i2c: Add the ov7740 image sensor driver
From: Wenyou Yang @ 2017-12-04 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204065858.3138-1-wenyou.yang@microchip.com>
The ov7740 (color) image sensor is a high performance VGA CMOS
image snesor, which supports for output formats: RAW RGB and YUV
and image sizes: VGA, and QVGA, CIF and any size smaller.
Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
---
Changes in v6:
- Remove unnecessary #include <linux/init>.
- Remove unnecessary comments and extra newline.
- Add const for some structures.
- Add the check of the return value from regmap_write().
- Simplify the calling of __v4l2_ctrl_handler_setup().
- Add the default format initialization function.
- Integrate the set_power() and enable/disable the clock into
one function.
Changes in v5:
- Squash the driver and MAINTAINERS entry patches to one.
- Precede the driver patch with the bindings patch.
Changes in v4:
- Assign 'val' a initial value to avoid warning: 'val' may be
used uninitialized.
- Rename REG_REG15 to avoid warning: "REG_REG15" redefined.
Changes in v3:
- Put the MAINTAINERS change to a separate patch.
Changes in v2:
- Split off the bindings into a separate patch.
- Add a new entry to the MAINTAINERS file.
MAINTAINERS | 8 +
drivers/media/i2c/Kconfig | 8 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov7740.c | 1226 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 1243 insertions(+)
create mode 100644 drivers/media/i2c/ov7740.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 7a52a66aa991..1de965009b13 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -10053,6 +10053,14 @@ S: Maintained
F: drivers/media/i2c/ov7670.c
F: Documentation/devicetree/bindings/media/i2c/ov7670.txt
+OMNIVISION OV7740 SENSOR DRIVER
+M: Wenyou Yang <wenyou.yang@microchip.com>
+L: linux-media at vger.kernel.org
+T: git git://linuxtv.org/media_tree.git
+S: Maintained
+F: drivers/media/i2c/ov7740.c
+F: Documentation/devicetree/bindings/media/i2c/ov7740.txt
+
ONENAND FLASH DRIVER
M: Kyungmin Park <kyungmin.park@samsung.com>
L: linux-mtd at lists.infradead.org
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index cb5d7ff82915..00b1c4c031d4 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -665,6 +665,14 @@ config VIDEO_OV7670
OV7670 VGA camera. It currently only works with the M88ALP01
controller.
+config VIDEO_OV7740
+ tristate "OmniVision OV7740 sensor support"
+ depends on I2C && VIDEO_V4L2
+ depends on MEDIA_CAMERA_SUPPORT
+ ---help---
+ This is a Video4Linux2 sensor-level driver for the OmniVision
+ OV7740 VGA camera sensor.
+
config VIDEO_OV9650
tristate "OmniVision OV9650/OV9652 sensor support"
depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index 548a9efce966..9b19ec7fcaf4 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_VIDEO_OV5670) += ov5670.o
obj-$(CONFIG_VIDEO_OV6650) += ov6650.o
obj-$(CONFIG_VIDEO_OV7640) += ov7640.o
obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
+obj-$(CONFIG_VIDEO_OV7740) += ov7740.o
obj-$(CONFIG_VIDEO_OV9650) += ov9650.o
obj-$(CONFIG_VIDEO_OV13858) += ov13858.o
obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o
diff --git a/drivers/media/i2c/ov7740.c b/drivers/media/i2c/ov7740.c
new file mode 100644
index 000000000000..42c25277d005
--- /dev/null
+++ b/drivers/media/i2c/ov7740.c
@@ -0,0 +1,1226 @@
+/*
+ * Copyright (c) 2017 Microchip Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-image-sizes.h>
+#include <media/v4l2-subdev.h>
+
+#define REG_OUTSIZE_LSB 0x34
+
+/* OV7740 register tables */
+#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
+#define REG_BGAIN 0x01 /* blue gain */
+#define REG_RGAIN 0x02 /* red gain */
+#define REG_GGAIN 0x03 /* green gain */
+#define REG_REG04 0x04 /* analog setting, dont change*/
+#define REG_BAVG 0x05 /* b channel average */
+#define REG_GAVG 0x06 /* g channel average */
+#define REG_RAVG 0x07 /* r channel average */
+
+#define REG_REG0C 0x0C /* filp enable */
+#define REG0C_IMG_FLIP 0x80
+#define REG0C_IMG_MIRROR 0x40
+
+#define REG_REG0E 0x0E /* blc line */
+#define REG_HAEC 0x0F /* auto exposure cntrl */
+#define REG_AEC 0x10 /* auto exposure cntrl */
+
+#define REG_CLK 0x11 /* Clock control */
+#define REG_REG55 0x55 /* Clock PLL DIV/PreDiv */
+
+#define REG_REG12 0x12
+
+#define REG_REG13 0x13 /* auto/manual AGC, AEC, Write Balance*/
+#define REG13_AEC_EN 0x01
+#define REG13_AGC_EN 0x04
+
+#define REG_REG14 0x14
+#define REG_CTRL15 0x15
+#define REG15_GAIN_MSB 0x03
+
+#define REG_REG16 0x16
+
+#define REG_MIDH 0x1C /* manufacture id byte */
+#define REG_MIDL 0x1D /* manufacture id byre */
+#define REG_PIDH 0x0A /* Product ID MSB */
+#define REG_PIDL 0x0B /* Product ID LSB */
+
+#define REG_84 0x84 /* lots of stuff */
+#define REG_REG38 0x38 /* sub-addr */
+
+#define REG_AHSTART 0x17 /* Horiz start high bits */
+#define REG_AHSIZE 0x18
+#define REG_AVSTART 0x19 /* Vert start high bits */
+#define REG_AVSIZE 0x1A
+#define REG_PSHFT 0x1b /* Pixel delay after HREF */
+
+#define REG_HOUTSIZE 0x31
+#define REG_VOUTSIZE 0x32
+#define REG_HVSIZEOFF 0x33
+#define REG_REG34 0x34 /* DSP output size H/V LSB*/
+
+#define REG_ISP_CTRL00 0x80
+#define ISPCTRL00_AWB_EN 0x10
+#define ISPCTRL00_AWB_GAIN_EN 0x04
+
+#define REG_YGAIN 0xE2 /* ygain for contrast control */
+
+#define REG_YBRIGHT 0xE3
+#define REG_SGNSET 0xE4
+#define SGNSET_YBRIGHT_MASK 0x08
+
+#define REG_USAT 0xDD
+#define REG_VSAT 0xDE
+
+
+struct ov7740 {
+ struct v4l2_subdev subdev;
+#if defined(CONFIG_MEDIA_CONTROLLER)
+ struct media_pad pad;
+#endif
+ struct v4l2_mbus_framefmt format;
+ const struct ov7740_pixfmt *fmt; /* Current format */
+ const struct ov7740_framesize *frmsize;
+ struct regmap *regmap;
+ struct clk *xvclk;
+ struct v4l2_ctrl_handler ctrl_handler;
+ struct {
+ /* gain cluster */
+ struct v4l2_ctrl *auto_gain;
+ struct v4l2_ctrl *gain;
+ };
+ struct {
+ struct v4l2_ctrl *auto_wb;
+ struct v4l2_ctrl *blue_balance;
+ struct v4l2_ctrl *red_balance;
+ };
+ struct {
+ struct v4l2_ctrl *hflip;
+ struct v4l2_ctrl *vflip;
+ };
+ struct {
+ /* exposure cluster */
+ struct v4l2_ctrl *auto_exposure;
+ struct v4l2_ctrl *exposure;
+ };
+ struct {
+ /* saturation/hue cluster */
+ struct v4l2_ctrl *saturation;
+ struct v4l2_ctrl *hue;
+ };
+ struct v4l2_ctrl *brightness;
+ struct v4l2_ctrl *contrast;
+
+ struct mutex mutex; /* To serialize asynchronus callbacks */
+ bool streaming; /* Streaming on/off */
+
+ struct gpio_desc *resetb_gpio;
+ struct gpio_desc *pwdn_gpio;
+};
+
+struct ov7740_pixfmt {
+ u32 mbus_code;
+ enum v4l2_colorspace colorspace;
+ const struct reg_sequence *regs;
+ u32 reg_num;
+};
+
+struct ov7740_framesize {
+ u16 width;
+ u16 height;
+ const struct reg_sequence *regs;
+ u32 reg_num;
+};
+
+static const struct reg_sequence ov7740_vga[] = {
+ {0x55, 0x40},
+ {0x11, 0x02},
+
+ {0xd5, 0x10},
+ {0x0c, 0x12},
+ {0x0d, 0x34},
+ {0x17, 0x25},
+ {0x18, 0xa0},
+ {0x19, 0x03},
+ {0x1a, 0xf0},
+ {0x1b, 0x89},
+ {0x22, 0x03},
+ {0x29, 0x18},
+ {0x2b, 0xf8},
+ {0x2c, 0x01},
+ {REG_HOUTSIZE, 0xa0},
+ {REG_VOUTSIZE, 0xf0},
+ {0x33, 0xc4},
+ {REG_OUTSIZE_LSB, 0x0},
+ {0x35, 0x05},
+ {0x04, 0x60},
+ {0x27, 0x80},
+ {0x3d, 0x0f},
+ {0x3e, 0x80},
+ {0x3f, 0x40},
+ {0x40, 0x7f},
+ {0x41, 0x6a},
+ {0x42, 0x29},
+ {0x44, 0x22},
+ {0x45, 0x41},
+ {0x47, 0x02},
+ {0x49, 0x64},
+ {0x4a, 0xa1},
+ {0x4b, 0x40},
+ {0x4c, 0x1a},
+ {0x4d, 0x50},
+ {0x4e, 0x13},
+ {0x64, 0x00},
+ {0x67, 0x88},
+ {0x68, 0x1a},
+
+ {0x14, 0x28},
+ {0x24, 0x3c},
+ {0x25, 0x30},
+ {0x26, 0x72},
+ {0x50, 0x97},
+ {0x51, 0x1f},
+ {0x52, 0x00},
+ {0x53, 0x00},
+ {0x20, 0x00},
+ {0x21, 0xcf},
+ {0x50, 0x4b},
+ {0x38, 0x14},
+ {0xe9, 0x00},
+ {0x56, 0x55},
+ {0x57, 0xff},
+ {0x58, 0xff},
+ {0x59, 0xff},
+ {0x5f, 0x04},
+ {0xec, 0x00},
+ {0x13, 0xff},
+
+ {0x81, 0x3f},
+ {0x82, 0x32},
+ {0x38, 0x11},
+ {0x84, 0x70},
+ {0x85, 0x00},
+ {0x86, 0x03},
+ {0x87, 0x01},
+ {0x88, 0x05},
+ {0x89, 0x30},
+ {0x8d, 0x30},
+ {0x8f, 0x85},
+ {0x93, 0x30},
+ {0x95, 0x85},
+ {0x99, 0x30},
+ {0x9b, 0x85},
+
+ {0x9c, 0x08},
+ {0x9d, 0x12},
+ {0x9e, 0x23},
+ {0x9f, 0x45},
+ {0xa0, 0x55},
+ {0xa1, 0x64},
+ {0xa2, 0x72},
+ {0xa3, 0x7f},
+ {0xa4, 0x8b},
+ {0xa5, 0x95},
+ {0xa6, 0xa7},
+ {0xa7, 0xb5},
+ {0xa8, 0xcb},
+ {0xa9, 0xdd},
+ {0xaa, 0xec},
+ {0xab, 0x1a},
+
+ {0xce, 0x78},
+ {0xcf, 0x6e},
+ {0xd0, 0x0a},
+ {0xd1, 0x0c},
+ {0xd2, 0x84},
+ {0xd3, 0x90},
+ {0xd4, 0x1e},
+
+ {0x5a, 0x24},
+ {0x5b, 0x1f},
+ {0x5c, 0x88},
+ {0x5d, 0x60},
+
+ {0xac, 0x6e},
+ {0xbe, 0xff},
+ {0xbf, 0x00},
+
+ {0x0f, 0x1d},
+ {0x0f, 0x1f},
+};
+
+static const struct ov7740_framesize ov7740_framesizes[] = {
+ {
+ .width = VGA_WIDTH,
+ .height = VGA_HEIGHT,
+ .regs = ov7740_vga,
+ .reg_num = ARRAY_SIZE(ov7740_vga),
+ },
+};
+
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+static int ov7740_get_register(struct v4l2_subdev *sd,
+ struct v4l2_dbg_register *reg)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+ struct regmap *regmap = ov7740->regmap;
+ unsigned int val = 0;
+ int ret;
+
+ ret = regmap_read(regmap, reg->reg & 0xff, &val);
+ reg->val = val;
+ reg->size = 1;
+
+ return 0;
+}
+
+static int ov7740_set_register(struct v4l2_subdev *sd,
+ const struct v4l2_dbg_register *reg)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+ struct regmap *regmap = ov7740->regmap;
+
+ regmap_write(regmap, reg->reg & 0xff, reg->val & 0xff);
+
+ return 0;
+}
+#endif
+
+static int ov7740_set_power(struct ov7740 *ov7740, int on)
+{
+ int ret;
+
+ if (on) {
+ ret = clk_prepare_enable(ov7740->xvclk);
+ if (ret)
+ return ret;
+
+ if (ov7740->pwdn_gpio)
+ gpiod_direction_output(ov7740->pwdn_gpio, 0);
+
+ if (ov7740->resetb_gpio) {
+ gpiod_set_value(ov7740->resetb_gpio, 1);
+ usleep_range(500, 1000);
+ gpiod_set_value(ov7740->resetb_gpio, 0);
+ usleep_range(3000, 5000);
+ }
+ } else {
+ clk_disable_unprepare(ov7740->xvclk);
+
+ if (ov7740->pwdn_gpio)
+ gpiod_direction_output(ov7740->pwdn_gpio, 0);
+ }
+
+ return 0;
+}
+
+static struct v4l2_subdev_core_ops ov7740_subdev_core_ops = {
+ .log_status = v4l2_ctrl_subdev_log_status,
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ .g_register = ov7740_get_register,
+ .s_register = ov7740_set_register,
+#endif
+ .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
+ .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static int ov7740_set_white_balance(struct ov7740 *ov7740, int awb)
+{
+ struct regmap *regmap = ov7740->regmap;
+ unsigned int value;
+ int ret;
+
+ ret = regmap_read(regmap, REG_ISP_CTRL00, &value);
+ if (!ret) {
+ if (awb)
+ value |= (ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
+ else
+ value &= ~(ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
+ ret = regmap_write(regmap, REG_ISP_CTRL00, value);
+ if (ret)
+ return ret;
+ }
+
+ if (!awb) {
+ ret = regmap_write(regmap, REG_BGAIN,
+ ov7740->blue_balance->val);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(regmap, REG_RGAIN, ov7740->red_balance->val);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int ov7740_set_saturation(struct regmap *regmap, int value)
+{
+ int ret;
+
+ ret = regmap_write(regmap, REG_USAT, (unsigned char)value);
+ if (ret)
+ return ret;
+
+ return regmap_write(regmap, REG_VSAT, (unsigned char)value);
+}
+
+static int ov7740_set_gain(struct regmap *regmap, int value)
+{
+ int ret;
+
+ ret = regmap_write(regmap, REG_GAIN, value & 0xff);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(regmap, REG_CTRL15,
+ REG15_GAIN_MSB, (value >> 8) & 0x3);
+ if (!ret)
+ ret = regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
+
+ return ret;
+}
+
+static int ov7740_set_autogain(struct regmap *regmap, int value)
+{
+ unsigned int reg;
+ int ret;
+
+ ret = regmap_read(regmap, REG_REG13, ®);
+ if (ret)
+ return ret;
+ if (value)
+ reg |= REG13_AGC_EN;
+ else
+ reg &= ~REG13_AGC_EN;
+ return regmap_write(regmap, REG_REG13, reg);
+}
+
+static int ov7740_set_brightness(struct regmap *regmap, int value)
+{
+ /* Turn off AEC/AGC */
+ regmap_update_bits(regmap, REG_REG13, REG13_AEC_EN, 0);
+ regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
+
+ if (value >= 0) {
+ regmap_write(regmap, REG_YBRIGHT, (unsigned char)value);
+ regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 0);
+ } else{
+ regmap_write(regmap, REG_YBRIGHT, (unsigned char)(-value));
+ regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 1);
+ }
+
+ return 0;
+}
+
+static int ov7740_set_contrast(struct regmap *regmap, int value)
+{
+ return regmap_write(regmap, REG_YGAIN, (unsigned char)value);
+}
+
+static int ov7740_get_gain(struct ov7740 *ov7740, struct v4l2_ctrl *ctrl)
+{
+ struct regmap *regmap = ov7740->regmap;
+ unsigned int value0, value1;
+ int ret;
+
+ if (!ctrl->val)
+ return 0;
+
+ ret = regmap_read(regmap, REG_GAIN, &value0);
+ if (ret)
+ return ret;
+ ret = regmap_read(regmap, REG_CTRL15, &value1);
+ if (ret)
+ return ret;
+
+ ov7740->gain->val = (value1 << 8) | (value0 & 0xff);
+
+ return 0;
+}
+
+static int ov7740_set_exp(struct regmap *regmap, int value)
+{
+ int ret;
+
+ /* Turn off AEC/AGC */
+ ret = regmap_update_bits(regmap, REG_REG13,
+ REG13_AEC_EN | REG13_AGC_EN, 0);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(regmap, REG_AEC, (unsigned char)value);
+ if (ret)
+ return ret;
+
+ return regmap_write(regmap, REG_HAEC, (unsigned char)(value >> 8));
+}
+
+static int ov7740_set_autoexp(struct regmap *regmap,
+ enum v4l2_exposure_auto_type value)
+{
+ unsigned int reg;
+ int ret;
+
+ ret = regmap_read(regmap, REG_REG13, ®);
+ if (!ret) {
+ if (value == V4L2_EXPOSURE_AUTO)
+ reg |= (REG13_AEC_EN | REG13_AGC_EN);
+ else
+ reg &= ~(REG13_AEC_EN | REG13_AGC_EN);
+ ret = regmap_write(regmap, REG_REG13, reg);
+ }
+
+ return ret;
+}
+
+
+static int ov7740_get_volatile_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ov7740 *ov7740 = container_of(ctrl->handler,
+ struct ov7740, ctrl_handler);
+ int ret;
+
+ switch (ctrl->id) {
+ case V4L2_CID_AUTOGAIN:
+ ret = ov7740_get_gain(ov7740, ctrl);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+ return ret;
+}
+
+static int ov7740_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct ov7740 *ov7740 = container_of(ctrl->handler,
+ struct ov7740, ctrl_handler);
+ struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
+ struct regmap *regmap = ov7740->regmap;
+ int ret;
+ u8 val = 0;
+
+ if (pm_runtime_get_if_in_use(&client->dev) <= 0)
+ return 0;
+
+ switch (ctrl->id) {
+ case V4L2_CID_AUTO_WHITE_BALANCE:
+ ret = ov7740_set_white_balance(ov7740, ctrl->val);
+ break;
+ case V4L2_CID_SATURATION:
+ ret = ov7740_set_saturation(regmap, ctrl->val);
+ break;
+ case V4L2_CID_BRIGHTNESS:
+ ret = ov7740_set_brightness(regmap, ctrl->val);
+ break;
+ case V4L2_CID_CONTRAST:
+ ret = ov7740_set_contrast(regmap, ctrl->val);
+ break;
+ case V4L2_CID_VFLIP:
+ ret = regmap_update_bits(regmap, REG_REG0C,
+ REG0C_IMG_FLIP, val);
+ break;
+ case V4L2_CID_HFLIP:
+ val = ctrl->val ? REG0C_IMG_MIRROR : 0x00;
+ ret = regmap_update_bits(regmap, REG_REG0C,
+ REG0C_IMG_MIRROR, val);
+ break;
+ case V4L2_CID_AUTOGAIN:
+ if (!ctrl->val)
+ return ov7740_set_gain(regmap, ov7740->gain->val);
+
+ ret = ov7740_set_autogain(regmap, ctrl->val);
+ break;
+
+ case V4L2_CID_EXPOSURE_AUTO:
+ if (ctrl->val == V4L2_EXPOSURE_MANUAL)
+ return ov7740_set_exp(regmap, ov7740->exposure->val);
+
+ ret = ov7740_set_autoexp(regmap, ctrl->val);
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ pm_runtime_put(&client->dev);
+
+ return ret;
+}
+
+static const struct v4l2_ctrl_ops ov7740_ctrl_ops = {
+ .g_volatile_ctrl = ov7740_get_volatile_ctrl,
+ .s_ctrl = ov7740_set_ctrl,
+};
+
+static int ov7740_start_streaming(struct ov7740 *ov7740)
+{
+ return __v4l2_ctrl_handler_setup(ov7740->subdev.ctrl_handler);
+}
+
+static int ov7740_set_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+ struct i2c_client *client = v4l2_get_subdevdata(sd);
+ int ret = 0;
+
+ mutex_lock(&ov7740->mutex);
+ if (ov7740->streaming == enable) {
+ mutex_unlock(&ov7740->mutex);
+ return 0;
+ }
+
+ if (enable) {
+ ret = pm_runtime_get_sync(&client->dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(&client->dev);
+ goto err_unlock;
+ }
+
+ ret = ov7740_start_streaming(ov7740);
+ if (ret)
+ goto err_rpm_put;
+ } else {
+ pm_runtime_put(&client->dev);
+ }
+
+ ov7740->streaming = enable;
+
+ mutex_unlock(&ov7740->mutex);
+ return ret;
+
+err_rpm_put:
+ pm_runtime_put(&client->dev);
+err_unlock:
+ mutex_unlock(&ov7740->mutex);
+ return ret;
+}
+
+static int ov7740_get_parm(struct v4l2_subdev *sd,
+ struct v4l2_streamparm *parms)
+{
+ struct v4l2_captureparm *cp = &parms->parm.capture;
+ struct v4l2_fract *tpf = &cp->timeperframe;
+
+ if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+
+ memset(cp, 0, sizeof(struct v4l2_captureparm));
+ cp->capability = V4L2_CAP_TIMEPERFRAME;
+
+ tpf->numerator = 1;
+ tpf->denominator = 60;
+
+ return 0;
+}
+
+static int ov7740_set_parm(struct v4l2_subdev *sd,
+ struct v4l2_streamparm *parms)
+{
+ struct v4l2_captureparm *cp = &parms->parm.capture;
+ struct v4l2_fract *tpf = &cp->timeperframe;
+
+ if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ if (cp->extendedmode != 0)
+ return -EINVAL;
+
+ cp->capability = V4L2_CAP_TIMEPERFRAME;
+
+ tpf->numerator = 1;
+ tpf->denominator = 60;
+
+ return 0;
+}
+
+static struct v4l2_subdev_video_ops ov7740_subdev_video_ops = {
+ .s_stream = ov7740_set_stream,
+ .s_parm = ov7740_set_parm,
+ .g_parm = ov7740_get_parm,
+};
+
+static const struct reg_sequence ov7740_format_yuyv[] = {
+ {0x12, 0x00},
+ {0x36, 0x3f},
+ {0x80, 0x7f},
+ {0x83, 0x01},
+};
+
+static const struct reg_sequence ov7740_format_bggr8[] = {
+ {0x36, 0x2f},
+ {0x80, 0x01},
+ {0x83, 0x04},
+};
+
+static const struct ov7740_pixfmt ov7740_formats[] = {
+ {
+ .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .regs = ov7740_format_yuyv,
+ .reg_num = ARRAY_SIZE(ov7740_format_yuyv),
+ },
+ {
+ .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .regs = ov7740_format_bggr8,
+ .reg_num = ARRAY_SIZE(ov7740_format_bggr8),
+ }
+};
+#define N_OV7740_FMTS ARRAY_SIZE(ov7740_formats)
+
+static int ov7740_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->pad || code->index >= N_OV7740_FMTS)
+ return -EINVAL;
+
+ code->code = ov7740_formats[code->index].mbus_code;
+
+ return 0;
+}
+
+static int ov7740_enum_frame_interval(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_interval_enum *fie)
+{
+ if (fie->pad)
+ return -EINVAL;
+
+ if (fie->index >= 1)
+ return -EINVAL;
+
+ if ((fie->width != VGA_WIDTH) || (fie->height != VGA_HEIGHT))
+ return -EINVAL;
+
+ fie->interval.numerator = 1;
+ fie->interval.denominator = 60;
+
+ return 0;
+}
+
+static int ov7740_enum_frame_size(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->pad)
+ return -EINVAL;
+
+ if (fse->index > 0)
+ return -EINVAL;
+
+ fse->min_width = fse->max_width = VGA_WIDTH;
+ fse->min_height = fse->max_height = VGA_HEIGHT;
+
+ return 0;
+}
+
+static int ov7740_try_fmt_internal(struct v4l2_subdev *sd,
+ struct v4l2_mbus_framefmt *fmt,
+ const struct ov7740_pixfmt **ret_fmt,
+ const struct ov7740_framesize **ret_frmsize)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+ const struct ov7740_framesize *fsize = &ov7740_framesizes[0];
+ int index, i;
+
+ for (index = 0; index < N_OV7740_FMTS; index++) {
+ if (ov7740_formats[index].mbus_code == fmt->code)
+ break;
+ }
+ if (index >= N_OV7740_FMTS) {
+ /* default to first format */
+ index = 0;
+ fmt->code = ov7740_formats[0].mbus_code;
+ }
+ if (ret_fmt != NULL)
+ *ret_fmt = ov7740_formats + index;
+
+ for (i = 0; i < ARRAY_SIZE(ov7740_framesizes); i++) {
+ if ((fsize->width >= fmt->width) &&
+ (fsize->height >= fmt->height)) {
+ fmt->width = fsize->width;
+ fmt->height = fsize->height;
+ break;
+ }
+
+ fsize++;
+ }
+
+ if (ret_frmsize != NULL)
+ *ret_frmsize = fsize;
+
+ fmt->field = V4L2_FIELD_NONE;
+ fmt->colorspace = ov7740_formats[index].colorspace;
+
+ ov7740->format = *fmt;
+
+ return 0;
+}
+
+static int ov7740_set_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *format)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+ const struct ov7740_pixfmt *ovfmt;
+ const struct ov7740_framesize *fsize;
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+ struct v4l2_mbus_framefmt *mbus_fmt;
+#endif
+ int ret;
+
+ mutex_lock(&ov7740->mutex);
+ if (format->pad) {
+ ret = -EINVAL;
+ goto error;
+ }
+
+ if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
+ ret = ov7740_try_fmt_internal(sd, &format->format, NULL, NULL);
+ if (ret)
+ goto error;
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+ mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
+ *mbus_fmt = format->format;
+
+ mutex_unlock(&ov7740->mutex);
+ return 0;
+#else
+ ret = -ENOTTY;
+ goto error;
+#endif
+ }
+
+ ret = ov7740_try_fmt_internal(sd, &format->format, &ovfmt, &fsize);
+ if (ret)
+ goto error;
+
+ if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+ regmap_multi_reg_write(ov7740->regmap,
+ ovfmt->regs, ovfmt->reg_num);
+
+ regmap_multi_reg_write(ov7740->regmap,
+ fsize->regs, fsize->reg_num);
+ }
+
+ ov7740->fmt = ovfmt;
+
+ mutex_unlock(&ov7740->mutex);
+ return 0;
+
+error:
+ mutex_unlock(&ov7740->mutex);
+ return ret;
+}
+
+static int ov7740_get_fmt(struct v4l2_subdev *sd,
+ struct v4l2_subdev_pad_config *cfg,
+ struct v4l2_subdev_format *format)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+ struct v4l2_mbus_framefmt *mbus_fmt;
+#endif
+ int ret = 0;
+
+ mutex_lock(&ov7740->mutex);
+ if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+ mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
+ format->format = *mbus_fmt;
+ ret = 0;
+#else
+ ret = -ENOTTY;
+#endif
+ } else {
+ format->format = ov7740->format;
+ }
+ mutex_unlock(&ov7740->mutex);
+
+ return ret;
+}
+
+static const struct v4l2_subdev_pad_ops ov7740_subdev_pad_ops = {
+ .enum_frame_interval = ov7740_enum_frame_interval,
+ .enum_frame_size = ov7740_enum_frame_size,
+ .enum_mbus_code = ov7740_enum_mbus_code,
+ .get_fmt = ov7740_get_fmt,
+ .set_fmt = ov7740_set_fmt,
+};
+
+static const struct v4l2_subdev_ops ov7740_subdev_ops = {
+ .core = &ov7740_subdev_core_ops,
+ .video = &ov7740_subdev_video_ops,
+ .pad = &ov7740_subdev_pad_ops,
+};
+
+static void ov7740_get_default_format(struct v4l2_subdev *sd,
+ struct v4l2_mbus_framefmt *format)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+
+ format->width = ov7740->frmsize->width;
+ format->height = ov7740->frmsize->height;
+ format->colorspace = ov7740->fmt->colorspace;
+ format->code = ov7740->fmt->mbus_code;
+ format->field = V4L2_FIELD_NONE;
+}
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+static int ov7740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
+{
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+ struct v4l2_mbus_framefmt *format =
+ v4l2_subdev_get_try_format(sd, fh->pad, 0);
+
+ mutex_lock(&ov7740->mutex);
+ ov7740_get_default_format(sd, format);
+ mutex_unlock(&ov7740->mutex);
+
+ return 0;
+}
+
+static const struct v4l2_subdev_internal_ops ov7740_subdev_internal_ops = {
+ .open = ov7740_open,
+};
+#endif
+
+static void ov7740_init_default_format(struct ov7740 *ov7740)
+{
+ ov7740->frmsize = &ov7740_framesizes[0];
+ ov7740->fmt = &ov7740_formats[0];
+
+ regmap_multi_reg_write(ov7740->regmap,
+ ov7740->fmt->regs, ov7740->fmt->reg_num);
+
+ regmap_multi_reg_write(ov7740->regmap,
+ ov7740->frmsize->regs, ov7740->frmsize->reg_num);
+}
+
+static int ov7740_probe_dt(struct i2c_client *client,
+ struct ov7740 *ov7740)
+{
+ ov7740->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
+ GPIOD_OUT_HIGH);
+ if (IS_ERR(ov7740->resetb_gpio)) {
+ dev_info(&client->dev, "can't get %s GPIO\n", "reset");
+ return PTR_ERR(ov7740->resetb_gpio);
+ }
+
+ ov7740->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
+ GPIOD_OUT_LOW);
+ if (IS_ERR(ov7740->pwdn_gpio)) {
+ dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
+ return PTR_ERR(ov7740->pwdn_gpio);
+ }
+
+ return 0;
+}
+
+static int ov7740_detect(struct ov7740 *ov7740)
+{
+ struct regmap *regmap = ov7740->regmap;
+ unsigned int midh, midl, pidh, pidl;
+ int ret;
+
+ ret = regmap_read(regmap, REG_MIDH, &midh);
+ if (ret)
+ return ret;
+ if (midh != 0x7f)
+ return -ENODEV;
+
+ ret = regmap_read(regmap, REG_MIDL, &midl);
+ if (ret)
+ return ret;
+ if (midl != 0xa2)
+ return -ENODEV;
+
+ ret = regmap_read(regmap, REG_PIDH, &pidh);
+ if (ret)
+ return ret;
+ if (pidh != 0x77)
+ return -ENODEV;
+
+ ret = regmap_read(regmap, REG_PIDL, &pidl);
+ if (ret)
+ return ret;
+ if ((pidl != 0x40) && (pidl != 0x41) && (pidl != 0x42))
+ return -ENODEV;
+
+ return 0;
+}
+
+static int ov7740_init_controls(struct ov7740 *ov7740)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
+ struct v4l2_ctrl_handler *ctrl_hdlr = &ov7740->ctrl_handler;
+ int ret;
+
+ ret = v4l2_ctrl_handler_init(ctrl_hdlr, 2);
+ if (ret < 0)
+ return ret;
+
+ ctrl_hdlr->lock = &ov7740->mutex;
+ ov7740->auto_wb = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_AUTO_WHITE_BALANCE,
+ 0, 1, 1, 1);
+ ov7740->blue_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_BLUE_BALANCE,
+ 0, 0xff, 1, 0x80);
+ ov7740->red_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_RED_BALANCE,
+ 0, 0xff, 1, 0x80);
+
+ ov7740->brightness = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_BRIGHTNESS,
+ -255, 255, 1, 0);
+ ov7740->contrast = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_CONTRAST,
+ 0, 127, 1, 0x20);
+ ov7740->saturation = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_SATURATION, 0, 256, 1, 0x80);
+ ov7740->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_HFLIP, 0, 1, 1, 0);
+ ov7740->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_VFLIP, 0, 1, 1, 0);
+ ov7740->gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_GAIN, 0, 1023, 1, 500);
+ ov7740->auto_gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
+ ov7740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
+ V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
+ ov7740->auto_exposure = v4l2_ctrl_new_std_menu(ctrl_hdlr,
+ &ov7740_ctrl_ops,
+ V4L2_CID_EXPOSURE_AUTO,
+ V4L2_EXPOSURE_MANUAL, 0,
+ V4L2_EXPOSURE_AUTO);
+
+ ov7740->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
+ ov7740->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
+
+ v4l2_ctrl_auto_cluster(3, &ov7740->auto_wb, 0, false);
+ v4l2_ctrl_auto_cluster(2, &ov7740->auto_gain, 0, true);
+ v4l2_ctrl_auto_cluster(2, &ov7740->auto_exposure,
+ V4L2_EXPOSURE_MANUAL, false);
+ v4l2_ctrl_cluster(2, &ov7740->hflip);
+
+ ret = v4l2_ctrl_handler_setup(ctrl_hdlr);
+ if (ret) {
+ dev_err(&client->dev, "%s control init failed (%d)\n",
+ __func__, ret);
+ goto error;
+ }
+
+ ov7740->subdev.ctrl_handler = ctrl_hdlr;
+ return 0;
+
+error:
+ v4l2_ctrl_handler_free(ctrl_hdlr);
+ mutex_destroy(&ov7740->mutex);
+ return ret;
+}
+
+static void ov7740_free_controls(struct ov7740 *ov7740)
+{
+ v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
+ mutex_destroy(&ov7740->mutex);
+}
+
+#define OV7740_MAX_REGISTER 0xff
+static const struct regmap_config ov7740_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+ .max_register = OV7740_MAX_REGISTER,
+};
+
+static int ov7740_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct ov7740 *ov7740;
+ struct v4l2_subdev *sd;
+ int ret;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(&client->dev,
+ "OV7740: I2C-Adapter doesn't support SMBUS\n");
+ return -EIO;
+ }
+
+ ov7740 = devm_kzalloc(&client->dev, sizeof(*ov7740), GFP_KERNEL);
+ if (!ov7740)
+ return -ENOMEM;
+
+ ov7740->xvclk = devm_clk_get(&client->dev, "xvclk");
+ if (IS_ERR(ov7740->xvclk)) {
+ ret = PTR_ERR(ov7740->xvclk);
+ dev_err(&client->dev,
+ "OV7740: fail to get xvclk: %d\n", ret);
+ return ret;
+ }
+
+ ret = ov7740_probe_dt(client, ov7740);
+ if (ret)
+ return ret;
+
+ ov7740->regmap = devm_regmap_init_i2c(client, &ov7740_regmap_config);
+ if (IS_ERR(ov7740->regmap)) {
+ ret = PTR_ERR(ov7740->regmap);
+ dev_err(&client->dev, "Failed to allocate register map: %d\n",
+ ret);
+ return ret;
+ }
+
+ sd = &ov7740->subdev;
+ client->flags |= I2C_CLIENT_SCCB;
+ v4l2_i2c_subdev_init(sd, client, &ov7740_subdev_ops);
+
+#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
+ sd->internal_ops = &ov7740_subdev_internal_ops;
+ sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+#endif
+
+#if defined(CONFIG_MEDIA_CONTROLLER)
+ ov7740->pad.flags = MEDIA_PAD_FL_SOURCE;
+ sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+ ret = media_entity_pads_init(&sd->entity, 1, &ov7740->pad);
+ if (ret)
+ return ret;
+#endif
+
+ ret = ov7740_set_power(ov7740, 1);
+ if (ret)
+ return ret;
+
+ ret = ov7740_detect(ov7740);
+ if (ret)
+ goto error_detect;
+
+ mutex_init(&ov7740->mutex);
+
+ ret = ov7740_init_controls(ov7740);
+ if (ret)
+ goto error_init_controls;
+
+ v4l_info(client, "chip found @ 0x%02x (%s)\n",
+ client->addr << 1, client->adapter->name);
+
+ ov7740_init_default_format(ov7740);
+
+ ov7740_get_default_format(sd, &ov7740->format);
+
+ ret = v4l2_async_register_subdev(sd);
+ if (ret)
+ goto error_async_register;
+
+ pm_runtime_set_active(&client->dev);
+ pm_runtime_enable(&client->dev);
+ pm_runtime_idle(&client->dev);
+
+ return 0;
+
+error_async_register:
+ v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
+error_init_controls:
+ ov7740_free_controls(ov7740);
+error_detect:
+ ov7740_set_power(ov7740, 0);
+ media_entity_cleanup(&ov7740->subdev.entity);
+
+ return ret;
+}
+
+static int ov7740_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+
+ mutex_destroy(&ov7740->mutex);
+ v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
+#if defined(CONFIG_MEDIA_CONTROLLER)
+ media_entity_cleanup(&ov7740->subdev.entity);
+#endif
+ v4l2_async_unregister_subdev(sd);
+ ov7740_free_controls(ov7740);
+
+ pm_runtime_get_sync(&client->dev);
+ pm_runtime_disable(&client->dev);
+ pm_runtime_set_suspended(&client->dev);
+ pm_runtime_put_noidle(&client->dev);
+
+ ov7740_set_power(ov7740, 0);
+ return 0;
+}
+
+static int __maybe_unused ov7740_runtime_suspend(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+
+ ov7740_set_power(ov7740, 0);
+
+ return 0;
+}
+
+static int __maybe_unused ov7740_runtime_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct v4l2_subdev *sd = i2c_get_clientdata(client);
+ struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
+
+ return ov7740_set_power(ov7740, 1);
+}
+
+static const struct i2c_device_id ov7740_id[] = {
+ { "ov7740", 0 },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(i2c, ov7740_id);
+
+static const struct dev_pm_ops ov7740_pm_ops = {
+ SET_RUNTIME_PM_OPS(ov7740_runtime_suspend, ov7740_runtime_resume, NULL)
+};
+
+static const struct of_device_id ov7740_of_match[] = {
+ {.compatible = "ovti,ov7740", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ov7740_of_match);
+
+static struct i2c_driver ov7740_i2c_driver = {
+ .driver = {
+ .name = "ov7740",
+ .pm = &ov7740_pm_ops,
+ .of_match_table = of_match_ptr(ov7740_of_match),
+ },
+ .probe = ov7740_probe,
+ .remove = ov7740_remove,
+ .id_table = ov7740_id,
+};
+module_i2c_driver(ov7740_i2c_driver);
+
+MODULE_DESCRIPTION("The V4L2 driver for Omnivision 7740 sensor");
+MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
+MODULE_LICENSE("GPL v2");
--
2.15.0
^ permalink raw reply related
* [PATCH v6 1/2] media: ov7740: Document device tree bindings
From: Wenyou Yang @ 2017-12-04 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204065858.3138-1-wenyou.yang@microchip.com>
Add the device tree binding documentation for the ov7740 sensor driver.
Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
---
Changes in v6: None
Changes in v5: None
Changes in v4: None
Changes in v3:
- Explicitly document the "remote-endpoint" property.
Changes in v2: None
.../devicetree/bindings/media/i2c/ov7740.txt | 47 ++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ov7740.txt
diff --git a/Documentation/devicetree/bindings/media/i2c/ov7740.txt b/Documentation/devicetree/bindings/media/i2c/ov7740.txt
new file mode 100644
index 000000000000..af781c3a5f0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/ov7740.txt
@@ -0,0 +1,47 @@
+* Omnivision OV7740 CMOS image sensor
+
+The Omnivision OV7740 image sensor supports multiple output image
+size, such as VGA, and QVGA, CIF and any size smaller. It also
+supports the RAW RGB and YUV output formats.
+
+The common video interfaces bindings (see video-interfaces.txt) should
+be used to specify link to the image data receiver. The OV7740 device
+node should contain one 'port' child node with an 'endpoint' subnode.
+
+Required Properties:
+- compatible: "ovti,ov7740".
+- reg: I2C slave address of the sensor.
+- clocks: Reference to the xvclk input clock.
+- clock-names: "xvclk".
+
+Optional Properties:
+- reset-gpios: Rreference to the GPIO connected to the reset_b pin,
+ if any. Active low with pull-ip resistor.
+- powerdown-gpios: Reference to the GPIO connected to the pwdn pin,
+ if any. Active high with pull-down resistor.
+
+Endpoint node mandatory properties:
+- remote-endpoint: A phandle to the bus receiver's endpoint node.
+
+Example:
+
+ i2c1: i2c at fc028000 {
+ ov7740: camera at 21 {
+ compatible = "ovti,ov7740";
+ reg = <0x21>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sensor_power &pinctrl_sensor_reset>;
+ clocks = <&isc>;
+ clock-names = "xvclk";
+ assigned-clocks = <&isc>;
+ assigned-clock-rates = <24000000>;
+ reset-gpios = <&pioA 43 GPIO_ACTIVE_LOW>;
+ powerdown-gpios = <&pioA 44 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov7740_0: endpoint {
+ remote-endpoint = <&isc_0>;
+ };
+ };
+ };
+ };
--
2.15.0
^ permalink raw reply related
* [PATCH v6 0/2] media: ov7740: Add a V4L2 sensor-level driver
From: Wenyou Yang @ 2017-12-04 6:58 UTC (permalink / raw)
To: linux-arm-kernel
Add a Video4Linux2 sensor-level driver for the OmniVision OV7740
VGA camera image sensor.
Changes in v6:
- Remove unnecessary #include <linux/init>.
- Remove unnecessary comments and extra newline.
- Add const for some structures.
- Add the check of the return value from regmap_write().
- Simplify the calling of __v4l2_ctrl_handler_setup().
- Add the default format initialization function.
- Integrate the set_power() and enable/disable the clock into
one function.
Changes in v5:
- Squash the driver and MAINTAINERS entry patches to one.
- Precede the driver patch with the bindings patch.
Changes in v4:
- Assign 'val' a initial value to avoid warning: 'val' may be
used uninitialized.
- Rename REG_REG15 to avoid warning: "REG_REG15" redefined.
Changes in v3:
- Explicitly document the "remote-endpoint" property.
- Put the MAINTAINERS change to a separate patch.
Changes in v2:
- Split off the bindings into a separate patch.
- Add a new entry to the MAINTAINERS file.
Wenyou Yang (2):
media: ov7740: Document device tree bindings
media: i2c: Add the ov7740 image sensor driver
.../devicetree/bindings/media/i2c/ov7740.txt | 47 +
MAINTAINERS | 8 +
drivers/media/i2c/Kconfig | 8 +
drivers/media/i2c/Makefile | 1 +
drivers/media/i2c/ov7740.c | 1226 ++++++++++++++++++++
5 files changed, 1290 insertions(+)
create mode 100644 Documentation/devicetree/bindings/media/i2c/ov7740.txt
create mode 100644 drivers/media/i2c/ov7740.c
--
2.15.0
^ permalink raw reply
* [PATCH v5 2/2] media: i2c: Add the ov7740 image sensor driver
From: Yang, Wenyou @ 2017-12-04 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171128120617.hmqbodu2usrtmkao@valkosipuli.retiisi.org.uk>
Hi Sakari,
Sorry for late answer.
Thank you for your review.
On 2017/11/28 20:06, Sakari Ailus wrote:
> Hi Wenyou,
>
> Thanks for the patch. Some comments below.
>
> On Tue, Nov 28, 2017 at 01:22:59PM +0800, Wenyou Yang wrote:
>> The ov7740 (color) image sensor is a high performance VGA CMOS
>> image snesor, which supports for output formats: RAW RGB and YUV
>> and image sizes: VGA, and QVGA, CIF and any size smaller.
>>
>> Signed-off-by: Songjun Wu <songjun.wu@microchip.com>
>> Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
>> ---
>>
>> Changes in v5:
>> - Squash the driver and MAINTAINERS entry patches to one.
>> - Precede the driver patch with the bindings patch.
>>
>> Changes in v4:
>> - Assign 'val' a initial value to avoid warning: 'val' may be
>> used uninitialized.
>> - Rename REG_REG15 to avoid warning: "REG_REG15" redefined.
>>
>> Changes in v3:
>> - Put the MAINTAINERS change to a separate patch.
>>
>> Changes in v2:
>> - Split off the bindings into a separate patch.
>> - Add a new entry to the MAINTAINERS file.
>>
>> MAINTAINERS | 8 +
>> drivers/media/i2c/Kconfig | 8 +
>> drivers/media/i2c/Makefile | 1 +
>> drivers/media/i2c/ov7740.c | 1220 ++++++++++++++++++++++++++++++++++++++++++++
>> 4 files changed, 1237 insertions(+)
>> create mode 100644 drivers/media/i2c/ov7740.c
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index aa71ab52fd76..19086a073ae9 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -10053,6 +10053,14 @@ S: Maintained
>> F: drivers/media/i2c/ov7670.c
>> F: Documentation/devicetree/bindings/media/i2c/ov7670.txt
>>
>> +OMNIVISION OV7740 SENSOR DRIVER
>> +M: Wenyou Yang <wenyou.yang@microchip.com>
>> +L: linux-media at vger.kernel.org
>> +T: git git://linuxtv.org/media_tree.git
>> +S: Maintained
>> +F: drivers/media/i2c/ov7740.c
>> +F: Documentation/devicetree/bindings/media/i2c/ov7740.txt
>> +
>> ONENAND FLASH DRIVER
>> M: Kyungmin Park <kyungmin.park@samsung.com>
>> L: linux-mtd at lists.infradead.org
>> diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
>> index 3c6d6428f525..ac484bb82fae 100644
>> --- a/drivers/media/i2c/Kconfig
>> +++ b/drivers/media/i2c/Kconfig
>> @@ -665,6 +665,14 @@ config VIDEO_OV7670
>> OV7670 VGA camera. It currently only works with the M88ALP01
>> controller.
>>
>> +config VIDEO_OV7740
>> + tristate "OmniVision OV7740 sensor support"
>> + depends on I2C && VIDEO_V4L2
>> + depends on MEDIA_CAMERA_SUPPORT
>> + ---help---
>> + This is a Video4Linux2 sensor-level driver for the OmniVision
>> + OV7740 VGA camera sensor.
>> +
>> config VIDEO_OV9650
>> tristate "OmniVision OV9650/OV9652 sensor support"
>> depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
>> diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
>> index 548a9efce966..9b19ec7fcaf4 100644
>> --- a/drivers/media/i2c/Makefile
>> +++ b/drivers/media/i2c/Makefile
>> @@ -68,6 +68,7 @@ obj-$(CONFIG_VIDEO_OV5670) += ov5670.o
>> obj-$(CONFIG_VIDEO_OV6650) += ov6650.o
>> obj-$(CONFIG_VIDEO_OV7640) += ov7640.o
>> obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
>> +obj-$(CONFIG_VIDEO_OV7740) += ov7740.o
>> obj-$(CONFIG_VIDEO_OV9650) += ov9650.o
>> obj-$(CONFIG_VIDEO_OV13858) += ov13858.o
>> obj-$(CONFIG_VIDEO_MT9M032) += mt9m032.o
>> diff --git a/drivers/media/i2c/ov7740.c b/drivers/media/i2c/ov7740.c
>> new file mode 100644
>> index 000000000000..b2ec015bf3f6
>> --- /dev/null
>> +++ b/drivers/media/i2c/ov7740.c
>> @@ -0,0 +1,1220 @@
>> +/*
>> + * Copyright (c) 2017 Microchip Corporation.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License version
>> + * 2 as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + *
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/gpio.h>
>> +#include <linux/i2c.h>
>> +#include <linux/init.h>
> Do you need init.h?
No, will remove it.
>
>> +#include <linux/module.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/regmap.h>
>> +#include <media/v4l2-ctrls.h>
>> +#include <media/v4l2-event.h>
>> +#include <media/v4l2-image-sizes.h>
>> +#include <media/v4l2-subdev.h>
>> +
>> +#define REG_OUTSIZE_LSB 0x34
>> +
>> +/* OV7740 register tables */
>> +#define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
>> +#define REG_BGAIN 0x01 /* blue gain */
>> +#define REG_RGAIN 0x02 /* red gain */
>> +#define REG_GGAIN 0x03 /* green gain */
>> +#define REG_REG04 0x04 /* analog setting, dont change*/
>> +#define REG_BAVG 0x05 /* b channel average */
>> +#define REG_GAVG 0x06 /* g channel average */
>> +#define REG_RAVG 0x07 /* r channel average */
>> +
>> +#define REG_REG0C 0x0C /* filp enable */
>> +#define REG0C_IMG_FLIP 0x80
>> +#define REG0C_IMG_MIRROR 0x40
>> +
>> +#define REG_REG0E 0x0E /* blc line */
>> +#define REG_HAEC 0x0F /* auto exposure cntrl */
>> +#define REG_AEC 0x10 /* auto exposure cntrl */
>> +
>> +#define REG_CLK 0x11 /* Clock control */
>> +#define REG_REG55 0x55 /* Clock PLL DIV/PreDiv */
>> +
>> +#define REG_REG12 0x12
>> +
>> +#define REG_REG13 0x13 /* auto/manual AGC, AEC, Write Balance*/
>> +#define REG13_AEC_EN 0x01
>> +#define REG13_AGC_EN 0x04
>> +
>> +#define REG_REG14 0x14
>> +#define REG_CTRL15 0x15
>> +#define REG15_GAIN_MSB 0x03
>> +
>> +#define REG_REG16 0x16
>> +
>> +#define REG_MIDH 0x1C /* manufacture id byte */
>> +#define REG_MIDL 0x1D /* manufacture id byre */
>> +#define REG_PIDH 0x0A /* Product ID MSB */
>> +#define REG_PIDL 0x0B /* Product ID LSB */
>> +
>> +#define REG_84 0x84 /* lots of stuff */
>> +#define REG_REG38 0x38 /* sub-addr */
>> +
>> +#define REG_AHSTART 0x17 /* Horiz start high bits */
>> +#define REG_AHSIZE 0x18
>> +#define REG_AVSTART 0x19 /* Vert start high bits */
>> +#define REG_AVSIZE 0x1A
>> +#define REG_PSHFT 0x1b /* Pixel delay after HREF */
>> +
>> +#define REG_HOUTSIZE 0x31
>> +#define REG_VOUTSIZE 0x32
>> +#define REG_HVSIZEOFF 0x33
>> +#define REG_REG34 0x34 /* DSP output size H/V LSB*/
>> +
>> +#define REG_ISP_CTRL00 0x80
>> +#define ISPCTRL00_AWB_EN 0x10
>> +#define ISPCTRL00_AWB_GAIN_EN 0x04
>> +
>> +#define REG_YGAIN 0xE2 /* ygain for contrast control */
>> +
>> +#define REG_YBRIGHT 0xE3
>> +#define REG_SGNSET 0xE4
>> +#define SGNSET_YBRIGHT_MASK 0x08
>> +
>> +#define REG_USAT 0xDD
>> +#define REG_VSAT 0xDE
>> +
>> +
>> +struct ov7740 {
>> + struct v4l2_subdev subdev;
>> +#if defined(CONFIG_MEDIA_CONTROLLER)
>> + struct media_pad pad;
>> +#endif
>> + struct v4l2_mbus_framefmt format;
>> + struct ov7740_pixfmt *fmt; /* Current format */
>> + struct ov7740_framesize *frmsize;
>> + struct regmap *regmap;
>> + struct clk *xvclk;
>> + struct v4l2_ctrl_handler ctrl_handler;
>> + struct {
>> + /* gain cluster */
>> + struct v4l2_ctrl *auto_gain;
>> + struct v4l2_ctrl *gain;
>> + };
>> + struct {
>> + struct v4l2_ctrl *auto_wb;
>> + struct v4l2_ctrl *blue_balance;
>> + struct v4l2_ctrl *red_balance;
>> + };
>> + struct {
>> + struct v4l2_ctrl *hflip;
>> + struct v4l2_ctrl *vflip;
>> + };
>> + struct {
>> + /* exposure cluster */
>> + struct v4l2_ctrl *auto_exposure;
>> + struct v4l2_ctrl *exposure;
>> + };
>> + struct {
>> + /* saturation/hue cluster */
>> + struct v4l2_ctrl *saturation;
>> + struct v4l2_ctrl *hue;
>> + };
>> + struct v4l2_ctrl *brightness;
>> + struct v4l2_ctrl *contrast;
>> +
>> + struct mutex mutex; /* To serialize asynchronus callbacks */
>> + bool streaming; /* Streaming on/off */
>> +
>> + struct gpio_desc *resetb_gpio;
>> + struct gpio_desc *pwdn_gpio;
>> +};
>> +
>> +struct ov7740_pixfmt {
>> + u32 mbus_code;
>> + enum v4l2_colorspace colorspace;
>> + const struct reg_sequence *regs;
>> + u32 reg_num;
>> +};
>> +
>> +struct ov7740_framesize {
>> + u16 width;
>> + u16 height;
>> + const struct reg_sequence *regs;
>> + u32 reg_num;
>> +};
>> +
> Are the register lists below for a particular external clock frequency?
>
>> +static const struct reg_sequence ov7740_vga[] = {
>> + {0x55, 0x40},
>> + {0x11, 0x02},
>> +
>> + {0xd5, 0x10},
>> + {0x0c, 0x12},
>> + {0x0d, 0x34},
>> + {0x17, 0x25},
>> + {0x18, 0xa0},
>> + {0x19, 0x03},
>> + {0x1a, 0xf0},
>> + {0x1b, 0x89},
>> + {0x22, 0x03},
>> + {0x29, 0x18},
>> + {0x2b, 0xf8},
>> + {0x2c, 0x01},
>> + {REG_HOUTSIZE, 0xa0},
>> + {REG_VOUTSIZE, 0xf0},
>> + {0x33, 0xc4},
>> + {REG_OUTSIZE_LSB, 0x0},
>> + {0x35, 0x05},
>> + //{0x36, 0x3f},
> Why?
Sorry, forgot to remove.
>
>> + {0x04, 0x60},
>> + {0x27, 0x80},
>> + {0x3d, 0x0f},
>> + {0x3e, 0x80},
>> + {0x3f, 0x40},
>> + {0x40, 0x7f},
>> + {0x41, 0x6a},
>> + {0x42, 0x29},
>> + {0x44, 0x22},
>> + {0x45, 0x41},
>> + {0x47, 0x02},
>> + {0x49, 0x64},
>> + {0x4a, 0xa1},
>> + {0x4b, 0x40},
>> + {0x4c, 0x1a},
>> + {0x4d, 0x50},
>> + {0x4e, 0x13},
>> + {0x64, 0x00},
>> + {0x67, 0x88},
>> + {0x68, 0x1a},
>> +
>> + {0x14, 0x28},
>> + {0x24, 0x3c},
>> + {0x25, 0x30},
>> + {0x26, 0x72},
>> + {0x50, 0x97},
>> + {0x51, 0x1f},
>> + {0x52, 0x00},
>> + {0x53, 0x00},
>> + {0x20, 0x00},
>> + {0x21, 0xcf},
>> + {0x50, 0x4b},
>> + {0x38, 0x14},
>> + {0xe9, 0x00},
>> + {0x56, 0x55},
>> + {0x57, 0xff},
>> + {0x58, 0xff},
>> + {0x59, 0xff},
>> + {0x5f, 0x04},
>> + {0xec, 0x00},
>> + {0x13, 0xff},
>> +
>> + //{0x80,0x7f},
>> + {0x81, 0x3f},
>> + {0x82, 0x32},
>> + //{0x83, 0x01},
> Yes, but why?
>
>> + {0x38, 0x11},
>> + {0x84, 0x70},
>> + {0x85, 0x00},
>> + {0x86, 0x03},
>> + {0x87, 0x01},
>> + {0x88, 0x05},
>> + {0x89, 0x30},
>> + {0x8d, 0x30},
>> + {0x8f, 0x85},
>> + {0x93, 0x30},
>> + {0x95, 0x85},
>> + {0x99, 0x30},
>> + {0x9b, 0x85},
>> +
>> + {0x9c, 0x08},
>> + {0x9d, 0x12},
>> + {0x9e, 0x23},
>> + {0x9f, 0x45},
>> + {0xa0, 0x55},
>> + {0xa1, 0x64},
>> + {0xa2, 0x72},
>> + {0xa3, 0x7f},
>> + {0xa4, 0x8b},
>> + {0xa5, 0x95},
>> + {0xa6, 0xa7},
>> + {0xa7, 0xb5},
>> + {0xa8, 0xcb},
>> + {0xa9, 0xdd},
>> + {0xaa, 0xec},
>> + {0xab, 0x1a},
>> +
>> + {0xce, 0x78},
>> + {0xcf, 0x6e},
>> + {0xd0, 0x0a},
>> + {0xd1, 0x0c},
>> + {0xd2, 0x84},
>> + {0xd3, 0x90},
>> + {0xd4, 0x1e},
>> +
>> + {0x5a, 0x24},
>> + {0x5b, 0x1f},
>> + {0x5c, 0x88},
>> + {0x5d, 0x60},
>> +
>> + {0xac, 0x6e},
>> + {0xbe, 0xff},
>> + {0xbf, 0x00},
>> +
>> + {0x0f, 0x1d},
>> + {0x0f, 0x1f},
>> +};
>> +
>> +static struct ov7740_framesize ov7740_framesizes[] = {
> const?
>
> Same for a number of structs below.
Yes, will add const.
>
>> + {
>> + .width = VGA_WIDTH,
>> + .height = VGA_HEIGHT,
>> + .regs = ov7740_vga,
>> + .reg_num = ARRAY_SIZE(ov7740_vga),
>> + },
>> +};
>> +
>> +#ifdef CONFIG_VIDEO_ADV_DEBUG
>> +static int ov7740_get_register(struct v4l2_subdev *sd,
>> + struct v4l2_dbg_register *reg)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> + struct regmap *regmap = ov7740->regmap;
>> + unsigned int val = 0;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, reg->reg & 0xff, &val);
>> + reg->val = val;
>> + reg->size = 1;
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_set_register(struct v4l2_subdev *sd,
>> + const struct v4l2_dbg_register *reg)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> + struct regmap *regmap = ov7740->regmap;
>> +
>> + regmap_write(regmap, reg->reg & 0xff, reg->val & 0xff);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static int ov7740_set_power(struct v4l2_subdev *sd, int on)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> +
>> + if (ov7740->pwdn_gpio)
>> + gpiod_direction_output(ov7740->pwdn_gpio, !on);
>> + if (on && ov7740->resetb_gpio) {
>> + gpiod_set_value(ov7740->resetb_gpio, 1);
>> + usleep_range(500, 1000);
>> + gpiod_set_value(ov7740->resetb_gpio, 0);
>> + usleep_range(3000, 5000);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static struct v4l2_subdev_core_ops ov7740_subdev_core_ops = {
>> + .log_status = v4l2_ctrl_subdev_log_status,
>> +#ifdef CONFIG_VIDEO_ADV_DEBUG
>> + .g_register = ov7740_get_register,
>> + .s_register = ov7740_set_register,
>> +#endif
>> + .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
>> + .unsubscribe_event = v4l2_event_subdev_unsubscribe,
>> +};
>> +
>> +static int ov7740_set_white_balance(struct ov7740 *ov7740, int awb)
>> +{
>> + struct regmap *regmap = ov7740->regmap;
>> + unsigned int value;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, REG_ISP_CTRL00, &value);
>> + if (!ret) {
>> + if (awb)
>> + value |= (ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
>> + else
>> + value &= ~(ISPCTRL00_AWB_EN | ISPCTRL00_AWB_GAIN_EN);
>> + ret = regmap_write(regmap, REG_ISP_CTRL00, value);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + if (!awb) {
>> + ret = regmap_write(regmap, REG_BGAIN,
>> + ov7740->blue_balance->val);
>> + if (ret)
>> + return ret;
>> +
>> + ret = regmap_write(regmap, REG_RGAIN, ov7740->red_balance->val);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_set_saturation(struct regmap *regmap, int value)
>> +{
>> + int ret;
>> +
>> + ret = regmap_write(regmap, REG_USAT, (unsigned char)value);
> ret is not checked.
Will add the check.
>
>> + ret = regmap_write(regmap, REG_VSAT, (unsigned char)value);
>> +
>> + return ret;
>> +}
>> +
>> +static int ov7740_set_gain(struct regmap *regmap, int value)
>> +{
>> + int ret;
>> +
>> + ret = regmap_write(regmap, REG_GAIN, value & 0xff);
>> + if (ret)
>> + return ret;
>> +
>> + ret = regmap_update_bits(regmap, REG_CTRL15,
>> + REG15_GAIN_MSB, (value >> 8) & 0x3);
>> + if (!ret)
>> + ret = regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
>> +
>> + return ret;
>> +}
>> +
>> +static int ov7740_set_autogain(struct regmap *regmap, int value)
>> +{
>> + unsigned int reg;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, REG_REG13, ®);
>> + if (ret)
>> + return ret;
>> + if (value)
>> + reg |= REG13_AGC_EN;
>> + else
>> + reg &= ~REG13_AGC_EN;
>> + return regmap_write(regmap, REG_REG13, reg);
>> +}
>> +
>> +static int ov7740_set_brightness(struct regmap *regmap, int value)
>> +{
>> + /* Turn off AEC/AGC */
>> + regmap_update_bits(regmap, REG_REG13, REG13_AEC_EN, 0);
>> + regmap_update_bits(regmap, REG_REG13, REG13_AGC_EN, 0);
>> +
>> + if (value >= 0) {
>> + regmap_write(regmap, REG_YBRIGHT, (unsigned char)value);
>> + regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 0);
>> + } else{
>> + regmap_write(regmap, REG_YBRIGHT, (unsigned char)(-value));
>> + regmap_update_bits(regmap, REG_SGNSET, SGNSET_YBRIGHT_MASK, 1);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_set_contrast(struct regmap *regmap, int value)
>> +{
>> + return regmap_write(regmap, REG_YGAIN, (unsigned char)value);
>> +}
>> +
>> +static int ov7740_get_gain(struct ov7740 *ov7740, struct v4l2_ctrl *ctrl)
>> +{
>> + struct regmap *regmap = ov7740->regmap;
>> + unsigned int value0, value1;
>> + int ret;
>> +
>> + if (!ctrl->val)
>> + return 0;
>> +
>> + ret = regmap_read(regmap, REG_GAIN, &value0);
>> + if (ret)
>> + return ret;
>> + ret = regmap_read(regmap, REG_CTRL15, &value1);
>> + if (ret)
>> + return ret;
>> +
>> + ov7740->gain->val = (value1 << 8) | (value0 & 0xff);
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_set_exp(struct regmap *regmap, int value)
>> +{
>> + int ret;
>> +
>> + /* Turn off AEC/AGC */
>> + ret = regmap_update_bits(regmap, REG_REG13,
>> + REG13_AEC_EN | REG13_AGC_EN, 0);
>> + if (ret)
>> + return ret;
>> +
>> + ret = regmap_write(regmap, REG_AEC, (unsigned char)value);
>> + if (ret)
>> + return ret;
>> +
>> + return regmap_write(regmap, REG_HAEC, (unsigned char)(value >> 8));
>> +}
>> +
>> +static int ov7740_set_autoexp(struct regmap *regmap,
>> + enum v4l2_exposure_auto_type value)
>> +{
>> + unsigned int reg;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, REG_REG13, ®);
>> + if (!ret) {
>> + if (value == V4L2_EXPOSURE_AUTO)
>> + reg |= (REG13_AEC_EN | REG13_AGC_EN);
>> + else
>> + reg &= ~(REG13_AEC_EN | REG13_AGC_EN);
>> + ret = regmap_write(regmap, REG_REG13, reg);
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +
>> +static int ov7740_get_volatile_ctrl(struct v4l2_ctrl *ctrl)
>> +{
>> + struct ov7740 *ov7740 = container_of(ctrl->handler,
>> + struct ov7740, ctrl_handler);
>> + int ret;
>> +
>> + switch (ctrl->id) {
>> + case V4L2_CID_AUTOGAIN:
>> + ret = ov7740_get_gain(ov7740, ctrl);
>> + break;
>> + default:
>> + ret = -EINVAL;
>> + break;
>> + }
>> + return ret;
>> +}
>> +
>> +static int ov7740_set_ctrl(struct v4l2_ctrl *ctrl)
>> +{
>> + struct ov7740 *ov7740 = container_of(ctrl->handler,
>> + struct ov7740, ctrl_handler);
>> + struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
>> + struct regmap *regmap = ov7740->regmap;
>> + int ret;
>> + u8 val = 0;
>> +
>> + if (pm_runtime_get_if_in_use(&client->dev) <= 0)
>> + return 0;
>> +
>> + switch (ctrl->id) {
>> + case V4L2_CID_AUTO_WHITE_BALANCE:
>> + ret = ov7740_set_white_balance(ov7740, ctrl->val);
>> + break;
>> + case V4L2_CID_SATURATION:
>> + ret = ov7740_set_saturation(regmap, ctrl->val);
>> + break;
>> + case V4L2_CID_BRIGHTNESS:
>> + ret = ov7740_set_brightness(regmap, ctrl->val);
>> + break;
>> + case V4L2_CID_CONTRAST:
>> + ret = ov7740_set_contrast(regmap, ctrl->val);
>> + break;
>> + case V4L2_CID_VFLIP:
>> + ret = regmap_update_bits(regmap, REG_REG0C,
>> + REG0C_IMG_FLIP, val);
>> + break;
>> + case V4L2_CID_HFLIP:
>> + val = ctrl->val ? REG0C_IMG_MIRROR : 0x00;
>> + ret = regmap_update_bits(regmap, REG_REG0C,
>> + REG0C_IMG_MIRROR, val);
>> + break;
>> + case V4L2_CID_AUTOGAIN:
>> + if (!ctrl->val)
>> + return ov7740_set_gain(regmap, ov7740->gain->val);
>> +
>> + ret = ov7740_set_autogain(regmap, ctrl->val);
>> + break;
>> +
>> + case V4L2_CID_EXPOSURE_AUTO:
>> + if (ctrl->val == V4L2_EXPOSURE_MANUAL)
>> + return ov7740_set_exp(regmap, ov7740->exposure->val);
>> +
>> + ret = ov7740_set_autoexp(regmap, ctrl->val);
>> + break;
>> + default:
>> + ret = -EINVAL;
>> + break;
>> + }
>> +
>> + pm_runtime_put(&client->dev);
>> +
>> + return ret;
>> +}
>> +
>> +static const struct v4l2_ctrl_ops ov7740_ctrl_ops = {
>> + .g_volatile_ctrl = ov7740_get_volatile_ctrl,
>> + .s_ctrl = ov7740_set_ctrl,
>> +};
>> +
>> +static int ov7740_start_streaming(struct ov7740 *ov7740)
>> +{
>> + int ret;
>> +
>> + /* Apply customized values from user */
>> + ret = __v4l2_ctrl_handler_setup(ov7740->subdev.ctrl_handler);
>> + if (ret)
>> + return ret;
> return __v4l2_ctrl_handler_setup(...);
Right.
>
> You could as well move this to where it's being called, there's a single
> instance.
>
> That would make it easier to see that the sensor is probably starting the
> stream based on its power on or mode register list. Shouldn't you set the
> controls before starting streaming?
>
>> +
>> + return 0;
>> +}
>> +static int ov7740_set_stream(struct v4l2_subdev *sd, int enable)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> + struct i2c_client *client = v4l2_get_subdevdata(sd);
>> + int ret = 0;
>> +
>> + mutex_lock(&ov7740->mutex);
>> + if (ov7740->streaming == enable) {
>> + mutex_unlock(&ov7740->mutex);
>> + return 0;
>> + }
>> +
>> + if (enable) {
>> + ret = pm_runtime_get_sync(&client->dev);
>> + if (ret < 0) {
>> + pm_runtime_put_noidle(&client->dev);
>> + goto err_unlock;
>> + }
>> +
>> + ret = ov7740_start_streaming(ov7740);
>> + if (ret)
>> + goto err_rpm_put;
>> + } else {
>> + pm_runtime_put(&client->dev);
>> + }
>> +
>> + ov7740->streaming = enable;
>> +
>> + mutex_unlock(&ov7740->mutex);
>> + return ret;
>> +
>> +err_rpm_put:
>> + pm_runtime_put(&client->dev);
>> +err_unlock:
>> + mutex_unlock(&ov7740->mutex);
>> + return ret;
>> +}
>> +
>> +static int ov7740_get_parm(struct v4l2_subdev *sd,
>> + struct v4l2_streamparm *parms)
>> +{
>> + struct v4l2_captureparm *cp = &parms->parm.capture;
>> + struct v4l2_fract *tpf = &cp->timeperframe;
>> +
>> + if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
>> + return -EINVAL;
>> +
>> + memset(cp, 0, sizeof(struct v4l2_captureparm));
>> + cp->capability = V4L2_CAP_TIMEPERFRAME;
>> +
>> + tpf->numerator = 1;
>> + tpf->denominator = 60;
> You implement also [gs]_frame_interval in pad ops. Do you have a need for
> this?
No,? don't need.
>
> It'd be better if sensor drivers just implemented one of these APIs to
> select the frame interval ([gs]_frame_interval), not both.
>
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_set_parm(struct v4l2_subdev *sd,
>> + struct v4l2_streamparm *parms)
>> +{
>> + struct v4l2_captureparm *cp = &parms->parm.capture;
>> + struct v4l2_fract *tpf = &cp->timeperframe;
>> +
>> + if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
>> + return -EINVAL;
>> + if (cp->extendedmode != 0)
>> + return -EINVAL;
>> +
>> + cp->capability = V4L2_CAP_TIMEPERFRAME;
>> +
>> + tpf->numerator = 1;
>> + tpf->denominator = 60;
>> +
>> + return 0;
>> +}
>> +
>> +static struct v4l2_subdev_video_ops ov7740_subdev_video_ops = {
> const?
>
>> + .s_stream = ov7740_set_stream,
>> + .s_parm = ov7740_set_parm,
>> + .g_parm = ov7740_get_parm,
>> +};
>> +
>> +static const struct reg_sequence ov7740_format_yuyv[] = {
>> + {0x12, 0x00},
>> + {0x36, 0x3f},
>> + {0x80, 0x7f},
>> + {0x83, 0x01},
>> +};
>> +
>> +static const struct reg_sequence ov7740_format_bggr8[] = {
>> + {0x36, 0x2f},
>> + {0x80, 0x01},
>> + {0x83, 0x04},
>> +};
>> +
>> +static struct ov7740_pixfmt ov7740_formats[] = {
>> + {
>> + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
>> + .colorspace = V4L2_COLORSPACE_SRGB,
>> + .regs = ov7740_format_yuyv,
>> + .reg_num = ARRAY_SIZE(ov7740_format_yuyv),
>> + },
>> + {
>> + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
>> + .colorspace = V4L2_COLORSPACE_SRGB,
>> + .regs = ov7740_format_bggr8,
>> + .reg_num = ARRAY_SIZE(ov7740_format_bggr8),
>> + }
>> +};
>> +#define N_OV7740_FMTS ARRAY_SIZE(ov7740_formats)
>> +
>> +static int ov7740_enum_mbus_code(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_mbus_code_enum *code)
>> +{
>> + if (code->pad || code->index >= N_OV7740_FMTS)
>> + return -EINVAL;
>> +
>> + code->code = ov7740_formats[code->index].mbus_code;
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_enum_frame_interval(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_frame_interval_enum *fie)
>> +{
>> + if (fie->pad)
>> + return -EINVAL;
>> +
>> + if (fie->index >= 1)
>> + return -EINVAL;
>> +
>> + if ((fie->width != VGA_WIDTH) || (fie->height != VGA_HEIGHT))
>> + return -EINVAL;
>> +
>> + fie->interval.numerator = 1;
>> + fie->interval.denominator = 60;
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_enum_frame_size(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_frame_size_enum *fse)
>> +{
>> + if (fse->pad)
>> + return -EINVAL;
>> +
>> + if (fse->index > 0)
>> + return -EINVAL;
>> +
>> + fse->min_width = fse->max_width = VGA_WIDTH;
>> + fse->min_height = fse->max_height = VGA_HEIGHT;
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_try_fmt_internal(struct v4l2_subdev *sd,
>> + struct v4l2_mbus_framefmt *fmt,
>> + struct ov7740_pixfmt **ret_fmt,
>> + struct ov7740_framesize **ret_frmsize)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> + struct ov7740_framesize *fsize = &ov7740_framesizes[0];
>> + int index, i;
>> +
>> + for (index = 0; index < N_OV7740_FMTS; index++) {
>> + if (ov7740_formats[index].mbus_code == fmt->code)
>> + break;
>> + }
>> + if (index >= N_OV7740_FMTS) {
>> + /* default to first format */
>> + index = 0;
>> + fmt->code = ov7740_formats[0].mbus_code;
>> + }
>> + if (ret_fmt != NULL)
>> + *ret_fmt = ov7740_formats + index;
>> +
>> + for (i = 0; i < ARRAY_SIZE(ov7740_framesizes); i++) {
>> + if ((fsize->width >= fmt->width) &&
>> + (fsize->height >= fmt->height)) {
>> + fmt->width = fsize->width;
>> + fmt->height = fsize->height;
>> + break;
>> + }
>> +
>> + fsize++;
>> + }
>> +
>> + if (ret_frmsize != NULL)
>> + *ret_frmsize = fsize;
>> +
>> + fmt->field = V4L2_FIELD_NONE;
>> + fmt->colorspace = ov7740_formats[index].colorspace;
>> +
>> + ov7740->format = *fmt;
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_set_fmt(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_format *format)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> + struct ov7740_pixfmt *ovfmt;
>> + struct ov7740_framesize *fsize;
>> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
>> + struct v4l2_mbus_framefmt *mbus_fmt;
>> +#endif
>> + int ret;
>> +
>> + mutex_lock(&ov7740->mutex);
>> + if (format->pad) {
>> + ret = -EINVAL;
>> + goto error;
>> + }
>> +
>> + if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
>> + ret = ov7740_try_fmt_internal(sd, &format->format, NULL, NULL);
>> + if (ret)
>> + goto error;
>> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
>> + mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
>> + *mbus_fmt = format->format;
>> +
>> + mutex_unlock(&ov7740->mutex);
>> + return 0;
>> +#else
>> + ret = -ENOTTY;
>> + goto error;
>> +#endif
>> + }
>> +
>> + ret = ov7740_try_fmt_internal(sd, &format->format, &ovfmt, &fsize);
>> + if (ret)
>> + goto error;
>> +
>> + if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
>> + regmap_multi_reg_write(ov7740->regmap,
>> + ovfmt->regs, ovfmt->reg_num);
> What if streaming is started without calling set_fmt after the device is
> powered on?
>
> These should probably be written when streaming is started.
Right, add the default format initialization function.
>
>> +
>> + regmap_multi_reg_write(ov7740->regmap,
>> + fsize->regs, fsize->reg_num);
>> + }
>> +
>> + ov7740->fmt = ovfmt;
>> +
>> + mutex_unlock(&ov7740->mutex);
>> + return 0;
>> +
>> +error:
>> + mutex_unlock(&ov7740->mutex);
>> + return ret;
>> +}
>> +
>> +static int ov7740_get_fmt(struct v4l2_subdev *sd,
>> + struct v4l2_subdev_pad_config *cfg,
>> + struct v4l2_subdev_format *format)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
>> + struct v4l2_mbus_framefmt *mbus_fmt;
>> +#endif
>> + int ret = 0;
>> +
>> + mutex_lock(&ov7740->mutex);
>> + if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
>> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
>> + mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
>> + format->format = *mbus_fmt;
>> + ret = 0;
>> +#else
>> + ret = -ENOTTY;
>> +#endif
>> + } else {
>> + format->format = ov7740->format;
>> + }
>> + mutex_unlock(&ov7740->mutex);
>> +
>> + return ret;
>> +}
>> +
>> +static const struct v4l2_subdev_pad_ops ov7740_subdev_pad_ops = {
>> + .enum_frame_interval = ov7740_enum_frame_interval,
>> + .enum_frame_size = ov7740_enum_frame_size,
>> + .enum_mbus_code = ov7740_enum_mbus_code,
>> + .get_fmt = ov7740_get_fmt,
>> + .set_fmt = ov7740_set_fmt,
>> +};
>> +
>> +static struct v4l2_subdev_ops ov7740_subdev_ops = {
>> + .core = &ov7740_subdev_core_ops,
>> + .video = &ov7740_subdev_video_ops,
>> + .pad = &ov7740_subdev_pad_ops,
>> +};
>> +
>> +static void ov7740_get_default_format(struct v4l2_subdev *sd,
>> + struct v4l2_mbus_framefmt *format)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> +
>> + format->width = ov7740->frmsize->width;
>> + format->height = ov7740->frmsize->height;
>> + format->colorspace = ov7740->fmt->colorspace;
>> + format->code = ov7740->fmt->mbus_code;
>> + format->field = V4L2_FIELD_NONE;
>> +}
>> +
>> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
>> +static int ov7740_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
>> +{
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> + struct v4l2_mbus_framefmt *format =
>> + v4l2_subdev_get_try_format(sd, fh->pad, 0);
>> +
>> + mutex_lock(&ov7740->mutex);
>> + ov7740_get_default_format(sd, format);
>> + mutex_unlock(&ov7740->mutex);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct v4l2_subdev_internal_ops ov7740_subdev_internal_ops = {
>> + .open = ov7740_open,
>> +};
>> +#endif
>> +
>> +static int ov7740_probe_dt(struct i2c_client *client,
>> + struct ov7740 *ov7740)
>> +{
>> + ov7740->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
>> + GPIOD_OUT_LOW);
>> + if (IS_ERR(ov7740->resetb_gpio)) {
>> + dev_info(&client->dev, "can't get %s GPIO\n", "reset");
>> + return PTR_ERR(ov7740->resetb_gpio);
>> + }
>> +
>> + ov7740->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
>> + GPIOD_OUT_HIGH);
>> + if (IS_ERR(ov7740->pwdn_gpio)) {
>> + dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
>> + return PTR_ERR(ov7740->pwdn_gpio);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_detect(struct ov7740 *ov7740)
>> +{
>> + struct regmap *regmap = ov7740->regmap;
>> + unsigned int midh, midl, pidh, pidl;
>> + int ret;
>> +
>> + ret = regmap_read(regmap, REG_MIDH, &midh);
>> + if (ret)
>> + return ret;
>> + if (midh != 0x7f)
>> + return -ENODEV;
>> +
>> + ret = regmap_read(regmap, REG_MIDL, &midl);
>> + if (ret)
>> + return ret;
>> + if (midl != 0xa2)
>> + return -ENODEV;
>> +
>> + ret = regmap_read(regmap, REG_PIDH, &pidh);
>> + if (ret)
>> + return ret;
>> + if (pidh != 0x77)
>> + return -ENODEV;
>> +
>> + ret = regmap_read(regmap, REG_PIDL, &pidl);
>> + if (ret)
>> + return ret;
>> + if ((pidl != 0x40) && (pidl != 0x41) && (pidl != 0x42))
>> + return -ENODEV;
>> +
>> + return 0;
>> +}
>> +
>> +static int ov7740_init_controls(struct ov7740 *ov7740)
>> +{
>> + struct i2c_client *client = v4l2_get_subdevdata(&ov7740->subdev);
>> + struct v4l2_ctrl_handler *ctrl_hdlr = &ov7740->ctrl_handler;
>> + int ret;
>> +
>> + ret = v4l2_ctrl_handler_init(ctrl_hdlr, 2);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ctrl_hdlr->lock = &ov7740->mutex;
>> + ov7740->auto_wb = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_AUTO_WHITE_BALANCE,
>> + 0, 1, 1, 1);
>> + ov7740->blue_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_BLUE_BALANCE,
>> + 0, 0xff, 1, 0x80);
>> + ov7740->red_balance = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_RED_BALANCE,
>> + 0, 0xff, 1, 0x80);
>> +
>> + ov7740->brightness = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_BRIGHTNESS,
>> + -255, 255, 1, 0);
>> + ov7740->contrast = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_CONTRAST,
>> + 0, 127, 1, 0x20);
>> + ov7740->saturation = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_SATURATION, 0, 256, 1, 0x80);
>> + ov7740->hflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_HFLIP, 0, 1, 1, 0);
>> + ov7740->vflip = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_VFLIP, 0, 1, 1, 0);
>> + ov7740->gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_GAIN, 0, 1023, 1, 500);
>> + ov7740->auto_gain = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
>> + ov7740->exposure = v4l2_ctrl_new_std(ctrl_hdlr, &ov7740_ctrl_ops,
>> + V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
>> + ov7740->auto_exposure = v4l2_ctrl_new_std_menu(ctrl_hdlr,
>> + &ov7740_ctrl_ops,
>> + V4L2_CID_EXPOSURE_AUTO,
>> + V4L2_EXPOSURE_MANUAL, 0,
>> + V4L2_EXPOSURE_AUTO);
>> +
>> + ov7740->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
>> + ov7740->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
>> +
>> + v4l2_ctrl_auto_cluster(3, &ov7740->auto_wb, 0, false);
>> + v4l2_ctrl_auto_cluster(2, &ov7740->auto_gain, 0, true);
>> + v4l2_ctrl_auto_cluster(2, &ov7740->auto_exposure,
>> + V4L2_EXPOSURE_MANUAL, false);
>> + v4l2_ctrl_cluster(2, &ov7740->hflip);
>> +
>> + ret = v4l2_ctrl_handler_setup(ctrl_hdlr);
>> + if (ret) {
>> + dev_err(&client->dev, "%s control init failed (%d)\n",
>> + __func__, ret);
>> + goto error;
>> + }
>> +
>> + ov7740->subdev.ctrl_handler = ctrl_hdlr;
>> + return 0;
>> +
>> +error:
>> + v4l2_ctrl_handler_free(ctrl_hdlr);
>> + mutex_destroy(&ov7740->mutex);
>> + return ret;
>> +}
>> +
>> +static void ov7740_free_controls(struct ov7740 *ov7740)
>> +{
>> + v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
>> + mutex_destroy(&ov7740->mutex);
>> +}
>> +
>> +#define OV7740_MAX_REGISTER 0xff
>> +static const struct regmap_config ov7740_regmap_config = {
>> + .reg_bits = 8,
>> + .val_bits = 8,
>> + .max_register = OV7740_MAX_REGISTER,
>> +};
>> +
>> +static int ov7740_probe(struct i2c_client *client,
>> + const struct i2c_device_id *id)
>> +{
>> + struct ov7740 *ov7740;
>> + struct v4l2_subdev *sd;
>> + int ret;
>> +
>> + if (!i2c_check_functionality(client->adapter,
>> + I2C_FUNC_SMBUS_BYTE_DATA)) {
>> + dev_err(&client->dev,
>> + "OV7740: I2C-Adapter doesn't support SMBUS\n");
>> + return -EIO;
>> + }
>> +
>> + ov7740 = devm_kzalloc(&client->dev, sizeof(*ov7740), GFP_KERNEL);
>> + if (!ov7740)
>> + return -ENOMEM;
>> +
>> + ov7740->xvclk = devm_clk_get(&client->dev, "xvclk");
>> + if (IS_ERR(ov7740->xvclk)) {
>> + ret = PTR_ERR(ov7740->xvclk);
>> + dev_err(&client->dev,
>> + "OV7740: fail to get xvclk: %d\n", ret);
>> + return ret;
>> + }
>> +
>> + ret = ov7740_probe_dt(client, ov7740);
>> + if (ret)
>> + return ret;
>> +
>> + ret = clk_prepare_enable(ov7740->xvclk);
>> + if (ret)
>> + return ret;
>> +
>> + ov7740->regmap = devm_regmap_init_i2c(client, &ov7740_regmap_config);
>> + if (IS_ERR(ov7740->regmap)) {
>> + ret = PTR_ERR(ov7740->regmap);
>> + dev_err(&client->dev, "Failed to allocate register map: %d\n",
>> + ret);
>> + goto error_regmap_init;
>> + }
>> +
>> + sd = &ov7740->subdev;
>> + client->flags |= I2C_CLIENT_SCCB;
>> + v4l2_i2c_subdev_init(sd, client, &ov7740_subdev_ops);
>> +
>> +#ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
>> + sd->internal_ops = &ov7740_subdev_internal_ops;
>> + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
>> +#endif
>> +
>> +#if defined(CONFIG_MEDIA_CONTROLLER)
>> + ov7740->pad.flags = MEDIA_PAD_FL_SOURCE;
>> + sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
>> + ret = media_entity_pads_init(&sd->entity, 1, &ov7740->pad);
>> + if (ret)
>> + goto error_regmap_init;
>> +#endif
>> +
>> + ov7740_set_power(sd, 1);
>> +
>> + ret = ov7740_detect(ov7740);
>> + if (ret)
>> + goto error_detect;
>> +
>> + mutex_init(&ov7740->mutex);
>> +
>> + ret = ov7740_init_controls(ov7740);
>> + if (ret)
>> + goto error_init_controls;
>> +
>> + v4l_info(client, "chip found @ 0x%02x (%s)\n",
>> + client->addr << 1, client->adapter->name);
>> +
>> + ov7740->fmt = &ov7740_formats[0];
>> + ov7740->frmsize = &ov7740_framesizes[0];
>> +
>> + ov7740_get_default_format(sd, &ov7740->format);
>> +
>> + ret = v4l2_async_register_subdev(sd);
>> + if (ret)
>> + goto error_async_register;
>> +
>> + pm_runtime_get_noresume(&client->dev);
>> + pm_runtime_set_active(&client->dev);
>> + pm_runtime_enable(&client->dev);
>> + pm_runtime_put(&client->dev);
> You can use pm_runtime_idle() to replace get_noresume + put.
>
>> +
>> + return 0;
>> +
>> +error_async_register:
>> + v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
>> +error_init_controls:
>> + ov7740_free_controls(ov7740);
>> + ov7740_set_power(sd, 0);
>> +error_detect:
> ov7740_set_power(sd, 0) here?
Right.
>
>> + media_entity_cleanup(&ov7740->subdev.entity);
>> +error_regmap_init:
>> + clk_disable_unprepare(ov7740->xvclk);
>> +
>> + return ret;
>> +}
>> +
>> +static int ov7740_remove(struct i2c_client *client)
>> +{
>> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> +
>> + clk_disable_unprepare(ov7740->xvclk);
>> + mutex_destroy(&ov7740->mutex);
>> + v4l2_ctrl_handler_free(ov7740->subdev.ctrl_handler);
>> +#if defined(CONFIG_MEDIA_CONTROLLER)
>> + media_entity_cleanup(&ov7740->subdev.entity);
>> +#endif
>> + v4l2_async_unregister_subdev(sd);
>> + ov7740_free_controls(ov7740);
>> +
>> + pm_runtime_get_sync(&client->dev);
>> + pm_runtime_disable(&client->dev);
>> + pm_runtime_set_suspended(&client->dev);
>> + pm_runtime_put_noidle(&client->dev);
> ov7740_set_power(sd, 0) if the device was suspended.
>
> I'd think the smiapp driver does this generally right. Think about how this
> works if runtime PM is disabled.
Yes. I will improve them in the future.
>
>> +
>> + return 0;
>> +}
>> +
>> +static int __maybe_unused ov7740_runtime_suspend(struct device *dev)
>> +{
>> + struct i2c_client *client = to_i2c_client(dev);
>> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> +
>> + clk_disable_unprepare(ov7740->xvclk);
>> + ov7740_set_power(sd, 0);
> How about moving clock control to ov7740_set_power()? Clock and the GPIOs
> appear to be always controller together, aren't they?
Yes, it is better.
Will get them together.
>
>> +
>> + return 0;
>> +}
>> +
>> +static int __maybe_unused ov7740_runtime_resume(struct device *dev)
>> +{
>> + struct i2c_client *client = to_i2c_client(dev);
>> + struct v4l2_subdev *sd = i2c_get_clientdata(client);
>> + struct ov7740 *ov7740 = container_of(sd, struct ov7740, subdev);
>> +
>> + ov7740_set_power(sd, 1);
>> + return clk_prepare_enable(ov7740->xvclk);
>> +}
>> +
>> +static const struct i2c_device_id ov7740_id[] = {
>> + { "ov7740", 0 },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(i2c, ov7740_id);
>> +
>> +static const struct dev_pm_ops ov7740_pm_ops = {
>> + SET_RUNTIME_PM_OPS(ov7740_runtime_suspend, ov7740_runtime_resume, NULL)
>> +};
>> +
>> +static const struct of_device_id ov7740_of_match[] = {
>> + {.compatible = "ovti,ov7740", },
>> + { /* sentinel */ },
>> +};
>> +MODULE_DEVICE_TABLE(of, ov7740_of_match);
>> +
> Extra newline.
>
>> +
>> +static struct i2c_driver ov7740_i2c_driver = {
>> + .driver = {
>> + .name = "ov7740",
>> + .pm = &ov7740_pm_ops,
>> + .of_match_table = of_match_ptr(ov7740_of_match),
>> + },
>> + .probe = ov7740_probe,
>> + .remove = ov7740_remove,
>> + .id_table = ov7740_id,
>> +};
>> +module_i2c_driver(ov7740_i2c_driver);
>> +
>> +MODULE_DESCRIPTION("The V4L2 driver for Omnivision 7740 sensor");
>> +MODULE_AUTHOR("Songjun Wu <songjun.wu@atmel.com>");
>> +MODULE_LICENSE("GPL v2");
Best Regards,
Wenyou Yang
^ permalink raw reply
* [PATCH 2/9] ASoC: sun4i-i2s: Add compatibility with A64 codec I2S
From: Code Kipper @ 2017-12-04 6:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171203204157.20829-3-anarsoul@gmail.com>
On 3 December 2017 at 21:41, Vasily Khoruzhick <anarsoul@gmail.com> wrote:
> From: Marcus Cooper <codekipper@gmail.com>
>
> The I2S block used for the audio codec in the A64 is very similar
> to what is used by the A10(sun4i) devices. However, its TX FIFO is
> located at a different address.
>
> [vasilykh: - added fixed_wss and wss_value to A64 quirks,
> - changed compatible to 'allwinner,sun50i-a64-acodec-i2s,
> since A64 has 3 more I2S blocks that are not compatible
> with audio codec I2S]
>
> Signed-off-by: Marcus Cooper <codekipper@gmail.com>
> Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
> ---
> .../devicetree/bindings/sound/sun4i-i2s.txt | 2 ++
> sound/soc/sunxi/sun4i-i2s.c | 23 ++++++++++++++++++++++
> 2 files changed, 25 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
> index 05d7135a8d2f..ab86f266962a 100644
> --- a/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
> +++ b/Documentation/devicetree/bindings/sound/sun4i-i2s.txt
> @@ -9,6 +9,7 @@ Required properties:
> - "allwinner,sun4i-a10-i2s"
> - "allwinner,sun6i-a31-i2s"
> - "allwinner,sun8i-h3-i2s"
> + - "allwinner,sun50i-a64-acodec-i2s"
> - reg: physical base address of the controller and length of memory mapped
> region.
> - interrupts: should contain the I2S interrupt.
> @@ -24,6 +25,7 @@ Required properties:
> Required properties for the following compatibles:
> - "allwinner,sun6i-a31-i2s"
> - "allwinner,sun8i-h3-i2s"
> + - "allwinner,sun50i-a64-acodec-i2s"
I would keep the compatible format the same. ie.
allwinner,sun50i-a64-i2s. The A33 for example uses the sun6i-a31-i2s
for it's dai.
> - resets: phandle to the reset line for this codec
>
> Example:
> diff --git a/sound/soc/sunxi/sun4i-i2s.c b/sound/soc/sunxi/sun4i-i2s.c
> index 54c16eb64713..2c060e015725 100644
> --- a/sound/soc/sunxi/sun4i-i2s.c
> +++ b/sound/soc/sunxi/sun4i-i2s.c
> @@ -942,6 +942,25 @@ static const struct sun4i_i2s_quirks sun8i_h3_i2s_quirks = {
> .field_rxchansel = REG_FIELD(SUN8I_I2S_RX_CHAN_SEL_REG, 0, 2),
> };
>
> +static const struct sun4i_i2s_quirks sun50i_a64_acodec_i2s_quirks = {
ditto
> + .has_reset = true,
> + .reg_offset_txdata = SUN8I_I2S_FIFO_TX_REG,
> + .sun4i_i2s_regmap = &sun4i_i2s_regmap_config,
> + .has_slave_select_bit = true,
> + .fixed_wss = true,
> + .wss_value = 3,
> + .field_clkdiv_mclk_en = REG_FIELD(SUN4I_I2S_CLK_DIV_REG, 7, 7),
> + .field_fmt_wss = REG_FIELD(SUN4I_I2S_FMT0_REG, 2, 3),
> + .field_fmt_sr = REG_FIELD(SUN4I_I2S_FMT0_REG, 4, 5),
> + .field_fmt_bclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 6, 6),
> + .field_fmt_lrclk = REG_FIELD(SUN4I_I2S_FMT0_REG, 7, 7),
> + .field_fmt_mode = REG_FIELD(SUN4I_I2S_FMT0_REG, 0, 1),
> + .field_txchanmap = REG_FIELD(SUN4I_I2S_TX_CHAN_MAP_REG, 0, 31),
> + .field_rxchanmap = REG_FIELD(SUN4I_I2S_RX_CHAN_MAP_REG, 0, 31),
> + .field_txchansel = REG_FIELD(SUN4I_I2S_TX_CHAN_SEL_REG, 0, 2),
> + .field_rxchansel = REG_FIELD(SUN4I_I2S_RX_CHAN_SEL_REG, 0, 2),
> +};
> +
> static int sun4i_i2s_init_regmap_fields(struct device *dev,
> struct sun4i_i2s *i2s)
> {
> @@ -1146,6 +1165,10 @@ static const struct of_device_id sun4i_i2s_match[] = {
> .compatible = "allwinner,sun8i-h3-i2s",
> .data = &sun8i_h3_i2s_quirks,
> },
> + {
> + .compatible = "allwinner,sun50i-a64-acodec-i2s",
> + .data = &sun50i_a64_acodec_i2s_quirks,
ditto
BR,
CK
> + },
> {}
> };
> MODULE_DEVICE_TABLE(of, sun4i_i2s_match);
> --
> 2.15.0
>
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