* [PATCH v2 2/5] mm: memory_hotplug: Remove assumption on memory state before hotremove
From: Rafael J. Wysocki @ 2017-12-04 14:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204112855.GA6373@samekh>
On Mon, Dec 4, 2017 at 12:28 PM, Andrea Reale <ar@linux.vnet.ibm.com> wrote:
> Hi Joey,
>
> and thanks for your comments. Response inline:
>
[cut]
>>
>> So, the BUG() is useful to capture state issue in memory subsystem. But, I
>> understood your concern about the two steps offline/remove from userland.
>>
>> Maybe we should move the BUG() to somewhere but not just remove it. Or if
>> we think that the BUG() is too intense, at least we should print out a error
>> message, and ACPI should checks the return value from subsystem to
>> interrupt memory-hotplug process.
>
> In this patchset, BUG() is moved to acpi_memory_remove_memory(),
> the caller of arch_remove_memory(). However, I agree with Michal, that
> we should not BUG() here but rather halt the hotremove process and print
> some errors.
> Is there any state in ACPI that should be undone in case of hotremove
> errors or we can just stop the process "halfway"?
I have to recall a couple of things before answering this question, so
that may take some time.
Thanks,
Rafael
^ permalink raw reply
* [PATCH] irqchip/gic-v3: Fix the driver probe() fail due to disabled GICC entry
From: Shanker Donthineni @ 2017-12-04 14:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8a926bff-f8aa-220c-85f0-9d39ec5bef4b@arm.com>
Hi Thanks,
On 12/04/2017 04:28 AM, Marc Zyngier wrote:
> On 03/12/17 23:21, Shanker Donthineni wrote:
>> As per MADT specification, it's perfectly valid firmware can pass
>> MADT table to OS with disabled GICC entries. ARM64-SMP code skips
>> those cpu cores to bring online. However the current GICv3 driver
>> probe bails out in this case on systems where redistributor regions
>> are not in the always-on power domain.
>>
>> This patch does the two things to fix the panic.
>> - Don't return an error in gic_acpi_match_gicc() for disabled GICC.
>> - No need to keep GICR region information for disabled GICC.
>>
>> Kernel crash traces:
>> Kernel panic - not syncing: No interrupt controller found.
>> CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.13.5 #26
>> [<ffff000008087770>] dump_backtrace+0x0/0x218
>> [<ffff0000080879dc>] show_stack+0x14/0x20
>> [<ffff00000883b078>] dump_stack+0x98/0xb8
>> [<ffff0000080c5c14>] panic+0x118/0x26c
>> [<ffff000008b62348>] init_IRQ+0x24/0x2c
>> [<ffff000008b609fc>] start_kernel+0x230/0x394
>> [<ffff000008b601e4>] __primary_switched+0x64/0x6c
>> ---[ end Kernel panic - not syncing: No interrupt controller found.
>>
>> Disabled GICC subtable example:
>> Subtable Type : 0B [Generic Interrupt Controller]
>> Length : 50
>> Reserved : 0000
>> CPU Interface Number : 0000003D
>> Processor UID : 0000003D
>> Flags (decoded below) : 00000000
>> Processor Enabled : 0
>> Performance Interrupt Trig Mode : 0
>> Virtual GIC Interrupt Trig Mode : 0
>> Parking Protocol Version : 00000000
>> Performance Interrupt : 00000017
>> Parked Address : 0000000000000000
>> Base Address : 0000000000000000
>> Virtual GIC Base Address : 0000000000000000
>> Hypervisor GIC Base Address : 0000000000000000
>> Virtual GIC Interrupt : 00000019
>> Redistributor Base Address : 0000FFFF88F40000
>> ARM MPIDR : 000000000000000D
>> Efficiency Class : 00
>> Reserved : 000000
>>
>> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
>> ---
>> drivers/irqchip/irq-gic-v3.c | 14 +++++++++-----
>> 1 file changed, 9 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>> index b56c3e2..a30fbac 100644
>> --- a/drivers/irqchip/irq-gic-v3.c
>> +++ b/drivers/irqchip/irq-gic-v3.c
>> @@ -1331,6 +1331,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
>> u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
>> void __iomem *redist_base;
>>
>> + /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
>> + if (!(gicc->flags & ACPI_MADT_ENABLED))
>> + return 0;
>> +
>> redist_base = ioremap(gicc->gicr_base_address, size);
>> if (!redist_base)
>> return -ENOMEM;
>> @@ -1374,13 +1378,13 @@ static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
>> (struct acpi_madt_generic_interrupt *)header;
>>
>> /*
>> - * If GICC is enabled and has valid gicr base address, then it means
>> - * GICR base is presented via GICC
>> + * If GICC is enabled and has not valid gicr base address, then it means
>> + * GICR base is not presented via GICC
>> */
>> - if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
>> - return 0;
>> + if ((gicc->flags & ACPI_MADT_ENABLED) && (!gicc->gicr_base_address))
>> + return -ENODEV;
>
> This doesn't feel quite right. It would mean that having the ENABLED
> flag cleared and potentially no address would make it valid? It looks to
> me that the original code is "less wrong".
>
> What am I missing?
>
Original definition of the function gic_acpi_match_gicc().
{
if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
return 0;
return -ENODEV;
}
Above code triggers the driver probe fail for the two reasons.
1) GICC with ACPI_MADT_ENABLED=0, it's a bug according to ACPI spec.
2) GICC with ACPI_MADT_ENABLED=1 and invalid GICR address, expected.
This patch fix the first failed case and keep the second case intact.
if ((gicc->flags & ACPI_MADT_ENABLED) && (!gicc->gicr_base_address))
return -ENODEV;
return 0;
> Thanks,
>
> M.
>
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PULL 19/19] KVM: arm/arm64: Fix broken GICH_ELRSR big endian conversion
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Christoffer Dall <christoffer.dall@linaro.org>
We are incorrectly rearranging 32-bit words inside a 64-bit typed value
for big endian systems, which would result in never marking a virtual
interrupt as inactive on big endian systems (assuming 32 or fewer LRs on
the hardware). Fix this by not doing any word order manipulation for
the typed values.
Cc: <stable@vger.kernel.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/hyp/vgic-v2-sr.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/virt/kvm/arm/hyp/vgic-v2-sr.c b/virt/kvm/arm/hyp/vgic-v2-sr.c
index a3f18d362366..d7fd46fe9efb 100644
--- a/virt/kvm/arm/hyp/vgic-v2-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v2-sr.c
@@ -34,11 +34,7 @@ static void __hyp_text save_elrsr(struct kvm_vcpu *vcpu, void __iomem *base)
else
elrsr1 = 0;
-#ifdef CONFIG_CPU_BIG_ENDIAN
- cpu_if->vgic_elrsr = ((u64)elrsr0 << 32) | elrsr1;
-#else
cpu_if->vgic_elrsr = ((u64)elrsr1 << 32) | elrsr0;
-#endif
}
static void __hyp_text save_lrs(struct kvm_vcpu *vcpu, void __iomem *base)
--
2.14.2
^ permalink raw reply related
* [PULL 18/19] KVM: arm/arm64: kvm_arch_destroy_vm cleanups
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Andrew Jones <drjones@redhat.com>
kvm_vgic_vcpu_destroy already gets called from kvm_vgic_destroy for
each vcpu, so we don't have to call it from kvm_arch_vcpu_free.
Additionally the other architectures set kvm->online_vcpus to zero
after freeing them. We might as well do that for ARM too.
Signed-off-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/arm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
index ca65d06b38a8..675844c2174a 100644
--- a/virt/kvm/arm/arm.c
+++ b/virt/kvm/arm/arm.c
@@ -188,6 +188,7 @@ void kvm_arch_destroy_vm(struct kvm *kvm)
kvm->vcpus[i] = NULL;
}
}
+ atomic_set(&kvm->online_vcpus, 0);
}
int kvm_vm_ioctl_check_extension(struct kvm *kvm, long ext)
@@ -296,7 +297,6 @@ void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
{
kvm_mmu_free_memory_caches(vcpu);
kvm_timer_vcpu_terminate(vcpu);
- kvm_vgic_vcpu_destroy(vcpu);
kvm_pmu_vcpu_destroy(vcpu);
kvm_vcpu_uninit(vcpu);
kmem_cache_free(kvm_vcpu_cache, vcpu);
--
2.14.2
^ permalink raw reply related
* [PULL 17/19] KVM: arm/arm64: Fix spinlock acquisition in vgic_set_owner
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Marc Zyngier <marc.zyngier@arm.com>
vgic_set_owner acquires the irq lock without disabling interrupts,
resulting in a lockdep splat (an interrupt could fire and result
in the same lock being taken if the same virtual irq is to be
injected).
In practice, it is almost impossible to trigger this bug, but
better safe than sorry. Convert the lock acquisition to a
spin_lock_irqsave() and keep lockdep happy.
Reported-by: James Morse <james.morse@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index 786cce7bd2ec..ecb8e25f5fe5 100644
--- a/virt/kvm/arm/vgic/vgic.c
+++ b/virt/kvm/arm/vgic/vgic.c
@@ -492,6 +492,7 @@ int kvm_vgic_unmap_phys_irq(struct kvm_vcpu *vcpu, unsigned int vintid)
int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner)
{
struct vgic_irq *irq;
+ unsigned long flags;
int ret = 0;
if (!vgic_initialized(vcpu->kvm))
@@ -502,12 +503,12 @@ int kvm_vgic_set_owner(struct kvm_vcpu *vcpu, unsigned int intid, void *owner)
return -EINVAL;
irq = vgic_get_irq(vcpu->kvm, vcpu, intid);
- spin_lock(&irq->irq_lock);
+ spin_lock_irqsave(&irq->irq_lock, flags);
if (irq->owner && irq->owner != owner)
ret = -EEXIST;
else
irq->owner = owner;
- spin_unlock(&irq->irq_lock);
+ spin_unlock_irqrestore(&irq->irq_lock, flags);
return ret;
}
--
2.14.2
^ permalink raw reply related
* [PULL 16/19] kvm: arm: don't treat unavailable HYP mode as an error
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Since it is perfectly legal to run the kernel at EL1, it is not
actually an error if HYP mode is not available when attempting to
initialize KVM, given that KVM support cannot be built as a module.
So demote the kvm_err() to kvm_info(), which prevents the error from
appearing on an otherwise 'quiet' console.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/arm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
index 322c570d211e..ca65d06b38a8 100644
--- a/virt/kvm/arm/arm.c
+++ b/virt/kvm/arm/arm.c
@@ -1507,7 +1507,7 @@ int kvm_arch_init(void *opaque)
bool in_hyp_mode;
if (!is_hyp_mode_available()) {
- kvm_err("HYP mode not available\n");
+ kvm_info("HYP mode not available\n");
return -ENODEV;
}
--
2.14.2
^ permalink raw reply related
* [PULL 15/19] KVM: arm/arm64: Avoid attempting to load timer vgic state without a vgic
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Christoffer Dall <christoffer.dall@linaro.org>
The timer optimization patches inadvertendly changed the logic to always
load the timer state as if we have a vgic, even if we don't have a vgic.
Fix this by doing the usual irqchip_in_kernel() check and call the
appropriate load function.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/arch_timer.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 190c99ed1b73..f9555b1e7f15 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -835,7 +835,10 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
no_vgic:
preempt_disable();
timer->enabled = 1;
- kvm_timer_vcpu_load_vgic(vcpu);
+ if (!irqchip_in_kernel(vcpu->kvm))
+ kvm_timer_vcpu_load_user(vcpu);
+ else
+ kvm_timer_vcpu_load_vgic(vcpu);
preempt_enable();
return 0;
--
2.14.2
^ permalink raw reply related
* [PULL 14/19] kvm: arm64: handle single-step of hyp emulated mmio instructions
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Alex Benn?e <alex.bennee@linaro.org>
There is a fast-path of MMIO emulation inside hyp mode. The handling
of single-step is broadly the same as kvm_arm_handle_step_debug()
except we just setup ESR/HSR so handle_exit() does the correct thing
as we exit.
For the case of an emulated illegal access causing an SError we will
exit via the ARM_EXCEPTION_EL1_SERROR path in handle_exit(). We behave
as we would during a real SError and clear the DBG_SPSR_SS bit for the
emulated instruction.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
arch/arm64/kvm/hyp/switch.c | 37 ++++++++++++++++++++++++++++++-------
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
index 525c01f48867..f7c651f3a8c0 100644
--- a/arch/arm64/kvm/hyp/switch.c
+++ b/arch/arm64/kvm/hyp/switch.c
@@ -22,6 +22,7 @@
#include <asm/kvm_emulate.h>
#include <asm/kvm_hyp.h>
#include <asm/fpsimd.h>
+#include <asm/debug-monitors.h>
static bool __hyp_text __fpsimd_enabled_nvhe(void)
{
@@ -269,7 +270,11 @@ static bool __hyp_text __populate_fault_info(struct kvm_vcpu *vcpu)
return true;
}
-static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
+/* Skip an instruction which has been emulated. Returns true if
+ * execution can continue or false if we need to exit hyp mode because
+ * single-step was in effect.
+ */
+static bool __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
{
*vcpu_pc(vcpu) = read_sysreg_el2(elr);
@@ -282,6 +287,14 @@ static void __hyp_text __skip_instr(struct kvm_vcpu *vcpu)
}
write_sysreg_el2(*vcpu_pc(vcpu), elr);
+
+ if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
+ vcpu->arch.fault.esr_el2 =
+ (ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT) | 0x22;
+ return false;
+ } else {
+ return true;
+ }
}
int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
@@ -342,13 +355,21 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
int ret = __vgic_v2_perform_cpuif_access(vcpu);
if (ret == 1) {
- __skip_instr(vcpu);
- goto again;
+ if (__skip_instr(vcpu))
+ goto again;
+ else
+ exit_code = ARM_EXCEPTION_TRAP;
}
if (ret == -1) {
- /* Promote an illegal access to an SError */
- __skip_instr(vcpu);
+ /* Promote an illegal access to an
+ * SError. If we would be returning
+ * due to single-step clear the SS
+ * bit so handle_exit knows what to
+ * do after dealing with the error.
+ */
+ if (!__skip_instr(vcpu))
+ *vcpu_cpsr(vcpu) &= ~DBG_SPSR_SS;
exit_code = ARM_EXCEPTION_EL1_SERROR;
}
@@ -363,8 +384,10 @@ int __hyp_text __kvm_vcpu_run(struct kvm_vcpu *vcpu)
int ret = __vgic_v3_perform_cpuif_access(vcpu);
if (ret == 1) {
- __skip_instr(vcpu);
- goto again;
+ if (__skip_instr(vcpu))
+ goto again;
+ else
+ exit_code = ARM_EXCEPTION_TRAP;
}
/* 0 falls through to be handled out of EL2 */
--
2.14.2
^ permalink raw reply related
* [PULL 13/19] kvm: arm64: handle single-step during SError exceptions
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Alex Benn?e <alex.bennee@linaro.org>
When an SError arrives during single-step both the SError and debug
exceptions may be pending when the step is completed, and the
architecture doesn't define the ordering of the two. This means that we
can observe en SError even though we've just completed a step, without
receiving a debug exception. In that case the DBG_SPSR_SS bit will have
flipped as the instruction executed. After handling the abort in
handle_exit() we test to see if the bit is clear and we were
single-stepping before deciding if we need to exit to user space.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
arch/arm64/kvm/handle_exit.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index 029c28dd25e9..304203fa9e33 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -28,6 +28,7 @@
#include <asm/kvm_emulate.h>
#include <asm/kvm_mmu.h>
#include <asm/kvm_psci.h>
+#include <asm/debug-monitors.h>
#define CREATE_TRACE_POINTS
#include "trace.h"
@@ -252,7 +253,12 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
return 1;
case ARM_EXCEPTION_EL1_SERROR:
kvm_inject_vabt(vcpu);
- return 1;
+ /* We may still need to return for single-step */
+ if (!(*vcpu_cpsr(vcpu) & DBG_SPSR_SS)
+ && kvm_arm_handle_step_debug(vcpu, run))
+ return 0;
+ else
+ return 1;
case ARM_EXCEPTION_TRAP:
return handle_trap_exceptions(vcpu, run);
case ARM_EXCEPTION_HYP_GONE:
--
2.14.2
^ permalink raw reply related
* [PULL 12/19] kvm: arm64: handle single-step of userspace mmio instructions
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Alex Benn?e <alex.bennee@linaro.org>
The system state of KVM when using userspace emulation is not complete
until we return into KVM_RUN. To handle mmio related updates we wait
until they have been committed and then schedule our KVM_EXIT_DEBUG.
The kvm_arm_handle_step_debug() helper tells us if we need to return
and sets up the exit_reason for us.
Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/arm.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
index a6524ff27de4..322c570d211e 100644
--- a/virt/kvm/arm/arm.c
+++ b/virt/kvm/arm/arm.c
@@ -628,6 +628,9 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
ret = kvm_handle_mmio_return(vcpu, vcpu->run);
if (ret)
return ret;
+ if (kvm_arm_handle_step_debug(vcpu, vcpu->run))
+ return 0;
+
}
if (run->immediate_exit)
--
2.14.2
^ permalink raw reply related
* [PULL 11/19] kvm: arm64: handle single-stepping trapped instructions
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Alex Benn?e <alex.bennee@linaro.org>
If we are using guest debug to single-step the guest, we need to ensure
that we exit after emulating the instruction. This only affects
instructions completely emulated by the kernel. For instructions
emulated in userspace, we need to exit and return to complete the
emulation.
The kvm_arm_handle_step_debug() helper sets up the necessary exit
state if needed.
Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
arch/arm64/kvm/handle_exit.c | 49 +++++++++++++++++++++++++++++++-------------
1 file changed, 35 insertions(+), 14 deletions(-)
diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c
index b71247995469..029c28dd25e9 100644
--- a/arch/arm64/kvm/handle_exit.c
+++ b/arch/arm64/kvm/handle_exit.c
@@ -186,6 +186,40 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
return arm_exit_handlers[hsr_ec];
}
+/*
+ * We may be single-stepping an emulated instruction. If the emulation
+ * has been completed in the kernel, we can return to userspace with a
+ * KVM_EXIT_DEBUG, otherwise userspace needs to complete its
+ * emulation first.
+ */
+static int handle_trap_exceptions(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ int handled;
+
+ /*
+ * See ARM ARM B1.14.1: "Hyp traps on instructions
+ * that fail their condition code check"
+ */
+ if (!kvm_condition_valid(vcpu)) {
+ kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+ handled = 1;
+ } else {
+ exit_handle_fn exit_handler;
+
+ exit_handler = kvm_get_exit_handler(vcpu);
+ handled = exit_handler(vcpu, run);
+ }
+
+ /*
+ * kvm_arm_handle_step_debug() sets the exit_reason on the kvm_run
+ * structure if we need to return to userspace.
+ */
+ if (handled > 0 && kvm_arm_handle_step_debug(vcpu, run))
+ handled = 0;
+
+ return handled;
+}
+
/*
* Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
* proper exit to userspace.
@@ -193,8 +227,6 @@ static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
int exception_index)
{
- exit_handle_fn exit_handler;
-
if (ARM_SERROR_PENDING(exception_index)) {
u8 hsr_ec = ESR_ELx_EC(kvm_vcpu_get_hsr(vcpu));
@@ -222,18 +254,7 @@ int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
kvm_inject_vabt(vcpu);
return 1;
case ARM_EXCEPTION_TRAP:
- /*
- * See ARM ARM B1.14.1: "Hyp traps on instructions
- * that fail their condition code check"
- */
- if (!kvm_condition_valid(vcpu)) {
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
- return 1;
- }
-
- exit_handler = kvm_get_exit_handler(vcpu);
-
- return exit_handler(vcpu, run);
+ return handle_trap_exceptions(vcpu, run);
case ARM_EXCEPTION_HYP_GONE:
/*
* EL2 has been reset to the hyp-stub. This happens when a guest
--
2.14.2
^ permalink raw reply related
* [PULL 10/19] KVM: arm/arm64: debug: Introduce helper for single-step
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Alex Benn?e <alex.bennee@linaro.org>
After emulating instructions we may want return to user-space to handle
single-step debugging. Introduce a helper function, which, if
single-step is enabled, sets the run structure for return and returns
true.
Signed-off-by: Alex Benn?e <alex.bennee@linaro.org>
Reviewed-by: Julien Thierry <julien.thierry@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
arch/arm/include/asm/kvm_host.h | 5 +++++
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/debug.c | 21 +++++++++++++++++++++
3 files changed, 27 insertions(+)
diff --git a/arch/arm/include/asm/kvm_host.h b/arch/arm/include/asm/kvm_host.h
index 242151ea6908..a9f7d3f47134 100644
--- a/arch/arm/include/asm/kvm_host.h
+++ b/arch/arm/include/asm/kvm_host.h
@@ -285,6 +285,11 @@ static inline void kvm_arm_init_debug(void) {}
static inline void kvm_arm_setup_debug(struct kvm_vcpu *vcpu) {}
static inline void kvm_arm_clear_debug(struct kvm_vcpu *vcpu) {}
static inline void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu) {}
+static inline bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu,
+ struct kvm_run *run)
+{
+ return false;
+}
int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
struct kvm_device_attr *attr);
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 674912d7a571..ea6cb5b24258 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -370,6 +370,7 @@ void kvm_arm_init_debug(void);
void kvm_arm_setup_debug(struct kvm_vcpu *vcpu);
void kvm_arm_clear_debug(struct kvm_vcpu *vcpu);
void kvm_arm_reset_debug_ptr(struct kvm_vcpu *vcpu);
+bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run);
int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu,
struct kvm_device_attr *attr);
int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu,
diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c
index dbadfaf850a7..fa63b28c65e0 100644
--- a/arch/arm64/kvm/debug.c
+++ b/arch/arm64/kvm/debug.c
@@ -221,3 +221,24 @@ void kvm_arm_clear_debug(struct kvm_vcpu *vcpu)
}
}
}
+
+
+/*
+ * After successfully emulating an instruction, we might want to
+ * return to user space with a KVM_EXIT_DEBUG. We can only do this
+ * once the emulation is complete, though, so for userspace emulations
+ * we have to wait until we have re-entered KVM before calling this
+ * helper.
+ *
+ * Return true (and set exit_reason) to return to userspace or false
+ * if no further action is required.
+ */
+bool kvm_arm_handle_step_debug(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP) {
+ run->exit_reason = KVM_EXIT_DEBUG;
+ run->debug.arch.hsr = ESR_ELx_EC_SOFTSTP_LOW << ESR_ELx_EC_SHIFT;
+ return true;
+ }
+ return false;
+}
--
2.14.2
^ permalink raw reply related
* [PULL 09/19] arm: KVM: Fix VTTBR_BADDR_MASK BUG_ON off-by-one
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Marc Zyngier <marc.zyngier@arm.com>
VTTBR_BADDR_MASK is used to sanity check the size and alignment of the
VTTBR address. It seems to currently be off by one, thereby only
allowing up to 39-bit addresses (instead of 40-bit) and also
insufficiently checking the alignment. This patch fixes it.
This patch is the 32bit pendent of Kristina's arm64 fix, and
she deserves the actual kudos for pinpointing that one.
Fixes: f7ed45be3ba52 ("KVM: ARM: World-switch implementation")
Cc: <stable@vger.kernel.org> # 3.9
Reported-by: Kristina Martsenko <kristina.martsenko@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
arch/arm/include/asm/kvm_arm.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/kvm_arm.h b/arch/arm/include/asm/kvm_arm.h
index c8781450905b..3ab8b3781bfe 100644
--- a/arch/arm/include/asm/kvm_arm.h
+++ b/arch/arm/include/asm/kvm_arm.h
@@ -161,8 +161,7 @@
#else
#define VTTBR_X (5 - KVM_T0SZ)
#endif
-#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
-#define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_BADDR_MASK (((_AC(1, ULL) << (40 - VTTBR_X)) - 1) << VTTBR_X)
#define VTTBR_VMID_SHIFT _AC(48, ULL)
#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
--
2.14.2
^ permalink raw reply related
* [PULL 08/19] arm64: KVM: fix VTTBR_BADDR_MASK BUG_ON off-by-one
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Kristina Martsenko <kristina.martsenko@arm.com>
VTTBR_BADDR_MASK is used to sanity check the size and alignment of the
VTTBR address. It seems to currently be off by one, thereby only
allowing up to 47-bit addresses (instead of 48-bit) and also
insufficiently checking the alignment. This patch fixes it.
As an example, with 4k pages, before this patch we have:
PHYS_MASK_SHIFT = 48
VTTBR_X = 37 - 24 = 13
VTTBR_BADDR_SHIFT = 13 - 1 = 12
VTTBR_BADDR_MASK = ((1 << 35) - 1) << 12 = 0x00007ffffffff000
Which is wrong, because the mask doesn't allow bit 47 of the VTTBR
address to be set, and only requires the address to be 12-bit (4k)
aligned, while it actually needs to be 13-bit (8k) aligned because we
concatenate two 4k tables.
With this patch, the mask becomes 0x0000ffffffffe000, which is what we
want.
Fixes: 0369f6a34b9f ("arm64: KVM: EL2 register definitions")
Cc: <stable@vger.kernel.org> # 3.11.x
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
arch/arm64/include/asm/kvm_arm.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index 7f069ff37f06..715d395ef45b 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -170,8 +170,7 @@
#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS | VTCR_EL2_TGRAN_FLAGS)
#define VTTBR_X (VTTBR_X_TGRAN_MAGIC - VTCR_EL2_T0SZ_IPA)
-#define VTTBR_BADDR_SHIFT (VTTBR_X - 1)
-#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_BADDR_SHIFT)
+#define VTTBR_BADDR_MASK (((UL(1) << (PHYS_MASK_SHIFT - VTTBR_X)) - 1) << VTTBR_X)
#define VTTBR_VMID_SHIFT (UL(48))
#define VTTBR_VMID_MASK(size) (_AT(u64, (1 << size) - 1) << VTTBR_VMID_SHIFT)
--
2.14.2
^ permalink raw reply related
* [PULL 07/19] KVM: arm/arm64: vgic-v4: Only perform an unmap for valid vLPIs
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Marc Zyngier <marc.zyngier@arm.com>
Before performing an unmap, let's check that what we have was
really mapped the first place.
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic-v4.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-v4.c b/virt/kvm/arm/vgic/vgic-v4.c
index 53c324aa44ef..4a37292855bc 100644
--- a/virt/kvm/arm/vgic/vgic-v4.c
+++ b/virt/kvm/arm/vgic/vgic-v4.c
@@ -337,8 +337,10 @@ int kvm_vgic_v4_unset_forwarding(struct kvm *kvm, int virq,
goto out;
WARN_ON(!(irq->hw && irq->host_irq == virq));
- irq->hw = false;
- ret = its_unmap_vlpi(virq);
+ if (irq->hw) {
+ irq->hw = false;
+ ret = its_unmap_vlpi(virq);
+ }
out:
mutex_unlock(&its->its_lock);
--
2.14.2
^ permalink raw reply related
* [PULL 06/19] KVM: arm/arm64: vgic-its: Check result of allocation before use
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Marc Zyngier <marc.zyngier@arm.com>
We miss a test against NULL after allocation.
Fixes: 6d03a68f8054 ("KVM: arm64: vgic-its: Turn device_id validation into generic ID validation")
Cc: <stable@vger.kernel.org> # 4.8
Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic-its.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index cb2d0a2dbe5a..8e633bd9cc1e 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -821,6 +821,8 @@ static int vgic_its_alloc_collection(struct vgic_its *its,
return E_ITS_MAPC_COLLECTION_OOR;
collection = kzalloc(sizeof(*collection), GFP_KERNEL);
+ if (!collection)
+ return -ENOMEM;
collection->collection_id = coll_id;
collection->target_addr = COLLECTION_NOT_MAPPED;
--
2.14.2
^ permalink raw reply related
* [PULL 05/19] KVM: arm/arm64: vgic-its: Preserve the revious read from the pending table
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Marc Zyngier <marc.zyngier@arm.com>
The current pending table parsing code assumes that we keep the
previous read of the pending bits, but keep that variable in
the current block, making sure it is discarded on each loop.
We end-up using whatever is on the stack. Who knows, it might
just be the right thing...
Fixes: 33d3bc9556a7d ("KVM: arm64: vgic-its: Read initial LPI pending table")
Cc: <stable@vger.kernel.org> # 4.8
Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic-its.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/vgic/vgic-its.c b/virt/kvm/arm/vgic/vgic-its.c
index 1f761a9991e7..cb2d0a2dbe5a 100644
--- a/virt/kvm/arm/vgic/vgic-its.c
+++ b/virt/kvm/arm/vgic/vgic-its.c
@@ -421,6 +421,7 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
u32 *intids;
int nr_irqs, i;
unsigned long flags;
+ u8 pendmask;
nr_irqs = vgic_copy_lpi_list(vcpu, &intids);
if (nr_irqs < 0)
@@ -428,7 +429,6 @@ static int its_sync_lpi_pending_table(struct kvm_vcpu *vcpu)
for (i = 0; i < nr_irqs; i++) {
int byte_offset, bit_nr;
- u8 pendmask;
byte_offset = intids[i] / BITS_PER_BYTE;
bit_nr = intids[i] % BITS_PER_BYTE;
--
2.14.2
^ permalink raw reply related
* [PULL 04/19] KVM: arm/arm64: vgic: Preserve the revious read from the pending table
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Marc Zyngier <marc.zyngier@arm.com>
The current pending table parsing code assumes that we keep the
previous read of the pending bits, but keep that variable in
the current block, making sure it is discarded on each loop.
We end-up using whatever is on the stack. Who knows, it might
just be the right thing...
Fixes: 280771252c1ba ("KVM: arm64: vgic-v3: KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES")
Cc: <stable@vger.kernel.org> # 4.12
Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic-v3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/vgic/vgic-v3.c b/virt/kvm/arm/vgic/vgic-v3.c
index 2f05f732d3fd..f47e8481fa45 100644
--- a/virt/kvm/arm/vgic/vgic-v3.c
+++ b/virt/kvm/arm/vgic/vgic-v3.c
@@ -327,13 +327,13 @@ int vgic_v3_save_pending_tables(struct kvm *kvm)
int last_byte_offset = -1;
struct vgic_irq *irq;
int ret;
+ u8 val;
list_for_each_entry(irq, &dist->lpi_list_head, lpi_list) {
int byte_offset, bit_nr;
struct kvm_vcpu *vcpu;
gpa_t pendbase, ptr;
bool stored;
- u8 val;
vcpu = irq->target_vcpu;
if (!vcpu)
--
2.14.2
^ permalink raw reply related
* [PULL 03/19] KVM: arm/arm64: vgic-irqfd: Fix MSI entry allocation
From: Christoffer Dall @ 2017-12-04 14:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Marc Zyngier <marc.zyngier@arm.com>
Using the size of the structure we're allocating is a good idea
and avoids any surprise... In this case, we're happilly confusing
kvm_kernel_irq_routing_entry and kvm_irq_routing_entry...
Fixes: 95b110ab9a09 ("KVM: arm/arm64: Enable irqchip routing")
Cc: <stable@vger.kernel.org> # 4.8
Reported-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic-irqfd.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-irqfd.c b/virt/kvm/arm/vgic/vgic-irqfd.c
index b7baf581611a..99e026d2dade 100644
--- a/virt/kvm/arm/vgic/vgic-irqfd.c
+++ b/virt/kvm/arm/vgic/vgic-irqfd.c
@@ -112,8 +112,7 @@ int kvm_vgic_setup_default_irq_routing(struct kvm *kvm)
u32 nr = dist->nr_spis;
int i, ret;
- entries = kcalloc(nr, sizeof(struct kvm_kernel_irq_routing_entry),
- GFP_KERNEL);
+ entries = kcalloc(nr, sizeof(*entries), GFP_KERNEL);
if (!entries)
return -ENOMEM;
--
2.14.2
^ permalink raw reply related
* arm64 crashkernel fails to boot on acpi-only machines due to ACPI regions being no longer mapped as NOMAP
From: Ard Biesheuvel @ 2017-12-04 14:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAFTCetQHmpprAVu6uYO+rc5Xi4EUVhmovbmSaU6nM1n1mAH62w@mail.gmail.com>
On 26 November 2017 at 08:29, Bhupesh SHARMA <bhupesh.linux@gmail.com> wrote:
> Hi Akashi,
>
> On Thu, Nov 16, 2017 at 12:30 PM, AKASHI Takahiro
> <takahiro.akashi@linaro.org> wrote:
>> Bhupesh,
>>
>> On Wed, Nov 15, 2017 at 04:28:55PM +0530, Bhupesh Sharma wrote:
>>>
>> (snip)
>>
>>> # dmesg | grep -B 2 -i "ACPI reclaim"
>>> [ 0.000000] efi: 0x000039670000-0x0000396bffff [Runtime Code |RUN| |
>>> | | | | | |WB|WT|WC|UC]
>>> [ 0.000000] efi: 0x0000396c0000-0x00003970ffff [Boot Code | | | |
>>> | | | | |WB|WT|WC|UC]
>>> [ 0.000000] efi: 0x000039710000-0x00003975ffff [ACPI Reclaim Memory|
>>> | | | | | | | |WB|WT|WC|UC]
>>>
>>> 2. Now, I am not sure which kernel layer does the following changes (I am
>>> still trying to dig it out more), but I see that the 'Boot Code' and ACPI
>>> DSDT table regions are somehow merged into one memblock_region and appear as
>>> range '396c0000-3975ffff' in the '/proc/iomem' interface:
>>>
>>> # cat /proc/iomem | grep -A 2 -B 2 39
>>> 00000000-3961ffff : System RAM
>>> 00080000-00b6ffff : Kernel code
>>> 00cb0000-0167ffff : Kernel data
>>> 0e800000-2e7fffff : Crash kernel
>>> 39620000-396bffff : reserved
>>> 396c0000-3975ffff : System RAM
>>> 39760000-3976ffff : reserved
>>> 39770000-397affff : reserved
>>> 397b0000-3989ffff : reserved
>>> 398a0000-398bffff : reserved
>>> 398c0000-39d3ffff : reserved
>>> 39d40000-3ed2ffff : System RAM
>>>
>> (snip)
>>>
>>> So, I am looking at what could be causing the 'Boot Code' and 'ACPI DSDT
>>> table' ranges to be merged into a single region at
>>> '0x0000396c0000-0x00003970ffff' which cannot be marked as RESERVED using
>>> 'memblock_is_reserved'.
>>
>> Simple:) The short answer is that memblock_add() does.
>>
>> The long answer:
>> First, please note that memblock maintains two type of regions list,
>> "memory" and "reserved".
>>
>> efi_init()
>> reserve_regions()
>> early_init_dt_add_memory_arch()
>> memblock_add()
>> memblock_add_range(memblock.memory)
>>
>> The memory regions described in efi.memmap are added to "memory" list
>> with all the neighboring regions being merged into ones,
>> in this case, "Runtime Code", "Boot Code", "ACPI Reclaim Memory" and others.
>>
>> The secret here is that "Runtime Code" is also marked with "NOMAP" flag in
>> reserve_regions(), which creates an isolated region since it now has
>> a different attribute.
>> Consequently only "Boot Code" and "ACPI Reclaim Memory" are
>> unified.
>>
>> Look at request_standard_resources(). It handles only "memory" list,
>> and doesn't care about whether any arbitrary part of memory is in
>> "reserved" list or not.
>
> Thanks for the pointers. Now I did some experiments and traversed the
> whole memblock path and I see
> how these two regions get merged into a single region which is later
> on recognized by
> 'request_standard_resources()' as a System RAM region rather than a
> RESERVED region.
>
> I recently reproduced this on a APM mustang with latest kernel as well
> when acpi is used to boot the machine, which makes me believe that
> this is a generic issue for arm64 machines with the 4.14 kernel and if
> they use acpi=force as the boot method.
>
> I am not sure, if a fix/or hack would be suitable for all underlying
> arm64 machines, but I am trying one on the arm64 machines I have to
> see if it fixes the issue.
>
> @Ard:
>
> Hi Ard,
>
> I think to create and test a clean solution for all arm64 boards it
> will take some time, in the meantime should we consider reverting the
> commit [1] to make sure that acpi enabled arm64 machines can boot with
> 4.14?
>
> Please let me know your opinion.
>
> [1] f56ab9a5b73ca2aee777ccdf2d355ae2dd31db5a (efi/arm: Don't mark
> ACPI reclaim memory as MEMBLOCK_NOMAP)
>
I don't think that is really going to help tbh.
ACPI reclaim regions are not the only regions that are
memblock_reserve()d and need to be reserved by the incoming kernel as
well. So as far as I can tell, this is a symptom of an underlying
issue that we will need to solve, and reverting the code that exposed
it will not make the bug go away.
--
Ard.
^ permalink raw reply
* [PATCH v2] ARM: dts: at91: add devicetree for the Axentia Nattis with Natte power
From: Peter Rosin @ 2017-12-04 13:57 UTC (permalink / raw)
To: linux-arm-kernel
The Axentia Nattis is a device designed for presenting departures for
public transport systems. The Natte helper board provides power and
features a battery of battery chargers.
Signed-off-by: Peter Rosin <peda@axentia.se>
---
This was part of a two-patch series, but the first patch in that
series was redundant, so I dropped it (there was a dt binding
recently added for the tfa9879 amplifier that I had not noticed).
Changes since v1: https://lkml.org/lkml/2017/12/1/844
- removed chip-ids from before the @-sign instead naming the nodes
for the function, e.g sx1502q at 20 -> ioexp at 20
- added #sound-dai-cells to the amplifier node
- switch to SPDX license tags
Cheers,
Peter
Documentation/devicetree/bindings/arm/axentia.txt | 9 +
MAINTAINERS | 2 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/at91-natte.dtsi | 244 ++++++++++++++++++++
arch/arm/boot/dts/at91-nattis-2-natte-2.dts | 258 ++++++++++++++++++++++
5 files changed, 514 insertions(+)
create mode 100644 arch/arm/boot/dts/at91-natte.dtsi
create mode 100644 arch/arm/boot/dts/at91-nattis-2-natte-2.dts
diff --git a/Documentation/devicetree/bindings/arm/axentia.txt b/Documentation/devicetree/bindings/arm/axentia.txt
index ea3fb96ae465..de58f2463880 100644
--- a/Documentation/devicetree/bindings/arm/axentia.txt
+++ b/Documentation/devicetree/bindings/arm/axentia.txt
@@ -10,6 +10,15 @@ compatible = "axentia,linea",
and following the rules from atmel-at91.txt for a sama5d31 SoC.
+Nattis v2 board with Natte v2 power board
+-----------------------------------------
+
+Required root node properties:
+compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+and following the rules from above for the axentia,linea CPU module.
+
+
TSE-850 v3 board
----------------
diff --git a/MAINTAINERS b/MAINTAINERS
index d4fdcb12616c..ec8a33f7cb01 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -2500,6 +2500,8 @@ L: linux-arm-kernel at lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: Documentation/devicetree/bindings/arm/axentia.txt
F: arch/arm/boot/dts/at91-linea.dtsi
+F: arch/arm/boot/dts/at91-natte.dtsi
+F: arch/arm/boot/dts/at91-nattis-2-natte-2.dts
F: arch/arm/boot/dts/at91-tse850-3.dts
AXENTIA ASOC DRIVERS
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9caf21..d62ee6f0271d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -47,6 +47,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
at91sam9x35ek.dtb
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2.dtb \
+ at91-nattis-2-natte-2.dtb \
at91-sama5d27_som1_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
diff --git a/arch/arm/boot/dts/at91-natte.dtsi b/arch/arm/boot/dts/at91-natte.dtsi
new file mode 100644
index 000000000000..49f0a0c46cde
--- /dev/null
+++ b/arch/arm/boot/dts/at91-natte.dtsi
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * at91-natte.dts - Device Tree include file for the Natte board
+ *
+ * Copyright (C) 2017 Axentia Technologies AB
+ *
+ * Author: Peter Rosin <peda@axentia.se>
+ */
+
+/ {
+ mux: mux-controller {
+ compatible = "gpio-mux";
+ #mux-control-cells = <0>;
+
+ mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
+ <&ioexp 1 GPIO_ACTIVE_HIGH>,
+ <&ioexp 2 GPIO_ACTIVE_HIGH>;
+ };
+
+ batntc-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 5>;
+ io-channel-names = "parent";
+ mux-controls = <&mux>;
+
+ channels =
+ "batntc0", "batntc1", "batntc2", "batntc3",
+ "batntc4", "batntc5", "batntc6", "batntc7";
+ };
+
+ batv-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 6>;
+ io-channel-names = "parent";
+ mux-controls = <&mux>;
+
+ channels =
+ "batv0", "batv1", "batv2", "batv3",
+ "batv4", "batv5", "batv6", "batv7";
+ };
+
+ iout-mux {
+ compatible = "io-channel-mux";
+ io-channels = <&adc 7>;
+ io-channel-names = "parent";
+ mux-controls = <&mux>;
+
+ channels =
+ "iout0", "iout1", "iout2", "iout3",
+ "iout4", "iout5", "iout6", "iout7";
+ };
+
+ i2c-mux {
+ compatible = "i2c-mux";
+ mux-locked;
+ i2c-parent = <&i2c0>;
+ mux-controls = <&mux>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ i2c at 0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+
+ i2c at 1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+
+ i2c at 2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+
+ i2c at 3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+
+ i2c at 4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+
+ i2c at 5 {
+ reg = <5>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+
+ i2c at 6 {
+ reg = <6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+
+ i2c at 7 {
+ reg = <7>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ charger at 9 {
+ compatible = "ti,bq24735";
+ reg = <0x9>;
+
+ ti,charge-current = <2000>;
+ ti,charge-voltage = <16800>;
+
+ poll-interval = <20000>;
+ };
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ ioexp: ioexp at 20 {
+ #gpio-cells = <2>;
+ compatible = "semtech,sx1502q";
+ reg = <0x20>;
+
+ gpio-controller;
+ ngpios = <8>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&gpio3_cfg_pins>;
+
+ gpio3_cfg_pins: gpio3_cfg {
+ pins = "gpio3";
+ bias-pull-up;
+ };
+ };
+
+ adc: adc at 48 {
+ compatible = "ti,ads1015";
+ reg = <0x48>;
+ #io-channel-cells = <1>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel at 4 {
+ reg = <4>;
+ ti,gain = <2>;
+ ti,datarate = <4>;
+ };
+
+ channel at 5 {
+ reg = <5>;
+ ti,gain = <2>;
+ ti,datarate = <4>;
+ };
+
+ channel at 6 {
+ reg = <6>;
+ ti,gain = <1>;
+ ti,datarate = <4>;
+ };
+
+ channel at 7 {
+ reg = <7>;
+ ti,gain = <3>;
+ ti,datarate = <4>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/at91-nattis-2-natte-2.dts b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
new file mode 100644
index 000000000000..3ea1d26e1c68
--- /dev/null
+++ b/arch/arm/boot/dts/at91-nattis-2-natte-2.dts
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * at91-nattis-2-natte-2.dts - Device Tree file for the Linea/Nattis board
+ *
+ * Copyright (C) 2017 Axentia Technologies AB
+ *
+ * Author: Peter Rosin <peda@axentia.se>
+ */
+/dts-v1/;
+#include "at91-linea.dtsi"
+#include "sama5d3_lcd.dtsi"
+#include "at91-natte.dtsi"
+
+/ {
+ model = "Axentia Linea-Nattis v2 Natte v2";
+ compatible = "axentia,nattis-2", "axentia,natte-2", "axentia,linea",
+ "atmel,sama5d31", "atmel,sama5d3", "atmel,sama5";
+
+ ahb {
+ apb {
+ pinctrl at fffff200 {
+ nattis {
+ pinctrl_usba_vbus: usba_vbus {
+ atmel,pins =
+ <AT91_PIOD 28
+ AT91_PERIPH_GPIO
+ AT91_PINCTRL_DEGLITCH>;
+ };
+
+ pinctrl_mmc0_cd: mmc0_cd {
+ atmel,pins =
+ <AT91_PIOD 5
+ AT91_PERIPH_GPIO
+ AT91_PINCTRL_PULL_UP_DEGLITCH>;
+ };
+
+ pinctrl_lcd_prlud0: lcd_prlud0 {
+ atmel,pins =
+ <AT91_PIOA 21
+ AT91_PERIPH_GPIO
+ AT91_PINCTRL_OUTPUT_VAL(0)>;
+ };
+
+ pinctrl_lcd_hipow0: lcd_hipow0 {
+ atmel,pins =
+ <AT91_PIOA 23
+ AT91_PERIPH_GPIO
+ AT91_PINCTRL_OUTPUT_VAL(0)>;
+ };
+ };
+ };
+
+ watchdog at fffffe40 {
+ status = "okay";
+ };
+ };
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+
+ wakeup {
+ label = "Wakeup";
+ linux,code = <10>;
+ gpio-key,wakeup;
+ gpios = <&pioB 27 GPIO_ACTIVE_LOW>;
+ };
+ };
+
+ panel_reg: panel-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-VCC";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ bl_reg: backlight-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "panel-VDD";
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ panel_bl: backlight {
+ compatible = "pwm-backlight";
+ pwms = <&hlcdc_pwm 0 100000 0>;
+
+ brightness-levels = < 0 1 2 3 4 5 6 7 8 9
+ 10 11 12 13 14 15 16 17 18 19
+ 20 21 22 23 24 25 26 27 28 29
+ 30 31 32 33 34 35 36 37 38 39
+ 40 41 42 43 44 45 46 47 48 49
+ 50 51 52 53 54 55 56 57 58 59
+ 60 61 62 63 64 65 66 67 68 69
+ 70 71 72 73 74 75 76 77 78 79
+ 80 81 82 83 84 85 86 87 88 89
+ 90 91 92 93 94 95 96 97 98 99
+ 100>;
+ default-brightness-level = <40>;
+
+ power-supply = <&bl_reg>;
+ enable-gpios = <&pioA 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ panel: panel {
+ compatible = "sharp,lq150x1lg11";
+ backlight = <&panel_bl>;
+ power-supply = <&panel_reg>;
+
+ port {
+ panel_input: endpoint {
+ remote-endpoint = <&hlcdc_panel_output>;
+ };
+ };
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+
+ simple-audio-card,name = "nattis-tfa9879";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&cpu_dai>;
+ simple-audio-card,frame-master = <&cpu_dai>;
+ simple-audio-card,widgets = "Line", "Line Out Jack";
+ simple-audio-card,routing = "Line Out Jack", "LINEOUT";
+
+ cpu_dai: simple-audio-card,cpu {
+ sound-dai = <&ssc0>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&>;
+ };
+ };
+};
+
+&i2c0 {
+ status = "okay";
+
+ clock-frequency = <100000>;
+
+ temp at 18 {
+ compatible = "nxp,se97b", "jedec,jc-42.4-temp";
+ reg = <0x18>;
+ smbus-timeout-disable;
+ };
+
+ eeprom at 50 {
+ compatible = "nxp,24c02";
+ reg = <0x50>;
+ pagesize = <16>;
+ };
+
+ amp: amplifier at 6c {
+ compatible = "nxp,tfa9879";
+ reg = <0x6c>;
+ #sound-dai-cells = <0>;
+ };
+};
+
+&ssc0 {
+ status = "okay";
+
+ atmel,clk-from-rk-pin;
+ #sound-dai-cells = <0>;
+};
+
+&hlcdc {
+ status = "okay";
+
+ hlcdc-display-controller {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcd_base
+ &pinctrl_lcd_rgb565
+ &pinctrl_lcd_prlud0
+ &pinctrl_lcd_hipow0>;
+
+ port at 0 {
+ hlcdc_panel_output: endpoint {
+ remote-endpoint = <&panel_input>;
+ };
+ };
+ };
+};
+
+&mmc0 {
+ status = "okay";
+
+ pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0
+ &pinctrl_mmc0_dat1_3
+ &pinctrl_mmc0_cd>;
+
+ slot at 0 {
+ reg = <0>;
+ bus-width = <4>;
+ cd-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>;
+ };
+};
+
+&usart0 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usart0>;
+ atmel,use-dma-rx;
+};
+
+&nand {
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap at 0 {
+ label = "at91bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader at 40000 {
+ label = "bootloader";
+ reg = <0x40000 0x80000>;
+ };
+
+ bootloaderenv at c0000 {
+ label = "bootloader env";
+ reg = <0xc0000 0xc0000>;
+ };
+
+ dtb at 180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel at 200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs at 800000 {
+ label = "rootfs";
+ reg = <0x800000 0x0f800000>;
+ };
+ };
+};
+
+&dbgu {
+ status = "okay";
+
+ atmel,use-dma-rx;
+};
+
+&usb0 {
+ status = "okay";
+
+ atmel,vbus-gpio = <&pioD 28 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+};
--
2.11.0
^ permalink raw reply related
* [PULL 02/19] KVM: arm/arm64: VGIC: extend !vgic_is_initialized guard
From: Christoffer Dall @ 2017-12-04 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Andre Przywara <andre.przywara@arm.com>
Commit f39d16cbabf9 ("KVM: arm/arm64: Guard kvm_vgic_map_is_active against
!vgic_initialized") introduced a check whether the VGIC has been
initialized before accessing the spinlock and the VGIC data structure.
However the vgic_get_irq() call in the variable declaration sneaked
through the net, so lets make sure that this also gets called only after
we actually allocated the arrays this function accesses.
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/vgic/vgic.c b/virt/kvm/arm/vgic/vgic.c
index b168a328a9e0..786cce7bd2ec 100644
--- a/virt/kvm/arm/vgic/vgic.c
+++ b/virt/kvm/arm/vgic/vgic.c
@@ -823,13 +823,14 @@ void vgic_kick_vcpus(struct kvm *kvm)
bool kvm_vgic_map_is_active(struct kvm_vcpu *vcpu, unsigned int vintid)
{
- struct vgic_irq *irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
+ struct vgic_irq *irq;
bool map_is_active;
unsigned long flags;
if (!vgic_initialized(vcpu->kvm))
return false;
+ irq = vgic_get_irq(vcpu->kvm, vcpu, vintid);
spin_lock_irqsave(&irq->irq_lock, flags);
map_is_active = irq->hw && irq->active;
spin_unlock_irqrestore(&irq->irq_lock, flags);
--
2.14.2
^ permalink raw reply related
* [PULL 01/19] KVM: arm/arm64: Don't enable/disable physical timer access on VHE
From: Christoffer Dall @ 2017-12-04 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204135637.21620-1-cdall@kernel.org>
From: Christoffer Dall <christoffer.dall@linaro.org>
After the timer optimization rework we accidentally end up calling
physical timer enable/disable functions on VHE systems, which is neither
needed nor correct, since the CNTHCTL_EL2 register format is
different when HCR_EL2.E2H is set.
The CNTHCTL_EL2 is initialized when CPUs become online in
kvm_timer_init_vhe() and we don't have to call these functions on VHE
systems, which also allows us to inline the non-VHE functionality.
Reported-by: Jintack Lim <jintack@cs.columbia.edu>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
include/kvm/arm_arch_timer.h | 3 ---
virt/kvm/arm/arch_timer.c | 6 ------
virt/kvm/arm/hyp/timer-sr.c | 48 ++++++++++++++++++--------------------------
3 files changed, 20 insertions(+), 37 deletions(-)
diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
index 01ee473517e2..6e45608b2399 100644
--- a/include/kvm/arm_arch_timer.h
+++ b/include/kvm/arm_arch_timer.h
@@ -93,7 +93,4 @@ void kvm_timer_init_vhe(void);
#define vcpu_vtimer(v) (&(v)->arch.timer_cpu.vtimer)
#define vcpu_ptimer(v) (&(v)->arch.timer_cpu.ptimer)
-void enable_el1_phys_timer_access(void);
-void disable_el1_phys_timer_access(void);
-
#endif
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 4151250ce8da..190c99ed1b73 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -479,9 +479,6 @@ void kvm_timer_vcpu_load(struct kvm_vcpu *vcpu)
vtimer_restore_state(vcpu);
- if (has_vhe())
- disable_el1_phys_timer_access();
-
/* Set the background timer for the physical timer emulation. */
phys_timer_emulate(vcpu);
}
@@ -510,9 +507,6 @@ void kvm_timer_vcpu_put(struct kvm_vcpu *vcpu)
if (unlikely(!timer->enabled))
return;
- if (has_vhe())
- enable_el1_phys_timer_access();
-
vtimer_save_state(vcpu);
/*
diff --git a/virt/kvm/arm/hyp/timer-sr.c b/virt/kvm/arm/hyp/timer-sr.c
index f39861639f08..f24404b3c8df 100644
--- a/virt/kvm/arm/hyp/timer-sr.c
+++ b/virt/kvm/arm/hyp/timer-sr.c
@@ -27,42 +27,34 @@ void __hyp_text __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high)
write_sysreg(cntvoff, cntvoff_el2);
}
-void __hyp_text enable_el1_phys_timer_access(void)
-{
- u64 val;
-
- /* Allow physical timer/counter access for the host */
- val = read_sysreg(cnthctl_el2);
- val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
- write_sysreg(val, cnthctl_el2);
-}
-
-void __hyp_text disable_el1_phys_timer_access(void)
-{
- u64 val;
-
- /*
- * Disallow physical timer access for the guest
- * Physical counter access is allowed
- */
- val = read_sysreg(cnthctl_el2);
- val &= ~CNTHCTL_EL1PCEN;
- val |= CNTHCTL_EL1PCTEN;
- write_sysreg(val, cnthctl_el2);
-}
-
void __hyp_text __timer_disable_traps(struct kvm_vcpu *vcpu)
{
/*
* We don't need to do this for VHE since the host kernel runs in EL2
* with HCR_EL2.TGE ==1, which makes those bits have no impact.
*/
- if (!has_vhe())
- enable_el1_phys_timer_access();
+ if (!has_vhe()) {
+ u64 val;
+
+ /* Allow physical timer/counter access for the host */
+ val = read_sysreg(cnthctl_el2);
+ val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
+ write_sysreg(val, cnthctl_el2);
+ }
}
void __hyp_text __timer_enable_traps(struct kvm_vcpu *vcpu)
{
- if (!has_vhe())
- disable_el1_phys_timer_access();
+ if (!has_vhe()) {
+ u64 val;
+
+ /*
+ * Disallow physical timer access for the guest
+ * Physical counter access is allowed
+ */
+ val = read_sysreg(cnthctl_el2);
+ val &= ~CNTHCTL_EL1PCEN;
+ val |= CNTHCTL_EL1PCTEN;
+ write_sysreg(val, cnthctl_el2);
+ }
}
--
2.14.2
^ permalink raw reply related
* [PULL 00/19] KVM/ARM Fixes for v4.15
From: Christoffer Dall @ 2017-12-04 13:56 UTC (permalink / raw)
To: linux-arm-kernel
From: Christoffer Dall <christoffer.dall@linaro.org>
Hi Paolo and Radim,
Here's the first round of fixes for KVM/ARM for v4.15. This is a fairly large
set of fixes, partially because we spotted a handful of issues from running the
SMATCH static analysis on the code (thanks to AKASHI Takahiro).
In more details, this pull request fixes:
- A number of issues in the vgic discovered using SMATCH
- A bit one-off calculation in out stage base address mask (32-bit and
64-bit)
- Fixes to single-step debugging instructions that trap for other
reasons such as MMMIO aborts
- Printing unavailable hyp mode as error
- Potential spinlock deadlock in the vgic
- Avoid calling vgic vcpu free more than once
- Broken bit calculation for big endian systems
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvm-arm-fixes-for-v4.15-1
for you to fetch changes up to fc396e066318c0a02208c1d3f0b62950a7714999:
KVM: arm/arm64: Fix broken GICH_ELRSR big endian conversion (2017-12-04 14:25:33 +0100)
Thanks,
-Christoffer
Alex Benn?e (5):
KVM: arm/arm64: debug: Introduce helper for single-step
kvm: arm64: handle single-stepping trapped instructions
kvm: arm64: handle single-step of userspace mmio instructions
kvm: arm64: handle single-step during SError exceptions
kvm: arm64: handle single-step of hyp emulated mmio instructions
Andre Przywara (1):
KVM: arm/arm64: VGIC: extend !vgic_is_initialized guard
Andrew Jones (1):
KVM: arm/arm64: kvm_arch_destroy_vm cleanups
Ard Biesheuvel (1):
kvm: arm: don't treat unavailable HYP mode as an error
Christoffer Dall (3):
KVM: arm/arm64: Don't enable/disable physical timer access on VHE
KVM: arm/arm64: Avoid attempting to load timer vgic state without a
vgic
KVM: arm/arm64: Fix broken GICH_ELRSR big endian conversion
Kristina Martsenko (1):
arm64: KVM: fix VTTBR_BADDR_MASK BUG_ON off-by-one
Marc Zyngier (7):
KVM: arm/arm64: vgic-irqfd: Fix MSI entry allocation
KVM: arm/arm64: vgic: Preserve the revious read from the pending table
KVM: arm/arm64: vgic-its: Preserve the revious read from the pending
table
KVM: arm/arm64: vgic-its: Check result of allocation before use
KVM: arm/arm64: vgic-v4: Only perform an unmap for valid vLPIs
arm: KVM: Fix VTTBR_BADDR_MASK BUG_ON off-by-one
KVM: arm/arm64: Fix spinlock acquisition in vgic_set_owner
arch/arm/include/asm/kvm_arm.h | 3 +--
arch/arm/include/asm/kvm_host.h | 5 ++++
arch/arm64/include/asm/kvm_arm.h | 3 +--
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/debug.c | 21 +++++++++++++++
arch/arm64/kvm/handle_exit.c | 57 ++++++++++++++++++++++++++++-----------
arch/arm64/kvm/hyp/switch.c | 37 ++++++++++++++++++++-----
include/kvm/arm_arch_timer.h | 3 ---
virt/kvm/arm/arch_timer.c | 11 +++-----
virt/kvm/arm/arm.c | 7 +++--
virt/kvm/arm/hyp/timer-sr.c | 48 ++++++++++++++-------------------
virt/kvm/arm/hyp/vgic-v2-sr.c | 4 ---
virt/kvm/arm/vgic/vgic-irqfd.c | 3 +--
virt/kvm/arm/vgic/vgic-its.c | 4 ++-
virt/kvm/arm/vgic/vgic-v3.c | 2 +-
virt/kvm/arm/vgic/vgic-v4.c | 6 +++--
virt/kvm/arm/vgic/vgic.c | 8 +++---
17 files changed, 144 insertions(+), 79 deletions(-)
--
2.14.2
^ permalink raw reply
* [PULL 00/19] KVM/ARM Fixes for v4.15
From: Christoffer Dall @ 2017-12-04 13:56 UTC (permalink / raw)
To: linux-arm-kernel
From: Christoffer Dall <christoffer.dall@linaro.org>
Hi Paolo and Radim,
Here's the first round of fixes for KVM/ARM for v4.15. This is a fairly large
set of fixes, partially because we spotted a handful of issues from running the
SMATCH static analysis on the code (thanks to AKASHI Takahiro).
In more details, this pull request fixes:
- A number of issues in the vgic discovered using SMATCH
- A bit one-off calculation in out stage base address mask (32-bit and
64-bit)
- Fixes to single-step debugging instructions that trap for other
reasons such as MMMIO aborts
- Printing unavailable hyp mode as error
- Potential spinlock deadlock in the vgic
- Avoid calling vgic vcpu free more than once
- Broken bit calculation for big endian systems
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvm-arm-fixes-for-v4.15-1
for you to fetch changes up to fc396e066318c0a02208c1d3f0b62950a7714999:
KVM: arm/arm64: Fix broken GICH_ELRSR big endian conversion (2017-12-04 14:25:33 +0100)
Thanks,
-Christoffer
Alex Benn?e (5):
KVM: arm/arm64: debug: Introduce helper for single-step
kvm: arm64: handle single-stepping trapped instructions
kvm: arm64: handle single-step of userspace mmio instructions
kvm: arm64: handle single-step during SError exceptions
kvm: arm64: handle single-step of hyp emulated mmio instructions
Andre Przywara (1):
KVM: arm/arm64: VGIC: extend !vgic_is_initialized guard
Andrew Jones (1):
KVM: arm/arm64: kvm_arch_destroy_vm cleanups
Ard Biesheuvel (1):
kvm: arm: don't treat unavailable HYP mode as an error
Christoffer Dall (3):
KVM: arm/arm64: Don't enable/disable physical timer access on VHE
KVM: arm/arm64: Avoid attempting to load timer vgic state without a
vgic
KVM: arm/arm64: Fix broken GICH_ELRSR big endian conversion
Kristina Martsenko (1):
arm64: KVM: fix VTTBR_BADDR_MASK BUG_ON off-by-one
Marc Zyngier (7):
KVM: arm/arm64: vgic-irqfd: Fix MSI entry allocation
KVM: arm/arm64: vgic: Preserve the revious read from the pending table
KVM: arm/arm64: vgic-its: Preserve the revious read from the pending
table
KVM: arm/arm64: vgic-its: Check result of allocation before use
KVM: arm/arm64: vgic-v4: Only perform an unmap for valid vLPIs
arm: KVM: Fix VTTBR_BADDR_MASK BUG_ON off-by-one
KVM: arm/arm64: Fix spinlock acquisition in vgic_set_owner
arch/arm/include/asm/kvm_arm.h | 3 +--
arch/arm/include/asm/kvm_host.h | 5 ++++
arch/arm64/include/asm/kvm_arm.h | 3 +--
arch/arm64/include/asm/kvm_host.h | 1 +
arch/arm64/kvm/debug.c | 21 +++++++++++++++
arch/arm64/kvm/handle_exit.c | 57 ++++++++++++++++++++++++++++-----------
arch/arm64/kvm/hyp/switch.c | 37 ++++++++++++++++++++-----
include/kvm/arm_arch_timer.h | 3 ---
virt/kvm/arm/arch_timer.c | 11 +++-----
virt/kvm/arm/arm.c | 7 +++--
virt/kvm/arm/hyp/timer-sr.c | 48 ++++++++++++++-------------------
virt/kvm/arm/hyp/vgic-v2-sr.c | 4 ---
virt/kvm/arm/vgic/vgic-irqfd.c | 3 +--
virt/kvm/arm/vgic/vgic-its.c | 4 ++-
virt/kvm/arm/vgic/vgic-v3.c | 2 +-
virt/kvm/arm/vgic/vgic-v4.c | 6 +++--
virt/kvm/arm/vgic/vgic.c | 8 +++---
17 files changed, 144 insertions(+), 79 deletions(-)
--
2.14.2
^ permalink raw reply
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