* [PATCH v2 4/5] ARM: imx_v4_v5_defconfig: enable RTC_DRV_MXC_V2
From: Fabio Estevam @ 2017-12-05 14:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205140646.30367-5-linux-kernel-dev@beckhoff.com>
Hi Patrick,
On Tue, Dec 5, 2017 at 12:06 PM, <linux-kernel-dev@beckhoff.com> wrote:
> arch/arm/configs/imx_v4_v5_defconfig | 1 +
i.mx53 uses imx_v6_v7_defconfig, not imx_v4_v5_defconfig.
^ permalink raw reply
* [PATCH v2 5/5] rtc: add mxc driver for i.MX53 SRTC
From: linux-kernel-dev at beckhoff.com @ 2017-12-05 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205140646.30367-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
This is driver enables support for the low power domain SRTC features:
- 32-bit MSB of non-rollover time counter
- 32-bit alarm register
Based on:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
v2:
- have seperate patches for dt-binding, CONFIG option, imx53.dtsi and driver
- add SPDX-License-Identifier and cleanup copyright notice
- replace __raw_readl/writel() with readl/writel()
- fix PM_SLEEP callbacks
- add CONFIG_RTC_DRV_MXC_V2 to build rtc-mxc_v2.c
- remove misleading or obvious comments and fix style of the remaining
- avoid endless loop while waiting for hw
- implement consistent locking; make spinlock a member of dev struct
- enable clk only for register accesses
- remove all udelay() calls since they are obsolete or redundant
(we are already waiting for register flags to change)
- init platform_data before registering irq callback
- let set_time() fail, when 32 bit rtc counter exceeded
- make names more consistent
- cleanup and reorder includes
- cleanup and remove unused defines
To: Alessandro Zummo <a.zummo@towertech.it>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc at vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree at vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel at vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel at lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Wa?mann <LW@KARO-electronics.de>
---
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mxc_v2.c | 433 +++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 434 insertions(+)
create mode 100644 drivers/rtc/rtc-mxc_v2.c
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index f2f50c11dc38..dcf60e61ae5c 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -106,6 +106,7 @@ obj-$(CONFIG_RTC_DRV_MT6397) += rtc-mt6397.o
obj-$(CONFIG_RTC_DRV_MT7622) += rtc-mt7622.o
obj-$(CONFIG_RTC_DRV_MV) += rtc-mv.o
obj-$(CONFIG_RTC_DRV_MXC) += rtc-mxc.o
+obj-$(CONFIG_RTC_DRV_MXC_V2) += rtc-mxc_v2.o
obj-$(CONFIG_RTC_DRV_NUC900) += rtc-nuc900.o
obj-$(CONFIG_RTC_DRV_OMAP) += rtc-omap.o
obj-$(CONFIG_RTC_DRV_OPAL) += rtc-opal.o
diff --git a/drivers/rtc/rtc-mxc_v2.c b/drivers/rtc/rtc-mxc_v2.c
new file mode 100644
index 000000000000..c5a6d2c293bb
--- /dev/null
+++ b/drivers/rtc/rtc-mxc_v2.c
@@ -0,0 +1,433 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Real Time Clock (RTC) Driver for i.MX53
+ * Copyright (c) 2004-2011 Freescale Semiconductor, Inc.
+ * Copyright (c) 2017 Beckhoff Automation GmbH & Co. KG
+ */
+
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+
+#define SRTC_LPPDR_INIT 0x41736166 /* init for glitch detect */
+
+#define SRTC_LPCR_EN_LP BIT(3) /* lp enable */
+#define SRTC_LPCR_WAE BIT(4) /* lp wakeup alarm enable */
+#define SRTC_LPCR_ALP BIT(7) /* lp alarm flag */
+#define SRTC_LPCR_NSA BIT(11) /* lp non secure access */
+#define SRTC_LPCR_NVE BIT(14) /* lp non valid state exit bit */
+#define SRTC_LPCR_IE BIT(15) /* lp init state exit bit */
+
+#define SRTC_LPSR_ALP BIT(3) /* lp alarm flag */
+#define SRTC_LPSR_NVES BIT(14) /* lp non-valid state exit status */
+#define SRTC_LPSR_IES BIT(15) /* lp init state exit status */
+
+#define SRTC_LPSCMR 0x00 /* LP Secure Counter MSB Reg */
+#define SRTC_LPSCLR 0x04 /* LP Secure Counter LSB Reg */
+#define SRTC_LPSAR 0x08 /* LP Secure Alarm Reg */
+#define SRTC_LPCR 0x10 /* LP Control Reg */
+#define SRTC_LPSR 0x14 /* LP Status Reg */
+#define SRTC_LPPDR 0x18 /* LP Power Supply Glitch Detector Reg */
+
+/* max. number of retries to read registers, 120 was max during test */
+#define REG_READ_TIMEOUT 2000
+
+struct mxc_rtc_data {
+ struct rtc_device *rtc;
+ void __iomem *ioaddr;
+ struct clk *clk;
+ spinlock_t lock; /* protects register access */
+ int irq;
+};
+
+/*
+ * This function does write synchronization for writes to the lp srtc block.
+ * To take care of the asynchronous CKIL clock, all writes from the IP domain
+ * will be synchronized to the CKIL domain.
+ * The caller should hold the pdata->lock
+ */
+static inline void mxc_rtc_sync_lp_locked(void __iomem *ioaddr)
+{
+ unsigned int i;
+
+ /* Wait for 3 CKIL cycles */
+ for (i = 0; i < 3; i++) {
+ const u32 count = readl(ioaddr + SRTC_LPSCLR);
+ unsigned int timeout = REG_READ_TIMEOUT;
+
+ while ((readl(ioaddr + SRTC_LPSCLR)) == count) {
+ if (!--timeout) {
+ pr_err("SRTC_LPSCLR stuck! Check your hw.\n");
+ return;
+ }
+ }
+ }
+}
+
+/*
+ * This function updates the RTC alarm registers and then clears all the
+ * interrupt status bits.
+ * The caller should hold the pdata->lock
+ *
+ * @param alrm the new alarm value to be updated in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_write_alarm_locked(struct mxc_rtc_data *const pdata,
+ struct rtc_time *alarm_tm)
+{
+ void __iomem *const ioaddr = pdata->ioaddr;
+ unsigned long time;
+
+ rtc_tm_to_time(alarm_tm, &time);
+
+ if (time > U32_MAX) {
+ pr_err("Hopefully I am out of service by then :-(\n");
+ return -EINVAL;
+ }
+
+ writel((u32)time, ioaddr + SRTC_LPSAR);
+
+ /* clear alarm interrupt status bit */
+ writel(SRTC_LPSR_ALP, ioaddr + SRTC_LPSR);
+
+ mxc_rtc_sync_lp_locked(ioaddr);
+ return 0;
+}
+
+/* This function is the RTC interrupt service routine. */
+static irqreturn_t mxc_rtc_interrupt(int irq, void *dev_id)
+{
+ struct platform_device *pdev = dev_id;
+ struct mxc_rtc_data *pdata = platform_get_drvdata(pdev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ unsigned long flags;
+ u32 events = 0;
+ u32 lp_status;
+ u32 lp_cr;
+
+ spin_lock_irqsave(&pdata->lock, flags);
+ if (clk_prepare_enable(pdata->clk)) {
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return IRQ_NONE;
+ }
+
+ lp_status = readl(ioaddr + SRTC_LPSR);
+ lp_cr = readl(ioaddr + SRTC_LPCR);
+
+ /* update irq data & counter */
+ if (lp_status & SRTC_LPSR_ALP) {
+ if (lp_cr & SRTC_LPCR_ALP)
+ events = (RTC_AF | RTC_IRQF);
+
+ /* disable further lp alarm interrupts */
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ }
+
+ /* Update interrupt enables */
+ writel(lp_cr, ioaddr + SRTC_LPCR);
+
+ /* clear interrupt status */
+ writel(lp_status, ioaddr + SRTC_LPSR);
+
+ mxc_rtc_sync_lp_locked(ioaddr);
+ rtc_update_irq(pdata->rtc, 1, events);
+ clk_disable_unprepare(pdata->clk);
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return IRQ_HANDLED;
+}
+
+/*
+ * Enable clk and aquire spinlock
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_lock(struct mxc_rtc_data *const pdata)
+{
+ int ret;
+
+ spin_lock_irq(&pdata->lock);
+ ret = clk_prepare_enable(pdata->clk);
+ if (ret) {
+ spin_unlock_irq(&pdata->lock);
+ return ret;
+ }
+ return 0;
+}
+
+static int mxc_rtc_unlock(struct mxc_rtc_data *const pdata)
+{
+ clk_disable_unprepare(pdata->clk);
+ spin_unlock_irq(&pdata->lock);
+ return 0;
+}
+
+/*
+ * This function reads the current RTC time into tm in Gregorian date.
+ *
+ * @param tm contains the RTC time value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_time(struct device *dev, struct rtc_time *tm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ time_t now;
+ int ret = mxc_rtc_lock(pdata);
+
+ if (ret)
+ return ret;
+
+ now = readl(pdata->ioaddr + SRTC_LPSCMR);
+ rtc_time_to_tm(now, tm);
+ ret = rtc_valid_tm(tm);
+ mxc_rtc_unlock(pdata);
+ return ret;
+}
+
+/*
+ * This function sets the internal RTC time based on tm in Gregorian date.
+ *
+ * @param tm the time value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_time(struct device *dev, struct rtc_time *tm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ time64_t time = rtc_tm_to_time64(tm);
+ int ret;
+
+ if (time > U32_MAX) {
+ dev_err(dev, "RTC exceeded by %llus\n", time - U32_MAX);
+ return -EINVAL;
+ }
+
+ ret = mxc_rtc_lock(pdata);
+ if (ret)
+ return ret;
+
+ writel(time, pdata->ioaddr + SRTC_LPSCMR);
+ mxc_rtc_sync_lp_locked(pdata->ioaddr);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * This function reads the current alarm value into the passed in \b alrm
+ * argument. It updates the \b alrm's pending field value based on the whether
+ * an alarm interrupt occurs or not.
+ *
+ * @param alrm contains the RTC alarm value upon return
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ void __iomem *ioaddr = pdata->ioaddr;
+ int ret;
+
+ ret = mxc_rtc_lock(pdata);
+ if (ret)
+ return ret;
+
+ rtc_time_to_tm(readl(ioaddr + SRTC_LPSAR), &alrm->time);
+ alrm->pending = !!(readl(ioaddr + SRTC_LPSR) & SRTC_LPSR_ALP);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * Enable/Disable alarm interrupt
+ * The caller should hold the pdata->lock
+ */
+static void mxc_rtc_alarm_irq_enable_locked(struct mxc_rtc_data *pdata,
+ unsigned int enable)
+{
+ u32 lp_cr = readl(pdata->ioaddr + SRTC_LPCR);
+
+ if (enable)
+ lp_cr |= (SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+ else
+ lp_cr &= ~(SRTC_LPCR_ALP | SRTC_LPCR_WAE);
+
+ writel(lp_cr, pdata->ioaddr + SRTC_LPCR);
+}
+
+static int mxc_rtc_alarm_irq_enable(struct device *dev, unsigned int enable)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ int ret = mxc_rtc_lock(pdata);
+
+ if (ret)
+ return ret;
+
+ mxc_rtc_alarm_irq_enable_locked(pdata, enable);
+ return mxc_rtc_unlock(pdata);
+}
+
+/*
+ * This function sets the RTC alarm based on passed in alrm.
+ *
+ * @param alrm the alarm value to be set in the RTC
+ *
+ * @return 0 if successful; non-zero otherwise.
+ */
+static int mxc_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+ int ret = mxc_rtc_lock(pdata);
+
+ if (ret)
+ return ret;
+
+ ret = mxc_rtc_write_alarm_locked(pdata, &alrm->time);
+ if (!ret) {
+ mxc_rtc_alarm_irq_enable_locked(pdata, alrm->enabled);
+ mxc_rtc_sync_lp_locked(pdata->ioaddr);
+ }
+ mxc_rtc_unlock(pdata);
+ return ret;
+}
+
+static const struct rtc_class_ops mxc_rtc_ops = {
+ .read_time = mxc_rtc_read_time,
+ .set_time = mxc_rtc_set_time,
+ .read_alarm = mxc_rtc_read_alarm,
+ .set_alarm = mxc_rtc_set_alarm,
+ .alarm_irq_enable = mxc_rtc_alarm_irq_enable,
+};
+
+static int mxc_rtc_wait_for_flag(void *__iomem ioaddr, int flag)
+{
+ unsigned int timeout = REG_READ_TIMEOUT;
+
+ while (!(readl(ioaddr) & flag)) {
+ if (!--timeout) {
+ pr_err("Wait timeout for 0x%x@%p!\n", flag, ioaddr);
+ return -EBUSY;
+ }
+ }
+ return 0;
+}
+
+static int mxc_rtc_probe(struct platform_device *pdev)
+{
+ struct mxc_rtc_data *pdata;
+ struct resource *res;
+ void __iomem *ioaddr;
+ int ret = 0;
+
+ pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ pdata->ioaddr = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(pdata->ioaddr))
+ return PTR_ERR(pdata->ioaddr);
+
+ ioaddr = pdata->ioaddr;
+
+ pdata->clk = devm_clk_get(&pdev->dev, NULL);
+ if (IS_ERR(pdata->clk)) {
+ dev_err(&pdev->dev, "unable to get rtc clock!\n");
+ return PTR_ERR(pdata->clk);
+ }
+
+ spin_lock_init(&pdata->lock);
+ pdata->irq = platform_get_irq(pdev, 0);
+ if (pdata->irq < 0)
+ return pdata->irq;
+
+ device_init_wakeup(&pdev->dev, 1);
+
+ ret = clk_prepare_enable(pdata->clk);
+ if (ret)
+ return ret;
+ /* initialize glitch detect */
+ writel(SRTC_LPPDR_INIT, ioaddr + SRTC_LPPDR);
+
+ /* clear lp interrupt status */
+ writel(0xFFFFFFFF, ioaddr + SRTC_LPSR);
+
+ /* move out of init state */
+ writel((SRTC_LPCR_IE | SRTC_LPCR_NSA), ioaddr + SRTC_LPCR);
+ mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_IES);
+
+ /* move out of non-valid state */
+ writel((SRTC_LPCR_IE | SRTC_LPCR_NVE | SRTC_LPCR_NSA |
+ SRTC_LPCR_EN_LP), ioaddr + SRTC_LPCR);
+ mxc_rtc_wait_for_flag(ioaddr + SRTC_LPSR, SRTC_LPSR_NVES);
+
+ clk_disable_unprepare(pdata->clk);
+ platform_set_drvdata(pdev, pdata);
+ ret =
+ devm_request_irq(&pdev->dev, pdata->irq, mxc_rtc_interrupt, 0,
+ pdev->name, pdev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "interrupt not available.\n");
+ return ret;
+ }
+
+ pdata->rtc =
+ devm_rtc_device_register(&pdev->dev, pdev->name, &mxc_rtc_ops,
+ THIS_MODULE);
+ if (IS_ERR(pdata->rtc))
+ return PTR_ERR(pdata->rtc);
+
+ return 0;
+}
+
+static int __exit mxc_rtc_remove(struct platform_device *pdev)
+{
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mxc_rtc_suspend(struct device *dev)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ enable_irq_wake(pdata->irq);
+
+ return 0;
+}
+
+static int mxc_rtc_resume(struct device *dev)
+{
+ struct mxc_rtc_data *pdata = dev_get_drvdata(dev);
+
+ if (device_may_wakeup(dev))
+ disable_irq_wake(pdata->irq);
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(mxc_rtc_pm_ops, mxc_rtc_suspend, mxc_rtc_resume);
+
+static const struct of_device_id mxc_ids[] = {
+ { .compatible = "fsl,imx53-rtc", },
+ {}
+};
+
+static struct platform_driver mxc_rtc_driver = {
+ .driver = {
+ .name = "mxc_rtc_v2",
+ .of_match_table = mxc_ids,
+ .pm = &mxc_rtc_pm_ops,
+ },
+ .probe = mxc_rtc_probe,
+ .remove = mxc_rtc_remove,
+};
+
+module_platform_driver(mxc_rtc_driver);
+
+MODULE_AUTHOR("Freescale Semiconductor, Inc.");
+MODULE_DESCRIPTION("Real Time Clock (RTC) Driver for i.MX53");
+MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related
* [PATCH v2 4/5] ARM: imx_v4_v5_defconfig: enable RTC_DRV_MXC_V2
From: linux-kernel-dev at beckhoff.com @ 2017-12-05 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205140646.30367-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
Enable SRTC driver for i.MX53 in default config
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
To: Shawn Guo <shawnguo@kernel.org>
To: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc at vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree at vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel at vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel at lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Wa?mann <LW@KARO-electronics.de>
---
arch/arm/configs/imx_v4_v5_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v4_v5_defconfig b/arch/arm/configs/imx_v4_v5_defconfig
index ca0f13cafe38..b48efd5ff8a7 100644
--- a/arch/arm/configs/imx_v4_v5_defconfig
+++ b/arch/arm/configs/imx_v4_v5_defconfig
@@ -167,6 +167,7 @@ CONFIG_RTC_DRV_PCF8563=y
CONFIG_RTC_DRV_IMXDI=y
CONFIG_RTC_DRV_MC13XXX=y
CONFIG_RTC_DRV_MXC=y
+CONFIG_RTC_DRV_MXC_V2=y
CONFIG_DMADEVICES=y
CONFIG_IMX_DMA=y
CONFIG_IMX_SDMA=y
--
2.11.0
^ permalink raw reply related
* [PATCH v2 3/5] rtc: mxc_v2: add driver for i.MX53 SRTC
From: linux-kernel-dev at beckhoff.com @ 2017-12-05 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205140646.30367-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
Add RTC_DRV_MXC_V2 config option
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
To: Alessandro Zummo <a.zummo@towertech.it>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc at vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree at vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel at vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel at lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Wa?mann <LW@KARO-electronics.de>
---
drivers/rtc/Kconfig | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index b59a31b079a5..440edebf5c71 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -1689,6 +1689,16 @@ config RTC_DRV_MXC
This driver can also be built as a module, if so, the module
will be called "rtc-mxc".
+config RTC_DRV_MXC_V2
+ tristate "Freescale MXC Real Time Clock for i.MX53"
+ depends on ARCH_MXC
+ help
+ If you say yes here you get support for the Freescale MXC
+ SRTC module in i.MX53 processor.
+
+ This driver can also be built as a module, if so, the module
+ will be called "rtc-mxc_v2".
+
config RTC_DRV_SNVS
tristate "Freescale SNVS RTC support"
select REGMAP_MMIO
--
2.11.0
^ permalink raw reply related
* [PATCH v2 2/5] ARM: dts: imx53: add srtc node
From: linux-kernel-dev at beckhoff.com @ 2017-12-05 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205140646.30367-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
rtc-mxc_v2 driver will add support for the i.MX53 SRTC
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
---
To: Shawn Guo <shawnguo@kernel.org>
To: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc at vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree at vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel at vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel at lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Wa?mann <LW@KARO-electronics.de>
---
arch/arm/boot/dts/imx53.dtsi | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 589a67c5f796..e4ca9d9ba2fe 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -434,12 +434,10 @@
};
srtc: srtc at 53fa4000 {
- compatible = "fsl,imx53-rtc", "fsl,imx25-rtc";
+ compatible = "fsl,imx53-rtc";
reg = <0x53fa4000 0x4000>;
interrupts = <24>;
- interrupt-parent = <&tzic>;
clocks = <&clks IMX5_CLK_SRTC_GATE>;
- clock-names = "ipg";
};
iomuxc: iomuxc at 53fa8000 {
--
2.11.0
^ permalink raw reply related
* [PATCH v2 1/5] dt-bindings: rtc: add bindings for i.MX53 SRTC
From: linux-kernel-dev at beckhoff.com @ 2017-12-05 14:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205140646.30367-1-linux-kernel-dev@beckhoff.com>
From: Patrick Bruenn <p.bruenn@beckhoff.com>
Document the binding for i.MX53 SRTC implemented by rtc-mxc_v2
Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com><Paste>
---
To: Alessandro Zummo <a.zummo@towertech.it>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc at vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree at vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel at vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel at lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Wa?mann <LW@KARO-electronics.de>
---
Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
diff --git a/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
new file mode 100644
index 000000000000..796e7f4995db
--- /dev/null
+++ b/Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
@@ -0,0 +1,17 @@
+* i.MX53 Real Time Clock controller
+
+Required properties:
+- compatible: should be: "fsl,imx53-rtc"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- clocks: should contain the phandle for the rtc clock
+- interrupts: rtc alarm interrupt
+
+Example:
+
+srtc at 53fa4000 {
+ compatible = "fsl,imx53-rtc";
+ reg = <0x53fa4000 0x4000>;
+ interrupts = <24>;
+ clocks = <&clks IMX5_CLK_SRTC_GATE>;
+};
--
2.11.0
^ permalink raw reply related
* [PATCH v2 0/5] add mxc driver for i.MX53 SRTC
From: linux-kernel-dev at beckhoff.com @ 2017-12-05 14:06 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrick Bruenn <p.bruenn@beckhoff.com>
Neither rtc-imxdi, rtc-mxc nor rtc-snvs are compatible with i.MX53.
This is driver enables support for the low power domain SRTC features:
- 32-bit MSB of non-rollover time counter
- 32-bit alarm register
Based on:
http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/tree/drivers/rtc/rtc-mxc_v2.c?h=imx_2.6.35_11.09.01
v2:
- have seperate patches for dt-binding, CONFIG option, imx53.dtsi and driver
- add SPDX-License-Identifier and cleanup copyright notice
- replace __raw_readl/writel() with readl/writel()
- fix PM_SLEEP callbacks
- add CONFIG_RTC_DRV_MXC_V2 to build rtc-mxc_v2.c
- remove misleading or obvious comments and fix style of the remaining
- avoid endless loop while waiting for hw
- implement consistent locking; make spinlock a member of dev struct
- enable clk only for register accesses
- remove all udelay() calls since they are obsolete or redundant
(we are already waiting for register flags to change)
- init platform_data before registering irq callback
- let set_time() fail, when 32 bit rtc counter exceeded
- make names more consistent
- cleanup and reorder includes
- cleanup and remove unused defines
To: Alessandro Zummo <a.zummo@towertech.it>
To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-rtc at vger.kernel.org (open list:REAL TIME CLOCK (RTC) SUBSYSTEM)
Cc: devicetree at vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
Cc: linux-kernel at vger.kernel.org (open list)
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Juergen Borleis <jbe@pengutronix.de>
Cc: Noel Vellemans <Noel.Vellemans@visionbms.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de> (maintainer:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Russell King <linux@armlinux.org.uk> (maintainer:ARM PORT)
Cc: linux-arm-kernel at lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE)
Cc: Philippe Ombredanne <pombredanne@nexb.com>
Cc: Lothar Wa?mann <LW@KARO-electronics.de>
Patrick Bruenn (5):
dt-bindings: rtc: add bindings for i.MX53 SRTC
ARM: dts: imx53: add srtc node
rtc: mxc_v2: add driver for i.MX53 SRTC
ARM: imx_v4_v5_defconfig: enable RTC_DRV_MXC_V2
rtc: add mxc driver for i.MX53 SRTC
.../devicetree/bindings/rtc/rtc-mxc_v2.txt | 17 +
arch/arm/boot/dts/imx53.dtsi | 4 +-
arch/arm/configs/imx_v4_v5_defconfig | 1 +
drivers/rtc/Kconfig | 10 +
drivers/rtc/Makefile | 1 +
drivers/rtc/rtc-mxc_v2.c | 433 +++++++++++++++++++++
6 files changed, 463 insertions(+), 3 deletions(-)
create mode 100644 Documentation/devicetree/bindings/rtc/rtc-mxc_v2.txt
create mode 100644 drivers/rtc/rtc-mxc_v2.c
--
2.11.0
^ permalink raw reply
* Tegra baseline test results for v4.15-rc2
From: Jon Hunter @ 2017-12-05 14:05 UTC (permalink / raw)
To: linux-arm-kernel
Here are some basic Tegra test results for Linux v4.15-rc2.
Logs and other details at:
https://nvtb.github.io//linux/test_v4.15-rc2/20171204140104/
Test summary - 84% Success
--------------------------
Build: zImage:
Pass: ( 3/ 3): multi_v7_defconfig, tegra_defconfig,
tegra_defconfig%tegra-fw
Build: Image:
Pass: ( 3/ 3): defconfig, defconfig%jetson-tx2,
defconfig%jetson-tx1
Boot to userspace: defconfig:
Pass: ( 4/ 4): qemu-vexpress64, tegra132-norrin,
tegra210-p2371-0000, tegra210-smaug
Boot to userspace: defconfig%jetson-tx1:
Pass: ( 2/ 2): tegra210-p2371-0000, tegra210-p2371-2180
Boot to userspace: defconfig%jetson-tx2:
Pass: ( 1/ 1): tegra186-p2771-0000
Boot to userspace: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
PM: System suspend: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
vmlinux object size
(delta in bytes from test_v4.15-rc1 (4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323)):
text data bss total kernel
+1919 +1464 0 +3383 defconfig
+3004 -376 0 +2628 multi_v7_defconfig
+3116 -320 0 +2796 tegra_defconfig
Boot-time memory difference
(delta in bytes from test_v4.15-rc1 (4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323))
avail rsrvd high freed board kconfig dtb
. . . . qemu-vexpress64 defconfig __internal
. . . . tegra114-dalmore-a04 multi_v7_defconfig tegra114-dalmore
. . . . tegra114-dalmore-a04 tegra_defconfig tegra114-dalmore
. . . . tegra124-jetson-tk1 multi_v7_defconfig tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig%tegr tegra124-jetson-tk1
. . . . tegra124-jetson-tk1 tegra_defconfig tegra124-jetson-tk1
. . . . tegra124-nyan-big multi_v7_defconfig tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig%tegr tegra124-nyan-big
. . . . tegra124-nyan-big tegra_defconfig tegra124-nyan-big
. . . . tegra132-norrin defconfig tegra132-norrin
. . . . tegra186-p2771-0000 defconfig%jetson-tx2 tegra186-p2771-0000
. . . . tegra20-trimslice multi_v7_defconfig tegra20-trimslice
. . . . tegra20-trimslice tegra_defconfig tegra20-trimslice
. . . . tegra210-p2371-0000 defconfig%jetson-tx1 tegra210-p2371-0000
. . . . tegra210-p2371-0000 defconfig tegra210-p2371-0000
. . . . tegra210-p2371-2180 defconfig%jetson-tx1 tegra210-p2371-2180
. . . . tegra210-smaug defconfig tegra210-smaug
. . . . tegra30-beaver multi_v7_defconfig tegra30-beaver
. . . . tegra30-beaver tegra_defconfig tegra30-beaver
--
nvpublic
^ permalink raw reply
* Tegra baseline test results for v4.15-rc1
From: Jon Hunter @ 2017-12-05 14:03 UTC (permalink / raw)
To: linux-arm-kernel
Here are some basic Tegra test results for Linux v4.15-rc1.
Logs and other details at:
https://nvtb.github.io//linux/test_v4.15-rc1/20171204133126/
Test summary - 84% Success
--------------------------
Build: zImage:
Pass: ( 3/ 3): multi_v7_defconfig, tegra_defconfig,
tegra_defconfig%tegra-fw
Build: Image:
Pass: ( 3/ 3): defconfig, defconfig%jetson-tx2,
defconfig%jetson-tx1
Boot to userspace: defconfig:
Pass: ( 4/ 4): qemu-vexpress64, tegra132-norrin,
tegra210-p2371-0000, tegra210-smaug
Boot to userspace: defconfig%jetson-tx1:
Pass: ( 2/ 2): tegra210-p2371-0000, tegra210-p2371-2180
Boot to userspace: defconfig%jetson-tx2:
Pass: ( 1/ 1): tegra186-p2771-0000
Boot to userspace: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
Boot to userspace: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
PM: System suspend: multi_v7_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig:
FAIL: ( 1/ 5): tegra124-nyan-big
Pass: ( 4/ 5): tegra114-dalmore-a04, tegra124-jetson-tk1,
tegra20-trimslice, tegra30-beaver
PM: System suspend: tegra_defconfig%tegra-fw:
FAIL: ( 1/ 2): tegra124-nyan-big
Pass: ( 1/ 2): tegra124-jetson-tk1
vmlinux object size
(delta in bytes from test_v4.14 (bebc6082da0a9f5d47a1ea2edc099bf671058bd4)):
text data bss total kernel
+178037 -144968 -8488 +24581 defconfig
+111965 -295324 -1816 -185175 multi_v7_defconfig
+79872 -300436 -1808 -222372 tegra_defconfig
Boot-time memory difference
(delta in bytes from test_v4.14 (bebc6082da0a9f5d47a1ea2edc099bf671058bd4))
avail rsrvd high freed board kconfig dtb
20k -20k . -64k qemu-vexpress64 defconfig __internal
-928k 928k . . tegra114-dalmore-a04 multi_v7_defconfig tegra114-dalmore
1108k -1108k . . tegra114-dalmore-a04 tegra_defconfig tegra114-dalmore
-916k 916k . . tegra124-jetson-tk1 multi_v7_defconfig tegra124-jetson-tk1
1120k -1120k . . tegra124-jetson-tk1 tegra_defconfig tegra124-jetson-tk1
-916k 916k . -2048k tegra124-nyan-big multi_v7_defconfig tegra124-nyan-big
1124k -1124k . -1024k tegra124-nyan-big tegra_defconfig tegra124-nyan-big
-2088k 2088k . -64k tegra132-norrin defconfig tegra132-norrin
-932k 932k . . tegra20-trimslice multi_v7_defconfig tegra20-trimslice
1104k -1104k . . tegra20-trimslice tegra_defconfig tegra20-trimslice
56k -56k . -64k tegra210-p2371-0000 defconfig tegra210-p2371-0000
-2064k 2064k . -64k tegra210-smaug defconfig tegra210-smaug
-920k 920k . . tegra30-beaver multi_v7_defconfig tegra30-beaver
1116k -1116k . . tegra30-beaver tegra_defconfig tegra30-beaver
--
nvpublic
^ permalink raw reply
* [PATCH v9 3/5] perf utils: use pmu->is_uncore to detect PMU UNCORE devices
From: Ganapatrao Kulkarni @ 2017-12-05 14:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205135648.GC28405@kernel.org>
Hi Arnaldo,
On Tue, Dec 5, 2017 at 7:26 PM, Arnaldo Carvalho de Melo
<arnaldo.melo@gmail.com> wrote:
> Em Tue, Dec 05, 2017 at 08:35:22PM +0800, Jin, Yao escreveu:
>> A quick test with the new patch 'fix_json_v9_2.patch' shows it working.
>
> Where is this fix_json_v9_2.patch file? I want to fold it with the patch
> introducing the problem.
I will send you formal patch ASAP.
thanks
Ganapat
>
> - Arnaldo
>
>> See the log:
>>
>> root at skl:/tmp# perf stat --per-thread -p 10322 -M CPI,IPC
>> ^C
>> Performance counter stats for process id '10322':
>>
>> vmstat-10322 1,879,654 inst_retired.any #
>> 0.8 CPI
>> vmstat-10322 1,565,807 cycles
>> vmstat-10322 1,879,654 inst_retired.any #
>> 1.2 IPC
>> vmstat-10322 1,565,807 cpu_clk_unhalted.thread
>>
>> 2.850291804 seconds time elapsed
>>
>> Thanks for fixing it quickly.
>>
>> Thanks
>> Jin Yao
>>
>> On 12/5/2017 3:23 PM, Jin, Yao wrote:
>> > Hi,
>> >
>> > I applied the diff but it's failed.
>> >
>> > jinyao at skl:~/skl-ws/perf-dev/lck-4594/src$ patch -p1 < 1.pat
>> > patching file tools/perf/util/pmu.c
>> > patch: **** malformed patch at line 41: *head, struct perf_pmu *pmu)
>> >
>> > Could you send the patch as attachment to me in another mail thread?
>> >
>> > to yao.jin at linux.intel.com
>> > cc yao.jin at intel.com
>> >
>> > Thanks
>> > Jin Yao
>> >
>> > On 12/5/2017 3:12 PM, Ganapatrao Kulkarni wrote:
>> > > diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
>> > > index 5ad8a18..57e38fd 100644
>> > > --- a/tools/perf/util/pmu.c
>> > > +++ b/tools/perf/util/pmu.c
>> > > @@ -538,6 +538,34 @@ static bool pmu_is_uncore(const char *name)
>> > > }
>> > >
>> > > /*
>> > > + * PMU CORE devices have different name other than cpu in sysfs on some
>> > > + * platforms. looking for possible sysfs files to identify as core
>> > > device.
>> > > + */
>> > > +static int is_pmu_core(const char *name)
>> > > +{
>> > > + struct stat st;
>> > > + char path[PATH_MAX];
>> > > + const char *sysfs = sysfs__mountpoint();
>> > > +
>> > > + if (!sysfs)
>> > > + return 0;
>> > > +
>> > > + /* Look for cpu sysfs (x86 and others) */
>> > > + scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu", sysfs);
>> > > + if ((stat(path, &st) == 0) &&
>> > > + (strncmp(name, "cpu", strlen("cpu")) == 0))
>> > > + return 1;
>> > > +
>> > > + /* Look for cpu sysfs (specific to arm) */
>> > > + scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s/cpus",
>> > > + sysfs, name);
>> > > + if (stat(path, &st) == 0)
>> > > + return 1;
>> > > +
>> > > + return 0;
>> > > +}
>> > > +
>> > > +/*
>> > > * Return the CPU id as a raw string.
>> > > *
>> > > * Each architecture should provide a more precise id string that
>> > > @@ -641,7 +669,7 @@ static void pmu_add_cpu_aliases(struct list_head
>> > > *head, struct perf_pmu *pmu)
>> > > break;
>> > > }
>> > >
>> > > - if (pmu->is_uncore) {
>> > > + if (!is_pmu_core(name)) {
>> > > /* check for uncore devices */
>> > > if (pe->pmu == NULL)
>> > > continue;
thanks
Ganapat
^ permalink raw reply
* [PATCH v9 3/5] perf utils: use pmu->is_uncore to detect PMU UNCORE devices
From: Arnaldo Carvalho de Melo @ 2017-12-05 13:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKTKpr7oM4h_gxj1P=r_J_T5L_Mmtqqj_Uvji-fARKnQRnCP1w@mail.gmail.com>
Em Tue, Dec 05, 2017 at 12:42:30PM +0530, Ganapatrao Kulkarni escreveu:
> thanks Jin Yao for point this out.
>
> looks like logic of leveraging uncore device type(which i have changed
> in v9) does not go well
> with some json events of x86.
> can you please try below diff(logic used till v8), which keeps the
> original logic of identifying core/cpu PMUs.
This seems space mangled :-\
- Arnaldo
>
> diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
> index 5ad8a18..57e38fd 100644
> --- a/tools/perf/util/pmu.c
> +++ b/tools/perf/util/pmu.c
> @@ -538,6 +538,34 @@ static bool pmu_is_uncore(const char *name)
> }
>
> /*
> + * PMU CORE devices have different name other than cpu in sysfs on some
> + * platforms. looking for possible sysfs files to identify as core device.
> + */
> +static int is_pmu_core(const char *name)
> +{
> + struct stat st;
> + char path[PATH_MAX];
> + const char *sysfs = sysfs__mountpoint();
> +
> + if (!sysfs)
> + return 0;
> +
> + /* Look for cpu sysfs (x86 and others) */
> + scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu", sysfs);
> + if ((stat(path, &st) == 0) &&
> + (strncmp(name, "cpu", strlen("cpu")) == 0))
> + return 1;
> +
> + /* Look for cpu sysfs (specific to arm) */
> + scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s/cpus",
> + sysfs, name);
> + if (stat(path, &st) == 0)
> + return 1;
> +
> + return 0;
> +}
> +
> +/*
> * Return the CPU id as a raw string.
> *
> * Each architecture should provide a more precise id string that
> @@ -641,7 +669,7 @@ static void pmu_add_cpu_aliases(struct list_head
> *head, struct perf_pmu *pmu)
> break;
> }
>
> - if (pmu->is_uncore) {
> + if (!is_pmu_core(name)) {
> /* check for uncore devices */
> if (pe->pmu == NULL)
> continue;
>
> i have tried this diff on my x86 PC(haswell) and looks to be ok.
> please confirm your testing on skylake.
>
> gkulkarni at gkFc25>perf>> ./perf stat --per-thread -p 12663 -M CPI,IPC sleep 1
>
> Performance counter stats for process id '12663':
>
> bash-12663 278,886 inst_retired.any:u
> bash-12663 482,284 cycles:u
> bash-12663 278,886 inst_retired.any:u
> bash-12663 483,597
> cpu_clk_unhalted.thread:u
>
> 1.000923760 seconds time elapsed
>
>
> On Tue, Dec 5, 2017 at 7:42 AM, Jin, Yao <yao.jin@linux.intel.com> wrote:
> > Hi Kulkarni, Arnaldo,
> >
> > This patch has been merged in perf/core branch today.
> >
> > But I see a regression issue when I run the 'perf stat'.
> >
> > With bisect checking, I locate to this patch.
> >
> > commit ad8737a08973f5dca632bdd63cf2abc99670e540
> > Author: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> > Date: Tue Oct 17 00:02:20 2017 +0530
> >
> > perf pmu: Use pmu->is_uncore to detect UNCORE devices
> >
> > For example (on Intel skylake desktop),
> >
> > 1. The correct output should be (without this patch):
> >
> > root at skl:/tmp# perf stat --per-thread -p 1754 -M CPI,IPC
> > ^C
> > Performance counter stats for process id '1754':
> >
> > vmstat-1754 1,882,798 inst_retired.any #
> > 0.8 CPI
> > vmstat-1754 1,589,720 cycles
> > vmstat-1754 1,882,798 inst_retired.any #
> > 1.2 IPC
> > vmstat-1754 1,589,720 cpu_clk_unhalted.thread
> >
> > 2.647443167 seconds time elapsed
> >
> > 2. With this patch, the output will be:
> >
> > root at skl:/tmp# perf stat --per-thread -p 1754 -M CPI,IPC
> > ^C
> > Performance counter stats for process id '1754':
> >
> > vmstat-1754 1,945,589 inst_retired.any
> > vmstat-1754 <not supported> inst_retired.any
> > vmstat-1754 1,609,892 cycles
> > vmstat-1754 1,945,589 inst_retired.any
> > vmstat-1754 <not supported> inst_retired.any
> > vmstat-1754 1,609,892 cpu_clk_unhalted.thread
> > vmstat-1754 <not supported> cpu_clk_unhalted.thread
> >
> > 3.051274166 seconds time elapsed
> >
> > Could you please help to take a look?
> >
> > Thanks
> > Jin Yao
> >
> >
> > On 10/17/2017 2:32 AM, Ganapatrao Kulkarni wrote:
> >>
> >> PMU CORE devices are identified using sysfs filename cpu, however
> >> on some platforms(like arm/arm64), PMU CORE sysfs name is not cpu.
> >> Hence cpu cannot be used to differentiate PMU CORE/UNCORE devices.
> >>
> >> commit:
> >> 66ec1191 ("perf pmu: Unbreak perf record for arm/arm64 with events with
> >> explicit PMU")
> >>
> >> has introduced pmu->is_uncore, which is set to PMU UNCORE devices only.
> >> Adding changes to use pmu->is_uncore to identify UNCORE devices.
> >>
> >> Acked-by: Will Deacon <will.deacon@arm.com>
> >> Tested-by: Shaokun Zhang <zhangshaokun@hisilicon.com>
> >> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> >> ---
> >> tools/perf/util/pmu.c | 11 +++++++----
> >> 1 file changed, 7 insertions(+), 4 deletions(-)
> >>
> >> diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
> >> index 8b17db5..9110718 100644
> >> --- a/tools/perf/util/pmu.c
> >> +++ b/tools/perf/util/pmu.c
> >> @@ -603,7 +603,6 @@ static void pmu_add_cpu_aliases(struct list_head
> >> *head, struct perf_pmu *pmu)
> >> */
> >> i = 0;
> >> while (1) {
> >> - const char *pname;
> >> pe = &map->table[i++];
> >> if (!pe->name) {
> >> @@ -612,9 +611,13 @@ static void pmu_add_cpu_aliases(struct list_head
> >> *head, struct perf_pmu *pmu)
> >> break;
> >> }
> >> - pname = pe->pmu ? pe->pmu : "cpu";
> >> - if (strncmp(pname, name, strlen(pname)))
> >> - continue;
> >> + if (pmu->is_uncore) {
> >> + /* check for uncore devices */
> >> + if (pe->pmu == NULL)
> >> + continue;
> >> + if (strncmp(pe->pmu, name, strlen(pe->pmu)))
> >> + continue;
> >> + }
> >> /* need type casts to override 'const' */
> >> __perf_pmu__new_alias(head, NULL, (char *)pe->name,
> >>
> >
>
> thanks
> Ganapat
^ permalink raw reply
* [PATCH v9 3/5] perf utils: use pmu->is_uncore to detect PMU UNCORE devices
From: Arnaldo Carvalho de Melo @ 2017-12-05 13:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1f79aa3c-a061-7c55-5d3e-f13638be01ad@linux.intel.com>
Em Tue, Dec 05, 2017 at 08:35:22PM +0800, Jin, Yao escreveu:
> A quick test with the new patch 'fix_json_v9_2.patch' shows it working.
Where is this fix_json_v9_2.patch file? I want to fold it with the patch
introducing the problem.
- Arnaldo
> See the log:
>
> root at skl:/tmp# perf stat --per-thread -p 10322 -M CPI,IPC
> ^C
> Performance counter stats for process id '10322':
>
> vmstat-10322 1,879,654 inst_retired.any #
> 0.8 CPI
> vmstat-10322 1,565,807 cycles
> vmstat-10322 1,879,654 inst_retired.any #
> 1.2 IPC
> vmstat-10322 1,565,807 cpu_clk_unhalted.thread
>
> 2.850291804 seconds time elapsed
>
> Thanks for fixing it quickly.
>
> Thanks
> Jin Yao
>
> On 12/5/2017 3:23 PM, Jin, Yao wrote:
> > Hi,
> >
> > I applied the diff but it's failed.
> >
> > jinyao at skl:~/skl-ws/perf-dev/lck-4594/src$ patch -p1 < 1.pat
> > patching file tools/perf/util/pmu.c
> > patch: **** malformed patch at line 41: *head, struct perf_pmu *pmu)
> >
> > Could you send the patch as attachment to me in another mail thread?
> >
> > to yao.jin at linux.intel.com
> > cc yao.jin at intel.com
> >
> > Thanks
> > Jin Yao
> >
> > On 12/5/2017 3:12 PM, Ganapatrao Kulkarni wrote:
> > > diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
> > > index 5ad8a18..57e38fd 100644
> > > --- a/tools/perf/util/pmu.c
> > > +++ b/tools/perf/util/pmu.c
> > > @@ -538,6 +538,34 @@ static bool pmu_is_uncore(const char *name)
> > > ? }
> > >
> > > ? /*
> > > + *? PMU CORE devices have different name other than cpu in sysfs on some
> > > + *? platforms. looking for possible sysfs files to identify as core
> > > device.
> > > + */
> > > +static int is_pmu_core(const char *name)
> > > +{
> > > + struct stat st;
> > > + char path[PATH_MAX];
> > > + const char *sysfs = sysfs__mountpoint();
> > > +
> > > + if (!sysfs)
> > > + return 0;
> > > +
> > > + /* Look for cpu sysfs (x86 and others) */
> > > + scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/cpu", sysfs);
> > > + if ((stat(path, &st) == 0) &&
> > > + (strncmp(name, "cpu", strlen("cpu")) == 0))
> > > + return 1;
> > > +
> > > + /* Look for cpu sysfs (specific to arm) */
> > > + scnprintf(path, PATH_MAX, "%s/bus/event_source/devices/%s/cpus",
> > > + sysfs, name);
> > > + if (stat(path, &st) == 0)
> > > + return 1;
> > > +
> > > + return 0;
> > > +}
> > > +
> > > +/*
> > > ?? * Return the CPU id as a raw string.
> > > ?? *
> > > ?? * Each architecture should provide a more precise id string that
> > > @@ -641,7 +669,7 @@ static void pmu_add_cpu_aliases(struct list_head
> > > *head, struct perf_pmu *pmu)
> > > ?? break;
> > > ?? }
> > >
> > > - if (pmu->is_uncore) {
> > > + if (!is_pmu_core(name)) {
> > > ?? /* check for uncore devices */
> > > ?? if (pe->pmu == NULL)
> > > ?? continue;
^ permalink raw reply
* [PATCH v6 2/8] KVM: arm/arm64: Factor out functionality to get vgic mmio requester_vcpu
From: Yury Norov @ 2017-12-05 13:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204200506.3224-3-cdall@kernel.org>
On Mon, Dec 04, 2017 at 09:05:00PM +0100, Christoffer Dall wrote:
> From: Christoffer Dall <christoffer.dall@linaro.org>
>
> We are about to distinguish between userspace accesses and mmio traps
> for a number of the mmio handlers. When the requester vcpu is NULL, it
> mens we are handling a userspace acccess.
Typo: means?
> Factor out the functionality to get the request vcpu into its own
> function, mostly so we have a common place to document the semantics of
> the return value.
>
> Also take the chance to move the functionality outside of holding a
> spinlock and instead explicitly disable and enable preemption. This
> supports PREEMPT_RT kernels as well.
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> ---
> virt/kvm/arm/vgic/vgic-mmio.c | 44 +++++++++++++++++++++++++++----------------
> 1 file changed, 28 insertions(+), 16 deletions(-)
>
> diff --git a/virt/kvm/arm/vgic/vgic-mmio.c b/virt/kvm/arm/vgic/vgic-mmio.c
> index deb51ee16a3d..747b0a3b4784 100644
> --- a/virt/kvm/arm/vgic/vgic-mmio.c
> +++ b/virt/kvm/arm/vgic/vgic-mmio.c
> @@ -122,6 +122,27 @@ unsigned long vgic_mmio_read_pending(struct kvm_vcpu *vcpu,
> return value;
> }
>
> +/*
> + * This function will return the VCPU that performed the MMIO access and
> + * trapped from twithin the VM, and will return NULL if this is a userspace
Typo: from within?
> + * access.
> + *
> + * We can disable preemption locally around accessing the per-CPU variable,
> + * and use the resolved vcpu pointer after enabling preemption again, because
> + * even if the current thread is migrated to another CPU, reading the per-CPU
> + * value later will give us the same value as we update the per-CPU variable
> + * in the preempt notifier handlers.
> + */
> +static struct kvm_vcpu *vgic_get_mmio_requester_vcpu(void)
> +{
> + struct kvm_vcpu *vcpu;
> +
> + preempt_disable();
> + vcpu = kvm_arm_get_running_vcpu();
> + preempt_enable();
> + return vcpu;
> +}
> +
> void vgic_mmio_write_spending(struct kvm_vcpu *vcpu,
> gpa_t addr, unsigned int len,
> unsigned long val)
> @@ -184,24 +205,10 @@ unsigned long vgic_mmio_read_active(struct kvm_vcpu *vcpu,
> static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
> bool new_active_state)
> {
> - struct kvm_vcpu *requester_vcpu;
> unsigned long flags;
> - spin_lock_irqsave(&irq->irq_lock, flags);
> + struct kvm_vcpu *requester_vcpu = vgic_get_mmio_requester_vcpu();
>
> - /*
> - * The vcpu parameter here can mean multiple things depending on how
> - * this function is called; when handling a trap from the kernel it
> - * depends on the GIC version, and these functions are also called as
> - * part of save/restore from userspace.
> - *
> - * Therefore, we have to figure out the requester in a reliable way.
> - *
> - * When accessing VGIC state from user space, the requester_vcpu is
> - * NULL, which is fine, because we guarantee that no VCPUs are running
> - * when accessing VGIC state from user space so irq->vcpu->cpu is
> - * always -1.
> - */
> - requester_vcpu = kvm_arm_get_running_vcpu();
> + spin_lock_irqsave(&irq->irq_lock, flags);
>
> /*
> * If this virtual IRQ was written into a list register, we
> @@ -213,6 +220,11 @@ static void vgic_mmio_change_active(struct kvm_vcpu *vcpu, struct vgic_irq *irq,
> * vgic_change_active_prepare) and still has to sync back this IRQ,
> * so we release and re-acquire the spin_lock to let the other thread
> * sync back the IRQ.
> + *
> + * When accessing VGIC state from user space, requester_vcpu is
> + * NULL, which is fine, because we guarantee that no VCPUs are running
> + * when accessing VGIC state from user space so irq->vcpu->cpu is
> + * always -1.
> */
> while (irq->vcpu && /* IRQ may have state in an LR somewhere */
> irq->vcpu != requester_vcpu && /* Current thread is not the VCPU thread */
> --
> 2.14.2
^ permalink raw reply
* [PATCH] Arm: mm: ftrace: Only set text back to ro after kernel has been marked ro
From: Russell King - ARM Linux @ 2017-12-05 13:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5b9b86cf-4b62-c984-fe52-a22df8fce33c@raspberrypi.org>
On Tue, Dec 05, 2017 at 01:30:11PM +0000, Phil Elwell wrote:
> On 05/12/2017 13:23, Matthias Reichl wrote:
> > On Tue, Dec 05, 2017 at 01:14:17PM +0000, Russell King - ARM Linux wrote:
> >> On Tue, Dec 05, 2017 at 12:47:09PM +0100, Matthias Reichl wrote:
> >>> On Wed, Aug 23, 2017 at 03:03:51PM -0400, Steven Rostedt wrote:
> >>>> On Wed, 23 Aug 2017 11:48:13 -0700
> >>>> Kees Cook <keescook@chromium.org> wrote:
> >>>>
> >>>>>> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> >>>>>> index ad80548..fd75f38 100644
> >>>>>> --- a/arch/arm/mm/init.c
> >>>>>> +++ b/arch/arm/mm/init.c
> >>>>>> @@ -745,19 +745,29 @@ static int __mark_rodata_ro(void *unused)
> >>>>>> return 0;
> >>>>>> }
> >>>>>>
> >>>>>> +static int kernel_set_to_readonly;
> >>>>>
> >>>>> Adding a comment here might be a good idea, something like:
> >>>>>
> >>>>> /* Has system boot-up reached mark_rodata_ro() yet? */
> >>>>
> >>>> I don't mind adding a comment, but the above is rather self explanatory
> >>>> (one can easily see that it is set in mark_rodata_ro() with a simple
> >>>> search).
> >>>>
> >>>> If a comment is to be added, something a bit more descriptive of the
> >>>> functionality of the variable would be appropriate:
> >>>>
> >>>> /*
> >>>> * Ignore modifying kernel text permissions until the kernel core calls
> >>>> * make_rodata_ro() at system start up.
> >>>> */
> >>>>
> >>>> I can resend with the comment, or whoever takes this could add it
> >>>> themselves.
> >>>
> >>> Gentle ping: this patch doesn't seem to have landed in upstream
> >>> trees yet. Is any more work required?
> >>>
> >>> It would be nice to have this fix added. Just tested next-20171205
> >>> on RPi B+, it oopses when the function tracer is enabled during boot.
> >>> next-20171205 plus this patch boots up fine.
> >>
> >> When does it oops?
> >
> > Rather early in the boot process:
> >
> > [ 0.000000] Booting Linux on physical CPU 0x0
> > [ 0.000000] Linux version 4.15.0-rc2-next-20171205 (hias at camel2) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #3 Tue Dec 5 12:35:08 CET 2017
> > [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
> > [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
> > [ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B Plus Rev 1.2
> > [ 0.000000] earlycon: pl11 at MMIO32 0x20201000 (options '')
> > [ 0.000000] bootconsole [pl11] enabled
> > [ 0.000000] Memory policy: Data cache writeback
> > [ 0.000000] cma: Reserved 32 MiB at 0x13c00000
> > [ 0.000000] CPU: All CPU(s) started in SVC mode.
> > [ 0.000000] random: fast init done
> > [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 89408
> > [ 0.000000] Kernel command line: bcm2708_fb.fbwidth=1280 bcm2708_fb.fbheight=1024 bcm2708_fb.fbswap=1 dma.dmachans=0x7f35 bcm2708.boardrev=0x10 bcm2708.serial=0x59ce1e57 bcm2708.uart_clock=48000000 bcm2708.disk_led_gpio=47 bcm2708.disk_led_active_low=0 smsc95xx.macaddr=B8:27:EB:CE:1E:57 vc_mem.mem_base=0x1ec00000 vc_mem.mem_size=0x20000000 root=/dev/mmcblk0p2 rw rootwait elevator=noop earlycon=pl011,mmio32,0x20201000 console=/dev/ttyAMA0,115200 ftrace=function
> > [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> > [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> > [ 0.000000] Memory: 311776K/360448K available (7168K kernel code, 561K rwdata, 2212K rodata, 1024K init, 683K bss, 15904K reserved, 32768K cma-reserved)
> > [ 0.000000] Virtual kernel memory layout:
> > [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> > [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
> > [ 0.000000] vmalloc : 0xd6800000 - 0xff800000 ( 656 MB)
> > [ 0.000000] lowmem : 0xc0000000 - 0xd6000000 ( 352 MB)
> > [ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
> > [ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (8160 kB)
> > [ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
> > [ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 562 kB)
> > [ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) ( 684 kB)
> > [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
> > [ 0.000000] ftrace: allocating 25789 entries in 76 pages
> > [ 0.000000] Starting tracer 'function'
> > [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> > [ 0.000052] sched_clock: 32 bits at 1000kHz, resolution 1000ns, wraps every 2147483647500ns
> > [ 0.008889] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275 ns
> > [ 0.018979] bcm2835: system timer (irq = 27)
> > [ 0.028070] Console: colour dummy device 80x30
> > [ 0.033154] Calibrating delay loop... 697.95 BogoMIPS (lpj=3489792)
> > [ 0.090179] pid_max: default: 32768 minimum: 301
> > [ 0.097851] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> > [ 0.104852] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> > [ 0.117353] CPU: Testing write buffer coherency: ok
> > [ 0.127472] Setting up static identity map for 0x100000 - 0x100054
> > [ 0.145654] devtmpfs: initialized
> > [ 0.235561] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 5
> > [ 0.245751] Unable to handle kernel paging request at virtual address c09eb214
> > [ 0.253373] pgd = 8aaa5336
> > [ 0.256250] [c09eb214] *pgd=0080840e(bad)
> > [ 0.260567] Internal error: Oops: 80d [#1] ARM
> > [ 0.265073] Modules linked in:
> > [ 0.268188] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-next-20171205 #3
> > [ 0.275592] Hardware name: BCM2835
> > [ 0.279046] task: 11ad8790 task.stack: 886fda4c
> > [ 0.283670] PC is at ksysfs_init+0x64/0xb0
> > [ 0.287840] LR is at internal_create_group+0x294/0x2c4
> > [ 0.293049] pc : [<c0b0a33c>] lr : [<c0292898>] psr: 20000053
> > [ 0.299400] sp : d3a3ded0 ip : c028e908 fp : d3a3dee4
> > [ 0.304694] r10: 00000000 r9 : c0c8c500 r8 : c0c8c500
> > [ 0.309991] r7 : 00000000 r6 : c0c04048 r5 : c0c8d19c r4 : 00000000
> > [ 0.316607] r3 : 00000024 r2 : c0abf19c r1 : c09eb20c r0 : d3a81d80
> > [ 0.323224] Flags: nzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment none
> > [ 0.330543] Control: 00c5387d Table: 00004008 DAC: 00000051
> > [ 0.336367] Process swapper (pid: 1, stack limit = 0xfa32e9e1)
> > [ 0.342280] Stack: (0xd3a3ded0 to 0xd3a3e000)
> > [ 0.346703] dec0: 00000001 c0b0a2d8 d3a3df5c d3a3dee8
> > [ 0.354999] dee0: c01027b0 c0b0a2e4 c0a280c0 00000000 d3a3df5c d3a3df00 c0138578 c0b00650
> > [ 0.363294] df00: d3a3df00 c0c0c328 00000000 c0a280d4 0000009f c0a280d4 00000001 00000001
> > [ 0.371590] df20: 000000a0 c0a27454 d5fffd21 d5fffd28 c014f4c0 4710e3ed 00000001 000000a0
> > [ 0.379886] df40: c0b5681c c0b7cb84 c0c8c500 c0c8c500 d3a3df94 d3a3df60 c0b00ef8 c01026f8
> > [ 0.388180] df60: 00000001 00000001 00000000 c0b00644 00000000 c07463a4 00000000 00000000
> > [ 0.396475] df80: 00000000 00000000 d3a3dfac d3a3df98 c07463bc c0b00df0 ffffffff 00000000
> > [ 0.404769] dfa0: 00000000 d3a3dfb0 c01010e8 c07463b0 00000000 00000000 00000000 00000000
> > [ 0.413061] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> > [ 0.421354] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
> > [ 0.429689] [<c0b0a33c>] (ksysfs_init) from [<c01027b0>] (do_one_initcall+0xc4/0x184)
> > [ 0.437652] [<c01027b0>] (do_one_initcall) from [<c0b00ef8>] (kernel_init_freeable+0x114/0x1d4)
> > [ 0.446490] [<c0b00ef8>] (kernel_init_freeable) from [<c07463bc>] (kernel_init+0x18/0x11c)
> > [ 0.454887] [<c07463bc>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c)
> > [ 0.462559] Exception stack(0xd3a3dfb0 to 0xd3a3dff8)
> > [ 0.467683] dfa0: 00000000 00000000 00000000 00000000
> > [ 0.475976] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> > [ 0.484266] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
> > [ 0.490982] Code: e3a00000 e89da830 e59f1048 e5950000 (e5813008)
> > [ 0.497194] ---[ end trace 53d55c7b93eb8c51 ]---
> > [ 0.502064] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
> > [ 0.502064]
> > [ 0.511346] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
> > [ 0.511346]
> >
> > so long,
> >
> > Hias
> >
> >>
> >> Reading through this code, I'm left wondering why we switch the rodata
> >> section to be writable here - if we're poking at kernel text, then
> >> surely we shouldn't be the read-only data read-write?
> >>
> >> Should kernel_set_to_readonly also be a rodata-after-init variable?
>
> This was my initial explanation:
>
> 1. Data which is marked __ro_after_init is initially writeable.
>
> 2. The ro_perms data covers kernel text, read-only data and __ro_after_init data.
>
> 3. set_kernel_text_rw marks everything in ro_perms as writeable.
>
> 4. set_kernel_text_ro marks everything in ro_perms as read-only, including the __ro_after_init data.
>
> 5. Using the function tracing code involves code modification, resulting in calls to
> __ftrace_modify_code and set_kernel_text_ro.
>
> 6. Therefore if function tracing is enabled before kernel_init has completed then the __ro_after_init
> data is made read-only prematurely.
My question still stands, but let me rephrase. Do we need
set_kernel_text_*() to touch the read-only data?
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH v2 3/3] mtd: nand: squash struct nand_buffers into struct nand_chip
From: Boris Brezillon @ 2017-12-05 13:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK7LNAQken7cQEPJEyL107pLbVJ9rPc+zZoPh4CA8D+CiKZz4g@mail.gmail.com>
Hi Masahiro,
On Tue, 5 Dec 2017 21:28:55 +0900
Masahiro Yamada <yamada.masahiro@socionext.com> wrote:
> Hi Boris,
>
> 2017-12-05 20:57 GMT+09:00 Boris Brezillon <boris.brezillon@free-electrons.com>:
> >>
> >>
> >> Sorry, I missed to update omap2.c
> >>
> >> I will send v3.
> >
> > No need to send a v3, I already fixed it when applying [1].
> >
> > [1]https://github.com/bbrezillon/linux-0day/commit/59a7bfff7103d48713b2125c3844400301a3d028
> >
>
> Thank you for your kind help!
>
>
No problem.
Thanks for working on improving the NAND framework, and if you're
looking for other things to cleanup in this area, I have a long TODO
list, so don't hesitate to ask. Just one example: I'd like to
dynamically allocate the onfi/jedec_params [1] struct instead of
embedding them in the nand_chip struct, because this increases the size
of the nand_chip object for everyone, even for those who don't have
ONFI/JEDEC compliant chips.
This should also allow us to get rid of the onfi/jedec_version fields
(if chip->onfi_params or chip->jedec_params are NULL, the NAND is not
ONFI or JEDEC compliant and the version has no meaning, if it's not
NULL, the version can be directly retrieved from the ->onfi/jedec_params
object itself).
Regards,
Boris
[1]http://elixir.free-electrons.com/linux/v4.15-rc2/source/include/linux/mtd/rawnand.h#L922
^ permalink raw reply
* [PATCH] Arm: mm: ftrace: Only set text back to ro after kernel has been marked ro
From: Phil Elwell @ 2017-12-05 13:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205132339.behn34z6b7ci2m4j@camel2.lan>
On 05/12/2017 13:23, Matthias Reichl wrote:
> On Tue, Dec 05, 2017 at 01:14:17PM +0000, Russell King - ARM Linux wrote:
>> On Tue, Dec 05, 2017 at 12:47:09PM +0100, Matthias Reichl wrote:
>>> On Wed, Aug 23, 2017 at 03:03:51PM -0400, Steven Rostedt wrote:
>>>> On Wed, 23 Aug 2017 11:48:13 -0700
>>>> Kees Cook <keescook@chromium.org> wrote:
>>>>
>>>>>> diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
>>>>>> index ad80548..fd75f38 100644
>>>>>> --- a/arch/arm/mm/init.c
>>>>>> +++ b/arch/arm/mm/init.c
>>>>>> @@ -745,19 +745,29 @@ static int __mark_rodata_ro(void *unused)
>>>>>> return 0;
>>>>>> }
>>>>>>
>>>>>> +static int kernel_set_to_readonly;
>>>>>
>>>>> Adding a comment here might be a good idea, something like:
>>>>>
>>>>> /* Has system boot-up reached mark_rodata_ro() yet? */
>>>>
>>>> I don't mind adding a comment, but the above is rather self explanatory
>>>> (one can easily see that it is set in mark_rodata_ro() with a simple
>>>> search).
>>>>
>>>> If a comment is to be added, something a bit more descriptive of the
>>>> functionality of the variable would be appropriate:
>>>>
>>>> /*
>>>> * Ignore modifying kernel text permissions until the kernel core calls
>>>> * make_rodata_ro() at system start up.
>>>> */
>>>>
>>>> I can resend with the comment, or whoever takes this could add it
>>>> themselves.
>>>
>>> Gentle ping: this patch doesn't seem to have landed in upstream
>>> trees yet. Is any more work required?
>>>
>>> It would be nice to have this fix added. Just tested next-20171205
>>> on RPi B+, it oopses when the function tracer is enabled during boot.
>>> next-20171205 plus this patch boots up fine.
>>
>> When does it oops?
>
> Rather early in the boot process:
>
> [ 0.000000] Booting Linux on physical CPU 0x0
> [ 0.000000] Linux version 4.15.0-rc2-next-20171205 (hias at camel2) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #3 Tue Dec 5 12:35:08 CET 2017
> [ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
> [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
> [ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B Plus Rev 1.2
> [ 0.000000] earlycon: pl11 at MMIO32 0x20201000 (options '')
> [ 0.000000] bootconsole [pl11] enabled
> [ 0.000000] Memory policy: Data cache writeback
> [ 0.000000] cma: Reserved 32 MiB at 0x13c00000
> [ 0.000000] CPU: All CPU(s) started in SVC mode.
> [ 0.000000] random: fast init done
> [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 89408
> [ 0.000000] Kernel command line: bcm2708_fb.fbwidth=1280 bcm2708_fb.fbheight=1024 bcm2708_fb.fbswap=1 dma.dmachans=0x7f35 bcm2708.boardrev=0x10 bcm2708.serial=0x59ce1e57 bcm2708.uart_clock=48000000 bcm2708.disk_led_gpio=47 bcm2708.disk_led_active_low=0 smsc95xx.macaddr=B8:27:EB:CE:1E:57 vc_mem.mem_base=0x1ec00000 vc_mem.mem_size=0x20000000 root=/dev/mmcblk0p2 rw rootwait elevator=noop earlycon=pl011,mmio32,0x20201000 console=/dev/ttyAMA0,115200 ftrace=function
> [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
> [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
> [ 0.000000] Memory: 311776K/360448K available (7168K kernel code, 561K rwdata, 2212K rodata, 1024K init, 683K bss, 15904K reserved, 32768K cma-reserved)
> [ 0.000000] Virtual kernel memory layout:
> [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
> [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
> [ 0.000000] vmalloc : 0xd6800000 - 0xff800000 ( 656 MB)
> [ 0.000000] lowmem : 0xc0000000 - 0xd6000000 ( 352 MB)
> [ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
> [ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (8160 kB)
> [ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
> [ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 562 kB)
> [ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) ( 684 kB)
> [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
> [ 0.000000] ftrace: allocating 25789 entries in 76 pages
> [ 0.000000] Starting tracer 'function'
> [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
> [ 0.000052] sched_clock: 32 bits at 1000kHz, resolution 1000ns, wraps every 2147483647500ns
> [ 0.008889] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275 ns
> [ 0.018979] bcm2835: system timer (irq = 27)
> [ 0.028070] Console: colour dummy device 80x30
> [ 0.033154] Calibrating delay loop... 697.95 BogoMIPS (lpj=3489792)
> [ 0.090179] pid_max: default: 32768 minimum: 301
> [ 0.097851] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [ 0.104852] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
> [ 0.117353] CPU: Testing write buffer coherency: ok
> [ 0.127472] Setting up static identity map for 0x100000 - 0x100054
> [ 0.145654] devtmpfs: initialized
> [ 0.235561] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 5
> [ 0.245751] Unable to handle kernel paging request at virtual address c09eb214
> [ 0.253373] pgd = 8aaa5336
> [ 0.256250] [c09eb214] *pgd=0080840e(bad)
> [ 0.260567] Internal error: Oops: 80d [#1] ARM
> [ 0.265073] Modules linked in:
> [ 0.268188] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-next-20171205 #3
> [ 0.275592] Hardware name: BCM2835
> [ 0.279046] task: 11ad8790 task.stack: 886fda4c
> [ 0.283670] PC is at ksysfs_init+0x64/0xb0
> [ 0.287840] LR is at internal_create_group+0x294/0x2c4
> [ 0.293049] pc : [<c0b0a33c>] lr : [<c0292898>] psr: 20000053
> [ 0.299400] sp : d3a3ded0 ip : c028e908 fp : d3a3dee4
> [ 0.304694] r10: 00000000 r9 : c0c8c500 r8 : c0c8c500
> [ 0.309991] r7 : 00000000 r6 : c0c04048 r5 : c0c8d19c r4 : 00000000
> [ 0.316607] r3 : 00000024 r2 : c0abf19c r1 : c09eb20c r0 : d3a81d80
> [ 0.323224] Flags: nzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment none
> [ 0.330543] Control: 00c5387d Table: 00004008 DAC: 00000051
> [ 0.336367] Process swapper (pid: 1, stack limit = 0xfa32e9e1)
> [ 0.342280] Stack: (0xd3a3ded0 to 0xd3a3e000)
> [ 0.346703] dec0: 00000001 c0b0a2d8 d3a3df5c d3a3dee8
> [ 0.354999] dee0: c01027b0 c0b0a2e4 c0a280c0 00000000 d3a3df5c d3a3df00 c0138578 c0b00650
> [ 0.363294] df00: d3a3df00 c0c0c328 00000000 c0a280d4 0000009f c0a280d4 00000001 00000001
> [ 0.371590] df20: 000000a0 c0a27454 d5fffd21 d5fffd28 c014f4c0 4710e3ed 00000001 000000a0
> [ 0.379886] df40: c0b5681c c0b7cb84 c0c8c500 c0c8c500 d3a3df94 d3a3df60 c0b00ef8 c01026f8
> [ 0.388180] df60: 00000001 00000001 00000000 c0b00644 00000000 c07463a4 00000000 00000000
> [ 0.396475] df80: 00000000 00000000 d3a3dfac d3a3df98 c07463bc c0b00df0 ffffffff 00000000
> [ 0.404769] dfa0: 00000000 d3a3dfb0 c01010e8 c07463b0 00000000 00000000 00000000 00000000
> [ 0.413061] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 0.421354] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
> [ 0.429689] [<c0b0a33c>] (ksysfs_init) from [<c01027b0>] (do_one_initcall+0xc4/0x184)
> [ 0.437652] [<c01027b0>] (do_one_initcall) from [<c0b00ef8>] (kernel_init_freeable+0x114/0x1d4)
> [ 0.446490] [<c0b00ef8>] (kernel_init_freeable) from [<c07463bc>] (kernel_init+0x18/0x11c)
> [ 0.454887] [<c07463bc>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c)
> [ 0.462559] Exception stack(0xd3a3dfb0 to 0xd3a3dff8)
> [ 0.467683] dfa0: 00000000 00000000 00000000 00000000
> [ 0.475976] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
> [ 0.484266] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
> [ 0.490982] Code: e3a00000 e89da830 e59f1048 e5950000 (e5813008)
> [ 0.497194] ---[ end trace 53d55c7b93eb8c51 ]---
> [ 0.502064] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
> [ 0.502064]
> [ 0.511346] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
> [ 0.511346]
>
> so long,
>
> Hias
>
>>
>> Reading through this code, I'm left wondering why we switch the rodata
>> section to be writable here - if we're poking at kernel text, then
>> surely we shouldn't be the read-only data read-write?
>>
>> Should kernel_set_to_readonly also be a rodata-after-init variable?
This was my initial explanation:
1. Data which is marked __ro_after_init is initially writeable.
2. The ro_perms data covers kernel text, read-only data and __ro_after_init data.
3. set_kernel_text_rw marks everything in ro_perms as writeable.
4. set_kernel_text_ro marks everything in ro_perms as read-only, including the __ro_after_init data.
5. Using the function tracing code involves code modification, resulting in calls to
__ftrace_modify_code and set_kernel_text_ro.
6. Therefore if function tracing is enabled before kernel_init has completed then the __ro_after_init
data is made read-only prematurely.
Phil
^ permalink raw reply
* [PATCH] ASoC: atmel-classd: select correct Kconfig symbol
From: Arnd Bergmann @ 2017-12-05 13:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205124707.GJ21780@piout.net>
On Tue, Dec 5, 2017 at 1:47 PM, Alexandre Belloni
<alexandre.belloni@free-electrons.com> wrote:
> On 05/12/2017 at 12:13:41 +0100, Arnd Bergmann wrote:
>
> Ok, does that solve both randconfigs?
>
> diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig
> index 4a56f3dfba51..dcee145dd179 100644
> --- a/sound/soc/atmel/Kconfig
> +++ b/sound/soc/atmel/Kconfig
> @@ -64,7 +64,7 @@ config SND_AT91_SOC_SAM9X5_WM8731
> config SND_ATMEL_SOC_CLASSD
> tristate "Atmel ASoC driver for boards using CLASSD"
> depends on ARCH_AT91 || COMPILE_TEST
> - select SND_ATMEL_SOC_DMA
> + select SND_SOC_GENERIC_DMAENGINE_PCM
> select REGMAP_MMIO
> help
> Say Y if you want to add support for Atmel ASoC driver for boards using
Yes, that works as well and looks reliable. I've sent another
follow-up now, working on the
assumption that we actually need SND_ATMEL_SOC_DMA.
Both patches make it build, but obviously only one of the two is
actually correct. I assume you know what you are doing, so if
you want to send your patch with a proper changelog, please add
my
Tested-by: Arnd Bergmann <arnd@arndb.de>
Arnd
^ permalink raw reply
* [PATCH] [v2] ASoC: atmel-classd: improve Kconfig dependencies
From: Alexandre Belloni @ 2017-12-05 13:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205131022.2082003-1-arnd@arndb.de>
On 05/12/2017 at 14:10:11 +0100, Arnd Bergmann wrote:
> Commit 061981ff8cc8 ("ASoC: atmel: properly select dma driver state")
> changed the way that the dependencies are handled, but then the
> Class D amplifier support got merged, which used the old method.
>
> This seems to have triggered a very rare randconfig condition for me
> now, leading to a link error:
>
> sound/soc/atmel/atmel_ssc_dai.o: In function `atmel_ssc_set_audio':
> atmel_ssc_dai.c:(.text+0x79c): undefined reference to `atmel_pcm_dma_platform_register'
> atmel_ssc_dai.c:(.text+0x79c): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `atmel_pcm_dma_platform_register'
> sound/soc/atmel/atmel_ssc_dai.o: In function `atmel_ssc_put_audio':
> atmel_ssc_dai.c:(.text+0xf24): undefined reference to `atmel_pcm_dma_platform_unregister'
> atmel_ssc_dai.c:(.text+0xf24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `atmel_pcm_dma_platform_unregister'
>
> This changes the SND_ATMEL_SOC_DMA option so it gets built whenever
> one of the two users (SND_ATMEL_SOC_SSC_DMA and SND_ATMEL_SOC_CLASSD)
> is enabled, with the twist that we make it built-in when SND_ATMEL_SOC_SSC
> is built-in, even if one of the other two is a module.
>
> I think this captures best what the real dependency in the hardware
> is, and it simplifies the logic a bit.
>
> Fixes: e0a25b6d1862 ("ASoC: atmel-classd: add the Audio Class D Amplifier")
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> v2: rewrite the change completely, after running into a new regression.
>
> I'm putting it out on the list so we can review the change together,
> but I'm still doing more testing at the same time. If I don't reply
> by Dec 6, nothing new has come up.
> ---
> sound/soc/atmel/Kconfig | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig
> index 4a56f3dfba51..af9a9096d50b 100644
> --- a/sound/soc/atmel/Kconfig
> +++ b/sound/soc/atmel/Kconfig
> @@ -20,8 +20,8 @@ config SND_ATMEL_SOC_SSC_PDC
> config SND_ATMEL_SOC_DMA
> tristate
> select SND_SOC_GENERIC_DMAENGINE_PCM
> - default m if SND_ATMEL_SOC_SSC_DMA=m && SND_ATMEL_SOC_SSC=m
> - default y if SND_ATMEL_SOC_SSC_DMA=y || (SND_ATMEL_SOC_SSC_DMA=m && SND_ATMEL_SOC_SSC=y)
> + default y if SND_ATMEL_SOC_SSC=y && (SND_ATMEL_SOC_SSC_DMA=m || SND_ATMEL_SOC_CLASSD=m)
> + default SND_ATMEL_SOC_CLASSD || SND_ATMEL_SOC_SSC_DMA
>
I really think the only required dependency for SND_ATMEL_SOC_CLASSD is
SND_SOC_GENERIC_DMAENGINE_PCM. It comes with SND_ATMEL_SOC_DMA but it
doesn't actually use anything provided specifically by atmel-pcm-dma.c
Basically, it handles all of its DMA operations itself.
> config SND_ATMEL_SOC_SSC_DMA
> tristate
> @@ -64,7 +64,6 @@ config SND_AT91_SOC_SAM9X5_WM8731
> config SND_ATMEL_SOC_CLASSD
> tristate "Atmel ASoC driver for boards using CLASSD"
> depends on ARCH_AT91 || COMPILE_TEST
> - select SND_ATMEL_SOC_DMA
> select REGMAP_MMIO
> help
> Say Y if you want to add support for Atmel ASoC driver for boards using
> --
> 2.9.0
>
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] arm64: dirty memory check, enable soft dirty for arm64
From: Steve Capper @ 2017-12-05 13:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512029649-61312-1-git-send-email-bin.lu@arm.com>
Hi Bin,
On Thu, Nov 30, 2017 at 12:14:09AM -0800, Bin Lu wrote:
> arch/arm64/Kconfig: enable CONFIG_HAVE_ARCH_SOFT_DIRTY
> arch/arm64/include/asm/pgtable.h: enable functions for soft dirty
>
> Checkpoint/Restore In Userspace(CRIU) needs the page's change
> to be soft tracked. This allows to do a pre checkpoint and then dump
> only touched pages.
>
> This is done by using a PTE bit (PTE_DIRTY) when
> the page is backed in memory, and a new _PAGE_SWP_SOFT_DIRTY bit when
> the page is swapped out.
>
> The bit of PTE_DIRTY is already defined in pgtable-prot.h.
>
> The _PAGE_SWP_SOFT_DIRTY bit is set as 59 in the swap pte.
>
> pmd_dirty and pmd_mkclean for THP page MADV_FREE also were
> supported in this patch.
>
> This patch has been tested with ZDTM test suite in CRIU.
> Such as: ./zdtm.py run -t zdtm/static/env00 --pre 10
> Signed-off-by: Bin Lu <bin.lu@arm.com>
> ---
> arch/arm64/Kconfig | 1 +
> arch/arm64/include/asm/pgtable.h | 46 ++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 47 insertions(+)
>
> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
> index dfd9086..933f5be 100644
> --- a/arch/arm64/Kconfig
> +++ b/arch/arm64/Kconfig
> @@ -73,6 +73,7 @@ config ARM64
> select HAVE_ARCH_MMAP_RND_BITS
> select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
> select HAVE_ARCH_SECCOMP_FILTER
> + select HAVE_ARCH_SOFT_DIRTY
> select HAVE_ARCH_TRACEHOOK
> select HAVE_ARCH_TRANSPARENT_HUGEPAGE
> select HAVE_ARM_SMCCC
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 6eae342..8ab251e 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -306,6 +306,28 @@ static inline pgprot_t mk_sect_prot(pgprot_t prot)
> return __pgprot(pgprot_val(prot) & ~PTE_TABLE_BIT);
> }
>
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline bool pte_soft_dirty(pte_t pte)
> +{
> + return pte_sw_dirty(pte);
> +}
> +
> +static inline pte_t pte_mksoft_dirty(pte_t pte)
> +{
> + return pte_mkdirty(pte);
> +}
> +
> +static inline pte_t pte_clear_soft_dirty(pte_t pte)
> +{
> + return pte_mkclean(pte);
> +}
> +
> +#define pmd_soft_dirty(pmd) pte_soft_dirty(pmd_pte(pmd))
> +#define pmd_mksoft_dirty(pmd) pte_pmd(pte_mksoft_dirty(pmd_pte(pmd)))
> +#define pmd_clear_soft_dirty(pmd) pte_pmd(pte_clear_soft_dirty(pmd_pte(pmd)))
> +
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> +
> #ifdef CONFIG_NUMA_BALANCING
> /*
> * See the comment in include/asm-generic/pgtable.h
> @@ -695,10 +717,12 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
> * bits 2-7: swap type
> * bits 8-57: swap offset
> * bit 58: PTE_PROT_NONE (must be zero)
> + * bit 59: swap software dirty tracking
> */
> #define __SWP_TYPE_SHIFT 2
> #define __SWP_TYPE_BITS 6
> #define __SWP_OFFSET_BITS 50
> +#define __SWP_PROT_NONE_BITS 1
> #define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
> #define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
> #define __SWP_OFFSET_MASK ((1UL << __SWP_OFFSET_BITS) - 1)
> @@ -710,6 +734,28 @@ extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
> #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
> #define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
>
> +#ifdef CONFIG_MEM_SOFT_DIRTY
> +#define _PAGE_SWP_SOFT_DIRTY (1UL << (__SWP_OFFSET_SHIFT + __SWP_OFFSET_BITS + __SWP_PROT_NONE_BITS))
> +#else
> +#define _PAGE_SWP_SOFT_DIRTY 0UL
> +#endif /* CONFIG_MEM_SOFT_DIRTY */
> +
> +#ifdef CONFIG_HAVE_ARCH_SOFT_DIRTY
> +static inline bool pte_swp_soft_dirty(pte_t pte)
> +{
> + return !!(pte_val(pte) & _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_mksoft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) | _PAGE_SWP_SOFT_DIRTY);
> +}
> +
> +static inline pte_t pte_swp_clear_soft_dirty(pte_t pte)
> +{
> + return __pte(pte_val(pte) & ~_PAGE_SWP_SOFT_DIRTY);
> +}
> +#endif /* CONFIG_HAVE_ARCH_SOFT_DIRTY */
> /*
> * Ensure that there are not more swap files than can be encoded in the kernel
> * PTEs.
> --
This looks good to me. Soft dirty pte's are created by both pte_mkdirty
and pte_mksoft_dirty. If a soft-dirty bit is cleared by
clear_soft_dirty(.), then the pte is also made read-only. Meaning
hardware DBM won't set the pte as dirty on write, a fault will take place
and then the pte will be made both writable and soft dirty.
Some changes to ptep_set_wrprotect(.) to preserve the dirty bit may
cause more soft dirty pte's to appear:
http://lists.infradead.org/pipermail/linux-arm-kernel/2017-December/545151.html
I *think* that shouldn't affect the use case I understand for the
patch - to identify whether or not a page has been written to since
last cleaned.
FWIW:
Reviewed-by: Steve Capper <steve.capper@arm.com>
Cheers,
--
Steve
^ permalink raw reply
* [PATCH] Arm: mm: ftrace: Only set text back to ro after kernel has been marked ro
From: Matthias Reichl @ 2017-12-05 13:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205131416.GW10595@n2100.armlinux.org.uk>
On Tue, Dec 05, 2017 at 01:14:17PM +0000, Russell King - ARM Linux wrote:
> On Tue, Dec 05, 2017 at 12:47:09PM +0100, Matthias Reichl wrote:
> > On Wed, Aug 23, 2017 at 03:03:51PM -0400, Steven Rostedt wrote:
> > > On Wed, 23 Aug 2017 11:48:13 -0700
> > > Kees Cook <keescook@chromium.org> wrote:
> > >
> > > > > diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> > > > > index ad80548..fd75f38 100644
> > > > > --- a/arch/arm/mm/init.c
> > > > > +++ b/arch/arm/mm/init.c
> > > > > @@ -745,19 +745,29 @@ static int __mark_rodata_ro(void *unused)
> > > > > return 0;
> > > > > }
> > > > >
> > > > > +static int kernel_set_to_readonly;
> > > >
> > > > Adding a comment here might be a good idea, something like:
> > > >
> > > > /* Has system boot-up reached mark_rodata_ro() yet? */
> > >
> > > I don't mind adding a comment, but the above is rather self explanatory
> > > (one can easily see that it is set in mark_rodata_ro() with a simple
> > > search).
> > >
> > > If a comment is to be added, something a bit more descriptive of the
> > > functionality of the variable would be appropriate:
> > >
> > > /*
> > > * Ignore modifying kernel text permissions until the kernel core calls
> > > * make_rodata_ro() at system start up.
> > > */
> > >
> > > I can resend with the comment, or whoever takes this could add it
> > > themselves.
> >
> > Gentle ping: this patch doesn't seem to have landed in upstream
> > trees yet. Is any more work required?
> >
> > It would be nice to have this fix added. Just tested next-20171205
> > on RPi B+, it oopses when the function tracer is enabled during boot.
> > next-20171205 plus this patch boots up fine.
>
> When does it oops?
Rather early in the boot process:
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.15.0-rc2-next-20171205 (hias at camel2) (gcc version 4.9.3 (crosstool-NG crosstool-ng-1.22.0-88-g8460611)) #3 Tue Dec 5 12:35:08 CET 2017
[ 0.000000] CPU: ARMv6-compatible processor [410fb767] revision 7 (ARMv7), cr=00c5387d
[ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT nonaliasing instruction cache
[ 0.000000] OF: fdt: Machine model: Raspberry Pi Model B Plus Rev 1.2
[ 0.000000] earlycon: pl11 at MMIO32 0x20201000 (options '')
[ 0.000000] bootconsole [pl11] enabled
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] cma: Reserved 32 MiB at 0x13c00000
[ 0.000000] CPU: All CPU(s) started in SVC mode.
[ 0.000000] random: fast init done
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 89408
[ 0.000000] Kernel command line: bcm2708_fb.fbwidth=1280 bcm2708_fb.fbheight=1024 bcm2708_fb.fbswap=1 dma.dmachans=0x7f35 bcm2708.boardrev=0x10 bcm2708.serial=0x59ce1e57 bcm2708.uart_clock=48000000 bcm2708.disk_led_gpio=47 bcm2708.disk_led_active_low=0 smsc95xx.macaddr=B8:27:EB:CE:1E:57 vc_mem.mem_base=0x1ec00000 vc_mem.mem_size=0x20000000 root=/dev/mmcblk0p2 rw rootwait elevator=noop earlycon=pl011,mmio32,0x20201000 console=/dev/ttyAMA0,115200 ftrace=function
[ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes)
[ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes)
[ 0.000000] Memory: 311776K/360448K available (7168K kernel code, 561K rwdata, 2212K rodata, 1024K init, 683K bss, 15904K reserved, 32768K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xd6800000 - 0xff800000 ( 656 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xd6000000 ( 352 MB)
[ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
[ 0.000000] .text : 0x(ptrval) - 0x(ptrval) (8160 kB)
[ 0.000000] .init : 0x(ptrval) - 0x(ptrval) (1024 kB)
[ 0.000000] .data : 0x(ptrval) - 0x(ptrval) ( 562 kB)
[ 0.000000] .bss : 0x(ptrval) - 0x(ptrval) ( 684 kB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
[ 0.000000] ftrace: allocating 25789 entries in 76 pages
[ 0.000000] Starting tracer 'function'
[ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16
[ 0.000052] sched_clock: 32 bits at 1000kHz, resolution 1000ns, wraps every 2147483647500ns
[ 0.008889] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 1911260446275 ns
[ 0.018979] bcm2835: system timer (irq = 27)
[ 0.028070] Console: colour dummy device 80x30
[ 0.033154] Calibrating delay loop... 697.95 BogoMIPS (lpj=3489792)
[ 0.090179] pid_max: default: 32768 minimum: 301
[ 0.097851] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.104852] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.117353] CPU: Testing write buffer coherency: ok
[ 0.127472] Setting up static identity map for 0x100000 - 0x100054
[ 0.145654] devtmpfs: initialized
[ 0.235561] VFP support v0.3: implementor 41 architecture 1 part 20 variant b rev 5
[ 0.245751] Unable to handle kernel paging request at virtual address c09eb214
[ 0.253373] pgd = 8aaa5336
[ 0.256250] [c09eb214] *pgd=0080840e(bad)
[ 0.260567] Internal error: Oops: 80d [#1] ARM
[ 0.265073] Modules linked in:
[ 0.268188] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-next-20171205 #3
[ 0.275592] Hardware name: BCM2835
[ 0.279046] task: 11ad8790 task.stack: 886fda4c
[ 0.283670] PC is at ksysfs_init+0x64/0xb0
[ 0.287840] LR is at internal_create_group+0x294/0x2c4
[ 0.293049] pc : [<c0b0a33c>] lr : [<c0292898>] psr: 20000053
[ 0.299400] sp : d3a3ded0 ip : c028e908 fp : d3a3dee4
[ 0.304694] r10: 00000000 r9 : c0c8c500 r8 : c0c8c500
[ 0.309991] r7 : 00000000 r6 : c0c04048 r5 : c0c8d19c r4 : 00000000
[ 0.316607] r3 : 00000024 r2 : c0abf19c r1 : c09eb20c r0 : d3a81d80
[ 0.323224] Flags: nzCv IRQs on FIQs off Mode SVC_32 ISA ARM Segment none
[ 0.330543] Control: 00c5387d Table: 00004008 DAC: 00000051
[ 0.336367] Process swapper (pid: 1, stack limit = 0xfa32e9e1)
[ 0.342280] Stack: (0xd3a3ded0 to 0xd3a3e000)
[ 0.346703] dec0: 00000001 c0b0a2d8 d3a3df5c d3a3dee8
[ 0.354999] dee0: c01027b0 c0b0a2e4 c0a280c0 00000000 d3a3df5c d3a3df00 c0138578 c0b00650
[ 0.363294] df00: d3a3df00 c0c0c328 00000000 c0a280d4 0000009f c0a280d4 00000001 00000001
[ 0.371590] df20: 000000a0 c0a27454 d5fffd21 d5fffd28 c014f4c0 4710e3ed 00000001 000000a0
[ 0.379886] df40: c0b5681c c0b7cb84 c0c8c500 c0c8c500 d3a3df94 d3a3df60 c0b00ef8 c01026f8
[ 0.388180] df60: 00000001 00000001 00000000 c0b00644 00000000 c07463a4 00000000 00000000
[ 0.396475] df80: 00000000 00000000 d3a3dfac d3a3df98 c07463bc c0b00df0 ffffffff 00000000
[ 0.404769] dfa0: 00000000 d3a3dfb0 c01010e8 c07463b0 00000000 00000000 00000000 00000000
[ 0.413061] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.421354] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000 00000000 00000000
[ 0.429689] [<c0b0a33c>] (ksysfs_init) from [<c01027b0>] (do_one_initcall+0xc4/0x184)
[ 0.437652] [<c01027b0>] (do_one_initcall) from [<c0b00ef8>] (kernel_init_freeable+0x114/0x1d4)
[ 0.446490] [<c0b00ef8>] (kernel_init_freeable) from [<c07463bc>] (kernel_init+0x18/0x11c)
[ 0.454887] [<c07463bc>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c)
[ 0.462559] Exception stack(0xd3a3dfb0 to 0xd3a3dff8)
[ 0.467683] dfa0: 00000000 00000000 00000000 00000000
[ 0.475976] dfc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
[ 0.484266] dfe0: 00000000 00000000 00000000 00000000 00000013 00000000
[ 0.490982] Code: e3a00000 e89da830 e59f1048 e5950000 (e5813008)
[ 0.497194] ---[ end trace 53d55c7b93eb8c51 ]---
[ 0.502064] Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 0.502064]
[ 0.511346] ---[ end Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
[ 0.511346]
so long,
Hias
>
> Reading through this code, I'm left wondering why we switch the rodata
> section to be writable here - if we're poking at kernel text, then
> surely we shouldn't be the read-only data read-write?
>
> Should kernel_set_to_readonly also be a rodata-after-init variable?
^ permalink raw reply
* [PATCH] irqchip/gic-v3: Fix the driver probe() fail due to disabled GICC entry
From: Shanker Donthineni @ 2017-12-05 13:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a854553a-f751-842d-c813-1871b18aae75@arm.com>
Hi Marc,
On 12/05/2017 02:59 AM, Marc Zyngier wrote:
> On 04/12/17 14:04, Shanker Donthineni wrote:
>> Hi Thanks,
>>
>> On 12/04/2017 04:28 AM, Marc Zyngier wrote:
>>> On 03/12/17 23:21, Shanker Donthineni wrote:
>>>> As per MADT specification, it's perfectly valid firmware can pass
>>>> MADT table to OS with disabled GICC entries. ARM64-SMP code skips
>>>> those cpu cores to bring online. However the current GICv3 driver
>>>> probe bails out in this case on systems where redistributor regions
>>>> are not in the always-on power domain.
>>>>
>>>> This patch does the two things to fix the panic.
>>>> - Don't return an error in gic_acpi_match_gicc() for disabled GICC.
>>>> - No need to keep GICR region information for disabled GICC.
>>>>
>>>> Kernel crash traces:
>>>> Kernel panic - not syncing: No interrupt controller found.
>>>> CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.13.5 #26
>>>> [<ffff000008087770>] dump_backtrace+0x0/0x218
>>>> [<ffff0000080879dc>] show_stack+0x14/0x20
>>>> [<ffff00000883b078>] dump_stack+0x98/0xb8
>>>> [<ffff0000080c5c14>] panic+0x118/0x26c
>>>> [<ffff000008b62348>] init_IRQ+0x24/0x2c
>>>> [<ffff000008b609fc>] start_kernel+0x230/0x394
>>>> [<ffff000008b601e4>] __primary_switched+0x64/0x6c
>>>> ---[ end Kernel panic - not syncing: No interrupt controller found.
>>>>
>>>> Disabled GICC subtable example:
>>>> Subtable Type : 0B [Generic Interrupt Controller]
>>>> Length : 50
>>>> Reserved : 0000
>>>> CPU Interface Number : 0000003D
>>>> Processor UID : 0000003D
>>>> Flags (decoded below) : 00000000
>>>> Processor Enabled : 0
>>>> Performance Interrupt Trig Mode : 0
>>>> Virtual GIC Interrupt Trig Mode : 0
>>>> Parking Protocol Version : 00000000
>>>> Performance Interrupt : 00000017
>>>> Parked Address : 0000000000000000
>>>> Base Address : 0000000000000000
>>>> Virtual GIC Base Address : 0000000000000000
>>>> Hypervisor GIC Base Address : 0000000000000000
>>>> Virtual GIC Interrupt : 00000019
>>>> Redistributor Base Address : 0000FFFF88F40000
>>>> ARM MPIDR : 000000000000000D
>>>> Efficiency Class : 00
>>>> Reserved : 000000
>>>>
>>>> Signed-off-by: Shanker Donthineni <shankerd@codeaurora.org>
>>>> ---
>>>> drivers/irqchip/irq-gic-v3.c | 14 +++++++++-----
>>>> 1 file changed, 9 insertions(+), 5 deletions(-)
>>>>
>>>> diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c
>>>> index b56c3e2..a30fbac 100644
>>>> --- a/drivers/irqchip/irq-gic-v3.c
>>>> +++ b/drivers/irqchip/irq-gic-v3.c
>>>> @@ -1331,6 +1331,10 @@ static int __init gic_of_init(struct device_node *node, struct device_node *pare
>>>> u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2;
>>>> void __iomem *redist_base;
>>>>
>>>> + /* GICC entry which has !ACPI_MADT_ENABLED is not unusable so skip */
>>>> + if (!(gicc->flags & ACPI_MADT_ENABLED))
>>>> + return 0;
>>>> +
>>>> redist_base = ioremap(gicc->gicr_base_address, size);
>>>> if (!redist_base)
>>>> return -ENOMEM;
>>>> @@ -1374,13 +1378,13 @@ static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header,
>>>> (struct acpi_madt_generic_interrupt *)header;
>>>>
>>>> /*
>>>> - * If GICC is enabled and has valid gicr base address, then it means
>>>> - * GICR base is presented via GICC
>>>> + * If GICC is enabled and has not valid gicr base address, then it means
>>>> + * GICR base is not presented via GICC
>>>> */
>>>> - if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
>>>> - return 0;
>>>> + if ((gicc->flags & ACPI_MADT_ENABLED) && (!gicc->gicr_base_address))
>>>> + return -ENODEV;
>>>
>>> This doesn't feel quite right. It would mean that having the ENABLED
>>> flag cleared and potentially no address would make it valid? It looks to
>>> me that the original code is "less wrong".
>>>
>>> What am I missing?
>>>
>>
>> Original definition of the function gic_acpi_match_gicc().
>> {
>> if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address)
>> return 0;
>>
>> return -ENODEV;
>> }
>>
>> Above code triggers the driver probe fail for the two reasons.
>> 1) GICC with ACPI_MADT_ENABLED=0, it's a bug according to ACPI spec.
>> 2) GICC with ACPI_MADT_ENABLED=1 and invalid GICR address, expected.
>>
>>
>> This patch fix the first failed case and keep the second case intact.
>> if ((gicc->flags & ACPI_MADT_ENABLED) && (!gicc->gicr_base_address))
>> return -ENODEV;
>>
>> return 0;
> If (1) is a firmware bug, then why is it handled in the SMP code? You're
> even saying that this is the right thing to do?
>
It's a bug in Linux GICv3 driver not firmware. Firmware is populating MADT
table according to ACPI specification.
> As for (2), you seem to imply that only the address matter. So why isn't
> it just:
>
> if (gicc->gicr_base_address)
> return 0;
>
> ?
ACPI spec says operating shouldn't attempt to use GICC configuration parameters
if the flag ACPI_MADT_ENABLED is cleared. I believe we should check GICR address
only for enabled GICC interfaces.
>
> Thanks,
>
> M.
>
--
Shanker Donthineni
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH] Arm: mm: ftrace: Only set text back to ro after kernel has been marked ro
From: Russell King - ARM Linux @ 2017-12-05 13:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205114709.f6aj6i426keq2cn5@camel2.lan>
On Tue, Dec 05, 2017 at 12:47:09PM +0100, Matthias Reichl wrote:
> On Wed, Aug 23, 2017 at 03:03:51PM -0400, Steven Rostedt wrote:
> > On Wed, 23 Aug 2017 11:48:13 -0700
> > Kees Cook <keescook@chromium.org> wrote:
> >
> > > > diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
> > > > index ad80548..fd75f38 100644
> > > > --- a/arch/arm/mm/init.c
> > > > +++ b/arch/arm/mm/init.c
> > > > @@ -745,19 +745,29 @@ static int __mark_rodata_ro(void *unused)
> > > > return 0;
> > > > }
> > > >
> > > > +static int kernel_set_to_readonly;
> > >
> > > Adding a comment here might be a good idea, something like:
> > >
> > > /* Has system boot-up reached mark_rodata_ro() yet? */
> >
> > I don't mind adding a comment, but the above is rather self explanatory
> > (one can easily see that it is set in mark_rodata_ro() with a simple
> > search).
> >
> > If a comment is to be added, something a bit more descriptive of the
> > functionality of the variable would be appropriate:
> >
> > /*
> > * Ignore modifying kernel text permissions until the kernel core calls
> > * make_rodata_ro() at system start up.
> > */
> >
> > I can resend with the comment, or whoever takes this could add it
> > themselves.
>
> Gentle ping: this patch doesn't seem to have landed in upstream
> trees yet. Is any more work required?
>
> It would be nice to have this fix added. Just tested next-20171205
> on RPi B+, it oopses when the function tracer is enabled during boot.
> next-20171205 plus this patch boots up fine.
When does it oops?
Reading through this code, I'm left wondering why we switch the rodata
section to be writable here - if we're poking at kernel text, then
surely we shouldn't be the read-only data read-write?
Should kernel_set_to_readonly also be a rodata-after-init variable?
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH] [v2] ASoC: atmel-classd: improve Kconfig dependencies
From: Arnd Bergmann @ 2017-12-05 13:10 UTC (permalink / raw)
To: linux-arm-kernel
Commit 061981ff8cc8 ("ASoC: atmel: properly select dma driver state")
changed the way that the dependencies are handled, but then the
Class D amplifier support got merged, which used the old method.
This seems to have triggered a very rare randconfig condition for me
now, leading to a link error:
sound/soc/atmel/atmel_ssc_dai.o: In function `atmel_ssc_set_audio':
atmel_ssc_dai.c:(.text+0x79c): undefined reference to `atmel_pcm_dma_platform_register'
atmel_ssc_dai.c:(.text+0x79c): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `atmel_pcm_dma_platform_register'
sound/soc/atmel/atmel_ssc_dai.o: In function `atmel_ssc_put_audio':
atmel_ssc_dai.c:(.text+0xf24): undefined reference to `atmel_pcm_dma_platform_unregister'
atmel_ssc_dai.c:(.text+0xf24): relocation truncated to fit: R_AARCH64_CALL26 against undefined symbol `atmel_pcm_dma_platform_unregister'
This changes the SND_ATMEL_SOC_DMA option so it gets built whenever
one of the two users (SND_ATMEL_SOC_SSC_DMA and SND_ATMEL_SOC_CLASSD)
is enabled, with the twist that we make it built-in when SND_ATMEL_SOC_SSC
is built-in, even if one of the other two is a module.
I think this captures best what the real dependency in the hardware
is, and it simplifies the logic a bit.
Fixes: e0a25b6d1862 ("ASoC: atmel-classd: add the Audio Class D Amplifier")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
v2: rewrite the change completely, after running into a new regression.
I'm putting it out on the list so we can review the change together,
but I'm still doing more testing at the same time. If I don't reply
by Dec 6, nothing new has come up.
---
sound/soc/atmel/Kconfig | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/sound/soc/atmel/Kconfig b/sound/soc/atmel/Kconfig
index 4a56f3dfba51..af9a9096d50b 100644
--- a/sound/soc/atmel/Kconfig
+++ b/sound/soc/atmel/Kconfig
@@ -20,8 +20,8 @@ config SND_ATMEL_SOC_SSC_PDC
config SND_ATMEL_SOC_DMA
tristate
select SND_SOC_GENERIC_DMAENGINE_PCM
- default m if SND_ATMEL_SOC_SSC_DMA=m && SND_ATMEL_SOC_SSC=m
- default y if SND_ATMEL_SOC_SSC_DMA=y || (SND_ATMEL_SOC_SSC_DMA=m && SND_ATMEL_SOC_SSC=y)
+ default y if SND_ATMEL_SOC_SSC=y && (SND_ATMEL_SOC_SSC_DMA=m || SND_ATMEL_SOC_CLASSD=m)
+ default SND_ATMEL_SOC_CLASSD || SND_ATMEL_SOC_SSC_DMA
config SND_ATMEL_SOC_SSC_DMA
tristate
@@ -64,7 +64,6 @@ config SND_AT91_SOC_SAM9X5_WM8731
config SND_ATMEL_SOC_CLASSD
tristate "Atmel ASoC driver for boards using CLASSD"
depends on ARCH_AT91 || COMPILE_TEST
- select SND_ATMEL_SOC_DMA
select REGMAP_MMIO
help
Say Y if you want to add support for Atmel ASoC driver for boards using
--
2.9.0
^ permalink raw reply related
* [GIT PULL] OMAP2+: clkctrl fixes/enhancements for OMAP SoCs for 4.16 merge
From: Tero Kristo @ 2017-12-05 13:02 UTC (permalink / raw)
To: linux-arm-kernel
Hi Tony,
This pull contains the series posted here [1], it has only been rebased
on top of 4.15-rc1. Can be applied separately from the clkctrl driver
series. The part missing after this is the DTS series, which I will post
later this week (I don't think I have time to post them today, but they
are available also under branch 4.15-rc1-clkctrl-dts in my public repo.)
-Tero
[1] http://www.spinics.net/lists/linux-omap/msg139902.html
===
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
https://github.com/t-kristo/linux-pm.git 4.15-rc1-clkctrl-mach-omap2
for you to fetch changes up to 71d50393ab0186b40860d31468a1b701c97339f6:
ARM: DM816x: hwmod_data: fix clockdomain name for sata hwmod
(2017-12-04 11:35:21 +0200)
----------------------------------------------------------------
Tero Kristo (7):
ARM: OMAP2+: CM: add support for getting phys address for a
clkctrl register
ARM: OMAP4: CMINST: add support for translating clkctrl addresses
ARM: OMAP2+: hwmod: fix clkctrl address translation logic
ARM: OMAP2+: clockdomain: remove the obsolete clkdm_xlate_address API
ARM: AM33xx: CM: add support for getting physical address for a
register
ARM: OMAP2+: hwmod: calculate physical register address on am33xx
ARM: DM816x: hwmod_data: fix clockdomain name for sata hwmod
arch/arm/mach-omap2/clockdomain.c | 8 ----
arch/arm/mach-omap2/clockdomain.h | 2 -
arch/arm/mach-omap2/cm.h | 3 ++
arch/arm/mach-omap2/cm33xx.c | 6 +++
arch/arm/mach-omap2/cm_common.c | 10 ++++
arch/arm/mach-omap2/cminst44xx.c | 10 ++--
arch/arm/mach-omap2/omap_hwmod.c | 73
+++++++++++++++---------------
arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 2 +-
8 files changed, 59 insertions(+), 55 deletions(-)
--
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^ permalink raw reply
* [PATCH] arm64: dts: allwinner: a64: bananapi-m64: Add LED device node
From: Chen-Yu Tsai @ 2017-12-05 13:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205100511.ohxcqlrozxfgq6id@flea.lan>
On Tue, Dec 5, 2017 at 6:05 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Hi,
>
> On Sat, Dec 02, 2017 at 12:27:33AM +0800, Chen-Yu Tsai wrote:
>> The Bananapi-M64 has 3 LEDS in red, green, and blue. These are toggled
>> via GPIO lines, which drive transistors that control current across the
>> LEDS. The red LED is by default on, via an additional pull-up on the
>> control line. We consider this means that it is a power indicator.
>> So we set the "default-on" property for it.
>>
>> The pingroups the GPIO lines belong to require external regulators be
>> enabled to be able to drive the GPIO high. These regulators also have
>> other purposes. However the pin controller does not have bindings for
>> regulators. Here we just set them to always-on.
>
> I guess we should take the opportunity to do just that.
>
> We have been deferring this for quite some time now, this is a perfect
> occasion to do it once and for all :)
True. But right now I don't see an elegant solution. What is the purpose
of having the regulator tied to pinctrl / GPIO? You can't have the pinctrl
driver asking for the regulator at probe time, as it might not be available
or even have a cyclic dependency (because the PMIC is I2C driven, which
needs an I2C controller, which needs the pinctrl). If you defer fetching
the regulator to a later point, you might end up with an inconsistent state.
Again with the I2C driven regulator example, what happens if the regulator
core decides to turn the regulator off before the pinctrl side has a chance
to take a reference and enable it?
Regards
ChenYu
^ permalink raw reply
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