* [PATCH 2/2] arm64: allwinner: a64: bananapi-m64: add usb otg
From: Chen-Yu Tsai @ 2017-12-07 7:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAD6G_RR-L1RH899peZgWdapyrENJC7b9-H0pNPu9+Ji93JnQ=w@mail.gmail.com>
On Thu, Dec 7, 2017 at 2:54 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
> On Thu, Dec 7, 2017 at 11:56 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>> On Thu, Dec 7, 2017 at 2:18 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>>> On Thu, Dec 7, 2017 at 8:54 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>>>> On Thu, Dec 7, 2017 at 1:51 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>>>>> usb otg on bananapi-m64 has configured with USB-ID with PH9
>>>>> and USB-DRVVBUS attached with dcdc1 regulatort.
>>>>
>>>> That is not how you read the schematic...
>>>>
>>>> Intersecting lines that are tied together will have a dot representing
>>>> the connection. The DCDC1 line is a pull-up for the ID pin. This is very
>>>> clear because it has a resistor connected in series.
>>>>
>>>> VBUS for OTG is controlled by the IC displayed to the right in the
>>>> schematic, which is powered from 5V, and controlled by the DRVVBUS
>>>> pin from the PMIC. Please take a look at how the A31/A33/A83T board
>>>> dts files represent this.
>>>
>>> This is where I confused, USB-DRVVBUS is connected to pin 51 of PMIC
>>> if we add 5v regulator how can configure gpio number for this? I saw
>>
>> From the axp20x bindings:
>>
>> - x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is
>> used as an output pin to control an external
>> regulator to drive the OTG VBus, rather then
>> as an input pin which signals whether the
>> board is driving OTG VBus or not.
>> (axp221 / axp223 / axp813 only)
>>
>> Setting this allows you to use the "drivevbus" regulator under the PMIC.
>> As I said, look at how other boards are doing it.
>>
>>> sun8i-a33-olinuxino.dts which is also similar but it has gpio = <&pio
>>> 1 9 GPIO_ACTIVE_HIGH>;
>>
>> I have no idea where you saw this. It does not exist in my tree.
>>
>> Why don't you just trace backwards from the usb0_vbus-supply property
>> under the usbphy node, and see where it all leads.
>
> This what exactly I did, usb0_vbus-supply = <®_drivevbus>; on
This is not what you did in your patch.
> sun8i-a33-olinuxino.dts is using usb0-vbus from
> sunxi-common-regulators.dtsi. reg_usb0_vbus regulator using gpio9
> which I couldn't find it on schematics.
And I'm telling you that in mainline a33-olinuxino.dts it is:
usb0_vbus-supply = <®_drivevbus>;
It has been that way since the initial commit adding the file.
What tree are you looking at exactly? Take a good look at everything,
including your patch, and stop arguing.
ChenYu
^ permalink raw reply
* [PATCH v3 2/3] clk: hisilicon: Add support for Hi3660 stub clocks
From: Stephen Boyd @ 2017-12-07 7:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1510910852-2175-3-git-send-email-xuyiping@hisilicon.com>
On 11/17, Xu YiPing wrote:
> From: Kaihua Zhong <zhongkaihua@huawei.com>
> +
> +static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
> + void *data)
> +{
> + unsigned int idx = clkspec->args[0];
> +
> + if (idx > HI3660_CLK_STUB_NUM) {
This should be >=
> + }
> +
> + return &hi3660_stub_clks[idx].hw;
> +}
> +
> +static int hi3660_stub_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *res;
> + unsigned int i;
> + int ret;
> +
> + /* Use mailbox client without blocking */
> + stub_clk_chan.cl.dev = dev;
> + stub_clk_chan.cl.tx_done = NULL;
> + stub_clk_chan.cl.tx_block = false;
> + stub_clk_chan.cl.knows_txdone = false;
> +
> + /* Allocate mailbox channel */
> + stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
> + if (IS_ERR(stub_clk_chan.mbox))
> + return PTR_ERR(stub_clk_chan.mbox);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + freq_reg = devm_ioremap(dev, res->start, resource_size(res));
> + if (IS_ERR(freq_reg))
Pretty sure this returns NULL on failure, not an error pointer.
> + return -ENOMEM;
> +
> + freq_reg += HI3660_STUB_CLOCK_DATA;
> +
> + for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
> + ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
> + if (ret)
> + return ret;
> + }
> +
> + ret = of_clk_add_hw_provider(pdev->dev.of_node, hi3660_stub_clk_hw_get,
> + hi3660_stub_clks);
This can use devm
> + return ret;
> +}
> +
I fixed it all and merged into clk-next.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v2] clk: stm32-h7: fix copyright
From: Stephen Boyd @ 2017-12-07 7:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171130084108.23083-1-benjamin.gaignard@st.com>
On 11/30, Benjamin Gaignard wrote:
> Uniformize STMicroelectronics copyrights header
> Add SPDX identifier
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> Acked-by: Alexandre TORGUE <alexandre.torgue@st.com>
> CC: Gabriel Fernandez <gabriel.fernandez@st.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 2/2] arm64: allwinner: a64: bananapi-m64: add usb otg
From: Jagan Teki @ 2017-12-07 7:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65OcqHSDyRowK7UKUpav_CbNtRm9DSs+_uLaZcbu6b7fg@mail.gmail.com>
On Thu, Dec 7, 2017 at 12:31 PM, Chen-Yu Tsai <wens@csie.org> wrote:
> On Thu, Dec 7, 2017 at 2:54 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>> On Thu, Dec 7, 2017 at 11:56 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>>> On Thu, Dec 7, 2017 at 2:18 PM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>>>> On Thu, Dec 7, 2017 at 8:54 AM, Chen-Yu Tsai <wens@csie.org> wrote:
>>>>> On Thu, Dec 7, 2017 at 1:51 AM, Jagan Teki <jagannadh.teki@gmail.com> wrote:
>>>>>> usb otg on bananapi-m64 has configured with USB-ID with PH9
>>>>>> and USB-DRVVBUS attached with dcdc1 regulatort.
>>>>>
>>>>> That is not how you read the schematic...
>>>>>
>>>>> Intersecting lines that are tied together will have a dot representing
>>>>> the connection. The DCDC1 line is a pull-up for the ID pin. This is very
>>>>> clear because it has a resistor connected in series.
>>>>>
>>>>> VBUS for OTG is controlled by the IC displayed to the right in the
>>>>> schematic, which is powered from 5V, and controlled by the DRVVBUS
>>>>> pin from the PMIC. Please take a look at how the A31/A33/A83T board
>>>>> dts files represent this.
>>>>
>>>> This is where I confused, USB-DRVVBUS is connected to pin 51 of PMIC
>>>> if we add 5v regulator how can configure gpio number for this? I saw
>>>
>>> From the axp20x bindings:
>>>
>>> - x-powers,drive-vbus-en: boolean, set this when the N_VBUSEN pin is
>>> used as an output pin to control an external
>>> regulator to drive the OTG VBus, rather then
>>> as an input pin which signals whether the
>>> board is driving OTG VBus or not.
>>> (axp221 / axp223 / axp813 only)
>>>
>>> Setting this allows you to use the "drivevbus" regulator under the PMIC.
>>> As I said, look at how other boards are doing it.
>>>
>>>> sun8i-a33-olinuxino.dts which is also similar but it has gpio = <&pio
>>>> 1 9 GPIO_ACTIVE_HIGH>;
>>>
>>> I have no idea where you saw this. It does not exist in my tree.
>>>
>>> Why don't you just trace backwards from the usb0_vbus-supply property
>>> under the usbphy node, and see where it all leads.
>>
>> This what exactly I did, usb0_vbus-supply = <®_drivevbus>; on
>
> This is not what you did in your patch.
>
>> sun8i-a33-olinuxino.dts is using usb0-vbus from
>> sunxi-common-regulators.dtsi. reg_usb0_vbus regulator using gpio9
>> which I couldn't find it on schematics.
>
> And I'm telling you that in mainline a33-olinuxino.dts it is:
>
> usb0_vbus-supply = <®_drivevbus>;
>
> It has been that way since the initial commit adding the file.
> What tree are you looking at exactly? Take a good look at everything,
> including your patch, and stop arguing.
Sorry, you miss understand. I've seen a33-olinuxino and bananapi-m64
has similar connection in otg. Just trying to compare both and
understand what I did different in my patch. Anyway thanks for your
time I will send next version it will be worth discussing the same
there.
thanks!
--
Jagan Teki
Free Software Engineer | www.openedev.com
U-Boot, Linux | Upstream Maintainer
Hyderabad, India.
^ permalink raw reply
* [PATCH V3] spi: sun4i: disable clocks in the remove function
From: Takuo Koguchi @ 2017-12-07 7:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206152005.yfbyylu6tbe5gnnv@flea.lan>
mclk and hclk need to be disabled. Since pm_runtime_disable does
not disable the clocks, use pm_runtime_force_suspend instead.
Found by Linux Driver Verification project (linuxtesting.org).
Signed-off-by: Takuo Koguchi <takuo.koguchi.sw@hitachi.com>
---
V3: remove redundant pm_runtime_disable call.
Compile test only, no runtime test done.
drivers/spi/spi-sun4i.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-sun4i.c b/drivers/spi/spi-sun4i.c
index c5cd635..4141003 100644
--- a/drivers/spi/spi-sun4i.c
+++ b/drivers/spi/spi-sun4i.c
@@ -525,7 +525,7 @@ static int sun4i_spi_probe(struct platform_device *pdev)
static int sun4i_spi_remove(struct platform_device *pdev)
{
- pm_runtime_disable(&pdev->dev);
+ pm_runtime_force_suspend(&pdev->dev);
return 0;
}
--
2.7.4
^ permalink raw reply related
* [PATCH v2] arm64: dts: ls1088a: Add USB support
From: Yinbo Zhu @ 2017-12-07 7:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <VI1PR04MB1262DD3C6A18257DEE2E907DE9200@VI1PR04MB1262.eurprd04.prod.outlook.com>
Hi shawn guo,
If my patch has no other issue,
Can you help me push it to upstream.
Thanks.
BRs.
-----Original Message-----
From: Yinbo Zhu
Sent: Wednesday, November 22, 2017 9:32 AM
To: 'Shawn Guo' <shawnguo@kernel.org>
Cc: 'Rob Herring' <robh+dt@kernel.org>; 'Mark Rutland' <mark.rutland@arm.com>; 'Catalin Marinas )' <catalin.marinas@arm.com>; 'Will Deacon )' <will.deacon@arm.com>; Harninder Rai <harninder.rai@nxp.com>; 'Raghav Dogra' <raghav.dogra@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>; Andy Tang <andy.tang@nxp.com>; 'open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS' <devicetree@vger.kernel.org>; 'linux-arm-kernel at lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'open list' <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
Hi
-----Original Message-----
From: Yinbo Zhu
Sent: Tuesday, November 14, 2017 4:00 PM
To: 'Shawn Guo' <shawnguo@kernel.org>
Cc: 'Rob Herring' <robh+dt@kernel.org>; 'Mark Rutland' <mark.rutland@arm.com>; 'Catalin Marinas )' <catalin.marinas@arm.com>; 'Will Deacon )' <will.deacon@arm.com>; Harninder Rai <harninder.rai@nxp.com>; 'Raghav Dogra' <raghav.dogra@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>; Andy Tang <andy.tang@nxp.com>; 'open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS' <devicetree@vger.kernel.org>; 'linux-arm-kernel at lists.infradead.org' <linux-arm-kernel@lists.infradead.org>; 'open list' <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
-----Original Message-----
From: Yinbo Zhu
Sent: Tuesday, October 24, 2017 5:15 PM
To: Shawn Guo <shawnguo@kernel.org>
Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Catalin Marinas ) <catalin.marinas@arm.com>; Will Deacon ) <will.deacon@arm.com>; Harninder Rai <harninder.rai@nxp.com>; Raghav Dogra <raghav.dogra@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>; Andy Tang <andy.tang@nxp.com>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-arm-kernel at lists.infradead.org; open list <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH v2] arm64: dts: ls1088a: Add USB support
-----Original Message-----
From: Shawn Guo [mailto:shawnguo at kernel.org]
Sent: Friday, September 22, 2017 2:55 PM
To: Yinbo Zhu <yinbo.zhu@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>; Catalin Marinas ) <catalin.marinas@arm.com>; Will Deacon ) <will.deacon@arm.com>; Harninder Rai <harninder.rai@nxp.com>; Raghav Dogra <raghav.dogra@nxp.com>; Ashish Kumar <ashish.kumar@nxp.com>; Andy Tang <andy.tang@nxp.com>; open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS <devicetree@vger.kernel.org>; linux-arm-kernel at lists.infradead.org; open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] arm64: dts: ls1088a: Add USB support
On Wed, Sep 13, 2017 at 05:10:09PM +0800, yinbo.zhu at nxp.com wrote:
> From: "yinbo.zhu" <yinbo.zhu@nxp.com>
>
> Fix the issue that usb is not detected on ls1088ardb
>It's not really about fixing issue but adding support.
The patch had been tested on upstream 4.14 code, it can fix the issue.
>
> Signed-off-by: yinbo.zhu <yinbo.zhu@nxp.com>
> Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
> ---
>You should better have a version history here to tell what's changed between version.
>I will add a version history on next v3 patch
Hi,
I had modified the code as v4 version,
https://patchwork.kernel.org/patch/10027393/
please check.
Thanks,
BRs
> arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts | 8 ++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 20 ++++++++++++++++++++
> 2 files changed, 28 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> index 213abb72de93..6c3c3bc4b681 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts
> @@ -118,6 +118,14 @@
> status = "okay";
> };
>
> +&usb0 {
> + status = "okay";
> +};
> +
> +&usb1 {
> + status = "okay";
> +};
> +
> &esdhc {
>Please sort these labeled nodes alphabetically.
>Shawn
> status = "okay";
> };
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index c144d06a6e33..c23fede8cf5d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -359,6 +359,26 @@
> status = "disabled";
> };
>
> + usb0: usb3 at 3100000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3100000 0x0 0x10000>;
> + interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + status = "disabled";
> + };
> +
> + usb1: usb3 at 3110000 {
> + compatible = "snps,dwc3";
> + reg = <0x0 0x3110000 0x0 0x10000>;
> + interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "host";
> + snps,quirk-frame-length-adjustment = <0x20>;
> + snps,dis_rxdet_inp3_quirk;
> + status = "disabled";
> + };
> +
> sata: sata at 3200000 {
> compatible = "fsl,ls1088a-ahci";
> reg = <0x0 0x3200000 0x0 0x10000>,
> --
> 2.14.1
>
^ permalink raw reply
* [PATCH v3] ARM: da850: Fix LEGO EV3 battery voltage gpio
From: Sekhar Nori @ 2017-12-07 7:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512338693-16781-1-git-send-email-david@lechnology.com>
On Monday 04 December 2017 03:34 AM, David Lechner wrote:
> This fixes the battery voltage monitoring gpio-hog settings.
>
> When the gpio is low, it turns off the battery voltage to the ADC chip.
> However, this needs to be on all of the time so that we can monitor
> battery voltage.
>
> Also, there was a typo that prevented pinmuxing from working correctly.
>
> Signed-off-by: David Lechner <david@lechnology.com>
Applied to fixes with subject line changed to:
ARM: dts: da850-lego-ev3: Fix battery voltage gpio
Please follow this style for future patches.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 1/1] codestyle issue fixed drivers/staging/vc04_services
From: Mikhail Shvetsov @ 2017-12-07 7:47 UTC (permalink / raw)
To: linux-arm-kernel
From: Mike <lameli67@gmail.com>
Signed-off-by: Mike <lameli67@gmail.com>
---
.../interface/vchiq_arm/vchiq_kern_lib.c | 64 ++++++++++++----------
1 file changed, 35 insertions(+), 29 deletions(-)
diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
index 34f746db19cd..d21bb154f78c 100644
--- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
+++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
@@ -65,10 +65,10 @@ vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
unsigned int size, VCHIQ_BULK_DIR_T dir);
/****************************************************************************
-*
-* vchiq_initialise
-*
-***************************************************************************/
+ *
+ * vchiq_initialise
+ *
+ ***************************************************************************/
#define VCHIQ_INIT_RETRIES 10
VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
{
@@ -80,7 +80,9 @@ VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
vchiq_log_trace(vchiq_core_log_level, "%s called", __func__);
/* VideoCore may not be ready due to boot up timing.
- It may never be ready if kernel and firmware are mismatched, so don't block forever. */
+ * It may never be ready if kernel and firmware are mismatched, so don't
+ * block forever.
+ */
for (i = 0; i < VCHIQ_INIT_RETRIES; i++) {
state = vchiq_get_state();
if (state)
@@ -93,7 +95,8 @@ VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
goto failed;
} else if (i > 0) {
vchiq_log_warning(vchiq_core_log_level,
- "%s: videocore initialized after %d retries\n", __func__, i);
+ "%s: videocore initialized after %d retries\n",
+ __func__, i);
}
instance = kzalloc(sizeof(*instance), GFP_KERNEL);
@@ -121,10 +124,10 @@ VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
EXPORT_SYMBOL(vchiq_initialise);
/****************************************************************************
-*
-* vchiq_shutdown
-*
-***************************************************************************/
+ *
+ * vchiq_shutdown
+ *
+ ***************************************************************************/
VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance)
{
@@ -169,10 +172,10 @@ VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance)
EXPORT_SYMBOL(vchiq_shutdown);
/****************************************************************************
-*
-* vchiq_is_connected
-*
-***************************************************************************/
+ *
+ * vchiq_is_connected
+ *
+ ***************************************************************************/
static int vchiq_is_connected(VCHIQ_INSTANCE_T instance)
{
@@ -180,10 +183,10 @@ static int vchiq_is_connected(VCHIQ_INSTANCE_T instance)
}
/****************************************************************************
-*
-* vchiq_connect
-*
-***************************************************************************/
+ *
+ * vchiq_connect
+ *
+ ***************************************************************************/
VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance)
{
@@ -215,10 +218,10 @@ VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance)
EXPORT_SYMBOL(vchiq_connect);
/****************************************************************************
-*
-* vchiq_add_service
-*
-***************************************************************************/
+ *
+ * vchiq_add_service
+ *
+ ***************************************************************************/
VCHIQ_STATUS_T vchiq_add_service(
VCHIQ_INSTANCE_T instance,
@@ -260,10 +263,10 @@ VCHIQ_STATUS_T vchiq_add_service(
EXPORT_SYMBOL(vchiq_add_service);
/****************************************************************************
-*
-* vchiq_open_service
-*
-***************************************************************************/
+ *
+ * vchiq_open_service
+ *
+ ***************************************************************************/
VCHIQ_STATUS_T vchiq_open_service(
VCHIQ_INSTANCE_T instance,
@@ -414,8 +417,9 @@ vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
if ((bulk->data != data) ||
(bulk->size != size)) {
/* This is not a retry of the previous one.
- ** Cancel the signal when the transfer
- ** completes. */
+ * Cancel the signal when the transfer
+ * completes.
+ */
spin_lock(&bulk_waiter_spinlock);
bulk->userdata = NULL;
spin_unlock(&bulk_waiter_spinlock);
@@ -441,7 +445,9 @@ vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
if (bulk) {
/* Cancel the signal when the transfer
- ** completes. */
+ *
+ * completes.
+ */
spin_lock(&bulk_waiter_spinlock);
bulk->userdata = NULL;
spin_unlock(&bulk_waiter_spinlock);
--
2.13.6 (Apple Git-96)
^ permalink raw reply related
* [RFC v3 PATCH 0/2] Introduce Security Version to EFI Stub
From: Gary Lin @ 2017-12-07 7:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207060927.i4b4h6ahas3iiyrc@gmail.com>
On Thu, Dec 07, 2017 at 07:09:27AM +0100, Ingo Molnar wrote:
>
> * Gary Lin <glin@suse.com> wrote:
>
> > On Wed, Dec 06, 2017 at 07:37:34PM +0100, Ingo Molnar wrote:
> > >
> > > * Gary Lin <glin@suse.com> wrote:
> > >
> > > > On Tue, Dec 05, 2017 at 04:14:26PM -0500, Josh Boyer wrote:
> > > > > On Tue, Dec 5, 2017 at 5:01 AM, Gary Lin <glin@suse.com> wrote:
> > > > > > The series of patches introduce Security Version to EFI stub.
> > > > > >
> > > > > > Security Version is a monotonically increasing number and designed to
> > > > > > prevent the user from loading an insecure kernel accidentally. The
> > > > > > bootloader maintains a list of security versions corresponding to
> > > > > > different distributions. After fixing a critical vulnerability, the
> > > > > > distribution kernel maintainer bumps the "version", and the bootloader
> > > > > > updates the list automatically. When the user tries to load a kernel
> > > > > > with a lower security version, the bootloader shows a warning prompt
> > > > > > to notify the user the potential risk.
> > > > >
> > > > > If a distribution releases a kernel with a higher security version and
> > > > > that it automatically updated on boot, what happens if that kernel
> > > > > contains a different bug that causes it to fail to boot or break
> > > > > critical functionality? At that point, the user's machine would be in
> > > > > a state where the higher security version is enforced but the only
> > > > > kernel that provides that is broken. Wouldn't that make a bad
> > > > > situation even worse by now requiring manual acceptance of the older
> > > > > SV kernel boot physically at the machine?
> > > > >
> > > > > I feel like I'm missing a detail here or something.
> > > > >
> > > > If the new kernel fails to boot, then the user has to choose the kernel
> > > > manually anyway, and there will be an option in the warning prompt to
> > > > lower SV.
> > >
> > > And what if the firmware does not support a lowering of the SV?
> > >
> > The SV list is manipulated by the bootloader, and the firmware only
> > provides the interface to the storage, i.e. non-volatile flash.
>
> What about systems where the bootloader is part of the system and users only have
> the ability to provide kernel images, but no ability to change the boot loader?
>
It depends on how the bootloader works. If the system uses my
implementation of shim loader, it surely has the ability to lower SV,
but it requires physical access on purpose.
The Security Version check is a warning rather than a hard block like the
signature check. The current plan is to add an extra check in the shim
verify protocol, so that we can check SV right after the signature check.
I'm thinking about adding a UEFI variable to control the timeout of the
warning prompt, e.g. 30 for 30 seconds and 0 for waiting indefinitely,
so that the warning prompt won't block the system boot unless the system
administrator wants so.
As for other bootloaders, SV is just a few extra bytes in the kernel
image and means nothing to them.
Cheers,
Gary Lin
^ permalink raw reply
* [PATCH v3 2/3] clk: hisilicon: Add support for Hi3660 stub clocks
From: Leo Yan @ 2017-12-07 8:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207070550.GY4283@codeaurora.org>
On Wed, Dec 06, 2017 at 11:05:50PM -0800, Stephen Boyd wrote:
> On 11/17, Xu YiPing wrote:
> > From: Kaihua Zhong <zhongkaihua@huawei.com>
> > +
> > +static struct clk_hw *hi3660_stub_clk_hw_get(struct of_phandle_args *clkspec,
> > + void *data)
> > +{
> > + unsigned int idx = clkspec->args[0];
> > +
> > + if (idx > HI3660_CLK_STUB_NUM) {
>
> This should be >=
>
> > + }
> > +
> > + return &hi3660_stub_clks[idx].hw;
> > +}
> > +
> > +static int hi3660_stub_clk_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct resource *res;
> > + unsigned int i;
> > + int ret;
> > +
> > + /* Use mailbox client without blocking */
> > + stub_clk_chan.cl.dev = dev;
> > + stub_clk_chan.cl.tx_done = NULL;
> > + stub_clk_chan.cl.tx_block = false;
> > + stub_clk_chan.cl.knows_txdone = false;
> > +
> > + /* Allocate mailbox channel */
> > + stub_clk_chan.mbox = mbox_request_channel(&stub_clk_chan.cl, 0);
> > + if (IS_ERR(stub_clk_chan.mbox))
> > + return PTR_ERR(stub_clk_chan.mbox);
> > +
> > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > + freq_reg = devm_ioremap(dev, res->start, resource_size(res));
> > + if (IS_ERR(freq_reg))
>
> Pretty sure this returns NULL on failure, not an error pointer.
>
> > + return -ENOMEM;
> > +
> > + freq_reg += HI3660_STUB_CLOCK_DATA;
> > +
> > + for (i = 0; i < HI3660_CLK_STUB_NUM; i++) {
> > + ret = devm_clk_hw_register(&pdev->dev, &hi3660_stub_clks[i].hw);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + ret = of_clk_add_hw_provider(pdev->dev.of_node, hi3660_stub_clk_hw_get,
> > + hi3660_stub_clks);
>
> This can use devm
>
> > + return ret;
> > +}
> > +
>
> I fixed it all and merged into clk-next.
Ah, very appreciate your help, Stephen.
Thanks,
Leo Yan
^ permalink raw reply
* [PATCH V6 01/12] drivers: move clock common macros out from vendor directories
From: Chunyan Zhang @ 2017-12-07 8:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207064723.GV4283@codeaurora.org>
On 7 December 2017 at 14:47, Stephen Boyd <sboyd@codeaurora.org> wrote:
> On 11/27, Chunyan Zhang wrote:
>> These macros are used by more than one SoC vendor platforms, avoid to
>> have many copies of these code, this patch moves them to the common
>> clock directory which every clock drivers can access to.
>>
>> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
>> ---
>> drivers/clk/clk_common.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 60 insertions(+)
>> create mode 100644 drivers/clk/clk_common.h
>>
>> diff --git a/drivers/clk/clk_common.h b/drivers/clk/clk_common.h
>> new file mode 100644
>> index 0000000..21e93d2
>> --- /dev/null
>> +++ b/drivers/clk/clk_common.h
>> @@ -0,0 +1,60 @@
>> +/*
>> + * drivers/clk/clk_common.h
>
> We don't need this in the file too. Please remove this line.
>
>> + *
>> + * SPDX-License-Identifier: GPL-2.0
>> + */
>> +
>> +#ifndef _CLK_COMMON_H_
>> +#define _CLK_COMMON_H_
>> +
>> +#include <linux/clk-provider.h>
>
> Maybe these macros should just go into clk-provider.h?
Ok. And I will also remove the same macros from sunxi-ng/ccu_common.h
and zte/clk.h.
>
>> +
>> +#define CLK_HW_INIT(_name, _parent, _ops, _flags) \
>> + (&(struct clk_init_data) { \
>> + .flags = _flags, \
>> + .name = _name, \
>> + .parent_names = (const char *[]) { _parent }, \
>> + .num_parents = 1, \
>> + .ops = _ops, \
>> + })
>
> Hopefully we don't extend the init structure anymore to have
> something else. I guess we'll do something if that happens.
>
>> +
>> +#define CLK_HW_INIT_PARENTS(_name, _parents, _ops, _flags) \
>> + (&(struct clk_init_data) { \
>> + .flags = _flags, \
>> + .name = _name, \
>> + .parent_names = _parents, \
>> + .num_parents = ARRAY_SIZE(_parents), \
>> + .ops = _ops, \
>> + })
>> +
>> +#define CLK_HW_INIT_NO_PARENT(_name, _ops, _flags) \
>> + (&(struct clk_init_data) { \
>> + .flags = _flags, \
>> + .name = _name, \
>> + .parent_names = NULL, \
>> + .num_parents = 0, \
>> + .ops = _ops, \
>> + })
>> +
>> +#define CLK_FIXED_FACTOR(_struct, _name, _parent, \
>> + _div, _mult, _flags) \
>> + struct clk_fixed_factor _struct = { \
>> + .div = _div, \
>> + .mult = _mult, \
>> + .hw.init = CLK_HW_INIT(_name, \
>> + _parent, \
>> + &clk_fixed_factor_ops, \
>> + _flags), \
>> + }
>> +
>> +#define CLK_FIXED_RATE(_struct, _name, _flags, \
>> + _fixed_rate, _fixed_accuracy) \
>> + struct clk_fixed_rate _struct = { \
>> + .fixed_rate = _fixed_rate, \
>> + .fixed_accuracy = _fixed_accuracy, \
>> + .hw.init = CLK_HW_INIT_NO_PARENT(_name, \
>> + &clk_fixed_rate_ops, \
>> + _flags), \
>> + }
>
> Maybe don't add this one? Usually fixed rate clks come from DT.
Ok, will also move the fixed rate clks from our driver to DT.
Thanks,
Chunyan
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
> a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 1/1] codestyle issue fixed drivers/staging/vc04_services
From: Stefan Wahren @ 2017-12-07 8:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <40d794a2bd0dd9dbb3add85c79b9b314ccbb480a.1512631936.git.lameli67@gmail.com>
Hello Mikhail,
Am 07.12.2017 um 08:47 schrieb Mikhail Shvetsov:
> From: Mike <lameli67@gmail.com>
please provide your full name and a changelog. Also the subject should
start with something like "staging: vchiq_arm:".
>
> Signed-off-by: Mike <lameli67@gmail.com>
> ---
> .../interface/vchiq_arm/vchiq_kern_lib.c | 64 ++++++++++++----------
> 1 file changed, 35 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
> index 34f746db19cd..d21bb154f78c 100644
> --- a/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
> +++ b/drivers/staging/vc04_services/interface/vchiq_arm/vchiq_kern_lib.c
> @@ -65,10 +65,10 @@ vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
> unsigned int size, VCHIQ_BULK_DIR_T dir);
>
> /****************************************************************************
> -*
> -* vchiq_initialise
> -*
> -***************************************************************************/
> + *
> + * vchiq_initialise
> + *
> + ***************************************************************************/
Instead of fixing the comment style, i prefer to drop this kind of
useless comments in a separate patch.
> #define VCHIQ_INIT_RETRIES 10
> VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
> {
> @@ -80,7 +80,9 @@ VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
> vchiq_log_trace(vchiq_core_log_level, "%s called", __func__);
>
> /* VideoCore may not be ready due to boot up timing.
> - It may never be ready if kernel and firmware are mismatched, so don't block forever. */
> + * It may never be ready if kernel and firmware are mismatched, so don't
> + * block forever.
> + */
> for (i = 0; i < VCHIQ_INIT_RETRIES; i++) {
> state = vchiq_get_state();
> if (state)
> @@ -93,7 +95,8 @@ VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
> goto failed;
> } else if (i > 0) {
> vchiq_log_warning(vchiq_core_log_level,
> - "%s: videocore initialized after %d retries\n", __func__, i);
> + "%s: videocore initialized after %d retries\n",
> + __func__, i);
This isn't a comment, so it should be a separate patch.
> }
>
> instance = kzalloc(sizeof(*instance), GFP_KERNEL);
> @@ -121,10 +124,10 @@ VCHIQ_STATUS_T vchiq_initialise(VCHIQ_INSTANCE_T *instance_out)
> EXPORT_SYMBOL(vchiq_initialise);
>
> /****************************************************************************
> -*
> -* vchiq_shutdown
> -*
> -***************************************************************************/
> + *
> + * vchiq_shutdown
> + *
> + ***************************************************************************/
>
> VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance)
> {
> @@ -169,10 +172,10 @@ VCHIQ_STATUS_T vchiq_shutdown(VCHIQ_INSTANCE_T instance)
> EXPORT_SYMBOL(vchiq_shutdown);
>
> /****************************************************************************
> -*
> -* vchiq_is_connected
> -*
> -***************************************************************************/
> + *
> + * vchiq_is_connected
> + *
> + ***************************************************************************/
>
> static int vchiq_is_connected(VCHIQ_INSTANCE_T instance)
> {
> @@ -180,10 +183,10 @@ static int vchiq_is_connected(VCHIQ_INSTANCE_T instance)
> }
>
> /****************************************************************************
> -*
> -* vchiq_connect
> -*
> -***************************************************************************/
> + *
> + * vchiq_connect
> + *
> + ***************************************************************************/
>
> VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance)
> {
> @@ -215,10 +218,10 @@ VCHIQ_STATUS_T vchiq_connect(VCHIQ_INSTANCE_T instance)
> EXPORT_SYMBOL(vchiq_connect);
>
> /****************************************************************************
> -*
> -* vchiq_add_service
> -*
> -***************************************************************************/
> + *
> + * vchiq_add_service
> + *
> + ***************************************************************************/
>
> VCHIQ_STATUS_T vchiq_add_service(
> VCHIQ_INSTANCE_T instance,
> @@ -260,10 +263,10 @@ VCHIQ_STATUS_T vchiq_add_service(
> EXPORT_SYMBOL(vchiq_add_service);
>
> /****************************************************************************
> -*
> -* vchiq_open_service
> -*
> -***************************************************************************/
> + *
> + * vchiq_open_service
> + *
> + ***************************************************************************/
>
> VCHIQ_STATUS_T vchiq_open_service(
> VCHIQ_INSTANCE_T instance,
> @@ -414,8 +417,9 @@ vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
> if ((bulk->data != data) ||
> (bulk->size != size)) {
> /* This is not a retry of the previous one.
> - ** Cancel the signal when the transfer
> - ** completes. */
> + * Cancel the signal when the transfer
> + * completes.
> + */
> spin_lock(&bulk_waiter_spinlock);
> bulk->userdata = NULL;
> spin_unlock(&bulk_waiter_spinlock);
> @@ -441,7 +445,9 @@ vchiq_blocking_bulk_transfer(VCHIQ_SERVICE_HANDLE_T handle, void *data,
>
> if (bulk) {
> /* Cancel the signal when the transfer
> - ** completes. */
> + *
Please avoid this empty line.
Thanks
> + * completes.
> + */
> spin_lock(&bulk_waiter_spinlock);
> bulk->userdata = NULL;
> spin_unlock(&bulk_waiter_spinlock);
^ permalink raw reply
* [RFC v3 PATCH 0/2] Introduce Security Version to EFI Stub
From: Ingo Molnar @ 2017-12-07 8:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207075203.gcxprq7ctv637fm7@GaryWorkstation>
* Gary Lin <glin@suse.com> wrote:
> On Thu, Dec 07, 2017 at 07:09:27AM +0100, Ingo Molnar wrote:
> >
> > * Gary Lin <glin@suse.com> wrote:
> >
> > > On Wed, Dec 06, 2017 at 07:37:34PM +0100, Ingo Molnar wrote:
> > > >
> > > > * Gary Lin <glin@suse.com> wrote:
> > > >
> > > > > On Tue, Dec 05, 2017 at 04:14:26PM -0500, Josh Boyer wrote:
> > > > > > On Tue, Dec 5, 2017 at 5:01 AM, Gary Lin <glin@suse.com> wrote:
> > > > > > > The series of patches introduce Security Version to EFI stub.
> > > > > > >
> > > > > > > Security Version is a monotonically increasing number and designed to
> > > > > > > prevent the user from loading an insecure kernel accidentally. The
> > > > > > > bootloader maintains a list of security versions corresponding to
> > > > > > > different distributions. After fixing a critical vulnerability, the
> > > > > > > distribution kernel maintainer bumps the "version", and the bootloader
> > > > > > > updates the list automatically. When the user tries to load a kernel
> > > > > > > with a lower security version, the bootloader shows a warning prompt
> > > > > > > to notify the user the potential risk.
> > > > > >
> > > > > > If a distribution releases a kernel with a higher security version and
> > > > > > that it automatically updated on boot, what happens if that kernel
> > > > > > contains a different bug that causes it to fail to boot or break
> > > > > > critical functionality? At that point, the user's machine would be in
> > > > > > a state where the higher security version is enforced but the only
> > > > > > kernel that provides that is broken. Wouldn't that make a bad
> > > > > > situation even worse by now requiring manual acceptance of the older
> > > > > > SV kernel boot physically at the machine?
> > > > > >
> > > > > > I feel like I'm missing a detail here or something.
> > > > > >
> > > > > If the new kernel fails to boot, then the user has to choose the kernel
> > > > > manually anyway, and there will be an option in the warning prompt to
> > > > > lower SV.
> > > >
> > > > And what if the firmware does not support a lowering of the SV?
> > > >
> > > The SV list is manipulated by the bootloader, and the firmware only
> > > provides the interface to the storage, i.e. non-volatile flash.
> >
> > What about systems where the bootloader is part of the system and users only have
> > the ability to provide kernel images, but no ability to change the boot loader?
>
> It depends on how the bootloader works. If the system uses my
> implementation of shim loader, it surely has the ability to lower SV,
> but it requires physical access on purpose.
And that's my problem: if in practice the bootloader is 'part of the system', is
signed and is updated like the firmware, then putting a "Security Version" into
the kernel image and architecting a boot protocol for a monotonic method for the
bootloader to restrict the loading of kernel images is an obviously bad idea.
Thanks,
Ingo
^ permalink raw reply
* [RESEND PATCH V2] ARM: dts: introduce the sama5d2 ptc ek board
From: Ludovic Desroches @ 2017-12-07 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206065844.27689-1-ludovic.desroches@microchip.com>
Add the official SAMA5D2 Peripheral Touch Controller Evaluation
Kit board.
Signed-off-by: Ludovic Desroches <ludovic.desroches@microchip.com>
---
Resend: Put SPDX-License-Identifier at the beginning of the file.
Changes:
- v2:
- remove memory node
- use SPDX-License-Identifier
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 401 ++++++++++++++++++++++++++++++
2 files changed, 402 insertions(+)
create mode 100644 arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 043d7c720d0c..ed60582eb1da 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -48,6 +48,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \
dtb-$(CONFIG_SOC_SAM_V7) += \
at91-kizbox2.dtb \
at91-sama5d27_som1_ek.dtb \
+ at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_xplained.dtb \
at91-tse850-3.dtb \
diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
new file mode 100644
index 000000000000..186cb03e2672
--- /dev/null
+++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
@@ -0,0 +1,401 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR X11)
+/*
+ * at91-sama5d2_ptc_ek.dts - Device Tree file for SAMA5D2 PTC EK board
+ *
+ * Copyright (C) 2017 Microchip/Atmel,
+ * 2017 Wenyou Yang <wenyou.yang@microchip.com>
+ * 2017 Ludovic Desroches <ludovic.desroches@microchip.com>
+ */
+/dts-v1/;
+#include "sama5d2.dtsi"
+#include "sama5d2-pinfunc.h"
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Atmel SAMA5D2 PTC EK";
+ compatible = "atmel,sama5d2-ptc_ek", "atmel,sama5d2", "atmel,sama5";
+
+ aliases {
+ serial0 = &uart0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ clocks {
+ slow_xtal {
+ clock-frequency = <32768>;
+ };
+
+ main_xtal {
+ clock-frequency = <24000000>;
+ };
+ };
+
+ ahb {
+ usb0: gadget at 300000 {
+ atmel,vbus-gpio = <&pioA PIN_PA27 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usba_vbus>;
+ status = "okay";
+ };
+
+ usb1: ohci at 400000 {
+ num-ports = <3>;
+ atmel,vbus-gpio = <0
+ &pioA PIN_PB12 GPIO_ACTIVE_HIGH
+ 0
+ >;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb_default>;
+ status = "okay";
+ };
+
+ usb2: ehci at 500000 {
+ status = "okay";
+ };
+
+ ebi: ebi at 10000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_nand_default>;
+ status = "okay"; /* conflicts with sdmmc1 and qspi0 */
+
+ nand_controller: nand-controller {
+ status = "okay";
+
+ nand at 3 {
+ reg = <0x3 0x0 0x2>;
+ atmel,rb = <0>;
+ nand-bus-width = <8>;
+ nand-ecc-mode = "hw";
+ nand-on-flash-bbt;
+ label = "atmel_nand";
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ at91bootstrap at 0 {
+ label = "bootstrap";
+ reg = <0x0 0x40000>;
+ };
+
+ bootloader at 40000 {
+ label = "bootloader";
+ reg = <0x40000 0xc0000>;
+ };
+
+ bootloaderenv at 0x100000 {
+ label = "bootloader env";
+ reg = <0x100000 0x40000>;
+ };
+
+ bootloaderenvred at 0x140000 {
+ label = "bootloader env redundant";
+ reg = <0x140000 0x40000>;
+ };
+
+ dtb at 180000 {
+ label = "device tree";
+ reg = <0x180000 0x80000>;
+ };
+
+ kernel at 200000 {
+ label = "kernel";
+ reg = <0x200000 0x600000>;
+ };
+
+ rootfs at 800000 {
+ label = "rootfs";
+ reg = <0x800000 0x1f800000>;
+ };
+ };
+ };
+ };
+ };
+
+ sdmmc0: sdio-host at a0000000 {
+ bus-width = <8>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sdmmc0_default>;
+ non-removable;
+ mmc-ddr-1_8v;
+ status = "okay";
+ };
+
+ apb {
+ spi0: spi at f8000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi0_default>;
+ status = "okay";
+ };
+
+ macb0: ethernet at f8008000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_macb0_default &pinctrl_macb0_phy_irq>;
+ phy-mode = "rmii";
+ status = "okay";
+
+ ethernet-phy at 1 {
+ reg = <0x1>;
+ interrupt-parent = <&pioA>;
+ interrupts = <56 IRQ_TYPE_LEVEL_LOW>;
+ };
+ };
+
+ uart0: serial at f801c000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+
+ uart2: serial at f8024000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_default>;
+ atmel,use-dma-rx;
+ atmel,use-dma-tx;
+ status = "okay";
+ };
+
+ i2c0: i2c at f8028000 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+ status = "okay";
+ };
+
+ flx0: flexcom at f8034000 {
+ atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;
+ status = "okay";
+
+ i2c2: i2c at 600 {
+ compatible = "atmel,sama5d2-i2c";
+ reg = <0x600 0x200>;
+ interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
+ dmas = <0>, <0>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&flx0_clk>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flx0_default>;
+ atmel,fifo-size = <16>;
+ status = "okay";
+ };
+ };
+
+ shdwc at f8048010 {
+ atmel,shdwc-debouncer = <976>;
+
+ input at 0 {
+ reg = <0>;
+ atmel,wakeup-type = "low";
+ };
+ };
+
+ watchdog at f8048040 {
+ status = "okay";
+ };
+
+ spi1: spi at fc000000 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_spi1_default>;
+ status = "okay";
+ };
+
+ i2c1: i2c at fc028000 {
+ dmas = <0>, <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+ status = "okay";
+
+ at24 at 50 {
+ compatible = "24c02";
+ reg = <0x50>;
+ pagesize = <8>;
+ };
+ };
+
+ pinctrl at fc038000 {
+ pinctrl_flx0_default: flx0_default {
+ pinmux = <PIN_PB28__FLEXCOM0_IO0>,
+ <PIN_PB29__FLEXCOM0_IO1>;
+ bias-disable;
+ };
+
+ pinctrl_i2c0_default: i2c0_default {
+ pinmux = <PIN_PD21__TWD0>,
+ <PIN_PD22__TWCK0>;
+ bias-disable;
+ };
+
+ pinctrl_i2c1_default: i2c1_default {
+ pinmux = <PIN_PC6__TWD1>,
+ <PIN_PC7__TWCK1>;
+ bias-disable;
+ };
+
+ pinctrl_key_gpio_default: key_gpio_default {
+ pinmux = <PIN_PA10__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_led_gpio_default: led_gpio_default {
+ pinmux = <PIN_PB6__GPIO>,
+ <PIN_PB8__GPIO>,
+ <PIN_PB10__GPIO>;
+ bias-pull-up;
+ };
+
+ pinctrl_macb0_default: macb0_default {
+ pinmux = <PIN_PB14__GTXCK>,
+ <PIN_PB15__GTXEN>,
+ <PIN_PB16__GRXDV>,
+ <PIN_PB17__GRXER>,
+ <PIN_PB18__GRX0>,
+ <PIN_PB19__GRX1>,
+ <PIN_PB20__GTX0>,
+ <PIN_PB21__GTX1>,
+ <PIN_PB22__GMDC>,
+ <PIN_PB23__GMDIO>;
+ bias-disable;
+ };
+
+ pinctrl_macb0_phy_irq: macb0_phy_irq {
+ pinmux = <PIN_PB24__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_nand_default: nand_default {
+ re_we_data {
+ pinmux = <PIN_PA22__D0>,
+ <PIN_PA23__D1>,
+ <PIN_PA24__D2>,
+ <PIN_PA25__D3>,
+ <PIN_PA26__D4>,
+ <PIN_PA27__D5>,
+ <PIN_PA28__D6>,
+ <PIN_PA29__D7>,
+ <PIN_PA30__NWE_NANDWE>,
+ <PIN_PB2__NRD_NANDOE>;
+ bias-pull-up;
+ };
+
+ ale_cle_rdy_cs {
+ pinmux = <PIN_PB0__A21_NANDALE>,
+ <PIN_PB1__A22_NANDCLE>,
+ <PIN_PC8__NANDRDY>,
+ <PIN_PA31__NCS3>;
+ bias-pull-up;
+ };
+ };
+
+ pinctrl_sdmmc0_default: sdmmc0_default {
+ cmd_data {
+ pinmux = <PIN_PA1__SDMMC0_CMD>,
+ <PIN_PA2__SDMMC0_DAT0>,
+ <PIN_PA3__SDMMC0_DAT1>,
+ <PIN_PA4__SDMMC0_DAT2>,
+ <PIN_PA5__SDMMC0_DAT3>,
+ <PIN_PA6__SDMMC0_DAT4>,
+ <PIN_PA7__SDMMC0_DAT5>,
+ <PIN_PA8__SDMMC0_DAT6>,
+ <PIN_PA9__SDMMC0_DAT7>;
+ bias-pull-up;
+ };
+
+ ck_cd_vddsel {
+ pinmux = <PIN_PA0__SDMMC0_CK>,
+ <PIN_PA11__SDMMC0_VDDSEL>,
+ <PIN_PA13__SDMMC0_CD>;
+ bias-disable;
+ };
+ };
+
+ pinctrl_spi0_default: spi0_default {
+ pinmux = <PIN_PA14__SPI0_SPCK>,
+ <PIN_PA15__SPI0_MOSI>,
+ <PIN_PA16__SPI0_MISO>,
+ <PIN_PA17__SPI0_NPCS0>;
+ bias-disable;
+ };
+
+ pinctrl_spi1_default: spi1_default {
+ pinmux = <PIN_PC1__SPI1_SPCK>,
+ <PIN_PC2__SPI1_MOSI>,
+ <PIN_PC3__SPI1_MISO>,
+ <PIN_PC4__SPI1_NPCS0>;
+ bias-disable;
+ };
+
+ pinctrl_uart0_default: uart0_default {
+ pinmux = <PIN_PB26__URXD0>,
+ <PIN_PB27__UTXD0>;
+ bias-disable;
+ };
+
+ pinctrl_uart2_default: uart2_default {
+ pinmux = <PIN_PD23__URXD2>,
+ <PIN_PD24__UTXD2>;
+ bias-disable;
+ };
+
+ pinctrl_usb_default: usb_default {
+ pinmux = <PIN_PB12__GPIO>;
+ bias-disable;
+ };
+
+ pinctrl_usba_vbus: usba_vbus {
+ pinmux = <PIN_PB11__GPIO>;
+ bias-disable;
+ };
+
+ };
+
+ };
+ };
+
+ gpio_keys {
+ compatible = "gpio-keys";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_key_gpio_default>;
+
+ bp1 {
+ label = "PB_USER";
+ gpios = <&pioA PIN_PA10 GPIO_ACTIVE_LOW>;
+ linux,code = <0x104>;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led_gpio_default>;
+ status = "okay";
+
+ red {
+ label = "red";
+ gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>;
+ };
+
+ green {
+ label = "green";
+ gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>;
+ };
+
+ blue {
+ label = "blue";
+ gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+};
--
2.12.2
^ permalink raw reply related
* [PATCH] ACPI / GED: unregister interrupts during shutdown
From: Greg Kroah-Hartman @ 2017-12-07 8:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJZ5v0hEdK_vJcHeoz=Z2H6od=bktspPpTo37Y6qiOT2qptnaA@mail.gmail.com>
On Thu, Dec 07, 2017 at 12:19:25AM +0100, Rafael J. Wysocki wrote:
> Hi Greg,
>
> On Wed, Dec 6, 2017 at 6:16 PM, Rafael J. Wysocki <rafael@kernel.org> wrote:
> > On Wed, Dec 6, 2017 at 5:55 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
> >> On 12/6/2017 11:41 AM, Rafael J. Wysocki wrote:
> >>> On Wed, Dec 6, 2017 at 5:11 PM, Sinan Kaya <okaya@codeaurora.org> wrote:
> >>>> On 12/6/2017 9:57 AM, Sinan Kaya wrote:
> >>>>>> Yes, it should, so I'm not sure why you need the list in the first place.
> >>>>>>
> >>>>>> Also it looks like something along the lines of devres_release_all()
> >>>>>> should be sufficient.
> >>>>> Good suggestion, let me test this.
> >>>>>
> >>>>
> >>>> I tried to pull the code into GED but the API is not public. I also looked
> >>>> at how it is used. I was afraid to mess up with the internals of base.c by
> >>>> calling devres_release_all() externally first and by the driver framework
> >>>> next. I moved away from this approach.
> >>>
> >>> Are you sure it is called by the core in the shutdown path?
> >>
> >> Sorry, I was thinking about a general case not the shutdown path. If we open
> >> this API and have device drivers call it from arbitrary places; then we could
> >> be opening a new can of worms that show up during device driver removal.
>
> [cut]
>
> >
> > OK
> >
> > Anyway, it looks like something is missing in the core.
> >
> > You shouldn't really need to do all that dance in a driver.
>
> We have a problem with the ACPI GED driver which essentially is a
> platform driver requesting a number of interrupts and handling them by
> dispatching a specific AML method.
>
> It uses devm_request_threaded_irq() to request the interrupts, so it
> doesn't need a ->remove() callback, but it turns out to need a
> ->shutdown() one to free all of these interrupts at the shutdown time.
>
> While we can add a ->shutdown() callback to it, that essentially needs
> to duplicate devres_release_all() somewhat.
>
> Any suggestions what to do with that?
Just don't use devm_request_threaded_irq()? :)
Seriously, those are just "helper" functions if your code happens to
follow the pattern they provide, if not, then don't use them, it's not
that hard to provide the correct code to unwind things properly by "open
coding" this logic as needed.
The devm_*irq() functions are known for not being able to be used all of
the time for lots of shutdown and cleanup issues, this isn't the first
time it has happened, which is why we are very careful when taking
"cleanup" patches that use those functions.
thanks,
greg k-h
^ permalink raw reply
* [PATCH] ARM64: dts: amlogic: use generic bus node names
From: Neil Armstrong @ 2017-12-07 8:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206193005.24171-1-khilman@baylibre.com>
On 06/12/2017 20:30, Kevin Hilman wrote:
> The DT spec recommends that node-names have generic names like "bus".
> Fix that in the Amlogic DTs, while leaving the label names to have more
> SoC-specific names that match with the HW documentation.
>
> Suggested-by: Stephen Boyd <sboyd@codeaurora.org>
> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 4 ++--
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 +++---
> 2 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index b932a784b02a..e7213eb53958 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -113,7 +113,7 @@
> #size-cells = <2>;
> ranges;
>
> - cbus: cbus at ffd00000 {
> + cbus: bus at ffd00000 {
> compatible = "simple-bus";
> reg = <0x0 0xffd00000 0x0 0x25000>;
> #address-cells = <2>;
> @@ -175,7 +175,7 @@
> };
> };
>
> - aobus: aobus at ff800000 {
> + aobus: bus at ff800000 {
> compatible = "simple-bus";
> reg = <0x0 0xff800000 0x0 0x100000>;
> #address-cells = <2>;
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index 7cdbf58a062f..6cb3c2a52baf 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -211,7 +211,7 @@
> #size-cells = <2>;
> ranges;
>
> - cbus: cbus at c1100000 {
> + cbus: bus at c1100000 {
> compatible = "simple-bus";
> reg = <0x0 0xc1100000 0x0 0x100000>;
> #address-cells = <2>;
> @@ -366,7 +366,7 @@
> };
> };
>
> - aobus: aobus at c8100000 {
> + aobus: bus at c8100000 {
> compatible = "simple-bus";
> reg = <0x0 0xc8100000 0x0 0x100000>;
> #address-cells = <2>;
> @@ -453,7 +453,7 @@
> };
> };
>
> - hiubus: hiubus at c883c000 {
> + hiubus: bus at c883c000 {
> compatible = "simple-bus";
> reg = <0x0 0xc883c000 0x0 0x2000>;
> #address-cells = <2>;
>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
* [PATCH] soc: fsl: support GUTS driver for ls1012a/ls1046a
From: Yangbo Lu @ 2017-12-07 8:36 UTC (permalink / raw)
To: linux-arm-kernel
This patch is to add compatible strings "fsl,ls1021a-dcfg" and
"fsl,ls1043a-dcfg" into device match table of GUTS driver.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
---
drivers/soc/fsl/guts.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
index d89a6a80c8ef..d98de2c76659 100644
--- a/drivers/soc/fsl/guts.c
+++ b/drivers/soc/fsl/guts.c
@@ -214,6 +214,8 @@ static const struct of_device_id fsl_guts_of_match[] = {
{ .compatible = "fsl,ls1043a-dcfg", },
{ .compatible = "fsl,ls2080a-dcfg", },
{ .compatible = "fsl,ls1088a-dcfg", },
+ { .compatible = "fsl,ls1012a-dcfg", },
+ { .compatible = "fsl,ls1046a-dcfg", },
{}
};
MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
--
2.14.1
^ permalink raw reply related
* [PATCH v4 3/4] clk: meson-axg: add clock controller drivers
From: Neil Armstrong @ 2017-12-07 8:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201012452.27086-4-yixun.lan@amlogic.com>
On 01/12/2017 02:24, Yixun Lan wrote:
> From: Qiufang Dai <qiufang.dai@amlogic.com>
>
> Add clock controller drivers for Amlogic Meson-AXG SoC.
>
> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> arch/arm64/Kconfig.platforms | 1 +
> drivers/clk/meson/Kconfig | 8 +
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/axg.c | 944 +++++++++++++++++++++++++++++++++++++++++++
> drivers/clk/meson/axg.h | 126 ++++++
> 5 files changed, 1080 insertions(+)
> create mode 100644 drivers/clk/meson/axg.c
> create mode 100644 drivers/clk/meson/axg.h
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 2401373565ff..fbedbd8f619a 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -105,6 +105,7 @@ config ARCH_MESON
> select PINCTRL_MESON
> select COMMON_CLK_AMLOGIC
> select COMMON_CLK_GXBB
> + select COMMON_CLK_AXG
> select MESON_IRQ_GPIO
> help
> This enables support for the Amlogic S905 SoCs.
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index d2d0174a6eca..7694302c70a4 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -19,3 +19,11 @@ config COMMON_CLK_GXBB
> help
> Support for the clock controller on AmLogic S905 devices, aka gxbb.
> Say Y if you want peripherals and CPU frequency scaling to work.
> +
> +config COMMON_CLK_AXG
> + bool
> + depends on COMMON_CLK_AMLOGIC
> + select RESET_CONTROLLER
> + help
> + Support for the clock controller on AmLogic A113D devices, aka axg.
> + Say Y if you want peripherals and CPU frequency scaling to work.
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index b139d41b25da..3c03ce583798 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -5,3 +5,4 @@
> obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o clk-audio-divider.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-regmap.o gxbb-aoclk-32k.o
> +obj-$(CONFIG_COMMON_CLK_AXG) += axg.o
> diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
> new file mode 100644
> index 000000000000..03f57541bc1e
> --- /dev/null
> +++ b/drivers/clk/meson/axg.c
> @@ -0,0 +1,944 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * AmLogic Meson-AXG Clock Controller Driver
> + *
> + * Copyright (c) 2016 Baylibre SAS.
> + * Author: Michael Turquette <mturquette@baylibre.com>
> + *
> + * Copyright (c) 2017 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai@amlogic.com>
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/clk-provider.h>
> +#include <linux/of_address.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/init.h>
> +
> +#include "clkc.h"
> +#include "axg.h"
> +
> +static DEFINE_SPINLOCK(clk_lock);
> +
> +static const struct pll_rate_table sys_pll_rate_table[] = {
> + PLL_RATE(24000000, 56, 1, 2),
> + PLL_RATE(48000000, 64, 1, 2),
> + PLL_RATE(72000000, 72, 1, 2),
> + PLL_RATE(96000000, 64, 1, 2),
> + PLL_RATE(120000000, 80, 1, 2),
> + PLL_RATE(144000000, 96, 1, 2),
> + PLL_RATE(168000000, 56, 1, 1),
> + PLL_RATE(192000000, 64, 1, 1),
> + PLL_RATE(216000000, 72, 1, 1),
> + PLL_RATE(240000000, 80, 1, 1),
> + PLL_RATE(264000000, 88, 1, 1),
> + PLL_RATE(288000000, 96, 1, 1),
> + PLL_RATE(312000000, 52, 1, 2),
> + PLL_RATE(336000000, 56, 1, 2),
> + PLL_RATE(360000000, 60, 1, 2),
> + PLL_RATE(384000000, 64, 1, 2),
> + PLL_RATE(408000000, 68, 1, 2),
> + PLL_RATE(432000000, 72, 1, 2),
> + PLL_RATE(456000000, 76, 1, 2),
> + PLL_RATE(480000000, 80, 1, 2),
> + PLL_RATE(504000000, 84, 1, 2),
> + PLL_RATE(528000000, 88, 1, 2),
> + PLL_RATE(552000000, 92, 1, 2),
> + PLL_RATE(576000000, 96, 1, 2),
> + PLL_RATE(600000000, 50, 1, 1),
> + PLL_RATE(624000000, 52, 1, 1),
> + PLL_RATE(648000000, 54, 1, 1),
> + PLL_RATE(672000000, 56, 1, 1),
> + PLL_RATE(696000000, 58, 1, 1),
> + PLL_RATE(720000000, 60, 1, 1),
> + PLL_RATE(744000000, 62, 1, 1),
> + PLL_RATE(768000000, 64, 1, 1),
> + PLL_RATE(792000000, 66, 1, 1),
> + PLL_RATE(816000000, 68, 1, 1),
> + PLL_RATE(840000000, 70, 1, 1),
> + PLL_RATE(864000000, 72, 1, 1),
> + PLL_RATE(888000000, 74, 1, 1),
> + PLL_RATE(912000000, 76, 1, 1),
> + PLL_RATE(936000000, 78, 1, 1),
> + PLL_RATE(960000000, 80, 1, 1),
> + PLL_RATE(984000000, 82, 1, 1),
> + PLL_RATE(1008000000, 84, 1, 1),
> + PLL_RATE(1032000000, 86, 1, 1),
> + PLL_RATE(1056000000, 88, 1, 1),
> + PLL_RATE(1080000000, 90, 1, 1),
> + PLL_RATE(1104000000, 92, 1, 1),
> + PLL_RATE(1128000000, 94, 1, 1),
> + PLL_RATE(1152000000, 96, 1, 1),
> + PLL_RATE(1176000000, 98, 1, 1),
> + PLL_RATE(1200000000, 50, 1, 0),
> + PLL_RATE(1224000000, 51, 1, 0),
> + PLL_RATE(1248000000, 52, 1, 0),
> + PLL_RATE(1272000000, 53, 1, 0),
> + PLL_RATE(1296000000, 54, 1, 0),
> + PLL_RATE(1320000000, 55, 1, 0),
> + PLL_RATE(1344000000, 56, 1, 0),
> + PLL_RATE(1368000000, 57, 1, 0),
> + PLL_RATE(1392000000, 58, 1, 0),
> + PLL_RATE(1416000000, 59, 1, 0),
> + PLL_RATE(1440000000, 60, 1, 0),
> + PLL_RATE(1464000000, 61, 1, 0),
> + PLL_RATE(1488000000, 62, 1, 0),
> + PLL_RATE(1512000000, 63, 1, 0),
> + PLL_RATE(1536000000, 64, 1, 0),
> + PLL_RATE(1560000000, 65, 1, 0),
> + PLL_RATE(1584000000, 66, 1, 0),
> + PLL_RATE(1608000000, 67, 1, 0),
> + PLL_RATE(1632000000, 68, 1, 0),
> + PLL_RATE(1656000000, 68, 1, 0),
> + PLL_RATE(1680000000, 68, 1, 0),
> + PLL_RATE(1704000000, 68, 1, 0),
> + PLL_RATE(1728000000, 69, 1, 0),
> + PLL_RATE(1752000000, 69, 1, 0),
> + PLL_RATE(1776000000, 69, 1, 0),
> + PLL_RATE(1800000000, 69, 1, 0),
> + PLL_RATE(1824000000, 70, 1, 0),
> + PLL_RATE(1848000000, 70, 1, 0),
> + PLL_RATE(1872000000, 70, 1, 0),
> + PLL_RATE(1896000000, 70, 1, 0),
> + PLL_RATE(1920000000, 71, 1, 0),
> + PLL_RATE(1944000000, 71, 1, 0),
> + PLL_RATE(1968000000, 71, 1, 0),
> + PLL_RATE(1992000000, 71, 1, 0),
> + PLL_RATE(2016000000, 72, 1, 0),
> + PLL_RATE(2040000000, 72, 1, 0),
> + PLL_RATE(2064000000, 72, 1, 0),
> + PLL_RATE(2088000000, 72, 1, 0),
> + PLL_RATE(2112000000, 73, 1, 0),
> + { /* sentinel */ },
> +};
> +
> +static struct meson_clk_pll axg_fixed_pll = {
> + .m = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 0,
> + .width = 9,
> + },
> + .n = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 9,
> + .width = 5,
> + },
> + .od = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 16,
> + .width = 2,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "fixed_pll",
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_names = (const char *[]){ "xtal" },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + },
> +};
> +
> +static struct meson_clk_pll axg_sys_pll = {
> + .m = {
> + .reg_off = HHI_SYS_PLL_CNTL,
> + .shift = 0,
> + .width = 9,
> + },
> + .n = {
> + .reg_off = HHI_SYS_PLL_CNTL,
> + .shift = 9,
> + .width = 5,
> + },
> + .od = {
> + .reg_off = HHI_SYS_PLL_CNTL,
> + .shift = 10,
> + .width = 2,
> + },
> + .rate_table = sys_pll_rate_table,
> + .rate_count = ARRAY_SIZE(sys_pll_rate_table),
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "sys_pll",
> + .ops = &meson_clk_pll_ro_ops,
> + .parent_names = (const char *[]){ "xtal" },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + },
> +};
> +
> +static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
> + PLL_RATE(240000000, 40, 1, 2),
> + PLL_RATE(246000000, 41, 1, 2),
> + PLL_RATE(252000000, 42, 1, 2),
> + PLL_RATE(258000000, 43, 1, 2),
> + PLL_RATE(264000000, 44, 1, 2),
> + PLL_RATE(270000000, 45, 1, 2),
> + PLL_RATE(276000000, 46, 1, 2),
> + PLL_RATE(282000000, 47, 1, 2),
> + PLL_RATE(288000000, 48, 1, 2),
> + PLL_RATE(294000000, 49, 1, 2),
> + PLL_RATE(300000000, 50, 1, 2),
> + PLL_RATE(306000000, 51, 1, 2),
> + PLL_RATE(312000000, 52, 1, 2),
> + PLL_RATE(318000000, 53, 1, 2),
> + PLL_RATE(324000000, 54, 1, 2),
> + PLL_RATE(330000000, 55, 1, 2),
> + PLL_RATE(336000000, 56, 1, 2),
> + PLL_RATE(342000000, 57, 1, 2),
> + PLL_RATE(348000000, 58, 1, 2),
> + PLL_RATE(354000000, 59, 1, 2),
> + PLL_RATE(360000000, 60, 1, 2),
> + PLL_RATE(366000000, 61, 1, 2),
> + PLL_RATE(372000000, 62, 1, 2),
> + PLL_RATE(378000000, 63, 1, 2),
> + PLL_RATE(384000000, 64, 1, 2),
> + PLL_RATE(390000000, 65, 1, 3),
> + PLL_RATE(396000000, 66, 1, 3),
> + PLL_RATE(402000000, 67, 1, 3),
> + PLL_RATE(408000000, 68, 1, 3),
> + PLL_RATE(480000000, 40, 1, 1),
> + PLL_RATE(492000000, 41, 1, 1),
> + PLL_RATE(504000000, 42, 1, 1),
> + PLL_RATE(516000000, 43, 1, 1),
> + PLL_RATE(528000000, 44, 1, 1),
> + PLL_RATE(540000000, 45, 1, 1),
> + PLL_RATE(552000000, 46, 1, 1),
> + PLL_RATE(564000000, 47, 1, 1),
> + PLL_RATE(576000000, 48, 1, 1),
> + PLL_RATE(588000000, 49, 1, 1),
> + PLL_RATE(600000000, 50, 1, 1),
> + PLL_RATE(612000000, 51, 1, 1),
> + PLL_RATE(624000000, 52, 1, 1),
> + PLL_RATE(636000000, 53, 1, 1),
> + PLL_RATE(648000000, 54, 1, 1),
> + PLL_RATE(660000000, 55, 1, 1),
> + PLL_RATE(672000000, 56, 1, 1),
> + PLL_RATE(684000000, 57, 1, 1),
> + PLL_RATE(696000000, 58, 1, 1),
> + PLL_RATE(708000000, 59, 1, 1),
> + PLL_RATE(720000000, 60, 1, 1),
> + PLL_RATE(732000000, 61, 1, 1),
> + PLL_RATE(744000000, 62, 1, 1),
> + PLL_RATE(756000000, 63, 1, 1),
> + PLL_RATE(768000000, 64, 1, 1),
> + PLL_RATE(780000000, 65, 1, 1),
> + PLL_RATE(792000000, 66, 1, 1),
> + PLL_RATE(804000000, 67, 1, 1),
> + PLL_RATE(816000000, 68, 1, 1),
> + PLL_RATE(960000000, 40, 1, 0),
> + PLL_RATE(984000000, 41, 1, 0),
> + PLL_RATE(1008000000, 42, 1, 0),
> + PLL_RATE(1032000000, 43, 1, 0),
> + PLL_RATE(1056000000, 44, 1, 0),
> + PLL_RATE(1080000000, 45, 1, 0),
> + PLL_RATE(1104000000, 46, 1, 0),
> + PLL_RATE(1128000000, 47, 1, 0),
> + PLL_RATE(1152000000, 48, 1, 0),
> + PLL_RATE(1176000000, 49, 1, 0),
> + PLL_RATE(1200000000, 50, 1, 0),
> + PLL_RATE(1224000000, 51, 1, 0),
> + PLL_RATE(1248000000, 52, 1, 0),
> + PLL_RATE(1272000000, 53, 1, 0),
> + PLL_RATE(1296000000, 54, 1, 0),
> + PLL_RATE(1320000000, 55, 1, 0),
> + PLL_RATE(1344000000, 56, 1, 0),
> + PLL_RATE(1368000000, 57, 1, 0),
> + PLL_RATE(1392000000, 58, 1, 0),
> + PLL_RATE(1416000000, 59, 1, 0),
> + PLL_RATE(1440000000, 60, 1, 0),
> + PLL_RATE(1464000000, 61, 1, 0),
> + PLL_RATE(1488000000, 62, 1, 0),
> + PLL_RATE(1512000000, 63, 1, 0),
> + PLL_RATE(1536000000, 64, 1, 0),
> + PLL_RATE(1560000000, 65, 1, 0),
> + PLL_RATE(1584000000, 66, 1, 0),
> + PLL_RATE(1608000000, 67, 1, 0),
> + PLL_RATE(1632000000, 68, 1, 0),
> + { /* sentinel */ },
> +};
> +
> +struct pll_params_table axg_gp0_params_table[] = {
> + PLL_PARAM(HHI_GP0_PLL_CNTL, 0x40010250),
> + PLL_PARAM(HHI_GP0_PLL_CNTL1, 0xc084a000),
> + PLL_PARAM(HHI_GP0_PLL_CNTL2, 0xb75020be),
> + PLL_PARAM(HHI_GP0_PLL_CNTL3, 0x0a59a288),
> + PLL_PARAM(HHI_GP0_PLL_CNTL4, 0xc000004d),
> + PLL_PARAM(HHI_GP0_PLL_CNTL5, 0x00078000),
> +};
> +
> +static struct meson_clk_pll axg_gp0_pll = {
> + .m = {
> + .reg_off = HHI_GP0_PLL_CNTL,
> + .shift = 0,
> + .width = 9,
> + },
> + .n = {
> + .reg_off = HHI_GP0_PLL_CNTL,
> + .shift = 9,
> + .width = 5,
> + },
> + .od = {
> + .reg_off = HHI_GP0_PLL_CNTL,
> + .shift = 16,
> + .width = 2,
> + },
> + .params = {
> + .params_table = axg_gp0_params_table,
> + .params_count = ARRAY_SIZE(axg_gp0_params_table),
> + .no_init_reset = true,
> + .reset_lock_loop = true,
> + },
> + .rate_table = axg_gp0_pll_rate_table,
> + .rate_count = ARRAY_SIZE(axg_gp0_pll_rate_table),
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "gp0_pll",
> + .ops = &meson_clk_pll_ops,
> + .parent_names = (const char *[]){ "xtal" },
> + .num_parents = 1,
> + .flags = CLK_GET_RATE_NOCACHE,
> + },
> +};
> +
> +
> +static struct clk_fixed_factor axg_fclk_div2 = {
> + .mult = 1,
> + .div = 2,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div2",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div3 = {
> + .mult = 1,
> + .div = 3,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div3",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div4 = {
> + .mult = 1,
> + .div = 4,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div4",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div5 = {
> + .mult = 1,
> + .div = 5,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div5",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_fixed_factor axg_fclk_div7 = {
> + .mult = 1,
> + .div = 7,
> + .hw.init = &(struct clk_init_data){
> + .name = "fclk_div7",
> + .ops = &clk_fixed_factor_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll0 = {
> + .sdm = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 15,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 16,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL_CNTL7,
> + .shift = 14,
> + .width = 1,
> + },
> + .ssen = {
> + .reg_off = HHI_MPLL_CNTL,
> + .shift = 25,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll0",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll1 = {
> + .sdm = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 15,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 16,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL_CNTL8,
> + .shift = 14,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll1",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll2 = {
> + .sdm = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 0,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 15,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 16,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL_CNTL9,
> + .shift = 14,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll2",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct meson_clk_mpll axg_mpll3 = {
> + .sdm = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 12,
> + .width = 14,
> + },
> + .sdm_en = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 11,
> + .width = 1,
> + },
> + .n2 = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 2,
> + .width = 9,
> + },
> + .en = {
> + .reg_off = HHI_MPLL3_CNTL0,
> + .shift = 0,
> + .width = 1,
> + },
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpll3",
> + .ops = &meson_clk_mpll_ops,
> + .parent_names = (const char *[]){ "fixed_pll" },
> + .num_parents = 1,
> + },
> +};
> +
> +/*
> + * FIXME The legacy composite clocks (e.g. clk81) are both PLL post-dividers
> + * and should be modeled with their respective PLLs via the forthcoming
> + * coordinated clock rates feature
> + */
> +static u32 mux_table_clk81[] = { 0, 2, 3, 4, 5, 6, 7 };
> +static const char * const clk81_parent_names[] = {
> + "xtal", "fclk_div7", "mpll1", "mpll2", "fclk_div4",
> + "fclk_div3", "fclk_div5"
> +};
> +
> +static struct clk_mux axg_mpeg_clk_sel = {
> + .reg = (void *)HHI_MPEG_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 12,
> + .flags = CLK_MUX_READ_ONLY,
> + .table = mux_table_clk81,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpeg_clk_sel",
> + .ops = &clk_mux_ro_ops,
> + /*
> + * bits 14:12 selects from 8 possible parents:
> + * xtal, 1'b0 (wtf), fclk_div7, mpll_clkout1, mpll_clkout2,
> + * fclk_div4, fclk_div3, fclk_div5
> + */
> + .parent_names = clk81_parent_names,
> + .num_parents = ARRAY_SIZE(clk81_parent_names),
> + .flags = CLK_SET_RATE_NO_REPARENT,
> + },
> +};
> +
> +static struct clk_divider axg_mpeg_clk_div = {
> + .reg = (void *)HHI_MPEG_CLK_CNTL,
> + .shift = 0,
> + .width = 7,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "mpeg_clk_div",
> + .ops = &clk_divider_ops,
> + .parent_names = (const char *[]){ "mpeg_clk_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_gate axg_clk81 = {
> + .reg = (void *)HHI_MPEG_CLK_CNTL,
> + .bit_idx = 7,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "clk81",
> + .ops = &clk_gate_ops,
> + .parent_names = (const char *[]){ "mpeg_clk_div" },
> + .num_parents = 1,
> + .flags = (CLK_SET_RATE_PARENT | CLK_IS_CRITICAL),
> + },
> +};
> +
> +static const char * const axg_sd_emmc_clk0_parent_names[] = {
> + "xtal", "fclk_div2", "fclk_div3", "fclk_div5", "fclk_div7",
> +
> + /*
> + * Following these parent clocks, we should also have had mpll2, mpll3
> + * and gp0_pll but these clocks are too precious to be used here. All
> + * the necessary rates for MMC and NAND operation can be acheived using
> + * xtal or fclk_div clocks
> + */
> +};
> +
> +/* SDcard clock */
> +static struct clk_mux axg_sd_emmc_b_clk0_sel = {
> + .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 25,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_b_clk0_sel",
> + .ops = &clk_mux_ops,
> + .parent_names = axg_sd_emmc_clk0_parent_names,
> + .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_divider axg_sd_emmc_b_clk0_div = {
> + .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
> + .shift = 16,
> + .width = 7,
> + .lock = &clk_lock,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_b_clk0_div",
> + .ops = &clk_divider_ops,
> + .parent_names = (const char *[]){ "sd_emmc_b_clk0_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_gate axg_sd_emmc_b_clk0 = {
> + .reg = (void *)HHI_SD_EMMC_CLK_CNTL,
> + .bit_idx = 23,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "sd_emmc_b_clk0",
> + .ops = &clk_gate_ops,
> + .parent_names = (const char *[]){ "sd_emmc_b_clk0_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* EMMC/NAND clock */
> +static struct clk_mux axg_sd_emmc_c_clk0_sel = {
> + .reg = (void *)HHI_NAND_CLK_CNTL,
> + .mask = 0x7,
> + .shift = 9,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_c_clk0_sel",
> + .ops = &clk_mux_ops,
> + .parent_names = axg_sd_emmc_clk0_parent_names,
> + .num_parents = ARRAY_SIZE(axg_sd_emmc_clk0_parent_names),
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_divider axg_sd_emmc_c_clk0_div = {
> + .reg = (void *)HHI_NAND_CLK_CNTL,
> + .shift = 0,
> + .width = 7,
> + .lock = &clk_lock,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> + .hw.init = &(struct clk_init_data) {
> + .name = "sd_emmc_c_clk0_div",
> + .ops = &clk_divider_ops,
> + .parent_names = (const char *[]){ "sd_emmc_c_clk0_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_gate axg_sd_emmc_c_clk0 = {
> + .reg = (void *)HHI_NAND_CLK_CNTL,
> + .bit_idx = 7,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "sd_emmc_c_clk0",
> + .ops = &clk_gate_ops,
> + .parent_names = (const char *[]){ "sd_emmc_c_clk0_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +/* Everything Else (EE) domain gates */
> +static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
> +static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
> +static MESON_GATE(axg_mipi_dsi_host, HHI_GCLK_MPEG0, 3);
> +static MESON_GATE(axg_isa, HHI_GCLK_MPEG0, 5);
> +static MESON_GATE(axg_pl301, HHI_GCLK_MPEG0, 6);
> +static MESON_GATE(axg_periphs, HHI_GCLK_MPEG0, 7);
> +static MESON_GATE(axg_spicc_0, HHI_GCLK_MPEG0, 8);
> +static MESON_GATE(axg_i2c, HHI_GCLK_MPEG0, 9);
> +static MESON_GATE(axg_rng0, HHI_GCLK_MPEG0, 12);
> +static MESON_GATE(axg_uart0, HHI_GCLK_MPEG0, 13);
> +static MESON_GATE(axg_mipi_dsi_phy, HHI_GCLK_MPEG0, 14);
> +static MESON_GATE(axg_spicc_1, HHI_GCLK_MPEG0, 15);
> +static MESON_GATE(axg_pcie_a, HHI_GCLK_MPEG0, 16);
> +static MESON_GATE(axg_pcie_b, HHI_GCLK_MPEG0, 17);
> +static MESON_GATE(axg_hiu_reg, HHI_GCLK_MPEG0, 19);
> +static MESON_GATE(axg_assist_misc, HHI_GCLK_MPEG0, 23);
> +static MESON_GATE(axg_emmc_b, HHI_GCLK_MPEG0, 25);
> +static MESON_GATE(axg_emmc_c, HHI_GCLK_MPEG0, 26);
> +static MESON_GATE(axg_dma, HHI_GCLK_MPEG0, 27);
> +static MESON_GATE(axg_spi, HHI_GCLK_MPEG0, 30);
> +
> +static MESON_GATE(axg_audio, HHI_GCLK_MPEG1, 0);
> +static MESON_GATE(axg_eth_core, HHI_GCLK_MPEG1, 3);
> +static MESON_GATE(axg_uart1, HHI_GCLK_MPEG1, 16);
> +static MESON_GATE(axg_g2d, HHI_GCLK_MPEG1, 20);
> +static MESON_GATE(axg_usb0, HHI_GCLK_MPEG1, 21);
> +static MESON_GATE(axg_usb1, HHI_GCLK_MPEG1, 22);
> +static MESON_GATE(axg_reset, HHI_GCLK_MPEG1, 23);
> +static MESON_GATE(axg_usb_general, HHI_GCLK_MPEG1, 26);
> +static MESON_GATE(axg_ahb_arb0, HHI_GCLK_MPEG1, 29);
> +static MESON_GATE(axg_efuse, HHI_GCLK_MPEG1, 30);
> +static MESON_GATE(axg_boot_rom, HHI_GCLK_MPEG1, 31);
> +
> +static MESON_GATE(axg_ahb_data_bus, HHI_GCLK_MPEG2, 1);
> +static MESON_GATE(axg_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
> +static MESON_GATE(axg_usb1_to_ddr, HHI_GCLK_MPEG2, 8);
> +static MESON_GATE(axg_usb0_to_ddr, HHI_GCLK_MPEG2, 9);
> +static MESON_GATE(axg_mmc_pclk, HHI_GCLK_MPEG2, 11);
> +static MESON_GATE(axg_vpu_intr, HHI_GCLK_MPEG2, 25);
> +static MESON_GATE(axg_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
> +static MESON_GATE(axg_gic, HHI_GCLK_MPEG2, 30);
> +
> +/* Always On (AO) domain gates */
> +
> +static MESON_GATE(axg_ao_media_cpu, HHI_GCLK_AO, 0);
> +static MESON_GATE(axg_ao_ahb_sram, HHI_GCLK_AO, 1);
> +static MESON_GATE(axg_ao_ahb_bus, HHI_GCLK_AO, 2);
> +static MESON_GATE(axg_ao_iface, HHI_GCLK_AO, 3);
> +static MESON_GATE(axg_ao_i2c, HHI_GCLK_AO, 4);
> +
> +/* Array of all clocks provided by this provider */
> +
> +static struct clk_hw_onecell_data axg_hw_onecell_data = {
> + .hws = {
> + [CLKID_SYS_PLL] = &axg_sys_pll.hw,
> + [CLKID_FIXED_PLL] = &axg_fixed_pll.hw,
> + [CLKID_FCLK_DIV2] = &axg_fclk_div2.hw,
> + [CLKID_FCLK_DIV3] = &axg_fclk_div3.hw,
> + [CLKID_FCLK_DIV4] = &axg_fclk_div4.hw,
> + [CLKID_FCLK_DIV5] = &axg_fclk_div5.hw,
> + [CLKID_FCLK_DIV7] = &axg_fclk_div7.hw,
> + [CLKID_GP0_PLL] = &axg_gp0_pll.hw,
> + [CLKID_MPEG_SEL] = &axg_mpeg_clk_sel.hw,
> + [CLKID_MPEG_DIV] = &axg_mpeg_clk_div.hw,
> + [CLKID_CLK81] = &axg_clk81.hw,
> + [CLKID_MPLL0] = &axg_mpll0.hw,
> + [CLKID_MPLL1] = &axg_mpll1.hw,
> + [CLKID_MPLL2] = &axg_mpll2.hw,
> + [CLKID_MPLL3] = &axg_mpll3.hw,
> + [CLKID_DDR] = &axg_ddr.hw,
> + [CLKID_AUDIO_LOCKER] = &axg_audio_locker.hw,
> + [CLKID_MIPI_DSI_HOST] = &axg_mipi_dsi_host.hw,
> + [CLKID_ISA] = &axg_isa.hw,
> + [CLKID_PL301] = &axg_pl301.hw,
> + [CLKID_PERIPHS] = &axg_periphs.hw,
> + [CLKID_SPICC0] = &axg_spicc_0.hw,
> + [CLKID_I2C] = &axg_i2c.hw,
> + [CLKID_RNG0] = &axg_rng0.hw,
> + [CLKID_UART0] = &axg_uart0.hw,
> + [CLKID_MIPI_DSI_PHY] = &axg_mipi_dsi_phy.hw,
> + [CLKID_SPICC1] = &axg_spicc_1.hw,
> + [CLKID_PCIE_A] = &axg_pcie_a.hw,
> + [CLKID_PCIE_B] = &axg_pcie_b.hw,
> + [CLKID_HIU_IFACE] = &axg_hiu_reg.hw,
> + [CLKID_ASSIST_MISC] = &axg_assist_misc.hw,
> + [CLKID_SD_EMMC_B] = &axg_emmc_b.hw,
> + [CLKID_SD_EMMC_C] = &axg_emmc_c.hw,
> + [CLKID_DMA] = &axg_dma.hw,
> + [CLKID_SPI] = &axg_spi.hw,
> + [CLKID_AUDIO] = &axg_audio.hw,
> + [CLKID_ETH] = &axg_eth_core.hw,
> + [CLKID_UART1] = &axg_uart1.hw,
> + [CLKID_G2D] = &axg_g2d.hw,
> + [CLKID_USB0] = &axg_usb0.hw,
> + [CLKID_USB1] = &axg_usb1.hw,
> + [CLKID_RESET] = &axg_reset.hw,
> + [CLKID_USB] = &axg_usb_general.hw,
> + [CLKID_AHB_ARB0] = &axg_ahb_arb0.hw,
> + [CLKID_EFUSE] = &axg_efuse.hw,
> + [CLKID_BOOT_ROM] = &axg_boot_rom.hw,
> + [CLKID_AHB_DATA_BUS] = &axg_ahb_data_bus.hw,
> + [CLKID_AHB_CTRL_BUS] = &axg_ahb_ctrl_bus.hw,
> + [CLKID_USB1_DDR_BRIDGE] = &axg_usb1_to_ddr.hw,
> + [CLKID_USB0_DDR_BRIDGE] = &axg_usb0_to_ddr.hw,
> + [CLKID_MMC_PCLK] = &axg_mmc_pclk.hw,
> + [CLKID_VPU_INTR] = &axg_vpu_intr.hw,
> + [CLKID_SEC_AHB_AHB3_BRIDGE] = &axg_sec_ahb_ahb3_bridge.hw,
> + [CLKID_GIC] = &axg_gic.hw,
> + [CLKID_AO_MEDIA_CPU] = &axg_ao_media_cpu.hw,
> + [CLKID_AO_AHB_SRAM] = &axg_ao_ahb_sram.hw,
> + [CLKID_AO_AHB_BUS] = &axg_ao_ahb_bus.hw,
> + [CLKID_AO_IFACE] = &axg_ao_iface.hw,
> + [CLKID_AO_I2C] = &axg_ao_i2c.hw,
> + [CLKID_SD_EMMC_B_CLK0_SEL] = &axg_sd_emmc_b_clk0_sel.hw,
> + [CLKID_SD_EMMC_B_CLK0_DIV] = &axg_sd_emmc_b_clk0_div.hw,
> + [CLKID_SD_EMMC_B_CLK0] = &axg_sd_emmc_b_clk0.hw,
> + [CLKID_SD_EMMC_C_CLK0_SEL] = &axg_sd_emmc_c_clk0_sel.hw,
> + [CLKID_SD_EMMC_C_CLK0_DIV] = &axg_sd_emmc_c_clk0_div.hw,
> + [CLKID_SD_EMMC_C_CLK0] = &axg_sd_emmc_c_clk0.hw,
> + [NR_CLKS] = NULL,
> + },
> + .num = NR_CLKS,
> +};
> +
> +/* Convenience tables to populate base addresses in .probe */
> +
> +static struct meson_clk_pll *const axg_clk_plls[] = {
> + &axg_fixed_pll,
> + &axg_sys_pll,
> + &axg_gp0_pll,
> +};
> +
> +static struct meson_clk_mpll *const axg_clk_mplls[] = {
> + &axg_mpll0,
> + &axg_mpll1,
> + &axg_mpll2,
> + &axg_mpll3,
> +};
> +
> +static struct clk_gate *const axg_clk_gates[] = {
> + &axg_clk81,
> + &axg_ddr,
> + &axg_audio_locker,
> + &axg_mipi_dsi_host,
> + &axg_isa,
> + &axg_pl301,
> + &axg_periphs,
> + &axg_spicc_0,
> + &axg_i2c,
> + &axg_rng0,
> + &axg_uart0,
> + &axg_mipi_dsi_phy,
> + &axg_spicc_1,
> + &axg_pcie_a,
> + &axg_pcie_b,
> + &axg_hiu_reg,
> + &axg_assist_misc,
> + &axg_emmc_b,
> + &axg_emmc_c,
> + &axg_dma,
> + &axg_spi,
> + &axg_audio,
> + &axg_eth_core,
> + &axg_uart1,
> + &axg_g2d,
> + &axg_usb0,
> + &axg_usb1,
> + &axg_reset,
> + &axg_usb_general,
> + &axg_ahb_arb0,
> + &axg_efuse,
> + &axg_boot_rom,
> + &axg_ahb_data_bus,
> + &axg_ahb_ctrl_bus,
> + &axg_usb1_to_ddr,
> + &axg_usb0_to_ddr,
> + &axg_mmc_pclk,
> + &axg_vpu_intr,
> + &axg_sec_ahb_ahb3_bridge,
> + &axg_gic,
> + &axg_ao_media_cpu,
> + &axg_ao_ahb_sram,
> + &axg_ao_ahb_bus,
> + &axg_ao_iface,
> + &axg_ao_i2c,
> + &axg_sd_emmc_b_clk0,
> + &axg_sd_emmc_c_clk0,
> +};
> +
> +static struct clk_mux *const axg_clk_muxes[] = {
> + &axg_mpeg_clk_sel,
> + &axg_sd_emmc_b_clk0_sel,
> + &axg_sd_emmc_c_clk0_sel,
> +};
> +
> +static struct clk_divider *const axg_clk_dividers[] = {
> + &axg_mpeg_clk_div,
> + &axg_sd_emmc_b_clk0_div,
> + &axg_sd_emmc_c_clk0_div,
> +};
> +
> +struct clkc_data {
> + struct clk_gate *const *clk_gates;
> + unsigned int clk_gates_count;
> + struct meson_clk_mpll *const *clk_mplls;
> + unsigned int clk_mplls_count;
> + struct meson_clk_pll *const *clk_plls;
> + unsigned int clk_plls_count;
> + struct clk_mux *const *clk_muxes;
> + unsigned int clk_muxes_count;
> + struct clk_divider *const *clk_dividers;
> + unsigned int clk_dividers_count;
> + struct clk_hw_onecell_data *hw_onecell_data;
> +};
> +
> +static const struct clkc_data axg_clkc_data = {
> + .clk_gates = axg_clk_gates,
> + .clk_gates_count = ARRAY_SIZE(axg_clk_gates),
> + .clk_mplls = axg_clk_mplls,
> + .clk_mplls_count = ARRAY_SIZE(axg_clk_mplls),
> + .clk_plls = axg_clk_plls,
> + .clk_plls_count = ARRAY_SIZE(axg_clk_plls),
> + .clk_muxes = axg_clk_muxes,
> + .clk_muxes_count = ARRAY_SIZE(axg_clk_muxes),
> + .clk_dividers = axg_clk_dividers,
> + .clk_dividers_count = ARRAY_SIZE(axg_clk_dividers),
> + .hw_onecell_data = &axg_hw_onecell_data,
> +};
> +
> +static const struct of_device_id clkc_match_table[] = {
> + { .compatible = "amlogic,axg-clkc", .data = &axg_clkc_data },
> + {}
> +};
> +
> +static int axg_clkc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + const struct clkc_data *clkc_data;
> + struct resource *res;
> + void __iomem *clk_base;
> + int ret, clkid, i;
> +
> + clkc_data = of_device_get_match_data(&pdev->dev);
> + if (!clkc_data)
> + return -EINVAL;
> +
> + /* Generic clocks and PLLs */
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + clk_base = devm_ioremap_resource(&pdev->dev, res);
Please use here devm_ioremap(&pdev->dev, res->start, resource_size(res))
since the HHI zone is shared with non clock related registers like the
memory power domains controls.
> + if (IS_ERR(clk_base)) {
> + dev_err(&pdev->dev, "Unable to map clk base\n");
> + return -ENXIO;
> + }
> +
> + /* Populate base address for PLLs */
> + for (i = 0; i < clkc_data->clk_plls_count; i++)
> + clkc_data->clk_plls[i]->base = clk_base;
> +
> + /* Populate base address for MPLLs */
> + for (i = 0; i < clkc_data->clk_mplls_count; i++)
> + clkc_data->clk_mplls[i]->base = clk_base;
> +
> + /* Populate base address for gates */
> + for (i = 0; i < clkc_data->clk_gates_count; i++)
> + clkc_data->clk_gates[i]->reg = clk_base +
> + (u64)clkc_data->clk_gates[i]->reg;
> +
> + /* Populate base address for muxes */
> + for (i = 0; i < clkc_data->clk_muxes_count; i++)
> + clkc_data->clk_muxes[i]->reg = clk_base +
> + (u64)clkc_data->clk_muxes[i]->reg;
> +
> + /* Populate base address for dividers */
> + for (i = 0; i < clkc_data->clk_dividers_count; i++)
> + clkc_data->clk_dividers[i]->reg = clk_base +
> + (u64)clkc_data->clk_dividers[i]->reg;
> +
> + for (clkid = 0; clkid < clkc_data->hw_onecell_data->num; clkid++) {
> + /* array might be sparse */
> + if (!clkc_data->hw_onecell_data->hws[clkid])
> + continue;
> +
> + ret = devm_clk_hw_register(dev,
> + clkc_data->hw_onecell_data->hws[clkid]);
> + if (ret) {
> + dev_err(&pdev->dev, "Clock registration failed\n");
> + return ret;
> + }
> + }
> +
> + return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
> + clkc_data->hw_onecell_data);
> +}
> +
> +static struct platform_driver axg_driver = {
> + .probe = axg_clkc_probe,
> + .driver = {
> + .name = "axg-clkc",
> + .of_match_table = clkc_match_table,
> + },
> +};
> +
> +builtin_platform_driver(axg_driver);
> diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
> new file mode 100644
> index 000000000000..ce0bafdb6b28
> --- /dev/null
> +++ b/drivers/clk/meson/axg.h
> @@ -0,0 +1,126 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Copyright (c) 2016 AmLogic, Inc.
> + * Author: Michael Turquette <mturquette@baylibre.com>
> + *
> + * Copyright (c) 2017 Amlogic, inc.
> + * Author: Qiufang Dai <qiufang.dai@amlogic.com>
> + *
> + */
> +#ifndef __AXG_H
> +#define __AXG_H
> +
> +/*
> + * Clock controller register offsets
> + *
> + * Register offsets from the data sheet must be multiplied by 4 before
> + * adding them to the base address to get the right value.
> + */
> +#define HHI_GP0_PLL_CNTL 0x40
> +#define HHI_GP0_PLL_CNTL2 0x44
> +#define HHI_GP0_PLL_CNTL3 0x48
> +#define HHI_GP0_PLL_CNTL4 0x4c
> +#define HHI_GP0_PLL_CNTL5 0x50
> +#define HHI_GP0_PLL_STS 0x54
> +#define HHI_GP0_PLL_CNTL1 0x58
> +#define HHI_HIFI_PLL_CNTL 0x80
> +#define HHI_HIFI_PLL_CNTL2 0x84
> +#define HHI_HIFI_PLL_CNTL3 0x88
> +#define HHI_HIFI_PLL_CNTL4 0x8C
> +#define HHI_HIFI_PLL_CNTL5 0x90
> +#define HHI_HIFI_PLL_STS 0x94
> +#define HHI_HIFI_PLL_CNTL1 0x98
> +
> +#define HHI_XTAL_DIVN_CNTL 0xbc
> +#define HHI_GCLK2_MPEG0 0xc0
> +#define HHI_GCLK2_MPEG1 0xc4
> +#define HHI_GCLK2_MPEG2 0xc8
> +#define HHI_GCLK2_OTHER 0xd0
> +#define HHI_GCLK2_AO 0xd4
> +#define HHI_PCIE_PLL_CNTL 0xd8
> +#define HHI_PCIE_PLL_CNTL1 0xdC
> +#define HHI_PCIE_PLL_CNTL2 0xe0
> +#define HHI_PCIE_PLL_CNTL3 0xe4
> +#define HHI_PCIE_PLL_CNTL4 0xe8
> +#define HHI_PCIE_PLL_CNTL5 0xec
> +#define HHI_PCIE_PLL_CNTL6 0xf0
> +#define HHI_PCIE_PLL_STS 0xf4
> +
> +#define HHI_MEM_PD_REG0 0x100
> +#define HHI_VPU_MEM_PD_REG0 0x104
> +#define HHI_VIID_CLK_DIV 0x128
> +#define HHI_VIID_CLK_CNTL 0x12c
> +
> +#define HHI_GCLK_MPEG0 0x140
> +#define HHI_GCLK_MPEG1 0x144
> +#define HHI_GCLK_MPEG2 0x148
> +#define HHI_GCLK_OTHER 0x150
> +#define HHI_GCLK_AO 0x154
> +#define HHI_SYS_CPU_CLK_CNTL1 0x15c
> +#define HHI_SYS_CPU_RESET_CNTL 0x160
> +#define HHI_VID_CLK_DIV 0x164
> +#define HHI_SPICC_HCLK_CNTL 0x168
> +
> +#define HHI_MPEG_CLK_CNTL 0x174
> +#define HHI_VID_CLK_CNTL 0x17c
> +#define HHI_TS_CLK_CNTL 0x190
> +#define HHI_VID_CLK_CNTL2 0x194
> +#define HHI_SYS_CPU_CLK_CNTL0 0x19c
> +#define HHI_VID_PLL_CLK_DIV 0x1a0
> +#define HHI_VPU_CLK_CNTL 0x1bC
> +
> +#define HHI_VAPBCLK_CNTL 0x1F4
> +
> +#define HHI_GEN_CLK_CNTL 0x228
> +
> +#define HHI_VDIN_MEAS_CLK_CNTL 0x250
> +#define HHI_NAND_CLK_CNTL 0x25C
> +#define HHI_SD_EMMC_CLK_CNTL 0x264
> +
> +#define HHI_MPLL_CNTL 0x280
> +#define HHI_MPLL_CNTL2 0x284
> +#define HHI_MPLL_CNTL3 0x288
> +#define HHI_MPLL_CNTL4 0x28C
> +#define HHI_MPLL_CNTL5 0x290
> +#define HHI_MPLL_CNTL6 0x294
> +#define HHI_MPLL_CNTL7 0x298
> +#define HHI_MPLL_CNTL8 0x29C
> +#define HHI_MPLL_CNTL9 0x2A0
> +#define HHI_MPLL_CNTL10 0x2A4
> +
> +#define HHI_MPLL3_CNTL0 0x2E0
> +#define HHI_MPLL3_CNTL1 0x2E4
> +#define HHI_PLL_TOP_MISC 0x2E8
> +
> +#define HHI_SYS_PLL_CNTL1 0x2FC
> +#define HHI_SYS_PLL_CNTL 0x300
> +#define HHI_SYS_PLL_CNTL2 0x304
> +#define HHI_SYS_PLL_CNTL3 0x308
> +#define HHI_SYS_PLL_CNTL4 0x30c
> +#define HHI_SYS_PLL_CNTL5 0x310
> +#define HHI_SYS_PLL_STS 0x314
> +#define HHI_DPLL_TOP_I 0x318
> +#define HHI_DPLL_TOP2_I 0x31C
> +
> +/*
> + * CLKID index values
> + *
> + * These indices are entirely contrived and do not map onto the hardware.
> + * It has now been decided to expose everything by default in the DT header:
> + * include/dt-bindings/clock/axg-clkc.h. Only the clocks ids we don't want
> + * to expose, such as the internal muxes and dividers of composite clocks,
> + * will remain defined here.
> + */
> +#define CLKID_MPEG_SEL 8
> +#define CLKID_MPEG_DIV 9
> +#define CLKID_SD_EMMC_B_CLK0_SEL 61
> +#define CLKID_SD_EMMC_B_CLK0_DIV 62
> +#define CLKID_SD_EMMC_C_CLK0_SEL 63
> +#define CLKID_SD_EMMC_C_CLK0_DIV 64
> +
> +#define NR_CLKS 65
> +
> +/* include the CLKIDs that have been made part of the DT binding */
> +#include <dt-bindings/clock/axg-clkc.h>
> +
> +#endif /* __AXG_H */
>
Apart the devm_ioremap,
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply
* [PATCH v2] firmware: qcom: scm: Fix incorrect of_node_put call in scm_init
From: Jerome Forissier @ 2017-12-07 8:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206200601.GH4283@codeaurora.org>
On 12/06/2017 09:06 PM, Stephen Boyd wrote:
> On 12/06, Loys Ollivier wrote:
>> When using other platform architectures, in the init of the qcom_scm
>> driver, of_node_put is called on /firmware if no qcom dt is found.
>> This results in a kernel error: Bad of_node_put() on /firmware.
>>
>> The call to of_node_put from the qcom_scm init is unnecessary as
>> of_find_matching_node is calling it automatically.
>>
>> Remove this of_node_put().
>>
>> Fixes: d0f6fa7ba2d6 ("firmware: qcom: scm: Convert SCM to platform driver")
>> Signed-off-by: Loys Ollivier <lollivier@baylibre.com>
>> ---
>
> This still looks wrong. Especially if of_find_matching_node() is
> going to look for siblings of the /firmware node for the
> compatible string for scm device. Why do we check at all? Can't
> we just delete this and let of_platform_populate() take care of
> it? BTW, OP-TEE driver seems to have a similar problem.
https://lkml.org/lkml/2017/11/29/230
>
> ---8<----
>
> diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
> index af4c75217ea6..440d8f796faa 100644
> --- a/drivers/firmware/qcom_scm.c
> +++ b/drivers/firmware/qcom_scm.c
> @@ -626,23 +626,11 @@ static int __init qcom_scm_init(void)
> int ret;
>
> fw_np = of_find_node_by_name(NULL, "firmware");
> -
> if (!fw_np)
> - return -ENODEV;
> -
> - np = of_find_matching_node(fw_np, qcom_scm_dt_match);
> -
> - if (!np) {
> - of_node_put(fw_np);
> - return -ENODEV;
> - }
> -
> - of_node_put(np);
> + return 0;
>
> ret = of_platform_populate(fw_np, qcom_scm_dt_match, NULL, NULL);
> -
> of_node_put(fw_np);
> -
> if (ret)
> return ret;
>
>
^ permalink raw reply
* [PATCH 1/2] arm64: defconfig: enable MUSB HDRC along with Allwinner glue
From: Maxime Ripard @ 2017-12-07 8:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512582598-24806-1-git-send-email-jagan@amarulasolutions.com>
On Wed, Dec 06, 2017 at 11:19:58PM +0530, Jagan Teki wrote:
> Allwinner SoCs typically have a Mentor Graphics Inventra MUSB
> dual role controller for USB OTG. This is need for verifying
> gadget functions, so enable them by default.
>
> Tested 'otg' mode with mass storage function.
>
> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Applied, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] drm/sun4i: Fix uninitialized variables in vi layer
From: Maxime Ripard @ 2017-12-07 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206152603.25937-1-jernej.skrabec@siol.net>
Hi,
On Wed, Dec 06, 2017 at 04:26:03PM +0100, Jernej Skrabec wrote:
> min_scale and max_scale in sun8i_vi_layer_atomic_check() can be used
> without initialization.
>
> Fix that.
>
> Fixes: b862a648de3b (drm/sun4i: Add support for HW scaling to DE2)
>
> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
I've applied this, but your fixes tag was at the wrong format. You
should use the one documented here:
https://www.kernel.org/doc/html/latest/process/submitting-patches.html#using-reported-by-tested-by-reviewed-by-suggested-by-and-fixes
or you can even use the git option to generate it directly.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 3/8] mfd: axp20x: probe axp20x_adc driver for AXP813
From: Quentin Schulz @ 2017-12-07 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171205080855.arr7vlgnxoxmyedd@flea.lan>
Hi Maxime,
On 05/12/2017 09:08, Maxime Ripard wrote:
> On Mon, Dec 04, 2017 at 03:12:49PM +0100, Quentin Schulz wrote:
>> This makes the axp20x_adc driver probe with platform device id
>> "axp813-adc".
>>
>> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
>> ---
>> drivers/mfd/axp20x.c | 4 +++-
>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
>> index 2468b43..42e54d1 100644
>> --- a/drivers/mfd/axp20x.c
>> +++ b/drivers/mfd/axp20x.c
>> @@ -878,7 +878,9 @@ static struct mfd_cell axp813_cells[] = {
>> .resources = axp803_pek_resources,
>> }, {
>> .name = "axp20x-regulator",
>> - }
>> + }, {
>> + .name = "axp813-adc",
>> + },
>
> Any particular reason you're not adding it to the DT?
>
No, no particular reason. It's just the way it is currently for AXP209
and AXP22x so did the same for AXP813.
I'll add DT "support" in next version for all AXPs supported by this
driver. Or is it worthy of a small separate patch series?
Thanks,
Quentin
--
Quentin Schulz, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 3/8] mfd: axp20x: probe axp20x_adc driver for AXP813
From: Chen-Yu Tsai @ 2017-12-07 8:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2021a653-d01e-f46f-2438-0760f579e0dc@free-electrons.com>
On Thu, Dec 7, 2017 at 4:51 PM, Quentin Schulz
<quentin.schulz@free-electrons.com> wrote:
> Hi Maxime,
>
> On 05/12/2017 09:08, Maxime Ripard wrote:
>> On Mon, Dec 04, 2017 at 03:12:49PM +0100, Quentin Schulz wrote:
>>> This makes the axp20x_adc driver probe with platform device id
>>> "axp813-adc".
>>>
>>> Signed-off-by: Quentin Schulz <quentin.schulz@free-electrons.com>
>>> ---
>>> drivers/mfd/axp20x.c | 4 +++-
>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
>>> index 2468b43..42e54d1 100644
>>> --- a/drivers/mfd/axp20x.c
>>> +++ b/drivers/mfd/axp20x.c
>>> @@ -878,7 +878,9 @@ static struct mfd_cell axp813_cells[] = {
>>> .resources = axp803_pek_resources,
>>> }, {
>>> .name = "axp20x-regulator",
>>> - }
>>> + }, {
>>> + .name = "axp813-adc",
>>> + },
>>
>> Any particular reason you're not adding it to the DT?
>>
>
> No, no particular reason. It's just the way it is currently for AXP209
> and AXP22x so did the same for AXP813.
>
> I'll add DT "support" in next version for all AXPs supported by this
> driver. Or is it worthy of a small separate patch series?
IIRC there's no DT support because there's no need to reference
it in the device tree.
ChenYu
^ permalink raw reply
* [PATCH 0/2] Fixes for SW PAN
From: Vinayak Menon @ 2017-12-07 8:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206182657.GA27883@arm.com>
On 12/6/2017 11:56 PM, Will Deacon wrote:
> On Wed, Dec 06, 2017 at 06:18:01PM +0000, Catalin Marinas wrote:
>> On Wed, Dec 06, 2017 at 06:07:07PM +0000, Will Deacon wrote:
>>> On Wed, Dec 06, 2017 at 06:01:35PM +0000, Catalin Marinas wrote:
>>>> On Wed, Dec 06, 2017 at 05:56:42PM +0000, Will Deacon wrote:
>>>>> On Wed, Dec 06, 2017 at 11:01:46PM +0530, Vinayak Menon wrote:
>>>>>> On 12/6/2017 4:46 PM, Will Deacon wrote:
>>>>>>> After lots of collective head scratching in response to Vinayak's mail
>>>>>>> here:
>>>>>>>
>>>>>>> http://lists.infradead.org/pipermail/linux-arm-kernel/2017-December/545641.html
>>>>>>>
>>>>>>> It turns out that we have a problem with SW PAN and kernel threads, where
>>>>>>> the saved ttbr0 value for a kernel thread can be stale and subsequently
>>>>>>> inherited by other kernel threads over a fork.
>>>>>>>
>>>>>>> These two patches attempt to fix that. We've not be able to reproduce
>>>>>>> the exact failure reported above, but I added some assertions to the
>>>>>>> uaccess routines to check for discrepancies between the active_mm pgd
>>>>>>> and the saved ttbr0 value (ignoring the zero page) and these no longer
>>>>>>> fire with these changes, but do fire without them if EFI runtime services
>>>>>>> are enabled on my Seattle board.
>>>>>> Thanks Will. So these 2 patches fix the case of kthreads having a stale saved ttbr0. The callstack I had shared
>>>>>> in the original issue description was not of a kthread (its user task with PF_KTHREAD not set. The tsk->mm was
>>>>>> set to NULL by exit_mm I think). So do you think this could be a different problem ?
>>>>>> I had a look at the dumps again and what I see is that, the PA part of the saved ttbr0
>>>>>> (from thread_info) is not the same as the pa(tsk->active_mm->pgd). The PA derived from saved ttbr0 actually
>>>>>> points to a page which is "now" owned by slab.
>>>>> Having not been able to reproduce the failure you described, I can't give
>>>>> you a good answer to this.
> Looking at the code (again), if we context switch in do_exit after exit_mm,
> then the thread behaves an awful lot like a kernel thread: current->mm is
> NULL and we're in lazy TLB mode.
Yes, that could be the case.
I am going to try out these 2 patches and see if the issue gets resolved. It usually takes more
than a day to reproduce the problem. Will update you as soon as I get the results.
> Furthermore, that context switch will drop
> the last reference to the old mm and the pgd will finally be freed.
>
> So I think my patches will solve your case too because we'll call
> enter_lazy_tlb again when getting scheduled back in. If you have any way
> to test them, that would be great.
^ permalink raw reply
* [PATCH 8/9] ARM: dts: imx7-colibri: add MCP2515 CAN controller
From: Stefan Agner @ 2017-12-07 8:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171206153005.6144-8-stefan@agner.ch>
On 2017-12-06 16:30, Stefan Agner wrote:
> The Colibri Evaluation Carrier Board provides a MCP2515 CAN
> controller connected via SPI. Note that the i.MX 7 provides
> an internal CAN controller which is much better suited for CAN
> operations. Using the MCP2515 with a Colibri iMX7 module is
> mainly useful to test the SPI interface.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
> ---
> arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi | 25 +++++++++++++++++++++++++
> arch/arm/boot/dts/imx7-colibri.dtsi | 14 +++++++++++++-
> 2 files changed, 38 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> index 87c23b769a08..3d6c282dd258 100644
> --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi
> @@ -45,6 +45,13 @@
> stdout-path = "serial0:115200n8";
> };
>
> + /* fixed crystal dedicated to mpc258x */
> + clk16m: clk16m {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <16000000>;
> + };
> +
> panel: panel {
> compatible = "edt,et057090dhu";
> backlight = <&bl>;
> @@ -99,6 +106,24 @@
> status = "okay";
> };
>
> +&ecspi3 {
> + status = "okay";
> +
> + mcp258x0: mcp258x at 0 {
Just realized that this is somewhat bogus, this should be "mcp2515:
can at 0".
--
Stefan
> + compatible = "microchip,mcp2515";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_can_int>;
> + reg = <0>;
> + clocks = <&clk16m>;
> + interrupt-parent = <&gpio5>;
> + interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
> + spi-max-frequency = <10000000>;
> + vdd-supply = <®_3v3>;
> + xceiver-supply = <®_5v0>;
> + status = "okay";
> + };
> +};
> +
> &fec1 {
> status = "okay";
> };
> diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi
> b/arch/arm/boot/dts/imx7-colibri.dtsi
> index 689ff6822634..e1c6da0a65e4 100644
> --- a/arch/arm/boot/dts/imx7-colibri.dtsi
> +++ b/arch/arm/boot/dts/imx7-colibri.dtsi
> @@ -92,6 +92,13 @@
> cpu-supply = <®_DCDC2>;
> };
>
> +&ecspi3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi3 &pinctrl_ecspi3_cs>;
> + num-cs = <1>;
> + cs-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>;
> +};
> +
> &fec1 {
> pinctrl-names = "default";
> pinctrl-0 = <&pinctrl_enet1>;
> @@ -313,7 +320,6 @@
> fsl,pins = <
> MX7D_PAD_ENET1_RGMII_RD3__GPIO7_IO3 0x74 /* SODIMM 55 */
> MX7D_PAD_ENET1_RGMII_RD2__GPIO7_IO2 0x74 /* SODIMM 63 */
> - MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
> MX7D_PAD_SAI1_RX_SYNC__GPIO6_IO16 0x14 /* SODIMM 77 */
> MX7D_PAD_EPDC_DATA09__GPIO2_IO9 0x14 /* SODIMM 89 */
> MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x74 /* SODIMM 91 */
> @@ -400,6 +406,12 @@
> >;
> };
>
> + pinctrl_can_int: can-int-grp {
> + fsl,pins = <
> + MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0X14 /* SODIMM 73 */
> + >;
> + };
> +
> pinctrl_enet1: enet1grp {
> fsl,pins = <
> MX7D_PAD_ENET1_CRS__GPIO7_IO14 0x14
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