* [PATCH] KVM: arm/arm64: timer: Don't set irq as forwarded if no usable GIC
From: Andre Przywara @ 2017-12-07 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207114615.23950-1-marc.zyngier@arm.com>
Hi,
On 07/12/17 11:46, Marc Zyngier wrote:
> If we don't have a usable GIC, do not try to set the vcpu affinity
> as this is guaranteed to fail.
Yes, I can confirm that this fixes the problem. With this patch and a DT
advertising only a 4K GICC region size KVM still initializes, but denies
the in-kernel VGIC. kvmtool does not work anymore (expected), but QEMU
helps out with its userland GIC emulation.
> Reported-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> include/kvm/arm_arch_timer.h | 2 +-
> virt/kvm/arm/arch_timer.c | 13 ++++++++-----
> virt/kvm/arm/arm.c | 2 +-
> 3 files changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/include/kvm/arm_arch_timer.h b/include/kvm/arm_arch_timer.h
> index 01ee473517e2..5fa4fef257a4 100644
> --- a/include/kvm/arm_arch_timer.h
> +++ b/include/kvm/arm_arch_timer.h
> @@ -62,7 +62,7 @@ struct arch_timer_cpu {
> bool enabled;
> };
>
> -int kvm_timer_hyp_init(void);
> +int kvm_timer_hyp_init(bool);
> int kvm_timer_enable(struct kvm_vcpu *vcpu);
> int kvm_timer_vcpu_reset(struct kvm_vcpu *vcpu);
> void kvm_timer_vcpu_init(struct kvm_vcpu *vcpu);
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index 4151250ce8da..4804b5608013 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -726,7 +726,7 @@ static int kvm_timer_dying_cpu(unsigned int cpu)
> return 0;
> }
>
> -int kvm_timer_hyp_init(void)
> +int kvm_timer_hyp_init(bool has_gic)
> {
> struct arch_timer_kvm_info *info;
> int err;
> @@ -762,10 +762,13 @@ int kvm_timer_hyp_init(void)
> return err;
> }
>
> - err = irq_set_vcpu_affinity(host_vtimer_irq, kvm_get_running_vcpus());
> - if (err) {
> - kvm_err("kvm_arch_timer: error setting vcpu affinity\n");
> - goto out_free_irq;
> + if (has_gic) {
> + err = irq_set_vcpu_affinity(host_vtimer_irq,
> + kvm_get_running_vcpus());
> + if (err) {
> + kvm_err("kvm_arch_timer: error setting vcpu affinity\n");
> + goto out_free_irq;
> + }
> }
>
> kvm_info("virtual timer IRQ%d\n", host_vtimer_irq);
> diff --git a/virt/kvm/arm/arm.c b/virt/kvm/arm/arm.c
> index a67c106d73f5..d9df6d0731e6 100644
> --- a/virt/kvm/arm/arm.c
> +++ b/virt/kvm/arm/arm.c
> @@ -1323,7 +1323,7 @@ static int init_subsystems(void)
> /*
> * Init HYP architected timer support
> */
> - err = kvm_timer_hyp_init();
> + err = kvm_timer_hyp_init(vgic_present);
> if (err)
> goto out;
>
>
^ permalink raw reply
* [PATCH] KVM: arm/arm64: Fix HYP unmapping going off limits
From: Andre Przywara @ 2017-12-07 15:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207114545.23845-1-marc.zyngier@arm.com>
Hi,
On 07/12/17 11:45, Marc Zyngier wrote:
> When we unmap the HYP memory, we try to be clever and unmap one
> PGD at a time. If we start with a non-PGD aligned address and try
> to unmap a whole PGD, things go horribly wrong in unmap_hyp_range
> (addr and end can never match, and it all goes really badly as we
> keep incrementing pgd and parse random memory as page tables...).
>
> The obvious fix is to let unmap_hyp_range do what it does best,
> which is to iterate over a range.
>
> Cc: stable at vger.kernel.org
> Reported-by: Andre Przywara <andre.przywara@arm.com>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Thanks for the patch (and the hours of analysis that preceded it)!
So yes, that fixes the crash with 4.15-rc1 on my Midway (with the
original DT). As expected, KVM gets shuts down in the process, so no one
is at home under chardev 10/232 anymore - with this patch only, that is.
Tested-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre.
> ---
> virt/kvm/arm/mmu.c | 10 ++++------
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index b36945d49986..b4b69c2d1012 100644
> --- a/virt/kvm/arm/mmu.c
> +++ b/virt/kvm/arm/mmu.c
> @@ -509,8 +509,6 @@ static void unmap_hyp_range(pgd_t *pgdp, phys_addr_t start, u64 size)
> */
> void free_hyp_pgds(void)
> {
> - unsigned long addr;
> -
> mutex_lock(&kvm_hyp_pgd_mutex);
>
> if (boot_hyp_pgd) {
> @@ -521,10 +519,10 @@ void free_hyp_pgds(void)
>
> if (hyp_pgd) {
> unmap_hyp_range(hyp_pgd, hyp_idmap_start, PAGE_SIZE);
> - for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE)
> - unmap_hyp_range(hyp_pgd, kern_hyp_va(addr), PGDIR_SIZE);
> - for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
> - unmap_hyp_range(hyp_pgd, kern_hyp_va(addr), PGDIR_SIZE);
> + unmap_hyp_range(hyp_pgd, kern_hyp_va(PAGE_OFFSET),
> + (uintptr_t)high_memory - PAGE_OFFSET);
> + unmap_hyp_range(hyp_pgd, kern_hyp_va(VMALLOC_START),
> + VMALLOC_END - VMALLOC_START);
>
> free_pages((unsigned long)hyp_pgd, hyp_pgd_order);
> hyp_pgd = NULL;
>
^ permalink raw reply
* [PATCH net-next v2 6/8] net: phy: meson-gxl: leave CONFIG_A6 untouched
From: Jerome Brunet @ 2017-12-07 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207154943.GI24750@lunn.ch>
On Thu, 2017-12-07 at 16:49 +0100, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:13PM +0100, Jerome Brunet wrote:
> > The PHY performs just as well when left in its default configuration and
> > it makes senses because this poke gets reset just after init.
>
> The only thing which might speak against this, is some bootloader
> which sets something other than the default, and here we put it back
> to the value it should have. But if you say a reset will put it back
> to the default value anyway, this seems save.
I was worried about this too bu the bank also gets reset on power down and soft
reset, so we won't get bootloader value at this point
>
> Reviewed-by: Andrew Lunn <andrew@lunn.ch>
>
> Andrew
^ permalink raw reply
* [PATCH net-next v2 8/8] net: phy: meson-gxl: join the authors
From: Andrew Lunn @ 2017-12-07 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207142715.32578-9-jbrunet@baylibre.com>
On Thu, Dec 07, 2017 at 03:27:15PM +0100, Jerome Brunet wrote:
> Following previous changes, join the other authors of this driver and
> take the blame with them
:-)
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH net-next v2 7/8] net: phy: meson-gxl: add interrupt support
From: Andrew Lunn @ 2017-12-07 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207142715.32578-8-jbrunet@baylibre.com>
On Thu, Dec 07, 2017 at 03:27:14PM +0100, Jerome Brunet wrote:
> Enable interrupt support in meson-gxl PHY driver
Hi Jerome
Is it possible to implement did_interrupt()? That allows for shared
interrupts. It does however work fine without it, so long as the
interrupt is not shared.
Thanks
Andrew
^ permalink raw reply
* [RESEND PATCH v3 2/2] ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC
From: Kevin Hilman @ 2017-12-07 15:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9d28dcdf-655b-a843-1f21-24ebb1f27be3@amlogic.com>
On Wed, Dec 6, 2017 at 5:44 PM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> Hi Kevin
>
>
> On 12/07/17 04:18, Kevin Hilman wrote:
>> Yixun Lan <yixun.lan@amlogic.com> writes:
>>
>>> From: Xingyu Chen <xingyu.chen@amlogic.com>
>>>
>>> Add new pinctrl DT info for the Amlogic's Meson-AXG SoC.
>>>
>>> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
>>> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>> ---
>>> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 44 ++++++++++++++++++++++++++++++
>>> 1 file changed, 44 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> index 5fc33b76b91c..e0fb860e12c5 100644
>>> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
>>> @@ -9,6 +9,7 @@
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> #include <dt-bindings/clock/axg-clkc.h>
>>> #include <dt-bindings/clock/axg-aoclkc.h>
>>
>> This doesn't apply because this aoclkc.h header does not exist in
>> mainline.
>>
>> Kevin
>>
>
> this is due to I create the patch in serial sequence (first clk, then
> pinctrl), I probably will fix my work flow next time - to rebase all the
> patch separately on the -rc version
>
> but here, the pinctrl DT part has no dependency on DT clk patch..
> you could drop the above two #include and just apply the reset
>
> could you amend & apply this? or do you want me to send another updated
> version?
I prefer that you rebase (either on -rc or my v4.16/dt64 branch[1]) and resend.
Thanks,
Kevin
[1] https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git/log/?h=v4.16/dt64
^ permalink raw reply
* [PATCH v3 11/20] arm64: assembler: add macros to conditionally yield the NEON under PREEMPT
From: Ard Biesheuvel @ 2017-12-07 15:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu-Otcg4UxhJA44PbbYamBJd26Be+YsSUQUaB+qy9owzvQ@mail.gmail.com>
On 7 December 2017 at 15:47, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 7 December 2017 at 14:50, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
>> On 7 December 2017 at 14:39, Dave Martin <Dave.Martin@arm.com> wrote:
>>> On Wed, Dec 06, 2017 at 07:43:37PM +0000, Ard Biesheuvel wrote:
>>>> Add support macros to conditionally yield the NEON (and thus the CPU)
>>>> that may be called from the assembler code.
>>>>
>>>> In some cases, yielding the NEON involves saving and restoring a non
>>>> trivial amount of context (especially in the CRC folding algorithms),
>>>> and so the macro is split into three, and the code in between is only
>>>> executed when the yield path is taken, allowing the context to be preserved.
>>>> The third macro takes an optional label argument that marks the resume
>>>> path after a yield has been performed.
>>>>
>>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>>> ---
>>>> arch/arm64/include/asm/assembler.h | 51 ++++++++++++++++++++
>>>> 1 file changed, 51 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
>>>> index 5f61487e9f93..c54e408fd5a7 100644
>>>> --- a/arch/arm64/include/asm/assembler.h
>>>> +++ b/arch/arm64/include/asm/assembler.h
>>>> @@ -572,4 +572,55 @@ alternative_else_nop_endif
>>>> #endif
>>>> .endm
>>>>
>>>> +/*
>>>> + * Check whether to yield to another runnable task from kernel mode NEON code
>>>> + * (which runs with preemption disabled).
>>>> + *
>>>> + * if_will_cond_yield_neon
>>>> + * // pre-yield patchup code
>>>> + * do_cond_yield_neon
>>>> + * // post-yield patchup code
>>>> + * endif_yield_neon
>>>
>>> ^ Mention the lbl argument?
>>>
>>
>> Yep will do
>>
>>>> + *
>>>> + * - Check whether the preempt count is exactly 1, in which case disabling
>>>
>>> enabling ^
>>>
>>>> + * preemption once will make the task preemptible. If this is not the case,
>>>> + * yielding is pointless.
>>>> + * - Check whether TIF_NEED_RESCHED is set, and if so, disable and re-enable
>>>> + * kernel mode NEON (which will trigger a reschedule), and branch to the
>>>> + * yield fixup code.
>>>
>>> Mention that neither patchup sequence is allowed to use section-changing
>>> directives?
>>>
>>> For example:
>>>
>>> if_will_cond_yield_neon
>>> // some code
>>>
>>> .pushsection .rodata, "a"
>>> foo: .quad // some literal data for some reason
>>> .popsection
>>>
>>> // some code
>>> do_cond_yield_neon
>>>
>>> is not safe, because .previous is now .rodata.
>>>
>>
>> Are you sure this is true?
>>
>> The gas info page for .previous tells me
>>
>> In terms of the section stack, this directive swaps the current
>> section with the top section on the section stack.
>>
>> and it seems to me that .rodata is no longer on the section stack
>> after .popsection. In that sense, push/pop should be safe, but
>> section/subsection/previous is not (I think). So yes, let's put a note
>> in to mention that section directives are unsupported.
>>
>>> (You could protect against this with
>>> .pushsection .text; .previous; .subsection 1; // ...
>>> .popsection
>>> but it may be overkill.)
>>>
>>>> + *
>>>> + * This macro sequence clobbers x0, x1 and the flags register unconditionally,
>>>> + * and may clobber x2 .. x18 if the yield path is taken.
>>>> + */
>>>> +
>>>> + .macro cond_yield_neon, lbl
>>>> + if_will_cond_yield_neon
>>>> + do_cond_yield_neon
>>>> + endif_yield_neon \lbl
>>>> + .endm
>>>> +
>>>> + .macro if_will_cond_yield_neon
>>>> +#ifdef CONFIG_PREEMPT
>>>> + get_thread_info x0
>>>> + ldr w1, [x0, #TSK_TI_PREEMPT]
>>>> + ldr x0, [x0, #TSK_TI_FLAGS]
>>>> + cmp w1, #1 // == PREEMPT_OFFSET
>>>
>>> Can we at least drop a BUILD_BUG_ON() somewhere to check this?
>>>
>>> Maybe in kernel_neon_begin() since this is intimately kernel-mode NEON
>>> related.
>>>
>>
>> Sure.
>>
>
> I only just understood your asm-offsets remark earlier. I wasn't aware
> that it allows exposing random constants as well (although it is
> fairly obvious now that I do). So I will expose PREEMPT_OFFSET rather
> than open code it
>
Of course, I mean 'arbitrary' not 'random' (like 6666)
^ permalink raw reply
* [PATCH net-next v2 3/8] net: phy: meson-gxl: add read and write helpers for bank registers
From: Jerome Brunet @ 2017-12-07 15:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207154610.GG24750@lunn.ch>
On Thu, 2017-12-07 at 16:46 +0100, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:10PM +0100, Jerome Brunet wrote:
> > Add read and write helpers to manipulate banked registers on this PHY
> > This helps clarify the settings applied to these registers in the init
> > function and upcoming changes.
> >
> > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> > ---
> > drivers/net/phy/meson-gxl.c | 103 ++++++++++++++++++++++++++++-------------
> > ---
> > 1 file changed, 67 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
> > index d82aa8cea401..05054770aefb 100644
> > --- a/drivers/net/phy/meson-gxl.c
> > +++ b/drivers/net/phy/meson-gxl.c
> > @@ -45,11 +45,13 @@
> > #define FR_PLL_DIV0 0x1c
> > #define FR_PLL_DIV1 0x1d
> >
> > -static int meson_gxl_config_init(struct phy_device *phydev)
> > +static int meson_gxl_open_banks(struct phy_device *phydev)
>
> Hi Jerome
>
> Does the word bank come from the datasheet? Most of the phy drives use
> page instead.
>
> Also, we have discovered a race condition which affects drivers using
> pages, which can lead to corruption of registers. At some point, i
> expect we will be adding helpers to access paged registers, which do
> the right thing with respect to locks.
>
> So it would be nice if you used the work page, not bank.
Banks actually comes from the datasheet, Yes.
I don't mind renaming it but I would be making things up. As you wish ?
Does the usual pages comes with this weird toggle thing to open the access ?
Would we able to use these generic helpers with our this kind of quirks ?
>
> Thanks
>
> Andrew
^ permalink raw reply
* [PATCH net-next v2 6/8] net: phy: meson-gxl: leave CONFIG_A6 untouched
From: Andrew Lunn @ 2017-12-07 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207142715.32578-7-jbrunet@baylibre.com>
On Thu, Dec 07, 2017 at 03:27:13PM +0100, Jerome Brunet wrote:
> The PHY performs just as well when left in its default configuration and
> it makes senses because this poke gets reset just after init.
The only thing which might speak against this, is some bootloader
which sets something other than the default, and here we put it back
to the value it should have. But if you say a reset will put it back
to the default value anyway, this seems save.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH net-next v2 3/8] net: phy: meson-gxl: add read and write helpers for bank registers
From: Neil Armstrong @ 2017-12-07 15:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207154610.GG24750@lunn.ch>
On 07/12/2017 16:46, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:10PM +0100, Jerome Brunet wrote:
>> Add read and write helpers to manipulate banked registers on this PHY
>> This helps clarify the settings applied to these registers in the init
>> function and upcoming changes.
>>
>> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
>> ---
>> drivers/net/phy/meson-gxl.c | 103 ++++++++++++++++++++++++++++----------------
>> 1 file changed, 67 insertions(+), 36 deletions(-)
>>
>> diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
>> index d82aa8cea401..05054770aefb 100644
>> --- a/drivers/net/phy/meson-gxl.c
>> +++ b/drivers/net/phy/meson-gxl.c
>> @@ -45,11 +45,13 @@
>> #define FR_PLL_DIV0 0x1c
>> #define FR_PLL_DIV1 0x1d
>>
>> -static int meson_gxl_config_init(struct phy_device *phydev)
>> +static int meson_gxl_open_banks(struct phy_device *phydev)
>
> Hi Jerome
>
> Does the word bank come from the datasheet? Most of the phy drives use
> page instead.
Yes, it's explicitly described as banks in the datasheet.
Neil
>
> Also, we have discovered a race condition which affects drivers using
> pages, which can lead to corruption of registers. At some point, i
> expect we will be adding helpers to access paged registers, which do
> the right thing with respect to locks.
>
> So it would be nice if you used the work page, not bank.
>
> Thanks
>
> Andrew
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
^ permalink raw reply
* [PATCH v3 11/20] arm64: assembler: add macros to conditionally yield the NEON under PREEMPT
From: Ard Biesheuvel @ 2017-12-07 15:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu8N6w3+VFpF3kq-qg9Gij=4VbtQqu+yfvfA67p2kWaRLg@mail.gmail.com>
On 7 December 2017 at 14:50, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 7 December 2017 at 14:39, Dave Martin <Dave.Martin@arm.com> wrote:
>> On Wed, Dec 06, 2017 at 07:43:37PM +0000, Ard Biesheuvel wrote:
>>> Add support macros to conditionally yield the NEON (and thus the CPU)
>>> that may be called from the assembler code.
>>>
>>> In some cases, yielding the NEON involves saving and restoring a non
>>> trivial amount of context (especially in the CRC folding algorithms),
>>> and so the macro is split into three, and the code in between is only
>>> executed when the yield path is taken, allowing the context to be preserved.
>>> The third macro takes an optional label argument that marks the resume
>>> path after a yield has been performed.
>>>
>>> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>>> ---
>>> arch/arm64/include/asm/assembler.h | 51 ++++++++++++++++++++
>>> 1 file changed, 51 insertions(+)
>>>
>>> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
>>> index 5f61487e9f93..c54e408fd5a7 100644
>>> --- a/arch/arm64/include/asm/assembler.h
>>> +++ b/arch/arm64/include/asm/assembler.h
>>> @@ -572,4 +572,55 @@ alternative_else_nop_endif
>>> #endif
>>> .endm
>>>
>>> +/*
>>> + * Check whether to yield to another runnable task from kernel mode NEON code
>>> + * (which runs with preemption disabled).
>>> + *
>>> + * if_will_cond_yield_neon
>>> + * // pre-yield patchup code
>>> + * do_cond_yield_neon
>>> + * // post-yield patchup code
>>> + * endif_yield_neon
>>
>> ^ Mention the lbl argument?
>>
>
> Yep will do
>
>>> + *
>>> + * - Check whether the preempt count is exactly 1, in which case disabling
>>
>> enabling ^
>>
>>> + * preemption once will make the task preemptible. If this is not the case,
>>> + * yielding is pointless.
>>> + * - Check whether TIF_NEED_RESCHED is set, and if so, disable and re-enable
>>> + * kernel mode NEON (which will trigger a reschedule), and branch to the
>>> + * yield fixup code.
>>
>> Mention that neither patchup sequence is allowed to use section-changing
>> directives?
>>
>> For example:
>>
>> if_will_cond_yield_neon
>> // some code
>>
>> .pushsection .rodata, "a"
>> foo: .quad // some literal data for some reason
>> .popsection
>>
>> // some code
>> do_cond_yield_neon
>>
>> is not safe, because .previous is now .rodata.
>>
>
> Are you sure this is true?
>
> The gas info page for .previous tells me
>
> In terms of the section stack, this directive swaps the current
> section with the top section on the section stack.
>
> and it seems to me that .rodata is no longer on the section stack
> after .popsection. In that sense, push/pop should be safe, but
> section/subsection/previous is not (I think). So yes, let's put a note
> in to mention that section directives are unsupported.
>
>> (You could protect against this with
>> .pushsection .text; .previous; .subsection 1; // ...
>> .popsection
>> but it may be overkill.)
>>
>>> + *
>>> + * This macro sequence clobbers x0, x1 and the flags register unconditionally,
>>> + * and may clobber x2 .. x18 if the yield path is taken.
>>> + */
>>> +
>>> + .macro cond_yield_neon, lbl
>>> + if_will_cond_yield_neon
>>> + do_cond_yield_neon
>>> + endif_yield_neon \lbl
>>> + .endm
>>> +
>>> + .macro if_will_cond_yield_neon
>>> +#ifdef CONFIG_PREEMPT
>>> + get_thread_info x0
>>> + ldr w1, [x0, #TSK_TI_PREEMPT]
>>> + ldr x0, [x0, #TSK_TI_FLAGS]
>>> + cmp w1, #1 // == PREEMPT_OFFSET
>>
>> Can we at least drop a BUILD_BUG_ON() somewhere to check this?
>>
>> Maybe in kernel_neon_begin() since this is intimately kernel-mode NEON
>> related.
>>
>
> Sure.
>
I only just understood your asm-offsets remark earlier. I wasn't aware
that it allows exposing random constants as well (although it is
fairly obvious now that I do). So I will expose PREEMPT_OFFSET rather
than open code it
>>> + csel x0, x0, xzr, eq
>>> + tbnz x0, #TIF_NEED_RESCHED, 5555f // needs rescheduling?
>>> +#endif
>>
>> A comment that we will fall through to 6666f here may be helpful.
>>
>
> Indeed. Will add that.
>
>>> + .subsection 1
>>> +5555:
>>> + .endm
>>> +
>>> + .macro do_cond_yield_neon
>>> + bl kernel_neon_end
>>> + bl kernel_neon_begin
>>> + .endm
>>> +
>>> + .macro endif_yield_neon, lbl=6666f
>>> + b \lbl
>>> + .previous
>>> +6666:
>>
>> Could have slightly more random "random" labels here, but otherwise
>> it looks ok to me.
>>
>
> Which number did you have in mind that is more random than 6666? :-)
>
>> I might go through and replace all the random labels with something
>> more robust sometime, but I've never been sure it was worth the
>> effort...
>>
>
> I guess we could invent all kinds of elaborate schemes but as you say,
> having 4 digit numbers and grep'ing the source before you add a new
> one has been working fine so far, so I don't think it should be a
> priority.
^ permalink raw reply
* [PATCH v2 07/10] arm64: dts: qcom: msm8916: drop remaining unused pinconfs
From: Rishi Bhattacharya @ 2017-12-07 15:46 UTC (permalink / raw)
To: linux-arm-kernel
^ permalink raw reply
* [PATCH net-next v2 4/8] net: phy: meson-gxl: use genphy_config_init
From: Andrew Lunn @ 2017-12-07 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207142715.32578-5-jbrunet@baylibre.com>
On Thu, Dec 07, 2017 at 03:27:11PM +0100, Jerome Brunet wrote:
> Use the generic init function to populate some of the phydev
> structure fields
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH net-next v2 3/8] net: phy: meson-gxl: add read and write helpers for bank registers
From: Andrew Lunn @ 2017-12-07 15:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207142715.32578-4-jbrunet@baylibre.com>
On Thu, Dec 07, 2017 at 03:27:10PM +0100, Jerome Brunet wrote:
> Add read and write helpers to manipulate banked registers on this PHY
> This helps clarify the settings applied to these registers in the init
> function and upcoming changes.
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
> ---
> drivers/net/phy/meson-gxl.c | 103 ++++++++++++++++++++++++++++----------------
> 1 file changed, 67 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/net/phy/meson-gxl.c b/drivers/net/phy/meson-gxl.c
> index d82aa8cea401..05054770aefb 100644
> --- a/drivers/net/phy/meson-gxl.c
> +++ b/drivers/net/phy/meson-gxl.c
> @@ -45,11 +45,13 @@
> #define FR_PLL_DIV0 0x1c
> #define FR_PLL_DIV1 0x1d
>
> -static int meson_gxl_config_init(struct phy_device *phydev)
> +static int meson_gxl_open_banks(struct phy_device *phydev)
Hi Jerome
Does the word bank come from the datasheet? Most of the phy drives use
page instead.
Also, we have discovered a race condition which affects drivers using
pages, which can lead to corruption of registers. At some point, i
expect we will be adding helpers to access paged registers, which do
the right thing with respect to locks.
So it would be nice if you used the work page, not bank.
Thanks
Andrew
^ permalink raw reply
* [PATCH] perf: qcom_l2_pmu: don't allow guest access
From: Leeder, Neil @ 2017-12-07 15:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207133812.GG31900@arm.com>
On 12/7/2017 8:38 AM, Will Deacon wrote:
> On Wed, Dec 06, 2017 at 04:19:24PM -0500, Leeder, Neil wrote:
>> On 12/6/2017 11:11 AM, Mark Rutland wrote:
>>> On Wed, Dec 06, 2017 at 10:55:33AM -0500, Neil Leeder wrote:
>>>> Guests cannot access IMPDEF system registers, which are used
>>>> by this driver. Disable the driver if it's running in a guest VM.
>>>>
>>>> Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
>>>> ---
>>>> drivers/perf/qcom_l2_pmu.c | 4 ++++
>>>> 1 file changed, 4 insertions(+)
>>>
>>> I'm a little confused by this. Why is this hypervisor providing a
>>> QCOM8130 device to the guest that it cannot use?
>>>
>>> Could you elaborate on what's going on?
>>>
>>
>> While there's an argument that the guest shouldn't be loading the driver
>> in the first place, we can't control everyone's guest configuration or what
>> their hypervisor does.
>
> Ok, but why is the hypervisor advertising a device that effectively doesn't
> exist? Most drivers trust the firmware tables they are given, so this makes
> it sound like we should start annotating all drivers for devices that we
> don't expect to see in a guest with is_hyp_mode_available() checks.
>
> That doesn't feel quite right to me.
Hi Will,
I suspect that most mis-configured drivers don't fail until they're used, or are
otherwise Mostly Harmless. The problem here is that this driver uses IMPDEF system
registers in its init, and I'd guess only a minority of drivers do that. So it
crashed the kernel with an illegal instruction on boot. I'm trying to be a good
citizen here and not allow my driver to stop a kernel from booting because someone
misconfigured something out of my control.
Neil
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm Technologies Inc.
Qualcomm Technologies, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH net-next v2 5/8] net: phy: meson-gxl: detect LPA corruption
From: Jerome Brunet @ 2017-12-07 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207153403.GE24750@lunn.ch>
On Thu, 2017-12-07 at 16:34 +0100, Andrew Lunn wrote:
> On Thu, Dec 07, 2017 at 03:27:12PM +0100, Jerome Brunet wrote:
> > The purpose of this change is to fix the incorrect detection of the link
> > partner (LP) advertised capabilities which sometimes happens with this PHY
> > (roughly 1 time in a dozen)
>
> Hi Jerome
>
> Since this is a real fix, please send it alone. Base it on net, not
> net-next. David will then get it applied to stable, so it will be
> backported.
I hesitated on this. For this fix to be "not too ugly" I need at least the
helper functions (patch 1 to 3) ... which are not really fixes.
Would it be Ok if send patches 1 to 5 to net ?
and 6 to 8 separately on net-next ?
>
> Thanks
> Andrew
^ permalink raw reply
* [PATCH net-next v2 1/8] net: phy: meson-gxl: check phy_write return value
From: Andrew Lunn @ 2017-12-07 15:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207142715.32578-2-jbrunet@baylibre.com>
On Thu, Dec 07, 2017 at 03:27:08PM +0100, Jerome Brunet wrote:
> Always check phy_write return values. Better to be safe than sorry
>
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH net-next v2 5/8] net: phy: meson-gxl: detect LPA corruption
From: Andrew Lunn @ 2017-12-07 15:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207142715.32578-6-jbrunet@baylibre.com>
On Thu, Dec 07, 2017 at 03:27:12PM +0100, Jerome Brunet wrote:
> The purpose of this change is to fix the incorrect detection of the link
> partner (LP) advertised capabilities which sometimes happens with this PHY
> (roughly 1 time in a dozen)
Hi Jerome
Since this is a real fix, please send it alone. Base it on net, not
net-next. David will then get it applied to stable, so it will be
backported.
Thanks
Andrew
^ permalink raw reply
* [PATCH v8 4/6] clocksource: stm32: only use 32 bits timers
From: Daniel Lezcano @ 2017-12-07 15:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1510649563-22975-5-git-send-email-benjamin.gaignard@linaro.org>
On 14/11/2017 09:52, Benjamin Gaignard wrote:
> The clock driving counters is at 90MHz so the maximum period
> for 16 bis counters is around 750 ms which is a short period
> for a clocksource.
Isn't it 728us ?
> For 32 bits counters this period is close
> 47 secondes which is more acceptable.
>
> This patch remove 16 bits counters support and makes sure that
> they won't be probed anymore.
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org>
> ---
> drivers/clocksource/timer-stm32.c | 26 ++++++++++++--------------
> 1 file changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/clocksource/timer-stm32.c b/drivers/clocksource/timer-stm32.c
> index ae41a19..8173bcf 100644
> --- a/drivers/clocksource/timer-stm32.c
> +++ b/drivers/clocksource/timer-stm32.c
> @@ -83,9 +83,9 @@ static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
> static int __init stm32_clockevent_init(struct device_node *node)
> {
> struct reset_control *rstc;
> - unsigned long max_delta;
> - int ret, bits, prescaler = 1;
> + unsigned long max_arr;
> struct timer_of *to;
> + int ret;
>
> to = kzalloc(sizeof(*to), GFP_KERNEL);
> if (!to)
> @@ -115,29 +115,27 @@ static int __init stm32_clockevent_init(struct device_node *node)
>
> /* Detect whether the timer is 16 or 32 bits */
> writel_relaxed(~0U, timer_of_base(to) + TIM_ARR);
> - max_delta = readl_relaxed(timer_of_base(to) + TIM_ARR);
> - if (max_delta == ~0U) {
> - prescaler = 1;
> - bits = 32;
> - } else {
> - prescaler = 1024;
> - bits = 16;
> + max_arr = readl_relaxed(timer_of_base(to) + TIM_ARR);
> + if (max_arr != ~0U) {
> + pr_err("32 bits timer is needed\n");
> + ret = -EINVAL;
> + goto deinit;
> }
> +
> writel_relaxed(0, timer_of_base(to) + TIM_ARR);
>
> - writel_relaxed(prescaler - 1, timer_of_base(to) + TIM_PSC);
> + writel_relaxed(0, timer_of_base(to) + TIM_PSC);
> writel_relaxed(TIM_EGR_UG, timer_of_base(to) + TIM_EGR);
> writel_relaxed(TIM_DIER_UIE, timer_of_base(to) + TIM_DIER);
> writel_relaxed(0, timer_of_base(to) + TIM_SR);
>
> clockevents_config_and_register(&to->clkevt,
> - timer_of_period(to), MIN_DELTA, max_delta);
> -
> - pr_info("%pOF: STM32 clockevent driver initialized (%d bits)\n",
> - node, bits);
> + timer_of_period(to), MIN_DELTA, ~0U);
>
> return 0;
>
> +deinit:
> + timer_of_exit(to);
> err:
> kfree(to);
> return ret;
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH V6 4/7] OF: properties: Implement get_match_data() callback
From: Lothar Waßmann @ 2017-12-07 15:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <def8e351-bc2d-7adc-fdc5-362b365302a8@codeaurora.org>
Hi,
On Thu, 7 Dec 2017 09:45:31 -0500 Sinan Kaya wrote:
> On 12/7/2017 8:10 AM, Lothar Wa?mann wrote:
> >> +void *of_fwnode_get_match_data(const struct fwnode_handle *fwnode,
> >> + struct device *dev)
> > Shouldn't this be 'const void *of_fwnode_get_match_data
>
> OF keeps the driver data as a (const void*) internally. ACPI keeps the
> driver data as kernel_ulong_t in struct acpi_device_id.
>
> I tried to find the middle ground here by converting output to void*
> but not keeping const.
>
It should be no problem to cast a (const void *) to an unsigned long
data type (without const qualifier).
Lothar Wa?mann
^ permalink raw reply
* [PATCH v2 10/10] arm64: dts: qcom: msm8916: add nodes for i2c1, i2c3, i2c5
From: Damien Riegel @ 2017-12-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207151942.5805-1-damien.riegel@savoirfairelinux.com>
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
---
Changes in v2:
- Reworded commit title
- Changed size to 0x500
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 48 ++++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 42 ++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8916.dtsi | 45 ++++++++++++++++++++++++++++
3 files changed, 135 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 53c1ddd281a4..11305015ba0b 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -630,6 +630,22 @@
};
};
+&i2c1_default {
+ pinconf {
+ pins = "gpio2", "gpio3";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&i2c1_sleep {
+ pinconf {
+ pins = "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
&i2c2_default {
pinconf {
pins = "gpio6", "gpio7";
@@ -646,6 +662,22 @@
};
};
+&i2c3_default {
+ pinconf {
+ pins = "gpio10", "gpio11";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&i2c3_sleep {
+ pinconf {
+ pins = "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
&i2c4_default {
pinconf {
pins = "gpio14", "gpio15";
@@ -662,6 +694,22 @@
};
};
+&i2c5_default {
+ pinconf {
+ pins = "gpio18", "gpio19";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&i2c5_sleep {
+ pinconf {
+ pins = "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
&i2c6_default {
pinconf {
pins = "gpio22", "gpio23";
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 7704ddecb6c4..44e68860fc8c 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -152,6 +152,20 @@
};
};
+ i2c1_default: i2c1_default {
+ pinmux {
+ function = "blsp_i2c1";
+ pins = "gpio2", "gpio3";
+ };
+ };
+
+ i2c1_sleep: i2c1_sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio2", "gpio3";
+ };
+ };
+
i2c2_default: i2c2_default {
pinmux {
function = "blsp_i2c2";
@@ -166,6 +180,20 @@
};
};
+ i2c3_default: i2c3_default {
+ pinmux {
+ function = "blsp_i2c3";
+ pins = "gpio10", "gpio11";
+ };
+ };
+
+ i2c3_sleep: i2c3_sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio10", "gpio11";
+ };
+ };
+
i2c4_default: i2c4_default {
pinmux {
function = "blsp_i2c4";
@@ -180,6 +208,20 @@
};
};
+ i2c5_default: i2c5_default {
+ pinmux {
+ function = "blsp_i2c5";
+ pins = "gpio18", "gpio19";
+ };
+ };
+
+ i2c5_sleep: i2c5_sleep {
+ pinmux {
+ function = "gpio";
+ pins = "gpio18", "gpio19";
+ };
+ };
+
i2c6_default: i2c6_default {
pinmux {
function = "blsp_i2c6";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index ac440f287633..7478c7337995 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -455,6 +455,21 @@
status = "disabled";
};
+ blsp_i2c1: i2c at 78b5000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b5000 0x500>;
+ interrupts = <GIC_SPI 95 0>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c1_default>;
+ pinctrl-1 = <&i2c1_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp_i2c2: i2c at 78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>;
@@ -470,6 +485,21 @@
status = "disabled";
};
+ blsp_i2c3: i2c at 78b7000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b7000 0x500>;
+ interrupts = <GIC_SPI 97 0>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c3_default>;
+ pinctrl-1 = <&i2c3_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp_i2c4: i2c at 78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x500>;
@@ -485,6 +515,21 @@
status = "disabled";
};
+ blsp_i2c5: i2c at 78b9000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x078b9000 0x500>;
+ interrupts = <GIC_SPI 99 0>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&i2c5_default>;
+ pinctrl-1 = <&i2c5_sleep>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
blsp_i2c6: i2c at 78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078ba000 0x500>;
--
2.15.0
^ permalink raw reply related
* [PATCH v2 09/10] arm64: dts: qcom: msm8916: normalize I2C and SPI nodes
From: Damien Riegel @ 2017-12-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207151942.5805-1-damien.riegel@savoirfairelinux.com>
The QUP core can be used either for I2C or SPI, so the same IP is mapped
by a driver or the other. SPI bindings use a leading 0 for the start
address and a size of 0x600, I2C bindings don't have the leading 0 and
have a size 0x1000.
To make them more similar, add the leading 0 to I2C bindings and changes
the size to 0x500 for all of them, as this is the actual size of these
blocks. Also align the second entry of the clocks array.
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
---
Changes in v2:
- Set size to 0x500
arch/arm64/boot/dts/qcom/msm8916.dtsi | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index e16ba8334518..ac440f287633 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -355,7 +355,7 @@
blsp_spi1: spi at 78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x078b5000 0x600>;
+ reg = <0x078b5000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -372,7 +372,7 @@
blsp_spi2: spi at 78b6000 {
compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x078b6000 0x600>;
+ reg = <0x078b6000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -389,7 +389,7 @@
blsp_spi3: spi at 78b7000 {
compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x078b7000 0x600>;
+ reg = <0x078b7000 0x500>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -406,7 +406,7 @@
blsp_spi4: spi at 78b8000 {
compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x078b8000 0x600>;
+ reg = <0x078b8000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -423,7 +423,7 @@
blsp_spi5: spi at 78b9000 {
compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x078b9000 0x600>;
+ reg = <0x078b9000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -440,7 +440,7 @@
blsp_spi6: spi at 78ba000 {
compatible = "qcom,spi-qup-v2.2.1";
- reg = <0x078ba000 0x600>;
+ reg = <0x078ba000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -457,10 +457,10 @@
blsp_i2c2: i2c at 78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x78b6000 0x1000>;
+ reg = <0x078b6000 0x500>;
interrupts = <GIC_SPI 96 0>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_default>;
@@ -472,10 +472,10 @@
blsp_i2c4: i2c at 78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x78b8000 0x1000>;
+ reg = <0x078b8000 0x500>;
interrupts = <GIC_SPI 98 0>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_default>;
@@ -487,10 +487,10 @@
blsp_i2c6: i2c at 78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0x78ba000 0x1000>;
+ reg = <0x078ba000 0x500>;
interrupts = <GIC_SPI 100 0>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
+ <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
--
2.15.0
^ permalink raw reply related
* [PATCH v2 08/10] arm64: dts: qcom: msm8916-pins: move sdhc2 cd node with its siblings
From: Damien Riegel @ 2017-12-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207151942.5805-1-damien.riegel@savoirfairelinux.com>
Nodes relative to the first sdhc node were interlaced with node of the
second sdhc. Move sdhc2_cd_pin with its siblings to prevent that. Also
rename the grouping node from sdhc2_cd_pin to pmx_sdc2_cd_pin, as
"pmx_sdc" is the prefix used by other nodes.
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
---
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 30 +++++++++++++++---------------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index c79301f204b7..7704ddecb6c4 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -194,21 +194,6 @@
};
};
- sdhc2_cd_pin {
- sdc2_cd_on: cd_on {
- pinmux {
- function = "gpio";
- pins = "gpio38";
- };
- };
- sdc2_cd_off: cd_off {
- pinmux {
- function = "gpio";
- pins = "gpio38";
- };
- };
- };
-
pmx_sdc1_clk {
sdc1_clk_on: clk_on {
pinmux {
@@ -287,6 +272,21 @@
};
};
+ pmx_sdc2_cd_pin {
+ sdc2_cd_on: cd_on {
+ pinmux {
+ function = "gpio";
+ pins = "gpio38";
+ };
+ };
+ sdc2_cd_off: cd_off {
+ pinmux {
+ function = "gpio";
+ pins = "gpio38";
+ };
+ };
+ };
+
cdc-pdm-lines {
cdc_pdm_lines_act: pdm_lines_on {
pinmux {
--
2.15.0
^ permalink raw reply related
* [PATCH v2 07/10] arm64: dts: qcom: msm8916: drop remaining unused pinconfs
From: Damien Riegel @ 2017-12-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207151942.5805-1-damien.riegel@savoirfairelinux.com>
This commit drops pin configs that cannot be moved to board files as
no boards use them.
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
---
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 33 ------------------------------
1 file changed, 33 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 0790232c4654..c79301f204b7 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -311,26 +311,13 @@
pins = "gpio113", "gpio114", "gpio115",
"gpio116";
};
- pinconf {
- pins = "gpio113", "gpio114", "gpio115",
- "gpio116";
- drive-strength = <8>;
- bias-pull-none;
- };
};
-
ext_pri_tlmm_lines_sus: ext_pa_off {
pinmux {
function = "pri_mi2s";
pins = "gpio113", "gpio114", "gpio115",
"gpio116";
};
- pinconf {
- pins = "gpio113", "gpio114", "gpio115",
- "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
};
};
@@ -340,23 +327,12 @@
function = "pri_mi2s_ws";
pins = "gpio110";
};
- pinconf {
- pins = "gpio110";
- drive-strength = <8>;
- bias-pull-none;
- };
};
-
ext_pri_ws_sus: ext_pa_off {
pinmux {
function = "pri_mi2s_ws";
pins = "gpio110";
};
- pinconf {
- pins = "gpio110";
- drive-strength = <2>;
- bias-disable;
- };
};
};
@@ -403,10 +379,6 @@
function = "dmic0_data";
pins = "gpio1";
};
- pinconf {
- pins = "gpio0", "gpio1";
- drive-strength = <8>;
- };
};
cdc_dmic_lines_sus: dmic_lines_off {
pinmux_dmic0_clk {
@@ -417,11 +389,6 @@
function = "dmic0_data";
pins = "gpio1";
};
- pinconf {
- pins = "gpio0", "gpio1";
- drive-strength = <2>;
- bias-disable;
- };
};
};
--
2.15.0
^ permalink raw reply related
* [PATCH v2 06/10] arm64: dts: qcom: msm8916: move pinconfs to board files
From: Damien Riegel @ 2017-12-07 15:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207151942.5805-1-damien.riegel@savoirfairelinux.com>
Following a suggestion from Bjorn Andersson [1], this commit moves
electrical specifications which were defined in mms8916-pins.dtsi to
board files, where they actually belong.
Pinmuxing is kept in the platform file because there are no alternative
pins on which all these functions could be routed, so this part is
indeed common to all boards using this SoC.
[1] https://www.spinics.net/lists/devicetree/msg201764.html
Signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com>
Suggested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi | 386 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi | 17 ++
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 258 -------------------
3 files changed, 403 insertions(+), 258 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
index 981450f50e10..53c1ddd281a4 100644
--- a/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
+++ b/arch/arm64/boot/dts/qcom/apq8016-sbc.dtsi
@@ -544,6 +544,384 @@
};
};
+&blsp1_uart1_default {
+ pinconf {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&blsp1_uart1_sleep {
+ pinconf {
+ pins = "gpio0", "gpio1",
+ "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&blsp1_uart2_default {
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&blsp1_uart2_sleep {
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&cdc_pdm_lines_act {
+ pinconf {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ drive-strength = <8>;
+ bias-pull-none;
+ };
+};
+
+&cdc_pdm_lines_sus {
+ pinconf {
+ pins = "gpio63", "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&ext_mclk_tlmm_lines_act {
+ pinconf {
+ pins = "gpio116";
+ drive-strength = <8>;
+ bias-pull-none;
+ };
+};
+
+&ext_mclk_tlmm_lines_sus {
+ pinconf {
+ pins = "gpio116";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&ext_sec_tlmm_lines_act {
+ pinconf {
+ pins = "gpio112", "gpio117", "gpio118",
+ "gpio119";
+ drive-strength = <8>;
+ bias-pull-none;
+ };
+};
+
+&ext_sec_tlmm_lines_sus {
+ pinconf {
+ pins = "gpio112", "gpio117", "gpio118",
+ "gpio119";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&i2c2_default {
+ pinconf {
+ pins = "gpio6", "gpio7";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&i2c2_sleep {
+ pinconf {
+ pins = "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&i2c4_default {
+ pinconf {
+ pins = "gpio14", "gpio15";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&i2c4_sleep {
+ pinconf {
+ pins = "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&i2c6_default {
+ pinconf {
+ pins = "gpio22", "gpio23";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&i2c6_sleep {
+ pinconf {
+ pins = "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&sdc1_clk_on {
+ pinconf {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+};
+
+&sdc1_clk_off {
+ pinconf {
+ pins = "sdc1_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+};
+
+&sdc1_cmd_on {
+ pinconf {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+};
+
+&sdc1_cmd_off {
+ pinconf {
+ pins = "sdc1_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+};
+
+&sdc1_data_on {
+ pinconf {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+};
+
+&sdc1_data_off {
+ pinconf {
+ pins = "sdc1_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+};
+
+&sdc2_clk_on {
+ pinconf {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <16>;
+ };
+};
+
+&sdc2_clk_off {
+ pinconf {
+ pins = "sdc2_clk";
+ bias-disable;
+ drive-strength = <2>;
+ };
+};
+
+&sdc2_cmd_on {
+ pinconf {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+};
+
+&sdc2_cmd_off {
+ pinconf {
+ pins = "sdc2_cmd";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+};
+
+&sdc2_data_on {
+ pinconf {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <10>;
+ };
+};
+
+&sdc2_data_off {
+ pinconf {
+ pins = "sdc2_data";
+ bias-pull-up;
+ drive-strength = <2>;
+ };
+};
+
+&sdc2_cd_on {
+ pinconf {
+ pins = "gpio38";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+};
+
+&sdc2_cd_off {
+ pinconf {
+ pins = "gpio38";
+ drive-strength = <2>;
+ bias-disable;
+ };
+};
+
+&spi1_default {
+ pinconf {
+ pins = "gpio0", "gpio1", "gpio3";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio2";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+};
+
+&spi1_sleep {
+ pinconf {
+ pins = "gpio0", "gpio1", "gpio2", "gpio3";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&spi2_default {
+ pinconf {
+ pins = "gpio4", "gpio5", "gpio7";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio6";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+};
+
+&spi2_sleep {
+ pinconf {
+ pins = "gpio4", "gpio5", "gpio6", "gpio7";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&spi3_default {
+ pinconf {
+ pins = "gpio8", "gpio9", "gpio11";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio10";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+};
+
+&spi3_sleep {
+ pinconf {
+ pins = "gpio8", "gpio9", "gpio10", "gpio11";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&spi4_default {
+ pinconf {
+ pins = "gpio12", "gpio13", "gpio15";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio14";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+};
+
+&spi4_sleep {
+ pinconf {
+ pins = "gpio12", "gpio13", "gpio14", "gpio15";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&spi5_default {
+ pinconf {
+ pins = "gpio16", "gpio17", "gpio19";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio18";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+};
+
+&spi5_sleep {
+ pinconf {
+ pins = "gpio16", "gpio17", "gpio18", "gpio19";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
+&spi6_default {
+ pinconf {
+ pins = "gpio20", "gpio21", "gpio23";
+ drive-strength = <12>;
+ bias-disable;
+ };
+ pinconf_cs {
+ pins = "gpio22";
+ drive-strength = <16>;
+ bias-disable;
+ output-high;
+ };
+};
+
+&spi6_sleep {
+ pinconf {
+ pins = "gpio20", "gpio21", "gpio22", "gpio23";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
&smd_rpm_regulators {
vdd_l1_l2_l3-supply = <&pm8916_s3>;
vdd_l5-supply = <&pm8916_s3>;
@@ -671,3 +1049,11 @@
qcom,mbhc-vthreshold-low = <75 150 237 450 500>;
qcom,mbhc-vthreshold-high = <75 150 237 450 500>;
};
+
+&wcnss_pin_a {
+ pinconf {
+ pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
+ drive-strength = <6>;
+ bias-pull-up;
+ };
+};
diff --git a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
index ceeb8a6feed6..9f15148f8a03 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-mtp.dtsi
@@ -33,3 +33,20 @@
};
};
};
+
+&blsp1_uart2_default {
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <16>;
+ bias-disable;
+ };
+};
+
+&blsp1_uart2_sleep {
+ pinconf {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
index 21f144c55638..0790232c4654 100644
--- a/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916-pins.dtsi
@@ -20,12 +20,6 @@
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
};
- pinconf {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- drive-strength = <16>;
- bias-disable;
- };
};
blsp1_uart1_sleep: blsp1_uart1_sleep {
@@ -34,12 +28,6 @@
pins = "gpio0", "gpio1",
"gpio2", "gpio3";
};
- pinconf {
- pins = "gpio0", "gpio1",
- "gpio2", "gpio3";
- drive-strength = <2>;
- bias-pull-down;
- };
};
blsp1_uart2_default: blsp1_uart2_default {
@@ -47,11 +35,6 @@
function = "blsp_uart2";
pins = "gpio4", "gpio5";
};
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <16>;
- bias-disable;
- };
};
blsp1_uart2_sleep: blsp1_uart2_sleep {
@@ -59,11 +42,6 @@
function = "gpio";
pins = "gpio4", "gpio5";
};
- pinconf {
- pins = "gpio4", "gpio5";
- drive-strength = <2>;
- bias-pull-down;
- };
};
spi1_default: spi1_default {
@@ -75,17 +53,6 @@
function = "gpio";
pins = "gpio2";
};
- pinconf {
- pins = "gpio0", "gpio1", "gpio3";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio2";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
};
spi1_sleep: spi1_sleep {
@@ -93,11 +60,6 @@
function = "gpio";
pins = "gpio0", "gpio1", "gpio2", "gpio3";
};
- pinconf {
- pins = "gpio0", "gpio1", "gpio2", "gpio3";
- drive-strength = <2>;
- bias-pull-down;
- };
};
spi2_default: spi2_default {
@@ -109,17 +71,6 @@
function = "gpio";
pins = "gpio6";
};
- pinconf {
- pins = "gpio4", "gpio5", "gpio7";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio6";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
};
spi2_sleep: spi2_sleep {
@@ -127,11 +78,6 @@
function = "gpio";
pins = "gpio4", "gpio5", "gpio6", "gpio7";
};
- pinconf {
- pins = "gpio4", "gpio5", "gpio6", "gpio7";
- drive-strength = <2>;
- bias-pull-down;
- };
};
spi3_default: spi3_default {
@@ -143,17 +89,6 @@
function = "gpio";
pins = "gpio10";
};
- pinconf {
- pins = "gpio8", "gpio9", "gpio11";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio10";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
};
spi3_sleep: spi3_sleep {
@@ -161,11 +96,6 @@
function = "gpio";
pins = "gpio8", "gpio9", "gpio10", "gpio11";
};
- pinconf {
- pins = "gpio8", "gpio9", "gpio10", "gpio11";
- drive-strength = <2>;
- bias-pull-down;
- };
};
spi4_default: spi4_default {
@@ -177,17 +107,6 @@
function = "gpio";
pins = "gpio14";
};
- pinconf {
- pins = "gpio12", "gpio13", "gpio15";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio14";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
};
spi4_sleep: spi4_sleep {
@@ -195,11 +114,6 @@
function = "gpio";
pins = "gpio12", "gpio13", "gpio14", "gpio15";
};
- pinconf {
- pins = "gpio12", "gpio13", "gpio14", "gpio15";
- drive-strength = <2>;
- bias-pull-down;
- };
};
spi5_default: spi5_default {
@@ -211,17 +125,6 @@
function = "gpio";
pins = "gpio18";
};
- pinconf {
- pins = "gpio16", "gpio17", "gpio19";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio18";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
};
spi5_sleep: spi5_sleep {
@@ -229,11 +132,6 @@
function = "gpio";
pins = "gpio16", "gpio17", "gpio18", "gpio19";
};
- pinconf {
- pins = "gpio16", "gpio17", "gpio18", "gpio19";
- drive-strength = <2>;
- bias-pull-down;
- };
};
spi6_default: spi6_default {
@@ -245,17 +143,6 @@
function = "gpio";
pins = "gpio22";
};
- pinconf {
- pins = "gpio20", "gpio21", "gpio23";
- drive-strength = <12>;
- bias-disable;
- };
- pinconf_cs {
- pins = "gpio22";
- drive-strength = <16>;
- bias-disable;
- output-high;
- };
};
spi6_sleep: spi6_sleep {
@@ -263,11 +150,6 @@
function = "gpio";
pins = "gpio20", "gpio21", "gpio22", "gpio23";
};
- pinconf {
- pins = "gpio20", "gpio21", "gpio22", "gpio23";
- drive-strength = <2>;
- bias-pull-down;
- };
};
i2c2_default: i2c2_default {
@@ -275,11 +157,6 @@
function = "blsp_i2c2";
pins = "gpio6", "gpio7";
};
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <16>;
- bias-disable;
- };
};
i2c2_sleep: i2c2_sleep {
@@ -287,11 +164,6 @@
function = "gpio";
pins = "gpio6", "gpio7";
};
- pinconf {
- pins = "gpio6", "gpio7";
- drive-strength = <2>;
- bias-disable;
- };
};
i2c4_default: i2c4_default {
@@ -299,11 +171,6 @@
function = "blsp_i2c4";
pins = "gpio14", "gpio15";
};
- pinconf {
- pins = "gpio14", "gpio15";
- drive-strength = <16>;
- bias-disable;
- };
};
i2c4_sleep: i2c4_sleep {
@@ -311,11 +178,6 @@
function = "gpio";
pins = "gpio14", "gpio15";
};
- pinconf {
- pins = "gpio14", "gpio15";
- drive-strength = <2>;
- bias-disable;
- };
};
i2c6_default: i2c6_default {
@@ -323,11 +185,6 @@
function = "blsp_i2c6";
pins = "gpio22", "gpio23";
};
- pinconf {
- pins = "gpio22", "gpio23";
- drive-strength = <16>;
- bias-disable;
- };
};
i2c6_sleep: i2c6_sleep {
@@ -335,11 +192,6 @@
function = "gpio";
pins = "gpio22", "gpio23";
};
- pinconf {
- pins = "gpio22", "gpio23";
- drive-strength = <2>;
- bias-disable;
- };
};
sdhc2_cd_pin {
@@ -348,22 +200,12 @@
function = "gpio";
pins = "gpio38";
};
- pinconf {
- pins = "gpio38";
- drive-strength = <2>;
- bias-pull-up;
- };
};
sdc2_cd_off: cd_off {
pinmux {
function = "gpio";
pins = "gpio38";
};
- pinconf {
- pins = "gpio38";
- drive-strength = <2>;
- bias-disable;
- };
};
};
@@ -372,21 +214,11 @@
pinmux {
pins = "sdc1_clk";
};
- pinconf {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <16>;
- };
};
sdc1_clk_off: clk_off {
pinmux {
pins = "sdc1_clk";
};
- pinconf {
- pins = "sdc1_clk";
- bias-disable;
- drive-strength = <2>;
- };
};
};
@@ -395,21 +227,11 @@
pinmux {
pins = "sdc1_cmd";
};
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
};
sdc1_cmd_off: cmd_off {
pinmux {
pins = "sdc1_cmd";
};
- pinconf {
- pins = "sdc1_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
};
};
@@ -418,21 +240,11 @@
pinmux {
pins = "sdc1_data";
};
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <10>;
- };
};
sdc1_data_off: data_off {
pinmux {
pins = "sdc1_data";
};
- pinconf {
- pins = "sdc1_data";
- bias-pull-up;
- drive-strength = <2>;
- };
};
};
@@ -441,21 +253,11 @@
pinmux {
pins = "sdc2_clk";
};
- pinconf {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <16>;
- };
};
sdc2_clk_off: clk_off {
pinmux {
pins = "sdc2_clk";
};
- pinconf {
- pins = "sdc2_clk";
- bias-disable;
- drive-strength = <2>;
- };
};
};
@@ -464,21 +266,11 @@
pinmux {
pins = "sdc2_cmd";
};
- pinconf {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <10>;
- };
};
sdc2_cmd_off: cmd_off {
pinmux {
pins = "sdc2_cmd";
};
- pinconf {
- pins = "sdc2_cmd";
- bias-pull-up;
- drive-strength = <2>;
- };
};
};
@@ -487,21 +279,11 @@
pinmux {
pins = "sdc2_data";
};
- pinconf {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <10>;
- };
};
sdc2_data_off: data_off {
pinmux {
pins = "sdc2_data";
};
- pinconf {
- pins = "sdc2_data";
- bias-pull-up;
- drive-strength = <2>;
- };
};
};
@@ -512,12 +294,6 @@
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
};
- pinconf {
- pins = "gpio63", "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68";
- drive-strength = <8>;
- bias-pull-none;
- };
};
cdc_pdm_lines_sus: pdm_lines_off {
pinmux {
@@ -525,12 +301,6 @@
pins = "gpio63", "gpio64", "gpio65", "gpio66",
"gpio67", "gpio68";
};
- pinconf {
- pins = "gpio63", "gpio64", "gpio65", "gpio66",
- "gpio67", "gpio68";
- drive-strength = <2>;
- bias-disable;
- };
};
};
@@ -596,22 +366,12 @@
function = "pri_mi2s";
pins = "gpio116";
};
- pinconf {
- pins = "gpio116";
- drive-strength = <8>;
- bias-pull-none;
- };
};
ext_mclk_tlmm_lines_sus: mclk_lines_off {
pinmux {
function = "pri_mi2s";
pins = "gpio116";
};
- pinconf {
- pins = "gpio116";
- drive-strength = <2>;
- bias-disable;
- };
};
};
@@ -623,12 +383,6 @@
pins = "gpio112", "gpio117", "gpio118",
"gpio119";
};
- pinconf {
- pins = "gpio112", "gpio117", "gpio118",
- "gpio119";
- drive-strength = <8>;
- bias-pull-none;
- };
};
ext_sec_tlmm_lines_sus: tlmm_lines_off {
pinmux {
@@ -636,12 +390,6 @@
pins = "gpio112", "gpio117", "gpio118",
"gpio119";
};
- pinconf {
- pins = "gpio112", "gpio117", "gpio118",
- "gpio119";
- drive-strength = <2>;
- bias-disable;
- };
};
};
@@ -682,11 +430,5 @@
pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
function = "wcss_wlan";
};
-
- pinconf {
- pins = "gpio40", "gpio41", "gpio42", "gpio43", "gpio44";
- drive-strength = <6>;
- bias-pull-up;
- };
};
};
--
2.15.0
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