* [PATCH v2] arm64: cpu_errata: Add Kryo to Falkor 1003 errata
From: Stephen Boyd @ 2017-12-13 21:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171212181156.GA25244@arm.com>
On 12/12, Will Deacon wrote:
> Hi Stephen,
>
> On Wed, Nov 29, 2017 at 03:03:53PM -0800, Stephen Boyd wrote:
> > The Kryo CPUs are also affected by the Falkor 1003 errata, so
> > we need to do the same workaround on Kryo CPUs. The MIDR is
> > slightly more complicated here, where the PART number is not
> > always the same when looking at all the bits from 15 to 4. Drop
> > the lower 8 bits and just look at the top 4 to see if it's '2'
> > and then consider those as Kryo CPUs. This covers all the
> > combinations without having to list them all out.
> >
> > Introduce a new hardware cap bit for the combination of hardware
> > PAN support and this errata so that we can disable support for
> > software PAN at runtime if this errata is present and the CPU
> > doesn't support HW PAN. This happens on some Kryo CPUs where the
> > HW PAN feature isn't supported but we can't prevent software PAN
> > from being selected in the configuration. Previously, Falkor CPUs
> > were all known to have HW PAN support, so we didn't need to worry
> > about this case.
> >
> > Fixes: 38fd94b0275c ("arm64: Work around Falkor erratum 1003")
> > Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
> > ---
>
> Can you respin this on top of for-next/core please? The PAN bits should
> be much simpler with the KPTI code.
>
No problem. I'll send it out in a couple hours.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] kbuild: fix dependency of dtbs targets
From: Rob Herring @ 2017-12-13 21:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK7LNASCQqaBvERg6NXPym62Dyza00TuZVOWtj0YqLDKPT2D5g@mail.gmail.com>
On Wed, Oct 25, 2017 at 12:40 AM, Masahiro Yamada
<yamada.masahiro@socionext.com> wrote:
> Hi.
>
>
> 2017-10-10 0:05 GMT+09:00 Russell King - ARM Linux <linux@armlinux.org.uk>:
>> On Wed, Oct 04, 2017 at 01:27:20PM +0900, Masahiro Yamada wrote:
>>> The target "dtbs" should depend on "scripts" because it needs to
>>> build dtc. The "prepare" target is unneeded here.
>>
>> Looks fine for ARM, as the only thing the dtbs should depend on is
>> the kernel configuration (to decide which to build) and DT tooling.
>>
>> Acked-by: Russell King <rmk+kernel@armlinux.org.uk>
>>
>> --
>
>
> I found a potential issue on this
> because the default DTB install path depends on $(KERNELRELEASE).
>
>
> In top-level Makefile:
> export INSTALL_DTBS_PATH ?= $(INSTALL_PATH)/dtbs/$(KERNELRELEASE)
>
>
> The include/config/kernel.release is created by "prepare3" target.
>
> If the dependency on "parepare" is removed,
> it is possible to run "make dtbs" and "make dtbs_install"
> without creating include/config/kernel.release.
>
> So, the $(KERNELRELEASE) could be empty when installing DTB.
>
>
> Maybe, drop this patch, or reduce the dependency to "parepare3"?
I was doing some work to get dtb builds to work without depending on
$arch cross compiler and this patch fixes some of the issues. The
dtbs_install target has the prepare dependency, so that should be
sufficient and your patch should be fine. BTW, Based on prior
discussion on "ARM: kbuild: Fix forced rebuild after 'make dtbs'"
thread, prepare should not be needed just for $(KERNELRELEASE).
Rob
^ permalink raw reply
* [PATCH v3] arm64: cpu_errata: Add Kryo to Falkor 1003 errata
From: Stephen Boyd @ 2017-12-13 22:19 UTC (permalink / raw)
To: linux-arm-kernel
The Kryo CPUs are also affected by the Falkor 1003 errata, so
we need to do the same workaround on Kryo CPUs. The MIDR is
slightly more complicated here, where the PART number is not
always the same when looking at all the bits from 15 to 4. Drop
the lower 8 bits and just look at the top 4 to see if it's '2'
and then consider those as Kryo CPUs. This covers all the
combinations without having to list them all out.
Fixes: 38fd94b0275c ("arm64: Work around Falkor erratum 1003")
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
Changes from v2:
* Dropped the new cap bit, rebased onto for-next/core in arm64 tree
Documentation/arm64/silicon-errata.txt | 2 +-
arch/arm64/include/asm/cputype.h | 2 ++
arch/arm64/kernel/cpu_errata.c | 21 +++++++++++++++++++++
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
index 304bf22bb83c..b9d93e981a05 100644
--- a/Documentation/arm64/silicon-errata.txt
+++ b/Documentation/arm64/silicon-errata.txt
@@ -72,6 +72,6 @@ stable kernels.
| Hisilicon | Hip0{6,7} | #161010701 | N/A |
| Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 |
| | | | |
-| Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
+| Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |
| Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |
| Qualcomm Tech. | QDF2400 ITS | E0065 | QCOM_QDF2400_ERRATUM_0065 |
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 235e77d98261..b5afa6668646 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -91,6 +91,7 @@
#define BRCM_CPU_PART_VULCAN 0x516
#define QCOM_CPU_PART_FALKOR_V1 0x800
+#define QCOM_CPU_PART_KRYO 0x200
#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
@@ -99,6 +100,7 @@
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
+#define MIDR_QCOM_KRYO MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_KRYO)
#ifndef __ASSEMBLY__
diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c
index 0e27f86ee709..e4c78630a730 100644
--- a/arch/arm64/kernel/cpu_errata.c
+++ b/arch/arm64/kernel/cpu_errata.c
@@ -30,6 +30,20 @@ is_affected_midr_range(const struct arm64_cpu_capabilities *entry, int scope)
entry->midr_range_max);
}
+static bool __maybe_unused
+is_kryo_midr(const struct arm64_cpu_capabilities *entry, int scope)
+{
+ u32 model;
+
+ WARN_ON(scope != SCOPE_LOCAL_CPU || preemptible());
+
+ model = read_cpuid_id();
+ model &= MIDR_IMPLEMENTOR_MASK | (0xf00 << MIDR_PARTNUM_SHIFT) |
+ MIDR_ARCHITECTURE_MASK;
+
+ return model == entry->midr_model;
+}
+
static bool
has_mismatched_cache_line_size(const struct arm64_cpu_capabilities *entry,
int scope)
@@ -169,6 +183,13 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
MIDR_CPU_VAR_REV(0, 0),
MIDR_CPU_VAR_REV(0, 0)),
},
+ {
+ .desc = "Qualcomm Technologies Kryo erratum 1003",
+ .capability = ARM64_WORKAROUND_QCOM_FALKOR_E1003,
+ .def_scope = SCOPE_LOCAL_CPU,
+ .midr_model = MIDR_QCOM_KRYO,
+ .matches = is_kryo_midr,
+ },
#endif
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1009
{
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* [PATCH v5 6/9] ACPI/PPTT: Add topology parsing code
From: Rafael J. Wysocki @ 2017-12-13 22:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171213173851.GA4060@red-moon>
On Wed, Dec 13, 2017 at 6:38 PM, Lorenzo Pieralisi
<lorenzo.pieralisi@arm.com> wrote:
> On Tue, Dec 12, 2017 at 10:13:08AM -0600, Jeremy Linton wrote:
>> Hi,
>>
>> First, thanks for taking a look at this.
>>
>> On 12/11/2017 07:12 PM, Rafael J. Wysocki wrote:
>> >On Friday, December 1, 2017 11:23:27 PM CET Jeremy Linton wrote:
>> >>The PPTT can be used to determine the groupings of CPU's at
>> >>given levels in the system. Lets add a few routines to the PPTT
>> >>parsing code to return a unique id for each unique level in the
>> >>processor hierarchy. This can then be matched to build
>> >>thread/core/cluster/die/package/etc mappings for each processing
>> >>element in the system.
>> >>
>> >>Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> >
>> >Why can't this be folded into patch [2/9]?
>>
>> It can, and I will be happy squash it.
>>
>> It was requested that the topology portion of the parser be split
>> out back in v3.
>>
>> https://www.spinics.net/lists/linux-acpi/msg78487.html
>
> I asked to split cache/topology since I am not familiar with cache
> code and Sudeep - who looks after the cache code - won't be able
> to review this series in time for v4.16.
OK, so why do we need it in 4.16?
^ permalink raw reply
* [PATCH 1/3] [v2] Revert "gpio: set up initial state from .get_direction()"
From: Stephen Boyd @ 2017-12-13 22:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513189818-7384-2-git-send-email-timur@codeaurora.org>
On 12/13, Timur Tabi wrote:
> This reverts commit 72d3200061776264941be1b5a9bb8e926b3b30a5.
>
> We cannot blindly query the direction of all GPIOs when the pins are
> first registered. The get_direction callback normally triggers a
> read/write to hardware, but we shouldn't be touching the hardware for
> an individual GPIO until after it's been properly claimed.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 2/3] [v8] pinctrl: qcom: disable GPIO groups with no pins
From: Stephen Boyd @ 2017-12-13 22:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513189818-7384-3-git-send-email-timur@codeaurora.org>
On 12/13, Timur Tabi wrote:
> pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects
> each group to support have only one pin (npins == 1).
>
> We can support "sparse" GPIO maps if we allow for some groups to have zero
> pins (npins == 0). These pins are "hidden" from the rest of the driver
> and gpiolib.
>
> Access to unavailable GPIOs is blocked via a request callback. If the
> requested GPIO is unavailable, -EACCES is returned, which prevents
> further access to that GPIO.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH V2 3/7] PCI: make pci_flr_wait() generic and rename to pci_dev_wait()
From: Bjorn Helgaas @ 2017-12-13 22:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1511763628-11856-4-git-send-email-okaya@codeaurora.org>
On Mon, Nov 27, 2017 at 01:20:24AM -0500, Sinan Kaya wrote:
> Rev 3.1 Sec 2.3.1 Request Handling Rules:
> Valid reset conditions after which a device is permitted to return CRS
> are:
> * Cold, Warm, and Hot Resets,
> * FLR
> * A reset initiated in response to a D3hot to D0 uninitialized
>
> Try to reuse FLR implementation towards other reset types.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> ---
> drivers/pci/pci.c | 47 ++++++++++++++++++++++++++++++-----------------
> 1 file changed, 30 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 27ec45d..ed3c3bc 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -125,6 +125,9 @@ static int __init pcie_port_pm_setup(char *str)
> }
> __setup("pcie_port_pm=", pcie_port_pm_setup);
>
> +/* time to wait after a reset for device to become responsive */
> +#define PCIE_RESET_READY_POLL_MS 60000
> +
> /**
> * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
> * @bus: pointer to PCI bus structure to search
> @@ -3820,20 +3823,13 @@ int pci_wait_for_pending_transaction(struct pci_dev *dev)
> }
> EXPORT_SYMBOL(pci_wait_for_pending_transaction);
>
> -static int pci_flr_wait(struct pci_dev *dev)
> +static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout)
> {
> - int delay = 1, timeout = 60000;
> + int delay = 1;
> u32 id;
>
> /*
> - * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
> - * 100ms, but may silently discard requests while the FLR is in
> - * progress. Wait 100ms before trying to access the device.
> - */
> - msleep(100);
> -
> - /*
> - * After 100ms, the device should not silently discard config
> + * After reset, the device should not silently discard config
> * requests, but it may still indicate that it needs more time by
> * responding to them with CRS completions. The Root Port will
> * generally synthesize ~0 data to complete the read (except when
> @@ -3847,14 +3843,14 @@ static int pci_flr_wait(struct pci_dev *dev)
> pci_read_config_dword(dev, PCI_COMMAND, &id);
> while (id == ~0) {
> if (delay > timeout) {
> - dev_warn(&dev->dev, "not ready %dms after FLR; giving up\n",
> - 100 + delay - 1);
> + dev_warn(&dev->dev, "not ready %dms after %s; giving up\n",
> + delay - 1, reset_type);
> return -ENOTTY;
> }
>
> if (delay > 1000)
> - dev_info(&dev->dev, "not ready %dms after FLR; waiting\n",
> - 100 + delay - 1);
> + dev_info(&dev->dev, "not ready %dms after %s; waiting\n",
> + delay - 1, reset_type);
>
> msleep(delay);
> delay *= 2;
> @@ -3862,7 +3858,8 @@ static int pci_flr_wait(struct pci_dev *dev)
> }
>
> if (delay > 1000)
> - dev_info(&dev->dev, "ready %dms after FLR\n", 100 + delay - 1);
> + dev_info(&dev->dev, "ready %dms after %s\n", delay - 1,
> + reset_type);
>
> return 0;
> }
> @@ -3899,7 +3896,15 @@ int pcie_flr(struct pci_dev *dev)
> dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
>
> pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
> - return pci_flr_wait(dev);
> +
> + /*
> + * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
> + * 100ms, but may silently discard requests while the FLR is in
> + * progress. Wait 100ms before trying to access the device.
> + */
> + msleep(100);
> +
> + return pci_dev_wait(dev, "FLR", PCIE_RESET_READY_POLL_MS);
> }
> EXPORT_SYMBOL_GPL(pcie_flr);
>
> @@ -3932,7 +3937,15 @@ static int pci_af_flr(struct pci_dev *dev, int probe)
> dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
>
> pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
> - return pci_flr_wait(dev);
> +
> + /*
> + * Per PCIe r3.1, sec 6.6.2, a device must complete an FLR within
I think this should reference the "Advanced Capabilities for
Conventional PCI" ECN, shouldn't it? The one I see is dated 13 April
2006, updated 27 July 2006, and I don't see a PCI spec that includes
it.
> + * 100ms, but may silently discard requests while the FLR is in
> + * progress. Wait 100ms before trying to access the device.
> + */
> + msleep(100);
> +
> + return pci_dev_wait(dev, "AF_FLR", PCIE_RESET_READY_POLL_MS);
CRS is not applicable to conventional PCI. The ECN mentions waiting
100ms. I don't see anything about polling after that, but I guess it
probably doesn't hurt anything.
> }
>
> /**
> --
> 1.9.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 1/3] dt-bindings: chosen: Add clocksource and clockevent selection
From: Rob Herring @ 2017-12-13 22:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171213185313.20017-2-alexandre.belloni@free-electrons.com>
On Wed, Dec 13, 2017 at 12:53 PM, Alexandre Belloni
<alexandre.belloni@free-electrons.com> wrote:
> The clocksource and clockevent timer are probed early in the boot process.
> At that time it is difficult for linux to know whether a particular timer
> can be used as the clocksource or the clockevent or by another driver,
> especially when they are all identical or have similar features.
If all identical, then it shouldn't matter. "similar" means some
difference. Describe those differences.
> Until now, multiple strategies have been used to solve that:
> - use Kconfig option as MXC_USE_EPIT or ATMEL_TCB_CLKSRC_BLOCK
Compile time probably means only one option is really used.
> - use a kernel parameter as the "clocksource" early_param in mach-omap2
Yeah, OMAP was one of the previous times this came up and also
attempted something like this. This parameter predates selecting
timers based on features described in DT. Look at commit
2eb03937df3ebc (ARM: OMAP3: Update clocksource timer selection).
> - registering the first seen timer as a clockevent and the second one as
> a clocksource as in rk_timer_init or dw_apb_timer_init
>
> Add a linux,clocksource and a linux,clockevent node in chosen with a timer
> property pointing to the timer to use. Other properties, like the targeted
> precision may be added later.
Open ended expansion of this does not help convince me it is needed.
Rob
^ permalink raw reply
* [xlnx:2017.3_video_ea 6585/6607] drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:49:19: warning: passing argument 2 of 'iowrite32' discards 'volatile' qualifier from pointer target type
From: kbuild test robot @ 2017-12-13 22:58 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://github.com/Xilinx/linux-xlnx 2017.3_video_ea
head: af045f9682c65a0c26afb2f638603d3c01079222
commit: b58dab7f9cf13f9004a220128317fc85a1b75b63 [6585/6607] staging: xilinx: Add xilinx hdmi drivers to staging area
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout b58dab7f9cf13f9004a220128317fc85a1b75b63
# save the attached .config to linux build tree
make.cross ARCH=sh
All warnings (new ones prefixed by >>):
In file included from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xvphy_hw.h:49:0,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xvphy.h:95,
from drivers/staging/xilinx/hdmi/include/linux/phy/phy-vphy.h:22,
from drivers/staging/xilinx/hdmi/xilinx-hdmirx.c:37:
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h: In function 'Xil_Out32':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:49:19: warning: passing argument 2 of 'iowrite32' discards 'volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
iowrite32(Value, (volatile void *)Addr);
^
In file included from arch/sh/include/asm/io.h:20:0,
from include/linux/io.h:25,
from include/linux/irq.h:24,
from arch/sh/include/asm/hardirq.h:5,
from include/linux/hardirq.h:8,
from include/linux/interrupt.h:12,
from drivers/staging/xilinx/hdmi/xilinx-hdmirx.c:24:
include/asm-generic/iomap.h:41:13: note: expected 'void *' but argument is of type 'volatile void *'
extern void iowrite32(u32, void __iomem *);
^~~~~~~~~
In file included from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xvphy_hw.h:49:0,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xvphy.h:95,
from drivers/staging/xilinx/hdmi/include/linux/phy/phy-vphy.h:22,
from drivers/staging/xilinx/hdmi/xilinx-hdmirx.c:37:
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h: In function 'Xil_In32':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:53:18: warning: passing argument 1 of 'ioread32' discards 'const volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
return ioread32((const volatile void *)Addr);
^
In file included from arch/sh/include/asm/io.h:20:0,
from include/linux/io.h:25,
from include/linux/irq.h:24,
from arch/sh/include/asm/hardirq.h:5,
from include/linux/hardirq.h:8,
from include/linux/interrupt.h:12,
from drivers/staging/xilinx/hdmi/xilinx-hdmirx.c:24:
include/asm-generic/iomap.h:31:21: note: expected 'void *' but argument is of type 'const volatile void *'
extern unsigned int ioread32(void __iomem *);
^~~~~~~~
--
In file included from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59:0,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx.h:92,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_i.h:51,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_crypt.c:41:
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h: In function 'Xil_Out32':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:49:19: warning: passing argument 2 of 'iowrite32' discards 'volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
iowrite32(Value, (volatile void *)Addr);
^
In file included from arch/sh/include/asm/io.h:20:0,
from include/linux/io.h:25,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:45,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx.h:92,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_i.h:51,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_crypt.c:41:
include/asm-generic/iomap.h:41:13: note: expected 'void *' but argument is of type 'volatile void *'
extern void iowrite32(u32, void __iomem *);
^~~~~~~~~
In file included from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59:0,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx.h:92,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_i.h:51,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_crypt.c:41:
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h: In function 'Xil_In32':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:53:18: warning: passing argument 1 of 'ioread32' discards 'const volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
return ioread32((const volatile void *)Addr);
^
In file included from arch/sh/include/asm/io.h:20:0,
from include/linux/io.h:25,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:45,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx.h:92,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_i.h:51,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_crypt.c:41:
include/asm-generic/iomap.h:31:21: note: expected 'void *' but argument is of type 'const volatile void *'
extern unsigned int ioread32(void __iomem *);
^~~~~~~~
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_crypt.c: In function 'XHdcp22Tx_RsaEncryptMsg':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_tx_crypt.c:254:1: warning: the frame size of 1536 bytes is larger than 1024 bytes [-Wframe-larger-than=]
}
^
--
In file included from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59:0,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx.h:105,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_i.h:47,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_crypt.c:46:
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h: In function 'Xil_Out32':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:49:19: warning: passing argument 2 of 'iowrite32' discards 'volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
iowrite32(Value, (volatile void *)Addr);
^
In file included from arch/sh/include/asm/io.h:20:0,
from include/linux/io.h:25,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:45,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx.h:105,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_i.h:47,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_crypt.c:46:
include/asm-generic/iomap.h:41:13: note: expected 'void *' but argument is of type 'volatile void *'
extern void iowrite32(u32, void __iomem *);
^~~~~~~~~
In file included from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59:0,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx.h:105,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_i.h:47,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_crypt.c:46:
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h: In function 'Xil_In32':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:53:18: warning: passing argument 1 of 'ioread32' discards 'const volatile' qualifier from pointer target type [-Wdiscarded-qualifiers]
return ioread32((const volatile void *)Addr);
^
In file included from arch/sh/include/asm/io.h:20:0,
from include/linux/io.h:25,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h:45,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr_l.h:59,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xtmrctr.h:162,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx.h:105,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_i.h:47,
from drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_crypt.c:46:
include/asm-generic/iomap.h:31:21: note: expected 'void *' but argument is of type 'const volatile void *'
extern unsigned int ioread32(void __iomem *);
^~~~~~~~
drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_crypt.c: In function 'XHdcp22Rx_CalcMontNPrime':
>> drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xhdcp22_rx_crypt.c:169:1: warning: the frame size of 1048 bytes is larger than 1024 bytes [-Wframe-larger-than=]
}
^
vim +49 drivers/staging/xilinx/hdmi/phy-xilinx-vphy/xil_io.h
73634d89 Rohit Consul 2017-10-31 46
73634d89 Rohit Consul 2017-10-31 47 static inline void Xil_Out32(INTPTR Addr, u32 Value)
73634d89 Rohit Consul 2017-10-31 48 {
73634d89 Rohit Consul 2017-10-31 @49 iowrite32(Value, (volatile void *)Addr);
73634d89 Rohit Consul 2017-10-31 50 }
73634d89 Rohit Consul 2017-10-31 51 static inline u32 Xil_In32(INTPTR Addr)
73634d89 Rohit Consul 2017-10-31 52 {
73634d89 Rohit Consul 2017-10-31 @53 return ioread32((const volatile void *)Addr);
73634d89 Rohit Consul 2017-10-31 54 }
73634d89 Rohit Consul 2017-10-31 55
:::::: The code at line 49 was first introduced by commit
:::::: 73634d891211ef92c9d8c789a1ccc002118164ba phy: xilinx-vphy: Initial release of xilinx video phy soft IP driver
:::::: TO: Rohit Consul <rohit.consul@xilinx.com>
:::::: CC: Jeffrey Mouroux <jmouroux@xilinx.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
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^ permalink raw reply
* [PATCH 3/3] [v6] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002
From: Stephen Boyd @ 2017-12-13 23:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513189818-7384-4-git-send-email-timur@codeaurora.org>
On 12/13, Timur Tabi wrote:
> Newer versions of the firmware for the Qualcomm Datacenter Technologies
> QDF2400 restricts access to a subset of the GPIOs on the TLMM. To
> prevent older kernels from accidentally accessing the restricted GPIOs,
> we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
> and introduce a new property "gpios". This property is an array of
> specific GPIOs that are accessible. When an older kernel boots on
> newer (restricted) firmware, it will fail to probe.
>
> To implement the sparse GPIO map, we register all of the GPIOs, but set
> the pin count for the unavailable GPIOs to zero. The pinctrl-msm
> driver will block those unavailable GPIOs from being accessed.
>
> To allow newer kernels to support older firmware, the driver retains
> support for QCOM8001.
>
> Signed-off-by: Timur Tabi <timur@codeaurora.org>
> ---
> drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 134 +++++++++++++++++++++++++--------
> 1 file changed, 103 insertions(+), 31 deletions(-)
>
> diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> index bb3ce5c3e18b..deb08e08e86d 100644
> --- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> +++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
> @@ -38,68 +38,139 @@
> /* maximum size of each gpio name (enough room for "gpioXXX" + null) */
> #define NAME_SIZE 8
>
> +enum {
> + QDF2XXX_V1,
> + QDF2XXX_V2,
> +};
> +
> static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
> {
> + const struct acpi_device_id *id;
> struct pinctrl_pin_desc *pins;
> struct msm_pingroup *groups;
> char (*names)[NAME_SIZE];
> unsigned int i;
> u32 num_gpios;
> + unsigned int avail_gpios; /* The number of GPIOs we support */
> + u16 *gpios; /* An array of supported GPIOs */
> int ret;
>
> /* Query the number of GPIOs from ACPI */
> ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
> if (ret < 0) {
> - dev_warn(&pdev->dev, "missing num-gpios property\n");
> + dev_err(&pdev->dev, "missing 'num-gpios' property\n");
> return ret;
> }
> -
> if (!num_gpios || num_gpios > MAX_GPIOS) {
Given that we have MAX_GPIOS, it would be better to declare a
bitmap of available gpios of that size on the stack and then
iterate through the bitmap and set bits for the available ones.
In the QCOM8001 case, that would be setting all bits up to
num_gpios, and in the QCOM8002 case it would be iterating through
the list of gpios from the DSD property and setting the bit for
that gpio number. This avoids explicitly allocating a list of
numbers that is freed almost immediately. Instead we just stack
256 / sizeof(unsigned long) words and set bits.
Hopefully we could lift the same logic into the core pinctrl msm
driver for usage on non-ACPI systems.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v5 6/9] ACPI/PPTT: Add topology parsing code
From: Jeremy Linton @ 2017-12-13 23:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJZ5v0hTcC8D6pJuPK+isntWpckNgNmqLHW98iFXL817VYHHdg@mail.gmail.com>
Hi,
On 12/13/2017 04:28 PM, Rafael J. Wysocki wrote:
> On Wed, Dec 13, 2017 at 6:38 PM, Lorenzo Pieralisi
> <lorenzo.pieralisi@arm.com> wrote:
>> On Tue, Dec 12, 2017 at 10:13:08AM -0600, Jeremy Linton wrote:
>>> Hi,
>>>
>>> First, thanks for taking a look at this.
>>>
>>> On 12/11/2017 07:12 PM, Rafael J. Wysocki wrote:
>>>> On Friday, December 1, 2017 11:23:27 PM CET Jeremy Linton wrote:
>>>>> The PPTT can be used to determine the groupings of CPU's at
>>>>> given levels in the system. Lets add a few routines to the PPTT
>>>>> parsing code to return a unique id for each unique level in the
>>>>> processor hierarchy. This can then be matched to build
>>>>> thread/core/cluster/die/package/etc mappings for each processing
>>>>> element in the system.
>>>>>
>>>>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>>>>
>>>> Why can't this be folded into patch [2/9]?
>>>
>>> It can, and I will be happy squash it.
>>>
>>> It was requested that the topology portion of the parser be split
>>> out back in v3.
>>>
>>> https://www.spinics.net/lists/linux-acpi/msg78487.html
>>
>> I asked to split cache/topology since I am not familiar with cache
>> code and Sudeep - who looks after the cache code - won't be able
>> to review this series in time for v4.16.
>
> OK, so why do we need it in 4.16?
I think its more case of as soon as possible. That is because there are
machines where the topology is completely incorrect due to assumptions
the kernel makes based on registers that aren't defined for that purpose
(say describing which cores are in a physical socket, or LLC's attached
to interconnects or memory controllers).
This incorrect topology information is reported to things like the
kernel scheduler, which then makes poor scheduling decisions resulting
in sub-optimal system performance.
This patchset (and ACPI 6.2) clears up a lot of those problems.
Thanks,
^ permalink raw reply
* [PATCH 3/3] [v6] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002
From: Timur Tabi @ 2017-12-13 23:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171213230155.GS7997@codeaurora.org>
On 12/13/2017 05:01 PM, Stephen Boyd wrote:
> Given that we have MAX_GPIOS, it would be better to declare a
> bitmap of available gpios of that size on the stack and then
> iterate through the bitmap and set bits for the available ones.
> In the QCOM8001 case, that would be setting all bits up to
> num_gpios, and in the QCOM8002 case it would be iterating through
> the list of gpios from the DSD property and setting the bit for
> that gpio number. This avoids explicitly allocating a list of
> numbers that is freed almost immediately. Instead we just stack
> 256 / sizeof(unsigned long) words and set bits.
I'm not sure I understand. The only think I'm allocating temporarily is
the 'gpios' array, which is an array of shorts. Each element stores the
gpio number. It's not a bit array, so "256 / sizeof(unsigned long)"
doesn't apply. I need that array to read the DSD. You can't iterate
through an DSD property without reading it completely first.
> Hopefully we could lift the same logic into the core pinctrl msm
> driver for usage on non-ACPI systems.
There is no new memory allocation being done in pinctrl-msm, so I don't
understand this either.
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH v5 6/9] ACPI/PPTT: Add topology parsing code
From: Rafael J. Wysocki @ 2017-12-13 23:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6aca3fa0-9099-f283-ae16-0c48aa00d00d@arm.com>
On Thu, Dec 14, 2017 at 12:06 AM, Jeremy Linton <jeremy.linton@arm.com> wrote:
> Hi,
>
>
> On 12/13/2017 04:28 PM, Rafael J. Wysocki wrote:
>>
>> On Wed, Dec 13, 2017 at 6:38 PM, Lorenzo Pieralisi
>> <lorenzo.pieralisi@arm.com> wrote:
>>>
>>> On Tue, Dec 12, 2017 at 10:13:08AM -0600, Jeremy Linton wrote:
>>>>
>>>> Hi,
>>>>
>>>> First, thanks for taking a look at this.
>>>>
>>>> On 12/11/2017 07:12 PM, Rafael J. Wysocki wrote:
>>>>>
>>>>> On Friday, December 1, 2017 11:23:27 PM CET Jeremy Linton wrote:
>>>>>>
>>>>>> The PPTT can be used to determine the groupings of CPU's at
>>>>>> given levels in the system. Lets add a few routines to the PPTT
>>>>>> parsing code to return a unique id for each unique level in the
>>>>>> processor hierarchy. This can then be matched to build
>>>>>> thread/core/cluster/die/package/etc mappings for each processing
>>>>>> element in the system.
>>>>>>
>>>>>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>>>>>
>>>>>
>>>>> Why can't this be folded into patch [2/9]?
>>>>
>>>>
>>>> It can, and I will be happy squash it.
>>>>
>>>> It was requested that the topology portion of the parser be split
>>>> out back in v3.
>>>>
>>>> https://www.spinics.net/lists/linux-acpi/msg78487.html
>>>
>>>
>>> I asked to split cache/topology since I am not familiar with cache
>>> code and Sudeep - who looks after the cache code - won't be able
>>> to review this series in time for v4.16.
>>
>>
>> OK, so why do we need it in 4.16?
>
>
> I think its more case of as soon as possible. That is because there are
> machines where the topology is completely incorrect due to assumptions the
> kernel makes based on registers that aren't defined for that purpose (say
> describing which cores are in a physical socket, or LLC's attached to
> interconnects or memory controllers).
>
> This incorrect topology information is reported to things like the kernel
> scheduler, which then makes poor scheduling decisions resulting in
> sub-optimal system performance.
>
> This patchset (and ACPI 6.2) clears up a lot of those problems.
As long as the ACPI tables are as expected that is, I suppose?
Anyway, fair enough, but I don't want to rush it in.
Thanks,
Rafael
^ permalink raw reply
* [xlnx:master 5502/6640] drivers//fpga/zynqmp-fpga.c:60:2: error: implicit declaration of function '__flush_cache_user_range'; did you mean 'flush_cache_range'?
From: kbuild test robot @ 2017-12-13 23:41 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://github.com/Xilinx/linux-xlnx master
head: 9c2e29b2c81dbb1efb7ee4944b18e12226b97513
commit: 280ca3f99087c428f2627bdeada12224596e0784 [5502/6640] fpga manager: Adding FPGA Manager support for Xilinx zynqmp
config: sh-allmodconfig (attached as .config)
compiler: sh4-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 280ca3f99087c428f2627bdeada12224596e0784
# save the attached .config to linux build tree
make.cross ARCH=sh
All errors (new ones prefixed by >>):
drivers//fpga/zynqmp-fpga.c: In function 'zynqmp_fpga_ops_write':
>> drivers//fpga/zynqmp-fpga.c:60:2: error: implicit declaration of function '__flush_cache_user_range'; did you mean 'flush_cache_range'? [-Werror=implicit-function-declaration]
__flush_cache_user_range(kbuf, kbuf + size);
^~~~~~~~~~~~~~~~~~~~~~~~
flush_cache_range
cc1: some warnings being treated as errors
vim +60 drivers//fpga/zynqmp-fpga.c
43
44 static int zynqmp_fpga_ops_write(struct fpga_manager *mgr,
45 const char *buf, size_t size)
46 {
47 struct zynqmp_fpga_priv *priv;
48 char *kbuf;
49 dma_addr_t dma_addr;
50 u32 transfer_length;
51 int ret;
52
53 priv = mgr->priv;
54
55 kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL);
56 if (!kbuf)
57 return -ENOMEM;
58
59 memcpy(kbuf, buf, size);
> 60 __flush_cache_user_range(kbuf, kbuf + size);
61
62 /**
63 * Translate size from bytes to number of 32bit words that
64 * the DMA should write to the PCAP interface
65 */
66 if (size & 3)
67 transfer_length = (size >> 2) + 1;
68 else
69 transfer_length = size >> 2;
70
71 ret = zynqmp_pm_fpga_load(dma_addr, transfer_length, priv->flags);
72
73 dma_free_coherent(priv->dev, size, kbuf, dma_addr);
74
75 return ret;
76 }
77
---
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* [PATCH v3 3/8] PCI: brcmstb: Add Broadcom STB PCIe host controller driver
From: Jim Quinlan @ 2017-12-13 23:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171212221642.GB95453@bhelgaas-glaptop.roam.corp.google.com>
On Tue, Dec 12, 2017 at 5:16 PM, Bjorn Helgaas <helgaas@kernel.org> wrote:
> On Tue, Nov 14, 2017 at 05:12:07PM -0500, Jim Quinlan wrote:
>> This commit adds the basic Broadcom STB PCIe controller. Missing is
>> the ability to process MSI and also handle dma-ranges for inbound
>> memory accesses. These two functionalities are added in subsequent
>> commits.
>>
>> The PCIe block contains an MDIO interface. This is a local interface
>> only accessible by the PCIe controller. It cannot be used or shared
>> by any other HW. As such, the small amount of code for this
>> controller is included in this driver as there is little upside to put
>> it elsewhere.
>>
>> Signed-off-by: Jim Quinlan <jim2101024@gmail.com>
>> ---
>> drivers/pci/host/Kconfig | 9 +
>> drivers/pci/host/Makefile | 1 +
>> drivers/pci/host/pcie-brcmstb.c | 1124 +++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 1134 insertions(+)
>> create mode 100644 drivers/pci/host/pcie-brcmstb.c
>>
>> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
>> index b868803..751463e 100644
>> --- a/drivers/pci/host/Kconfig
>> +++ b/drivers/pci/host/Kconfig
>> @@ -220,4 +220,13 @@ config VMD
>> To compile this driver as a module, choose M here: the
>> module will be called vmd.
>>
>> +config PCIE_BRCMSTB
>> + tristate "Broadcom Brcmstb PCIe platform host driver"
>> + depends on ARCH_BRCMSTB || BMIPS_GENERIC
>> + depends on OF
>> + depends on SOC_BRCMSTB
>> + default ARCH_BRCMSTB || BMIPS_GENERIC
>> + help
>> + Adds support for Broadcom Settop Box PCIe host controller.
>> +
>> endmenu
>> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
>> index 1238278..a8b9923 100644
>> --- a/drivers/pci/host/Makefile
>> +++ b/drivers/pci/host/Makefile
>> @@ -21,6 +21,7 @@ obj-$(CONFIG_PCIE_ROCKCHIP) += pcie-rockchip.o
>> obj-$(CONFIG_PCIE_MEDIATEK) += pcie-mediatek.o
>> obj-$(CONFIG_PCIE_TANGO_SMP8759) += pcie-tango.o
>> obj-$(CONFIG_VMD) += vmd.o
>> +obj-$(CONFIG_PCIE_BRCMSTB) += pcie-brcmstb.o
>>
>> # The following drivers are for devices that use the generic ACPI
>> # pci_root.c driver but don't support standard ECAM config access.
>> diff --git a/drivers/pci/host/pcie-brcmstb.c b/drivers/pci/host/pcie-brcmstb.c
>> new file mode 100644
>> index 0000000..d8a8f7a
>> --- /dev/null
>> +++ b/drivers/pci/host/pcie-brcmstb.c
>> @@ -0,0 +1,1124 @@
>> +/*
>> + * Copyright (C) 2009 - 2017 Broadcom
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/compiler.h>
>> +#include <linux/delay.h>
>> +#include <linux/init.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +#include <linux/ioport.h>
>> +#include <linux/irqdomain.h>
>> +#include <linux/kernel.h>
>> +#include <linux/list.h>
>> +#include <linux/log2.h>
>> +#include <linux/module.h>
>> +#include <linux/of_address.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/of_pci.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/pci.h>
>> +#include <linux/printk.h>
>> +#include <linux/sizes.h>
>> +#include <linux/slab.h>
>> +#include <soc/brcmstb/memory_api.h>
>> +#include <linux/string.h>
>> +#include <linux/types.h>
>> +
>> +/* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
>> +#define BRCM_PCIE_CAP_REGS 0x00ac
>
> Add a blank line before multi-line comments.
>
>> +/*
>> + * Broadcom Settop Box PCIE Register Offsets. The names are from
>> + * the chip's RDB and we use them here so that a script can correlate
>> + * this code and the RDB to prevent discrepancies.
>
> Use "PCIe" capitalization in English text and messages.
>
>> + */
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3 0x043c
>> +#define PCIE_RC_DL_MDIO_ADDR 0x1100
>> +#define PCIE_RC_DL_MDIO_WR_DATA 0x1104
>> +#define PCIE_RC_DL_MDIO_RD_DATA 0x1108
>> +#define PCIE_MISC_MISC_CTRL 0x4008
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO 0x400c
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI 0x4010
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO 0x402c
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO 0x4034
>> +#define PCIE_MISC_RC_BAR2_CONFIG_HI 0x4038
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO 0x403c
>> +#define PCIE_MISC_PCIE_CTRL 0x4064
>> +#define PCIE_MISC_PCIE_STATUS 0x4068
>> +#define PCIE_MISC_REVISION 0x406c
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT 0x4070
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI 0x4080
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI 0x4084
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204
>> +#define PCIE_INTR2_CPU_BASE 0x4300
>> +
>> +/*
>> + * Broadcom Settop Box PCIE Register Field shift and mask info. The
>> + * names are from the chip's RDB and we use them here so that a script
>> + * can correlate this code and the RDB to prevent discrepancies.
>> + */
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
>> +#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_SHIFT 0x2
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_MASK 0xffffff
>> +#define PCIE_RC_CFG_PRIV1_ID_VAL3_CLASS_CODE_SHIFT 0x0
>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_MASK 0x1000
>> +#define PCIE_MISC_MISC_CTRL_SCB_ACCESS_EN_SHIFT 0xc
>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_MASK 0x2000
>> +#define PCIE_MISC_MISC_CTRL_CFG_READ_UR_MODE_SHIFT 0xd
>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_MASK 0x300000
>> +#define PCIE_MISC_MISC_CTRL_MAX_BURST_SIZE_SHIFT 0x14
>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_MASK 0xf8000000
>> +#define PCIE_MISC_MISC_CTRL_SCB0_SIZE_SHIFT 0x1b
>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_MASK 0x7c00000
>> +#define PCIE_MISC_MISC_CTRL_SCB1_SIZE_SHIFT 0x16
>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_MASK 0x1f
>> +#define PCIE_MISC_MISC_CTRL_SCB2_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_MASK 0x1f
>> +#define PCIE_MISC_RC_BAR1_CONFIG_LO_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_MASK 0x1f
>> +#define PCIE_MISC_RC_BAR2_CONFIG_LO_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_MASK 0x1f
>> +#define PCIE_MISC_RC_BAR3_CONFIG_LO_SIZE_SHIFT 0x0
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_MASK 0x4
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_PERSTB_SHIFT 0x2
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_MASK 0x1
>> +#define PCIE_MISC_PCIE_CTRL_PCIE_L23_REQUEST_SHIFT 0x0
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_MASK 0x80
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PORT_SHIFT 0x7
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_MASK 0x20
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_DL_ACTIVE_SHIFT 0x5
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_MASK 0x10
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_PHYLINKUP_SHIFT 0x4
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_MASK 0x40
>> +#define PCIE_MISC_PCIE_STATUS_PCIE_LINK_IN_L23_SHIFT 0x6
>> +#define PCIE_MISC_REVISION_MAJMIN_MASK 0xffff
>> +#define PCIE_MISC_REVISION_MAJMIN_SHIFT 0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_MASK 0xfff00000
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_LIMIT_SHIFT 0x14
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_MASK 0xfff0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_BASE_SHIFT 0x4
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS 0xc
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_MASK 0xff
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI_BASE_SHIFT 0x0
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_MASK 0xff
>> +#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI_LIMIT_SHIFT 0x0
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_SHIFT 0x1
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000
>> +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_SHIFT 0x1b
>> +#define PCIE_RGR1_SW_INIT_1_PERST_MASK 0x1
>> +#define PCIE_RGR1_SW_INIT_1_PERST_SHIFT 0x0
>> +
>> +#define BRCM_NUM_PCIE_OUT_WINS 0x4
>> +#define BRCM_MAX_SCB 0x4
>> +
>> +#define BRCM_MSI_TARGET_ADDR_LT_4GB 0x0fffffffcULL
>> +#define BRCM_MSI_TARGET_ADDR_GT_4GB 0xffffffffcULL
>> +
>> +#define BURST_SIZE_128 0
>> +#define BURST_SIZE_256 1
>> +#define BURST_SIZE_512 2
>> +
>> +/* Offsets from PCIE_INTR2_CPU_BASE */
>> +#define STATUS 0x0
>> +#define SET 0x4
>> +#define CLR 0x8
>> +#define MASK_STATUS 0xc
>> +#define MASK_SET 0x10
>> +#define MASK_CLR 0x14
>> +
>> +#define PCIE_BUSNUM_SHIFT 20
>> +#define PCIE_SLOT_SHIFT 15
>> +#define PCIE_FUNC_SHIFT 12
>> +
>> +#if defined(__BIG_ENDIAN)
>> +#define DATA_ENDIAN 2 /* PCIe->DDR inbound accesses */
>> +#define MMIO_ENDIAN 2 /* CPU->PCIe outbound accesses */
>> +#else
>> +#define DATA_ENDIAN 0
>> +#define MMIO_ENDIAN 0
>> +#endif
>> +
>> +#define MDIO_PORT0 0x0
>> +#define MDIO_DATA_MASK 0x7fffffff
>> +#define MDIO_DATA_SHIFT 0x0
>> +#define MDIO_PORT_MASK 0xf0000
>> +#define MDIO_PORT_SHIFT 0x16
>> +#define MDIO_REGAD_MASK 0xffff
>> +#define MDIO_REGAD_SHIFT 0x0
>> +#define MDIO_CMD_MASK 0xfff00000
>> +#define MDIO_CMD_SHIFT 0x14
>> +#define MDIO_CMD_READ 0x1
>> +#define MDIO_CMD_WRITE 0x0
>> +#define MDIO_DATA_DONE_MASK 0x80000000
>> +#define MDIO_RD_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 1 : 0)
>> +#define MDIO_WT_DONE(x) (((x) & MDIO_DATA_DONE_MASK) ? 0 : 1)
>> +#define SSC_REGS_ADDR 0x1100
>> +#define SET_ADDR_OFFSET 0x1f
>> +#define SSC_CNTL_OFFSET 0x2
>> +#define SSC_CNTL_OVRD_EN_MASK 0x8000
>> +#define SSC_CNTL_OVRD_EN_SHIFT 0xf
>> +#define SSC_CNTL_OVRD_VAL_MASK 0x4000
>> +#define SSC_CNTL_OVRD_VAL_SHIFT 0xe
>> +#define SSC_STATUS_OFFSET 0x1
>> +#define SSC_STATUS_SSC_MASK 0x400
>> +#define SSC_STATUS_SSC_SHIFT 0xa
>> +#define SSC_STATUS_PLL_LOCK_MASK 0x800
>> +#define SSC_STATUS_PLL_LOCK_SHIFT 0xb
>> +
>> +#define IDX_ADDR(pcie) \
>> + ((pcie)->reg_offsets[EXT_CFG_INDEX])
>> +#define DATA_ADDR(pcie) \
>> + ((pcie)->reg_offsets[EXT_CFG_DATA])
>> +#define PCIE_RGR1_SW_INIT_1(pcie) \
>> + ((pcie)->reg_offsets[RGR1_SW_INIT_1])
>> +
>> +enum {
>> + RGR1_SW_INIT_1,
>> + EXT_CFG_INDEX,
>> + EXT_CFG_DATA,
>> +};
>> +
>> +enum {
>> + RGR1_SW_INIT_1_INIT_MASK,
>> + RGR1_SW_INIT_1_INIT_SHIFT,
>> + RGR1_SW_INIT_1_PERST_MASK,
>> + RGR1_SW_INIT_1_PERST_SHIFT,
>> +};
>> +
>> +enum pcie_type {
>> + BCM7425,
>> + BCM7435,
>> + GENERIC,
>> + BCM7278,
>> +};
>> +
>> +struct brcm_window {
>> + dma_addr_t pcie_addr;
>> + phys_addr_t cpu_addr;
>> + dma_addr_t size;
>> +};
>> +
>> +/* Internal PCIe Host Controller Information.*/
>> +struct brcm_pcie {
>> + struct list_head list;
>> + struct device *dev;
>> + void __iomem *base;
>> + struct list_head resources;
>> + int irq;
>> + struct clk *clk;
>> + struct pci_bus *root_bus;
>> + struct device_node *dn;
>> + int id;
>> + bool suspended;
>> + int num_out_wins;
>> + bool ssc;
>> + int gen;
>> + struct brcm_window out_wins[BRCM_NUM_PCIE_OUT_WINS];
>> + unsigned int rev;
>> + const int *reg_offsets;
>> + const int *reg_field_info;
>> + enum pcie_type type;
>> +};
>> +
>> +struct pcie_cfg_data {
>> + const int *reg_field_info;
>> + const int *offsets;
>> + const enum pcie_type type;
>> +};
>> +
>> +static const int pcie_reg_field_info[] = {
>> + [RGR1_SW_INIT_1_INIT_MASK] = 0x2,
>> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x1,
>> +};
>> +
>> +static const int pcie_reg_field_info_bcm7278[] = {
>> + [RGR1_SW_INIT_1_INIT_MASK] = 0x1,
>> + [RGR1_SW_INIT_1_INIT_SHIFT] = 0x0,
>> +};
>> +
>> +static const int pcie_offset_bcm7425[] = {
>> + [RGR1_SW_INIT_1] = 0x8010,
>> + [EXT_CFG_INDEX] = 0x8300,
>> + [EXT_CFG_DATA] = 0x8304,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7425_cfg = {
>> + .reg_field_info = pcie_reg_field_info,
>> + .offsets = pcie_offset_bcm7425,
>> + .type = BCM7425,
>> +};
>> +
>> +static const int pcie_offsets[] = {
>> + [RGR1_SW_INIT_1] = 0x9210,
>> + [EXT_CFG_INDEX] = 0x9000,
>> + [EXT_CFG_DATA] = 0x9004,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7435_cfg = {
>> + .reg_field_info = pcie_reg_field_info,
>> + .offsets = pcie_offsets,
>> + .type = BCM7435,
>> +};
>> +
>> +static const struct pcie_cfg_data generic_cfg = {
>> + .reg_field_info = pcie_reg_field_info,
>> + .offsets = pcie_offsets,
>> + .type = GENERIC,
>> +};
>> +
>> +static const int pcie_offset_bcm7278[] = {
>> + [RGR1_SW_INIT_1] = 0xc010,
>> + [EXT_CFG_INDEX] = 0x9000,
>> + [EXT_CFG_DATA] = 0x9004,
>> +};
>> +
>> +static const struct pcie_cfg_data bcm7278_cfg = {
>> + .reg_field_info = pcie_reg_field_info_bcm7278,
>> + .offsets = pcie_offset_bcm7278,
>> + .type = BCM7278,
>> +};
>> +
>> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
>> + int where);
>> +
>> +static struct pci_ops brcm_pcie_ops = {
>> + .map_bus = brcm_pcie_map_conf,
>> + .read = pci_generic_config_read,
>> + .write = pci_generic_config_write,
>> +};
>> +
>> +#if defined(CONFIG_MIPS)
>> +/* Broadcom MIPs HW implicitly does the swapping if necessary */
>> +#define bcm_readl(a) __raw_readl(a)
>> +#define bcm_writel(d, a) __raw_writel(d, a)
>> +#define bcm_readw(a) __raw_readw(a)
>> +#define bcm_writew(d, a) __raw_writew(d, a)
>> +#else
>> +#define bcm_readl(a) readl(a)
>> +#define bcm_writel(d, a) writel(d, a)
>> +#define bcm_readw(a) readw(a)
>> +#define bcm_writew(d, a) writew(d, a)
>> +#endif
>> +
>> +/*
>> + * These macros are designed to sxtract/insert fields to host controller's
>> + * register set.
>
> s/are designed to s/ e/ (I assume they actually *do* extract/insert)
>
>> + */
>> +#define RD_FLD(base, reg, field) \
>> + rd_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT)
>> +#define WR_FLD(base, reg, field, val) \
>> + wr_fld(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
>> +#define WR_FLD_RB(base, reg, field, val) \
>> + wr_fld_rb(base + reg, reg##_##field##_MASK, reg##_##field##_SHIFT, val)
>> +#define WR_FLD_WITH_OFFSET(base, off, reg, field, val) \
>> + wr_fld(base + reg + off, reg##_##field##_MASK, \
>> + reg##_##field##_SHIFT, val)
>> +#define EXTRACT_FIELD(val, reg, field) \
>> + ((val & reg##_##field##_MASK) >> reg##_##field##_SHIFT)
>> +#define INSERT_FIELD(val, reg, field, field_val) \
>> + ((val & ~reg##_##field##_MASK) | \
>> + (reg##_##field##_MASK & (field_val << reg##_##field##_SHIFT)))
>> +
>> +static struct list_head brcm_pcie = LIST_HEAD_INIT(brcm_pcie);
>> +static phys_addr_t scb_size[BRCM_MAX_SCB];
>> +static int num_memc;
>> +static DEFINE_MUTEX(brcm_pcie_lock);
>> +
>> +static u32 rd_fld(void __iomem *p, u32 mask, int shift)
>> +{
>> + return (bcm_readl(p) & mask) >> shift;
>> +}
>> +
>> +static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
>> +{
>> + u32 reg = bcm_readl(p);
>> +
>> + reg = (reg & ~mask) | ((val << shift) & mask);
>> + bcm_writel(reg, p);
>> +}
>> +
>> +static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
>> +{
>> + wr_fld(p, mask, shift, val);
>> + (void)bcm_readl(p);
>> +}
>> +
>> +static const char *link_speed_to_str(int s)
>> +{
>> + switch (s) {
>> + case 1:
>> + return "2.5";
>> + case 2:
>> + return "5.0";
>> + case 3:
>> + return "8.0";
>> + default:
>> + break;
>> + }
>> + return "???";
>> +}
>> +
>> +/*
>> + * The roundup_pow_of_two() from log2.h invokes
>> + * __roundup_pow_of_two(unsigned long), but we really need a
>> + * such a function to take a native u64 since unsigned long
>> + * is 32 bits on some configurations. So we provide this helper
>> + * function below.
>> + */
>> +static u64 roundup_pow_of_two_64(u64 n)
>> +{
>> + return 1ULL << fls64(n - 1);
>> +}
>> +
>> +/*
>> + * This is to convert the size of the inbound bar region to the
>> + * non-liniear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
>
> s/bar/BAR/ (This doesn't sound like a BAR in the PCI spec sense, but if
> that's what you call it, might as well spell it as the acronym)
>
> s/non-liniear/non-linear/
>
>> + */
>> +int encode_ibar_size(u64 size)
>> +{
>> + int log2_in = ilog2(size);
>> +
>> + if (log2_in >= 12 && log2_in <= 15)
>> + /* Covers 4KB to 32KB (inclusive) */
>> + return (log2_in - 12) + 0x1c;
>> + else if (log2_in >= 16 && log2_in <= 37)
>> + /* Covers 64KB to 32GB, (inclusive) */
>> + return log2_in - 15;
>> + /* Something is awry so disable */
>> + return 0;
>> +}
>> +
>> +static u32 mdio_form_pkt(int port, int regad, int cmd)
>> +{
>> + u32 pkt = 0;
>> +
>> + pkt |= (port << MDIO_PORT_SHIFT) & MDIO_PORT_MASK;
>> + pkt |= (regad << MDIO_REGAD_SHIFT) & MDIO_REGAD_MASK;
>> + pkt |= (cmd << MDIO_CMD_SHIFT) & MDIO_CMD_MASK;
>> +
>> + return pkt;
>> +}
>> +
>> +/* negative return value indicates error */
>> +static int mdio_read(void __iomem *base, u8 port, u8 regad)
>> +{
>> + int tries;
>> + u32 data;
>> +
>> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_READ),
>> + base + PCIE_RC_DL_MDIO_ADDR);
>> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>> +
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>> + for (tries = 0; !MDIO_RD_DONE(data) && tries < 10; tries++) {
>> + udelay(10);
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
>> + }
>> +
>> + return MDIO_RD_DONE(data)
>> + ? (data & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT
>> + : -EIO;
>> +}
>> +
>> +/* negative return value indicates error */
>> +static int mdio_write(void __iomem *base, u8 port, u8 regad, u16 wrdata)
>> +{
>> + int tries;
>> + u32 data;
>> +
>> + bcm_writel(mdio_form_pkt(port, regad, MDIO_CMD_WRITE),
>> + base + PCIE_RC_DL_MDIO_ADDR);
>> + bcm_readl(base + PCIE_RC_DL_MDIO_ADDR);
>> + bcm_writel(MDIO_DATA_DONE_MASK | wrdata,
>> + base + PCIE_RC_DL_MDIO_WR_DATA);
>> +
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>> + for (tries = 0; !MDIO_WT_DONE(data) && tries < 10; tries++) {
>> + udelay(10);
>> + data = bcm_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
>> + }
>> +
>> + return MDIO_WT_DONE(data) ? 0 : -EIO;
>> +}
>> +
>> +/* configures device for ssc mode; negative return value indicates error */
>
> I guess "ssc" means Spread Spectrum Clocking? Maybe spell out the
> first occurrence and spell as acronym in English text?
>
>> +static int set_ssc(void __iomem *base)
>> +{
>> + int tmp;
>> + u16 wrdata;
>> + int pll, ssc;
>> +
>> + tmp = mdio_write(base, MDIO_PORT0, SET_ADDR_OFFSET, SSC_REGS_ADDR);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + tmp = mdio_read(base, MDIO_PORT0, SSC_CNTL_OFFSET);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + wrdata = INSERT_FIELD(tmp, SSC_CNTL_OVRD, EN, 1);
>> + wrdata = INSERT_FIELD(wrdata, SSC_CNTL_OVRD, VAL, 1);
>> + tmp = mdio_write(base, MDIO_PORT0, SSC_CNTL_OFFSET, wrdata);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + usleep_range(1000, 2000);
>> + tmp = mdio_read(base, MDIO_PORT0, SSC_STATUS_OFFSET);
>> + if (tmp < 0)
>> + return tmp;
>> +
>> + ssc = EXTRACT_FIELD(tmp, SSC_STATUS, SSC);
>> + pll = EXTRACT_FIELD(tmp, SSC_STATUS, PLL_LOCK);
>> +
>> + return (ssc && pll) ? 0 : -EIO;
>> +}
>> +
>> +/* limits operation to a specific generation (1, 2, or 3) */
>> +static void set_gen(void __iomem *base, int gen)
>> +{
>> + u32 lnkcap = bcm_readl(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
>> + u16 lnkctl2 = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
>> +
>> + lnkcap = (lnkcap & ~PCI_EXP_LNKCAP_SLS) | gen;
>> + bcm_writel(lnkcap, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCAP);
>> +
>> + lnkctl2 = (lnkctl2 & ~0xf) | gen;
>> + bcm_writew(lnkctl2, base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2);
>> +}
>> +
>> +static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie,
>> + unsigned int win, phys_addr_t cpu_addr,
>> + dma_addr_t pcie_addr, dma_addr_t size)
>> +{
>> + void __iomem *base = pcie->base;
>> + phys_addr_t cpu_addr_mb, limit_addr_mb;
>> + u32 tmp;
>> +
>> + /* Set the base of the pcie_addr window */
>> + bcm_writel(lower_32_bits(pcie_addr) + MMIO_ENDIAN,
>> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO + (win * 8));
>> + bcm_writel(upper_32_bits(pcie_addr),
>> + base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI + (win * 8));
>> +
>> + cpu_addr_mb = cpu_addr >> 20;
>> + limit_addr_mb = (cpu_addr + size - 1) >> 20;
>> +
>> + /* Write the addr base low register */
>> + WR_FLD_WITH_OFFSET(base, (win * 4),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>> + BASE, cpu_addr_mb);
>> + /* Write the addr limit low register */
>> + WR_FLD_WITH_OFFSET(base, (win * 4),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT,
>> + LIMIT, limit_addr_mb);
>> +
>> + if (pcie->type != BCM7435 && pcie->type != BCM7425) {
>> + /* Write the cpu addr high register */
>> + tmp = (u32)(cpu_addr_mb >>
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>> + WR_FLD_WITH_OFFSET(base, (win * 8),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_HI,
>> + BASE, tmp);
>> + /* Write the cpu limit high register */
>> + tmp = (u32)(limit_addr_mb >>
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT_NUM_MASK_BITS);
>> + WR_FLD_WITH_OFFSET(base, (win * 8),
>> + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LIMIT_HI,
>> + LIMIT, tmp);
>> + }
>> +}
>> +
>> +/* Configuration space read/write support */
>> +static int cfg_index(int busnr, int devfn, int reg)
>> +{
>> + return ((PCI_SLOT(devfn) & 0x1f) << PCIE_SLOT_SHIFT)
>> + | ((PCI_FUNC(devfn) & 0x07) << PCIE_FUNC_SHIFT)
>> + | (busnr << PCIE_BUSNUM_SHIFT)
>> + | (reg & ~3);
>> +}
>> +
>> +static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
>> +
>> + return !!EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PORT);
>> +}
>> +
>> +static bool brcm_pcie_link_up(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + u32 val = bcm_readl(base + PCIE_MISC_PCIE_STATUS);
>> + u32 dla = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_DL_ACTIVE);
>> + u32 plu = EXTRACT_FIELD(val, PCIE_MISC_PCIE_STATUS, PCIE_PHYLINKUP);
>> +
>> + return (dla && plu) ? true : false;
>> +}
>> +
>> +static bool brcm_pcie_valid_device(struct brcm_pcie *pcie, struct pci_bus *bus,
>> + int dev)
>> +{
>> + if (pci_is_root_bus(bus)) {
>> + if (dev > 0)
>> + return false;
>> + } else {
>> + /* If there is no link, then there is no device */
>> + if (!brcm_pcie_link_up(pcie))
>> + return false;
>
> This is racy, since the link can go down after you check but before
> you do the config access. I assume your hardware can deal with a
> config access that targets a link that is down?
Yes, that can happen but there is really nothing that can be done if
the link goes down in that vulnerability window. What do you suggest
doing?
>
>> + }
>> +
>> + return true;
>> +}
>> +
>> +static void __iomem *brcm_pcie_map_conf(struct pci_bus *bus, unsigned int devfn,
>> + int where)
>> +{
>> + struct brcm_pcie *pcie = bus->sysdata;
>> + void __iomem *base = pcie->base;
>> + int idx;
>> +
>> + if (!brcm_pcie_valid_device(pcie, bus, PCI_SLOT(devfn)))
>> + return NULL;
>> +
>> + /* Accesses to the RC go right to the RC registers */
>> + if (pci_is_root_bus(bus))
>> + return base + where;
>> +
>> + /* For devices, write to the config space index register */
>> + idx = cfg_index(bus->number, devfn, where);
>> + bcm_writel(idx, pcie->base + IDX_ADDR(pcie));
>> + return base + DATA_ADDR(pcie) + (where & 0x3);
>
> I guess this is protected by a higher-level config access lock?
>
>> +}
>> +
>> +static inline void brcm_pcie_bridge_sw_init_set(struct brcm_pcie *pcie,
>> + unsigned int val)
>> +{
>> + unsigned int offset;
>> + unsigned int shift = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_SHIFT];
>> + u32 mask = pcie->reg_field_info[RGR1_SW_INIT_1_INIT_MASK];
>> +
>> + if (pcie->type != BCM7278) {
>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
>> + val);
>> + } else if (of_machine_is_compatible("brcm,bcm7278a0")) {
>> + /*
>> + * The two PCIe instances on 7278a0 are not even consistent with
>> + * respect to each other for internal offsets, here we offset
>> + * by 0x14000 + RGR1_SW_INIT_1's relative offset to account for
>> + * that.
>> + */
>> + offset = pcie->id ? 0x14010 : pcie->reg_offsets[RGR1_SW_INIT_1];
>> + wr_fld_rb(pcie->base + offset, mask, shift, val);
>> + } else {
>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie), mask, shift,
>> + val);
>> + }
>> +}
>> +
>> +static inline void brcm_pcie_perst_set(struct brcm_pcie *pcie,
>> + unsigned int val)
>> +{
>> + if (pcie->type != BCM7278)
>> + wr_fld_rb(pcie->base + PCIE_RGR1_SW_INIT_1(pcie),
>> + PCIE_RGR1_SW_INIT_1_PERST_MASK,
>> + PCIE_RGR1_SW_INIT_1_PERST_SHIFT, val);
>> + else
>> + /* Assert = 0, de-assert = 1 on 7278 */
>> + WR_FLD_RB(pcie->base, PCIE_MISC_PCIE_CTRL, PCIE_PERSTB, !val);
>> +}
>> +
>> +static int brcm_pcie_add_controller(struct brcm_pcie *pcie)
>> +{
>> + mutex_lock(&brcm_pcie_lock);
>> + list_add_tail(&pcie->list, &brcm_pcie);
>> + mutex_unlock(&brcm_pcie_lock);
>> +
>> + return 0;
>> +}
>> +
>> +static void brcm_pcie_remove_controller(struct brcm_pcie *pcie)
>> +{
>> + struct list_head *pos, *q;
>> + struct brcm_pcie *tmp;
>> +
>> + mutex_lock(&brcm_pcie_lock);
>> + list_for_each_safe(pos, q, &brcm_pcie) {
>> + tmp = list_entry(pos, struct brcm_pcie, list);
>> + if (tmp == pcie) {
>> + list_del(pos);
>> + if (list_empty(&brcm_pcie))
>> + num_memc = 0;
>> + break;
>> + }
>> + }
>> + mutex_unlock(&brcm_pcie_lock);
>
> I'm missing something. I don't see that num_memc is ever set to
> anything *other* than zero.
The num_memc is set and used in the dma commit. I will remove its
declaration from this commit.
> This pattern of keeping a list of controllers is highly unusual and
> needs some explanation.
I think I can remove the list but still need brcm_pcie_lock.
>
>> +}
>> +
>> +static int brcm_pcie_parse_request_of_pci_ranges(struct brcm_pcie *pcie)
>> +{
>> + struct resource_entry *win;
>> + int ret;
>> +
>> + ret = of_pci_get_host_bridge_resources(pcie->dn, 0, 0xff,
>> + &pcie->resources, NULL);
>> + if (ret) {
>> + dev_err(pcie->dev, "failed to get host resources\n");
>> + return ret;
>> + }
>> +
>> + resource_list_for_each_entry(win, &pcie->resources) {
>> + struct resource *parent, *res = win->res;
>> + dma_addr_t offset = (dma_addr_t)win->offset;
>> +
>> + if (resource_type(res) == IORESOURCE_IO) {
>> + parent = &ioport_resource;
>> + } else if (resource_type(res) == IORESOURCE_MEM) {
>> + if (pcie->num_out_wins >= BRCM_NUM_PCIE_OUT_WINS) {
>> + dev_err(pcie->dev, "too many outbound wins\n");
>> + return -EINVAL;
>> + }
>> + pcie->out_wins[pcie->num_out_wins].cpu_addr
>> + = (phys_addr_t)res->start;
>> + pcie->out_wins[pcie->num_out_wins].pcie_addr
>> + = (dma_addr_t)(res->start
>> + - (phys_addr_t)offset);
>> + pcie->out_wins[pcie->num_out_wins].size
>> + = (dma_addr_t)(res->end - res->start + 1);
>> + pcie->num_out_wins++;
>> + parent = &iomem_resource;
>> + } else {
>> + continue;
>> + }
>> +
>> + ret = devm_request_resource(pcie->dev, parent, res);
>> + if (ret) {
>> + dev_err(pcie->dev, "failed to get res %pR\n", res);
>> + return ret;
>> + }
>> + }
>> + return 0;
>> +}
>> +
>> +static int brcm_pcie_setup(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + unsigned int scb_size_val;
>> + u64 rc_bar2_size = 0, rc_bar2_offset = 0, total_mem_size = 0;
>
> Unnecessary initializations (at least of rc_bar2_size, I didn't check
> the rest).
>
> Add
>
> struct device *dev = pcie->dev;
>
> then use it below.
>
>> + u32 tmp, burst;
>> + int i, j, ret, limit;
>> + u16 nlw, cls, lnksta;
>> + bool ssc_good = false;
>> +
>> + /* reset the bridge and the endpoint device */
>> + /* field: PCIE_BRIDGE_SW_INIT = 1 */
>
> Not sure what these "field: ..." comments mean. Are they for some
> automated tool? To a human, it looks like they repeat what the code
> does.
>
>> + brcm_pcie_bridge_sw_init_set(pcie, 1);
>> +
>> + /* field: PCIE_SW_PERST = 1, on 7278, we start de-asserted already */
>> + if (pcie->type != BCM7278)
>> + brcm_pcie_perst_set(pcie, 1);
>> +
>> + usleep_range(100, 200);
>> +
>> + /* take the bridge out of reset */
>> + /* field: PCIE_BRIDGE_SW_INIT = 0 */
>> + brcm_pcie_bridge_sw_init_set(pcie, 0);
>> +
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>> + /* wait for serdes to be stable */
>> + usleep_range(100, 200);
>> +
>> + /* Grab the PCIe hw revision number */
>> + tmp = bcm_readl(base + PCIE_MISC_REVISION);
>> + pcie->rev = EXTRACT_FIELD(tmp, PCIE_MISC_REVISION, MAJMIN);
>> +
>> + /* Set SCB_MAX_BURST_SIZE, CFG_READ_UR_MODE, SCB_ACCESS_EN */
>> + tmp = INSERT_FIELD(0, PCIE_MISC_MISC_CTRL, SCB_ACCESS_EN, 1);
>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, CFG_READ_UR_MODE, 1);
>> + burst = (pcie->type == GENERIC || pcie->type == BCM7278)
>> + ? BURST_SIZE_512 : BURST_SIZE_256;
>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_MISC_CTRL, MAX_BURST_SIZE, burst);
>> + bcm_writel(tmp, base + PCIE_MISC_MISC_CTRL);
>> +
>> + /*
>> + * Set up inbound memory view for the EP (called RC_BAR2,
>> + * not to be confused with the BARs that are advertised by
>> + * the EP).
>> + */
>> + for (i = 0; i < num_memc; i++)
>> + total_mem_size += scb_size[i];
>> +
>> + /*
>> + * The PCIe host controller by design must set the inbound
>> + * viewport to be a contiguous arrangement of all of the
>> + * system's memory. In addition, its size mut be a power of
>> + * two. To further complicate matters, the viewport must
>> + * start on a pcie-address that is aligned on a multiple of its
>> + * size. If a portion of the viewport does not represent
>> + * system memory -- e.g. 3GB of memory requires a 4GB viewport
>> + * -- we can map the outbound memory in or after 3GB and even
>> + * though the viewport will overlap the outbound memory the
>> + * controller will know to send outbound memory downstream and
>> + * everything else upstream.
>> + */
>> + rc_bar2_size = roundup_pow_of_two_64(total_mem_size);
>> +
>> + /*
>> + * Set simple configuration based on memory sizes
>> + * only. We always start the viewport at address 0.
>> + */
>> + rc_bar2_offset = 0;
>> +
>> + tmp = lower_32_bits(rc_bar2_offset);
>> + tmp = INSERT_FIELD(tmp, PCIE_MISC_RC_BAR2_CONFIG_LO, SIZE,
>> + encode_ibar_size(rc_bar2_size));
>> + bcm_writel(tmp, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
>> + bcm_writel(upper_32_bits(rc_bar2_offset),
>> + base + PCIE_MISC_RC_BAR2_CONFIG_HI);
>> +
>> + /* field: SCB0_SIZE, default = 0xf (1 GB) */
>> + scb_size_val = scb_size[0]
>> + ? ilog2(scb_size[0]) - 15 : 0xf;
>> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB0_SIZE, scb_size_val);
>> +
>> + /* field: SCB1_SIZE, default = 0xf (1 GB) */
>> + if (num_memc > 1) {
>> + scb_size_val = scb_size[1]
>> + ? ilog2(scb_size[1]) - 15 : 0xf;
>> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB1_SIZE, scb_size_val);
>> + }
>> +
>> + /* field: SCB2_SIZE, default = 0xf (1 GB) */
>> + if (num_memc > 2) {
>> + scb_size_val = scb_size[2]
>> + ? ilog2(scb_size[2]) - 15 : 0xf;
>> + WR_FLD(base, PCIE_MISC_MISC_CTRL, SCB2_SIZE, scb_size_val);
>> + }
>> +
>> + /* disable the PCIe->GISB memory window (RC_BAR1) */
>> + WR_FLD(base, PCIE_MISC_RC_BAR1_CONFIG_LO, SIZE, 0);
>> +
>> + /* disable the PCIe->SCB memory window (RC_BAR3) */
>> + WR_FLD(base, PCIE_MISC_RC_BAR3_CONFIG_LO, SIZE, 0);
>> +
>> + if (!pcie->suspended) {
>> + /* clear any interrupts we find on boot */
>> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + CLR);
>> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + CLR);
>> + }
>> +
>> + /* Mask all interrupts since we are not handling any yet */
>> + bcm_writel(0xffffffff, base + PCIE_INTR2_CPU_BASE + MASK_SET);
>> + (void)bcm_readl(base + PCIE_INTR2_CPU_BASE + MASK_SET);
>> +
>> + if (pcie->gen)
>> + set_gen(base, pcie->gen);
>> +
>> + /* take the EP device out of reset */
>> + /* field: PCIE_SW_PERST = 0 */
>> + brcm_pcie_perst_set(pcie, 0);
>
> <raises eyebrows> Take the *EP* out of reset? The host controller
> driver shouldn't be touching an EP directly. Maybe the comment
> doesn't match what the code actually does.
>
>> +
>> + /*
>> + * Give the RC/EP time to wake up, before trying to configure RC.
>> + * Intermittently check status for link-up, up to a total of 100ms
>> + * when we don't know if the device is there, and up to 1000ms if
>> + * we do know the device is there.
>> + */
>> + limit = pcie->suspended ? 1000 : 100;
>> + for (i = 1, j = 0; j < limit && !brcm_pcie_link_up(pcie);
>> + j += i, i = i * 2)
>> + msleep(i + j > limit ? limit - j : i);
>> +
>> + if (!brcm_pcie_link_up(pcie)) {
>> + dev_info(pcie->dev, "link down\n");
>> + return -ENODEV;
>> + }
>> +
>> + if (!brcm_pcie_rc_mode(pcie)) {
>> + dev_err(pcie->dev, "PCIe misconfigured; is in EP mode\n");
>> + return -EINVAL;
>> + }
>> +
>> + for (i = 0; i < pcie->num_out_wins; i++)
>> + brcm_pcie_set_outbound_win(pcie, i, pcie->out_wins[i].cpu_addr,
>> + pcie->out_wins[i].pcie_addr,
>> + pcie->out_wins[i].size);
>> +
>> + /*
>> + * For config space accesses on the RC, show the right class for
>> + * a PCIe-PCIe bridge (the default setting is to be EP mode).
>> + */
>> + WR_FLD_RB(base, PCIE_RC_CFG_PRIV1_ID_VAL3, CLASS_CODE, 0x060400);
>> +
>> + if (pcie->ssc) {
>> + ret = set_ssc(base);
>> + if (ret == 0)
>> + ssc_good = true;
>> + else
>> + dev_err(pcie->dev,
>> + "failed attempt to enter ssc mode\n");
>> + }
>> +
>> + lnksta = bcm_readw(base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKSTA);
>> + cls = lnksta & PCI_EXP_LNKSTA_CLS;
>> + nlw = (lnksta & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
>> + dev_info(pcie->dev, "link up, %s Gbps x%u %s\n", link_speed_to_str(cls),
>> + nlw, ssc_good ? "(SSC)" : "(!SSC)");
>> +
>> + /* PCIe->SCB endian mode for BAR */
>> + /* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
>> + WR_FLD_RB(base, PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1,
>> + ENDIAN_MODE_BAR2, DATA_ENDIAN);
>> +
>> + /*
>> + * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
>> + * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1.
>> + */
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, CLKREQ_DEBUG_ENABLE, 1);
>> +
>> + return 0;
>> +}
>> +
>> +static void enter_l23(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> + int tries, l23;
>> +
>> + /* assert request for L23 */
>> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 1);
>> + /* poll L23 status */
>> + for (tries = 0, l23 = 0; tries < 1000 && !l23; tries++)
>> + l23 = RD_FLD(base, PCIE_MISC_PCIE_STATUS, PCIE_LINK_IN_L23);
>> + if (!l23)
>> + dev_err(pcie->dev, "failed to enter L23\n");
>
> What does "L23" mean? Some power management thing?
>
Yes, it is a low power link state. I will add a comment.
>> +}
>> +
>> +static void turn_off(struct brcm_pcie *pcie)
>> +{
>> + void __iomem *base = pcie->base;
>> +
>> + if (brcm_pcie_link_up(pcie))
>> + enter_l23(pcie);
>> + /* Reset endpoint device */
>> + brcm_pcie_perst_set(pcie, 1);
>> + /* deassert request for L23 in case it was asserted */
>> + WR_FLD_RB(base, PCIE_MISC_PCIE_CTRL, PCIE_L23_REQUEST, 0);
>> + /* SERDES_IDDQ = 1 */
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 1);
>> + /* Shutdown PCIe bridge */
>> + brcm_pcie_bridge_sw_init_set(pcie, 1);
>> +}
>> +
>> +static int brcm_pcie_suspend(struct device *dev)
>> +{
>> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
>> +
>> + turn_off(pcie);
>> + clk_disable_unprepare(pcie->clk);
>> + pcie->suspended = true;
>> +
>> + return 0;
>> +}
>> +
>> +static int brcm_pcie_resume(struct device *dev)
>> +{
>> + struct brcm_pcie *pcie = dev_get_drvdata(dev);
>> + void __iomem *base;
>> + int ret;
>> +
>> + base = pcie->base;
>> + clk_prepare_enable(pcie->clk);
>> +
>> + /* Take bridge out of reset so we can access the SERDES reg */
>
> Some comments above and below spell it "serdes"; here you spell it
> "SERDES".
>
>> + brcm_pcie_bridge_sw_init_set(pcie, 0);
>> +
>> + /* SERDES_IDDQ = 0 */
>> + WR_FLD_RB(base, PCIE_MISC_HARD_PCIE_HARD_DEBUG, SERDES_IDDQ, 0);
>> + /* wait for serdes to be stable */
>> + usleep_range(100, 200);
>> +
>> + ret = brcm_pcie_setup(pcie);
>> + if (ret)
>> + return ret;
>> +
>> + pcie->suspended = false;
>> +
>> + return 0;
>> +}
>> +
>> +static void _brcm_pcie_remove(struct brcm_pcie *pcie)
>> +{
>> + turn_off(pcie);
>> + clk_disable_unprepare(pcie->clk);
>> + clk_put(pcie->clk);
>> + brcm_pcie_remove_controller(pcie);
>> +}
>> +
>> +static int brcm_pcie_remove(struct platform_device *pdev)
>> +{
>> + struct brcm_pcie *pcie = platform_get_drvdata(pdev);
>> +
>> + pci_stop_root_bus(pcie->root_bus);
>> + pci_remove_root_bus(pcie->root_bus);
>> + _brcm_pcie_remove(pcie);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id brcm_pcie_match[] = {
>> + { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
>> + { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
>> + { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
>> + { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
>> + {},
>> +};
>> +MODULE_DEVICE_TABLE(of, brcm_pcie_match);
>> +
>> +static int brcm_pcie_probe(struct platform_device *pdev)
>> +{
>> + struct device_node *dn = pdev->dev.of_node;
>> + const struct of_device_id *of_id;
>> + const struct pcie_cfg_data *data;
>> + int ret;
>> + struct brcm_pcie *pcie;
>> + struct resource *res;
>> + void __iomem *base;
>> + u32 tmp;
>> + struct pci_host_bridge *bridge;
>> + struct pci_bus *child;
>> +
>> + bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie));
>> + if (!bridge)
>> + return -ENOMEM;
>> +
>> + pcie = pci_host_bridge_priv(bridge);
>> + INIT_LIST_HEAD(&pcie->resources);
>> +
>> + of_id = of_match_node(brcm_pcie_match, dn);
>> + if (!of_id) {
>> + dev_err(&pdev->dev, "failed to look up compatible string\n");
>> + return -EINVAL;
>> + }
>> +
>> + if (of_property_read_u32(dn, "dma-ranges", &tmp) == 0) {
>> + dev_err(&pdev->dev, "cannot yet handle dma-ranges\n");
>> + return -EINVAL;
>> + }
>> +
>> + data = of_id->data;
>> + pcie->reg_offsets = data->offsets;
>> + pcie->reg_field_info = data->reg_field_info;
>> + pcie->type = data->type;
>> + pcie->dn = dn;
>> + pcie->dev = &pdev->dev;
>> +
>> + pcie->id = of_get_pci_domain_nr(dn);
>
> Why do you call of_get_pci_domain_nr() directly? No other driver
> does.
We use the domain as the controller number (id). We use the id to
identify and fix a HW bug that only affects the 2nd controller; see
the clause
" } else if (of_machine_is_compatible("brcm,bcm7278a0")) {".
>
>> + if (pcie->id < 0)
>> + return pcie->id;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res)
>> + return -EINVAL;
>> +
>> + base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(base))
>> + return PTR_ERR(base);
>> +
>> + pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
>> + if (IS_ERR(pcie->clk)) {
>> + dev_err(&pdev->dev, "could not get clock\n");
>> + pcie->clk = NULL;
>> + }
>> + pcie->base = base;
>> +
>> + ret = of_pci_get_max_link_speed(dn);
>> + pcie->gen = (ret < 0) ? 0 : ret;
>> +
>> + pcie->ssc = of_property_read_bool(dn, "brcm,enable-ssc");
>> +
>> + ret = irq_of_parse_and_map(pdev->dev.of_node, 0);
>> + if (ret == 0)
>> + /* keep going, as we don't use this intr yet */
>> + dev_warn(pcie->dev, "cannot get pcie interrupt\n");
>> + else
>> + pcie->irq = ret;
>> +
>> + ret = brcm_pcie_parse_request_of_pci_ranges(pcie);
>> + if (ret)
>> + return ret;
>> +
>> + ret = clk_prepare_enable(pcie->clk);
>> + if (ret) {
>> + dev_err(&pdev->dev, "could not enable clock\n");
>> + return ret;
>> + }
>> +
>> + ret = brcm_pcie_add_controller(pcie);
>> + if (ret)
>> + return ret;
>> +
>> + ret = brcm_pcie_setup(pcie);
>> + if (ret)
>> + goto fail;
>> +
>> + list_splice_init(&pcie->resources, &bridge->windows);
>> + bridge->dev.parent = &pdev->dev;
>> + bridge->busnr = 0;
>> + bridge->ops = &brcm_pcie_ops;
>> + bridge->sysdata = pcie;
>> + bridge->map_irq = of_irq_parse_and_map_pci;
>> + bridge->swizzle_irq = pci_common_swizzle;
>> +
>> + ret = pci_scan_root_bus_bridge(bridge);
>> + if (ret < 0) {
>> + dev_err(pcie->dev, "Scanning root bridge failed");
>> + goto fail;
>> + }
>> +
>> + pci_assign_unassigned_bus_resources(bridge->bus);
>> + list_for_each_entry(child, &bridge->bus->children, node)
>> + pcie_bus_configure_settings(child);
>> + pci_bus_add_devices(bridge->bus);
>> + platform_set_drvdata(pdev, pcie);
>> + pcie->root_bus = bridge->bus;
>> +
>> + return 0;
>> +
>> +fail:
>> + _brcm_pcie_remove(pcie);
>> + return ret;
>> +}
>> +
>> +static const struct dev_pm_ops brcm_pcie_pm_ops = {
>> + .suspend_noirq = brcm_pcie_suspend,
>> + .resume_noirq = brcm_pcie_resume,
>> +};
>> +
>> +static struct platform_driver __refdata brcm_pcie_driver = {
>
> Why do you need __refdata? There's only only other occurrence in
> drivers/pci, and I'm dubious about that one as well.
>
>> + .probe = brcm_pcie_probe,
>> + .remove = brcm_pcie_remove,
>> + .driver = {
>> + .name = "brcm-pcie",
>> + .owner = THIS_MODULE,
>> + .of_match_table = brcm_pcie_match,
>> + .pm = &brcm_pcie_pm_ops,
>> + },
>> +};
>> +
>> +module_platform_driver(brcm_pcie_driver);
>> +
>> +MODULE_LICENSE("GPL");
>
> Copyright notice above says "GPL v2", which is not the same as the
> "GPL" here.
>
>> +MODULE_DESCRIPTION("Broadcom STB PCIE RC driver");
>> +MODULE_AUTHOR("Broadcom");
>> --
>> 1.9.0.138.g2de3478
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] ARM: OMAP2+: Drop unused legacy data for prcm_reg_id and module_bit
From: Tony Lindgren @ 2017-12-14 0:46 UTC (permalink / raw)
To: linux-arm-kernel
We are now using clock drivers in driver/clk/ti for enabling and disabling
modules and these are all unused.
Let's also remove the related unused defines in cm-regbits-24xx.h and
cm-regbits-34xx.h.
Reported-by: H. Nikolaus Schaller <hns@goldelico.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
arch/arm/mach-omap2/cm-regbits-24xx.h | 81 -----------
arch/arm/mach-omap2/cm-regbits-34xx.h | 162 ---------------------
arch/arm/mach-omap2/omap_hwmod.h | 6 -
arch/arm/mach-omap2/omap_hwmod_2420_data.c | 14 --
arch/arm/mach-omap2/omap_hwmod_2430_data.c | 28 ----
arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 64 --------
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 131 -----------------
7 files changed, 486 deletions(-)
diff --git a/arch/arm/mach-omap2/cm-regbits-24xx.h b/arch/arm/mach-omap2/cm-regbits-24xx.h
--- a/arch/arm/mach-omap2/cm-regbits-24xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-24xx.h
@@ -14,38 +14,8 @@
* published by the Free Software Foundation.
*/
-#define OMAP24XX_EN_CAM_SHIFT 31
-#define OMAP24XX_EN_WDT4_SHIFT 29
-#define OMAP2420_EN_WDT3_SHIFT 28
-#define OMAP24XX_EN_MSPRO_SHIFT 27
-#define OMAP24XX_EN_FAC_SHIFT 25
-#define OMAP2420_EN_EAC_SHIFT 24
-#define OMAP24XX_EN_HDQ_SHIFT 23
-#define OMAP2420_EN_I2C2_SHIFT 20
-#define OMAP2420_EN_I2C1_SHIFT 19
-#define OMAP2430_EN_MCBSP5_SHIFT 5
-#define OMAP2430_EN_MCBSP4_SHIFT 4
-#define OMAP2430_EN_MCBSP3_SHIFT 3
-#define OMAP24XX_EN_SSI_SHIFT 1
-#define OMAP24XX_EN_MPU_WDT_SHIFT 3
-#define OMAP24XX_CLKSEL_MPU_SHIFT 0
-#define OMAP24XX_CLKSEL_MPU_WIDTH 5
#define OMAP24XX_AUTOSTATE_MPU_MASK (1 << 0)
-#define OMAP24XX_EN_TV_SHIFT 2
-#define OMAP24XX_EN_DSS2_SHIFT 1
-#define OMAP24XX_EN_DSS1_SHIFT 0
#define OMAP24XX_EN_DSS1_MASK (1 << 0)
-#define OMAP2430_EN_I2CHS2_SHIFT 20
-#define OMAP2430_EN_I2CHS1_SHIFT 19
-#define OMAP2430_EN_MMCHSDB2_SHIFT 17
-#define OMAP2430_EN_MMCHSDB1_SHIFT 16
-#define OMAP24XX_EN_MAILBOXES_SHIFT 30
-#define OMAP2430_EN_SDRC_SHIFT 2
-#define OMAP24XX_EN_PKA_SHIFT 4
-#define OMAP24XX_EN_AES_SHIFT 3
-#define OMAP24XX_EN_RNG_SHIFT 2
-#define OMAP24XX_EN_SHA_SHIFT 1
-#define OMAP24XX_EN_DES_SHIFT 0
#define OMAP24XX_ST_MAILBOXES_SHIFT 30
#define OMAP24XX_ST_HDQ_SHIFT 23
#define OMAP2420_ST_I2C2_SHIFT 20
@@ -54,81 +24,30 @@
#define OMAP2430_ST_I2CHS2_SHIFT 20
#define OMAP24XX_ST_MCBSP2_SHIFT 16
#define OMAP24XX_ST_MCBSP1_SHIFT 15
-#define OMAP24XX_ST_DSS_SHIFT 0
#define OMAP2430_ST_MCBSP5_SHIFT 5
#define OMAP2430_ST_MCBSP4_SHIFT 4
#define OMAP2430_ST_MCBSP3_SHIFT 3
#define OMAP24XX_ST_AES_SHIFT 3
#define OMAP24XX_ST_RNG_SHIFT 2
#define OMAP24XX_ST_SHA_SHIFT 1
-#define OMAP24XX_AUTO_SDRC_SHIFT 2
-#define OMAP24XX_AUTO_GPMC_SHIFT 1
-#define OMAP24XX_AUTO_SDMA_SHIFT 0
-#define OMAP24XX_CLKSEL_USB_MASK (0x7 << 25)
-#define OMAP24XX_CLKSEL_SSI_MASK (0x1f << 20)
-#define OMAP2420_CLKSEL_VLYNQ_MASK (0x1f << 15)
#define OMAP24XX_CLKSEL_DSS2_MASK (0x1 << 13)
-#define OMAP24XX_CLKSEL_DSS1_MASK (0x1f << 8)
-#define OMAP24XX_CLKSEL_L4_SHIFT 5
-#define OMAP24XX_CLKSEL_L4_WIDTH 2
-#define OMAP24XX_CLKSEL_L3_SHIFT 0
-#define OMAP24XX_CLKSEL_L3_WIDTH 5
-#define OMAP24XX_CLKSEL_GPT12_MASK (0x3 << 22)
-#define OMAP24XX_CLKSEL_GPT11_MASK (0x3 << 20)
-#define OMAP24XX_CLKSEL_GPT10_MASK (0x3 << 18)
-#define OMAP24XX_CLKSEL_GPT9_MASK (0x3 << 16)
-#define OMAP24XX_CLKSEL_GPT8_MASK (0x3 << 14)
-#define OMAP24XX_CLKSEL_GPT7_MASK (0x3 << 12)
-#define OMAP24XX_CLKSEL_GPT6_MASK (0x3 << 10)
-#define OMAP24XX_CLKSEL_GPT5_MASK (0x3 << 8)
-#define OMAP24XX_CLKSEL_GPT4_MASK (0x3 << 6)
-#define OMAP24XX_CLKSEL_GPT3_MASK (0x3 << 4)
-#define OMAP24XX_CLKSEL_GPT2_MASK (0x3 << 2)
#define OMAP24XX_AUTOSTATE_DSS_MASK (1 << 2)
#define OMAP24XX_AUTOSTATE_L4_MASK (1 << 1)
#define OMAP24XX_AUTOSTATE_L3_MASK (1 << 0)
-#define OMAP24XX_EN_3D_SHIFT 2
-#define OMAP24XX_EN_2D_SHIFT 1
#define OMAP24XX_AUTOSTATE_GFX_MASK (1 << 0)
-#define OMAP2430_EN_ICR_SHIFT 6
-#define OMAP24XX_EN_OMAPCTRL_SHIFT 5
-#define OMAP24XX_EN_WDT1_SHIFT 4
-#define OMAP24XX_EN_32KSYNC_SHIFT 1
#define OMAP24XX_ST_MPU_WDT_SHIFT 3
#define OMAP24XX_ST_32KSYNC_SHIFT 1
-#define OMAP24XX_CLKSEL_GPT1_MASK (0x3 << 0)
#define OMAP24XX_EN_54M_PLL_SHIFT 6
#define OMAP24XX_EN_96M_PLL_SHIFT 2
-#define OMAP24XX_EN_DPLL_MASK (0x3 << 0)
#define OMAP24XX_ST_54M_APLL_SHIFT 9
#define OMAP24XX_ST_96M_APLL_SHIFT 8
#define OMAP24XX_AUTO_54M_MASK (0x3 << 6)
#define OMAP24XX_AUTO_96M_MASK (0x3 << 2)
#define OMAP24XX_AUTO_DPLL_SHIFT 0
#define OMAP24XX_AUTO_DPLL_MASK (0x3 << 0)
-#define OMAP24XX_APLLS_CLKIN_SHIFT 23
-#define OMAP24XX_APLLS_CLKIN_WIDTH 3
-#define OMAP24XX_APLLS_CLKIN_MASK (0x7 << 23)
-#define OMAP24XX_DPLL_MULT_MASK (0x3ff << 12)
-#define OMAP24XX_DPLL_DIV_MASK (0xf << 8)
-#define OMAP24XX_54M_SOURCE_SHIFT 5
-#define OMAP24XX_54M_SOURCE_WIDTH 1
-#define OMAP2430_96M_SOURCE_SHIFT 4
-#define OMAP2430_96M_SOURCE_WIDTH 1
-#define OMAP24XX_48M_SOURCE_MASK (1 << 3)
#define OMAP24XX_CORE_CLK_SRC_MASK (0x3 << 0)
-#define OMAP2420_EN_IVA_COP_SHIFT 10
-#define OMAP2420_EN_IVA_MPU_SHIFT 8
-#define OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT 0
-#define OMAP2420_EN_DSP_IPI_SHIFT 1
-#define OMAP2420_CLKSEL_IVA_MASK (0x1f << 8)
-#define OMAP24XX_CLKSEL_DSP_IF_MASK (0x3 << 5)
-#define OMAP24XX_CLKSEL_DSP_MASK (0x1f << 0)
#define OMAP2420_AUTOSTATE_IVA_MASK (1 << 8)
#define OMAP24XX_AUTOSTATE_DSP_MASK (1 << 0)
-#define OMAP2430_EN_OSC_SHIFT 1
-#define OMAP2430_CM_ICLKEN_MDM_EN_MDM_SHIFT 0
-#define OMAP2430_CLKSEL_MDM_MASK (0xf << 0)
#define OMAP2430_AUTOSTATE_MDM_MASK (1 << 0)
#define OMAP24XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP24XX_CLKSTCTRL_ENABLE_AUTO 0x1
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -14,68 +14,11 @@
* published by the Free Software Foundation.
*/
-#define OMAP3430ES2_EN_MMC3_SHIFT 30
-#define OMAP3430_EN_MSPRO_SHIFT 23
-#define OMAP3430_EN_HDQ_SHIFT 22
-#define OMAP3430ES1_EN_FSHOSTUSB_SHIFT 5
-#define OMAP3430ES1_EN_D2D_SHIFT 3
-#define OMAP3430_EN_SSI_SHIFT 0
-#define OMAP3430ES2_EN_USBTLL_SHIFT 2
-#define OMAP3430_EN_WDT2_SHIFT 5
-#define OMAP3430_EN_CAM_SHIFT 0
-#define OMAP3430_EN_WDT3_SHIFT 12
#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_MASK (1 << 0)
-#define OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT 0
-#define OMAP3430_IVA2_DPLL_FREQSEL_SHIFT 4
-#define OMAP3430_IVA2_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430_EN_IVA2_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430_EN_IVA2_DPLL_SHIFT 0
-#define OMAP3430_EN_IVA2_DPLL_MASK (0x7 << 0)
#define OMAP3430_ST_IVA2_SHIFT 0
-#define OMAP3430_ST_IVA2_CLK_MASK (1 << 0)
-#define OMAP3430_AUTO_IVA2_DPLL_SHIFT 0
-#define OMAP3430_AUTO_IVA2_DPLL_MASK (0x7 << 0)
-#define OMAP3430_IVA2_CLK_SRC_SHIFT 19
-#define OMAP3430_IVA2_CLK_SRC_WIDTH 3
-#define OMAP3430_IVA2_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3430_IVA2_DPLL_DIV_MASK (0x7f << 0)
-#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_SHIFT 0
-#define OMAP3430_IVA2_DPLL_CLKOUT_DIV_WIDTH 5
#define OMAP3430_CLKTRCTRL_IVA2_MASK (0x3 << 0)
#define OMAP3430_CLKACTIVITY_IVA2_MASK (1 << 0)
-#define OMAP3430_MPU_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430_EN_MPU_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430_EN_MPU_DPLL_MASK (0x7 << 0)
-#define OMAP3430_ST_MPU_CLK_SHIFT 0
-#define OMAP3430_ST_MPU_CLK_MASK (1 << 0)
-#define OMAP3430_ST_MPU_CLK_WIDTH 1
-#define OMAP3430_AUTO_MPU_DPLL_MASK (0x7 << 0)
-#define OMAP3430_MPU_CLK_SRC_SHIFT 19
-#define OMAP3430_MPU_CLK_SRC_WIDTH 3
-#define OMAP3430_MPU_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3430_MPU_DPLL_DIV_MASK (0x7f << 0)
-#define OMAP3430_MPU_DPLL_CLKOUT_DIV_SHIFT 0
-#define OMAP3430_MPU_DPLL_CLKOUT_DIV_WIDTH 5
#define OMAP3430_CLKTRCTRL_MPU_MASK (0x3 << 0)
-#define OMAP3430_EN_MODEM_SHIFT 31
-#define OMAP3430_EN_ICR_SHIFT 29
-#define OMAP3430_EN_AES2_SHIFT 28
-#define OMAP3430_EN_SHA12_SHIFT 27
-#define OMAP3430_EN_DES2_SHIFT 26
-#define OMAP3430ES1_EN_FAC_SHIFT 8
-#define OMAP3430_EN_MAILBOXES_SHIFT 7
-#define OMAP3430_EN_OMAPCTRL_SHIFT 6
-#define OMAP3430_EN_SAD2D_SHIFT 3
-#define OMAP3430_EN_SDRC_SHIFT 1
-#define AM35XX_EN_IPSS_SHIFT 4
-#define OMAP3430_EN_PKA_SHIFT 4
-#define OMAP3430_EN_AES1_SHIFT 3
-#define OMAP3430_EN_RNG_SHIFT 2
-#define OMAP3430_EN_SHA11_SHIFT 1
-#define OMAP3430_EN_DES1_SHIFT 0
-#define OMAP3430_EN_MAD2D_SHIFT 3
-#define OMAP3430ES2_EN_TS_SHIFT 1
-#define OMAP3430ES2_EN_CPEFUSE_SHIFT 0
#define OMAP3430_ST_AES2_SHIFT 28
#define OMAP3430_ST_SHA12_SHIFT 27
#define AM35XX_ST_UART4_SHIFT 23
@@ -84,131 +27,26 @@
#define OMAP3430_ST_MAILBOXES_SHIFT 7
#define OMAP3430_ST_SAD2D_SHIFT 3
#define OMAP3430_ST_SDMA_SHIFT 2
-#define AM35XX_ST_IPSS_SHIFT 5
#define OMAP3430ES2_ST_USBTLL_SHIFT 2
-#define OMAP3430_CLKSEL_SSI_MASK (0xf << 8)
-#define OMAP3430_CLKSEL_GPT11_MASK (1 << 7)
-#define OMAP3430_CLKSEL_GPT10_MASK (1 << 6)
-#define OMAP3430ES1_CLKSEL_FSHOSTUSB_MASK (0x3 << 4)
-#define OMAP3430_CLKSEL_L4_SHIFT 2
-#define OMAP3430_CLKSEL_L4_WIDTH 2
-#define OMAP3430_CLKSEL_L3_SHIFT 0
-#define OMAP3430_CLKSEL_L3_WIDTH 2
-#define OMAP3630_CLKSEL_96M_MASK (0x3 << 12)
#define OMAP3430ES1_CLKTRCTRL_D2D_MASK (0x3 << 4)
#define OMAP3430_CLKTRCTRL_L4_MASK (0x3 << 2)
#define OMAP3430_CLKTRCTRL_L3_MASK (0x3 << 0)
-#define OMAP3430ES1_EN_3D_SHIFT 2
-#define OMAP3430ES1_EN_2D_SHIFT 1
#define OMAP3430ES1_CLKTRCTRL_GFX_MASK (0x3 << 0)
-#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1
-#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0
-#define OMAP3430ES2_CLKSEL_SGX_MASK (0x7 << 0)
#define OMAP3430ES2_CLKTRCTRL_SGX_MASK (0x3 << 0)
-#define OMAP3430ES2_EN_USIMOCP_SHIFT 9
-#define OMAP3430_EN_WDT1_SHIFT 4
-#define OMAP3430_EN_32KSYNC_SHIFT 2
#define OMAP3430_ST_WDT2_SHIFT 5
#define OMAP3430_ST_32KSYNC_SHIFT 2
-#define OMAP3430ES2_CLKSEL_USIMOCP_MASK (0xf << 3)
-#define OMAP3430_CLKSEL_RM_SHIFT 1
-#define OMAP3430_CLKSEL_RM_WIDTH 2
-#define OMAP3430_CLKSEL_GPT1_MASK (1 << 0)
-#define OMAP3430_PWRDN_EMU_PERIPH_SHIFT 31
-#define OMAP3430_PWRDN_CAM_SHIFT 30
-#define OMAP3430_PWRDN_DSS1_SHIFT 29
-#define OMAP3430_PWRDN_TV_SHIFT 28
-#define OMAP3430_PWRDN_96M_SHIFT 27
-#define OMAP3430_PERIPH_DPLL_FREQSEL_MASK (0xf << 20)
-#define OMAP3430_EN_PERIPH_DPLL_DRIFTGUARD_SHIFT 19
-#define OMAP3430_EN_PERIPH_DPLL_MASK (0x7 << 16)
-#define OMAP3430_PWRDN_EMU_CORE_SHIFT 12
-#define OMAP3430_CORE_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430_EN_CORE_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430_EN_CORE_DPLL_MASK (0x7 << 0)
-#define OMAP3430ES2_PERIPH2_DPLL_FREQSEL_MASK (0xf << 4)
-#define OMAP3430ES2_EN_PERIPH2_DPLL_DRIFTGUARD_SHIFT 3
-#define OMAP3430ES2_EN_PERIPH2_DPLL_MASK (0x7 << 0)
-#define OMAP3430_ST_PERIPH_CLK_MASK (1 << 1)
-#define OMAP3430_ST_CORE_CLK_MASK (1 << 0)
-#define OMAP3430ES2_ST_PERIPH2_CLK_MASK (1 << 0)
#define OMAP3430_AUTO_PERIPH_DPLL_MASK (0x7 << 3)
-#define OMAP3430_AUTO_CORE_DPLL_MASK (0x7 << 0)
-#define OMAP3430ES2_AUTO_PERIPH2_DPLL_MASK (0x7 << 0)
-#define OMAP3430_CORE_DPLL_CLKOUT_DIV_SHIFT 27
-#define OMAP3430_CORE_DPLL_CLKOUT_DIV_WIDTH 5
-#define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16)
-#define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8)
-#define OMAP3430_SOURCE_96M_SHIFT 6
-#define OMAP3430_SOURCE_96M_WIDTH 1
-#define OMAP3430_SOURCE_54M_SHIFT 5
-#define OMAP3430_SOURCE_54M_WIDTH 1
-#define OMAP3430_SOURCE_48M_MASK (1 << 3)
-#define OMAP3430_PERIPH_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3630_PERIPH_DPLL_MULT_MASK (0xfff << 8)
-#define OMAP3430_PERIPH_DPLL_DIV_MASK (0x7f << 0)
-#define OMAP3630_PERIPH_DPLL_DCO_SEL_MASK (0x7 << 21)
-#define OMAP3630_PERIPH_DPLL_SD_DIV_MASK (0xff << 24)
-#define OMAP3430_DIV_96M_SHIFT 0
-#define OMAP3630_DIV_96M_WIDTH 6
-#define OMAP3430ES2_PERIPH2_DPLL_MULT_MASK (0x7ff << 8)
-#define OMAP3430ES2_PERIPH2_DPLL_DIV_MASK (0x7f << 0)
-#define OMAP3430ES2_DIV_120M_SHIFT 0
-#define OMAP3430ES2_DIV_120M_WIDTH 5
-#define OMAP3430_CLKOUT2_EN_SHIFT 7
-#define OMAP3430_CLKOUT2_DIV_SHIFT 3
-#define OMAP3430_CLKOUT2_DIV_WIDTH 3
-#define OMAP3430_CLKOUT2SOURCE_MASK (0x3 << 0)
-#define OMAP3430_EN_TV_SHIFT 2
-#define OMAP3430_EN_DSS2_SHIFT 1
-#define OMAP3430_EN_DSS1_SHIFT 0
-#define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0
#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1
-#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0
-#define OMAP3430ES1_ST_DSS_SHIFT 0
-#define OMAP3430_CLKSEL_TV_SHIFT 8
-#define OMAP3630_CLKSEL_TV_WIDTH 6
-#define OMAP3430_CLKSEL_DSS1_SHIFT 0
-#define OMAP3630_CLKSEL_DSS1_WIDTH 6
#define OMAP3430_CLKTRCTRL_DSS_MASK (0x3 << 0)
-#define OMAP3430_EN_CSI2_SHIFT 1
-#define OMAP3430_CLKSEL_CAM_SHIFT 0
-#define OMAP3630_CLKSEL_CAM_WIDTH 6
#define OMAP3430_CLKTRCTRL_CAM_MASK (0x3 << 0)
#define OMAP3430_ST_MCBSP4_SHIFT 2
#define OMAP3430_ST_MCBSP3_SHIFT 1
#define OMAP3430_ST_MCBSP2_SHIFT 0
-#define OMAP3430_CLKSEL_GPT9_MASK (1 << 7)
-#define OMAP3430_CLKSEL_GPT8_MASK (1 << 6)
-#define OMAP3430_CLKSEL_GPT7_MASK (1 << 5)
-#define OMAP3430_CLKSEL_GPT6_MASK (1 << 4)
-#define OMAP3430_CLKSEL_GPT5_MASK (1 << 3)
-#define OMAP3430_CLKSEL_GPT4_MASK (1 << 2)
-#define OMAP3430_CLKSEL_GPT3_MASK (1 << 1)
-#define OMAP3430_CLKSEL_GPT2_MASK (1 << 0)
#define OMAP3430_CLKTRCTRL_PER_MASK (0x3 << 0)
-#define OMAP3430_DIV_DPLL4_SHIFT 24
-#define OMAP3630_DIV_DPLL4_WIDTH 6
-#define OMAP3430_DIV_DPLL3_SHIFT 16
-#define OMAP3430_DIV_DPLL3_WIDTH 5
-#define OMAP3430_CLKSEL_TRACECLK_SHIFT 11
-#define OMAP3430_CLKSEL_TRACECLK_WIDTH 3
-#define OMAP3430_CLKSEL_PCLK_SHIFT 8
-#define OMAP3430_CLKSEL_PCLK_WIDTH 3
-#define OMAP3430_CLKSEL_PCLKX2_SHIFT 6
-#define OMAP3430_CLKSEL_PCLKX2_WIDTH 2
-#define OMAP3430_CLKSEL_ATCLK_SHIFT 4
-#define OMAP3430_CLKSEL_ATCLK_WIDTH 2
-#define OMAP3430_TRACE_MUX_CTRL_SHIFT 2
-#define OMAP3430_TRACE_MUX_CTRL_WIDTH 2
-#define OMAP3430_MUX_CTRL_MASK (0x3 << 0)
#define OMAP3430_CLKTRCTRL_EMU_MASK (0x3 << 0)
#define OMAP3430_CLKTRCTRL_NEON_MASK (0x3 << 0)
#define OMAP3430ES2_EN_USBHOST2_SHIFT 1
-#define OMAP3430ES2_EN_USBHOST1_SHIFT 0
-#define OMAP3430ES2_EN_USBHOST_SHIFT 0
#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1
-#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0
#define OMAP3430ES2_CLKTRCTRL_USBHOST_MASK (3 << 0)
#define OMAP34XX_CLKSTCTRL_DISABLE_AUTO 0x0
#define OMAP34XX_CLKSTCTRL_FORCE_SLEEP 0x1
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -329,11 +329,8 @@ struct omap_hwmod_class_sysconfig {
/**
* struct omap_hwmod_omap2_prcm - OMAP2/3-specific PRCM data
* @module_offs: PRCM submodule offset from the start of the PRM/CM
- * @prcm_reg_id: PRCM register ID (e.g., 3 for CM_AUTOIDLE3)
- * @module_bit: register bit shift for AUTOIDLE, WKST, WKEN, GRPSEL regs
* @idlest_reg_id: IDLEST register ID (e.g., 3 for CM_IDLEST3)
* @idlest_idle_bit: register bit shift for CM_IDLEST slave idle bit
- * @idlest_stdby_bit: register bit shift for CM_IDLEST master standby bit
*
* @prcm_reg_id and @module_bit are specific to the AUTOIDLE, WKST,
* WKEN, GRPSEL registers. In an ideal world, no extra information
@@ -343,11 +340,8 @@ struct omap_hwmod_class_sysconfig {
*/
struct omap_hwmod_omap2_prcm {
s16 module_offs;
- u8 prcm_reg_id;
- u8 module_bit;
u8 idlest_reg_id;
u8 idlest_idle_bit;
- u8 idlest_stdby_bit;
};
/*
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -111,8 +111,6 @@ static struct omap_hwmod omap2420_i2c1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2420_EN_I2C1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT,
},
@@ -134,8 +132,6 @@ static struct omap_hwmod omap2420_i2c2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2420_EN_I2C2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT,
},
@@ -167,8 +163,6 @@ static struct omap_hwmod omap2420_mailbox_hwmod = {
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
@@ -197,8 +191,6 @@ static struct omap_hwmod omap2420_mcbsp1_hwmod = {
.main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
@@ -215,8 +207,6 @@ static struct omap_hwmod omap2420_mcbsp2_hwmod = {
.main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
@@ -247,8 +237,6 @@ static struct omap_hwmod omap2420_msdi1_hwmod = {
.main_clk = "mmc_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2420_EN_MMC_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP2420_ST_MMC_SHIFT,
@@ -264,8 +252,6 @@ static struct omap_hwmod omap2420_hdq1w_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_HDQ_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
},
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -97,8 +97,6 @@ static struct omap_hwmod omap2430_i2c1_hwmod = {
* to hwmod framework.
*/
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_I2CHS1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP2430_ST_I2CHS1_SHIFT,
},
@@ -115,8 +113,6 @@ static struct omap_hwmod omap2430_i2c2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_I2CHS2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP2430_ST_I2CHS2_SHIFT,
},
@@ -132,8 +128,6 @@ static struct omap_hwmod omap2430_gpio5_hwmod = {
.main_clk = "gpio5_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_GPIO5_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_GPIO5_SHIFT,
@@ -165,8 +159,6 @@ static struct omap_hwmod omap2430_mailbox_hwmod = {
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT,
@@ -185,8 +177,6 @@ static struct omap_hwmod omap2430_mcspi3_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_MCSPI3_SHIFT,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_MCSPI3_SHIFT,
},
@@ -219,8 +209,6 @@ static struct omap_hwmod omap2430_usbhsotg_hwmod = {
.main_clk = "usbhs_ick",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_USBHS_MASK,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP2430_ST_USBHS_SHIFT,
@@ -266,8 +254,6 @@ static struct omap_hwmod omap2430_mcbsp1_hwmod = {
.main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT,
@@ -284,8 +270,6 @@ static struct omap_hwmod omap2430_mcbsp2_hwmod = {
.main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCBSP2_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT,
@@ -302,8 +286,6 @@ static struct omap_hwmod omap2430_mcbsp3_hwmod = {
.main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_MCBSP3_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_MCBSP3_SHIFT,
@@ -320,8 +302,6 @@ static struct omap_hwmod omap2430_mcbsp4_hwmod = {
.main_clk = "mcbsp4_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_MCBSP4_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_MCBSP4_SHIFT,
@@ -338,8 +318,6 @@ static struct omap_hwmod omap2430_mcbsp5_hwmod = {
.main_clk = "mcbsp5_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP2430_EN_MCBSP5_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_MCBSP5_SHIFT,
@@ -384,8 +362,6 @@ static struct omap_hwmod omap2430_mmc1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_MMCHS1_SHIFT,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_MMCHS1_SHIFT,
},
@@ -408,8 +384,6 @@ static struct omap_hwmod omap2430_mmc2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP2430_EN_MMCHS2_SHIFT,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP2430_ST_MMCHS2_SHIFT,
},
@@ -424,8 +398,6 @@ static struct omap_hwmod omap2430_hdq1w_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_HDQ_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_HDQ_SHIFT,
},
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -242,8 +242,6 @@ struct omap_hwmod omap2xxx_timer1_hwmod = {
.main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT1_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT1_SHIFT,
@@ -261,8 +259,6 @@ struct omap_hwmod omap2xxx_timer2_hwmod = {
.main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT2_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT2_SHIFT,
@@ -279,8 +275,6 @@ struct omap_hwmod omap2xxx_timer3_hwmod = {
.main_clk = "gpt3_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT3_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT3_SHIFT,
@@ -297,8 +291,6 @@ struct omap_hwmod omap2xxx_timer4_hwmod = {
.main_clk = "gpt4_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT4_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT4_SHIFT,
@@ -315,8 +307,6 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
.main_clk = "gpt5_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT5_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
@@ -334,8 +324,6 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
.main_clk = "gpt6_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT6_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
@@ -353,8 +341,6 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
.main_clk = "gpt7_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT7_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
@@ -372,8 +358,6 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
.main_clk = "gpt8_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT8_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
@@ -391,8 +375,6 @@ struct omap_hwmod omap2xxx_timer9_hwmod = {
.main_clk = "gpt9_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT9_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT9_SHIFT,
@@ -410,8 +392,6 @@ struct omap_hwmod omap2xxx_timer10_hwmod = {
.main_clk = "gpt10_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT10_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT10_SHIFT,
@@ -429,8 +409,6 @@ struct omap_hwmod omap2xxx_timer11_hwmod = {
.main_clk = "gpt11_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT11_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT11_SHIFT,
@@ -448,8 +426,6 @@ struct omap_hwmod omap2xxx_timer12_hwmod = {
.main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPT12_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPT12_SHIFT,
@@ -467,8 +443,6 @@ struct omap_hwmod omap2xxx_wd_timer2_hwmod = {
.main_clk = "mpu_wdt_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MPU_WDT_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MPU_WDT_SHIFT,
@@ -485,8 +459,6 @@ struct omap_hwmod omap2xxx_uart1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_UART1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_EN_UART1_SHIFT,
},
@@ -503,8 +475,6 @@ struct omap_hwmod omap2xxx_uart2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_UART2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_EN_UART2_SHIFT,
},
@@ -521,8 +491,6 @@ struct omap_hwmod omap2xxx_uart3_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 2,
- .module_bit = OMAP24XX_EN_UART3_SHIFT,
.idlest_reg_id = 2,
.idlest_idle_bit = OMAP24XX_EN_UART3_SHIFT,
},
@@ -547,11 +515,8 @@ struct omap_hwmod omap2xxx_dss_core_hwmod = {
.main_clk = "dss1_fck", /* instead of dss_fck */
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
},
},
.opt_clks = dss_opt_clks,
@@ -565,11 +530,8 @@ struct omap_hwmod omap2xxx_dss_dispc_hwmod = {
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP24XX_ST_DSS_SHIFT,
},
},
.flags = HWMOD_NO_IDLEST,
@@ -586,8 +548,6 @@ struct omap_hwmod omap2xxx_dss_rfbi_hwmod = {
.main_clk = "dss1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
},
},
@@ -602,8 +562,6 @@ struct omap_hwmod omap2xxx_dss_venc_hwmod = {
.main_clk = "dss_54m_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_DSS1_SHIFT,
.module_offs = CORE_MOD,
},
},
@@ -623,8 +581,6 @@ struct omap_hwmod omap2xxx_gpio1_hwmod = {
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
@@ -641,8 +597,6 @@ struct omap_hwmod omap2xxx_gpio2_hwmod = {
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
@@ -659,8 +613,6 @@ struct omap_hwmod omap2xxx_gpio3_hwmod = {
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
@@ -677,8 +629,6 @@ struct omap_hwmod omap2xxx_gpio4_hwmod = {
.main_clk = "gpios_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_GPIOS_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_GPIOS_SHIFT,
@@ -699,8 +649,6 @@ struct omap_hwmod omap2xxx_mcspi1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCSPI1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCSPI1_SHIFT,
},
@@ -720,8 +668,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_EN_MCSPI2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_MCSPI2_SHIFT,
},
@@ -740,8 +686,6 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP24XX_ST_32KSYNC_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP24XX_ST_32KSYNC_SHIFT,
},
@@ -758,8 +702,6 @@ struct omap_hwmod omap2xxx_gpmc_hwmod = {
.flags = HWMOD_NO_IDLEST | DEBUG_OMAP_GPMC_HWMOD_FLAGS,
.prcm = {
.omap2 = {
- .prcm_reg_id = 3,
- .module_bit = OMAP24XX_EN_GPMC_MASK,
.module_offs = CORE_MOD,
},
},
@@ -787,8 +729,6 @@ struct omap_hwmod omap2xxx_rng_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 4,
- .module_bit = OMAP24XX_EN_RNG_SHIFT,
.idlest_reg_id = 4,
.idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
},
@@ -825,8 +765,6 @@ struct omap_hwmod omap2xxx_sham_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 4,
- .module_bit = OMAP24XX_EN_SHA_SHIFT,
.idlest_reg_id = 4,
.idlest_idle_bit = OMAP24XX_ST_SHA_SHIFT,
},
@@ -856,8 +794,6 @@ struct omap_hwmod omap2xxx_aes_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 4,
- .module_bit = OMAP24XX_EN_AES_SHIFT,
.idlest_reg_id = 4,
.idlest_idle_bit = OMAP24XX_ST_AES_SHIFT,
},
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -113,8 +113,6 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
.prcm = {
.omap2 = {
.module_offs = OMAP3430_IVA2_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
},
@@ -188,8 +186,6 @@ static struct omap_hwmod omap3xxx_timer1_hwmod = {
.main_clk = "gpt1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT1_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT1_SHIFT,
@@ -206,8 +202,6 @@ static struct omap_hwmod omap3xxx_timer2_hwmod = {
.main_clk = "gpt2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT2_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT2_SHIFT,
@@ -223,8 +217,6 @@ static struct omap_hwmod omap3xxx_timer3_hwmod = {
.main_clk = "gpt3_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT3_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT3_SHIFT,
@@ -240,8 +232,6 @@ static struct omap_hwmod omap3xxx_timer4_hwmod = {
.main_clk = "gpt4_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT4_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT4_SHIFT,
@@ -257,8 +247,6 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
.main_clk = "gpt5_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT5_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
@@ -275,8 +263,6 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
.main_clk = "gpt6_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT6_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
@@ -293,8 +279,6 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
.main_clk = "gpt7_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT7_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
@@ -311,8 +295,6 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
.main_clk = "gpt8_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT8_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
@@ -329,8 +311,6 @@ static struct omap_hwmod omap3xxx_timer9_hwmod = {
.main_clk = "gpt9_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT9_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT9_SHIFT,
@@ -347,8 +327,6 @@ static struct omap_hwmod omap3xxx_timer10_hwmod = {
.main_clk = "gpt10_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT10_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT10_SHIFT,
@@ -365,8 +343,6 @@ static struct omap_hwmod omap3xxx_timer11_hwmod = {
.main_clk = "gpt11_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT11_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT11_SHIFT,
@@ -384,8 +360,6 @@ static struct omap_hwmod omap3xxx_timer12_hwmod = {
.main_clk = "gpt12_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPT12_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPT12_SHIFT,
@@ -439,8 +413,6 @@ static struct omap_hwmod omap3xxx_wd_timer2_hwmod = {
.main_clk = "wdt2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_WDT2_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_WDT2_SHIFT,
@@ -461,8 +433,6 @@ static struct omap_hwmod omap3xxx_uart1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_UART1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_EN_UART1_SHIFT,
},
@@ -478,8 +448,6 @@ static struct omap_hwmod omap3xxx_uart2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_UART2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_EN_UART2_SHIFT,
},
@@ -496,8 +464,6 @@ static struct omap_hwmod omap3xxx_uart3_hwmod = {
.prcm = {
.omap2 = {
.module_offs = OMAP3430_PER_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_UART3_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_EN_UART3_SHIFT,
},
@@ -515,8 +481,6 @@ static struct omap_hwmod omap36xx_uart4_hwmod = {
.prcm = {
.omap2 = {
.module_offs = OMAP3430_PER_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3630_EN_UART4_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3630_EN_UART4_SHIFT,
},
@@ -546,8 +510,6 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = AM35XX_EN_UART4_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
},
@@ -583,11 +545,8 @@ static struct omap_hwmod omap3430es1_dss_core_hwmod = {
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
.idlest_reg_id = 1,
- .idlest_stdby_bit = OMAP3430ES1_ST_DSS_SHIFT,
},
},
.opt_clks = dss_opt_clks,
@@ -602,12 +561,9 @@ static struct omap_hwmod omap3xxx_dss_core_hwmod = {
.main_clk = "dss1_alwon_fck", /* instead of dss_fck */
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430ES2_ST_DSS_IDLE_SHIFT,
- .idlest_stdby_bit = OMAP3430ES2_ST_DSS_STDBY_SHIFT,
},
},
.opt_clks = dss_opt_clks,
@@ -642,8 +598,6 @@ static struct omap_hwmod omap3xxx_dss_dispc_hwmod = {
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
@@ -683,8 +637,6 @@ static struct omap_hwmod omap3xxx_dss_dsi1_hwmod = {
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
@@ -703,8 +655,6 @@ static struct omap_hwmod omap3xxx_dss_rfbi_hwmod = {
.main_clk = "dss1_alwon_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
@@ -724,8 +674,6 @@ static struct omap_hwmod omap3xxx_dss_venc_hwmod = {
.main_clk = "dss_tv_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_DSS1_SHIFT,
.module_offs = OMAP3430_DSS_MOD,
},
},
@@ -747,8 +695,6 @@ static struct omap_hwmod omap3xxx_i2c1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_I2C1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_I2C1_SHIFT,
},
@@ -770,8 +716,6 @@ static struct omap_hwmod omap3xxx_i2c2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_I2C2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_I2C2_SHIFT,
},
@@ -795,8 +739,6 @@ static struct omap_hwmod omap3xxx_i2c3_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_I2C3_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_I2C3_SHIFT,
},
@@ -846,8 +788,6 @@ static struct omap_hwmod omap3xxx_gpio1_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks),
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO1_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPIO1_SHIFT,
@@ -870,8 +810,6 @@ static struct omap_hwmod omap3xxx_gpio2_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks),
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO2_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPIO2_SHIFT,
@@ -894,8 +832,6 @@ static struct omap_hwmod omap3xxx_gpio3_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks),
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO3_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPIO3_SHIFT,
@@ -918,8 +854,6 @@ static struct omap_hwmod omap3xxx_gpio4_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks),
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO4_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPIO4_SHIFT,
@@ -943,8 +877,6 @@ static struct omap_hwmod omap3xxx_gpio5_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks),
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO5_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPIO5_SHIFT,
@@ -968,8 +900,6 @@ static struct omap_hwmod omap3xxx_gpio6_hwmod = {
.opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks),
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_GPIO6_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_GPIO6_SHIFT,
@@ -1012,8 +942,6 @@ static struct omap_hwmod omap3xxx_dma_system_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_ST_SDMA_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_SDMA_SHIFT,
},
@@ -1060,8 +988,6 @@ static struct omap_hwmod omap3xxx_mcbsp1_hwmod = {
.main_clk = "mcbsp1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP1_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCBSP1_SHIFT,
@@ -1083,8 +1009,6 @@ static struct omap_hwmod omap3xxx_mcbsp2_hwmod = {
.main_clk = "mcbsp2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP2_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCBSP2_SHIFT,
@@ -1107,8 +1031,6 @@ static struct omap_hwmod omap3xxx_mcbsp3_hwmod = {
.main_clk = "mcbsp3_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP3_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCBSP3_SHIFT,
@@ -1128,8 +1050,6 @@ static struct omap_hwmod omap3xxx_mcbsp4_hwmod = {
.main_clk = "mcbsp4_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP4_SHIFT,
.module_offs = OMAP3430_PER_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCBSP4_SHIFT,
@@ -1148,8 +1068,6 @@ static struct omap_hwmod omap3xxx_mcbsp5_hwmod = {
.main_clk = "mcbsp5_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCBSP5_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCBSP5_SHIFT,
@@ -1228,8 +1146,6 @@ static struct omap_hwmod omap34xx_sr1_hwmod = {
.main_clk = "sr1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR1_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
@@ -1245,8 +1161,6 @@ static struct omap_hwmod omap36xx_sr1_hwmod = {
.main_clk = "sr1_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR1_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_EN_SR1_SHIFT,
@@ -1267,8 +1181,6 @@ static struct omap_hwmod omap34xx_sr2_hwmod = {
.main_clk = "sr2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR2_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
@@ -1284,8 +1196,6 @@ static struct omap_hwmod omap36xx_sr2_hwmod = {
.main_clk = "sr2_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SR2_SHIFT,
.module_offs = WKUP_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_EN_SR2_SHIFT,
@@ -1321,8 +1231,6 @@ static struct omap_hwmod omap3xxx_mailbox_hwmod = {
.main_clk = "mailboxes_ick",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MAILBOXES_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MAILBOXES_SHIFT,
@@ -1364,8 +1272,6 @@ static struct omap_hwmod omap34xx_mcspi1 = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI1_SHIFT,
},
@@ -1385,8 +1291,6 @@ static struct omap_hwmod omap34xx_mcspi2 = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI2_SHIFT,
},
@@ -1408,8 +1312,6 @@ static struct omap_hwmod omap34xx_mcspi3 = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI3_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI3_SHIFT,
},
@@ -1431,8 +1333,6 @@ static struct omap_hwmod omap34xx_mcspi4 = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MCSPI4_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MCSPI4_SHIFT,
},
@@ -1466,12 +1366,9 @@ static struct omap_hwmod omap3xxx_usbhsotg_hwmod = {
.main_clk = "hsotgusb_ick",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_HSOTGUSB_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430ES2_ST_HSOTGUSB_IDLE_SHIFT,
- .idlest_stdby_bit = OMAP3430ES2_ST_HSOTGUSB_STDBY_SHIFT,
},
},
.class = &usbotg_class,
@@ -1546,8 +1443,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
},
@@ -1564,8 +1459,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc1_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MMC1_SHIFT,
},
@@ -1595,8 +1488,6 @@ static struct omap_hwmod omap3xxx_pre_es3_mmc2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
},
@@ -1613,8 +1504,6 @@ static struct omap_hwmod omap3xxx_es3plus_mmc2_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MMC2_SHIFT,
},
@@ -1638,8 +1527,6 @@ static struct omap_hwmod omap3xxx_mmc3_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_MMC3_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_MMC3_SHIFT,
},
@@ -1679,11 +1566,8 @@ static struct omap_hwmod omap3xxx_usb_host_hs_hwmod = {
.prcm = {
.omap2 = {
.module_offs = OMAP3430ES2_USBHOST_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430ES2_EN_USBHOST1_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430ES2_ST_USBHOST_IDLE_SHIFT,
- .idlest_stdby_bit = OMAP3430ES2_ST_USBHOST_STDBY_SHIFT,
},
},
@@ -1757,8 +1641,6 @@ static struct omap_hwmod omap3xxx_usb_tll_hs_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 3,
- .module_bit = OMAP3430ES2_EN_USBTLL_SHIFT,
.idlest_reg_id = 3,
.idlest_idle_bit = OMAP3430ES2_ST_USBTLL_SHIFT,
},
@@ -1771,8 +1653,6 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_HDQ_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_HDQ_SHIFT,
},
@@ -1798,8 +1678,6 @@ static struct omap_hwmod omap3xxx_sad2d_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SAD2D_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
},
@@ -1833,8 +1711,6 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
.prcm = {
.omap2 = {
.module_offs = WKUP_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_ST_32KSYNC_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_32KSYNC_SHIFT,
},
@@ -2445,7 +2321,6 @@ static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
.prcm = {
.omap2 = {
.module_offs = OMAP3430_IVA2_MOD,
- .module_bit = OMAP3430_CM_FCLKEN_IVA2_EN_IVA2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_IVA2_SHIFT,
},
@@ -2745,8 +2620,6 @@ static struct omap_hwmod omap3xxx_sham_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SHA12_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_SHA12_SHIFT,
},
@@ -2785,8 +2658,6 @@ static struct omap_hwmod omap3xxx_aes_hwmod = {
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_AES2_SHIFT,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
},
@@ -2829,8 +2700,6 @@ static struct omap_hwmod omap3xxx_ssi_hwmod = {
.main_clk = "ssi_ssr_fck",
.prcm = {
.omap2 = {
- .prcm_reg_id = 1,
- .module_bit = OMAP3430_EN_SSI_SHIFT,
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430ES2_ST_SSI_IDLE_SHIFT,
--
2.15.0
^ permalink raw reply
* [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information
From: Leo Yan @ 2017-12-14 1:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cddaf386-5688-a064-7cb0-1e75485330c4@arm.com>
On Wed, Dec 13, 2017 at 03:16:13PM +0000, Valentin Schneider wrote:
> Hi Leo,
>
>
> On 12/13/2017 02:53 PM, Leo Yan wrote:
> >Hi Valentin,
> >
> >On Wed, Dec 13, 2017 at 02:21:06PM +0000, Valentin Schneider wrote:
> >>The following dt entries are added:
> >> cpus [0-3] (Cortex A53):
> >> - capacity-dmips-mhz = <592>;
> >>
> >> cpus [4-7] (Cortex A73):
> >> - capacity-dmips-mhz = <1024>;
> >>
> >>Those values were obtained by running dhrystone 2.1 on a
> >>HiKey960 with the following procedure:
> >>- Offline all CPUs but CPU0 (A53)
> >>- Set CPU0 frequency to maximum
> >>- Run Dhrystone 2.1 for 20 seconds
> >>
> >>- Offline all CPUs but CPU4 (A73)
> >>- set CPU4 frequency to maximum
> >>- Run Dhrystone 2.1 for 20 seconds
> >>
> >>The results are as follows:
> >>A53: 129633887 loops
> >>A73: 287034147 loops
> >Seems to me the capacity-dmips-mhz should be:
> >
> >CA53: 129633887 / 20 / 1844 = 3515
> >CA73: 287034147 / 20 / 2362 = 6076
> >
> >After normalized to range [0..1024], we could get:
> >
> >CA53: 592
> >CA73: 1024
>
> Yes, that's the "direct approach". I wanted to underline the fact that there
> are two different max frequencies so what I followed would be:
>
> 1) Computing the performance ratio:
> (129633887 / 287034147) * 1024 = 462.47
>
> 2) Scaling that to the same frequency scale:
> 462.47 * (2362/1844) = 592.38
>
> Which gives the same end result (it's the same equation but split in two
> steps). Also it makes it easy to check that the cpu_capacity sysfs entry for
> the A53s gets correctly set (to 462).
Yeah, thanks for clear explanation.
[...]
Thanks,
Leo Yan
^ permalink raw reply
* [PATCH 1/2] cpufreq: mvebu: Free the clock reference in the normal path
From: Viresh Kumar @ 2017-12-14 2:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171213172914.6148-2-gregory.clement@free-electrons.com>
On 13-12-17, 18:29, Gregory CLEMENT wrote:
> In case of error the clock reference was freed but not in normal path
> once it was nor more used. This patch fixes it.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> drivers/cpufreq/mvebu-cpufreq.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/cpufreq/mvebu-cpufreq.c b/drivers/cpufreq/mvebu-cpufreq.c
> index ed915ee85dd9..c043aad8e3a0 100644
> --- a/drivers/cpufreq/mvebu-cpufreq.c
> +++ b/drivers/cpufreq/mvebu-cpufreq.c
> @@ -99,6 +99,7 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
> if (ret)
> dev_err(cpu_dev, "%s: failed to mark OPPs as shared: %d\n",
> __func__, ret);
> + clk_put(clk);
> }
>
> platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* [PATCH 2/2] cpufreq: mvebu: Free opp if registering failed
From: Viresh Kumar @ 2017-12-14 2:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171213172914.6148-3-gregory.clement@free-electrons.com>
On 13-12-17, 18:29, Gregory CLEMENT wrote:
> Since the introduction of this driver, the functions to remove the opp
> were added. So stop claiming we can't remove opp and use one of them in
> case of failure.
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> drivers/cpufreq/mvebu-cpufreq.c | 15 ++++++++-------
> 1 file changed, 8 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/cpufreq/mvebu-cpufreq.c b/drivers/cpufreq/mvebu-cpufreq.c
> index c043aad8e3a0..31513bd42705 100644
> --- a/drivers/cpufreq/mvebu-cpufreq.c
> +++ b/drivers/cpufreq/mvebu-cpufreq.c
> @@ -76,12 +76,6 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
> return PTR_ERR(clk);
> }
>
> - /*
> - * In case of a failure of dev_pm_opp_add(), we don't
> - * bother with cleaning up the registered OPP (there's
> - * no function to do so), and simply cancel the
> - * registration of the cpufreq device.
> - */
> ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk), 0);
> if (ret) {
> clk_put(clk);
> @@ -91,7 +85,8 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
> ret = dev_pm_opp_add(cpu_dev, clk_get_rate(clk) / 2, 0);
> if (ret) {
> clk_put(clk);
> - return ret;
> + dev_err(cpu_dev, "Failed to register OPPs\n");
> + goto opp_register_failed;
> }
>
> ret = dev_pm_opp_set_sharing_cpus(cpu_dev,
> @@ -104,5 +99,11 @@ static int __init armada_xp_pmsu_cpufreq_init(void)
>
> platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
> return 0;
> +
> +opp_register_failed:
> + /* As registering has failed remove all the opp for all cpus */
> + dev_pm_opp_cpumask_remove_table(cpu_possible_mask);
> +
> + return ret;
> }
> device_initcall(armada_xp_pmsu_cpufreq_init);
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply
* [PATCH v2] ARM64: dts: meson-axg: add ethernet mac controller
From: Yixun Lan @ 2017-12-14 3:02 UTC (permalink / raw)
To: linux-arm-kernel
Add DT info for the stmmac ethernet MAC which found in
the Amlogic's Meson-AXG SoC, also describe the ethernet
pinctrl & clock information here.
This is tested in the S400 dev board which use a RTL8211F PHY,
and the pins connect to the 'eth_rgmii_y_pins' group.
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
Changes in v2 since [1]:
- rebase to kevin's v4.16/dt64 branch
- add Neil's Reviewed-by
- move clock info to board.dts instead of in soc.dtsi
- drop "meson-axg-dwmac" compatible string, since we didn't use this
we could re-add it later when we really need.
- note: to make ethernet work properly,it depend on clock & pinctrl[2],
to compile the DTS, the patch [3] is required.
the code part will be taken via clock & pinctrl subsystem tree.
[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005301.html
[2]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005735.html
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005694.html
[3]
http://lists.infradead.org/pipermail/linux-amlogic/2017-December/005738.html
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 11 ++++++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 50 ++++++++++++++++++++++++++
2 files changed, 61 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 70eca1f8736a..138de3bc7cc8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -20,3 +20,14 @@
&uart_AO {
status = "okay";
};
+
+ðmac {
+ status = "okay";
+ clocks = <&clkc CLKID_ETH>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_MPLL2>;
+ clock-names = "stmmaceth", "clkin0", "clkin1";
+ phy-mode = "rgmii";
+ pinctrl-0 = <ð_rgmii_y_pins>;
+ pinctrl-names = "default";
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index d356ce74ad89..106234fda765 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/axg-clkc.h>
/ {
compatible = "amlogic,meson-axg";
@@ -148,6 +149,15 @@
#address-cells = <0>;
};
+ ethmac: ethernet at ff3f0000 {
+ compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
+ reg = <0x0 0xff3f0000 0x0 0x10000
+ 0x0 0xff634540 0x0 0x8>;
+ interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "macirq";
+ status = "disabled";
+ };
+
hiubus: bus at ff63c000 {
compatible = "simple-bus";
reg = <0x0 0xff63c000 0x0 0x1c00>;
@@ -194,6 +204,46 @@
#gpio-cells = <2>;
gpio-ranges = <&pinctrl_periphs 0 0 86>;
};
+
+ eth_rgmii_x_pins: eth-x-rgmii {
+ mux {
+ groups = "eth_mdio_x",
+ "eth_mdc_x",
+ "eth_rgmii_rx_clk_x",
+ "eth_rx_dv_x",
+ "eth_rxd0_x",
+ "eth_rxd1_x",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen_x",
+ "eth_txd0_x",
+ "eth_txd1_x",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ };
+ };
+
+ eth_rgmii_y_pins: eth-y-rgmii {
+ mux {
+ groups = "eth_mdio_y",
+ "eth_mdc_y",
+ "eth_rgmii_rx_clk_y",
+ "eth_rx_dv_y",
+ "eth_rxd0_y",
+ "eth_rxd1_y",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen_y",
+ "eth_txd0_y",
+ "eth_txd1_y",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ };
+ };
};
};
--
2.15.1
^ permalink raw reply related
* [PATCH v3 3/4] cpufreq: Add DVFS support for Armada 37xx
From: Viresh Kumar @ 2017-12-14 3:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171213175119.9441-4-gregory.clement@free-electrons.com>
I just searched for tabs and spaces in this patch and here are the observations.
On 13-12-17, 18:51, Gregory CLEMENT wrote:
> +/* Power management in North Bridge register set */
> +#define ARMADA_37XX_NB_L0L1 0x18
There is a single space after #define here, which is good.
> +#define ARMADA_37XX_NB_L2L3 0x1C
> +#define ARMADA_37XX_NB_TBG_DIV_OFF 13
But here and at many places below you have two spaces after #define, which isn't
bad but isn't consistent as well.
> +#define ARMADA_37XX_NB_TBG_DIV_MASK 0x7
> +#define ARMADA_37XX_NB_CLK_SEL_OFF 11
> +#define ARMADA_37XX_NB_CLK_SEL_MASK 0x1
> +#define ARMADA_37XX_NB_CLK_SEL_TBG 0x1
You have used space instead of TAB after ARMADA_37XX_NB_CLK_SEL_TBG here, while
everywhere else we have tabs. Maybe its better to be consistent ?
> +#define ARMADA_37XX_NB_TBG_SEL_OFF 9
> +#define ARMADA_37XX_NB_TBG_SEL_MASK 0x3
> +#define ARMADA_37XX_NB_VDD_SEL_OFF 6
> +#define ARMADA_37XX_NB_VDD_SEL_MASK 0x3
> +#define ARMADA_37XX_NB_CONFIG_SHIFT 16
> +#define ARMADA_37XX_NB_DYN_MOD 0x24
> +#define ARMADA_37XX_NB_CLK_SEL_EN BIT(26)
> +#define ARMADA_37XX_NB_TBG_EN BIT(28)
> +#define ARMADA_37XX_NB_DIV_EN BIT(29)
> +#define ARMADA_37XX_NB_VDD_EN BIT(30)
> +#define ARMADA_37XX_NB_DFS_EN BIT(31)
> +#define ARMADA_37XX_NB_CPU_LOAD 0x30
> +#define ARMADA_37XX_NB_CPU_LOAD_MASK 0x3
> +#define ARMADA_37XX_DVFS_LOAD_0 0
> +#define ARMADA_37XX_DVFS_LOAD_1 1
> +#define ARMADA_37XX_DVFS_LOAD_2 2
> +#define ARMADA_37XX_DVFS_LOAD_3 3
> +
> +/*
> + * On Armada 37xx the Power management manages 4 level of CPU load,
> + * each level can be associated with a CPU clock source, a CPU
> + * divider, a VDD level, etc...
> + */
> +#define LOAD_LEVEL_NR 4
> +
> +struct armada_37xx_dvfs {
> + u32 cpu_freq_max;
> + u8 divider[LOAD_LEVEL_NR];
> +};
> +
> +static struct armada_37xx_dvfs armada_37xx_dvfs[] = {
> + {.cpu_freq_max = 1200*1000*1000, .divider = {1, 2, 4, 6} },
> + {.cpu_freq_max = 1000*1000*1000, .divider = {1, 2, 4, 5} },
> + {.cpu_freq_max = 800*1000*1000, .divider = {1, 2, 3, 4} },
> + {.cpu_freq_max = 600*1000*1000, .divider = {2, 4, 5, 6} },
> +};
> +
> +static struct armada_37xx_dvfs *armada_37xx_cpu_freq_info_get(u32 freq)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(armada_37xx_dvfs); i++) {
> + if (freq == armada_37xx_dvfs[i].cpu_freq_max)
> + return &armada_37xx_dvfs[i];
> + }
> +
> + pr_err("Unsupported CPU frequency %d MHz\n", freq/1000000);
> + return NULL;
> +}
> +
> +/*
> + * Setup the four level managed by the hardware. Once the four level
> + * will be configured then the DVFS will be enabled.
> + */
> +static void __init armada37xx_cpufreq_dvfs_setup(struct regmap *base,
> + struct clk *clk, u8 *divider)
> +{
> + int load_lvl;
> + struct clk *parent;
> +
> + for (load_lvl = 0; load_lvl < LOAD_LEVEL_NR; load_lvl++) {
> + unsigned int reg, mask, val, offset = 0;
double space before "val".
> +
> + if (load_lvl <= ARMADA_37XX_DVFS_LOAD_1)
> + reg = ARMADA_37XX_NB_L0L1;
> + else
> + reg = ARMADA_37XX_NB_L2L3;
> +
> + if (load_lvl == ARMADA_37XX_DVFS_LOAD_0 ||
> + load_lvl == ARMADA_37XX_DVFS_LOAD_2)
double spaces after ==
> + offset += ARMADA_37XX_NB_CONFIG_SHIFT;
> +
> + /* Set cpu clock source, for all the level we use TBG */
> + val = ARMADA_37XX_NB_CLK_SEL_TBG << ARMADA_37XX_NB_CLK_SEL_OFF;
> + mask = (ARMADA_37XX_NB_CLK_SEL_MASK
> + << ARMADA_37XX_NB_CLK_SEL_OFF);
> +
> + /*
> + * Set cpu divider based on the pre-computed array in
> + * order to have balanced step.
> + */
> + val |= divider[load_lvl] << ARMADA_37XX_NB_TBG_DIV_OFF;
> + mask |= (ARMADA_37XX_NB_TBG_DIV_MASK
> + << ARMADA_37XX_NB_TBG_DIV_OFF);
> +
> + /* Set VDD divider which is actually the load level. */
> + val |= load_lvl << ARMADA_37XX_NB_VDD_SEL_OFF;
> + mask |= (ARMADA_37XX_NB_VDD_SEL_MASK
> + << ARMADA_37XX_NB_VDD_SEL_OFF);
> +
> + val <<= offset;
> + mask <<= offset;
> +
> + regmap_update_bits(base, reg, mask, val);
> + }
> +
> + /*
> + * Set cpu clock source, for all the level we keep the same
> + * clock source that the one already configured. For this one
> + * we need to use the clock framework
> + */
> + parent = clk_get_parent(clk);
> + clk_set_parent(clk, parent);
> +}
> +
> +static void __init armada37xx_cpufreq_disable_dvfs(struct regmap *base)
> +{
> + unsigned int reg = ARMADA_37XX_NB_DYN_MOD,
> + mask = ARMADA_37XX_NB_DFS_EN;
> +
> + regmap_update_bits(base, reg, mask, 0);
> +}
> +
> +static void __init armada37xx_cpufreq_enable_dvfs(struct regmap *base)
> +{
> + unsigned int val, reg = ARMADA_37XX_NB_CPU_LOAD,
> + mask = ARMADA_37XX_NB_CPU_LOAD_MASK;
> +
> + /* Start with the highest load (0) */
> + val = ARMADA_37XX_DVFS_LOAD_0;
> + regmap_update_bits(base, reg, mask, val);
> +
> + /* Now enable DVFS for the CPUs */
> + reg = ARMADA_37XX_NB_DYN_MOD;
> + mask = ARMADA_37XX_NB_CLK_SEL_EN | ARMADA_37XX_NB_TBG_EN |
> + ARMADA_37XX_NB_DIV_EN | ARMADA_37XX_NB_VDD_EN |
> + ARMADA_37XX_NB_DFS_EN;
> +
> + regmap_update_bits(base, reg, mask, mask);
> +}
> +
> +static int __init armada37xx_cpufreq_driver_init(void)
> +{
> + struct armada_37xx_dvfs *dvfs;
> + struct platform_device *pdev;
> + unsigned int cur_frequency;
> + struct regmap *nb_pm_base;
> + struct device *cpu_dev;
> + int load_lvl, ret;
> + struct clk *clk;
> +
> + nb_pm_base =
> + syscon_regmap_lookup_by_compatible("marvell,armada-3700-nb-pm");
> +
> + if (IS_ERR(nb_pm_base))
> + return -ENODEV;
> +
> + /* Before doing any configuration on the DVFS first, disable it */
> + armada37xx_cpufreq_disable_dvfs(nb_pm_base);
> +
> + /*
> + * On CPU 0 register the operating points supported (which are
> + * the nominal CPU frequency and full integer divisions of
> + * it).
> + */
> + cpu_dev = get_cpu_device(0);
> + if (!cpu_dev) {
> + dev_err(cpu_dev, "Cannot get CPU\n");
> + return -ENODEV;
> + }
> +
> + clk = clk_get(cpu_dev, 0);
> + if (IS_ERR(clk)) {
> + dev_err(cpu_dev, "Cannot get clock for CPU0\n");
> + return PTR_ERR(clk);
> + }
> +
> + /* Get nominal (current) CPU frequency */
> + cur_frequency = clk_get_rate(clk);
> + if (!cur_frequency) {
> + dev_err(cpu_dev, "Failed to get clock rate for CPU\n");
> + return -EINVAL;
> + }
> +
> + dvfs = armada_37xx_cpu_freq_info_get(cur_frequency);
> + if (!dvfs)
> + return -EINVAL;
> +
> + armada37xx_cpufreq_dvfs_setup(nb_pm_base, clk, dvfs->divider);
> +
> + for (load_lvl = ARMADA_37XX_DVFS_LOAD_0; load_lvl < LOAD_LEVEL_NR;
> + load_lvl++) {
> + unsigned long freq = cur_frequency / dvfs->divider[load_lvl];
> +
> + ret = dev_pm_opp_add(cpu_dev, freq, 0);
> + if (ret) {
> + /* clean-up the already added opp before leaving */
Double space after /*
> + while (load_lvl-- > ARMADA_37XX_DVFS_LOAD_0) {
> + freq = cur_frequency / dvfs->divider[load_lvl];
> + dev_pm_opp_remove(cpu_dev, freq);
> + }
> + return ret;
> + }
> + }
> +
> + /* Now that everything is setup, enable the DVFS at hardware level */
> + armada37xx_cpufreq_enable_dvfs(nb_pm_base);
> +
> + pdev = platform_device_register_simple("cpufreq-dt", -1, NULL, 0);
> +
> + return PTR_ERR_OR_ZERO(pdev);
> +}
> +/* late_initcall, to guarantee the driver is loaded after A37xx clock driver */
> +late_initcall(armada37xx_cpufreq_driver_init);
> +
> +MODULE_AUTHOR("Gregory CLEMENT <gregory.clement@free-electrons.com>");
> +MODULE_DESCRIPTION("Armada 37xx cpufreq driver");
> +MODULE_LICENSE("GPL");
I am not objecting to using double spaces at all these locations, its fine. Just
that I wanted to point it out in case it is not intentional.
--
viresh
^ permalink raw reply
* [PATCH 2/2] ARM: dts: sun8i: Add ADC routing
From: Chen-Yu Tsai @ 2017-12-14 3:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171213123408.10422-3-mylene.josserand@free-electrons.com>
On Wed, Dec 13, 2017 at 8:34 PM, Myl?ne Josserand
<mylene.josserand@free-electrons.com> wrote:
> Add the ADC route between the analog and the digital parts
> of sun8i A33. Configure the MIC1 to use MBIAS and MIC2 to use HBIAS.
>
> Signed-off-by: Myl?ne Josserand <mylene.josserand@free-electrons.com>
> ---
> arch/arm/boot/dts/sun8i-a33.dtsi | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi
> index 22660919bd08..1841eecd5993 100644
> --- a/arch/arm/boot/dts/sun8i-a33.dtsi
> +++ b/arch/arm/boot/dts/sun8i-a33.dtsi
> @@ -191,7 +191,15 @@
> simple-audio-card,aux-devs = <&codec_analog>;
> simple-audio-card,routing =
> "Left DAC", "AIF1 Slot 0 Left",
> - "Right DAC", "AIF1 Slot 0 Right";
> + "Right DAC", "AIF1 Slot 0 Right",
> + "AIF1 Slot 0 Left ADC", "Left ADC",
> + "AIF1 Slot 0 Right ADC", "Right ADC",
> + "Left ADC", "ADC",
> + "Right ADC", "ADC",
> + "Mic", "MBIAS",
> + "Headset Mic", "HBIAS",
> + "MIC1", "Mic",
> + "MIC2", "Headset Mic";
These entries are board level routing. They should be done in the
board dts files. Unfortunately device tree does not provide a way
to "append" entries to properties, which means one has to copy all
the preceding entries as well.
Also, you are not adding the "Mic" and "Headset Mic" widgets. A33
uses simple-card, which means these connection/board level widgets
must be added using simple-audio-card,widgets.
ChenYu
> status = "disabled";
>
> simple-audio-card,cpu {
> --
> 2.11.0
>
^ permalink raw reply
* [PATCH 2/3] reset: meson-axg: add compatible string for Meson-AXG SoC
From: Yixun Lan @ 2017-12-14 3:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513180898.9445.3.camel@pengutronix.de>
On 12/14/17 00:01, Philipp Zabel wrote:
> Hi Yixun,
>
> On Wed, 2017-12-13 at 22:07 +0800, Yixun Lan wrote:
>> Hi Philipp
>>
>> On 11/10/2017 04:46 PM, Yixun Lan wrote:
>>> Try to add compatible string explictly to support new Meson-AXG SoC.
>>>
>>> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
>>> ---
>>> drivers/reset/reset-meson.c | 2 ++
>>> 1 file changed, 2 insertions(+)
>>>
>>> diff --git a/drivers/reset/reset-meson.c b/drivers/reset/reset-meson.c
>>> index c419a3753d00..93cbee1ae8ef 100644
>>> --- a/drivers/reset/reset-meson.c
>>> +++ b/drivers/reset/reset-meson.c
>>> @@ -139,6 +139,8 @@ static const struct of_device_id meson_reset_dt_ids[] = {
>>> .data = &meson_reset_meson8_ops, },
>>> { .compatible = "amlogic,meson-gxbb-reset",
>>> .data = &meson_reset_gx_ops, },
>>> + { .compatible = "amlogic,meson-axg-reset",
>>> + .data = &meson_reset_gx_ops, },
>>> { /* sentinel */ },
>>> };
>>>
>>>
>>
>> it's generally a ping to the status of these two patches[1], are they
>> ready to go? or do you have any comment? or do you want me to send
>> another version with Neil's Reviewed-by added[1]
>
> I forgot to update you on the status. I have put both patches on the
> reset/next branch with Neil's R-b, they are in linux-next:
>
> 0e5721f76252 ("reset: meson-axg: add compatible string for Meson-AXG SoC")
> c16292578ffa ("dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller")
>
> I'll include them with the next pull request.
>
Hi Philipp
great & thanks.
Hi Kevin:
could you take the DT part[1] via your tree, also with Neil's
Reviewed-by added? I've checked, it could apply cleanly to your
v4.16/dt64 branch
many thanks
Yixun
[1]
http://lists.infradead.org/pipermail/linux-amlogic/2017-November/005280.html
^ permalink raw reply
* [PATCH v4 03/15] dt-bindings: display: sun4i-drm: Add LVDS properties
From: Chen-Yu Tsai @ 2017-12-14 3:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8b7042f5e85cc868ea802deba79a0c53ffbe6564.1512662253.git-series.maxime.ripard@free-electrons.com>
On Thu, Dec 7, 2017 at 11:58 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> Some clocks and resets supposed to drive the LVDS logic in the display
> engine have been overlooked when the driver was first introduced.
>
> Add those additional resources to the binding, and we'll deal with the ABI
> stability in the code.
>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
^ permalink raw reply
* [PATCH v4 06/15] drm/sun4i: Force the mixer rate at 150MHz
From: Chen-Yu Tsai @ 2017-12-14 3:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <34f2c9d5c9ab48ead94253144a8e829cccfa4653.1512662253.git-series.maxime.ripard@free-electrons.com>
On Thu, Dec 7, 2017 at 11:58 PM, Maxime Ripard
<maxime.ripard@free-electrons.com> wrote:
> It seems like the mixer can only run properly when clocked at 150MHz. In
> order to have something more robust than simply a fire-and-forget
> assigned-clocks-rate, let's put that in the code.
>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> drivers/gpu/drm/sun4i/sun8i_mixer.c | 9 +++++++++
> drivers/gpu/drm/sun4i/sun8i_mixer.h | 3 +++
> 2 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> index 29ceeb016d72..ff235e3228ce 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
> @@ -400,6 +400,14 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
> }
> clk_prepare_enable(mixer->mod_clk);
>
> + /*
> + * It seems that we need to enforce that rate for whatever
> + * reason for the mixer to be functional. Make sure it's the
> + * case.
> + */
> + if (mixer->cfg->mod_rate)
> + clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate);
> +
I think it might be better to set the rate first, then enable the clock.
This is sort of implied by the user manual saying "PLLs other than CPU
do not support DVFS". And it fits better with CLK_SET_RATE_GATE semantics,
if we ever adopt it.
Otherwise,
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> list_add_tail(&mixer->engine.list, &drv->engine_list);
>
> /* Reset the registers */
> @@ -474,6 +482,7 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
> .ui_num = 1,
> .scaler_mask = 0x3,
> .ccsc = 0,
> + .mod_rate = 150000000,
> };
>
> static const struct of_device_id sun8i_mixer_of_table[] = {
> diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
> index bc58040a88f9..f34e70c42adf 100644
> --- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
> +++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
> @@ -121,12 +121,15 @@ struct de2_fmt_info {
> * Set value to 0 if this is first mixer or second mixer with VEP support.
> * Set value to 1 if this is second mixer without VEP support. Other values
> * are invalid.
> + * @mod_rate: module clock rate that needs to be set in order to have
> + * a functional block.
> */
> struct sun8i_mixer_cfg {
> int vi_num;
> int ui_num;
> int scaler_mask;
> int ccsc;
> + unsigned long mod_rate;
> };
>
> struct sun8i_mixer {
> --
> git-series 0.9.1
^ permalink raw reply
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