* [PATCH 03/14] ARM: configs: keystone: Enable CONFIG_MMC_SDHCI_OMAP
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Enable CONFIG_MMC_SDHCI_OMAP so that TI's k2g SoC
can use sdhci-omap driver for MMC/SD controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index f710c192b33a..264260a9b1be 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -170,7 +170,10 @@ CONFIG_USB_DWC3=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
2.11.0
^ permalink raw reply related
* [PATCH 02/14] ARM: omap2plus_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Enable CONFIG_MMC_SDHCI_OMAP so that TI's dra7 based SoC's
can use sdhci-omap driver for eMMC/SD/SDIO controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/configs/omap2plus_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 7b97200c1d64..c70a00e1ff6a 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -423,8 +423,11 @@ CONFIG_USB_ZERO=m
CONFIG_USB_G_NOKIA=m
CONFIG_MMC=y
CONFIG_SDIO_UART=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CPCAP=m
--
2.11.0
^ permalink raw reply related
* [PATCH 01/14] ARM: multi_v7_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Enable CONFIG_MMC_SDHCI_OMAP so that TI's dra7/k2g based SoC's
can use sdhci-omap for eMMC/SD/SDIO controller..
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 61509c4b769f..c8761731aaee 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -741,6 +741,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_BCM2835=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
--
2.11.0
^ permalink raw reply related
* [PATCH 00/14] ARM: dra7/k2g: Use sdhci-omap for MMC/SD controller
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
This series enables sdhci-omap driver in omap2plus_defconfig/
keystone_defconfig/multi_v7_defconfig and also modifies the dts
file to use sdhci-omap. Switching to sdhci-omap is required to
support high speed modes like UHS and HS200.
This series should be merged only after [1]
[1] -> https://lkml.org/lkml/2017/12/14/269
The sdhci-omap patches and the dt patches are also pushed to
https://github.com/kishon/linux-wip.git sdhci_omap_uhs
Kishon Vijay Abraham I (10):
ARM: multi_v7_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
ARM: omap2plus_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
ARM: configs: keystone: Enable CONFIG_MMC_SDHCI_OMAP
ARM: dts: am57xx-beagle-x15: Add "vqmmc-supply" property for mmc2
ARM: dts: am57xx-idk: Add "vqmmc-supply" property for mmc2
ARM: dts: dra76-evm: Add "vqmmc-supply" property for mmc2
ARM: dts: dra71-evm: Select pull down for mmc1_clk line in default
mode
ARM: dts: am57xx-idk: Select pull down for mmc1_clk line in default
mode
ARM: dts: dra7: Use sdhci-omap programming model
ARM: dts: keystone-k2g: Use sdhci-omap programming model
Ravikumar Kattekola (1):
ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
Sekhar Nori (3):
ARM: dts: dra76x: Create a common file with MMC/SD IOdelay data
ARM: dts: dra76-evm: Shift to using common IOdelay data
ARM: dts: dra76-evm: Add pinctrl data for higher speed MMC/SD modes
arch/arm/boot/dts/am571x-idk.dts | 2 +-
arch/arm/boot/dts/am572x-idk.dts | 2 +-
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 4 +-
arch/arm/boot/dts/am57xx-idk-common.dtsi | 14 +-
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra7.dtsi | 25 +-
arch/arm/boot/dts/dra71-evm.dts | 17 +-
arch/arm/boot/dts/dra72-evm-common.dtsi | 2 +-
arch/arm/boot/dts/dra76-evm.dts | 53 +--
arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 435 ++++++++++++++++++++++++
arch/arm/boot/dts/keystone-k2g.dtsi | 13 +-
arch/arm/configs/keystone_defconfig | 3 +
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/omap2plus_defconfig | 3 +
14 files changed, 505 insertions(+), 70 deletions(-)
create mode 100644 arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
--
2.11.0
^ permalink raw reply
* [PATCH v2 08/19] arm64: KVM: Dynamically patch the kernel/hyp VA mask
From: Marc Zyngier @ 2017-12-14 13:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5A3279E8.2070507@arm.com>
On 14/12/17 13:17, James Morse wrote:
> Hi Marc,
>
> On 11/12/17 14:49, Marc Zyngier wrote:
>> So far, we're using a complicated sequence of alternatives to
>> patch the kernel/hyp VA mask on non-VHE, and NOP out the
>> masking altogether when on VHE.
>>
>> THe newly introduced dynamic patching gives us the opportunity
>> to simplify that code by patching a single instruction with
>> the correct mask (instead of the mind bending cummulative masking
>> we have at the moment) or even a single NOP on VHE.
>
> (and just a single NOP on VHE?)
Yes, much better. Thanks.
>
>
>> diff --git a/arch/arm64/kvm/haslr.c b/arch/arm64/kvm/haslr.c
>> new file mode 100644
>> index 000000000000..5e1643a4e7bf
>> --- /dev/null
>> +++ b/arch/arm64/kvm/haslr.c
>
>> +u32 __init kvm_update_va_mask(struct alt_instr *alt, int index, u32 oinsn)
>> +{
>> + u32 rd, rn, insn;
>> + u64 imm;
>> +
>> + /* We only expect a 1 instruction sequence */
>> + BUG_ON((alt->alt_len / sizeof(insn)) != 1);
>> +
>> + /* VHE doesn't need any address translation, let's NOP everything */
>> + if (has_vhe())
>> + return aarch64_insn_gen_nop();
>> +
>> + rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
>> + rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
>> +
>> + switch (index) {
>> + default:
>> + /* Something went wrong... */
>> + insn = AARCH64_BREAK_FAULT;
>> + break;
>
> Can this happen? You bug-on alt->alt_len != 1-instruction above, and the loop in
> __apply_alternatives() is calculated in the same way.
> If it can, BUG_ON(index != 0) should catch both cases in one go.
No, it cannot happen. Yes, I'm paranoid. I guess I should just
initialise insn to AARCH64_BREAK_FAULT and achieve the same level of
paranoia without that default clause.
Oh, and it keeps GCC quiet.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v2 08/19] arm64: KVM: Dynamically patch the kernel/hyp VA mask
From: James Morse @ 2017-12-14 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171211144937.4537-9-marc.zyngier@arm.com>
Hi Marc,
On 11/12/17 14:49, Marc Zyngier wrote:
> So far, we're using a complicated sequence of alternatives to
> patch the kernel/hyp VA mask on non-VHE, and NOP out the
> masking altogether when on VHE.
>
> THe newly introduced dynamic patching gives us the opportunity
> to simplify that code by patching a single instruction with
> the correct mask (instead of the mind bending cummulative masking
> we have at the moment) or even a single NOP on VHE.
(and just a single NOP on VHE?)
> diff --git a/arch/arm64/kvm/haslr.c b/arch/arm64/kvm/haslr.c
> new file mode 100644
> index 000000000000..5e1643a4e7bf
> --- /dev/null
> +++ b/arch/arm64/kvm/haslr.c
> +u32 __init kvm_update_va_mask(struct alt_instr *alt, int index, u32 oinsn)
> +{
> + u32 rd, rn, insn;
> + u64 imm;
> +
> + /* We only expect a 1 instruction sequence */
> + BUG_ON((alt->alt_len / sizeof(insn)) != 1);
> +
> + /* VHE doesn't need any address translation, let's NOP everything */
> + if (has_vhe())
> + return aarch64_insn_gen_nop();
> +
> + rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
> + rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
> +
> + switch (index) {
> + default:
> + /* Something went wrong... */
> + insn = AARCH64_BREAK_FAULT;
> + break;
Can this happen? You bug-on alt->alt_len != 1-instruction above, and the loop in
__apply_alternatives() is calculated in the same way.
If it can, BUG_ON(index != 0) should catch both cases in one go.
> + case 0:
> + imm = get_hyp_va_mask();
> + insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
> + AARCH64_INSN_VARIANT_64BIT,
> + rn, rd, imm);
> + break;
> + }
> +
> + BUG_ON(insn == AARCH64_BREAK_FAULT);
> +
> + return insn;
> +}
>
Thanks,
James
^ permalink raw reply
* [PATCH v3 07/11] thermal: armada: Update Kconfig and module description
From: Thomas Petazzoni @ 2017-12-14 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87efnxo8cf.fsf@free-electrons.com>
Hello,
On Thu, 14 Dec 2017 12:30:08 +0100, Gregory CLEMENT wrote:
> Unfortunately Armada SoCs is more that just these SoC!
>
> Have a look on Documentation/arm/Marvell/README to see how the Marvell
> marketing guys had been creative :)
>
> Some kirkwood are called Armada 300 and Armada 310.
> The Dove is also called Armada 510.
> Some PXA are called Armada too such as Armada 168 or Armada 610.
> And finally the Berlin also use Aramda as code name: Armada 1000 or
> Aramda 1500
However: "Marvell EBU Armada" should be distinctive enough.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] KVM: arm/arm64: don't set vtimer->cnt_ctl in kvm_arch_timer_handler
From: Christoffer Dall @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <dc95b58c-ee6c-e5c7-1f37-8f69c789a1fc@gmail.com>
On Thu, Dec 14, 2017 at 12:57:54PM +0800, Jia He wrote:
Hi Jia,
>
> I have tried your newer level-mapped-v7 branch, but bug is still there.
>
> There is no special load in both host and guest. The guest (kernel
> 4.14) is often hanging when booting
>
> the guest kernel log
>
> [ OK ] Reached target Remote File Systems.
> Starting File System Check on /dev/mapper/fedora-root...
> [ OK ] Started File System Check on /dev/mapper/fedora-root.
> Mounting /sysroot...
> [ 2.670764] SGI XFS with ACLs, security attributes, no debug enabled
> [ 2.678180] XFS (dm-0): Mounting V5 Filesystem
> [ 2.740364] XFS (dm-0): Ending clean mount
> [ OK ] Mounted /sysroot.
> [ OK ] Reached target Initrd Root File System.
> Starting Reload Configuration from the Real Root...
> [ 61.288215] INFO: rcu_sched detected stalls on CPUs/tasks:
> [ 61.290791] 1-...!: (0 ticks this GP) idle=574/0/0 softirq=5/5 fqs=1
> [ 61.293664] (detected by 0, t=6002 jiffies, g=-263, c=-264, q=39760)
> [ 61.296480] Task dump for CPU 1:
> [ 61.297938] swapper/1 R running task 0 0 1 0x00000020
> [ 61.300643] Call trace:
> [ 61.301260] __switch_to+0x6c/0x78
> [ 61.302095] cpu_number+0x0/0x8
> [ 61.302867] rcu_sched kthread starved for 6000 jiffies!
> g18446744073709551353 c18446744073709551352 f0x0 RCU_GP_WAIT_FQS(3)
> ->state=0x402 ->cpu=1
> [ 61.305941] rcu_sched I 0 8 2 0x00000020
> [ 61.307250] Call trace:
> [ 61.307854] __switch_to+0x6c/0x78
> [ 61.308693] __schedule+0x268/0x8f0
> [ 61.309545] schedule+0x2c/0x88
> [ 61.310325] schedule_timeout+0x84/0x3b8
> [ 61.311278] rcu_gp_kthread+0x4d4/0x7d8
> [ 61.312213] kthread+0x134/0x138
> [ 61.313001] ret_from_fork+0x10/0x1c
>
> Maybe my previous patch is not perfect enough, thanks for your comments.
>
> I digged it futher more, do you think below code logic is possibly
> problematic?
>
>
> vtimer_save_state?????????? (vtimer->loaded = false, cntv_ctl is 0)
>
> kvm_arch_timer_handler????????(read cntv_ctl and set vtimer->cnt_ctl = 0)
>
> vtimer_restore_state ? ? ? ? ?? (write vtimer->cnt_ctl to cntv_ctl,
> then cntv_ctl will
>
> ??? ??? ??? ??? ?? ? ? be 0 forever)
>
>
> If above analysis is reasonable
Yes, I think there's something there if the hardware doesn't retire the
signal fast enough...
> how about below patch? already
> tested in my arm64 server.
>
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index f9555b1..ee6dd3f 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -99,7 +99,7 @@ static irqreturn_t kvm_arch_timer_handler(int irq,
> void *dev_id)
> ??????? }
> ??????? vtimer = vcpu_vtimer(vcpu);
>
> -?????? if (!vtimer->irq.level) {
> +?????? if (vtimer->loaded && !vtimer->irq.level) {
> ??????????????? vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl);
> ??????????????? if (kvm_timer_irq_can_fire(vtimer))
> ??????????????????????? kvm_timer_update_irq(vcpu, true, vtimer);
>
There's nothing really wrong with that patch, I just didn't think it
would be necessary, as we really shouldn't see interrupts if the timer
is not loaded. Can you confirm that a WARN_ON(!vtimer->loaded) in
kvm_arch_timer_handler() gives you a splat?
Also, could you give the following a try (without your patch):
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 73d262c4712b..4751255345d1 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -367,6 +367,7 @@ static void vtimer_save_state(struct kvm_vcpu *vcpu)
/* Disable the virtual timer */
write_sysreg_el0(0, cntv_ctl);
+ isb();
vtimer->loaded = false;
out:
Thanks,
-Christoffer
^ permalink raw reply related
* [PATCH 12/12] ARM: OMAP2+: Use sdhci-omap specific pdata-quirks for MMC/SD on DRA74x EVM
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Use sdhci-omap specific pdata-quirks for MMC/SD on DRA74x EVM since
UHS modes are supported only in sdhci-omap (and not in omap-hsmmc).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/mach-omap2/pdata-quirks.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 6b433fce65a5..92fb8828d57f 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -21,7 +21,7 @@
#include <linux/regulator/fixed.h>
#include <linux/platform_data/pinctrl-single.h>
-#include <linux/platform_data/hsmmc-omap.h>
+#include <linux/platform_data/sdhci-omap.h>
#include <linux/platform_data/iommu-omap.h>
#include <linux/platform_data/wkup_m3.h>
#include <linux/platform_data/pwm_omap_dmtimer.h>
@@ -38,7 +38,7 @@
#include "soc.h"
#include "hsmmc.h"
-static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2];
+static struct sdhci_omap_platform_data __maybe_unused mmc_pdata[2];
struct pdata_init {
const char *compatible;
@@ -435,21 +435,21 @@ static void __init omap5_uevm_legacy_init(void)
#endif
#ifdef CONFIG_SOC_DRA7XX
-static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1;
-static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2;
-static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3;
+static struct sdhci_omap_platform_data dra7_sdhci_data_mmc1;
+static struct sdhci_omap_platform_data dra7_sdhci_data_mmc2;
+static struct sdhci_omap_platform_data dra7_sdhci_data_mmc3;
static void __init dra7x_evm_mmc_quirk(void)
{
if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) {
- dra7_hsmmc_data_mmc1.version = "rev11";
- dra7_hsmmc_data_mmc1.max_freq = 96000000;
+ dra7_sdhci_data_mmc1.version = "rev11";
+ dra7_sdhci_data_mmc1.max_freq = 96000000;
- dra7_hsmmc_data_mmc2.version = "rev11";
- dra7_hsmmc_data_mmc2.max_freq = 48000000;
+ dra7_sdhci_data_mmc2.version = "rev11";
+ dra7_sdhci_data_mmc2.max_freq = 48000000;
- dra7_hsmmc_data_mmc3.version = "rev11";
- dra7_hsmmc_data_mmc3.max_freq = 48000000;
+ dra7_sdhci_data_mmc3.version = "rev11";
+ dra7_sdhci_data_mmc3.max_freq = 48000000;
}
}
#endif
@@ -582,12 +582,12 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
&omap4_iommu_pdata),
#endif
#ifdef CONFIG_SOC_DRA7XX
- OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc",
- &dra7_hsmmc_data_mmc1),
- OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc",
- &dra7_hsmmc_data_mmc2),
- OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc",
- &dra7_hsmmc_data_mmc3),
+ OF_DEV_AUXDATA("ti,dra7-sdhci", 0x4809c000, "4809c000.mmc",
+ &dra7_sdhci_data_mmc1),
+ OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480b4000, "480b4000.mmc",
+ &dra7_sdhci_data_mmc2),
+ OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480ad000, "480ad000.mmc",
+ &dra7_sdhci_data_mmc3),
#endif
/* Common auxdata */
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
--
2.11.0
^ permalink raw reply related
* [PATCH 11/12] mmc: sdhci-omap: Add support for MMC/SD controller in k2g SoC
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Add support for the new compatible added specifically to support
k2g's MMC/SD controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index cddc3ad1331f..5e81e29383d9 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -767,6 +767,10 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
.ops = &sdhci_omap_ops,
};
+static const struct sdhci_omap_data k2g_data = {
+ .offset = 0x200,
+};
+
static const struct sdhci_omap_data dra7_data = {
.offset = 0x200,
.flags = SDHCI_OMAP_REQUIRE_IODELAY,
@@ -774,6 +778,7 @@ static const struct sdhci_omap_data dra7_data = {
static const struct of_device_id omap_sdhci_match[] = {
{ .compatible = "ti,dra7-sdhci", .data = &dra7_data },
+ { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
{},
};
MODULE_DEVICE_TABLE(of, omap_sdhci_match);
@@ -882,6 +887,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
int ret;
u32 offset;
struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_omap_host *omap_host;
@@ -908,6 +914,9 @@ static int sdhci_omap_probe(struct platform_device *pdev)
return PTR_ERR(host);
}
+ if (of_device_is_compatible(node, "ti,k2g-sdhci"))
+ host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
+
pltfm_host = sdhci_priv(host);
omap_host = sdhci_pltfm_priv(pltfm_host);
omap_host->host = host;
--
2.11.0
^ permalink raw reply related
* [PATCH 10/12] dt-bindings: sdhci-omap: Add K2G specific binding
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Add binding for the TI's sdhci-omap controller present in K2G.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/mmc/sdhci-omap.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt
index 51775a372c06..8d09b837e350 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt
@@ -4,7 +4,9 @@ Refer to mmc.txt for standard MMC bindings.
Required properties:
- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
+ Should be "ti,k2g-sdhci" for K2G
- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
+ (Not required for K2G).
Example:
mmc1: mmc at 4809c000 {
--
2.11.0
^ permalink raw reply related
* [RFC PATCH 09/12] mmc: sdhci: Use software timer when timeout greater than hardware capablility
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Errata i834 in AM572x Sitara Processors Silicon Revision 2.0, 1.1
(SPRZ429K July 2014?Revised March 2017 [1]) mentions
Under high speed HS200 and SDR104 modes, the functional clock for MMC
modules will reach up to 192 MHz. At this frequency, the maximum obtainable
timeout (DTO = 0xE) through MMC host controller is (1/192MHz)*2^27 = 700ms.
Commands taking longer than 700ms may be affected by this small window
frame. Workaround for this errata is use a software timer instead of
hardware timer to provide the delay requested by the upper layer.
While this errata is specific to AM572x, it is applicable to all sdhci
based controllers when a particular request require timeout greater
than hardware capability.
Re-use the software timer already implemented in sdhci to program the
correct timeout value and also disable the hardware timeout when
the required timeout is greater than hardware capabiltiy in order to
avoid spurious timeout interrupts.
This patch is based on the earlier patch implemented for omap_hsmmc [2]
[1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf
[2] -> https://patchwork.kernel.org/patch/9791449/
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci.c | 41 +++++++++++++++++++++++++++++++++++++++--
drivers/mmc/host/sdhci.h | 11 +++++++++++
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index e9290a3439d5..d0655e1d2cc7 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -673,6 +673,27 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
}
}
+static void sdhci_calc_sw_timeout(struct sdhci_host *host,
+ struct mmc_command *cmd,
+ unsigned int target_timeout)
+{
+ struct mmc_host *mmc = host->mmc;
+ struct mmc_ios *ios = &mmc->ios;
+ struct mmc_data *data = cmd->data;
+ unsigned long long transfer_time;
+
+ if (data) {
+ transfer_time = MMC_BLOCK_TRANSFER_TIME_MS(data->blksz,
+ ios->bus_width,
+ ios->clock);
+ /* calculate timeout for the entire data */
+ host->data_timeout = (data->blocks * (target_timeout +
+ transfer_time));
+ } else if (cmd->flags & MMC_RSP_BUSY) {
+ host->data_timeout = cmd->busy_timeout * MSEC_PER_SEC;
+ }
+}
+
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 count;
@@ -732,8 +753,12 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
}
if (count >= 0xF) {
- DBG("Too large timeout 0x%x requested for CMD%d!\n",
- count, cmd->opcode);
+ DBG("Too large timeout.. using SW timeout for CMD%d!\n",
+ cmd->opcode);
+ sdhci_calc_sw_timeout(host, cmd, target_timeout);
+ host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
count = 0xE;
}
@@ -1198,6 +1223,14 @@ static void sdhci_finish_command(struct sdhci_host *host)
{
struct mmc_command *cmd = host->cmd;
+ if (host->data_timeout) {
+ unsigned long timeout;
+
+ timeout = jiffies +
+ msecs_to_jiffies(host->data_timeout);
+ sdhci_mod_timer(host, host->cmd->mrq, timeout);
+ }
+
host->cmd = NULL;
if (cmd->flags & MMC_RSP_PRESENT) {
@@ -2341,6 +2374,10 @@ static bool sdhci_request_done(struct sdhci_host *host)
return true;
}
+ host->data_timeout = 0;
+ host->ier |= SDHCI_INT_DATA_TIMEOUT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
sdhci_del_timer(host, mrq);
/*
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 54bc444c317f..e6e0278bea1a 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -332,6 +332,15 @@ struct sdhci_adma2_64_desc {
/* Allow for a a command request and a data request at the same time */
#define SDHCI_MAX_MRQS 2
+/*
+ * Time taken for transferring one block. It is multiplied by a constant
+ * factor '2' to account for any errors
+ */
+#define MMC_BLOCK_TRANSFER_TIME_MS(blksz, bus_width, freq) \
+ ((unsigned long long) \
+ (2 * (((blksz) * MSEC_PER_SEC * \
+ (8 / (bus_width))) / (freq))))
+
enum sdhci_cookie {
COOKIE_UNMAPPED,
COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
@@ -546,6 +555,8 @@ struct sdhci_host {
/* Host SDMA buffer boundary. */
u32 sdma_boundary;
+ unsigned long long data_timeout;
+
unsigned long private[0] ____cacheline_aligned;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 08/12] mmc: sdhci-omap: Add support to override f_max and iodelay from pdata
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
DRA74x EVM Rev H EVM comes with revision 2.0 silicon. However, earlier
versions of EVM can come with either revision 1.1 or revision 1.0 of
silicon.
The device-tree file is written to support rev 2.0 of silicon.
pdata-quirks are used to then override the settings needed for
PG 1.1 silicon.
PG 1.1 silicon has limitations w.r.t frequencies at which MMC1/2/3
can operate as well as different IOdelay numbers.
Add support in sdhci-omap driver to get platform data if available
(added using pdata quirks) and override the data (max-frequency and
iodelay data) obtained from device tree.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 17 ++++++++++++++++
include/linux/platform_data/sdhci-omap.h | 35 ++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 include/linux/platform_data/sdhci-omap.h
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 6dee275b2e57..cddc3ad1331f 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -22,6 +22,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/platform_data/sdhci-omap.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
@@ -102,6 +103,7 @@ struct sdhci_omap_data {
};
struct sdhci_omap_host {
+ char *version;
void __iomem *base;
struct device *dev;
struct regulator *pbias;
@@ -781,11 +783,18 @@ static struct pinctrl_state
u32 *caps, u32 capmask)
{
struct device *dev = omap_host->dev;
+ char *version = omap_host->version;
struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
+ char str[20];
if (!(*caps & capmask))
goto ret;
+ if (version) {
+ sprintf(str, "%s-%s", mode, version);
+ pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
+ }
+
pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
if (IS_ERR(pinctrl_state)) {
dev_err(dev, "no pinctrl state for %s mode", mode);
@@ -879,6 +888,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
struct mmc_host *mmc;
const struct of_device_id *match;
struct sdhci_omap_data *data;
+ struct sdhci_omap_platform_data *platform_data;
match = of_match_device(omap_sdhci_match, dev);
if (!match)
@@ -913,6 +923,13 @@ static int sdhci_omap_probe(struct platform_device *pdev)
if (ret)
goto err_pltfm_free;
+ platform_data = dev_get_platdata(dev);
+ if (platform_data) {
+ omap_host->version = platform_data->version;
+ if (platform_data->max_freq)
+ mmc->f_max = platform_data->max_freq;
+ }
+
pltfm_host->clk = devm_clk_get(dev, "fck");
if (IS_ERR(pltfm_host->clk)) {
ret = PTR_ERR(pltfm_host->clk);
diff --git a/include/linux/platform_data/sdhci-omap.h b/include/linux/platform_data/sdhci-omap.h
new file mode 100644
index 000000000000..a46e1240956a
--- /dev/null
+++ b/include/linux/platform_data/sdhci-omap.h
@@ -0,0 +1,35 @@
+/**
+ * SDHCI Controller Platform Data for TI's OMAP SoCs
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __SDHCI_OMAP_PDATA_H__
+#define __SDHCI_OMAP_PDATA_H__
+
+struct sdhci_omap_platform_data {
+ const char *name;
+
+ /*
+ * set if your board has components or wiring that limits the
+ * maximum frequency on the MMC bus
+ */
+ unsigned int max_freq;
+
+ /* string specifying a particular variant of hardware */
+ char *version;
+};
+
+#endif
--
2.11.0
^ permalink raw reply related
* [PATCH 07/12] mmc: sdhci_omap: Fix sdhci-omap quirks
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Remove SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk as gpio card detection
is supported in sdhci-omap.
Add SDHCI_QUIRK2_PRESET_VALUE_BROKEN quirk as setting preset values loads
incorrect CLKD values (for UHS modes).
Remove SDHCI_QUIRK2_NO_1_8_V quirk as sdhci-omap now supports UHS modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 594e41200d8a..6dee275b2e57 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -755,13 +755,12 @@ static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
}
static const struct sdhci_pltfm_data sdhci_omap_pdata = {
- .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
- SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+ .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
SDHCI_QUIRK_NO_HISPD_BIT |
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
- .quirks2 = SDHCI_QUIRK2_NO_1_8_V |
- SDHCI_QUIRK2_ACMD23_BROKEN |
+ .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
+ SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_RSP_136_HAS_CRC,
.ops = &sdhci_omap_ops,
};
--
2.11.0
^ permalink raw reply related
* [PATCH 06/12] mmc: sdhci_omap: Add support to set IODELAY values
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met.
Add support to set the IODELAY values depending on the various MMC
modes using the pinctrl APIs.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 174 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 174 insertions(+)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index b20f4c79ccc6..594e41200d8a 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -93,8 +93,12 @@
#define MAX_PHASE_DELAY 0x7C
+/* sdhci-omap controller flags */
+#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
+
struct sdhci_omap_data {
u32 offset;
+ u8 flags;
};
struct sdhci_omap_host {
@@ -105,6 +109,20 @@ struct sdhci_omap_host {
struct sdhci_host *host;
u8 bus_mode;
u8 power_mode;
+ u8 timing;
+ u8 flags;
+
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pinctrl_state;
+ struct pinctrl_state *default_pinctrl_state;
+ struct pinctrl_state *sdr104_pinctrl_state;
+ struct pinctrl_state *hs200_1_8v_pinctrl_state;
+ struct pinctrl_state *ddr50_pinctrl_state;
+ struct pinctrl_state *sdr50_pinctrl_state;
+ struct pinctrl_state *sdr25_pinctrl_state;
+ struct pinctrl_state *sdr12_pinctrl_state;
+ struct pinctrl_state *hs_pinctrl_state;
+ struct pinctrl_state *ddr_1_8v_pinctrl_state;
};
static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
@@ -449,6 +467,62 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
return 0;
}
+static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
+{
+ int ret;
+ struct pinctrl_state *pinctrl_state;
+ struct device *dev = omap_host->dev;
+
+ if (omap_host->timing == timing)
+ return;
+
+ sdhci_omap_stop_clock(omap_host);
+
+ switch (timing) {
+ case MMC_TIMING_UHS_SDR104:
+ pinctrl_state = omap_host->sdr104_pinctrl_state;
+ break;
+ case MMC_TIMING_MMC_HS200:
+ pinctrl_state = omap_host->hs200_1_8v_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ pinctrl_state = omap_host->ddr50_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ pinctrl_state = omap_host->sdr50_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_SDR25:
+ pinctrl_state = omap_host->sdr25_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_SDR12:
+ pinctrl_state = omap_host->sdr12_pinctrl_state;
+ break;
+ case MMC_TIMING_SD_HS:
+ case MMC_TIMING_MMC_HS:
+ pinctrl_state = omap_host->hs_pinctrl_state;
+ break;
+ case MMC_TIMING_MMC_DDR52:
+ pinctrl_state = omap_host->ddr_1_8v_pinctrl_state;
+ break;
+ default:
+ pinctrl_state = omap_host->default_pinctrl_state;
+ break;
+ }
+
+ if (omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY) {
+ ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
+ if (ret) {
+ dev_err(dev, "failed to select pinctrl state\n");
+ goto ret;
+ }
+ omap_host->pinctrl_state = pinctrl_state;
+ }
+
+ret:
+ sdhci_omap_start_clock(omap_host);
+ omap_host->timing = timing;
+}
+
static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
u8 power_mode)
{
@@ -485,6 +559,7 @@ static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
omap_host = sdhci_pltfm_priv(pltfm_host);
sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
+ sdhci_omap_set_timing(omap_host, ios->timing);
sdhci_set_ios(mmc, ios);
sdhci_omap_set_power_mode(omap_host, ios->power_mode);
}
@@ -693,6 +768,7 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
static const struct sdhci_omap_data dra7_data = {
.offset = 0x200,
+ .flags = SDHCI_OMAP_REQUIRE_IODELAY,
};
static const struct of_device_id omap_sdhci_match[] = {
@@ -701,6 +777,98 @@ static const struct of_device_id omap_sdhci_match[] = {
};
MODULE_DEVICE_TABLE(of, omap_sdhci_match);
+static struct pinctrl_state
+*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
+ u32 *caps, u32 capmask)
+{
+ struct device *dev = omap_host->dev;
+ struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
+
+ if (!(*caps & capmask))
+ goto ret;
+
+ pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
+ if (IS_ERR(pinctrl_state)) {
+ dev_err(dev, "no pinctrl state for %s mode", mode);
+ *caps &= ~capmask;
+ }
+
+ret:
+ return pinctrl_state;
+}
+
+static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
+ *omap_host)
+{
+ struct device *dev = omap_host->dev;
+ struct sdhci_host *host = omap_host->host;
+ struct mmc_host *mmc = host->mmc;
+ u32 *caps = &mmc->caps;
+ u32 *caps2 = &mmc->caps2;
+ struct pinctrl_state *state;
+
+ if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
+ return 0;
+
+ omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
+ if (IS_ERR(omap_host->pinctrl)) {
+ dev_err(dev, "Cannot get pinctrl\n");
+ return PTR_ERR(omap_host->pinctrl);
+ }
+
+ state = pinctrl_lookup_state(omap_host->pinctrl, "default");
+ if (IS_ERR(state)) {
+ dev_err(dev, "no pinctrl state for default mode\n");
+ return PTR_ERR(state);
+ }
+ omap_host->default_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
+ MMC_CAP_UHS_SDR104);
+ if (!IS_ERR(state))
+ omap_host->sdr104_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
+ MMC_CAP_UHS_DDR50);
+ if (!IS_ERR(state))
+ omap_host->ddr50_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
+ MMC_CAP_UHS_SDR50);
+ if (!IS_ERR(state))
+ omap_host->sdr50_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
+ MMC_CAP_UHS_SDR25);
+ if (!IS_ERR(state))
+ omap_host->sdr25_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
+ MMC_CAP_UHS_SDR12);
+ if (!IS_ERR(state))
+ omap_host->sdr12_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
+ MMC_CAP_1_8V_DDR);
+ if (!IS_ERR(state))
+ omap_host->ddr_1_8v_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
+ MMC_CAP_MMC_HIGHSPEED |
+ MMC_CAP_SD_HIGHSPEED);
+ if (!IS_ERR(state))
+ omap_host->hs_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
+ MMC_CAP2_HS200_1_8V_SDR);
+ if (!IS_ERR(state))
+ omap_host->hs200_1_8v_pinctrl_state = state;
+
+ omap_host->pinctrl_state = omap_host->default_pinctrl_state;
+
+ return 0;
+}
+
static int sdhci_omap_probe(struct platform_device *pdev)
{
int ret;
@@ -737,6 +905,8 @@ static int sdhci_omap_probe(struct platform_device *pdev)
omap_host->base = host->ioaddr;
omap_host->dev = dev;
omap_host->power_mode = MMC_POWER_UNDEFINED;
+ omap_host->timing = MMC_TIMING_LEGACY;
+ omap_host->flags = data->flags;
host->ioaddr += offset;
mmc = host->mmc;
@@ -785,6 +955,10 @@ static int sdhci_omap_probe(struct platform_device *pdev)
goto err_put_sync;
}
+ ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
+ if (ret)
+ goto err_put_sync;
+
host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
host->mmc_host_ops.start_signal_voltage_switch =
sdhci_omap_start_signal_voltage_switch;
--
2.11.0
^ permalink raw reply related
* [PATCH 05/12] mmc: sdhci-omap: Workaround for Errata i802
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Errata i802 in AM572x Sitara Processors Silicon Revision 2.0, 1.1
(SPRZ429K July 2014?Revised March 2017 [1]) mentions
DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
during the tuning procedure and it has to be disabled during the
tuning procedure Implement workaround for Errata i802 here..
[1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index df8a0a472996..b20f4c79ccc6 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -266,6 +266,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_omap_host *omap_host;
struct device *dev;
+ u32 ier = host->ier;
pltfm_host = sdhci_priv(host);
omap_host = sdhci_pltfm_priv(pltfm_host);
@@ -283,6 +284,16 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
reg |= DLL_SWT;
sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
+ /*
+ * OMAP5/DRA74X/DRA72x Errata i802:
+ * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
+ * during the tuning procedure. So disable it during the
+ * tuning procedure.
+ */
+ ier &= ~SDHCI_INT_DATA_CRC;
+ sdhci_writel(host, ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+
while (phase_delay <= MAX_PHASE_DELAY) {
sdhci_omap_set_dll(omap_host, phase_delay);
@@ -328,6 +339,8 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
ret:
sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
return ret;
}
--
2.11.0
^ permalink raw reply related
* [PATCH 04/12] mmc: sdhci-omap: Add tuning support
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
MMC tuning procedure is required to support SD card
UHS1-SDR104 mode and EMMC HS200 mode.
SDR104/HS200 DLL Tuning Procedure for AM572x platform is mentioned
in Figure 25-51. SDR104/HS200 DLL Tuning Procedure of
AM572x Sitara Processors Silicon Revision 2.0, 1.1 TRM
(SPRUHZ6I - October 2014?Revised April 2017 [1]).
The tuning function sdhci_omap_execute_tuning() will only be
called by the MMC/SD core if the corresponding speed modes
are supported by the OMAP silicon which is set in the mmc
host "caps" field.
[1] -> http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 130 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 130 insertions(+)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 8f7239e2edc2..df8a0a472996 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -37,6 +37,13 @@
#define CON_INIT BIT(1)
#define CON_OD BIT(0)
+#define SDHCI_OMAP_DLL 0x0134
+#define DLL_SWT BIT(20)
+#define DLL_FORCE_SR_C_SHIFT 13
+#define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
+#define DLL_FORCE_VALUE BIT(12)
+#define DLL_CALIB BIT(1)
+
#define SDHCI_OMAP_CMD 0x20c
#define SDHCI_OMAP_PSTATE 0x0224
@@ -66,12 +73,16 @@
#define SDHCI_OMAP_AC12 0x23c
#define AC12_V1V8_SIGEN BIT(19)
+#define AC12_SCLK_SEL BIT(23)
#define SDHCI_OMAP_CAPA 0x240
#define CAPA_VS33 BIT(24)
#define CAPA_VS30 BIT(25)
#define CAPA_VS18 BIT(26)
+#define SDHCI_OMAP_CAPA2 0x0244
+#define CAPA2_TSDR50 BIT(13)
+
#define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
#define SYSCTL_CLKD_MAX 0x3FF
@@ -80,6 +91,8 @@
#define IOV_3V0 3000000 /* 300000 uV */
#define IOV_3V3 3300000 /* 330000 uV */
+#define MAX_PHASE_DELAY 0x7C
+
struct sdhci_omap_data {
u32 offset;
};
@@ -204,6 +217,120 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
}
}
+static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
+ int count)
+{
+ int i;
+ u32 reg;
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
+ reg |= DLL_FORCE_VALUE;
+ reg &= ~DLL_FORCE_SR_C_MASK;
+ reg |= (count << DLL_FORCE_SR_C_SHIFT);
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
+
+ reg |= DLL_CALIB;
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
+ for (i = 0; i < 1000; i++) {
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
+ if (reg & DLL_CALIB)
+ break;
+ }
+ reg &= ~DLL_CALIB;
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
+}
+
+static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
+{
+ u32 reg;
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
+ reg &= ~AC12_SCLK_SEL;
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
+ reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
+}
+
+static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
+{
+ u32 reg;
+ int ret = 0;
+ u8 cur_match, prev_match = 0;
+ u32 phase_delay = 0;
+ u32 start_window = 0, max_window = 0;
+ u32 length = 0, max_len = 0;
+ struct mmc_ios *ios = &mmc->ios;
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_omap_host *omap_host;
+ struct device *dev;
+
+ pltfm_host = sdhci_priv(host);
+ omap_host = sdhci_pltfm_priv(pltfm_host);
+ dev = omap_host->dev;
+
+ /* clock tuning is not needed for upto 52MHz */
+ if (ios->clock <= 52000000)
+ return 0;
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
+ if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
+ return 0;
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
+ reg |= DLL_SWT;
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
+
+ while (phase_delay <= MAX_PHASE_DELAY) {
+ sdhci_omap_set_dll(omap_host, phase_delay);
+
+ cur_match = !mmc_send_tuning(mmc, opcode, NULL);
+ if (cur_match) {
+ if (prev_match) {
+ length++;
+ } else {
+ start_window = phase_delay;
+ length = 1;
+ }
+ }
+
+ if (length > max_len) {
+ max_window = start_window;
+ max_len = length;
+ }
+
+ prev_match = cur_match;
+ phase_delay += 4;
+ }
+
+ if (!max_len) {
+ dev_err(dev, "Unable to find match\n");
+ ret = -EIO;
+ goto tuning_error;
+ }
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
+ if (!(reg & AC12_SCLK_SEL)) {
+ ret = -EIO;
+ goto tuning_error;
+ }
+
+ phase_delay = max_window + 4 * (max_len >> 1);
+ sdhci_omap_set_dll(omap_host, phase_delay);
+
+ goto ret;
+
+tuning_error:
+ dev_err(dev, "Tuning failed\n");
+ sdhci_omap_disable_tuning(omap_host);
+
+ret:
+ sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
+ return ret;
+}
+
static int sdhci_omap_card_busy(struct mmc_host *mmc)
{
int i;
@@ -312,6 +439,8 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
u8 power_mode)
{
+ if (omap_host->bus_mode == MMC_POWER_OFF)
+ sdhci_omap_disable_tuning(omap_host);
omap_host->power_mode = power_mode;
}
@@ -648,6 +777,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
sdhci_omap_start_signal_voltage_switch;
host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
+ host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
sdhci_read_caps(host);
host->caps |= SDHCI_CAN_DO_ADMA2;
--
2.11.0
^ permalink raw reply related
* [PATCH 03/12] mmc: sdhci-omap: Add custom set_uhs_signaling sdhci_host ops
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
UHS-1 DDR50 and MMC DDR52 mode require DDR bit to be
set in the configuration register (MMCHS_CON). Add
sdhci-omap specific set_uhs_signaling ops to set
this bit. Also while setting the UHSMS bit, clock should be
disabled.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index defe4eac020d..8f7239e2edc2 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -31,6 +31,7 @@
#define SDHCI_OMAP_CON 0x12c
#define CON_DW8 BIT(5)
#define CON_DMA_MASTER BIT(20)
+#define CON_DDR BIT(19)
#define CON_CLKEXTFREE BIT(16)
#define CON_PADEN BIT(15)
#define CON_INIT BIT(1)
@@ -93,6 +94,9 @@ struct sdhci_omap_host {
u8 power_mode;
};
+static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
+static void sdhci_omap_stop_clock(struct sdhci_omap_host *omap_host);
+
static inline u32 sdhci_omap_readl(struct sdhci_omap_host *host,
unsigned int offset)
{
@@ -471,6 +475,26 @@ static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
enable_irq(host->irq);
}
+static void sdhci_omap_set_uhs_signaling(struct sdhci_host *host,
+ unsigned int timing)
+{
+ u32 reg;
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
+
+ sdhci_omap_stop_clock(omap_host);
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
+ if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52)
+ reg |= CON_DDR;
+ else
+ reg &= ~CON_DDR;
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
+
+ sdhci_set_uhs_signaling(host, timing);
+ sdhci_omap_start_clock(omap_host);
+}
+
static struct sdhci_ops sdhci_omap_ops = {
.set_clock = sdhci_omap_set_clock,
.set_power = sdhci_omap_set_power,
@@ -480,7 +504,7 @@ static struct sdhci_ops sdhci_omap_ops = {
.set_bus_width = sdhci_omap_set_bus_width,
.platform_send_init_74_clocks = sdhci_omap_init_74_clocks,
.reset = sdhci_reset,
- .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .set_uhs_signaling = sdhci_omap_set_uhs_signaling,
};
static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
--
2.11.0
^ permalink raw reply related
* [PATCH 02/12] mmc: sdhci-omap: Add card_busy host ops
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
card_busy ops is used by mmc core in
1) mmc_set_uhs_voltage to verify voltage switch
2) __mmc_start_request/mmc_poll_for_busy to check the card busy status
While only DAT0 can be used to check the card busy status (in '2' above),
CMD and DAT[0..3] is used to verify voltage switch (in '1' above).
The voltage switching sequence for AM572x platform is mentioned
in Figure 25-48. eMMC/SD/SDIO Power Switching Procedure of
AM572x Sitara Processors Silicon Revision 2.0, 1.1 TRM
(SPRUHZ6I - October 2014?Revised April 2017 [1]).
Add card_busy host ops in sdhci_omap that checks for both CMD and
DAT[0..3]. card_busy here returns true if one of CMD and DAT[0..3] is
low though during voltage switch sequence all of CMD and DAT[0..3] has
to be low (however haven't observed a case where some DAT lines are low
and some are high).
In the voltage switching sequence, CLKEXTFREE bit in MMCHS_CON
should also be set after switching to 1.8v which is also taken
care in the card_busy ops.
[1] -> http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 62 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 96985786cadf..defe4eac020d 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -31,11 +31,20 @@
#define SDHCI_OMAP_CON 0x12c
#define CON_DW8 BIT(5)
#define CON_DMA_MASTER BIT(20)
+#define CON_CLKEXTFREE BIT(16)
+#define CON_PADEN BIT(15)
#define CON_INIT BIT(1)
#define CON_OD BIT(0)
#define SDHCI_OMAP_CMD 0x20c
+#define SDHCI_OMAP_PSTATE 0x0224
+#define PSTATE_CLEV BIT(24)
+#define PSTATE_DLEV_SHIFT 20
+#define PSTATE_DLEV_DAT(x) (1 << (PSTATE_DLEV_SHIFT + (x)))
+#define PSTATE_DLEV (PSTATE_DLEV_DAT(0) | PSTATE_DLEV_DAT(1) | \
+ PSTATE_DLEV_DAT(2) | PSTATE_DLEV_DAT(3))
+
#define SDHCI_OMAP_HCTL 0x228
#define HCTL_SDBP BIT(8)
#define HCTL_SDVS_SHIFT 9
@@ -191,6 +200,58 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
}
}
+static int sdhci_omap_card_busy(struct mmc_host *mmc)
+{
+ int i;
+ u32 reg, ac12;
+ int ret = true;
+ struct sdhci_host *host = mmc_priv(mmc);
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_omap_host *omap_host;
+ u32 ier = host->ier;
+
+ pltfm_host = sdhci_priv(host);
+ omap_host = sdhci_pltfm_priv(pltfm_host);
+
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
+ ac12 = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
+ reg &= ~CON_CLKEXTFREE;
+ if (ac12 & AC12_V1V8_SIGEN)
+ reg |= CON_CLKEXTFREE;
+ reg |= CON_PADEN;
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
+
+ disable_irq(host->irq);
+ ier |= SDHCI_INT_CARD_INT;
+ sdhci_writel(host, ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
+
+ for (i = 0; i < 5; i++) {
+ /*
+ * Delay is required for PSTATE to correctly reflect
+ * DLEV/CLEV values after PADEM is set.
+ */
+ usleep_range(100, 200);
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_PSTATE);
+ if ((reg & PSTATE_CLEV) &&
+ ((reg & PSTATE_DLEV) == PSTATE_DLEV)) {
+ ret = false;
+ goto ret;
+ }
+ }
+
+ret:
+ reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CON);
+ reg &= ~(CON_CLKEXTFREE | CON_PADEN);
+ sdhci_omap_writel(omap_host, SDHCI_OMAP_CON, reg);
+
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
+ enable_irq(host->irq);
+
+ return ret;
+}
+
static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
struct mmc_ios *ios)
{
@@ -562,6 +623,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
host->mmc_host_ops.start_signal_voltage_switch =
sdhci_omap_start_signal_voltage_switch;
host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
+ host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
sdhci_read_caps(host);
host->caps |= SDHCI_CAN_DO_ADMA2;
--
2.11.0
^ permalink raw reply related
* [PATCH 01/12] mmc: sdhci-omap: Update 'power_mode' outside sdhci_omap_init_74_clocks
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Updating 'power_mode' in sdhci_omap_init_74_clocks results in
'power_mode' never updated to MMC_POWER_OFF during card
removal. This results in initialization sequence not sent to the
card during re-insertion.
Fix it here by adding sdhci_omap_set_power_mode to update power_mode.
This function can also be used later to perform operations that
are specific to a power mode (e.g, disable tuning during power off).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 628bfe9a3d17..96985786cadf 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -244,6 +244,12 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
return 0;
}
+static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
+ u8 power_mode)
+{
+ omap_host->power_mode = power_mode;
+}
+
static void sdhci_omap_set_bus_mode(struct sdhci_omap_host *omap_host,
unsigned int mode)
{
@@ -273,6 +279,7 @@ static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
sdhci_set_ios(mmc, ios);
+ sdhci_omap_set_power_mode(omap_host, ios->power_mode);
}
static u16 sdhci_omap_calc_divisor(struct sdhci_pltfm_host *host,
@@ -401,8 +408,6 @@ static void sdhci_omap_init_74_clocks(struct sdhci_host *host, u8 power_mode)
sdhci_omap_writel(omap_host, SDHCI_OMAP_STAT, INT_CC_EN);
enable_irq(host->irq);
-
- omap_host->power_mode = power_mode;
}
static struct sdhci_ops sdhci_omap_ops = {
@@ -504,6 +509,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
omap_host->host = host;
omap_host->base = host->ioaddr;
omap_host->dev = dev;
+ omap_host->power_mode = MMC_POWER_UNDEFINED;
host->ioaddr += offset;
mmc = host->mmc;
--
2.11.0
^ permalink raw reply related
* [PATCH 00/12] mmc: sdhci-omap: Add UHS/HS200 mode support
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
Add UHS/HS200 mode support in sdhci-omap. The programming sequence
for voltage switching, tuning is followed from AM572x TRM
http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf
(Similar to all AM57x/DRA7x SoCs). The patch series also implements
workaround for errata published in
http://www.ti.com/lit/er/sprz429k/sprz429k.pdf.
While most of this series is specific to sdhci-omap, it also
patches sdhci to use software timer when the requested timeout
is greater than hardware capablility. This re-uses the SW data timer
already implemented in sdhci while disabling the HW timeout (so that
spurious timeout is not observed). The patch for sdhci.c is based on
an earlier patch that was done specific to omap_hsmmc.c
(https://patchwork.kernel.org/patch/9791449/)
It also includes a pdata-quirk patch since both pdata-quirks and
sdhci-omap uses struct sdhci_omap_platform_data.
The dt patches enabling UHS/HS200 will be follow this patch series.
This series is created on
git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git next
Kishon Vijay Abraham I (12):
mmc: sdhci-omap: Update 'power_mode' outside sdhci_omap_init_74_clocks
mmc: sdhci-omap: Add card_busy host ops
mmc: sdhci-omap: Add custom set_uhs_signaling sdhci_host ops
mmc: sdhci-omap: Add tuning support
mmc: sdhci-omap: Workaround for Errata i802
mmc: sdhci_omap: Add support to set IODELAY values
mmc: sdhci_omap: Fix sdhci-omap quirks
mmc: sdhci-omap: Add support to override f_max and iodelay from pdata
mmc: sdhci: Use software timer when timeout greater than hardware
capablility
dt-bindings: sdhci-omap: Add K2G specific binding
mmc: sdhci-omap: Add support for MMC/SD controller in k2g SoC
ARM: OMAP2+: Use sdhci-omap specific pdata-quirks for MMC/SD on DRA74x
EVM
.../devicetree/bindings/mmc/sdhci-omap.txt | 2 +
arch/arm/mach-omap2/pdata-quirks.c | 34 +-
drivers/mmc/host/sdhci-omap.c | 446 ++++++++++++++++++++-
drivers/mmc/host/sdhci.c | 41 +-
drivers/mmc/host/sdhci.h | 11 +
include/linux/platform_data/sdhci-omap.h | 35 ++
6 files changed, 544 insertions(+), 25 deletions(-)
create mode 100644 include/linux/platform_data/sdhci-omap.h
--
2.11.0
^ permalink raw reply
* [PATCH v2 15/36] KVM: arm64: Move userspace system registers into separate function
From: Christoffer Dall @ 2017-12-14 12:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a965d4ae-2bbf-5f57-61c4-aee38ae74991@arm.com>
On Mon, Dec 11, 2017 at 10:14:23AM +0000, Marc Zyngier wrote:
> On 07/12/17 17:06, Christoffer Dall wrote:
> > There's a semantic difference between the EL1 registers that control
> > operation of a kernel running in EL1 and EL1 registers that only control
> > userspace execution in EL0. Since we can defer saving/restoring the
> > latter, move them into their own function.
> >
> > We also take this chance to rename the function saving/restoring the
> > remaining system register to make it clear this function deals with
> > the EL1 system registers.
> >
> > No functional change.
> >
> > Reviewed-by: Andrew Jones <drjones@redhat.com>
> > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> > ---
> >
> > Notes:
> > Changes since v1:
> > - Added comment about sp_el0 to common save sysreg save/restore functions
> >
> > arch/arm64/kvm/hyp/sysreg-sr.c | 44 +++++++++++++++++++++++++++++++-----------
> > 1 file changed, 33 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/hyp/sysreg-sr.c b/arch/arm64/kvm/hyp/sysreg-sr.c
> > index 68a7d164e5e1..bbfb4d01af88 100644
> > --- a/arch/arm64/kvm/hyp/sysreg-sr.c
> > +++ b/arch/arm64/kvm/hyp/sysreg-sr.c
> > @@ -33,15 +33,24 @@ static void __hyp_text __sysreg_do_nothing(struct kvm_cpu_context *ctxt) { }
> > */
> >
> > static void __hyp_text __sysreg_save_common_state(struct kvm_cpu_context *ctxt)
> > +{
> > + ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1);
> > +
> > + /*
> > + * The host arm64 Linux uses sp_el0 to point to 'current' and it must
> > + * therefore be saved/restored on every entry/exit to/from the guest.
> > + */
> > + ctxt->gp_regs.regs.sp = read_sysreg(sp_el0);
> > +}
> > +
> > +static void __hyp_text __sysreg_save_user_state(struct kvm_cpu_context *ctxt)
> > {
> > ctxt->sys_regs[ACTLR_EL1] = read_sysreg(actlr_el1);
>
> What is the rational for keeping ACTLR_EL1 as part of the user state?
>
The rationale was that I missed the note you pointed me to below, and
therefore I figured that ACTLR_EL1 couldn't affect the host kernel,
because it runs in EL2, but could affect host userspace, which is
incorrect. So I was basically just being overlay cautious.
> > ctxt->sys_regs[TPIDR_EL0] = read_sysreg(tpidr_el0);
> > ctxt->sys_regs[TPIDRRO_EL0] = read_sysreg(tpidrro_el0);
> > - ctxt->sys_regs[MDSCR_EL1] = read_sysreg(mdscr_el1);
> > - ctxt->gp_regs.regs.sp = read_sysreg(sp_el0);
> > }
> >
> > -static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
> > +static void __hyp_text __sysreg_save_el1_state(struct kvm_cpu_context *ctxt)
> > {
> > ctxt->sys_regs[MPIDR_EL1] = read_sysreg(vmpidr_el2);
> > ctxt->sys_regs[CSSELR_EL1] = read_sysreg(csselr_el1);
> > @@ -70,31 +79,42 @@ static void __hyp_text __sysreg_save_state(struct kvm_cpu_context *ctxt)
> > }
> >
> > static hyp_alternate_select(__sysreg_call_save_host_state,
> > - __sysreg_save_state, __sysreg_do_nothing,
> > + __sysreg_save_el1_state, __sysreg_do_nothing,
> > ARM64_HAS_VIRT_HOST_EXTN);
> >
> > void __hyp_text __sysreg_save_host_state(struct kvm_cpu_context *ctxt)
> > {
> > __sysreg_call_save_host_state()(ctxt);
> > __sysreg_save_common_state(ctxt);
> > + __sysreg_save_user_state(ctxt);
> > }
> >
> > void __hyp_text __sysreg_save_guest_state(struct kvm_cpu_context *ctxt)
> > {
> > - __sysreg_save_state(ctxt);
> > + __sysreg_save_el1_state(ctxt);
> > __sysreg_save_common_state(ctxt);
> > + __sysreg_save_user_state(ctxt);
> > }
> >
> > static void __hyp_text __sysreg_restore_common_state(struct kvm_cpu_context *ctxt)
> > {
> > - write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
> > - write_sysreg(ctxt->sys_regs[TPIDR_EL0], tpidr_el0);
> > - write_sysreg(ctxt->sys_regs[TPIDRRO_EL0], tpidrro_el0);
> > write_sysreg(ctxt->sys_regs[MDSCR_EL1], mdscr_el1);
> > +
> > + /*
> > + * The host arm64 Linux uses sp_el0 to point to 'current' and it must
> > + * therefore be saved/restored on every entry/exit to/from the guest.
> > + */
> > write_sysreg(ctxt->gp_regs.regs.sp, sp_el0);
> > }
> >
> > -static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
> > +static void __hyp_text __sysreg_restore_user_state(struct kvm_cpu_context *ctxt)
> > +{
> > + write_sysreg(ctxt->sys_regs[ACTLR_EL1], actlr_el1);
>
> Same here.
>
> > + write_sysreg(ctxt->sys_regs[TPIDR_EL0], tpidr_el0);
> > + write_sysreg(ctxt->sys_regs[TPIDRRO_EL0], tpidrro_el0);
> > +}
> > +
> > +static void __hyp_text __sysreg_restore_el1_state(struct kvm_cpu_context *ctxt)
> > {
> > write_sysreg(ctxt->sys_regs[MPIDR_EL1], vmpidr_el2);
> > write_sysreg(ctxt->sys_regs[CSSELR_EL1], csselr_el1);
> > @@ -123,19 +143,21 @@ static void __hyp_text __sysreg_restore_state(struct kvm_cpu_context *ctxt)
> > }
> >
> > static hyp_alternate_select(__sysreg_call_restore_host_state,
> > - __sysreg_restore_state, __sysreg_do_nothing,
> > + __sysreg_restore_el1_state, __sysreg_do_nothing,
> > ARM64_HAS_VIRT_HOST_EXTN);
> >
> > void __hyp_text __sysreg_restore_host_state(struct kvm_cpu_context *ctxt)
> > {
> > __sysreg_call_restore_host_state()(ctxt);
> > __sysreg_restore_common_state(ctxt);
> > + __sysreg_restore_user_state(ctxt);
> > }
> >
> > void __hyp_text __sysreg_restore_guest_state(struct kvm_cpu_context *ctxt)
> > {
> > - __sysreg_restore_state(ctxt);
> > + __sysreg_restore_el1_state(ctxt);
> > __sysreg_restore_common_state(ctxt);
> > + __sysreg_restore_user_state(ctxt);
> > }
> >
> > static void __hyp_text __fpsimd32_save_state(struct kvm_cpu_context *ctxt)
> >
>
> I think we should move ACTLR_EL1 to the EL1 state, allowing it to be
> lazily switched. See the note in D10.2.1 that recommends a VHE enabled
> system to have ACTLR_EL1 as a guest-only register.
Thanks for this pointer. I will adjust the code as you suggest.
-Christoffer
^ permalink raw reply
* [PATCH v11 1/3] ACPI/IORT: Add msi address regions reservation helper
From: Lorenzo Pieralisi @ 2017-12-14 12:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5FC3163CFD30C246ABAA99954A238FA838628CDD@FRAEML521-MBX.china.huawei.com>
On Thu, Dec 14, 2017 at 12:17:50PM +0000, Shameerali Kolothum Thodi wrote:
> Hi Lorenzo,
>
> > -----Original Message-----
> > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi at arm.com]
> > Sent: Thursday, December 14, 2017 11:48 AM
> > To: Shameerali Kolothum Thodi <shameerali.kolothum.thodi@huawei.com>
> > Cc: robin.murphy at arm.com; marc.zyngier at arm.com; will.deacon at arm.com;
> > joro at 8bytes.org; John Garry <john.garry@huawei.com>; xuwei (O)
> > <xuwei5@hisilicon.com>; Guohanjun (Hanjun Guo) <guohanjun@huawei.com>;
> > iommu at lists.linux-foundation.org; linux-arm-kernel at lists.infradead.org; linux-
> > acpi at vger.kernel.org; devicetree at vger.kernel.org; Linuxarm
> > <linuxarm@huawei.com>
> > Subject: Re: [PATCH v11 1/3] ACPI/IORT: Add msi address regions reservation
> > helper
> >
> > On Wed, Dec 13, 2017 at 11:58:28AM +0000, Shameer Kolothum wrote:
> > > On some platforms msi parent address regions have to be excluded from
> > > normal IOVA allocation in that they are detected and decoded in a HW
> > > specific way by system components and so they cannot be considered normal
> > > IOVA address space.
> > >
> > > Add a helper function that retrieves ITS address regions - the msi
> > > parent - through IORT device <-> ITS mappings and reserves it so that
> > > these regions will not be translated by IOMMU and will be excluded from
> > > IOVA allocations. The function checks for the smmu model number and
> > > only applies the msi reservation if the platform requires it.
> > >
> > > Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> > > ---
> > > drivers/acpi/arm64/iort.c | 112
> > +++++++++++++++++++++++++++++++++++++--
> > > drivers/irqchip/irq-gic-v3-its.c | 3 +-
> > > include/linux/acpi_iort.h | 7 ++-
> > > 3 files changed, 117 insertions(+), 5 deletions(-)
> >
> > You need this additional hunk to make it compile on !CONFIG_IOMMU_API:
>
> Oops..Sorry, missed that. If you are happy with the rest, I will make the below
> change and sent out the v12(hopefully final).
I am ok with it, yes.
Thanks,
Lorenzo
> Please let me know.
>
> Thanks,
> Shameer
>
> >
> > -- >8 --
> > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> > index 3e0ce652c3e8..e2f7bddf5522 100644
> > --- a/drivers/acpi/arm64/iort.c
> > +++ b/drivers/acpi/arm64/iort.c
> > @@ -762,25 +762,6 @@ static int __maybe_unused __get_pci_rid(struct
> > pci_dev *pdev, u16 alias,
> > return 0;
> > }
> >
> > -static __maybe_unused struct acpi_iort_node *iort_get_msi_resv_iommu(
> > - struct device *dev)
> > -{
> > - struct acpi_iort_node *iommu;
> > - struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> > -
> > - iommu = iort_get_iort_node(fwspec->iommu_fwnode);
> > -
> > - if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) {
> > - struct acpi_iort_smmu_v3 *smmu;
> > -
> > - smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data;
> > - if (smmu->model ==
> > ACPI_IORT_SMMU_V3_HISILICON_HI161X)
> > - return iommu;
> > - }
> > -
> > - return NULL;
> > -}
> > -
> > static int arm_smmu_iort_xlate(struct device *dev, u32 streamid,
> > struct fwnode_handle *fwnode,
> > const struct iommu_ops *ops)
> > @@ -807,6 +788,24 @@ static inline bool iort_iommu_driver_enabled(u8 type)
> > }
> >
> > #ifdef CONFIG_IOMMU_API
> > +static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev)
> > +{
> > + struct acpi_iort_node *iommu;
> > + struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> > +
> > + iommu = iort_get_iort_node(fwspec->iommu_fwnode);
> > +
> > + if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) {
> > + struct acpi_iort_smmu_v3 *smmu;
> > +
> > + smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data;
> > + if (smmu->model ==
> > ACPI_IORT_SMMU_V3_HISILICON_HI161X)
> > + return iommu;
> > + }
> > +
> > + return NULL;
> > +}
> > +
> > static inline const struct iommu_ops *iort_fwspec_iommu_ops(
> > struct iommu_fwspec *fwspec)
> > {
^ permalink raw reply
* [PATCH v2 14/36] KVM: arm64: Remove noop calls to timer save/restore from VHE switch
From: Christoffer Dall @ 2017-12-14 12:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <76009e9a-0518-6b0c-c1f4-9fc5ce6a1138@arm.com>
On Mon, Dec 11, 2017 at 10:02:58AM +0000, Marc Zyngier wrote:
> On 07/12/17 17:06, Christoffer Dall wrote:
> > The VHE switch function calls __timer_enable_traps and
> > __timer_disable_traps which don't do anything on VHE systems.
> > Therefore, simply remove these calls from the VHE switch function and
> > make the functions non-conditional as they are now only called from the
> > non-VHE switch path.
> >
> > Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> > ---
> > arch/arm64/kvm/hyp/switch.c | 2 --
> > virt/kvm/arm/hyp/timer-sr.c | 36 ++++++++++++++----------------------
> > 2 files changed, 14 insertions(+), 24 deletions(-)
> >
> > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c
> > index e783e2371b7c..09aafa0470f7 100644
> > --- a/arch/arm64/kvm/hyp/switch.c
> > +++ b/arch/arm64/kvm/hyp/switch.c
> > @@ -358,7 +358,6 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
> > __activate_vm(vcpu->kvm);
> >
> > __vgic_restore_state(vcpu);
> > - __timer_enable_traps(vcpu);
> >
> > /*
> > * We must restore the 32-bit state before the sysregs, thanks
> > @@ -377,7 +376,6 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
> >
> > __sysreg_save_guest_state(guest_ctxt);
> > __sysreg32_save_state(vcpu);
> > - __timer_disable_traps(vcpu);
> > __vgic_save_state(vcpu);
> >
> > __deactivate_traps(vcpu);
> > diff --git a/virt/kvm/arm/hyp/timer-sr.c b/virt/kvm/arm/hyp/timer-sr.c
> > index f24404b3c8df..752b37f9133c 100644
> > --- a/virt/kvm/arm/hyp/timer-sr.c
> > +++ b/virt/kvm/arm/hyp/timer-sr.c
> > @@ -29,32 +29,24 @@ void __hyp_text __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high)
> >
> > void __hyp_text __timer_disable_traps(struct kvm_vcpu *vcpu)
> > {
> > - /*
> > - * We don't need to do this for VHE since the host kernel runs in EL2
> > - * with HCR_EL2.TGE ==1, which makes those bits have no impact.
> > - */
> > - if (!has_vhe()) {
> > - u64 val;
> > + u64 val;
> >
> > - /* Allow physical timer/counter access for the host */
> > - val = read_sysreg(cnthctl_el2);
> > - val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
> > - write_sysreg(val, cnthctl_el2);
> > - }
> > + /* Allow physical timer/counter access for the host */
> > + val = read_sysreg(cnthctl_el2);
> > + val |= CNTHCTL_EL1PCTEN | CNTHCTL_EL1PCEN;
> > + write_sysreg(val, cnthctl_el2);
> > }
> >
> > void __hyp_text __timer_enable_traps(struct kvm_vcpu *vcpu)
> > {
> > - if (!has_vhe()) {
> > - u64 val;
> > + u64 val;
> >
> > - /*
> > - * Disallow physical timer access for the guest
> > - * Physical counter access is allowed
> > - */
> > - val = read_sysreg(cnthctl_el2);
> > - val &= ~CNTHCTL_EL1PCEN;
> > - val |= CNTHCTL_EL1PCTEN;
> > - write_sysreg(val, cnthctl_el2);
> > - }
> > + /*
> > + * Disallow physical timer access for the guest
> > + * Physical counter access is allowed
> > + */
> > + val = read_sysreg(cnthctl_el2);
> > + val &= ~CNTHCTL_EL1PCEN;
> > + val |= CNTHCTL_EL1PCTEN;
> > + write_sysreg(val, cnthctl_el2);
> > }
> >
>
> Since we're not testing for !VHE anymore, can you add a small comment
> saying that these two function are for the benefit of !VHE only and
> shouldn't be called on VHE?
Yes, absolutely:
diff --git a/virt/kvm/arm/hyp/timer-sr.c b/virt/kvm/arm/hyp/timer-sr.c
index 752b37f9133c..77754a62eb0c 100644
--- a/virt/kvm/arm/hyp/timer-sr.c
+++ b/virt/kvm/arm/hyp/timer-sr.c
@@ -27,6 +27,10 @@ void __hyp_text __kvm_timer_set_cntvoff(u32 cntvoff_low, u32 cntvoff_high)
write_sysreg(cntvoff, cntvoff_el2);
}
+/*
+ * Should only be called on non-VHE systems.
+ * VHE systems use EL2 timers and configure EL1 timers in kvm_timer_init_vhe().
+ */
void __hyp_text __timer_disable_traps(struct kvm_vcpu *vcpu)
{
u64 val;
@@ -37,6 +41,10 @@ void __hyp_text __timer_disable_traps(struct kvm_vcpu *vcpu)
write_sysreg(val, cnthctl_el2);
}
+/*
+ * Should only be called on non-VHE systems.
+ * VHE systems use EL2 timers and configure EL1 timers in kvm_timer_init_vhe().
+ */
void __hyp_text __timer_enable_traps(struct kvm_vcpu *vcpu)
{
u64 val;
>
> Otherwise,
>
> Acked-by: Marc Zyngier <marc.zyngier@arm.com>
>
Thanks,
-Christoffer
^ permalink raw reply related
* [PATCH v3 06/11] thermal: armada: Add support for Armada CP110
From: Miquel RAYNAL @ 2017-12-14 12:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87a7ylo803.fsf@free-electrons.com>
On Thu, 14 Dec 2017 12:37:32 +0100
Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi Miquel,
>
> On jeu., d?c. 14 2017, Miquel RAYNAL
> <miquel.raynal@free-electrons.com> wrote:
>
> > On Thu, 14 Dec 2017 12:11:49 +0100
> > Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> >
> >> Hi Miquel,
> >>
> >> On jeu., d?c. 14 2017, Miquel Raynal
> >> <miquel.raynal@free-electrons.com> wrote:
> >>
> >> > From: Baruch Siach <baruch@tkos.co.il>
> >> >
> >> > The CP110 component is integrated in the Armada 8k and 7k lines
> >> > of processors.
> >> >
> >> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> >> > [<miquel.raynal@free-electrons.com>: renamed the register
> >> > pointers]
> >>
> >> Actually you did more thant this see below
> >>
> >>
> >> > Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
> >> > ---
> >> > drivers/thermal/armada_thermal.c | 30
> >> > ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+),
> >> > 6 deletions(-)
> >> >
> >> > diff --git a/drivers/thermal/armada_thermal.c
> >> > b/drivers/thermal/armada_thermal.c index
> >> > 279d01937bb8..f5c911524656 100644 ---
> >> > a/drivers/thermal/armada_thermal.c +++
> >> > b/drivers/thermal/armada_thermal.c @@ -37,7 +37,6 @@
> >> > #define A375_UNIT_CONTROL_MASK 0x7
> >> > #define A375_READOUT_INVERT BIT(15)
> >> > #define A375_HW_RESETn BIT(8)
> >> > -#define A380_HW_RESET BIT(8)
> >> >
> >> > /* Legacy bindings */
> >> > #define LEGACY_CONTROL_MEM_LEN 0x4
> >> > @@ -52,6 +51,10 @@
> >> > #define CONTROL0_TSEN_RESET BIT(1)
> >> > #define CONTROL0_TSEN_ENABLE BIT(2)
> >> >
> >> > +/* EXT_TSEN refers to the external temperature sensors, out of
> >> > the AP */ +#define CONTROL1_EXT_TSEN_SW_RESET BIT(7)
> >> > +#define CONTROL1_EXT_TSEN_HW_RESETn BIT(8)
> >> You added or rename these values
> >>
> >> > +
> >> > struct armada_thermal_data;
> >> >
> >> > /* Marvell EBU Thermal Sensor Dev Structure */
> >> > @@ -153,11 +156,10 @@ static void armada380_init_sensor(struct
> >> > platform_device *pdev, u32 reg = readl_relaxed(priv->control1);
> >> >
> >> > /* Reset hardware once */
> >> > - if (!(reg & A380_HW_RESET)) {
> >> > - reg |= A380_HW_RESET;
> >> > - writel(reg, priv->control1);
> >> > - msleep(10);
> >> > - }
> >> > + reg |= CONTROL1_EXT_TSEN_HW_RESETn;
> >> > + reg &= ~CONTROL1_EXT_TSEN_SW_RESET;
> >> > + writel(reg, priv->control1);
> >>
> >> And here you modified the behavior of this function.
> >> Did you checked that it is valid for Armada 38x?
> >
> > There is nothing about it the documentation and anyway this register
> > can be accessed later, so writing it is harmless ayway.
> >
> >>
> >> Given the comment we had, I thought we should not do anything if
> >> CONTROL1_EXT_TSEN_HW_RESETn was not set.
> >
> > That is the opposite, if it is not set (ie. reset is active), you
> > have to set it (reset is then disabled).
>
> Actually I was concerned by the "once" for me it means "only one
> time", but maybe it just meant it was useless to reset it again but
> not harmful.
This:
reg |= CONTROL1_EXT_TSEN_HW_RESETn;
does not reset the IP, instead it cancels the reset, if one is
happening. So no, doing it unconditionally is not harmful.
Miqu?l
>
> Gregory
>
> >
> >>
> >> By the way, if the new sequence is valid, this comment should be
> >> removed or at least updated.
> >
> > That's right, I will in v4.
> >
> > Thanks for reviewing,
> > Miqu?l
> >
> >
>
--
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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