* [PATCH 13/14] ARM: dts: dra7: Use sdhci-omap programming model
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Use sdhci-omap programming model based on the generic sdhci
library for programming the first 2 instances of eMMC/SD/SDIO
controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 3 +--
arch/arm/boot/dts/am57xx-idk-common.dtsi | 2 +-
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra7.dtsi | 25 ++++++++++++++++---------
arch/arm/boot/dts/dra72-evm-common.dtsi | 2 +-
arch/arm/boot/dts/dra76-evm.dts | 3 ++-
6 files changed, 22 insertions(+), 14 deletions(-)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 50e7c3c0d111..44e6720bc939 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -444,8 +444,7 @@
vmmc-supply = <&vdd_3v3>;
vqmmc-supply = <&vdd_3v3>;
bus-width = <8>;
- ti,non-removable;
- cap-mmc-dual-data-rate;
+ non-removable;
};
&sata {
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 43cdf523a8a0..855c130afc69 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -423,7 +423,7 @@
vmmc-supply = <&v3_3d>;
vqmmc-supply = <&v3_3d>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
max-frequency = <96000000>;
};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index ef9c90daa74b..b5ec42f16efc 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -351,6 +351,7 @@
status = "okay";
vmmc-supply = <&evm_1v8_sw>;
bus-width = <8>;
+ non-removable;
pinctrl-names = "default", "hs", "ddr_1_8v-rev11", "ddr_1_8v", "hs200_1_8v-rev11", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index ac9216293b7c..1acd77f29d0b 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1057,17 +1057,21 @@
};
mmc1: mmc at 4809c000 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,dra7-sdhci";
reg = <0x4809c000 0x400>;
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc1";
- ti,dual-volt;
- ti,needs-special-reset;
- dmas = <&sdma_xbar 61>, <&sdma_xbar 62>;
- dma-names = "tx", "rx";
status = "disabled";
pbias-supply = <&pbias_mmc_reg>;
max-frequency = <192000000>;
+ sd-uhs-sdr104;
+ sd-uhs-sdr50;
+ sd-uhs-ddr50;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ cap-sd-highspeed;
+ mmc-ddr-1_8v;
+ cap-mmc-highspeed;
};
hdqw1w: 1w at 480b2000 {
@@ -1078,15 +1082,18 @@
};
mmc2: mmc at 480b4000 {
- compatible = "ti,omap4-hsmmc";
+ compatible = "ti,dra7-sdhci";
reg = <0x480b4000 0x400>;
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "mmc2";
- ti,needs-special-reset;
- dmas = <&sdma_xbar 47>, <&sdma_xbar 48>;
- dma-names = "tx", "rx";
status = "disabled";
max-frequency = <192000000>;
+ cap-sd-highspeed;
+ sd-uhs-sdr25;
+ sd-uhs-sdr12;
+ mmc-hs200-1_8v;
+ mmc-ddr-1_8v;
+ cap-mmc-highspeed;
};
mmc3: mmc at 480ad000 {
diff --git a/arch/arm/boot/dts/dra72-evm-common.dtsi b/arch/arm/boot/dts/dra72-evm-common.dtsi
index 2e485a13dfd7..4f48f97c9c47 100644
--- a/arch/arm/boot/dts/dra72-evm-common.dtsi
+++ b/arch/arm/boot/dts/dra72-evm-common.dtsi
@@ -421,7 +421,7 @@
pinctrl-names = "default";
pinctrl-0 = <&mmc2_pins_default>;
bus-width = <8>;
- ti,non-removable;
+ non-removable;
max-frequency = <192000000>;
};
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 4dd8a5ac8fae..02c01cecc417 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -306,7 +306,7 @@
&mmc1 {
status = "okay";
vmmc-supply = <&vio_3v3_sd>;
- vmmc_aux-supply = <&ldo4_reg>;
+ vqmmc-supply = <&ldo4_reg>;
bus-width = <4>;
/*
* SDCD signal is not being used here - using the fact that GPIO mode
@@ -323,6 +323,7 @@
vmmc-supply = <&vio_1v8>;
vqmmc-supply = <&vio_1v8>;
bus-width = <8>;
+ non-removable;
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
pinctrl-1 = <&mmc2_pins_hs>;
--
2.11.0
^ permalink raw reply related
* [PATCH 12/14] ARM: dts: am57xx-idk: Select pull down for mmc1_clk line in default mode
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
During a short period when the bus voltage is switched from 3.3v to 1.8v,
(to enumerate UHS mode), the mmc module is disabled and the mmc IO lines
are kept in a state according to the programmed pad mux pull type.
According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications
Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the
host should hold CLK low for at least 5ms.
In order to keep the card line low during voltage switch, the pad mux of
mmc1_clk line should be configured to pull down.
This is specific to am57xx-idk (and not all dra72/dra74 based boards)
since mmc1_clk line in am57xx-idk is not connected to an external
pullup.
While at that change the order of header files in am571x-idk.dts and
am572x-idk.dts so that the modified pinctrl values in am57xx-idk-common
could take effect.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/am571x-idk.dts | 2 +-
arch/arm/boot/dts/am572x-idk.dts | 2 +-
arch/arm/boot/dts/am57xx-idk-common.dtsi | 11 +++++++++++
3 files changed, 13 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/am571x-idk.dts b/arch/arm/boot/dts/am571x-idk.dts
index debf9464403e..c7d77acffa28 100644
--- a/arch/arm/boot/dts/am571x-idk.dts
+++ b/arch/arm/boot/dts/am571x-idk.dts
@@ -10,8 +10,8 @@
#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include "am57xx-idk-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"
+#include "am57xx-idk-common.dtsi"
/ {
model = "TI AM5718 IDK";
diff --git a/arch/arm/boot/dts/am572x-idk.dts b/arch/arm/boot/dts/am572x-idk.dts
index a578fe97ba3b..144376ad5f35 100644
--- a/arch/arm/boot/dts/am572x-idk.dts
+++ b/arch/arm/boot/dts/am572x-idk.dts
@@ -11,8 +11,8 @@
#include "dra74x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
-#include "am57xx-idk-common.dtsi"
#include "dra74x-mmc-iodelay.dtsi"
+#include "am57xx-idk-common.dtsi"
/ {
model = "TI AM5728 IDK";
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 43a6d0590f7c..43cdf523a8a0 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -115,6 +115,17 @@
DRA7XX_CORE_IOPAD(0x37d4, MUX_MODE15 | PULL_UP) /* dcan1_rx.off */
>;
};
+
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
};
&i2c1 {
--
2.11.0
^ permalink raw reply related
* [PATCH 11/14] ARM: dts: dra71-evm: Select pull down for mmc1_clk line in default mode
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
During a short period when the bus voltage is switched from 3.3v to 1.8v,
(to enumerate UHS mode), the mmc module is disabled and the mmc IO lines
are kept in a state according to the programmed pad mux pull type.
According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications
Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the
host should hold CLK low for at least 5ms.
In order to keep the card line low during voltage switch, the pad mux of
mmc1_clk line should be configured to pull down.
This is specific only to dra71-evm (and not all dra72 based boards) since
mmc1_clk line in dra71-evm is not connected to an external pullup.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra71-evm.dts | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index 64363f75c01a..ebc4bbae981e 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -50,6 +50,19 @@
};
};
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+};
+
&i2c1 {
status = "okay";
clock-frequency = <400000>;
--
2.11.0
^ permalink raw reply related
* [PATCH 10/14] ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
From: Ravikumar Kattekola <rk@ti.com>
Correct vpo_sd_1v8_3v3 regulator max voltage to 3.3V
Fixes: 9868bc585ae2 ("ARM: dts: Add support for dra718-evm")
Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra71-evm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra71-evm.dts b/arch/arm/boot/dts/dra71-evm.dts
index 41c9132eb550..64363f75c01a 100644
--- a/arch/arm/boot/dts/dra71-evm.dts
+++ b/arch/arm/boot/dts/dra71-evm.dts
@@ -24,13 +24,13 @@
regulator-name = "vddshv8";
regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <3000000>;
+ regulator-max-microvolt = <3300000>;
regulator-boot-on;
vin-supply = <&evm_5v0>;
gpios = <&gpio7 11 GPIO_ACTIVE_HIGH>;
states = <1800000 0x0
- 3000000 0x1>;
+ 3300000 0x1>;
};
evm_1v8_sw: fixedregulator-evm_1v8 {
--
2.11.0
^ permalink raw reply related
* [PATCH 09/14] ARM: dts: dra76-evm: Add "vqmmc-supply" property for mmc2
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Add "vqmmc-supply" property for mmc2 to indicate the supply connected
to the IO lines.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra76-evm.dts | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index ec8af5841061..4dd8a5ac8fae 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -321,6 +321,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&vio_1v8>;
+ vqmmc-supply = <&vio_1v8>;
bus-width = <8>;
pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
--
2.11.0
^ permalink raw reply related
* [PATCH 08/14] ARM: dts: am57xx-idk: Add "vqmmc-supply" property for mmc2
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Add "vqmmc-supply" property for mmc2 to indicate the supply connected
to the IO lines.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/am57xx-idk-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/am57xx-idk-common.dtsi b/arch/arm/boot/dts/am57xx-idk-common.dtsi
index 97aa8e6a56da..43a6d0590f7c 100644
--- a/arch/arm/boot/dts/am57xx-idk-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-idk-common.dtsi
@@ -410,6 +410,7 @@
&mmc2 {
status = "okay";
vmmc-supply = <&v3_3d>;
+ vqmmc-supply = <&v3_3d>;
bus-width = <8>;
ti,non-removable;
max-frequency = <96000000>;
--
2.11.0
^ permalink raw reply related
* [PATCH 07/14] ARM: dts: am57xx-beagle-x15: Add "vqmmc-supply" property for mmc2
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Add "vqmmc-supply" property for mmc2 to indicate the supply connected
to the IO lines.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 49aeecd312b4..50e7c3c0d111 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -442,6 +442,7 @@
pinctrl-0 = <&mmc2_pins_default>;
vmmc-supply = <&vdd_3v3>;
+ vqmmc-supply = <&vdd_3v3>;
bus-width = <8>;
ti,non-removable;
cap-mmc-dual-data-rate;
--
2.11.0
^ permalink raw reply related
* [PATCH 06/14] ARM: dts: dra76-evm: Add pinctrl data for higher speed MMC/SD modes
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
From: Sekhar Nori <nsekhar@ti.com>
The SD card interface on DRA76x EVM can support
high speed SD cards. The eMMC onboard can support
upto HS200 mode.
Enable support for these higher speed modes in the
device-tree file.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra76-evm.dts | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index 2770f6d3e1cb..ec8af5841061 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -313,16 +313,20 @@
* is always hardwired.
*/
cd-gpios = <&gpio6 27 GPIO_ACTIVE_LOW>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs";
pinctrl-0 = <&mmc1_pins_default>;
+ pinctrl-1 = <&mmc1_pins_hs>;
};
&mmc2 {
status = "okay";
vmmc-supply = <&vio_1v8>;
bus-width = <8>;
- pinctrl-names = "default";
+ pinctrl-names = "default", "hs", "ddr_1_8v", "hs200_1_8v";
pinctrl-0 = <&mmc2_pins_default>;
+ pinctrl-1 = <&mmc2_pins_hs>;
+ pinctrl-2 = <&mmc2_pins_ddr>;
+ pinctrl-3 = <&mmc2_pins_hs200 &mmc2_iodelay_hs200_conf>;
};
/* No RTC on this device */
--
2.11.0
^ permalink raw reply related
* [PATCH 05/14] ARM: dts: dra76-evm: Shift to using common IOdelay data
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
From: Sekhar Nori <nsekhar@ti.com>
Now that we have a device-tree include file with common
MMC/SD IOdelay data for DRA76x SoC, shift the EVM device-tree
file to using that.
Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra76-evm.dts | 41 +----------------------------------------
1 file changed, 1 insertion(+), 40 deletions(-)
diff --git a/arch/arm/boot/dts/dra76-evm.dts b/arch/arm/boot/dts/dra76-evm.dts
index b024a65c6e27..2770f6d3e1cb 100644
--- a/arch/arm/boot/dts/dra76-evm.dts
+++ b/arch/arm/boot/dts/dra76-evm.dts
@@ -9,6 +9,7 @@
#include "dra76x.dtsi"
#include "dra7-evm-common.dtsi"
+#include "dra76x-mmc-iodelay.dtsi"
#include <dt-bindings/net/ti-dp83867.h>
/ {
@@ -100,46 +101,6 @@
};
};
-&dra7_pmx_core {
- mmc1_pins_default: mmc1_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x376c, PIN_INPUT | MUX_MODE14) /* mmc1sdcd.gpio219 */
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc1_pins_sdr12: pinmux_mmc1_sdr12_pins {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
- DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
- DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
- DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
- DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
- DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
- >;
- };
-
- mmc2_pins_default: mmc2_pins_default {
- pinctrl-single,pins = <
- DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
- DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
- DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
- DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
- DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
- DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
- DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
- DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
- DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
- DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
- >;
- };
-};
-
&i2c1 {
status = "okay";
clock-frequency = <400000>;
--
2.11.0
^ permalink raw reply related
* [PATCH 04/14] ARM: dts: dra76x: Create a common file with MMC/SD IOdelay data
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
From: Sekhar Nori <nsekhar@ti.com>
Add a common device-tree include file with MMC/SD IOdelay data
for DRA76x SoC.
In the most common case, IOdelay data available in datamanual
can directly be used. This file caters to that common case.
Data is based on DRA76x datamanual, SPRS993A, revised July 2017.
Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 435 ++++++++++++++++++++++++++++++
1 file changed, 435 insertions(+)
create mode 100644 arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
diff --git a/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
new file mode 100644
index 000000000000..67aa3e4d671d
--- /dev/null
+++ b/arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
@@ -0,0 +1,435 @@
+/*
+ * MMC IOdelay values for TI's DRA76x and AM576x SoCs.
+ *
+ * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Rules for modifying this file:
+ * a) Update of this file should typically correspond to a datamanual revision.
+ * Datamanual revision that was used should be updated in comment below.
+ * If there is no update to datamanual, do not update the values. If you
+ * need to use values different from that recommended by the datamanual
+ * for your design, then you should consider adding values to the device-
+ * -tree file for your board directly.
+ * b) We keep the mode names as close to the datamanual as possible. So
+ * if the manual calls a mode, DDR50, or DDR or DDR 1.8v or DDR 3.3v,
+ * we follow that in code too.
+ * c) If the values change between multiple revisions of silicon, we add
+ * a revision tag to both the new and old entry. Use 'rev11' for PG 1.1,
+ * 'rev20' for PG 2.0 and so on.
+ * d) The node name and node label should be the exact same string. This is
+ * to curb naming creativity and achieve consistency.
+ *
+ * Datamanual Revisions:
+ *
+ * DRA76x Silicon Revision 1.0: SPRS993A, Revised July 2017
+ *
+ */
+
+&dra7_pmx_core {
+ mmc1_pins_default: mmc1_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr12: mmc1_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_hs: mmc1_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr25: mmc1_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE11 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr50: mmc1_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_VIRTUAL_MODE10 | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_ddr50: mmc1_pins_ddr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc1_pins_sdr104: mmc1_pins_sdr104 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_clk.clk */
+ DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_cmd.cmd */
+ DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat0.dat0 */
+ DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat1.dat1 */
+ DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat2.dat2 */
+ DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0) /* mmc1_dat3.dat3 */
+ >;
+ };
+
+ mmc2_pins_default: mmc2_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs: mmc2_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_ddr: mmc2_pins_ddr {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc2_pins_hs200: mmc2_pins_hs200 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a23.mmc2_clk */
+ DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_cs1.mmc2_cmd */
+ DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a24.mmc2_dat0 */
+ DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a25.mmc2_dat1 */
+ DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a26.mmc2_dat2 */
+ DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a27.mmc2_dat3 */
+ DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a19.mmc2_dat4 */
+ DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a20.mmc2_dat5 */
+ DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a21.mmc2_dat6 */
+ DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1) /* gpmc_a22.mmc2_dat7 */
+ >;
+ };
+
+ mmc3_pins_default: mmc3_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_hs: mmc3_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr12: mmc3_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr25: mmc3_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc3_pins_sdr50: mmc3_pins_sdr50 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x377c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_clk.mmc3_clk */
+ DRA7XX_CORE_IOPAD(0x3780, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_cmd.mmc3_cmd */
+ DRA7XX_CORE_IOPAD(0x3784, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat0.mmc3_dat0 */
+ DRA7XX_CORE_IOPAD(0x3788, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat1.mmc3_dat1 */
+ DRA7XX_CORE_IOPAD(0x378c, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat2.mmc3_dat2 */
+ DRA7XX_CORE_IOPAD(0x3790, (PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE0)) /* mmc3_dat3.mmc3_dat3 */
+ >;
+ };
+
+ mmc4_pins_default: mmc4_pins_default {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc4_pins_sdr12: mmc4_pins_sdr12 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc4_pins_hs: mmc4_pins_hs {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+
+ mmc4_pins_sdr25: mmc4_pins_sdr25 {
+ pinctrl-single,pins = <
+ DRA7XX_CORE_IOPAD(0x37e8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_ctsn.mmc4_clk */
+ DRA7XX_CORE_IOPAD(0x37ec, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart1_rtsn.mmc4_cmd */
+ DRA7XX_CORE_IOPAD(0x37f0, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rxd.mmc4_dat0 */
+ DRA7XX_CORE_IOPAD(0x37f4, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_txd.mmc4_dat1 */
+ DRA7XX_CORE_IOPAD(0x37f8, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_ctsn.mmc4_dat2 */
+ DRA7XX_CORE_IOPAD(0x37fc, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE3) /* uart2_rtsn.mmc4_dat3 */
+ >;
+ };
+};
+
+&dra7_iodelay_core {
+
+ /* Corresponds to MMC1_DDR_MANUAL1 in datamanual */
+ mmc1_iodelay_ddr_conf: mmc1_iodelay_ddr_conf {
+ pinctrl-pin-array = <
+ 0x618 A_DELAY_PS(489) G_DELAY_PS(0) /* CFG_MMC1_CLK_IN */
+ 0x624 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_IN */
+ 0x630 A_DELAY_PS(374) G_DELAY_PS(0) /* CFG_MMC1_DAT0_IN */
+ 0x63c A_DELAY_PS(31) G_DELAY_PS(0) /* CFG_MMC1_DAT1_IN */
+ 0x648 A_DELAY_PS(56) G_DELAY_PS(0) /* CFG_MMC1_DAT2_IN */
+ 0x654 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_IN */
+ 0x620 A_DELAY_PS(1355) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(4) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC1_SDR104_MANUAL1 in datamanual */
+ mmc1_iodelay_sdr104_conf: mmc1_iodelay_sdr104_conf {
+ pinctrl-pin-array = <
+ 0x620 A_DELAY_PS(892) G_DELAY_PS(0) /* CFG_MMC1_CLK_OUT */
+ 0x628 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OEN */
+ 0x62c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_CMD_OUT */
+ 0x634 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OEN */
+ 0x638 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT0_OUT */
+ 0x640 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OEN */
+ 0x644 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT1_OUT */
+ 0x64c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OEN */
+ 0x650 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT2_OUT */
+ 0x658 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OEN */
+ 0x65c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC1_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC2_HS200_MANUAL1 in datamanual */
+ mmc2_iodelay_hs200_conf: mmc2_iodelay_hs200_conf {
+ pinctrl-pin-array = <
+ 0x190 A_DELAY_PS(384) G_DELAY_PS(0) /* CFG_GPMC_A19_OEN */
+ 0x194 A_DELAY_PS(0) G_DELAY_PS(174) /* CFG_GPMC_A19_OUT */
+ 0x1a8 A_DELAY_PS(410) G_DELAY_PS(0) /* CFG_GPMC_A20_OEN */
+ 0x1ac A_DELAY_PS(85) G_DELAY_PS(0) /* CFG_GPMC_A20_OUT */
+ 0x1b4 A_DELAY_PS(468) G_DELAY_PS(0) /* CFG_GPMC_A21_OEN */
+ 0x1b8 A_DELAY_PS(139) G_DELAY_PS(0) /* CFG_GPMC_A21_OUT */
+ 0x1c0 A_DELAY_PS(676) G_DELAY_PS(0) /* CFG_GPMC_A22_OEN */
+ 0x1c4 A_DELAY_PS(69) G_DELAY_PS(0) /* CFG_GPMC_A22_OUT */
+ 0x1d0 A_DELAY_PS(1062) G_DELAY_PS(154) /* CFG_GPMC_A23_OUT */
+ 0x1d8 A_DELAY_PS(640) G_DELAY_PS(0) /* CFG_GPMC_A24_OEN */
+ 0x1dc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A24_OUT */
+ 0x1e4 A_DELAY_PS(356) G_DELAY_PS(0) /* CFG_GPMC_A25_OEN */
+ 0x1e8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A25_OUT */
+ 0x1f0 A_DELAY_PS(579) G_DELAY_PS(0) /* CFG_GPMC_A26_OEN */
+ 0x1f4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_GPMC_A26_OUT */
+ 0x1fc A_DELAY_PS(435) G_DELAY_PS(0) /* CFG_GPMC_A27_OEN */
+ 0x200 A_DELAY_PS(36) G_DELAY_PS(0) /* CFG_GPMC_A27_OUT */
+ 0x364 A_DELAY_PS(759) G_DELAY_PS(0) /* CFG_GPMC_CS1_OEN */
+ 0x368 A_DELAY_PS(72) G_DELAY_PS(0) /* CFG_GPMC_CS1_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL1 in datamanual */
+ mmc3_iodelay_manual1_conf: mmc3_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(0) G_DELAY_PS(386) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(605) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(171) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(221) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(474) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC3_MANUAL2 in datamanual */
+ mmc3_iodelay_sdr50_conf: mmc3_iodelay_sdr50_conf {
+ pinctrl-pin-array = <
+ 0x678 A_DELAY_PS(852) G_DELAY_PS(0) /* CFG_MMC3_CLK_IN */
+ 0x680 A_DELAY_PS(94) G_DELAY_PS(0) /* CFG_MMC3_CLK_OUT */
+ 0x684 A_DELAY_PS(122) G_DELAY_PS(0) /* CFG_MMC3_CMD_IN */
+ 0x688 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OEN */
+ 0x68c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_CMD_OUT */
+ 0x690 A_DELAY_PS(91) G_DELAY_PS(0) /* CFG_MMC3_DAT0_IN */
+ 0x694 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OEN */
+ 0x698 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT0_OUT */
+ 0x69c A_DELAY_PS(57) G_DELAY_PS(0) /* CFG_MMC3_DAT1_IN */
+ 0x6a0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OEN */
+ 0x6a4 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT1_OUT */
+ 0x6a8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_IN */
+ 0x6ac A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OEN */
+ 0x6b0 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT2_OUT */
+ 0x6b4 A_DELAY_PS(375) G_DELAY_PS(0) /* CFG_MMC3_DAT3_IN */
+ 0x6b8 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OEN */
+ 0x6bc A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_MMC3_DAT3_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_MANUAL1 in datamanual */
+ mmc4_iodelay_manual1_conf: mmc4_iodelay_manual1_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(1147) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(1834) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(2165) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(1929) G_DELAY_PS(64) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(1935) G_DELAY_PS(128) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(2172) G_DELAY_PS(44) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+
+ /* Corresponds to MMC4_DS_MANUAL1 in datamanual */
+ mmc4_iodelay_default_conf: mmc4_iodelay_default_conf {
+ pinctrl-pin-array = <
+ 0x840 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_IN */
+ 0x848 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_CTSN_OUT */
+ 0x84c A_DELAY_PS(307) G_DELAY_PS(0) /* CFG_UART1_RTSN_IN */
+ 0x850 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OEN */
+ 0x854 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART1_RTSN_OUT */
+ 0x870 A_DELAY_PS(785) G_DELAY_PS(0) /* CFG_UART2_CTSN_IN */
+ 0x874 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OEN */
+ 0x878 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_CTSN_OUT */
+ 0x87c A_DELAY_PS(613) G_DELAY_PS(0) /* CFG_UART2_RTSN_IN */
+ 0x880 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OEN */
+ 0x884 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RTSN_OUT */
+ 0x888 A_DELAY_PS(683) G_DELAY_PS(0) /* CFG_UART2_RXD_IN */
+ 0x88c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OEN */
+ 0x890 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_RXD_OUT */
+ 0x894 A_DELAY_PS(835) G_DELAY_PS(0) /* CFG_UART2_TXD_IN */
+ 0x898 A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OEN */
+ 0x89c A_DELAY_PS(0) G_DELAY_PS(0) /* CFG_UART2_TXD_OUT */
+ >;
+ };
+};
--
2.11.0
^ permalink raw reply related
* [PATCH 03/14] ARM: configs: keystone: Enable CONFIG_MMC_SDHCI_OMAP
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Enable CONFIG_MMC_SDHCI_OMAP so that TI's k2g SoC
can use sdhci-omap driver for MMC/SD controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/configs/keystone_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig
index f710c192b33a..264260a9b1be 100644
--- a/arch/arm/configs/keystone_defconfig
+++ b/arch/arm/configs/keystone_defconfig
@@ -170,7 +170,10 @@ CONFIG_USB_DWC3=y
CONFIG_NOP_USB_XCEIV=y
CONFIG_KEYSTONE_USB_PHY=y
CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
2.11.0
^ permalink raw reply related
* [PATCH 02/14] ARM: omap2plus_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Enable CONFIG_MMC_SDHCI_OMAP so that TI's dra7 based SoC's
can use sdhci-omap driver for eMMC/SD/SDIO controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/configs/omap2plus_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index 7b97200c1d64..c70a00e1ff6a 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -423,8 +423,11 @@ CONFIG_USB_ZERO=m
CONFIG_USB_G_NOKIA=m
CONFIG_MMC=y
CONFIG_SDIO_UART=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_OMAP=y
CONFIG_MMC_OMAP_HS=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_CPCAP=m
--
2.11.0
^ permalink raw reply related
* [PATCH 01/14] ARM: multi_v7_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214134054.7749-1-kishon@ti.com>
Enable CONFIG_MMC_SDHCI_OMAP so that TI's dra7/k2g based SoC's
can use sdhci-omap for eMMC/SD/SDIO controller..
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 61509c4b769f..c8761731aaee 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -741,6 +741,7 @@ CONFIG_MMC_DW_ROCKCHIP=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_MMC_SUNXI=y
CONFIG_MMC_BCM2835=y
+CONFIG_MMC_SDHCI_OMAP=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_CLASS_FLASH=m
--
2.11.0
^ permalink raw reply related
* [PATCH 00/14] ARM: dra7/k2g: Use sdhci-omap for MMC/SD controller
From: Kishon Vijay Abraham I @ 2017-12-14 13:40 UTC (permalink / raw)
To: linux-arm-kernel
This series enables sdhci-omap driver in omap2plus_defconfig/
keystone_defconfig/multi_v7_defconfig and also modifies the dts
file to use sdhci-omap. Switching to sdhci-omap is required to
support high speed modes like UHS and HS200.
This series should be merged only after [1]
[1] -> https://lkml.org/lkml/2017/12/14/269
The sdhci-omap patches and the dt patches are also pushed to
https://github.com/kishon/linux-wip.git sdhci_omap_uhs
Kishon Vijay Abraham I (10):
ARM: multi_v7_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
ARM: omap2plus_defconfig: Enable CONFIG_MMC_SDHCI_OMAP
ARM: configs: keystone: Enable CONFIG_MMC_SDHCI_OMAP
ARM: dts: am57xx-beagle-x15: Add "vqmmc-supply" property for mmc2
ARM: dts: am57xx-idk: Add "vqmmc-supply" property for mmc2
ARM: dts: dra76-evm: Add "vqmmc-supply" property for mmc2
ARM: dts: dra71-evm: Select pull down for mmc1_clk line in default
mode
ARM: dts: am57xx-idk: Select pull down for mmc1_clk line in default
mode
ARM: dts: dra7: Use sdhci-omap programming model
ARM: dts: keystone-k2g: Use sdhci-omap programming model
Ravikumar Kattekola (1):
ARM: dts: dra71-evm: Correct evm_sd regulator max voltage
Sekhar Nori (3):
ARM: dts: dra76x: Create a common file with MMC/SD IOdelay data
ARM: dts: dra76-evm: Shift to using common IOdelay data
ARM: dts: dra76-evm: Add pinctrl data for higher speed MMC/SD modes
arch/arm/boot/dts/am571x-idk.dts | 2 +-
arch/arm/boot/dts/am572x-idk.dts | 2 +-
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 4 +-
arch/arm/boot/dts/am57xx-idk-common.dtsi | 14 +-
arch/arm/boot/dts/dra7-evm.dts | 1 +
arch/arm/boot/dts/dra7.dtsi | 25 +-
arch/arm/boot/dts/dra71-evm.dts | 17 +-
arch/arm/boot/dts/dra72-evm-common.dtsi | 2 +-
arch/arm/boot/dts/dra76-evm.dts | 53 +--
arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi | 435 ++++++++++++++++++++++++
arch/arm/boot/dts/keystone-k2g.dtsi | 13 +-
arch/arm/configs/keystone_defconfig | 3 +
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm/configs/omap2plus_defconfig | 3 +
14 files changed, 505 insertions(+), 70 deletions(-)
create mode 100644 arch/arm/boot/dts/dra76x-mmc-iodelay.dtsi
--
2.11.0
^ permalink raw reply
* [PATCH v2 08/19] arm64: KVM: Dynamically patch the kernel/hyp VA mask
From: Marc Zyngier @ 2017-12-14 13:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5A3279E8.2070507@arm.com>
On 14/12/17 13:17, James Morse wrote:
> Hi Marc,
>
> On 11/12/17 14:49, Marc Zyngier wrote:
>> So far, we're using a complicated sequence of alternatives to
>> patch the kernel/hyp VA mask on non-VHE, and NOP out the
>> masking altogether when on VHE.
>>
>> THe newly introduced dynamic patching gives us the opportunity
>> to simplify that code by patching a single instruction with
>> the correct mask (instead of the mind bending cummulative masking
>> we have at the moment) or even a single NOP on VHE.
>
> (and just a single NOP on VHE?)
Yes, much better. Thanks.
>
>
>> diff --git a/arch/arm64/kvm/haslr.c b/arch/arm64/kvm/haslr.c
>> new file mode 100644
>> index 000000000000..5e1643a4e7bf
>> --- /dev/null
>> +++ b/arch/arm64/kvm/haslr.c
>
>> +u32 __init kvm_update_va_mask(struct alt_instr *alt, int index, u32 oinsn)
>> +{
>> + u32 rd, rn, insn;
>> + u64 imm;
>> +
>> + /* We only expect a 1 instruction sequence */
>> + BUG_ON((alt->alt_len / sizeof(insn)) != 1);
>> +
>> + /* VHE doesn't need any address translation, let's NOP everything */
>> + if (has_vhe())
>> + return aarch64_insn_gen_nop();
>> +
>> + rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
>> + rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
>> +
>> + switch (index) {
>> + default:
>> + /* Something went wrong... */
>> + insn = AARCH64_BREAK_FAULT;
>> + break;
>
> Can this happen? You bug-on alt->alt_len != 1-instruction above, and the loop in
> __apply_alternatives() is calculated in the same way.
> If it can, BUG_ON(index != 0) should catch both cases in one go.
No, it cannot happen. Yes, I'm paranoid. I guess I should just
initialise insn to AARCH64_BREAK_FAULT and achieve the same level of
paranoia without that default clause.
Oh, and it keeps GCC quiet.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v2 08/19] arm64: KVM: Dynamically patch the kernel/hyp VA mask
From: James Morse @ 2017-12-14 13:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171211144937.4537-9-marc.zyngier@arm.com>
Hi Marc,
On 11/12/17 14:49, Marc Zyngier wrote:
> So far, we're using a complicated sequence of alternatives to
> patch the kernel/hyp VA mask on non-VHE, and NOP out the
> masking altogether when on VHE.
>
> THe newly introduced dynamic patching gives us the opportunity
> to simplify that code by patching a single instruction with
> the correct mask (instead of the mind bending cummulative masking
> we have at the moment) or even a single NOP on VHE.
(and just a single NOP on VHE?)
> diff --git a/arch/arm64/kvm/haslr.c b/arch/arm64/kvm/haslr.c
> new file mode 100644
> index 000000000000..5e1643a4e7bf
> --- /dev/null
> +++ b/arch/arm64/kvm/haslr.c
> +u32 __init kvm_update_va_mask(struct alt_instr *alt, int index, u32 oinsn)
> +{
> + u32 rd, rn, insn;
> + u64 imm;
> +
> + /* We only expect a 1 instruction sequence */
> + BUG_ON((alt->alt_len / sizeof(insn)) != 1);
> +
> + /* VHE doesn't need any address translation, let's NOP everything */
> + if (has_vhe())
> + return aarch64_insn_gen_nop();
> +
> + rd = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RD, oinsn);
> + rn = aarch64_insn_decode_register(AARCH64_INSN_REGTYPE_RN, oinsn);
> +
> + switch (index) {
> + default:
> + /* Something went wrong... */
> + insn = AARCH64_BREAK_FAULT;
> + break;
Can this happen? You bug-on alt->alt_len != 1-instruction above, and the loop in
__apply_alternatives() is calculated in the same way.
If it can, BUG_ON(index != 0) should catch both cases in one go.
> + case 0:
> + imm = get_hyp_va_mask();
> + insn = aarch64_insn_gen_logical_immediate(AARCH64_INSN_LOGIC_AND,
> + AARCH64_INSN_VARIANT_64BIT,
> + rn, rd, imm);
> + break;
> + }
> +
> + BUG_ON(insn == AARCH64_BREAK_FAULT);
> +
> + return insn;
> +}
>
Thanks,
James
^ permalink raw reply
* [PATCH v3 07/11] thermal: armada: Update Kconfig and module description
From: Thomas Petazzoni @ 2017-12-14 13:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87efnxo8cf.fsf@free-electrons.com>
Hello,
On Thu, 14 Dec 2017 12:30:08 +0100, Gregory CLEMENT wrote:
> Unfortunately Armada SoCs is more that just these SoC!
>
> Have a look on Documentation/arm/Marvell/README to see how the Marvell
> marketing guys had been creative :)
>
> Some kirkwood are called Armada 300 and Armada 310.
> The Dove is also called Armada 510.
> Some PXA are called Armada too such as Armada 168 or Armada 610.
> And finally the Berlin also use Aramda as code name: Armada 1000 or
> Aramda 1500
However: "Marvell EBU Armada" should be distinctive enough.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] KVM: arm/arm64: don't set vtimer->cnt_ctl in kvm_arch_timer_handler
From: Christoffer Dall @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <dc95b58c-ee6c-e5c7-1f37-8f69c789a1fc@gmail.com>
On Thu, Dec 14, 2017 at 12:57:54PM +0800, Jia He wrote:
Hi Jia,
>
> I have tried your newer level-mapped-v7 branch, but bug is still there.
>
> There is no special load in both host and guest. The guest (kernel
> 4.14) is often hanging when booting
>
> the guest kernel log
>
> [ OK ] Reached target Remote File Systems.
> Starting File System Check on /dev/mapper/fedora-root...
> [ OK ] Started File System Check on /dev/mapper/fedora-root.
> Mounting /sysroot...
> [ 2.670764] SGI XFS with ACLs, security attributes, no debug enabled
> [ 2.678180] XFS (dm-0): Mounting V5 Filesystem
> [ 2.740364] XFS (dm-0): Ending clean mount
> [ OK ] Mounted /sysroot.
> [ OK ] Reached target Initrd Root File System.
> Starting Reload Configuration from the Real Root...
> [ 61.288215] INFO: rcu_sched detected stalls on CPUs/tasks:
> [ 61.290791] 1-...!: (0 ticks this GP) idle=574/0/0 softirq=5/5 fqs=1
> [ 61.293664] (detected by 0, t=6002 jiffies, g=-263, c=-264, q=39760)
> [ 61.296480] Task dump for CPU 1:
> [ 61.297938] swapper/1 R running task 0 0 1 0x00000020
> [ 61.300643] Call trace:
> [ 61.301260] __switch_to+0x6c/0x78
> [ 61.302095] cpu_number+0x0/0x8
> [ 61.302867] rcu_sched kthread starved for 6000 jiffies!
> g18446744073709551353 c18446744073709551352 f0x0 RCU_GP_WAIT_FQS(3)
> ->state=0x402 ->cpu=1
> [ 61.305941] rcu_sched I 0 8 2 0x00000020
> [ 61.307250] Call trace:
> [ 61.307854] __switch_to+0x6c/0x78
> [ 61.308693] __schedule+0x268/0x8f0
> [ 61.309545] schedule+0x2c/0x88
> [ 61.310325] schedule_timeout+0x84/0x3b8
> [ 61.311278] rcu_gp_kthread+0x4d4/0x7d8
> [ 61.312213] kthread+0x134/0x138
> [ 61.313001] ret_from_fork+0x10/0x1c
>
> Maybe my previous patch is not perfect enough, thanks for your comments.
>
> I digged it futher more, do you think below code logic is possibly
> problematic?
>
>
> vtimer_save_state?????????? (vtimer->loaded = false, cntv_ctl is 0)
>
> kvm_arch_timer_handler????????(read cntv_ctl and set vtimer->cnt_ctl = 0)
>
> vtimer_restore_state ? ? ? ? ?? (write vtimer->cnt_ctl to cntv_ctl,
> then cntv_ctl will
>
> ??? ??? ??? ??? ?? ? ? be 0 forever)
>
>
> If above analysis is reasonable
Yes, I think there's something there if the hardware doesn't retire the
signal fast enough...
> how about below patch? already
> tested in my arm64 server.
>
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index f9555b1..ee6dd3f 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -99,7 +99,7 @@ static irqreturn_t kvm_arch_timer_handler(int irq,
> void *dev_id)
> ??????? }
> ??????? vtimer = vcpu_vtimer(vcpu);
>
> -?????? if (!vtimer->irq.level) {
> +?????? if (vtimer->loaded && !vtimer->irq.level) {
> ??????????????? vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl);
> ??????????????? if (kvm_timer_irq_can_fire(vtimer))
> ??????????????????????? kvm_timer_update_irq(vcpu, true, vtimer);
>
There's nothing really wrong with that patch, I just didn't think it
would be necessary, as we really shouldn't see interrupts if the timer
is not loaded. Can you confirm that a WARN_ON(!vtimer->loaded) in
kvm_arch_timer_handler() gives you a splat?
Also, could you give the following a try (without your patch):
diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
index 73d262c4712b..4751255345d1 100644
--- a/virt/kvm/arm/arch_timer.c
+++ b/virt/kvm/arm/arch_timer.c
@@ -367,6 +367,7 @@ static void vtimer_save_state(struct kvm_vcpu *vcpu)
/* Disable the virtual timer */
write_sysreg_el0(0, cntv_ctl);
+ isb();
vtimer->loaded = false;
out:
Thanks,
-Christoffer
^ permalink raw reply related
* [PATCH 12/12] ARM: OMAP2+: Use sdhci-omap specific pdata-quirks for MMC/SD on DRA74x EVM
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Use sdhci-omap specific pdata-quirks for MMC/SD on DRA74x EVM since
UHS modes are supported only in sdhci-omap (and not in omap-hsmmc).
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
arch/arm/mach-omap2/pdata-quirks.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm/mach-omap2/pdata-quirks.c b/arch/arm/mach-omap2/pdata-quirks.c
index 6b433fce65a5..92fb8828d57f 100644
--- a/arch/arm/mach-omap2/pdata-quirks.c
+++ b/arch/arm/mach-omap2/pdata-quirks.c
@@ -21,7 +21,7 @@
#include <linux/regulator/fixed.h>
#include <linux/platform_data/pinctrl-single.h>
-#include <linux/platform_data/hsmmc-omap.h>
+#include <linux/platform_data/sdhci-omap.h>
#include <linux/platform_data/iommu-omap.h>
#include <linux/platform_data/wkup_m3.h>
#include <linux/platform_data/pwm_omap_dmtimer.h>
@@ -38,7 +38,7 @@
#include "soc.h"
#include "hsmmc.h"
-static struct omap_hsmmc_platform_data __maybe_unused mmc_pdata[2];
+static struct sdhci_omap_platform_data __maybe_unused mmc_pdata[2];
struct pdata_init {
const char *compatible;
@@ -435,21 +435,21 @@ static void __init omap5_uevm_legacy_init(void)
#endif
#ifdef CONFIG_SOC_DRA7XX
-static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc1;
-static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc2;
-static struct omap_hsmmc_platform_data dra7_hsmmc_data_mmc3;
+static struct sdhci_omap_platform_data dra7_sdhci_data_mmc1;
+static struct sdhci_omap_platform_data dra7_sdhci_data_mmc2;
+static struct sdhci_omap_platform_data dra7_sdhci_data_mmc3;
static void __init dra7x_evm_mmc_quirk(void)
{
if (omap_rev() == DRA752_REV_ES1_1 || omap_rev() == DRA752_REV_ES1_0) {
- dra7_hsmmc_data_mmc1.version = "rev11";
- dra7_hsmmc_data_mmc1.max_freq = 96000000;
+ dra7_sdhci_data_mmc1.version = "rev11";
+ dra7_sdhci_data_mmc1.max_freq = 96000000;
- dra7_hsmmc_data_mmc2.version = "rev11";
- dra7_hsmmc_data_mmc2.max_freq = 48000000;
+ dra7_sdhci_data_mmc2.version = "rev11";
+ dra7_sdhci_data_mmc2.max_freq = 48000000;
- dra7_hsmmc_data_mmc3.version = "rev11";
- dra7_hsmmc_data_mmc3.max_freq = 48000000;
+ dra7_sdhci_data_mmc3.version = "rev11";
+ dra7_sdhci_data_mmc3.max_freq = 48000000;
}
}
#endif
@@ -582,12 +582,12 @@ static struct of_dev_auxdata omap_auxdata_lookup[] __initdata = {
&omap4_iommu_pdata),
#endif
#ifdef CONFIG_SOC_DRA7XX
- OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x4809c000, "4809c000.mmc",
- &dra7_hsmmc_data_mmc1),
- OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480b4000, "480b4000.mmc",
- &dra7_hsmmc_data_mmc2),
- OF_DEV_AUXDATA("ti,dra7-hsmmc", 0x480ad000, "480ad000.mmc",
- &dra7_hsmmc_data_mmc3),
+ OF_DEV_AUXDATA("ti,dra7-sdhci", 0x4809c000, "4809c000.mmc",
+ &dra7_sdhci_data_mmc1),
+ OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480b4000, "480b4000.mmc",
+ &dra7_sdhci_data_mmc2),
+ OF_DEV_AUXDATA("ti,dra7-sdhci", 0x480ad000, "480ad000.mmc",
+ &dra7_sdhci_data_mmc3),
#endif
/* Common auxdata */
OF_DEV_AUXDATA("pinctrl-single", 0, NULL, &pcs_pdata),
--
2.11.0
^ permalink raw reply related
* [PATCH 11/12] mmc: sdhci-omap: Add support for MMC/SD controller in k2g SoC
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Add support for the new compatible added specifically to support
k2g's MMC/SD controller.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index cddc3ad1331f..5e81e29383d9 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -767,6 +767,10 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
.ops = &sdhci_omap_ops,
};
+static const struct sdhci_omap_data k2g_data = {
+ .offset = 0x200,
+};
+
static const struct sdhci_omap_data dra7_data = {
.offset = 0x200,
.flags = SDHCI_OMAP_REQUIRE_IODELAY,
@@ -774,6 +778,7 @@ static const struct sdhci_omap_data dra7_data = {
static const struct of_device_id omap_sdhci_match[] = {
{ .compatible = "ti,dra7-sdhci", .data = &dra7_data },
+ { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
{},
};
MODULE_DEVICE_TABLE(of, omap_sdhci_match);
@@ -882,6 +887,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
int ret;
u32 offset;
struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
struct sdhci_host *host;
struct sdhci_pltfm_host *pltfm_host;
struct sdhci_omap_host *omap_host;
@@ -908,6 +914,9 @@ static int sdhci_omap_probe(struct platform_device *pdev)
return PTR_ERR(host);
}
+ if (of_device_is_compatible(node, "ti,k2g-sdhci"))
+ host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
+
pltfm_host = sdhci_priv(host);
omap_host = sdhci_pltfm_priv(pltfm_host);
omap_host->host = host;
--
2.11.0
^ permalink raw reply related
* [PATCH 10/12] dt-bindings: sdhci-omap: Add K2G specific binding
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Add binding for the TI's sdhci-omap controller present in K2G.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
Documentation/devicetree/bindings/mmc/sdhci-omap.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt
index 51775a372c06..8d09b837e350 100644
--- a/Documentation/devicetree/bindings/mmc/sdhci-omap.txt
+++ b/Documentation/devicetree/bindings/mmc/sdhci-omap.txt
@@ -4,7 +4,9 @@ Refer to mmc.txt for standard MMC bindings.
Required properties:
- compatible: Should be "ti,dra7-sdhci" for DRA7 and DRA72 controllers
+ Should be "ti,k2g-sdhci" for K2G
- ti,hwmods: Must be "mmc<n>", <n> is controller instance starting 1
+ (Not required for K2G).
Example:
mmc1: mmc at 4809c000 {
--
2.11.0
^ permalink raw reply related
* [RFC PATCH 09/12] mmc: sdhci: Use software timer when timeout greater than hardware capablility
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Errata i834 in AM572x Sitara Processors Silicon Revision 2.0, 1.1
(SPRZ429K July 2014?Revised March 2017 [1]) mentions
Under high speed HS200 and SDR104 modes, the functional clock for MMC
modules will reach up to 192 MHz. At this frequency, the maximum obtainable
timeout (DTO = 0xE) through MMC host controller is (1/192MHz)*2^27 = 700ms.
Commands taking longer than 700ms may be affected by this small window
frame. Workaround for this errata is use a software timer instead of
hardware timer to provide the delay requested by the upper layer.
While this errata is specific to AM572x, it is applicable to all sdhci
based controllers when a particular request require timeout greater
than hardware capability.
Re-use the software timer already implemented in sdhci to program the
correct timeout value and also disable the hardware timeout when
the required timeout is greater than hardware capabiltiy in order to
avoid spurious timeout interrupts.
This patch is based on the earlier patch implemented for omap_hsmmc [2]
[1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf
[2] -> https://patchwork.kernel.org/patch/9791449/
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci.c | 41 +++++++++++++++++++++++++++++++++++++++--
drivers/mmc/host/sdhci.h | 11 +++++++++++
2 files changed, 50 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index e9290a3439d5..d0655e1d2cc7 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -673,6 +673,27 @@ static void sdhci_adma_table_post(struct sdhci_host *host,
}
}
+static void sdhci_calc_sw_timeout(struct sdhci_host *host,
+ struct mmc_command *cmd,
+ unsigned int target_timeout)
+{
+ struct mmc_host *mmc = host->mmc;
+ struct mmc_ios *ios = &mmc->ios;
+ struct mmc_data *data = cmd->data;
+ unsigned long long transfer_time;
+
+ if (data) {
+ transfer_time = MMC_BLOCK_TRANSFER_TIME_MS(data->blksz,
+ ios->bus_width,
+ ios->clock);
+ /* calculate timeout for the entire data */
+ host->data_timeout = (data->blocks * (target_timeout +
+ transfer_time));
+ } else if (cmd->flags & MMC_RSP_BUSY) {
+ host->data_timeout = cmd->busy_timeout * MSEC_PER_SEC;
+ }
+}
+
static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 count;
@@ -732,8 +753,12 @@ static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
}
if (count >= 0xF) {
- DBG("Too large timeout 0x%x requested for CMD%d!\n",
- count, cmd->opcode);
+ DBG("Too large timeout.. using SW timeout for CMD%d!\n",
+ cmd->opcode);
+ sdhci_calc_sw_timeout(host, cmd, target_timeout);
+ host->ier &= ~SDHCI_INT_DATA_TIMEOUT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
count = 0xE;
}
@@ -1198,6 +1223,14 @@ static void sdhci_finish_command(struct sdhci_host *host)
{
struct mmc_command *cmd = host->cmd;
+ if (host->data_timeout) {
+ unsigned long timeout;
+
+ timeout = jiffies +
+ msecs_to_jiffies(host->data_timeout);
+ sdhci_mod_timer(host, host->cmd->mrq, timeout);
+ }
+
host->cmd = NULL;
if (cmd->flags & MMC_RSP_PRESENT) {
@@ -2341,6 +2374,10 @@ static bool sdhci_request_done(struct sdhci_host *host)
return true;
}
+ host->data_timeout = 0;
+ host->ier |= SDHCI_INT_DATA_TIMEOUT;
+ sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
+ sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
sdhci_del_timer(host, mrq);
/*
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 54bc444c317f..e6e0278bea1a 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -332,6 +332,15 @@ struct sdhci_adma2_64_desc {
/* Allow for a a command request and a data request at the same time */
#define SDHCI_MAX_MRQS 2
+/*
+ * Time taken for transferring one block. It is multiplied by a constant
+ * factor '2' to account for any errors
+ */
+#define MMC_BLOCK_TRANSFER_TIME_MS(blksz, bus_width, freq) \
+ ((unsigned long long) \
+ (2 * (((blksz) * MSEC_PER_SEC * \
+ (8 / (bus_width))) / (freq))))
+
enum sdhci_cookie {
COOKIE_UNMAPPED,
COOKIE_PRE_MAPPED, /* mapped by sdhci_pre_req() */
@@ -546,6 +555,8 @@ struct sdhci_host {
/* Host SDMA buffer boundary. */
u32 sdma_boundary;
+ unsigned long long data_timeout;
+
unsigned long private[0] ____cacheline_aligned;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 08/12] mmc: sdhci-omap: Add support to override f_max and iodelay from pdata
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
DRA74x EVM Rev H EVM comes with revision 2.0 silicon. However, earlier
versions of EVM can come with either revision 1.1 or revision 1.0 of
silicon.
The device-tree file is written to support rev 2.0 of silicon.
pdata-quirks are used to then override the settings needed for
PG 1.1 silicon.
PG 1.1 silicon has limitations w.r.t frequencies at which MMC1/2/3
can operate as well as different IOdelay numbers.
Add support in sdhci-omap driver to get platform data if available
(added using pdata quirks) and override the data (max-frequency and
iodelay data) obtained from device tree.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 17 ++++++++++++++++
include/linux/platform_data/sdhci-omap.h | 35 ++++++++++++++++++++++++++++++++
2 files changed, 52 insertions(+)
create mode 100644 include/linux/platform_data/sdhci-omap.h
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 6dee275b2e57..cddc3ad1331f 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -22,6 +22,7 @@
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_device.h>
+#include <linux/platform_data/sdhci-omap.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/regulator/consumer.h>
@@ -102,6 +103,7 @@ struct sdhci_omap_data {
};
struct sdhci_omap_host {
+ char *version;
void __iomem *base;
struct device *dev;
struct regulator *pbias;
@@ -781,11 +783,18 @@ static struct pinctrl_state
u32 *caps, u32 capmask)
{
struct device *dev = omap_host->dev;
+ char *version = omap_host->version;
struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
+ char str[20];
if (!(*caps & capmask))
goto ret;
+ if (version) {
+ sprintf(str, "%s-%s", mode, version);
+ pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
+ }
+
pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
if (IS_ERR(pinctrl_state)) {
dev_err(dev, "no pinctrl state for %s mode", mode);
@@ -879,6 +888,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
struct mmc_host *mmc;
const struct of_device_id *match;
struct sdhci_omap_data *data;
+ struct sdhci_omap_platform_data *platform_data;
match = of_match_device(omap_sdhci_match, dev);
if (!match)
@@ -913,6 +923,13 @@ static int sdhci_omap_probe(struct platform_device *pdev)
if (ret)
goto err_pltfm_free;
+ platform_data = dev_get_platdata(dev);
+ if (platform_data) {
+ omap_host->version = platform_data->version;
+ if (platform_data->max_freq)
+ mmc->f_max = platform_data->max_freq;
+ }
+
pltfm_host->clk = devm_clk_get(dev, "fck");
if (IS_ERR(pltfm_host->clk)) {
ret = PTR_ERR(pltfm_host->clk);
diff --git a/include/linux/platform_data/sdhci-omap.h b/include/linux/platform_data/sdhci-omap.h
new file mode 100644
index 000000000000..a46e1240956a
--- /dev/null
+++ b/include/linux/platform_data/sdhci-omap.h
@@ -0,0 +1,35 @@
+/**
+ * SDHCI Controller Platform Data for TI's OMAP SoCs
+ *
+ * Copyright (C) 2017 Texas Instruments
+ * Author: Kishon Vijay Abraham I <kishon@ti.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 of
+ * the License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __SDHCI_OMAP_PDATA_H__
+#define __SDHCI_OMAP_PDATA_H__
+
+struct sdhci_omap_platform_data {
+ const char *name;
+
+ /*
+ * set if your board has components or wiring that limits the
+ * maximum frequency on the MMC bus
+ */
+ unsigned int max_freq;
+
+ /* string specifying a particular variant of hardware */
+ char *version;
+};
+
+#endif
--
2.11.0
^ permalink raw reply related
* [PATCH 07/12] mmc: sdhci_omap: Fix sdhci-omap quirks
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
Remove SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk as gpio card detection
is supported in sdhci-omap.
Add SDHCI_QUIRK2_PRESET_VALUE_BROKEN quirk as setting preset values loads
incorrect CLKD values (for UHS modes).
Remove SDHCI_QUIRK2_NO_1_8_V quirk as sdhci-omap now supports UHS modes.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index 594e41200d8a..6dee275b2e57 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -755,13 +755,12 @@ static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
}
static const struct sdhci_pltfm_data sdhci_omap_pdata = {
- .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
- SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
+ .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
SDHCI_QUIRK_NO_HISPD_BIT |
SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
- .quirks2 = SDHCI_QUIRK2_NO_1_8_V |
- SDHCI_QUIRK2_ACMD23_BROKEN |
+ .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
+ SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
SDHCI_QUIRK2_RSP_136_HAS_CRC,
.ops = &sdhci_omap_ops,
};
--
2.11.0
^ permalink raw reply related
* [PATCH 06/12] mmc: sdhci_omap: Add support to set IODELAY values
From: Kishon Vijay Abraham I @ 2017-12-14 13:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-1-kishon@ti.com>
The data manual of J6/J6 Eco recommends to set different IODELAY values
depending on the mode in which the MMC/SD is enumerated in order to
ensure IO timings are met.
Add support to set the IODELAY values depending on the various MMC
modes using the pinctrl APIs.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/mmc/host/sdhci-omap.c | 174 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 174 insertions(+)
diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
index b20f4c79ccc6..594e41200d8a 100644
--- a/drivers/mmc/host/sdhci-omap.c
+++ b/drivers/mmc/host/sdhci-omap.c
@@ -93,8 +93,12 @@
#define MAX_PHASE_DELAY 0x7C
+/* sdhci-omap controller flags */
+#define SDHCI_OMAP_REQUIRE_IODELAY BIT(0)
+
struct sdhci_omap_data {
u32 offset;
+ u8 flags;
};
struct sdhci_omap_host {
@@ -105,6 +109,20 @@ struct sdhci_omap_host {
struct sdhci_host *host;
u8 bus_mode;
u8 power_mode;
+ u8 timing;
+ u8 flags;
+
+ struct pinctrl *pinctrl;
+ struct pinctrl_state *pinctrl_state;
+ struct pinctrl_state *default_pinctrl_state;
+ struct pinctrl_state *sdr104_pinctrl_state;
+ struct pinctrl_state *hs200_1_8v_pinctrl_state;
+ struct pinctrl_state *ddr50_pinctrl_state;
+ struct pinctrl_state *sdr50_pinctrl_state;
+ struct pinctrl_state *sdr25_pinctrl_state;
+ struct pinctrl_state *sdr12_pinctrl_state;
+ struct pinctrl_state *hs_pinctrl_state;
+ struct pinctrl_state *ddr_1_8v_pinctrl_state;
};
static void sdhci_omap_start_clock(struct sdhci_omap_host *omap_host);
@@ -449,6 +467,62 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
return 0;
}
+static void sdhci_omap_set_timing(struct sdhci_omap_host *omap_host, u8 timing)
+{
+ int ret;
+ struct pinctrl_state *pinctrl_state;
+ struct device *dev = omap_host->dev;
+
+ if (omap_host->timing == timing)
+ return;
+
+ sdhci_omap_stop_clock(omap_host);
+
+ switch (timing) {
+ case MMC_TIMING_UHS_SDR104:
+ pinctrl_state = omap_host->sdr104_pinctrl_state;
+ break;
+ case MMC_TIMING_MMC_HS200:
+ pinctrl_state = omap_host->hs200_1_8v_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ pinctrl_state = omap_host->ddr50_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ pinctrl_state = omap_host->sdr50_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_SDR25:
+ pinctrl_state = omap_host->sdr25_pinctrl_state;
+ break;
+ case MMC_TIMING_UHS_SDR12:
+ pinctrl_state = omap_host->sdr12_pinctrl_state;
+ break;
+ case MMC_TIMING_SD_HS:
+ case MMC_TIMING_MMC_HS:
+ pinctrl_state = omap_host->hs_pinctrl_state;
+ break;
+ case MMC_TIMING_MMC_DDR52:
+ pinctrl_state = omap_host->ddr_1_8v_pinctrl_state;
+ break;
+ default:
+ pinctrl_state = omap_host->default_pinctrl_state;
+ break;
+ }
+
+ if (omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY) {
+ ret = pinctrl_select_state(omap_host->pinctrl, pinctrl_state);
+ if (ret) {
+ dev_err(dev, "failed to select pinctrl state\n");
+ goto ret;
+ }
+ omap_host->pinctrl_state = pinctrl_state;
+ }
+
+ret:
+ sdhci_omap_start_clock(omap_host);
+ omap_host->timing = timing;
+}
+
static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
u8 power_mode)
{
@@ -485,6 +559,7 @@ static void sdhci_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
omap_host = sdhci_pltfm_priv(pltfm_host);
sdhci_omap_set_bus_mode(omap_host, ios->bus_mode);
+ sdhci_omap_set_timing(omap_host, ios->timing);
sdhci_set_ios(mmc, ios);
sdhci_omap_set_power_mode(omap_host, ios->power_mode);
}
@@ -693,6 +768,7 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
static const struct sdhci_omap_data dra7_data = {
.offset = 0x200,
+ .flags = SDHCI_OMAP_REQUIRE_IODELAY,
};
static const struct of_device_id omap_sdhci_match[] = {
@@ -701,6 +777,98 @@ static const struct of_device_id omap_sdhci_match[] = {
};
MODULE_DEVICE_TABLE(of, omap_sdhci_match);
+static struct pinctrl_state
+*sdhci_omap_iodelay_pinctrl_state(struct sdhci_omap_host *omap_host, char *mode,
+ u32 *caps, u32 capmask)
+{
+ struct device *dev = omap_host->dev;
+ struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
+
+ if (!(*caps & capmask))
+ goto ret;
+
+ pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
+ if (IS_ERR(pinctrl_state)) {
+ dev_err(dev, "no pinctrl state for %s mode", mode);
+ *caps &= ~capmask;
+ }
+
+ret:
+ return pinctrl_state;
+}
+
+static int sdhci_omap_config_iodelay_pinctrl_state(struct sdhci_omap_host
+ *omap_host)
+{
+ struct device *dev = omap_host->dev;
+ struct sdhci_host *host = omap_host->host;
+ struct mmc_host *mmc = host->mmc;
+ u32 *caps = &mmc->caps;
+ u32 *caps2 = &mmc->caps2;
+ struct pinctrl_state *state;
+
+ if (!(omap_host->flags & SDHCI_OMAP_REQUIRE_IODELAY))
+ return 0;
+
+ omap_host->pinctrl = devm_pinctrl_get(omap_host->dev);
+ if (IS_ERR(omap_host->pinctrl)) {
+ dev_err(dev, "Cannot get pinctrl\n");
+ return PTR_ERR(omap_host->pinctrl);
+ }
+
+ state = pinctrl_lookup_state(omap_host->pinctrl, "default");
+ if (IS_ERR(state)) {
+ dev_err(dev, "no pinctrl state for default mode\n");
+ return PTR_ERR(state);
+ }
+ omap_host->default_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr104", caps,
+ MMC_CAP_UHS_SDR104);
+ if (!IS_ERR(state))
+ omap_host->sdr104_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr50", caps,
+ MMC_CAP_UHS_DDR50);
+ if (!IS_ERR(state))
+ omap_host->ddr50_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr50", caps,
+ MMC_CAP_UHS_SDR50);
+ if (!IS_ERR(state))
+ omap_host->sdr50_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr25", caps,
+ MMC_CAP_UHS_SDR25);
+ if (!IS_ERR(state))
+ omap_host->sdr25_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "sdr12", caps,
+ MMC_CAP_UHS_SDR12);
+ if (!IS_ERR(state))
+ omap_host->sdr12_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "ddr_1_8v", caps,
+ MMC_CAP_1_8V_DDR);
+ if (!IS_ERR(state))
+ omap_host->ddr_1_8v_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs", caps,
+ MMC_CAP_MMC_HIGHSPEED |
+ MMC_CAP_SD_HIGHSPEED);
+ if (!IS_ERR(state))
+ omap_host->hs_pinctrl_state = state;
+
+ state = sdhci_omap_iodelay_pinctrl_state(omap_host, "hs200_1_8v", caps2,
+ MMC_CAP2_HS200_1_8V_SDR);
+ if (!IS_ERR(state))
+ omap_host->hs200_1_8v_pinctrl_state = state;
+
+ omap_host->pinctrl_state = omap_host->default_pinctrl_state;
+
+ return 0;
+}
+
static int sdhci_omap_probe(struct platform_device *pdev)
{
int ret;
@@ -737,6 +905,8 @@ static int sdhci_omap_probe(struct platform_device *pdev)
omap_host->base = host->ioaddr;
omap_host->dev = dev;
omap_host->power_mode = MMC_POWER_UNDEFINED;
+ omap_host->timing = MMC_TIMING_LEGACY;
+ omap_host->flags = data->flags;
host->ioaddr += offset;
mmc = host->mmc;
@@ -785,6 +955,10 @@ static int sdhci_omap_probe(struct platform_device *pdev)
goto err_put_sync;
}
+ ret = sdhci_omap_config_iodelay_pinctrl_state(omap_host);
+ if (ret)
+ goto err_put_sync;
+
host->mmc_host_ops.get_ro = mmc_gpio_get_ro;
host->mmc_host_ops.start_signal_voltage_switch =
sdhci_omap_start_signal_voltage_switch;
--
2.11.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox