* [PATCH] KVM: arm/arm64: don't set vtimer->cnt_ctl in kvm_arch_timer_handler
From: Christoffer Dall @ 2017-12-15 11:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <83d52c86-0c09-0a18-34e3-55eb213f8083@arm.com>
On Fri, Dec 15, 2017 at 10:33:48AM +0000, Marc Zyngier wrote:
> On 15/12/17 10:10, Christoffer Dall wrote:
> > On Fri, Dec 15, 2017 at 09:09:05AM +0000, Marc Zyngier wrote:
> >> On 15/12/17 02:27, Jia He wrote:
> >>>
> >>>
> >>
> >> [...]
> >>
> >>>> @@ -367,6 +368,7 @@ static void vtimer_save_state(struct kvm_vcpu *vcpu)
> >>>>
> >>>> /* Disable the virtual timer */
> >>>> write_sysreg_el0(0, cntv_ctl);
> >>>> + isb();
> >>> My only concern is whether this isb() is required here?
> >>> Sorryif this is a stupid question.I understand little about arm arch
> >>> memory barrier. But seems isb will flush all the instruction prefetch.Do
> >>> you think if an timer interrupt irq arrives, arm will use the previous
> >>> instruction prefetch?
> >>
> >>
> >> This barrier has little to do with prefetch. It just guarantees that the
> >> code after the isb() is now running with a disabled virtual timer.
> >> Otherwise, a CPU can freely reorder the write_sysreg() until the next
> >> context synchronization event.
> >>
> >> An interrupt coming between the write and the barrier will also act as a
> >> context synchronization event. For more details, see the ARMv8 ARM (the
> >> glossary has a section on the concept).
> >>
> >
> > So since an ISB doesn't guarantee that the timer will actually be
> > disabled, is it a waste of energy to have it, or should we keep it as a
> > best effort kind of thing?
>
> nit: the ISB does offer that guarantee. It is just that the guarantee
> doesn't extend to an interrupt that has already been signalled.
right, I should have said that it doesn't guarantee that an already
signalled interrupt will have been retired prior to enabling interrupts
on the CPU again.
>
> The main issue I have with not having an ISB is that it makes it harder
> to think of when the disabling actually happens. The disabling could be
> delayed for a very long time, and would make things harder to debug if
> they were going wrong.
>
Yes, it definitely indicates the intention of the code and the flow, and
the fact that we have to work around delayed signals in the ISR is then
something we can describe with a comment there.
I'll add an ISB in the other version of the patch I sent before.
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH v2 1/3] media: V3s: Add support for Allwinner CSI.
From: Yong @ 2017-12-15 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215105047.ist7epuida2uao74@flea.lan>
Hi Maxime,
On Fri, 15 Dec 2017 11:50:47 +0100
Maxime Ripard <maxime.ripard@free-electrons.com> wrote:
> Hi Yong,
>
> On Mon, Dec 04, 2017 at 05:45:11PM +0800, Yong wrote:
> > I just noticed that you are using the second iteration?
> > Have you received my third iteration?
>
> Sorry for the late reply, and for not coming back to you yet about
> that test. No, this is still in your v2. I've definitely received your
> v3, I just didn't have time to update to it yet.
>
> But don't worry, my mail was mostly to know if you had tested that
> setup on your side to try to nail down the issue on my end, not really
> a review or comment that would prevent your patch from going in.
I mean,
The v2 exactly has a bug which may cause the CSI writing frame to
a wrong memory address.
BTW, should I send a new version. I have made some improve sine v3.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
Thanks,
Yong
^ permalink raw reply
* [PATCH v3 5/5] arm64: dts: rockchip: add reset property for dwc3 controllers on rk3399.
From: Enric Balletbo i Serra @ 2017-12-15 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215110005.7564-1-enric.balletbo@collabora.com>
After commit '06c47e6286d usb: dwc3: of-simple: Add support to get resets
for the device' you can add the reset property to the dwc3 node, the reset
is required for the controller to work properly, otherwise bind / unbind
stress testing of the USB controller on rk3399 we'd often end up with lots
of failures that looked like this:
phy phy-ff800000.phy.9: phy poweron failed --> -110
dwc3 fe900000.dwc3: failed to initialize core
dwc3: probe of fe900000.dwc3 failed with error -110
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes since v1:
- This patch did not exists in the series.
Changes since v2:
- Introduced this patch
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index c18ff88..83f0f71 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -402,6 +402,8 @@
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "aclk_usb3_rksoc_axi_perf",
"aclk_usb3", "grf_clk";
+ resets = <&cru SRST_A_USB3_OTG0>;
+ reset-names = "usb3-otg";
status = "disabled";
usbdrd_dwc3_0: dwc3 {
@@ -433,6 +435,8 @@
clock-names = "ref_clk", "suspend_clk",
"bus_clk", "aclk_usb3_rksoc_axi_perf",
"aclk_usb3", "grf_clk";
+ resets = <&cru SRST_A_USB3_OTG1>;
+ reset-names = "usb3-otg";
status = "disabled";
usbdrd_dwc3_1: dwc3 {
--
2.9.3
^ permalink raw reply related
* [PATCH v3 4/5] arm64: dts: rockchip: add pd_usb3 power-domain node for rk3399.
From: Enric Balletbo i Serra @ 2017-12-15 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215110005.7564-1-enric.balletbo@collabora.com>
Add the usb3 power-domain, its qos area and assign it to the usb device
node.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes since v1:
- Split the original patch in different commits
Changes since v2:
- None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index ea91f25..c18ff88 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -417,6 +417,7 @@
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
+ power-domains = <&power RK3399_PD_USB3>;
status = "disabled";
};
};
@@ -447,6 +448,7 @@
snps,dis_u2_susphy_quirk;
snps,dis-del-phy-power-chg-quirk;
snps,dis-tx-ipgap-linecheck-quirk;
+ power-domains = <&power RK3399_PD_USB3>;
status = "disabled";
};
};
@@ -995,6 +997,12 @@
clocks = <&cru HCLK_SDIO>;
pm_qos = <&qos_sdioaudio>;
};
+ pd_usb3 at RK3399_PD_USB3 {
+ reg = <RK3399_PD_USB3>;
+ clocks = <&cru ACLK_USB3>;
+ pm_qos = <&qos_usb_otg0>,
+ <&qos_usb_otg1>;
+ };
pd_vio at RK3399_PD_VIO {
reg = <RK3399_PD_VIO>;
#address-cells = <1>;
--
2.9.3
^ permalink raw reply related
* [PATCH v3 3/5] arm64: dts: rockchip: add usb3-phy otg-port support for rk3399.
From: Enric Balletbo i Serra @ 2017-12-15 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215110005.7564-1-enric.balletbo@collabora.com>
Add the usb3 phyter for the USB3.0 OTG controller.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes since v1:
- Split the original patch in different commits
Changes since v2:
- None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index f32e9c4..ea91f25 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -409,8 +409,8 @@
reg = <0x0 0xfe800000 0x0 0x100000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy0_otg>;
- phy-names = "usb2-phy";
+ phys = <&u2phy0_otg>, <&tcphy0_usb3>;
+ phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
@@ -439,8 +439,8 @@
reg = <0x0 0xfe900000 0x0 0x100000>;
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
dr_mode = "otg";
- phys = <&u2phy1_otg>;
- phy-names = "usb2-phy";
+ phys = <&u2phy1_otg>, <&tcphy1_usb3>;
+ phy-names = "usb2-phy", "usb3-phy";
phy_type = "utmi_wide";
snps,dis_enblslpm_quirk;
snps,dis-u2-freeclk-exists-quirk;
--
2.9.3
^ permalink raw reply related
* [PATCH v3 2/5] arm64: dts: rockchip: add the aclk_usb3 clocks for USB3.
From: Enric Balletbo i Serra @ 2017-12-15 11:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215110005.7564-1-enric.balletbo@collabora.com>
The aclk_usb3 must be enabled to support USB3 for rk3399.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
Changes since v1:
- Split the original patch in different commits
Changes since v2:
- None
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index 17e5e1a..f32e9c4 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -397,9 +397,11 @@
#size-cells = <2>;
ranges;
clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
- <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
+ <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "grf_clk";
+ "bus_clk", "aclk_usb3_rksoc_axi_perf",
+ "aclk_usb3", "grf_clk";
status = "disabled";
usbdrd_dwc3_0: dwc3 {
@@ -425,9 +427,11 @@
#size-cells = <2>;
ranges;
clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
- <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_GRF>;
+ <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
+ <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
clock-names = "ref_clk", "suspend_clk",
- "bus_clk", "grf_clk";
+ "bus_clk", "aclk_usb3_rksoc_axi_perf",
+ "aclk_usb3", "grf_clk";
status = "disabled";
usbdrd_dwc3_1: dwc3 {
--
2.9.3
^ permalink raw reply related
* [PATCH v3 1/5] arm64: dts: rockchip: add extcon nodes and enable tcphy.
From: Enric Balletbo i Serra @ 2017-12-15 11:00 UTC (permalink / raw)
To: linux-arm-kernel
Enable tcphy and create the cros-ec's extcon node for the USB Type-C port.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
---
Changes since v1:
- Add the Reviewed-by: Brian Norris
Changes since v2:
- None
arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
index 470105d..03f1950 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi
@@ -855,6 +855,20 @@ ap_i2c_audio: &i2c8 {
compatible = "google,cros-ec-pwm";
#pwm-cells = <1>;
};
+
+ usbc_extcon0: extcon at 0 {
+ compatible = "google,extcon-usbc-cros-ec";
+ google,usb-port-id = <0>;
+
+ #extcon-cells = <0>;
+ };
+
+ usbc_extcon1: extcon at 1 {
+ compatible = "google,extcon-usbc-cros-ec";
+ google,usb-port-id = <1>;
+
+ #extcon-cells = <0>;
+ };
};
};
@@ -865,6 +879,16 @@ ap_i2c_audio: &i2c8 {
rockchip,hw-tshut-polarity = <1>; /* tshut polarity 0:LOW 1:HIGH */
};
+&tcphy0 {
+ status = "okay";
+ extcon = <&usbc_extcon0>;
+};
+
+&tcphy1 {
+ status = "okay";
+ extcon = <&usbc_extcon1>;
+};
+
&u2phy0 {
status = "okay";
};
@@ -911,6 +935,7 @@ ap_i2c_audio: &i2c8 {
&usbdrd3_0 {
status = "okay";
+ extcon = <&usbc_extcon0>;
};
&usbdrd_dwc3_0 {
@@ -920,6 +945,7 @@ ap_i2c_audio: &i2c8 {
&usbdrd3_1 {
status = "okay";
+ extcon = <&usbc_extcon1>;
};
&usbdrd_dwc3_1 {
--
2.9.3
^ permalink raw reply related
* [PATCH v3 03/11] thermal: armada: Simplify the check of the validity bit
From: Miquel RAYNAL @ 2017-12-15 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215083316.4xswddwbcijxhuxn@tarshish>
Hello Baruch,
On Fri, 15 Dec 2017 10:33:16 +0200
Baruch Siach <baruch@tkos.co.il> wrote:
> Hi Miquel,
>
> On Thu, Dec 14, 2017 at 11:30:03AM +0100, Miquel Raynal wrote:
> > All Armada SoCs use one bit to declare if the sensor values are
> > valid. This bit moves across the versions of the IP.
> >
> > The method until then was to do both a shift and compare with an
> > useless flag of "0x1". It is clearer and quicker to directly save
> > the value that must be ANDed instead of the bit position and do a
> > single bitwise AND operation.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
> > ---
> > drivers/thermal/armada_thermal.c | 12 +++++-------
> > 1 file changed, 5 insertions(+), 7 deletions(-)
> >
> > diff --git a/drivers/thermal/armada_thermal.c
> > b/drivers/thermal/armada_thermal.c index 6c4af2622d4f..26698f2d3ca7
> > 100644 --- a/drivers/thermal/armada_thermal.c
> > +++ b/drivers/thermal/armada_thermal.c
> > @@ -24,8 +24,6 @@
> > #include <linux/of_device.h>
> > #include <linux/thermal.h>
> >
> > -#define THERMAL_VALID_MASK 0x1
> > -
> > /* Thermal Manager Control and Status Register */
> > #define PMU_TDC0_SW_RST_MASK (0x1 << 1)
> > #define PMU_TM_DISABLE_OFFS 0
> > @@ -67,7 +65,7 @@ struct armada_thermal_data {
> > /* Register shift and mask to access the sensor
> > temperature */ unsigned int temp_shift;
> > unsigned int temp_mask;
> > - unsigned int is_valid_shift;
> > + unsigned int is_valid_bit;
>
> Type should be u32 now, I think.
Indeed, I'll change it in next version.
>
> > };
> >
> > static void armadaxp_init_sensor(struct platform_device *pdev,
> > @@ -151,7 +149,7 @@ static bool armada_is_valid(struct
> > armada_thermal_priv *priv) {
> > unsigned long reg = readl_relaxed(priv->sensor);
>
> u32 here also, I think. But that's unrelated to this patch.
I completely agree, actually this is done in the next patch, moving all
"unsigned long reg" to "u32 reg" while renaming the registers
pointers, hope this is fine?
>
> > - return (reg >> priv->data->is_valid_shift) &
> > THERMAL_VALID_MASK;
> > + return reg & priv->data->is_valid_bit;
> > }
> >
> > static int armada_get_temp(struct thermal_zone_device *thermal,
> > @@ -199,7 +197,7 @@ static const struct armada_thermal_data
> > armadaxp_data = { static const struct armada_thermal_data
> > armada370_data = { .is_valid = armada_is_valid,
> > .init_sensor = armada370_init_sensor,
> > - .is_valid_shift = 9,
> > + .is_valid_bit = BIT(9),
> > .temp_shift = 10,
> > .temp_mask = 0x1ff,
> > .coef_b = 3153000000UL,
> > @@ -210,7 +208,7 @@ static const struct armada_thermal_data
> > armada370_data = { static const struct armada_thermal_data
> > armada375_data = { .is_valid = armada_is_valid,
> > .init_sensor = armada375_init_sensor,
> > - .is_valid_shift = 10,
> > + .is_valid_bit = BIT(10),
> > .temp_shift = 0,
> > .temp_mask = 0x1ff,
> > .coef_b = 3171900000UL,
> > @@ -221,7 +219,7 @@ static const struct armada_thermal_data
> > armada375_data = { static const struct armada_thermal_data
> > armada380_data = { .is_valid = armada_is_valid,
> > .init_sensor = armada380_init_sensor,
> > - .is_valid_shift = 10,
> > + .is_valid_bit = BIT(10),
> > .temp_shift = 0,
> > .temp_mask = 0x3ff,
> > .coef_b = 1172499100UL,
>
> baruch
>
Best regards,
Miqu?l
^ permalink raw reply
* [PATCH 3/4] ARM: pxa/spitz: Remove hardcoded partitioning, use sharpslpart parser
From: Pavel Machek @ 2017-12-15 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87efoi6pg4.fsf@belgarion.home>
On Tue 2017-11-28 22:52:43, Robert Jarzmik wrote:
> Andrea Adami <andrea.adami@gmail.com> writes:
>
> > On Thu, Nov 23, 2017 at 12:06 AM, Pavel Machek <pavel@ucw.cz> wrote:
> >> On Tue 2017-11-21 22:43:50, Andrea Adami wrote:
>
> Pavel, given that you didn't challenge Andrea's statement, I assume QEMU users
> will switch to mtdparts again.
>
> I'll apply the serie to pxa/for-next.
Well, I believe it is bad idea, but whatever. I still have zaurus, but
don't use it any more.
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
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* [PATCH v1] mfd: ab8500: introduce DEFINE_SHOW_ATTRIBUTE() macro
From: Lee Jones @ 2017-12-15 10:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214105121.77015-1-andriy.shevchenko@linux.intel.com>
Linus,
> This macro deduplicates a lot of similar code in the ab8500-debugfs.c module.
> Targeting to be moved to seq_file.h eventually.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> ---
> drivers/mfd/ab8500-debugfs.c | 406 +++++++------------------------------------
> 1 file changed, 62 insertions(+), 344 deletions(-)
>
> diff --git a/drivers/mfd/ab8500-debugfs.c b/drivers/mfd/ab8500-debugfs.c
> index 7eaa3493a828..f66c458228ec 100644
> --- a/drivers/mfd/ab8500-debugfs.c
> +++ b/drivers/mfd/ab8500-debugfs.c
> @@ -1258,6 +1258,19 @@ static struct ab8500_prcmu_ranges ab8540_debug_ranges[AB8500_NUM_BANKS] = {
> },
> };
>
> +#define DEFINE_SHOW_ATTRIBUTE(__name) \
> +static int __name ## _open(struct inode *inode, struct file *file) \
> +{ \
> + return single_open(file, __name ## _show, inode->i_private); \
> +} \
> + \
> +static const struct file_operations __name ## _fops = { \
> + .owner = THIS_MODULE, \
> + .open = __name ## _open, \
> + .read = seq_read, \
> + .llseek = seq_lseek, \
> + .release = single_release, \
> +} \
>
> static irqreturn_t ab8500_debug_handler(int irq, void *data)
> {
> @@ -1318,7 +1331,7 @@ static int ab8500_registers_print(struct device *dev, u32 bank,
> return 0;
> }
>
> -static int ab8500_print_bank_registers(struct seq_file *s, void *p)
> +static int ab8500_bank_registers_show(struct seq_file *s, void *p)
> {
> struct device *dev = s->private;
> u32 bank = debug_bank;
> @@ -1330,18 +1343,7 @@ static int ab8500_print_bank_registers(struct seq_file *s, void *p)
> return ab8500_registers_print(dev, bank, s);
> }
>
> -static int ab8500_registers_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_print_bank_registers, inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_registers_fops = {
> - .open = ab8500_registers_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_bank_registers);
>
> static int ab8500_print_all_banks(struct seq_file *s, void *p)
> {
> @@ -1528,7 +1530,7 @@ void ab8500_debug_register_interrupt(int line)
> num_interrupts[line]++;
> }
>
> -static int ab8500_interrupts_print(struct seq_file *s, void *p)
> +static int ab8500_interrupts_show(struct seq_file *s, void *p)
> {
> int line;
>
> @@ -1557,10 +1559,7 @@ static int ab8500_interrupts_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_interrupts_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_interrupts_print, inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_interrupts);
>
> /*
> * - HWREG DB8500 formated routines
> @@ -1603,7 +1602,7 @@ static int ab8500_hwreg_open(struct inode *inode, struct file *file)
> #define AB8500_LAST_SIM_REG 0x8B
> #define AB8505_LAST_SIM_REG 0x8C
>
> -static int ab8500_print_modem_registers(struct seq_file *s, void *p)
> +static int ab8500_modem_show(struct seq_file *s, void *p)
> {
> struct device *dev = s->private;
> struct ab8500 *ab8500;
> @@ -1659,21 +1658,9 @@ static int ab8500_print_modem_registers(struct seq_file *s, void *p)
> return err;
> }
>
> -static int ab8500_modem_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_print_modem_registers,
> - inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_modem_fops = {
> - .open = ab8500_modem_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_modem);
>
> -static int ab8500_gpadc_bat_ctrl_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_bat_ctrl_show(struct seq_file *s, void *p)
> {
> int bat_ctrl_raw;
> int bat_ctrl_convert;
> @@ -1690,21 +1677,9 @@ static int ab8500_gpadc_bat_ctrl_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_bat_ctrl_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_bat_ctrl_print,
> - inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_gpadc_bat_ctrl_fops = {
> - .open = ab8500_gpadc_bat_ctrl_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_bat_ctrl);
>
> -static int ab8500_gpadc_btemp_ball_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_btemp_ball_show(struct seq_file *s, void *p)
> {
> int btemp_ball_raw;
> int btemp_ball_convert;
> @@ -1721,22 +1696,9 @@ static int ab8500_gpadc_btemp_ball_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_btemp_ball_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_btemp_ball_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_btemp_ball);
>
> -static const struct file_operations ab8500_gpadc_btemp_ball_fops = {
> - .open = ab8500_gpadc_btemp_ball_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8500_gpadc_main_charger_v_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_main_charger_v_show(struct seq_file *s, void *p)
> {
> int main_charger_v_raw;
> int main_charger_v_convert;
> @@ -1753,22 +1715,9 @@ static int ab8500_gpadc_main_charger_v_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_main_charger_v_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_main_charger_v_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_main_charger_v);
>
> -static const struct file_operations ab8500_gpadc_main_charger_v_fops = {
> - .open = ab8500_gpadc_main_charger_v_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8500_gpadc_acc_detect1_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_acc_detect1_show(struct seq_file *s, void *p)
> {
> int acc_detect1_raw;
> int acc_detect1_convert;
> @@ -1785,22 +1734,9 @@ static int ab8500_gpadc_acc_detect1_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_acc_detect1_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_acc_detect1_print,
> - inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_gpadc_acc_detect1_fops = {
> - .open = ab8500_gpadc_acc_detect1_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_acc_detect1);
>
> -static int ab8500_gpadc_acc_detect2_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_acc_detect2_show(struct seq_file *s, void *p)
> {
> int acc_detect2_raw;
> int acc_detect2_convert;
> @@ -1817,22 +1753,9 @@ static int ab8500_gpadc_acc_detect2_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_acc_detect2_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_acc_detect2_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_acc_detect2);
>
> -static const struct file_operations ab8500_gpadc_acc_detect2_fops = {
> - .open = ab8500_gpadc_acc_detect2_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8500_gpadc_aux1_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_aux1_show(struct seq_file *s, void *p)
> {
> int aux1_raw;
> int aux1_convert;
> @@ -1849,20 +1772,9 @@ static int ab8500_gpadc_aux1_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_aux1_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_aux1_print, inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_gpadc_aux1_fops = {
> - .open = ab8500_gpadc_aux1_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_aux1);
>
> -static int ab8500_gpadc_aux2_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_aux2_show(struct seq_file *s, void *p)
> {
> int aux2_raw;
> int aux2_convert;
> @@ -1879,20 +1791,9 @@ static int ab8500_gpadc_aux2_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_aux2_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_aux2_print, inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_gpadc_aux2_fops = {
> - .open = ab8500_gpadc_aux2_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_aux2);
>
> -static int ab8500_gpadc_main_bat_v_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_main_bat_v_show(struct seq_file *s, void *p)
> {
> int main_bat_v_raw;
> int main_bat_v_convert;
> @@ -1909,22 +1810,9 @@ static int ab8500_gpadc_main_bat_v_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_main_bat_v_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_main_bat_v_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_main_bat_v);
>
> -static const struct file_operations ab8500_gpadc_main_bat_v_fops = {
> - .open = ab8500_gpadc_main_bat_v_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8500_gpadc_vbus_v_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_vbus_v_show(struct seq_file *s, void *p)
> {
> int vbus_v_raw;
> int vbus_v_convert;
> @@ -1941,20 +1829,9 @@ static int ab8500_gpadc_vbus_v_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_vbus_v_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_vbus_v_print, inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_vbus_v);
>
> -static const struct file_operations ab8500_gpadc_vbus_v_fops = {
> - .open = ab8500_gpadc_vbus_v_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8500_gpadc_main_charger_c_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_main_charger_c_show(struct seq_file *s, void *p)
> {
> int main_charger_c_raw;
> int main_charger_c_convert;
> @@ -1971,22 +1848,9 @@ static int ab8500_gpadc_main_charger_c_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_main_charger_c_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_main_charger_c_print,
> - inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_gpadc_main_charger_c_fops = {
> - .open = ab8500_gpadc_main_charger_c_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_main_charger_c);
>
> -static int ab8500_gpadc_usb_charger_c_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_usb_charger_c_show(struct seq_file *s, void *p)
> {
> int usb_charger_c_raw;
> int usb_charger_c_convert;
> @@ -2003,22 +1867,9 @@ static int ab8500_gpadc_usb_charger_c_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_usb_charger_c_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_usb_charger_c_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_usb_charger_c);
>
> -static const struct file_operations ab8500_gpadc_usb_charger_c_fops = {
> - .open = ab8500_gpadc_usb_charger_c_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8500_gpadc_bk_bat_v_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_bk_bat_v_show(struct seq_file *s, void *p)
> {
> int bk_bat_v_raw;
> int bk_bat_v_convert;
> @@ -2035,21 +1886,9 @@ static int ab8500_gpadc_bk_bat_v_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_bk_bat_v_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_bk_bat_v_print,
> - inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_gpadc_bk_bat_v_fops = {
> - .open = ab8500_gpadc_bk_bat_v_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_bk_bat_v);
>
> -static int ab8500_gpadc_die_temp_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_die_temp_show(struct seq_file *s, void *p)
> {
> int die_temp_raw;
> int die_temp_convert;
> @@ -2066,21 +1905,9 @@ static int ab8500_gpadc_die_temp_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_die_temp_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_die_temp_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_die_temp);
>
> -static const struct file_operations ab8500_gpadc_die_temp_fops = {
> - .open = ab8500_gpadc_die_temp_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8500_gpadc_usb_id_print(struct seq_file *s, void *p)
> +static int ab8500_gpadc_usb_id_show(struct seq_file *s, void *p)
> {
> int usb_id_raw;
> int usb_id_convert;
> @@ -2097,20 +1924,9 @@ static int ab8500_gpadc_usb_id_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8500_gpadc_usb_id_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8500_gpadc_usb_id_print, inode->i_private);
> -}
> -
> -static const struct file_operations ab8500_gpadc_usb_id_fops = {
> - .open = ab8500_gpadc_usb_id_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8500_gpadc_usb_id);
>
> -static int ab8540_gpadc_xtal_temp_print(struct seq_file *s, void *p)
> +static int ab8540_gpadc_xtal_temp_show(struct seq_file *s, void *p)
> {
> int xtal_temp_raw;
> int xtal_temp_convert;
> @@ -2127,21 +1943,9 @@ static int ab8540_gpadc_xtal_temp_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8540_gpadc_xtal_temp_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8540_gpadc_xtal_temp_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8540_gpadc_xtal_temp);
>
> -static const struct file_operations ab8540_gpadc_xtal_temp_fops = {
> - .open = ab8540_gpadc_xtal_temp_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8540_gpadc_vbat_true_meas_print(struct seq_file *s, void *p)
> +static int ab8540_gpadc_vbat_true_meas_show(struct seq_file *s, void *p)
> {
> int vbat_true_meas_raw;
> int vbat_true_meas_convert;
> @@ -2159,22 +1963,9 @@ static int ab8540_gpadc_vbat_true_meas_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8540_gpadc_vbat_true_meas_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8540_gpadc_vbat_true_meas_print,
> - inode->i_private);
> -}
> -
> -static const struct file_operations ab8540_gpadc_vbat_true_meas_fops = {
> - .open = ab8540_gpadc_vbat_true_meas_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8540_gpadc_vbat_true_meas);
>
> -static int ab8540_gpadc_bat_ctrl_and_ibat_print(struct seq_file *s, void *p)
> +static int ab8540_gpadc_bat_ctrl_and_ibat_show(struct seq_file *s, void *p)
> {
> int bat_ctrl_raw;
> int bat_ctrl_convert;
> @@ -2200,22 +1991,9 @@ static int ab8540_gpadc_bat_ctrl_and_ibat_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8540_gpadc_bat_ctrl_and_ibat_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8540_gpadc_bat_ctrl_and_ibat_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8540_gpadc_bat_ctrl_and_ibat);
>
> -static const struct file_operations ab8540_gpadc_bat_ctrl_and_ibat_fops = {
> - .open = ab8540_gpadc_bat_ctrl_and_ibat_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8540_gpadc_vbat_meas_and_ibat_print(struct seq_file *s, void *p)
> +static int ab8540_gpadc_vbat_meas_and_ibat_show(struct seq_file *s, void *p)
> {
> int vbat_meas_raw;
> int vbat_meas_convert;
> @@ -2240,23 +2018,9 @@ static int ab8540_gpadc_vbat_meas_and_ibat_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8540_gpadc_vbat_meas_and_ibat_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8540_gpadc_vbat_meas_and_ibat_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8540_gpadc_vbat_meas_and_ibat);
>
> -static const struct file_operations ab8540_gpadc_vbat_meas_and_ibat_fops = {
> - .open = ab8540_gpadc_vbat_meas_and_ibat_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8540_gpadc_vbat_true_meas_and_ibat_print(struct seq_file *s,
> - void *p)
> +static int ab8540_gpadc_vbat_true_meas_and_ibat_show(struct seq_file *s, void *p)
> {
> int vbat_true_meas_raw;
> int vbat_true_meas_convert;
> @@ -2282,23 +2046,9 @@ static int ab8540_gpadc_vbat_true_meas_and_ibat_print(struct seq_file *s,
> return 0;
> }
>
> -static int ab8540_gpadc_vbat_true_meas_and_ibat_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8540_gpadc_vbat_true_meas_and_ibat_print,
> - inode->i_private);
> -}
> -
> -static const struct file_operations
> -ab8540_gpadc_vbat_true_meas_and_ibat_fops = {
> - .open = ab8540_gpadc_vbat_true_meas_and_ibat_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8540_gpadc_vbat_true_meas_and_ibat);
>
> -static int ab8540_gpadc_bat_temp_and_ibat_print(struct seq_file *s, void *p)
> +static int ab8540_gpadc_bat_temp_and_ibat_show(struct seq_file *s, void *p)
> {
> int bat_temp_raw;
> int bat_temp_convert;
> @@ -2323,22 +2073,9 @@ static int ab8540_gpadc_bat_temp_and_ibat_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8540_gpadc_bat_temp_and_ibat_open(struct inode *inode,
> - struct file *file)
> -{
> - return single_open(file, ab8540_gpadc_bat_temp_and_ibat_print,
> - inode->i_private);
> -}
> +DEFINE_SHOW_ATTRIBUTE(ab8540_gpadc_bat_temp_and_ibat);
>
> -static const struct file_operations ab8540_gpadc_bat_temp_and_ibat_fops = {
> - .open = ab8540_gpadc_bat_temp_and_ibat_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> -static int ab8540_gpadc_otp_cal_print(struct seq_file *s, void *p)
> +static int ab8540_gpadc_otp_calib_show(struct seq_file *s, void *p)
> {
> struct ab8500_gpadc *gpadc;
> u16 vmain_l, vmain_h, btemp_l, btemp_h;
> @@ -2362,18 +2099,7 @@ static int ab8540_gpadc_otp_cal_print(struct seq_file *s, void *p)
> return 0;
> }
>
> -static int ab8540_gpadc_otp_cal_open(struct inode *inode, struct file *file)
> -{
> - return single_open(file, ab8540_gpadc_otp_cal_print, inode->i_private);
> -}
> -
> -static const struct file_operations ab8540_gpadc_otp_calib_fops = {
> - .open = ab8540_gpadc_otp_cal_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> +DEFINE_SHOW_ATTRIBUTE(ab8540_gpadc_otp_calib);
>
> static int ab8500_gpadc_avg_sample_print(struct seq_file *s, void *p)
> {
> @@ -2906,14 +2632,6 @@ static const struct file_operations ab8500_val_fops = {
> .owner = THIS_MODULE,
> };
>
> -static const struct file_operations ab8500_interrupts_fops = {
> - .open = ab8500_interrupts_open,
> - .read = seq_read,
> - .llseek = seq_lseek,
> - .release = single_release,
> - .owner = THIS_MODULE,
> -};
> -
> static const struct file_operations ab8500_subscribe_fops = {
> .open = ab8500_subscribe_unsubscribe_open,
> .write = ab8500_subscribe_write,
> @@ -3000,7 +2718,7 @@ static int ab8500_debug_probe(struct platform_device *plf)
> goto err;
>
> file = debugfs_create_file("all-bank-registers", S_IRUGO, ab8500_dir,
> - &plf->dev, &ab8500_registers_fops);
> + &plf->dev, &ab8500_bank_registers_fops);
> if (!file)
> goto err;
>
--
Lee Jones
Linaro Services Technical Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v3 01/11] dt-bindings: thermal: Describe Armada AP806 and CP110
From: Miquel RAYNAL @ 2017-12-15 10:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87po7gmlcs.fsf@free-electrons.com>
Hello Baruch and Gregory,
On Fri, 15 Dec 2017 09:44:19 +0100
Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi Miquel,
>
> On ven., d?c. 15 2017, Miquel RAYNAL
> <miquel.raynal@free-electrons.com> wrote:
>
> > Hello Baruch,
> >
> > On Fri, 15 Dec 2017 10:27:59 +0200
> > Baruch Siach <baruch@tkos.co.il> wrote:
> >
> >> Hi Miquel
> >>
> >> On Thu, Dec 14, 2017 at 11:30:01AM +0100, Miquel Raynal wrote:
> >> > +- marvell,thermal-zone-name: The name to identify the thermal
> >> > zone
> >> > + within the sysfs, useful when
> >> > multiple
> >> > + thermal zones are registered (AP,
> >> > CPx...).
> >>
> >> I don't think that would be acceptable. DT is about describing the
> >> hardware. sysfs is a Linux implementation detail which is not tied
> >> to any specific hardware. If this is accepted, the property should
> >> be named 'linux,thermal-zone-name'.
> >
> > You are right the sysfs mention should not appear in the
> > description.
Actually, you are right for all of it, this property should not
exist, sorry for my too quick answer.
> >
> > Otherwise for the naming I'm not sure "linux," is a valid prefix in
> > that case.
Thank you both for your explanations, I was also wrong about the prefix.
>
> Actually the choice between linux or marvell make me realize that
> there is something wrong. Having a name associated to a device is
> something pretty usual with the device tree, however it is as the
> class device level, such as clock-names, line-name, or
> regulator-name. So in my opinion if we want to support naming from
> device tree it would be done for all the thermal device not just for
> the Marvell one.
>
> However I don't think we need it. For example for the clocks we
> created the name dynamically using of the base address of the
> register to keep them unique.
I was convinced that dev_name's would be the same but after trying it on
a 8040-DB, using dev_name(&pdev->dev) gives:
f06f808c.thermal
f2400078.thermal
f4400078.thermal
which I found meaningful enough.
I will drop the property and use dev_name instead. I still need your
help to solve one problem though: how to make the distinction between
using "armada_thermal" (the previous name) and dev_name() ? If I don't
it kind of breaks userspace, doesn't it ?
Thank you,
Miqu?l
^ permalink raw reply
* [PATCH v2 1/3] media: V3s: Add support for Allwinner CSI.
From: Maxime Ripard @ 2017-12-15 10:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171204174511.a5be3b521e9a7c7004d32d0d@magewell.com>
Hi Yong,
On Mon, Dec 04, 2017 at 05:45:11PM +0800, Yong wrote:
> I just noticed that you are using the second iteration?
> Have you received my third iteration?
Sorry for the late reply, and for not coming back to you yet about
that test. No, this is still in your v2. I've definitely received your
v3, I just didn't have time to update to it yet.
But don't worry, my mail was mostly to know if you had tested that
setup on your side to try to nail down the issue on my end, not really
a review or comment that would prevent your patch from going in.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH] arm64: defconfig: Select schedutil as default cpufreq governor
From: Viresh Kumar @ 2017-12-15 10:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <af12e002bc165844101830c0eb00e283b536a879.1510813288.git.viresh.kumar@linaro.org>
On 16-11-17, 11:51, Viresh Kumar wrote:
> Currently performance governor is getting selected by default, which is
> surely not a very good choice as its pretty much power hungry.
>
> Select schedutil instead.
>
> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index 34480e9af2e7..9424a7aafdb2 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -93,6 +93,7 @@ CONFIG_HIBERNATION=y
> CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
> CONFIG_ARM_CPUIDLE=y
> CONFIG_CPU_FREQ=y
> +CONFIG_CPU_FREQ_DEFAULT_GOV_SCHEDUTIL=y
> CONFIG_CPUFREQ_DT=y
> CONFIG_ARM_BIG_LITTLE_CPUFREQ=y
> CONFIG_ARM_SCPI_CPUFREQ=y
Ping !!
--
viresh
^ permalink raw reply
* [PATCH 12/12] ARM64: dts: marvell: use reworked NAND controller driver on Armada 8K
From: Gregory CLEMENT @ 2017-12-15 10:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87y3m4l1wi.fsf@free-electrons.com>
Hi,
On ven., d?c. 15 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi Miquel,
>
> On jeu., d?c. 07 2017, Miquel Raynal <miquel.raynal@free-electrons.com> wrote:
>
>> Use the new bindings of the reworked Marvell NAND controller driver.
>> Also adapt the nand controller node organization to distinguish which
>> property is relevant for the controller, and which one is NAND chip
>> specific. Expose the partitions as a subnode of the NAND chip.
>>
>> Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
>> the driver activates the arbiter by default for all boards (either
>> needed or harmless).
>>
>> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
>
> Applied on mvebu/dt64
As for the other paych, I have been said that actually thess changes are
not ready and that we should wait for the driver would me merged first
so I moved it on mvebu/dt64-nand
Gregory
>
> Thanks,
>
> Gregory
>
>> ---
>> arch/arm64/boot/dts/marvell/armada-8040-db.dts | 46 +++++++++++++---------
>> .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 10 ++---
>> 2 files changed, 32 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
>> index b1f6cccc5081..c25ac3fa9aec 100644
>> --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
>> +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
>> @@ -272,27 +272,35 @@
>> * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
>> * MDIO signal of CP1.
>> */
>> -&cps_nand {
>> - num-cs = <1>;
>> +&cps_nand_controller {
>> pinctrl-0 = <&nand_pins>, <&nand_rb>;
>> pinctrl-names = "default";
>> - nand-ecc-strength = <4>;
>> - nand-ecc-step-size = <512>;
>> - marvell,nand-enable-arbiter;
>> - marvell,system-controller = <&cps_syscon0>;
>> - nand-on-flash-bbt;
>> -
>> - partition at 0 {
>> - label = "U-Boot";
>> - reg = <0 0x200000>;
>> - };
>> - partition at 200000 {
>> - label = "Linux";
>> - reg = <0x200000 0xe00000>;
>> - };
>> - partition at 1000000 {
>> - label = "Filesystem";
>> - reg = <0x1000000 0x3f000000>;
>> +
>> + nand at 0 {
>> + reg = <0>;
>> + marvell,rb = <0>;
>> + nand-on-flash-bbt;
>> + nand-ecc-strength = <4>;
>> + nand-ecc-step-size = <512>;
>> +
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + partition at 0 {
>> + label = "U-Boot";
>> + reg = <0 0x200000>;
>> + };
>> + partition at 200000 {
>> + label = "Linux";
>> + reg = <0x200000 0xe00000>;
>> + };
>> + partition at 1000000 {
>> + label = "Filesystem";
>> + reg = <0x1000000 0x3f000000>;
>> + };
>> + };
>> };
>> };
>>
>> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
>> index cb1fb49ccf81..8610163bb1a4 100644
>> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
>> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
>> @@ -310,20 +310,20 @@
>> status = "disabled";
>> };
>>
>> - cps_nand: nand at 720000 {
>> + cps_nand_controller: nand at 720000 {
>> /*
>> * Due to the limiation of the pin available
>> * this controller is only usable on the CPM
>> * for A7K and on the CPS for A8K.
>> */
>> - compatible = "marvell,armada370-nand",
>> - "marvell,armada-8k-nand";
>> + compatible = "marvell,armada-8k-nand-controller",
>> + "marvell,armada370-nand-controller";
>> reg = <0x720000 0x54>;
>> #address-cells = <1>;
>> - #size-cells = <1>;
>> + #size-cells = <0>;
>> interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
>> clocks = <&cps_clk 1 2>;
>> - marvell,system-controller = <&cpm_syscon0>;
>> + marvell,system-controller = <&cps_syscon0>;
>> status = "disabled";
>> };
>>
>> --
>> 2.11.0
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 11/12] ARM64: dts: marvell: use reworked NAND controller driver on Armada 7K
From: Gregory CLEMENT @ 2017-12-15 10:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87374cmghe.fsf@free-electrons.com>
Hi,
On ven., d?c. 15 2017, Gregory CLEMENT <gregory.clement@free-electrons.com> wrote:
> Hi Miquel,
>
> On jeu., d?c. 07 2017, Miquel Raynal <miquel.raynal@free-electrons.com> wrote:
>
>> Use the new bindings of the reworked Marvell NAND controller driver.
>> Also adapt the nand controller node organization to distinguish which
>> property is relevant for the controller, and which one is NAND chip
>> specific. Expose the partitions as a subnode of the NAND chip.
>>
>> Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
>> the driver activates the arbiter by default for all boards (either
>> needed or harmless).
>>
>> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
>
> Applied on mvebu/dt64
Well I have been said that actually thess changes are not ready and that
we should wait for the driver would me merged first so I moved it on
mvebu/dt64-nand
>
> Thanks,
>
> Gregory
>
>> ---
>> arch/arm64/boot/dts/marvell/armada-7040-db.dts | 52 +++++++++++++---------
>> .../boot/dts/marvell/armada-cp110-master.dtsi | 8 ++--
>> 2 files changed, 36 insertions(+), 24 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
>> index 52b5341cb270..758452c10612 100644
>> --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
>> +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
>> @@ -156,36 +156,48 @@
>> };
>> };
>>
>> -&cpm_nand {
>> +&cpm_nand_controller {
>> /*
>> * SPI on CPM and NAND have common pins on this board. We can
>> - * use only one at a time. To enable the NAND (whihch will
>> + * use only one at a time. To enable the NAND (which will
>> * disable the SPI), the "status = "okay";" line have to be
>> * added here.
>> */
>> - num-cs = <1>;
>> pinctrl-0 = <&nand_pins>, <&nand_rb>;
>> pinctrl-names = "default";
>> - nand-ecc-strength = <4>;
>> - nand-ecc-step-size = <512>;
>> - marvell,nand-enable-arbiter;
>> - nand-on-flash-bbt;
>> -
>> - partition at 0 {
>> - label = "U-Boot";
>> - reg = <0 0x200000>;
>> - };
>> - partition at 200000 {
>> - label = "Linux";
>> - reg = <0x200000 0xe00000>;
>> - };
>> - partition at 1000000 {
>> - label = "Filesystem";
>> - reg = <0x1000000 0x3f000000>;
>> +
>> + nand at 0 {
>> + reg = <0>;
>> + label = "pxa3xx_nand-0";
>> + marvell,rb = <0>;
>> + nand-on-flash-bbt;
>> + nand-ecc-strength = <4>;
>> + nand-ecc-step-size = <512>;
>> +
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + partition at 0 {
>> + label = "U-Boot";
>> + reg = <0 0x200000>;
>> + };
>> +
>> + partition at 200000 {
>> + label = "Linux";
>> + reg = <0x200000 0xe00000>;
>> + };
>> +
>> + partition at 1000000 {
>> + label = "Filesystem";
>> + reg = <0x1000000 0x3f000000>;
>> + };
>> +
>> + };
>> };
>> };
>>
>> -
>> &cpm_spi1 {
>> status = "okay";
>>
>> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
>> index e3b64d03fbd8..8a3cff9a7343 100644
>> --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
>> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
>> @@ -309,17 +309,17 @@
>> status = "disabled";
>> };
>>
>> - cpm_nand: nand at 720000 {
>> + cpm_nand_controller: nand at 720000 {
>> /*
>> * Due to the limiation of the pin available
>> * this controller is only usable on the CPM
>> * for A7K and on the CPS for A8K.
>> */
>> - compatible = "marvell,armada-8k-nand",
>> - "marvell,armada370-nand";
>> + compatible = "marvell,armada-8k-nand-controller",
>> + "marvell,armada370-nand-controller";
>> reg = <0x720000 0x54>;
>> #address-cells = <1>;
>> - #size-cells = <1>;
>> + #size-cells = <0>;
>> interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
>> clocks = <&cpm_clk 1 2>;
>> marvell,system-controller = <&cpm_syscon0>;
>> --
>> 2.11.0
>>
>>
>> _______________________________________________
>> linux-arm-kernel mailing list
>> linux-arm-kernel at lists.infradead.org
>> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> Gregory Clement, Free Electrons
> Kernel, drivers, real-time and embedded Linux
> development, consulting, training and support.
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] KVM: arm/arm64: don't set vtimer->cnt_ctl in kvm_arch_timer_handler
From: Marc Zyngier @ 2017-12-15 10:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215101053.GZ910@cbox>
On 15/12/17 10:10, Christoffer Dall wrote:
> On Fri, Dec 15, 2017 at 09:09:05AM +0000, Marc Zyngier wrote:
>> On 15/12/17 02:27, Jia He wrote:
>>>
>>>
>>
>> [...]
>>
>>>> @@ -367,6 +368,7 @@ static void vtimer_save_state(struct kvm_vcpu *vcpu)
>>>>
>>>> /* Disable the virtual timer */
>>>> write_sysreg_el0(0, cntv_ctl);
>>>> + isb();
>>> My only concern is whether this isb() is required here?
>>> Sorryif this is a stupid question.I understand little about arm arch
>>> memory barrier. But seems isb will flush all the instruction prefetch.Do
>>> you think if an timer interrupt irq arrives, arm will use the previous
>>> instruction prefetch?
>>
>>
>> This barrier has little to do with prefetch. It just guarantees that the
>> code after the isb() is now running with a disabled virtual timer.
>> Otherwise, a CPU can freely reorder the write_sysreg() until the next
>> context synchronization event.
>>
>> An interrupt coming between the write and the barrier will also act as a
>> context synchronization event. For more details, see the ARMv8 ARM (the
>> glossary has a section on the concept).
>>
>
> So since an ISB doesn't guarantee that the timer will actually be
> disabled, is it a waste of energy to have it, or should we keep it as a
> best effort kind of thing?
nit: the ISB does offer that guarantee. It is just that the guarantee
doesn't extend to an interrupt that has already been signalled.
The main issue I have with not having an ISB is that it makes it harder
to think of when the disabling actually happens. The disabling could be
delayed for a very long time, and would make things harder to debug if
they were going wrong.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [RFC PATCH 0/5] Introduce PMSAv8 memory protection unit
From: Vladimir Murzin @ 2017-12-15 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0B16DB97-D4E6-4DEE-A03F-FD215475C448@esh.hu>
Hi,
On 15/12/17 10:21, Szemz? Andr?s wrote:
> Hi,
>
>> On 2017. Dec 13., at 18:02, Vladimir Murzin <vladimir.murzin@arm.com> wrote:
>>
>> Hi,
>>
>> This series is an attempt to add support for PMSAv8 MPU defined by
>> ARMv8R/M architecture.
>>
>> I'm have a doubt about adding dedicated config option, so both v7 and
>> v8 versions of PMSA are covered with CONFIG_MPU, but I'd glad to hear
>> what people think of it.
>>
>> Thanks!
>>
>> Vladimir Murzin (5):
>> ARM: NOMMU: Move PMSAv7 MPU under it's own namespace
>> ARM: NOMMU: Reorganise __setup_mpu
>> ARM: NOMMU: Postpone MPU activation till __after_proc_init
>> ARM: NOMMU: Make _stext and _end meet PMSAv8 alignment restrictions
>> ARM: NOMMU: Support PMSAv8 MPU
>>
>
> I?ve tested this series on my Atmel armv7m board, and it doesn?t break anything on my side.
> (My test setup is running kernel from SDRAM, with rootfs on SDcard, so no XIP was tested)
>
> FWIW, you can add my Tested-by for patches 1-4.
Mach appreciated!
Cheers
Vladimir
>
> Thanks!
>
> Regards,
> Andras
>
>
>
>
^ permalink raw reply
* [PATCH 12/12] ARM64: dts: marvell: use reworked NAND controller driver on Armada 8K
From: Gregory CLEMENT @ 2017-12-15 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207201814.30411-13-miquel.raynal@free-electrons.com>
Hi Miquel,
On jeu., d?c. 07 2017, Miquel Raynal <miquel.raynal@free-electrons.com> wrote:
> Use the new bindings of the reworked Marvell NAND controller driver.
> Also adapt the nand controller node organization to distinguish which
> property is relevant for the controller, and which one is NAND chip
> specific. Expose the partitions as a subnode of the NAND chip.
>
> Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
> the driver activates the arbiter by default for all boards (either
> needed or harmless).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-8040-db.dts | 46 +++++++++++++---------
> .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 10 ++---
> 2 files changed, 32 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> index b1f6cccc5081..c25ac3fa9aec 100644
> --- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
> @@ -272,27 +272,35 @@
> * Proper NAND usage will require DPR-76 to be in position 1-2, which disables
> * MDIO signal of CP1.
> */
> -&cps_nand {
> - num-cs = <1>;
> +&cps_nand_controller {
> pinctrl-0 = <&nand_pins>, <&nand_rb>;
> pinctrl-names = "default";
> - nand-ecc-strength = <4>;
> - nand-ecc-step-size = <512>;
> - marvell,nand-enable-arbiter;
> - marvell,system-controller = <&cps_syscon0>;
> - nand-on-flash-bbt;
> -
> - partition at 0 {
> - label = "U-Boot";
> - reg = <0 0x200000>;
> - };
> - partition at 200000 {
> - label = "Linux";
> - reg = <0x200000 0xe00000>;
> - };
> - partition at 1000000 {
> - label = "Filesystem";
> - reg = <0x1000000 0x3f000000>;
> +
> + nand at 0 {
> + reg = <0>;
> + marvell,rb = <0>;
> + nand-on-flash-bbt;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0 0x200000>;
> + };
> + partition at 200000 {
> + label = "Linux";
> + reg = <0x200000 0xe00000>;
> + };
> + partition at 1000000 {
> + label = "Filesystem";
> + reg = <0x1000000 0x3f000000>;
> + };
> + };
> };
> };
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> index cb1fb49ccf81..8610163bb1a4 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> @@ -310,20 +310,20 @@
> status = "disabled";
> };
>
> - cps_nand: nand at 720000 {
> + cps_nand_controller: nand at 720000 {
> /*
> * Due to the limiation of the pin available
> * this controller is only usable on the CPM
> * for A7K and on the CPS for A8K.
> */
> - compatible = "marvell,armada370-nand",
> - "marvell,armada-8k-nand";
> + compatible = "marvell,armada-8k-nand-controller",
> + "marvell,armada370-nand-controller";
> reg = <0x720000 0x54>;
> #address-cells = <1>;
> - #size-cells = <1>;
> + #size-cells = <0>;
> interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cps_clk 1 2>;
> - marvell,system-controller = <&cpm_syscon0>;
> + marvell,system-controller = <&cps_syscon0>;
> status = "disabled";
> };
>
> --
> 2.11.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 11/12] ARM64: dts: marvell: use reworked NAND controller driver on Armada 7K
From: Gregory CLEMENT @ 2017-12-15 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207201814.30411-12-miquel.raynal@free-electrons.com>
Hi Miquel,
On jeu., d?c. 07 2017, Miquel Raynal <miquel.raynal@free-electrons.com> wrote:
> Use the new bindings of the reworked Marvell NAND controller driver.
> Also adapt the nand controller node organization to distinguish which
> property is relevant for the controller, and which one is NAND chip
> specific. Expose the partitions as a subnode of the NAND chip.
>
> Remove the 'marvell,nand-enable-arbiter' property, not needed anymore as
> the driver activates the arbiter by default for all boards (either
> needed or harmless).
>
> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-7040-db.dts | 52 +++++++++++++---------
> .../boot/dts/marvell/armada-cp110-master.dtsi | 8 ++--
> 2 files changed, 36 insertions(+), 24 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
> index 52b5341cb270..758452c10612 100644
> --- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
> @@ -156,36 +156,48 @@
> };
> };
>
> -&cpm_nand {
> +&cpm_nand_controller {
> /*
> * SPI on CPM and NAND have common pins on this board. We can
> - * use only one at a time. To enable the NAND (whihch will
> + * use only one at a time. To enable the NAND (which will
> * disable the SPI), the "status = "okay";" line have to be
> * added here.
> */
> - num-cs = <1>;
> pinctrl-0 = <&nand_pins>, <&nand_rb>;
> pinctrl-names = "default";
> - nand-ecc-strength = <4>;
> - nand-ecc-step-size = <512>;
> - marvell,nand-enable-arbiter;
> - nand-on-flash-bbt;
> -
> - partition at 0 {
> - label = "U-Boot";
> - reg = <0 0x200000>;
> - };
> - partition at 200000 {
> - label = "Linux";
> - reg = <0x200000 0xe00000>;
> - };
> - partition at 1000000 {
> - label = "Filesystem";
> - reg = <0x1000000 0x3f000000>;
> +
> + nand at 0 {
> + reg = <0>;
> + label = "pxa3xx_nand-0";
> + marvell,rb = <0>;
> + nand-on-flash-bbt;
> + nand-ecc-strength = <4>;
> + nand-ecc-step-size = <512>;
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + partition at 0 {
> + label = "U-Boot";
> + reg = <0 0x200000>;
> + };
> +
> + partition at 200000 {
> + label = "Linux";
> + reg = <0x200000 0xe00000>;
> + };
> +
> + partition at 1000000 {
> + label = "Filesystem";
> + reg = <0x1000000 0x3f000000>;
> + };
> +
> + };
> };
> };
>
> -
> &cpm_spi1 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> index e3b64d03fbd8..8a3cff9a7343 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> @@ -309,17 +309,17 @@
> status = "disabled";
> };
>
> - cpm_nand: nand at 720000 {
> + cpm_nand_controller: nand at 720000 {
> /*
> * Due to the limiation of the pin available
> * this controller is only usable on the CPM
> * for A7K and on the CPS for A8K.
> */
> - compatible = "marvell,armada-8k-nand",
> - "marvell,armada370-nand";
> + compatible = "marvell,armada-8k-nand-controller",
> + "marvell,armada370-nand-controller";
> reg = <0x720000 0x54>;
> #address-cells = <1>;
> - #size-cells = <1>;
> + #size-cells = <0>;
> interrupts = <ICU_GRP_NSR 115 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpm_clk 1 2>;
> marvell,system-controller = <&cpm_syscon0>;
> --
> 2.11.0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH v12 1/3] ACPI/IORT: Add msi address regions reservation helper
From: Lorenzo Pieralisi @ 2017-12-15 10:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214160957.13716-2-shameerali.kolothum.thodi@huawei.com>
On Thu, Dec 14, 2017 at 04:09:55PM +0000, Shameer Kolothum wrote:
> On some platforms msi parent address regions have to be excluded from
> normal IOVA allocation in that they are detected and decoded in a HW
> specific way by system components and so they cannot be considered normal
> IOVA address space.
>
> Add a helper function that retrieves ITS address regions - the msi
> parent - through IORT device <-> ITS mappings and reserves it so that
> these regions will not be translated by IOMMU and will be excluded from
> IOVA allocations. The function checks for the smmu model number and
> only applies the msi reservation if the platform requires it.
>
> Signed-off-by: Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>
> ---
> drivers/acpi/arm64/iort.c | 111 +++++++++++++++++++++++++++++++++++++--
> drivers/irqchip/irq-gic-v3-its.c | 3 +-
> include/linux/acpi_iort.h | 7 ++-
> 3 files changed, 116 insertions(+), 5 deletions(-)
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c
> index 95255ec..e2f7bdd 100644
> --- a/drivers/acpi/arm64/iort.c
> +++ b/drivers/acpi/arm64/iort.c
> @@ -39,6 +39,7 @@
> struct iort_its_msi_chip {
> struct list_head list;
> struct fwnode_handle *fw_node;
> + phys_addr_t base_addr;
> u32 translation_id;
> };
>
> @@ -161,14 +162,16 @@ typedef acpi_status (*iort_find_node_callback)
> static DEFINE_SPINLOCK(iort_msi_chip_lock);
>
> /**
> - * iort_register_domain_token() - register domain token and related ITS ID
> - * to the list from where we can get it back later on.
> + * iort_register_domain_token() - register domain token along with related
> + * ITS ID and base address to the list from where we can get it back later on.
> * @trans_id: ITS ID.
> + * @base: ITS base address.
> * @fw_node: Domain token.
> *
> * Returns: 0 on success, -ENOMEM if no memory when allocating list element
> */
> -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node)
> +int iort_register_domain_token(int trans_id, phys_addr_t base,
> + struct fwnode_handle *fw_node)
> {
> struct iort_its_msi_chip *its_msi_chip;
>
> @@ -178,6 +181,7 @@ int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node)
>
> its_msi_chip->fw_node = fw_node;
> its_msi_chip->translation_id = trans_id;
> + its_msi_chip->base_addr = base;
>
> spin_lock(&iort_msi_chip_lock);
> list_add(&its_msi_chip->list, &iort_msi_chip_list);
> @@ -581,6 +585,24 @@ int iort_pmsi_get_dev_id(struct device *dev, u32 *dev_id)
> return -ENODEV;
> }
>
> +static int __maybe_unused iort_find_its_base(u32 its_id, phys_addr_t *base)
> +{
> + struct iort_its_msi_chip *its_msi_chip;
> + int ret = -ENODEV;
> +
> + spin_lock(&iort_msi_chip_lock);
> + list_for_each_entry(its_msi_chip, &iort_msi_chip_list, list) {
> + if (its_msi_chip->translation_id == its_id) {
> + *base = its_msi_chip->base_addr;
> + ret = 0;
> + break;
> + }
> + }
> + spin_unlock(&iort_msi_chip_lock);
> +
> + return ret;
> +}
> +
> /**
> * iort_dev_find_its_id() - Find the ITS identifier for a device
> * @dev: The device.
> @@ -766,6 +788,24 @@ static inline bool iort_iommu_driver_enabled(u8 type)
> }
>
> #ifdef CONFIG_IOMMU_API
> +static struct acpi_iort_node *iort_get_msi_resv_iommu(struct device *dev)
> +{
> + struct acpi_iort_node *iommu;
> + struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> +
> + iommu = iort_get_iort_node(fwspec->iommu_fwnode);
> +
> + if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) {
> + struct acpi_iort_smmu_v3 *smmu;
> +
> + smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data;
> + if (smmu->model == ACPI_IORT_SMMU_V3_HISILICON_HI161X)
> + return iommu;
> + }
> +
> + return NULL;
> +}
> +
> static inline const struct iommu_ops *iort_fwspec_iommu_ops(
> struct iommu_fwspec *fwspec)
> {
> @@ -782,6 +822,69 @@ static inline int iort_add_device_replay(const struct iommu_ops *ops,
>
> return err;
> }
> +
> +/**
> + * iort_iommu_msi_get_resv_regions - Reserved region driver helper
> + * @dev: Device from iommu_get_resv_regions()
> + * @head: Reserved region list from iommu_get_resv_regions()
> + *
> + * Returns: Number of msi reserved regions on success (0 if platform
> + * doesn't require the reservation or no associated msi regions),
> + * appropriate error value otherwise. The ITS interrupt translation
> + * spaces (ITS_base + SZ_64K, SZ_64K) associated with the device
> + * are the msi reserved regions.
> + */
> +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
> +{
> + struct acpi_iort_its_group *its;
> + struct acpi_iort_node *iommu_node, *its_node = NULL;
> + int i, resv = 0;
> +
> + iommu_node = iort_get_msi_resv_iommu(dev);
> + if (!iommu_node)
> + return 0;
> +
> + /*
> + * Current logic to reserve ITS regions relies on HW topologies
> + * where a given PCI or named component maps its IDs to only one
> + * ITS group; if a PCI or named component can map its IDs to
> + * different ITS groups through IORT mappings this function has
> + * to be reworked to ensure we reserve regions for all ITS groups
> + * a given PCI or named component may map IDs to.
> + */
> +
> + for (i = 0; i < dev->iommu_fwspec->num_ids; i++) {
> + its_node = iort_node_map_id(iommu_node,
> + dev->iommu_fwspec->ids[i],
> + NULL, IORT_MSI_TYPE);
> + if (its_node)
> + break;
> + }
> +
> + if (!its_node)
> + return 0;
> +
> + /* Move to ITS specific data */
> + its = (struct acpi_iort_its_group *)its_node->node_data;
> +
> + for (i = 0; i < its->its_count; i++) {
> + phys_addr_t base;
> +
> + if (!iort_find_its_base(its->identifiers[i], &base)) {
> + int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
> + struct iommu_resv_region *region;
> +
> + region = iommu_alloc_resv_region(base + SZ_64K, SZ_64K,
> + prot, IOMMU_RESV_MSI);
> + if (region) {
> + list_add_tail(®ion->list, head);
> + resv++;
> + }
> + }
> + }
> +
> + return (resv == its->its_count) ? resv : -ENODEV;
> +}
> #else
> static inline const struct iommu_ops *iort_fwspec_iommu_ops(
> struct iommu_fwspec *fwspec)
> @@ -789,6 +892,8 @@ static inline const struct iommu_ops *iort_fwspec_iommu_ops(
> static inline int iort_add_device_replay(const struct iommu_ops *ops,
> struct device *dev)
> { return 0; }
> +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
> +{ return 0; }
> #endif
>
> static int iort_iommu_xlate(struct device *dev, struct acpi_iort_node *node,
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 4039e64..d4cff12 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -3450,7 +3450,8 @@ static int __init gic_acpi_parse_madt_its(struct acpi_subtable_header *header,
> return -ENOMEM;
> }
>
> - err = iort_register_domain_token(its_entry->translation_id, dom_handle);
> + err = iort_register_domain_token(its_entry->translation_id, res.start,
> + dom_handle);
> if (err) {
> pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n",
> &res.start, its_entry->translation_id);
> diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h
> index 2f7a292..38cd77b 100644
> --- a/include/linux/acpi_iort.h
> +++ b/include/linux/acpi_iort.h
> @@ -26,7 +26,8 @@
> #define IORT_IRQ_MASK(irq) (irq & 0xffffffffULL)
> #define IORT_IRQ_TRIGGER_MASK(irq) ((irq >> 32) & 0xffffffffULL)
>
> -int iort_register_domain_token(int trans_id, struct fwnode_handle *fw_node);
> +int iort_register_domain_token(int trans_id, phys_addr_t base,
> + struct fwnode_handle *fw_node);
> void iort_deregister_domain_token(int trans_id);
> struct fwnode_handle *iort_find_domain_token(int trans_id);
> #ifdef CONFIG_ACPI_IORT
> @@ -38,6 +39,7 @@
> /* IOMMU interface */
> void iort_dma_setup(struct device *dev, u64 *dma_addr, u64 *size);
> const struct iommu_ops *iort_iommu_configure(struct device *dev);
> +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head);
> #else
> static inline void acpi_iort_init(void) { }
> static inline u32 iort_msi_map_rid(struct device *dev, u32 req_id)
> @@ -52,6 +54,9 @@ static inline void iort_dma_setup(struct device *dev, u64 *dma_addr,
> static inline const struct iommu_ops *iort_iommu_configure(
> struct device *dev)
> { return NULL; }
> +static inline
> +int iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)
> +{ return 0; }
> #endif
>
> #endif /* __ACPI_IORT_H__ */
> --
> 1.9.1
>
>
^ permalink raw reply
* [PATCH 1/2] soc: imx: gpc: Add i.MX6SX PCI power domain
From: Fabio Estevam @ 2017-12-15 10:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513329946.20023.1.camel@pengutronix.de>
Hi Lucas,
On Fri, Dec 15, 2017 at 7:25 AM, Lucas Stach <l.stach@pengutronix.de> wrote:
> Seems like the GPC rework did turn out to work as expected by making it
> easy to add additional power domains. :)
Yes, thanks for doing the GPC driver rework. It really helped :-)
> I didn't validate the register offsets, so this is:
> Acked-by: Lucas Stach <l.stach@pengutronix.de>
Thanks!
^ permalink raw reply
* [PATCH] ARM: dts: imx6q-h100: use usdhc2 VSELECT
From: Lucas Stach @ 2017-12-15 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215092624.12806-1-m.tretter@pengutronix.de>
Am Freitag, den 15.12.2017, 10:26 +0100 schrieb Michael Tretter:
> The uSDHC controller directly provides a VSELECT signal that can be
> muxed to the external voltage select. Mux the VSELECT directly to
> avoid
> using a GPIO.
>
> Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> ?arch/arm/boot/dts/imx6q-h100.dts | 25 +++----------------------
> ?1 file changed, 3 insertions(+), 22 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6q-h100.dts
> b/arch/arm/boot/dts/imx6q-h100.dts
> index a3269f57df2b..450ec967c257 100644
> --- a/arch/arm/boot/dts/imx6q-h100.dts
> +++ b/arch/arm/boot/dts/imx6q-h100.dts
> @@ -108,21 +108,6 @@
> ? regulator-always-on;
> ? };
> ?
> - reg_nvcc_sd2: regulator-nvcc-sd2 {
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_h100_reg_nvcc_sd2>;
> - compatible = "regulator-gpio";
> - regulator-name = "NVCC_SD2";
> - regulator-min-microvolt = <1800000>;
> - regulator-max-microvolt = <3300000>;
> - regulator-type = "voltage";
> - regulator-boot-on;
> - regulator-always-on;
> - gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
> - states = <1800000 0x1
> - ??3300000 0x0>;
> - };
> -
> ? reg_usbh1_vbus: regulator-usb-h1-vbus {
> ? compatible = "regulator-fixed";
> ? enable-active-high;
> @@ -260,12 +245,6 @@
> ? >;
> ? };
> ?
> - pinctrl_h100_reg_nvcc_sd2: h100-reg-nvcc-sd2 {
> - fsl,pins = <
> - MX6QDL_PAD_KEY_ROW1__GPIO4_IO09
> 0x1b0b0
> - >;
> - };
> -
> ? pinctrl_h100_sgtl5000: h100-sgtl5000 {
> ? fsl,pins = <
> ? MX6QDL_PAD_DISP0_DAT19__AUD5_RXD
> 0x130b0
> @@ -316,6 +295,7 @@
> ? MX6QDL_PAD_SD2_DAT1__SD2_DATA1
> 0x17059
> ? MX6QDL_PAD_SD2_DAT2__SD2_DATA2
> 0x17059
> ? MX6QDL_PAD_SD2_DAT3__SD2_DATA3
> 0x13059
> + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT
> 0x1b0b0
> ? >;
> ? };
> ?
> @@ -328,6 +308,7 @@
> ? MX6QDL_PAD_SD2_DAT1__SD2_DATA1
> 0x170b9
> ? MX6QDL_PAD_SD2_DAT2__SD2_DATA2
> 0x170b9
> ? MX6QDL_PAD_SD2_DAT3__SD2_DATA3
> 0x170b9
> + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT
> 0x1b0b0
> ? >;
> ? };
> ?
> @@ -340,6 +321,7 @@
> ? MX6QDL_PAD_SD2_DAT1__SD2_DATA1
> 0x170f9
> ? MX6QDL_PAD_SD2_DAT2__SD2_DATA2
> 0x170f9
> ? MX6QDL_PAD_SD2_DAT3__SD2_DATA3
> 0x170f9
> + MX6QDL_PAD_KEY_ROW1__SD2_VSELECT
> 0x1b0b0
> ? >;
> ? };
> ? };
> @@ -389,7 +371,6 @@
> ? pinctrl-1 = <&pinctrl_h100_usdhc2_100mhz>;
> ? pinctrl-2 = <&pinctrl_h100_usdhc2_200mhz>;
> ? vmmc-supply = <®_3p3v>;
> - vqmmc-supply = <®_nvcc_sd2>;
> ? cd-gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
> ? status = "okay";
> ?};
^ permalink raw reply
* [RFC PATCH 0/5] Introduce PMSAv8 memory protection unit
From: Szemző András @ 2017-12-15 10:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513184527-44120-1-git-send-email-vladimir.murzin@arm.com>
Hi,
> On 2017. Dec 13., at 18:02, Vladimir Murzin <vladimir.murzin@arm.com> wrote:
>
> Hi,
>
> This series is an attempt to add support for PMSAv8 MPU defined by
> ARMv8R/M architecture.
>
> I'm have a doubt about adding dedicated config option, so both v7 and
> v8 versions of PMSA are covered with CONFIG_MPU, but I'd glad to hear
> what people think of it.
>
> Thanks!
>
> Vladimir Murzin (5):
> ARM: NOMMU: Move PMSAv7 MPU under it's own namespace
> ARM: NOMMU: Reorganise __setup_mpu
> ARM: NOMMU: Postpone MPU activation till __after_proc_init
> ARM: NOMMU: Make _stext and _end meet PMSAv8 alignment restrictions
> ARM: NOMMU: Support PMSAv8 MPU
>
I?ve tested this series on my Atmel armv7m board, and it doesn?t break anything on my side.
(My test setup is running kernel from SDRAM, with rootfs on SDcard, so no XIP was tested)
FWIW, you can add my Tested-by for patches 1-4.
Thanks!
Regards,
Andras
^ permalink raw reply
* [PATCH 02/10] arm64: limit PA size to supported range
From: Suzuki K Poulose @ 2017-12-15 10:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cdca0649-fa3d-a5ea-a7ee-fc30626ca2fc@arm.com>
On 14/12/17 18:34, Marc Zyngier wrote:
> On 13/12/17 17:07, Kristina Martsenko wrote:
>> We currently copy the physical address size from
>> ID_AA64MMFR0_EL1.PARange directly into TCR.(I)PS. This will not work for
>> 4k and 16k granule kernels on systems that support 52-bit physical
>> addresses, since 52-bit addresses are only permitted with the 64k
>> granule.
>>
>> To fix this, fall back to 48 bits when configuring the PA size when the
>> kernel does not support 52-bit PAs. When it does, fall back to 52, to
>> avoid similar problems in the future if the PA size is ever increased
>> above 52.
>>
>> Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
>> ---
>> arch/arm64/include/asm/assembler.h | 13 +++++++++++++
>> arch/arm64/include/asm/sysreg.h | 8 ++++++++
>> arch/arm64/kvm/hyp-init.S | 6 ++----
>> arch/arm64/kvm/hyp/s2-setup.c | 2 ++
>> arch/arm64/mm/proc.S | 6 ++----
>> 5 files changed, 27 insertions(+), 8 deletions(-)
>>
>> diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
>> index aef72d886677..6cddf12a0250 100644
>> --- a/arch/arm64/include/asm/assembler.h
>> +++ b/arch/arm64/include/asm/assembler.h
>> @@ -351,6 +351,19 @@ alternative_endif
>> .endm
>>
>> /*
>> + * tcr_set_pa_size - set TCR.(I)PS to the highest supported
>> + * ID_AA64MMFR0_EL1.PARange value
>
> It'd be good to document what are the expected parameters here.
>
>> + */
>> + .macro tcr_set_pa_size, tcr, pos, tmp0, tmp1
>
> Small nit: "tcr_compute_pa_size" would better describe what this does.
>
>> + mrs \tmp0, ID_AA64MMFR0_EL1
>> + ubfx \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
>
> It'd be good to have a comment explaining that we narrow the PARange to
> fit the PS firld in TCR. Who knows what will happen once (if ever) we
> get two other PARange extentions... ;-)
>
>> + mov \tmp1, #ID_AA64MMFR0_PARANGE_MAX
>> + cmp \tmp0, \tmp1
>> + csel \tmp0, \tmp1, \tmp0, hi
>> + bfi \tcr, \tmp0, \pos, #3> + .endm
>> +
>> +/*
>> * Macro to perform a data cache maintenance for the interval
>> * [kaddr, kaddr + size)
>> *
>> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
>> index 08cc88574659..ec144f480b39 100644
>> --- a/arch/arm64/include/asm/sysreg.h
>> +++ b/arch/arm64/include/asm/sysreg.h
>> @@ -471,6 +471,14 @@
>> #define ID_AA64MMFR0_TGRAN64_SUPPORTED 0x0
>> #define ID_AA64MMFR0_TGRAN16_NI 0x0
>> #define ID_AA64MMFR0_TGRAN16_SUPPORTED 0x1
>> +#define ID_AA64MMFR0_PARANGE_48 0x5
>> +#define ID_AA64MMFR0_PARANGE_52 0x6
>> +
>> +#ifdef CONFIG_ARM64_PA_BITS_52
>> +#define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_52
>> +#else
>> +#define ID_AA64MMFR0_PARANGE_MAX ID_AA64MMFR0_PARANGE_48
>> +#endif
>>
>> /* id_aa64mmfr1 */
>> #define ID_AA64MMFR1_PAN_SHIFT 20
>> diff --git a/arch/arm64/kvm/hyp-init.S b/arch/arm64/kvm/hyp-init.S
>> index 3f9615582377..f731a48bd9f1 100644
>> --- a/arch/arm64/kvm/hyp-init.S
>> +++ b/arch/arm64/kvm/hyp-init.S
>> @@ -90,11 +90,9 @@ __do_hyp_init:
>> bfi x4, x5, TCR_T0SZ_OFFSET, TCR_TxSZ_WIDTH
>> #endif
>> /*
>> - * Read the PARange bits from ID_AA64MMFR0_EL1 and set the PS bits in
>> - * TCR_EL2.
>> + * Set the PS bits in TCR_EL2.
>> */
>> - mrs x5, ID_AA64MMFR0_EL1
>> - bfi x4, x5, #16, #3
>> + tcr_set_pa_size x4, #16, x5, x6
>>
>> msr tcr_el2, x4
>>
>> diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c
>> index a81f5e10fc8c..603e1ee83e89 100644
>> --- a/arch/arm64/kvm/hyp/s2-setup.c
>> +++ b/arch/arm64/kvm/hyp/s2-setup.c
>> @@ -32,6 +32,8 @@ u32 __hyp_text __init_stage2_translation(void)
>> * PS is only 3. Fortunately, bit 19 is RES0 in VTCR_EL2...
>> */
>> parange = read_sysreg(id_aa64mmfr0_el1) & 7;
>> + if (parange > ID_AA64MMFR0_PARANGE_MAX)
>> + parange = ID_AA64MMFR0_PARANGE_MAX;
>> val |= parange << 16;
>>
>> /* Compute the actual PARange... */
>> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
>> index 95233dfc4c39..c10c6c180961 100644
>> --- a/arch/arm64/mm/proc.S
>> +++ b/arch/arm64/mm/proc.S
>> @@ -228,11 +228,9 @@ ENTRY(__cpu_setup)
>> tcr_set_idmap_t0sz x10, x9
>>
>> /*
>> - * Read the PARange bits from ID_AA64MMFR0_EL1 and set the IPS bits in
>> - * TCR_EL1.
>> + * Set the IPS bits in TCR_EL1.
>> */
>> - mrs x9, ID_AA64MMFR0_EL1
>> - bfi x10, x9, #32, #3
>> + tcr_set_pa_size x10, #32, x5, x6
>> #ifdef CONFIG_ARM64_HW_AFDBM
>> /*
>> * Hardware update of the Access and Dirty bits.
>>
>
> Other than the nits above:
>
Kristina,
If you are spinning another version correcting those, please could you
also add the bit definitions for TCR_EL2_PS and TCR_EL1_IPS and use them
here instead of the constants above ?
Cheers
Suzuki
^ permalink raw reply
* [PATCH] KVM: arm/arm64: don't set vtimer->cnt_ctl in kvm_arch_timer_handler
From: Christoffer Dall @ 2017-12-15 10:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <519f0e33-4419-68be-32b4-11bb5e19cf17@arm.com>
On Fri, Dec 15, 2017 at 09:09:05AM +0000, Marc Zyngier wrote:
> On 15/12/17 02:27, Jia He wrote:
> >
> >
>
> [...]
>
> >> @@ -367,6 +368,7 @@ static void vtimer_save_state(struct kvm_vcpu *vcpu)
> >>
> >> /* Disable the virtual timer */
> >> write_sysreg_el0(0, cntv_ctl);
> >> + isb();
> > My only concern is whether this isb() is required here?
> > Sorryif this is a stupid question.I understand little about arm arch
> > memory barrier. But seems isb will flush all the instruction prefetch.Do
> > you think if an timer interrupt irq arrives, arm will use the previous
> > instruction prefetch?
>
>
> This barrier has little to do with prefetch. It just guarantees that the
> code after the isb() is now running with a disabled virtual timer.
> Otherwise, a CPU can freely reorder the write_sysreg() until the next
> context synchronization event.
>
> An interrupt coming between the write and the barrier will also act as a
> context synchronization event. For more details, see the ARMv8 ARM (the
> glossary has a section on the concept).
>
So since an ISB doesn't guarantee that the timer will actually be
disabled, is it a waste of energy to have it, or should we keep it as a
best effort kind of thing?
Thanks,
-Christoffer
^ permalink raw reply
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