* [PATCH v6] atmel_flexcom: Support resuming after a chip reset
From: Nicolas Ferre @ 2017-12-19 8:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218201907.GU7022@piout.net>
On 18/12/2017 at 21:19, Alexandre Belloni wrote:
> On 12/12/2017 at 17:21:19 +0100, Romain Izard wrote:
>> The controller used by a flexcom module is configured at boot, and left
>> alone after this. In the suspend mode called "backup with self-refresh"
>> available on SAMA5D2, the chip will resume with most of its registers
>> reset. In this case, we need to restore the state of the flexcom driver
>> on resume.
>>
>> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
>
> Seems good to me
>
> Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Thanks Romain, of course I can add the tags that I gave you already:
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Tested-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Lee,
It seems that you already gave your tag for the v5 of this patch. The
wording is even better with this patch. So, can you take this patch in
your tree?
Best regards,
Nicolas
>> ---
>> Changes in v5:
>> * extract from the patch series, and send as a standalone patch
>>
>> Changes in v6:
>> * Reword the patch title and description
>> * Rename the internal structure to ddata
>>
>> drivers/mfd/atmel-flexcom.c | 63 ++++++++++++++++++++++++++++++++++-----------
>> 1 file changed, 48 insertions(+), 15 deletions(-)
>>
>> diff --git a/drivers/mfd/atmel-flexcom.c b/drivers/mfd/atmel-flexcom.c
>> index 064bde9cff5a..f684a93a3340 100644
>> --- a/drivers/mfd/atmel-flexcom.c
>> +++ b/drivers/mfd/atmel-flexcom.c
>> @@ -39,34 +39,43 @@
>> #define FLEX_MR_OPMODE(opmode) (((opmode) << FLEX_MR_OPMODE_OFFSET) & \
>> FLEX_MR_OPMODE_MASK)
>>
>> +struct atmel_flexcom {
>> + void __iomem *base;
>> + u32 opmode;
>> + struct clk *clk;
>> +};
>>
>> static int atmel_flexcom_probe(struct platform_device *pdev)
>> {
>> struct device_node *np = pdev->dev.of_node;
>> - struct clk *clk;
>> struct resource *res;
>> - void __iomem *base;
>> - u32 opmode;
>> + struct atmel_flexcom *ddata;
>> int err;
>>
>> - err = of_property_read_u32(np, "atmel,flexcom-mode", &opmode);
>> + ddata = devm_kzalloc(&pdev->dev, sizeof(*ddata), GFP_KERNEL);
>> + if (!ddata)
>> + return -ENOMEM;
>> +
>> + platform_set_drvdata(pdev, ddata);
>> +
>> + err = of_property_read_u32(np, "atmel,flexcom-mode", &ddata->opmode);
>> if (err)
>> return err;
>>
>> - if (opmode < ATMEL_FLEXCOM_MODE_USART ||
>> - opmode > ATMEL_FLEXCOM_MODE_TWI)
>> + if (ddata->opmode < ATMEL_FLEXCOM_MODE_USART ||
>> + ddata->opmode > ATMEL_FLEXCOM_MODE_TWI)
>> return -EINVAL;
>>
>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> - base = devm_ioremap_resource(&pdev->dev, res);
>> - if (IS_ERR(base))
>> - return PTR_ERR(base);
>> + ddata->base = devm_ioremap_resource(&pdev->dev, res);
>> + if (IS_ERR(ddata->base))
>> + return PTR_ERR(ddata->base);
>>
>> - clk = devm_clk_get(&pdev->dev, NULL);
>> - if (IS_ERR(clk))
>> - return PTR_ERR(clk);
>> + ddata->clk = devm_clk_get(&pdev->dev, NULL);
>> + if (IS_ERR(ddata->clk))
>> + return PTR_ERR(ddata->clk);
>>
>> - err = clk_prepare_enable(clk);
>> + err = clk_prepare_enable(ddata->clk);
>> if (err)
>> return err;
>>
>> @@ -76,9 +85,9 @@ static int atmel_flexcom_probe(struct platform_device *pdev)
>> * inaccessible and are read as zero. Also the external I/O lines of the
>> * Flexcom are muxed to reach the selected device.
>> */
>> - writel(FLEX_MR_OPMODE(opmode), base + FLEX_MR);
>> + writel(FLEX_MR_OPMODE(ddata->opmode), ddata->base + FLEX_MR);
>>
>> - clk_disable_unprepare(clk);
>> + clk_disable_unprepare(ddata->clk);
>>
>> return devm_of_platform_populate(&pdev->dev);
>> }
>> @@ -89,10 +98,34 @@ static const struct of_device_id atmel_flexcom_of_match[] = {
>> };
>> MODULE_DEVICE_TABLE(of, atmel_flexcom_of_match);
>>
>> +#ifdef CONFIG_PM_SLEEP
>> +static int atmel_flexcom_resume(struct device *dev)
>> +{
>> + struct atmel_flexcom *ddata = dev_get_drvdata(dev);
>> + int err;
>> + u32 val;
>> +
>> + err = clk_prepare_enable(ddata->clk);
>> + if (err)
>> + return err;
>> +
>> + val = FLEX_MR_OPMODE(ddata->opmode),
>> + writel(val, ddata->base + FLEX_MR);
>> +
>> + clk_disable_unprepare(ddata->clk);
>> +
>> + return 0;
>> +}
>> +#endif
>> +
>> +static SIMPLE_DEV_PM_OPS(atmel_flexcom_pm_ops, NULL,
>> + atmel_flexcom_resume);
>> +
>> static struct platform_driver atmel_flexcom_driver = {
>> .probe = atmel_flexcom_probe,
>> .driver = {
>> .name = "atmel_flexcom",
>> + .pm = &atmel_flexcom_pm_ops,
>> .of_match_table = atmel_flexcom_of_match,
>> },
>> };
>> --
>> 2.14.1
>>
>
--
Nicolas Ferre
^ permalink raw reply
* [PATCH v3 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
From: Maxime Ripard @ 2017-12-19 8:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219080747.4507-3-embed3d@gmail.com>
On Tue, Dec 19, 2017 at 09:07:43AM +0100, Philipp Rossak wrote:
> This patch updates documentation for Device-Tree bindings for sunxi IR
> controller and adds the new optional property for the base clock
> frequency.
>
> Signed-off-by: Philipp Rossak <embed3d@gmail.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH V4 21/26] backlight: deprecate pci_get_bus_and_slot()
From: Lee Jones @ 2017-12-19 8:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513661883-28662-22-git-send-email-okaya@codeaurora.org>
On Tue, 19 Dec 2017, Sinan Kaya wrote:
> pci_get_bus_and_slot() is restrictive such that it assumes domain=0 as
> where a PCI device is present. This restricts the device drivers to be
> reused for other domain numbers.
>
> Getting ready to remove pci_get_bus_and_slot() function in favor of
> pci_get_domain_bus_and_slot().
>
> Hard-coding the domain as 0.
>
> Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
> Acked-by: Jingoo Han <jingoohan1@gmail.com>
> Acked-by: Daniel Thompson <daniel.thompson@linaro.org>
> ---
> drivers/video/backlight/apple_bl.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
--
Lee Jones
Linaro Services Technical Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH v2] IPI performance benchmark
From: Yury Norov @ 2017-12-19 8:50 UTC (permalink / raw)
To: linux-arm-kernel
This benchmark sends many IPIs in different modes and measures
time for IPI delivery (first column), and total time, ie including
time to acknowledge the receive by sender (second column).
The scenarios are:
Dry-run: do everything except actually sending IPI. Useful
to estimate system overhead.
Self-IPI: Send IPI to self CPU.
Normal IPI: Send IPI to some other CPU.
Broadcast IPI: Send broadcast IPI to all online CPUs.
Broadcast lock: Send broadcast IPI to all online CPUs and force them
acquire/release spinlock.
The raw output looks like this:
[ 155.363374] Dry-run: 0, 2999696 ns
[ 155.429162] Self-IPI: 30385328, 65589392 ns
[ 156.060821] Normal IPI: 566914128, 631453008 ns
[ 158.384427] Broadcast IPI: 0, 2323368720 ns
[ 160.831850] Broadcast lock: 0, 2447000544 ns
For virtualized guests, sending and reveiving IPIs causes guest exit.
I used this test to measure performance impact on KVM subsystem of
Christoffer Dall's series "Optimize KVM/ARM for VHE systems" [1].
Test machine is ThunderX2, 112 online CPUs. Below the results normalized
to host dry-run time, broadcast lock results omitted. Smaller - better.
Host, v4.14:
Dry-run: 0 1
Self-IPI: 9 18
Normal IPI: 81 110
Broadcast IPI: 0 2106
Guest, v4.14:
Dry-run: 0 1
Self-IPI: 10 18
Normal IPI: 305 525
Broadcast IPI: 0 9729
Guest, v4.14 + [1]:
Dry-run: 0 1
Self-IPI: 9 18
Normal IPI: 176 343
Broadcast IPI: 0 9885
[1] https://www.spinics.net/lists/kvm/msg156755.html
v2:
added broadcast lock test;
added example raw output in patch description;
CC: Andrew Morton <akpm@linux-foundation.org>
CC: Ashish Kalra <Ashish.Kalra@cavium.com>
CC: Christoffer Dall <christoffer.dall@linaro.org>
CC: Geert Uytterhoeven <geert@linux-m68k.org>
CC: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
CC: Linu Cherian <Linu.Cherian@cavium.com>
CC: Shih-Wei Li <shihwei@cs.columbia.edu>
CC: Sunil Goutham <Sunil.Goutham@cavium.com>
Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
---
arch/Kconfig | 10 ++++
kernel/Makefile | 1 +
kernel/ipi_benchmark.c | 153 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 164 insertions(+)
create mode 100644 kernel/ipi_benchmark.c
diff --git a/arch/Kconfig b/arch/Kconfig
index 400b9e1b2f27..1b216eb15642 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -82,6 +82,16 @@ config JUMP_LABEL
( On 32-bit x86, the necessary options added to the compiler
flags may increase the size of the kernel slightly. )
+config IPI_BENCHMARK
+ tristate "Test IPI performance on SMP systems"
+ depends on SMP
+ help
+ Test IPI performance on SMP systems. If system has only one online
+ CPU, sending IPI to other CPU is obviously not possible, and ENOENT
+ is returned for corresponding test.
+
+ If unsure, say N.
+
config STATIC_KEYS_SELFTEST
bool "Static key selftest"
depends on JUMP_LABEL
diff --git a/kernel/Makefile b/kernel/Makefile
index 172d151d429c..04e550e1990c 100644
--- a/kernel/Makefile
+++ b/kernel/Makefile
@@ -101,6 +101,7 @@ obj-$(CONFIG_TRACEPOINTS) += trace/
obj-$(CONFIG_IRQ_WORK) += irq_work.o
obj-$(CONFIG_CPU_PM) += cpu_pm.o
obj-$(CONFIG_BPF) += bpf/
+obj-$(CONFIG_IPI_BENCHMARK) += ipi_benchmark.o
obj-$(CONFIG_PERF_EVENTS) += events/
diff --git a/kernel/ipi_benchmark.c b/kernel/ipi_benchmark.c
new file mode 100644
index 000000000000..1dfa15e5ef70
--- /dev/null
+++ b/kernel/ipi_benchmark.c
@@ -0,0 +1,153 @@
+/*
+ * Performance test for IPI on SMP machines.
+ *
+ * Copyright (c) 2017 Cavium Networks.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of version 2 of the GNU General Public
+ * License as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/ktime.h>
+
+#define NTIMES 100000
+
+#define POKE_ANY 0
+#define DRY_RUN 1
+#define POKE_SELF 2
+#define POKE_ALL 3
+#define POKE_ALL_LOCK 4
+
+static void __init handle_ipi_spinlock(void *t)
+{
+ spinlock_t *lock = (spinlock_t *) t;
+
+ spin_lock(lock);
+ spin_unlock(lock);
+}
+
+static void __init handle_ipi(void *t)
+{
+ ktime_t *time = (ktime_t *) t;
+
+ if (time)
+ *time = ktime_get() - *time;
+}
+
+static ktime_t __init send_ipi(int flags)
+{
+ ktime_t time = 0;
+ DEFINE_SPINLOCK(lock);
+ unsigned int cpu = get_cpu();
+
+ switch (flags) {
+ case DRY_RUN:
+ /* Do everything except actually sending IPI. */
+ break;
+ case POKE_ALL:
+ /* If broadcasting, don't force all CPUs to update time. */
+ smp_call_function_many(cpu_online_mask, handle_ipi, NULL, 1);
+ break;
+ case POKE_ALL_LOCK:
+ smp_call_function_many(cpu_online_mask,
+ handle_ipi_spinlock, &lock, 1);
+ break;
+ case POKE_ANY:
+ cpu = cpumask_any_but(cpu_online_mask, cpu);
+ if (cpu >= nr_cpu_ids) {
+ time = -ENOENT;
+ break;
+ }
+ /* Fall thru */
+ case POKE_SELF:
+ time = ktime_get();
+ smp_call_function_single(cpu, handle_ipi, &time, 1);
+ break;
+ default:
+ time = -EINVAL;
+ }
+
+ put_cpu();
+ return time;
+}
+
+static int __init __bench_ipi(unsigned long i, ktime_t *time, int flags)
+{
+ ktime_t t;
+
+ *time = 0;
+ while (i--) {
+ t = send_ipi(flags);
+ if ((int) t < 0)
+ return (int) t;
+
+ *time += t;
+ }
+
+ return 0;
+}
+
+static int __init bench_ipi(unsigned long times, int flags,
+ ktime_t *ipi, ktime_t *total)
+{
+ int ret;
+
+ *total = ktime_get();
+ ret = __bench_ipi(times, ipi, flags);
+ if (unlikely(ret))
+ return ret;
+
+ *total = ktime_get() - *total;
+
+ return 0;
+}
+
+static int __init init_bench_ipi(void)
+{
+ ktime_t ipi, total;
+ int ret;
+
+ ret = bench_ipi(NTIMES, DRY_RUN, &ipi, &total);
+ if (ret)
+ pr_err("Dry-run FAILED: %d\n", ret);
+ else
+ pr_err("Dry-run: %18llu, %18llu ns\n", ipi, total);
+
+ ret = bench_ipi(NTIMES, POKE_SELF, &ipi, &total);
+ if (ret)
+ pr_err("Self-IPI FAILED: %d\n", ret);
+ else
+ pr_err("Self-IPI: %18llu, %18llu ns\n", ipi, total);
+
+ ret = bench_ipi(NTIMES, POKE_ANY, &ipi, &total);
+ if (ret)
+ pr_err("Normal IPI FAILED: %d\n", ret);
+ else
+ pr_err("Normal IPI: %18llu, %18llu ns\n", ipi, total);
+
+ ret = bench_ipi(NTIMES, POKE_ALL, &ipi, &total);
+ if (ret)
+ pr_err("Broadcast IPI FAILED: %d\n", ret);
+ else
+ pr_err("Broadcast IPI: %18llu, %18llu ns\n", ipi, total);
+
+ ret = bench_ipi(NTIMES, POKE_ALL_LOCK, &ipi, &total);
+ if (ret)
+ pr_err("Broadcast lock FAILED: %d\n", ret);
+ else
+ pr_err("Broadcast lock: %18llu, %18llu ns\n", ipi, total);
+
+ /* Return error to avoid annoying rmmod. */
+ return -EINVAL;
+}
+module_init(init_bench_ipi);
+
+MODULE_LICENSE("GPL");
--
2.11.0
^ permalink raw reply related
* [PATCH v6] atmel_flexcom: Support resuming after a chip reset
From: Lee Jones @ 2017-12-19 8:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171212162119.32138-1-romain.izard.pro@gmail.com>
On Tue, 12 Dec 2017, Romain Izard wrote:
> The controller used by a flexcom module is configured at boot, and left
> alone after this. In the suspend mode called "backup with self-refresh"
> available on SAMA5D2, the chip will resume with most of its registers
> reset. In this case, we need to restore the state of the flexcom driver
> on resume.
>
> Signed-off-by: Romain Izard <romain.izard.pro@gmail.com>
> ---
> Changes in v5:
> * extract from the patch series, and send as a standalone patch
>
> Changes in v6:
> * Reword the patch title and description
> * Rename the internal structure to ddata
>
> drivers/mfd/atmel-flexcom.c | 63 ++++++++++++++++++++++++++++++++++-----------
> 1 file changed, 48 insertions(+), 15 deletions(-)
Applied, thanks.
--
Lee Jones
Linaro Services Technical Lead
Linaro.org ? Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* [PATCH V2 9/9] ARM: dts: stm32: add initial support of stm32mp157c eval board
From: Ludovic BARRE @ 2017-12-19 8:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a14KzxGK8j75UUBfWgexg2fdzrtdgcqUT=uHfjWrVaWbA@mail.gmail.com>
On 12/18/2017 09:20 PM, Arnd Bergmann wrote:
> On Mon, Dec 18, 2017 at 4:17 PM, Ludovic Barre <ludovic.Barre@st.com> wrote:
> =
>> +
>> +/ {
>> + model = "STMicroelectronics STM32MP157C eval daughter";
>> + compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
>> +
>> + chosen {
>> + bootargs = "earlyprintk console=ttySTM3,115200 root=/dev/ram";
>> + stdout-path = "serial3:115200n8";
>> + };
>
> I'd remove the bootargs here and let the boot loader take care of
> that, in particular
> since all three arguments are rather old-school: earlycon is preferred over
> earlyprintk, console= should not be needed if you set stdout-path, and
> /dev/ram is obsoleted by initramfs.
OK, thanks
BR
Ludo
>
> Arnd
>
^ permalink raw reply
* [PATCH 2/2] ARM: dts: r8a7745: move timer node out of bus
From: Geert Uytterhoeven @ 2017-12-19 8:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218215044.13088-3-horms+renesas@verge.net.au>
On Mon, Dec 18, 2017 at 10:50 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> The timer node does not have any register properties and thus shouldn't be
> placed on the bus.
>
> This problem is flagged by the compiler as follows:
> $ make dtbs W=1
> ...
> arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> DTC arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb
> arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 1/2] ARM: dts: r8a7745: sort root sub-nodes alphabetically
From: Geert Uytterhoeven @ 2017-12-19 8:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218215044.13088-2-horms+renesas@verge.net.au>
On Mon, Dec 18, 2017 at 10:50 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Sort root sub-nodes alphabetically for allow for easier maintenance
to allow for
> of this file.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v2 2/2] ARM: dts: r8a7743: move timer node out of bus
From: Geert Uytterhoeven @ 2017-12-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218214043.10796-3-horms+renesas@verge.net.au>
On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> The timer node does not have any register properties and thus shouldn't be
> placed on the bus.
>
> This problem is flagged by the compiler as follows:
> $ make
> DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
> arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> DTC arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb
> arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: r8a7743: sort root sub-nodes alphabetically
From: Geert Uytterhoeven @ 2017-12-19 8:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218214043.10796-2-horms+renesas@verge.net.au>
Hi Simon,
On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Sort root sub-nodes alphabetically for allow for easier maintenance
to allow for
> of this file.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/arch/arm/boot/dts/r8a7743.dtsi
> +++ b/arch/arm/boot/dts/r8a7743.dtsi
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -79,6 +102,37 @@
> };
> };
>
> + /* External CAN clock */
> + can_clk: can {
Doesn't look alphabetically to me...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 2/2] ARM: dts: r8a7792: move timer node out of bus
From: Geert Uytterhoeven @ 2017-12-19 8:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218213233.3373-3-horms+renesas@verge.net.au>
On Mon, Dec 18, 2017 at 10:32 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> The timer node does not have any register properties and thus shouldn't be
> placed on the bus.
>
> This problem is flagged by the compiler as follows:
> $ make dtbs W=1
> ...
> DTC arch/arm/boot/dts/r8a7792-wheat.dtb
> arch/arm/boot/dts/r8a7792-blanche.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> arch/arm/boot/dts/r8a7792-wheat.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH 1/2] ARM: dts: r8a7792: sort root sub-nodes alphabetically
From: Geert Uytterhoeven @ 2017-12-19 8:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218213233.3373-2-horms+renesas@verge.net.au>
On Mon, Dec 18, 2017 at 10:32 PM, Simon Horman
<horms+renesas@verge.net.au> wrote:
> Sort root sub-nodes alphabetically for allow for easier maintenance
to allow for
> of this file.
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH] i2c: stm32: Fixes multibyte transfer for STM32F4 I2C controller
From: Radosław Pietrzyk @ 2017-12-19 8:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <dae4399e-4209-b052-a4c0-8a11c17ce032@st.com>
My understanding is that this driver is currently vulnerable to any
IRQ delays that may happen in the system and this patch eliminates the
problem but you may prove me wrong.
2017-12-07 14:23 GMT+01:00 Pierre Yves MORDRET <pierre-yves.mordret@st.com>:
>
> I do believe some investigation has to be done prior merging this patch.
> The impact is genuine and has to be tested thoroughly before granting an ack.
>
> Thus I prefer having a better understanding of the issue.
> I will try to work on this later on.
>
> Regards
>
>
> On 12/07/2017 11:52 AM, Wolfram Sang wrote:
>> On Tue, Oct 24, 2017 at 01:45:43PM +0200, Rados?aw Pietrzyk wrote:
>>> I'm afraid that didn't help and the problem still exists even with
>>> those patches applied.
>>
>> So, my reading is: There is an issue which needs to be investigated?
>> Does applying the patch make sense until the issue is fully understood?
>>
^ permalink raw reply
* [PATCH 1/2] clocksource: timer-dm: Make unexported functions static
From: Keerthy @ 2017-12-19 8:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218113056.GA18637@lenoch>
On Monday 18 December 2017 05:00 PM, Ladislav Michl wrote:
> As dmtimer no longer exports functions, there is no point
> to have them non-static. Also delete those not used anywhere.
I will refrain from this patch at the moment. I have plans of another
series to do some more cleanups. For now want to keep the changes minimal.
Some of the functions that you are removing in this patch might be
needed and can be added for ops in future.
So i will let this be separate patch.
Thanks,
Keerthy
>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> ---
> drivers/clocksource/timer-dm.c | 125 ++++++++---------------------------------
> include/clocksource/dmtimer.h | 26 ---------
> 2 files changed, 23 insertions(+), 128 deletions(-)
>
> diff --git a/drivers/clocksource/timer-dm.c b/drivers/clocksource/timer-dm.c
> index 392978ccd8a6..ec3a28c90c70 100644
> --- a/drivers/clocksource/timer-dm.c
> +++ b/drivers/clocksource/timer-dm.c
> @@ -204,16 +204,6 @@ static inline u32 omap_dm_timer_reserved_systimer(int id)
> return (omap_reserved_systimers & (1 << (id - 1))) ? 1 : 0;
> }
>
> -int omap_dm_timer_reserve_systimer(int id)
> -{
> - if (omap_dm_timer_reserved_systimer(id))
> - return -ENODEV;
> -
> - omap_reserved_systimers |= (1 << (id - 1));
> -
> - return 0;
> -}
> -
> static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
> {
> struct omap_dm_timer *timer = NULL, *t;
> @@ -298,16 +288,16 @@ static struct omap_dm_timer *_omap_dm_timer_request(int req_type, void *data)
> return timer;
> }
>
> -struct omap_dm_timer *omap_dm_timer_request(void)
> +static struct omap_dm_timer *omap_dm_timer_request(void)
> {
> return _omap_dm_timer_request(REQUEST_ANY, NULL);
> }
>
> -struct omap_dm_timer *omap_dm_timer_request_specific(int id)
> +static struct omap_dm_timer *omap_dm_timer_request_specific(int id)
> {
> /* Requesting timer by ID is not supported when device tree is used */
> if (of_have_populated_dt()) {
> - pr_warn("%s: Please use omap_dm_timer_request_by_cap/node()\n",
> + pr_warn("%s: Please use omap_dm_timer_request_by_node()\n",
> __func__);
> return NULL;
> }
> @@ -315,20 +305,6 @@ struct omap_dm_timer *omap_dm_timer_request_specific(int id)
> return _omap_dm_timer_request(REQUEST_BY_ID, &id);
> }
>
> -/**
> - * omap_dm_timer_request_by_cap - Request a timer by capability
> - * @cap: Bit mask of capabilities to match
> - *
> - * Find a timer based upon capabilities bit mask. Callers of this function
> - * should use the definitions found in the plat/dmtimer.h file under the
> - * comment "timer capabilities used in hwmod database". Returns pointer to
> - * timer handle on success and a NULL pointer on failure.
> - */
> -struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
> -{
> - return _omap_dm_timer_request(REQUEST_BY_CAP, &cap);
> -}
> -
> /**
> * omap_dm_timer_request_by_node - Request a timer by device-tree node
> * @np: Pointer to device-tree timer node
> @@ -336,7 +312,7 @@ struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap)
> * Request a timer based upon a device node pointer. Returns pointer to
> * timer handle on success and a NULL pointer on failure.
> */
> -struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
> +static struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
> {
> if (!np)
> return NULL;
> @@ -344,7 +320,7 @@ struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np)
> return _omap_dm_timer_request(REQUEST_BY_NODE, np);
> }
>
> -int omap_dm_timer_free(struct omap_dm_timer *timer)
> +static int omap_dm_timer_free(struct omap_dm_timer *timer)
> {
> if (unlikely(!timer))
> return -EINVAL;
> @@ -424,7 +400,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
>
> #else
>
> -struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
> +static struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer)
> {
> if (timer && !IS_ERR(timer->fclk))
> return timer->fclk;
> @@ -440,18 +416,7 @@ __u32 omap_dm_timer_modify_idlect_mask(__u32 inputmask)
>
> #endif
>
> -int omap_dm_timer_trigger(struct omap_dm_timer *timer)
> -{
> - if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
> - pr_err("%s: timer not available or enabled.\n", __func__);
> - return -EINVAL;
> - }
> -
> - omap_dm_timer_write_reg(timer, OMAP_TIMER_TRIGGER_REG, 0);
> - return 0;
> -}
> -
> -int omap_dm_timer_start(struct omap_dm_timer *timer)
> +static int omap_dm_timer_start(struct omap_dm_timer *timer)
> {
> u32 l;
>
> @@ -471,7 +436,7 @@ int omap_dm_timer_start(struct omap_dm_timer *timer)
> return 0;
> }
>
> -int omap_dm_timer_stop(struct omap_dm_timer *timer)
> +static int omap_dm_timer_stop(struct omap_dm_timer *timer)
> {
> unsigned long rate = 0;
>
> @@ -556,8 +521,8 @@ int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source)
> return ret;
> }
>
> -int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
> - unsigned int load)
> +static int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
> + unsigned int load)
> {
> u32 l;
>
> @@ -581,37 +546,8 @@ int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload,
> return 0;
> }
>
> -/* Optimized set_load which removes costly spin wait in timer_start */
> -int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload,
> - unsigned int load)
> -{
> - u32 l;
> -
> - if (unlikely(!timer))
> - return -EINVAL;
> -
> - omap_dm_timer_enable(timer);
> -
> - l = omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
> - if (autoreload) {
> - l |= OMAP_TIMER_CTRL_AR;
> - omap_dm_timer_write_reg(timer, OMAP_TIMER_LOAD_REG, load);
> - } else {
> - l &= ~OMAP_TIMER_CTRL_AR;
> - }
> - l |= OMAP_TIMER_CTRL_ST;
> -
> - __omap_dm_timer_load_start(timer, l, load, timer->posted);
> -
> - /* Save the context */
> - timer->context.tclr = l;
> - timer->context.tldr = load;
> - timer->context.tcrr = load;
> - return 0;
> -}
> -
> -int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
> - unsigned int match)
> +static int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
> + unsigned int match)
> {
> u32 l;
>
> @@ -634,8 +570,8 @@ int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable,
> return 0;
> }
>
> -int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
> - int toggle, int trigger)
> +static int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
> + int toggle, int trigger)
> {
> u32 l;
>
> @@ -659,7 +595,8 @@ int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on,
> return 0;
> }
>
> -int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
> +static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
> + int prescaler)
> {
> u32 l;
>
> @@ -681,8 +618,8 @@ int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
> return 0;
> }
>
> -int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
> - unsigned int value)
> +static int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
> + unsigned int value)
> {
> if (unlikely(!timer))
> return -EINVAL;
> @@ -704,7 +641,7 @@ int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer,
> *
> * Disables the specified timer interrupts for a timer.
> */
> -int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
> +static int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
> {
> u32 l = mask;
>
> @@ -727,7 +664,7 @@ int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask)
> return 0;
> }
>
> -unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
> +static unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
> {
> unsigned int l;
>
> @@ -741,7 +678,7 @@ unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer)
> return l;
> }
>
> -int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
> +static int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
> {
> if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev)))
> return -EINVAL;
> @@ -751,7 +688,7 @@ int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value)
> return 0;
> }
>
> -unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
> +static unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
> {
> if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
> pr_err("%s: timer not iavailable or enabled.\n", __func__);
> @@ -761,7 +698,7 @@ unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer)
> return __omap_dm_timer_read_counter(timer, timer->posted);
> }
>
> -int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
> +static int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
> {
> if (unlikely(!timer || pm_runtime_suspended(&timer->pdev->dev))) {
> pr_err("%s: timer not available or enabled.\n", __func__);
> @@ -775,22 +712,6 @@ int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value)
> return 0;
> }
>
> -int omap_dm_timers_active(void)
> -{
> - struct omap_dm_timer *timer;
> -
> - list_for_each_entry(timer, &omap_timer_list, node) {
> - if (!timer->reserved)
> - continue;
> -
> - if (omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG) &
> - OMAP_TIMER_CTRL_ST) {
> - return 1;
> - }
> - }
> - return 0;
> -}
> -
> static const struct of_device_id omap_timer_match[];
>
> /**
> diff --git a/include/clocksource/dmtimer.h b/include/clocksource/dmtimer.h
> index 862ad62dab9d..63d6ec0747d9 100644
> --- a/include/clocksource/dmtimer.h
> +++ b/include/clocksource/dmtimer.h
> @@ -124,40 +124,14 @@ struct omap_dm_timer {
> struct list_head node;
> };
>
> -int omap_dm_timer_reserve_systimer(int id);
> -struct omap_dm_timer *omap_dm_timer_request(void);
> -struct omap_dm_timer *omap_dm_timer_request_specific(int timer_id);
> -struct omap_dm_timer *omap_dm_timer_request_by_cap(u32 cap);
> -struct omap_dm_timer *omap_dm_timer_request_by_node(struct device_node *np);
> -int omap_dm_timer_free(struct omap_dm_timer *timer);
> void omap_dm_timer_enable(struct omap_dm_timer *timer);
> void omap_dm_timer_disable(struct omap_dm_timer *timer);
>
> int omap_dm_timer_get_irq(struct omap_dm_timer *timer);
>
> u32 omap_dm_timer_modify_idlect_mask(u32 inputmask);
> -struct clk *omap_dm_timer_get_fclk(struct omap_dm_timer *timer);
> -
> -int omap_dm_timer_trigger(struct omap_dm_timer *timer);
> -int omap_dm_timer_start(struct omap_dm_timer *timer);
> -int omap_dm_timer_stop(struct omap_dm_timer *timer);
>
> int omap_dm_timer_set_source(struct omap_dm_timer *timer, int source);
> -int omap_dm_timer_set_load(struct omap_dm_timer *timer, int autoreload, unsigned int value);
> -int omap_dm_timer_set_load_start(struct omap_dm_timer *timer, int autoreload, unsigned int value);
> -int omap_dm_timer_set_match(struct omap_dm_timer *timer, int enable, unsigned int match);
> -int omap_dm_timer_set_pwm(struct omap_dm_timer *timer, int def_on, int toggle, int trigger);
> -int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler);
> -
> -int omap_dm_timer_set_int_enable(struct omap_dm_timer *timer, unsigned int value);
> -int omap_dm_timer_set_int_disable(struct omap_dm_timer *timer, u32 mask);
> -
> -unsigned int omap_dm_timer_read_status(struct omap_dm_timer *timer);
> -int omap_dm_timer_write_status(struct omap_dm_timer *timer, unsigned int value);
> -unsigned int omap_dm_timer_read_counter(struct omap_dm_timer *timer);
> -int omap_dm_timer_write_counter(struct omap_dm_timer *timer, unsigned int value);
> -
> -int omap_dm_timers_active(void);
>
> /*
> * Do not use the defines below, they are not needed. They should be only
>
^ permalink raw reply
* [PATCH] clk: sunxi: sun9i-mmc: Implement reset callback for reset controls
From: Maxime Ripard @ 2017-12-19 8:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218210709.GY7997@codeaurora.org>
On Mon, Dec 18, 2017 at 01:07:09PM -0800, Stephen Boyd wrote:
> On 12/18, Chen-Yu Tsai wrote:
> > Our MMC host driver now issues a reset, instead of just deasserting
> > the reset control, since commit c34eda69ad4c ("mmc: sunxi: Reset the
> > device at probe time"). The sun9i-mmc clock driver does not support
> > this, and will fail, which results in MMC not probing.
> >
> > This patch implements the reset callback by asserting the reset control,
> > then deasserting it after a small delay.
> >
> > Fixes: 7a6fca879f59 ("clk: sunxi: Add driver for A80 MMC config clocks/resets")
> > Cc: <stable@vger.kernel.org> # 4.14.x
> > Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> > ---
>
> Did you want us to pick this up into clk-fixes? It seems to be
> causing MMC to not work for some time? That sounds annoying
> enough.
That would be great, thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [PATCH 2/2] clocksource: timer-dm: Check prescaler value
From: Keerthy @ 2017-12-19 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218113153.GB18637@lenoch>
On Monday 18 December 2017 05:01 PM, Ladislav Michl wrote:
> Invalid prescaler value is silently ignored. Fix that
> by returning -EINVAL in such case. As invalid value
> disabled use of the prescaler, use -1 explicitely for
> that purpose.
Thanks. I will post this as part of my migration series.
>
> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> ---
> drivers/clocksource/timer-dm.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clocksource/timer-dm.c b/drivers/clocksource/timer-dm.c
> index ec3a28c90c70..95cd98be8541 100644
> --- a/drivers/clocksource/timer-dm.c
> +++ b/drivers/clocksource/timer-dm.c
> @@ -609,6 +609,9 @@ static int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer,
> if (prescaler >= 0x00 && prescaler <= 0x07) {
> l |= OMAP_TIMER_CTRL_PRE;
> l |= prescaler << 2;
> + } else {
> + if (prescaler != -1)
> + return -EINVAL;
> }
> omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
>
>
^ permalink raw reply
* [PATCH 3/8] media: v4l2-async: simplify v4l2_async_subdev structure
From: Sakari Ailus @ 2017-12-19 8:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <014b64d13c8b9d516afc3319a9de1a97b2a845de.1513625884.git.mchehab@s-opensource.com>
On Mon, Dec 18, 2017 at 05:53:57PM -0200, Mauro Carvalho Chehab wrote:
> The V4L2_ASYNC_MATCH_FWNODE match criteria requires just one
> struct to be filled (struct fwnode_handle). The V4L2_ASYNC_MATCH_DEVNAME
> match criteria requires just a device name.
>
> So, it doesn't make sense to enclose those into structs,
> as the criteria can go directly into the union.
>
> That makes easier to document it, as we don't need to document
> weird senseless structs.
>
> At drivers, this makes even clearer about the match criteria.
>
> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@s-opensource.com>
I'm not sure this is needed but it doesn't break anything either.
Feel free to add:
Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
--
Sakari Ailus
e-mail: sakari.ailus at iki.fi
^ permalink raw reply
* [PATCH v5 7/8] pwm: pwm-omap-dmtimer: Adapt driver to utilize dmtimer pdata ops
From: Keerthy @ 2017-12-19 8:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b780d238-91fa-035e-65dc-4e8ee607f6a7@ti.com>
On Tuesday 19 December 2017 10:28 AM, Keerthy wrote:
>
>
> On Monday 18 December 2017 06:25 PM, Keerthy wrote:
>>
>>
>> On Monday 18 December 2017 03:01 PM, Ladislav Michl wrote:
>>> Keerthy,
>>>
>>> On Tue, Dec 12, 2017 at 11:42:16AM +0530, Keerthy wrote:
>>>> Adapt driver to utilize dmtimer pdata ops instead of pdata-quirks.
>>>>
>>>> Signed-off-by: Keerthy <j-keerthy@ti.com>
>>>> ---
>>>>
>>>> Changes in v4:
>>>>
>>>> * Switched to dev_get_platdata.
>>>
>>> Where do you expect dev.platform_data to be set? PWM driver is failing
>>> with:
>>> omap-dmtimer-pwm dmtimer-pwm: dmtimer pdata structure NULL
>>> omap-dmtimer-pwm: probe of dmtimer-pwm failed with error -22
>>>
>>> Which I fixed with patch bellow, to be able to test your patchset.
>>
>> Thanks! I will make the below patch part of my series.
>>
>>>
>>> Also I'm running a bit out of time, so I'll send few clean up
>>> patches and event capture code to get some feedback early.
>>>
>>> Regards,
>>> ladis
>>>
>>> diff --git a/drivers/clocksource/timer-dm.c b/drivers/clocksource/timer-dm.c
>>> index 39be39e6a8dd..d3d8a49cae0d 100644
>>> --- a/drivers/clocksource/timer-dm.c
>>> +++ b/drivers/clocksource/timer-dm.c
>>> @@ -773,6 +773,7 @@ static int omap_dm_timer_probe(struct platform_device *pdev)
>>> dev_err(dev, "%s: no platform data.\n", __func__);
>>> return -ENODEV;
>>> }
>>> + dev->platform_data = pdata;
>
> drivers/clocksource/timer-dm.c: In function 'omap_dm_timer_probe':
> drivers/clocksource/timer-dm.c:744:21: warning: assignment discards
> 'const' qualifier from pointer target type
>
> This cannot be done as we are assigning a const pointer to a non-const
> pointer.
>
> I will figure out a different way for this fix.
Ladis,
I fixed that:
diff --git a/drivers/clocksource/timer-dm.c b/drivers/clocksource/timer-dm.c
index 1cbd954..e58f555 100644
--- a/drivers/clocksource/timer-dm.c
+++ b/drivers/clocksource/timer-dm.c
@@ -807,17 +807,21 @@ static int omap_dm_timer_probe(struct
platform_device *pdev)
struct resource *mem, *irq;
struct device *dev = &pdev->dev;
const struct of_device_id *match;
- const struct dmtimer_platform_data *pdata;
+ struct dmtimer_platform_data *pdata;
int ret;
match = of_match_device(of_match_ptr(omap_timer_match), dev);
- pdata = match ? match->data : dev->platform_data;
+ pdata = match ? (struct dmtimer_platform_data *)match->data :
+ dev->platform_data;
if (!pdata && !dev->of_node) {
dev_err(dev, "%s: no platform data.\n", __func__);
return -ENODEV;
}
+ if (!dev->platform_data)
+ dev->platform_data = pdata;
+
irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
if (unlikely(!irq)) {
dev_err(dev, "%s: no IRQ resource.\n", __func__);
@@ -946,7 +950,7 @@ static int omap_dm_timer_remove(struct
platform_device *pdev)
.write_status = omap_dm_timer_write_status,
};
-static const struct dmtimer_platform_data omap3plus_pdata = {
+static struct dmtimer_platform_data omap3plus_pdata = {
.timer_errata = OMAP_TIMER_ERRATA_I103_I767,
.timer_ops = &dmtimer_ops,
};
Can you check at your end if this works for you?
>
>>>
>>> irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
>>> if (unlikely(!irq)) {
>>>
>>>>
>>>> Changes in v3:
>>>>
>>>> * Used of_find_platdata_by_node function to fetch platform
>>>> data for timer node.
>>>>
>>>> drivers/pwm/pwm-omap-dmtimer.c | 39 ++++++++++++++++++++++-----------------
>>>> 1 file changed, 22 insertions(+), 17 deletions(-)
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-omap" in
>> the body of a message to majordomo at vger.kernel.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>>
^ permalink raw reply related
* [PATCH] fix perl locale warnings in arch/arm/boot/
From: Masahiro Yamada @ 2017-12-19 8:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215201639.GA32042@amd>
2017-12-16 5:16 GMT+09:00 Pavel Machek <pavel@ucw.cz>:
> On Mon 2017-11-27 10:46:20, Pavel Machek wrote:
>>
>> Commit 429f7a062e3b5cf6fcf01eb00600cee5fe4d751f introduced perl into
>> arch/arm/boot/compressed/Makefile, which unfortunately leads to locale
>> warnings.
>>
>> Fix it by setting default locale.
>>
>> Signed-off-by: Pavel Machek <pavel@ucw.cz>
>
> RMK apparently can't be bothered to fix the stuff he broke. Can
> someone take the patch? Arm-soc? Linus? Andrew?
>
> Thanks,
> Pavel
Russell does not directly pick up patches from ML.
If you want him to apply your patch,
you need to put it in his patch tracker.
(patches at arm.linux.org.uk)
>> diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
>> index 45a6b9b..4656e98 100644
>> --- a/arch/arm/boot/compressed/Makefile
>> +++ b/arch/arm/boot/compressed/Makefile
>> @@ -118,7 +118,7 @@ asflags-y := -DZIMAGE
>>
>> # Supply kernel BSS size to the decompressor via a linker symbol.
>> KBSS_SZ = $(shell $(CROSS_COMPILE)nm $(obj)/../../../../vmlinux | \
>> - perl -e 'while (<>) { \
>> + LC_ALL=C perl -e 'while (<>) { \
>> $$bss_start=hex($$1) if /^([[:xdigit:]]+) B __bss_start$$/; \
>> $$bss_end=hex($$1) if /^([[:xdigit:]]+) B __bss_stop$$/; \
>> }; printf "%d\n", $$bss_end - $$bss_start;')
>>
>>
>
>
>
> --
> (english) http://www.livejournal.com/~pavelmachek
> (cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH v4 04/12] thermal: armada: Clarify control registers accesses
From: Miquel RAYNAL @ 2017-12-19 8:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219081941.utke7dh5bmmlub6h@sapphire.tkos.co.il>
Hi Baruch,
On Tue, 19 Dec 2017 10:19:41 +0200
Baruch Siach <baruch@tkos.co.il> wrote:
> Hi Miqu?l,
>
> On Tue, Dec 19, 2017 at 09:08:14AM +0100, Miquel RAYNAL wrote:
> > On Tue, 19 Dec 2017 07:51:54 +0200
> > Baruch Siach <baruch@tkos.co.il> wrote:
> > > On Tue, Dec 19, 2017 at 01:32:33AM +0100, Miquel RAYNAL wrote:
> > > > On Mon, 18 Dec 2017 22:35:42 +0200
> > > > Baruch Siach <baruch@tkos.co.il> wrote:
> > > > > On Mon, Dec 18, 2017 at 03:36:35PM +0100, Miquel Raynal
> > > > > wrote:
> > > > > > Bindings were incomplete for a long time by only exposing
> > > > > > one of the two available control registers. To ease the
> > > > > > migration to the full bindings (already in use for the
> > > > > > Armada 375 SoC), rename the pointers for clarification.
> > > > > > This way, it will only be needed to add another pointer to
> > > > > > access the other control register when the time comes.
> > > > > >
> > > > > > This avoids dangerous situations where the offset 0 of the
> > > > > > control area can be either one register or the other
> > > > > > depending on the bindings used. After this change, device
> > > > > > trees of other SoCs could be migrated to the "full"
> > > > > > bindings if they may benefit from features from the
> > > > > > unaccessible register, without any change in the driver.
> > > > > >
> > > > > > Signed-off-by: Miquel Raynal
> > > > > > <miquel.raynal@free-electrons.com> Reviewed-by: Gregory
> > > > > > CLEMENT <gregory.clement@free-electrons.com> ---
> > > > >
> > > > > [...]
> > > > >
> > > > > > + /*
> > > > > > + * Legacy DT bindings only described "control1"
> > > > > > register (also referred
> > > > > > + * as "control MSB" on old documentation). New
> > > > > > bindings cover
> > > > > > + * "control0/control LSB" and "control1/control
> > > > > > MSB" registers within
> > > > > > + * the same resource, which is then of size 8
> > > > > > instead of 4.
> > > > > > + */
> > > > > > + if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
> > > > > > + /* ->control0 unavailable in this
> > > > > > configuration */
> > > > > > + priv->control1 = control +
> > > > > > LEGACY_CONTROL1_OFFSET;
> > > > > > + } else {
> > > > > > + priv->control0 = control + CONTROL0_OFFSET;
> > > > > > + priv->control1 = control + CONTROL1_OFFSET;
> > > > > > + }
> > > > >
> > > > > The needs_control0 field that you mentioned in the cover page
> > > > > is missing here.
> > > >
> > > > Yes, at this point nobody actually *needs* control0 so the
> > > > limitation is added with the patch that introduce ap806 support
> > > > as it is the first compatible that needs both control0 and
> > > > control1 to work correctly. Does this bother you?
> > >
> > > No. It is just that we agreed to have a verification here that the
> > > size of the control registers resource matches the binding. I
> > > thought that the needs_control0 field that you mention in the
> > > cover page is meant to implement that.
> >
> > That is absolutely right, but at this point in the series, the
> > supported compatible strings are
> > "marvell,armada[370|375|38x|xp]-thermal". All of them can use both
> > bindings so I don't see the point to have a needs_control0 field in
> > this patch. It is introduced in the next patch that adds support
> > for ap806 by only supporting the new bindings though.
>
> OK. Makes sense.
>
> > > necessary. It would just make sure that no one introduces a DT
> > > with the wrong resource size.
> >
> > Not sure I understand what exactly you wanna check, can you
> > give me an example?
>
> I wrote that before it occurred to me that we can use the control
> registers size the distinguish between the old binding and the new
> one.
>
> I still think it would be nice to add needs_control0=true to
> armada375_data, for consistency with the ap806 and cp110.
Oh that is right, I forgot about that. I will add it and move the
need_control0 boolean to this patch.
Thank you,
Miqu?l
>
> baruch
>
--
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v4 04/12] thermal: armada: Clarify control registers accesses
From: Baruch Siach @ 2017-12-19 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219090814.3a53ec3d@xps13>
Hi Miqu?l,
On Tue, Dec 19, 2017 at 09:08:14AM +0100, Miquel RAYNAL wrote:
> On Tue, 19 Dec 2017 07:51:54 +0200
> Baruch Siach <baruch@tkos.co.il> wrote:
> > On Tue, Dec 19, 2017 at 01:32:33AM +0100, Miquel RAYNAL wrote:
> > > On Mon, 18 Dec 2017 22:35:42 +0200
> > > Baruch Siach <baruch@tkos.co.il> wrote:
> > > > On Mon, Dec 18, 2017 at 03:36:35PM +0100, Miquel Raynal wrote:
> > > > > Bindings were incomplete for a long time by only exposing one of
> > > > > the two available control registers. To ease the migration to
> > > > > the full bindings (already in use for the Armada 375 SoC),
> > > > > rename the pointers for clarification. This way, it will only
> > > > > be needed to add another pointer to access the other control
> > > > > register when the time comes.
> > > > >
> > > > > This avoids dangerous situations where the offset 0 of the
> > > > > control area can be either one register or the other depending
> > > > > on the bindings used. After this change, device trees of other
> > > > > SoCs could be migrated to the "full" bindings if they may
> > > > > benefit from features from the unaccessible register, without
> > > > > any change in the driver.
> > > > >
> > > > > Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
> > > > > Reviewed-by: Gregory CLEMENT
> > > > > <gregory.clement@free-electrons.com> ---
> > > >
> > > > [...]
> > > >
> > > > > + /*
> > > > > + * Legacy DT bindings only described "control1"
> > > > > register (also referred
> > > > > + * as "control MSB" on old documentation). New bindings
> > > > > cover
> > > > > + * "control0/control LSB" and "control1/control MSB"
> > > > > registers within
> > > > > + * the same resource, which is then of size 8 instead
> > > > > of 4.
> > > > > + */
> > > > > + if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
> > > > > + /* ->control0 unavailable in this
> > > > > configuration */
> > > > > + priv->control1 = control +
> > > > > LEGACY_CONTROL1_OFFSET;
> > > > > + } else {
> > > > > + priv->control0 = control + CONTROL0_OFFSET;
> > > > > + priv->control1 = control + CONTROL1_OFFSET;
> > > > > + }
> > > >
> > > > The needs_control0 field that you mentioned in the cover page is
> > > > missing here.
> > >
> > > Yes, at this point nobody actually *needs* control0 so the
> > > limitation is added with the patch that introduce ap806 support as
> > > it is the first compatible that needs both control0 and control1 to
> > > work correctly. Does this bother you?
> >
> > No. It is just that we agreed to have a verification here that the
> > size of the control registers resource matches the binding. I thought
> > that the needs_control0 field that you mention in the cover page is
> > meant to implement that.
>
> That is absolutely right, but at this point in the series, the supported
> compatible strings are "marvell,armada[370|375|38x|xp]-thermal". All of
> them can use both bindings so I don't see the point to have a
> needs_control0 field in this patch. It is introduced in the next patch
> that adds support for ap806 by only supporting the new bindings
> though.
OK. Makes sense.
> > necessary. It would just make sure that no one introduces a DT with
> > the wrong resource size.
>
> Not sure I understand what exactly you wanna check, can you
> give me an example?
I wrote that before it occurred to me that we can use the control registers
size the distinguish between the old binding and the new one.
I still think it would be nice to add needs_control0=true to armada375_data,
for consistency with the ap806 and cp110.
baruch
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
^ permalink raw reply
* [PATCH 23/25] arm: da8: dts: Remove leading 0x and 0s from bindings notation
From: Sekhar Nori @ 2017-12-19 8:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215124657.31052-1-malat@debian.org>
On Friday 15 December 2017 06:16 PM, Mathieu Malaterre wrote:
> Improve the DTS files by removing all the leading "0x" and zeros to fix the
> following dtc warnings:
>
> Warning (unit_address_format): Node /XXX unit name should not have leading "0x"
>
> and
>
> Warning (unit_address_format): Node /XXX unit name should not have leading 0s
>
> Converted using the following command:
>
> find . -type f \( -iname *.dts -o -iname *.dtsi \) -exec sed -i -e "s/@\([0-9a-fA-FxX\.;:#]+\)\s*{/@\L\1 {/g" -e "s/@0x\(.*\) {/@\1 {/g" -e "s/@0+\(.*\) {/@\1 {/g" {} +^C
>
> For simplicity, two sed expressions were used to solve each warnings separately.
>
> To make the regex expression more robust a few other issues were resolved,
> namely setting unit-address to lower case, and adding a whitespace before the
> the opening curly brace:
>
> https://elinux.org/Device_Tree_Linux#Linux_conventions
>
> This will solve as a side effect warning:
>
> Warning (simple_bus_reg): Node /XXX@<UPPER> simple-bus unit address format error, expected "<lower>"
>
> This is a follow up to commit 4c9847b7375a ("dt-bindings: Remove leading 0x from bindings notation")
>
> Reported-by: David Daney <ddaney@caviumnetworks.com>
> Suggested-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Mathieu Malaterre <malat@debian.org>
Applied to v4.16/fixes-non-critical with some headline adjustments.
The subject prefix we use for this file is "ARM: dts: da850-lcdk:". You
can check that with 'git log --oneline'
Also, you are not fixing bindings notation here, but the actual device
tree source itself. So:
"
ARM: dts: da850-lcdk: Remove leading 0x and 0s from unit address
"
Thanks for the patch!
Sekhar
^ permalink raw reply
* [PATCH v4 04/12] thermal: armada: Clarify control registers accesses
From: Miquel RAYNAL @ 2017-12-19 8:08 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219055154.f23leaob3zndmmqo@sapphire.tkos.co.il>
On Tue, 19 Dec 2017 07:51:54 +0200
Baruch Siach <baruch@tkos.co.il> wrote:
> Hi Miqu?l,
>
> On Tue, Dec 19, 2017 at 01:32:33AM +0100, Miquel RAYNAL wrote:
> > On Mon, 18 Dec 2017 22:35:42 +0200
> > Baruch Siach <baruch@tkos.co.il> wrote:
> > > On Mon, Dec 18, 2017 at 03:36:35PM +0100, Miquel Raynal wrote:
> > > > Bindings were incomplete for a long time by only exposing one of
> > > > the two available control registers. To ease the migration to
> > > > the full bindings (already in use for the Armada 375 SoC),
> > > > rename the pointers for clarification. This way, it will only
> > > > be needed to add another pointer to access the other control
> > > > register when the time comes.
> > > >
> > > > This avoids dangerous situations where the offset 0 of the
> > > > control area can be either one register or the other depending
> > > > on the bindings used. After this change, device trees of other
> > > > SoCs could be migrated to the "full" bindings if they may
> > > > benefit from features from the unaccessible register, without
> > > > any change in the driver.
> > > >
> > > > Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
> > > > Reviewed-by: Gregory CLEMENT
> > > > <gregory.clement@free-electrons.com> ---
> > >
> > > [...]
> > >
> > > > + /*
> > > > + * Legacy DT bindings only described "control1"
> > > > register (also referred
> > > > + * as "control MSB" on old documentation). New bindings
> > > > cover
> > > > + * "control0/control LSB" and "control1/control MSB"
> > > > registers within
> > > > + * the same resource, which is then of size 8 instead
> > > > of 4.
> > > > + */
> > > > + if (resource_size(res) == LEGACY_CONTROL_MEM_LEN) {
> > > > + /* ->control0 unavailable in this
> > > > configuration */
> > > > + priv->control1 = control +
> > > > LEGACY_CONTROL1_OFFSET;
> > > > + } else {
> > > > + priv->control0 = control + CONTROL0_OFFSET;
> > > > + priv->control1 = control + CONTROL1_OFFSET;
> > > > + }
> > >
> > > The needs_control0 field that you mentioned in the cover page is
> > > missing here.
> >
> > Yes, at this point nobody actually *needs* control0 so the
> > limitation is added with the patch that introduce ap806 support as
> > it is the first compatible that needs both control0 and control1 to
> > work correctly. Does this bother you?
>
> No. It is just that we agreed to have a verification here that the
> size of the control registers resource matches the binding. I thought
> that the needs_control0 field that you mention in the cover page is
> meant to implement that.
That is absolutely right, but at this point in the series, the supported
compatible strings are "marvell,armada[370|375|38x|xp]-thermal". All of
them can use both bindings so I don't see the point to have a
needs_control0 field in this patch. It is introduced in the next patch
that adds support for ap806 by only supporting the new bindings
though.
> necessary. It would just make sure that no one introduces a DT with
> the wrong resource size.
Not sure I understand what exactly you wanna check, can you
give me an example?
Thank you,
Miqu?l
>
> baruch
>
--
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v3 6/6] arm: dts: sun8i: h3-h8: ir register size should be the whole memory block
From: Philipp Rossak @ 2017-12-19 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219080747.4507-1-embed3d@gmail.com>
The size of the register should be the size of the whole memory block,
not just the registers, that are needed.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index 8d40c00d64bb..a9caeda4a574 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -674,7 +674,7 @@
clock-names = "apb", "ir";
resets = <&r_ccu RST_APB0_IR>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x01f02000 0x40>;
+ reg = <0x01f02000 0x400>;
status = "disabled";
};
--
2.11.0
^ permalink raw reply related
* [PATCH v3 5/6] arm: dts: sun8i: a83t: bananapi-m3: Enable IR controller
From: Philipp Rossak @ 2017-12-19 8:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219080747.4507-1-embed3d@gmail.com>
The Bananapi M3 has an onboard IR receiver.
This enables the onboard IR receiver subnode.
Unlike the other IR receivers this one needs a base clock frequency
of 3000000 Hz (3 MHz), to be able to work.
Signed-off-by: Philipp Rossak <embed3d@gmail.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..ffc6445fd281 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -82,6 +82,13 @@
};
};
+&cir {
+ pinctrl-names = "default";
+ pinctrl-0 = <&cir_pins>;
+ clock-frequency = <3000000>;
+ status = "okay";
+};
+
&ehci0 {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
--
2.11.0
^ permalink raw reply related
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