* [PATCH 6/6] ARM: imx_v6_v7_defconfig: Enable Dialog Semicondocter DA9062 driver
From: Fabio Estevam @ 2017-12-19 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-7-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> The phyCORE-i.MX 6 uses the DA9062/63 PMIC, RTC and Watchdog driver.
>
> Enable this option by default.
"these options"
>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH] ARM: dts: add minimal device tree for compute model 3
From: Stefan Wahren @ 2017-12-19 17:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171124121813.11318-1-kernel@martin.sperl.org>
Hi Martin,
> kernel at martin.sperl.org hat am 24. November 2017 um 13:18 geschrieben:
>
>
> From: Martin Sperl <kernel@martin.sperl.org>
>
> Add a minimal working device tree for the compute model 3
> for both arm and arm64.
>
just a note before you send a V2. Recently i looked at the CM datasheet (revision 1.0) and noticed on the block diagram (page 8) that the CM3 eMMC I/O voltage is fixed at 1.8 Volt (doesn't apply to CM3 lite). Providing a fixed regulator for vmmc/vqmmc-supply [1] would give the MMC core the chance to figure out the right voltage.
[1] - http://elixir.free-electrons.com/linux/latest/source/Documentation/devicetree/bindings/mmc/mmc.txt
^ permalink raw reply
* [PATCH 00/10] arm64: 52-bit physical address support
From: Kristina Martsenko @ 2017-12-19 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214175259.GA4219@zareason>
On 14/12/17 17:52, Bob Picco wrote:
> Kristina Martsenko wrote: [Wed Dec 13 2017, 12:07:15PM EST]
>> Hi,
>>
>> This series adds 52-bit physical address space support to arm64, up from
>> the current 48 bits. This is an ARMv8.2 feature (ARMv8.2-LPA).
>>
>> The series is based on 4.15-rc3. It has been lightly tested on an ARM
>> Fast Model. There's still some cases and areas to think through, as well
>> as more testing to do.
>>
>> Patches for SMMU 52-bit PA support have been sent separately [1]. A GIC
>> ITS patch has already been merged [2]. ARMv8.2 also allows 52-bit IPA,
>> but support for that is not part of this series.
>>
>> This version mostly addresses various review comments received.
>>
>> Changes from RFC:
>> - Split kconfig symbol into two patches, to enable 52-bit PA at the end
>> - Patch #3: Changed phys_to_ttbr to use a macro, added an #include
>> - Patch #4: Changed phys_to_pte to use a macro
>> - Patch #6: Replaced __phys_to_pte with __phys_to_pte_val (same for
>> pmd/pud/pgd)
>> - Patch #6: Changed __phys_to_pte_val, __pte_to_phys, and
>> pgtable-hwdef.h macros
>> - Patches #5, #6: Removed kvm_extended_idmap_pgd, inlined its code,
>> moved the comment
>> - Patch #5: Added pfn_pud definition (to make the kernel build on that
>> commit)
>>
>> Thanks,
>> Kristina
>>
>> [1] https://www.spinics.net/lists/arm-kernel/msg619040.html
>> [2] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=30ae9610d275f8f03f5bf7612ce71d8af6fc400b
>>
>>
>> Kristina Martsenko (10):
>> arm64: add kconfig symbol to configure physical address size
>> arm64: limit PA size to supported range
>> arm64: handle 52-bit addresses in TTBR
>> arm64: head.S: handle 52-bit PAs in PTEs in early page table setup
>> arm64: don't open code page table entry creation
>> arm64: handle 52-bit physical addresses in page table entries
>> arm64: increase PHYS_MASK to 52 bits
>> arm64: increase sparsemem MAX_PHYSMEM_BITS to 52
>> arm64: allow ID map to be extended to 52 bits
>> arm64: enable 52-bit physical address support
>>
>> arch/arm/include/asm/kvm_mmu.h | 7 ++
>> arch/arm64/Kconfig | 29 ++++++++
>> arch/arm64/include/asm/assembler.h | 31 ++++++++-
>> arch/arm64/include/asm/kvm_mmu.h | 21 +++++-
>> arch/arm64/include/asm/mmu_context.h | 16 ++++-
>> arch/arm64/include/asm/pgalloc.h | 6 +-
>> arch/arm64/include/asm/pgtable-hwdef.h | 19 +++++-
>> arch/arm64/include/asm/pgtable.h | 53 ++++++++++++---
>> arch/arm64/include/asm/sparsemem.h | 2 +-
>> arch/arm64/include/asm/sysreg.h | 8 +++
>> arch/arm64/kernel/head.S | 118 +++++++++++++++++++++------------
>> arch/arm64/kernel/hibernate-asm.S | 12 ++--
>> arch/arm64/kernel/hibernate.c | 5 +-
>> arch/arm64/kvm/hyp-init.S | 26 ++++----
>> arch/arm64/kvm/hyp/s2-setup.c | 2 +
>> arch/arm64/mm/mmu.c | 15 +++--
>> arch/arm64/mm/pgd.c | 8 +++
>> arch/arm64/mm/proc.S | 19 +++---
>> virt/kvm/arm/arm.c | 2 +-
>> virt/kvm/arm/mmu.c | 12 ++--
>> 20 files changed, 302 insertions(+), 109 deletions(-)
>>
>> --
>> 2.1.4
> Hi Kristina,
>
> I boot tested but on VM and had a couple issues. I will examine and share
> should the issues be of value.
> Tested-by: Bob Picco <bob.picco@oracle.com>
Thanks for testing! I assume it was on a VM with less than 52 bits of
PA? In any case, let me know if you find any issues.
> I reviewed and thank you. Your effort caused me to return to some code
> examined/learned during the last few months.
> Reviewed-by: Bob Picco <bob.picco@oracle.com>
Thanks for reviewing! Hope it was useful.
Kristina
^ permalink raw reply
* [PATCH 5/6] ARM: dts: imx6: Add support for phyBOARD-Mira with i.MX 6QuadPlus
From: Fabio Estevam @ 2017-12-19 17:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-6-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> +/ {
> + model = "PHYTEC phyBOARD-Mira QuadPlus Carrier-Board with NAND";
> + compatible = "phytec,imx6qp-pbac06-nand", "phytec,imx6qp-pbac06",
> + "phytec,imx6qdl-pcm058", "fsl,imx6qp";
> +
> + aliases {
> + ipu1 = &ipu2;
> + };
Same comment as previous patch. You can drop this alias.
^ permalink raw reply
* [PATCH 4/6] ARM: dts: imx6: Add support for phxBOARD-Mira i.MX 6 DualLight/Solo RDK
From: Fabio Estevam @ 2017-12-19 17:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-5-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> From: Christian Hemp <c.hemp@phytec.de>
>
> Add support for the PHYTEC phyBOARD-Mira Low-Cost Rapid Development Kit
> with i.MX 6DualLight/Solo with NAND.
>
> Following interfaces are supported:
> - 100 MBit Ethernet
> - USB Host
> - RS232
> - HDMI
>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> Signed-off-by: Stefan Christ <s.christ@phytec.de>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH 3/6] ARM: dts: imx6: Add support for phyBOARD-Mira i.MX 6Quad/Dual RDK
From: Fabio Estevam @ 2017-12-19 17:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-4-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> +/ {
> + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with eMMC";
> + compatible = "phytec,imx6q-pbac06-emmc", "phytec,imx6q-pbac06",
> + "phytec,imx6qdl-pcm058", "fsl,imx6q";
> +
> + aliases {
> + ipu1 = &ipu2;
> + };
This alias is not needed as it is part of imx6q.dtsi.
> +/ {
> + model = "PHYTEC phyBOARD-Mira Quad Carrier-Board with NAND";
> + compatible = "phytec,imx6q-pbac06-nand", "phytec,imx6q-pbac06",
> + "phytec,imx6qdl-pcm058", "fsl,imx6q";
> +
> + aliases {
> + ipu1 = &ipu2;
> + };
Ditto.
^ permalink raw reply
* pwm: atmel-tcb: Delete an error message for a failed memory allocation in atmel_tcb_pwm_probe()
From: SF Markus Elfring @ 2017-12-19 17:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6d607786-4c1b-0949-0768-1bc0a4749fd5@microchip.com>
>> Omit an extra message for a memory allocation failure in this function.
>>
>> This issue was detected by using the Coccinelle software.
>
> Can you point which coccinelle script highlited this issue?
Not directly (so far).
I constructed an approach for the semantic patch language based on
information from the script ?checkpatch.pl?.
Would you like to improve it any ways?
Regards,
Markus
^ permalink raw reply
* [PATCH 2/6] ARM: dts: imx6: Add initial support for phyBOARD-Mira
From: Fabio Estevam @ 2017-12-19 17:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-3-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> + reg_pcie: regulator-pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie_reg>;
> + compatible = "regulator-fixed";
> + regulator-name = "mPCIe_1V5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + regulator-always-on;
Instead of using 'regulator-always-on' here, you could use:
vpcie-supply = <®_pcie>;
under the &pcie node
> + panel {
> + compatible = "auo,g104sn02";
I could not find this compatible in linux-next.
> + i2c_rtc: rtc at 68 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc_int>;
> + compatible = "mc,rv4162";
I could not find this compatible in linux-next.
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio2 25 GPIO_ACTIVE_HIGH>;
The imx driver ignores the polarity and it is active high only when
'reset-gpio-active-high' property is present.
The correct here would be: reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + fsl,uart-has-rtscts;
uart-has-rtscts, please.
^ permalink raw reply
* [PATCH 1/6] ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM
From: Fabio Estevam @ 2017-12-19 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698588-13325-2-git-send-email-s.riedmueller@phytec.de>
On Tue, Dec 19, 2017 at 1:49 PM, Stefan Riedmueller
<s.riedmueller@phytec.de> wrote:
> +
> +/ {
> + model = "PHYTEC phyCORE-i.MX 6";
> + compatible = "phytec,imx6qdl-pcm058", "fsl,imx6qdl";
> +
> + aliases {
> + ipu0 = &ipu1;
Is this alias needed?
> + rtc1 = &da9062_rtc;
> + rtc2 = &snvs_rtc;
> + };
> +
> + /*
> + * Set the minimum memory size here and
> + * let the bootloader set the real size.
> + */
> + memory {
memory at 10000000 so that you don't get warnings when building with W=1.
Also, please build W=1 and make sure to not introduce any build
warning in this series.
> +&i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + eeprom: eeprom at 50 {
> + compatible = "cat,24c32";
This compatible is not documented.
^ permalink raw reply
* [PATCH net 3/3] net: mvneta: eliminate wrong call to handle rx descriptor error
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219165947.28516-1-gregory.clement@free-electrons.com>
From: Yelena Krivosheev <yelena@marvell.com>
There are few reasons in mvneta_rx_swbm() function when received packet
is dropped. mvneta_rx_error() should be called only if error bit [16]
is set in rx descriptor.
[gregory.clement at free-electrons.com: add fixes tag]
Cc: stable at vger.kernel.org
Fixes: dc35a10f68d3 ("net: mvneta: bm: add support for hardware buffer management")
Signed-off-by: Yelena Krivosheev <yelena@marvell.com>
Tested-by: Dmitri Epshtein <dima@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 1e0835655c93..a539263cd79c 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1962,9 +1962,9 @@ static int mvneta_rx_swbm(struct mvneta_port *pp, int rx_todo,
if (!mvneta_rxq_desc_is_first_last(rx_status) ||
(rx_status & MVNETA_RXD_ERR_SUMMARY)) {
+ mvneta_rx_error(pp, rx_desc);
err_drop_frame:
dev->stats.rx_errors++;
- mvneta_rx_error(pp, rx_desc);
/* leave the descriptor untouched */
continue;
}
--
2.15.1
^ permalink raw reply related
* [PATCH net 2/3] net: mvneta: use proper rxq_number in loop on rx queues
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219165947.28516-1-gregory.clement@free-electrons.com>
From: Yelena Krivosheev <yelena@marvell.com>
When adding the RX queue association with each CPU, a typo was made in
the mvneta_cleanup_rxqs() function. This patch fixes it.
[gregory.clement at free-electrons.com: add commit log and fixes tag]
Cc: stable at vger.kernel.org
Fixes: 2dcf75e2793c ("net: mvneta: Associate RX queues with each CPU")
Signed-off-by: Yelena Krivosheev <yelena@marvell.com>
Tested-by: Dmitri Epshtein <dima@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index 16b2bfb2cf51..1e0835655c93 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3015,7 +3015,7 @@ static void mvneta_cleanup_rxqs(struct mvneta_port *pp)
{
int queue;
- for (queue = 0; queue < txq_number; queue++)
+ for (queue = 0; queue < rxq_number; queue++)
mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
}
--
2.15.1
^ permalink raw reply related
* [PATCH net 1/3] net: mvneta: clear interface link status on port disable
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219165947.28516-1-gregory.clement@free-electrons.com>
From: Yelena Krivosheev <yelena@marvell.com>
When port connect to PHY in polling mode (with poll interval 1 sec),
port and phy link status must be synchronize in order don't loss link
change event.
[gregory.clement at free-electrons.com: add fixes tag]
Cc: <stable@vger.kernel.org>
Fixes: c5aff18204da ("net: mvneta: driver for Marvell Armada 370/XP network unit")
Signed-off-by: Yelena Krivosheev <yelena@marvell.com>
Tested-by: Dmitri Epshtein <dima@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
---
drivers/net/ethernet/marvell/mvneta.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/marvell/mvneta.c b/drivers/net/ethernet/marvell/mvneta.c
index bc93b69cfd1e..16b2bfb2cf51 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1214,6 +1214,10 @@ static void mvneta_port_disable(struct mvneta_port *pp)
val &= ~MVNETA_GMAC0_PORT_ENABLE;
mvreg_write(pp, MVNETA_GMAC_CTRL_0, val);
+ pp->link = 0;
+ pp->duplex = -1;
+ pp->speed = 0;
+
udelay(200);
}
--
2.15.1
^ permalink raw reply related
* [PATCH net 0/3] Few mvneta fixes
From: Gregory CLEMENT @ 2017-12-19 16:59 UTC (permalink / raw)
To: linux-arm-kernel
Hello,
here it is a small series of fixes found on the mvneta driver. They
had been already used in the vendor kernel and are now ported to
mainline.
Thanks,
Gregory
Yelena Krivosheev (3):
net: mvneta: clear interface link status on port disable
net: mvneta: use proper rxq_number in loop on rx queues
net: mvneta: eliminate wrong call to handle rx descriptor error
drivers/net/ethernet/marvell/mvneta.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
--
2.15.1
^ permalink raw reply
* [PATCH V1 1/1] iommu: Make sure device's ID array elements are unique
From: Alex Williamson @ 2017-12-19 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513696821-32291-1-git-send-email-tomasz.nowicki@caviumnetworks.com>
On Tue, 19 Dec 2017 16:20:21 +0100
Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> wrote:
> While iterating over DMA aliases for a PCI device, for some rare cases
> (i.e. PCIe-to-PCI/X bridges) we may get exactly the same ID as initial child
> device. In turn, the same ID may get registered for a device multiple times.
> Eventually IOMMU driver may try to configure the same ID within domain
> multiple times too which for some IOMMU drivers is illegal and causes kernel
> panic.
>
> Rule out ID duplication prior to device ID array registration.
>
> CC: stable at vger.kernel.org # v4.14+
You've identified a release, is there a specific commit this fixes?
> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com>
> ---
> drivers/iommu/iommu.c | 28 ++++++++++++++++++++++++++++
> 1 file changed, 28 insertions(+)
>
> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
> index 3de5c0b..9b2c138 100644
> --- a/drivers/iommu/iommu.c
> +++ b/drivers/iommu/iommu.c
> @@ -1945,6 +1945,31 @@ void iommu_fwspec_free(struct device *dev)
> }
> EXPORT_SYMBOL_GPL(iommu_fwspec_free);
>
> +static void iommu_fwspec_remove_ids_dup(struct device *dev, u32 *ids,
> + int *num_ids)
> +{
> + struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> + int i, j, k, valid_ids = *num_ids;
> +
> + for (i = 0; i < valid_ids; i++) {
> + for (j = 0; j < fwspec->num_ids; j++) {
> + if (ids[i] != fwspec->ids[j])
> + continue;
> +
> + dev_info(dev, "found 0x%x ID duplication, skipped\n",
> + ids[i]);
> +
> + for (k = i + 1; k < valid_ids; k++)
> + ids[k - 1] = ids[k];
Use memmove()?
> +
> + valid_ids--;
> + break;
At this point ids[i] is not the ids[i] that we tested for dupes, it's
what was ids[i + 1], but we're going to i++ on the next iteration and
we therefore never test that entry.
> + }
> + }
> +
> + *num_ids = valid_ids;
> +}
> +
> int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids)
> {
> struct iommu_fwspec *fwspec = dev->iommu_fwspec;
> @@ -1954,6 +1979,9 @@ int iommu_fwspec_add_ids(struct device *dev, u32 *ids, int num_ids)
> if (!fwspec)
> return -EINVAL;
>
> + /* Rule out IDs already registered */
> + iommu_fwspec_remove_ids_dup(dev, ids, &num_ids);
> +
> size = offsetof(struct iommu_fwspec, ids[fwspec->num_ids + num_ids]);
> if (size > sizeof(*fwspec)) {
> fwspec = krealloc(dev->iommu_fwspec, size, GFP_KERNEL);
^ permalink raw reply
* [PATCH 0/3] irqchip: irq-bcm2836: add support for DT interrupt polarity
From: Marc Zyngier @ 2017-12-19 16:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d0c81267-8379-d4a1-ec56-fec3492c1df6@i2se.com>
On 19/12/17 07:02, Stefan Wahren wrote:
> Hi Marc,
>
> Am 11.12.2017 um 21:39 schrieb Stefan Wahren:
>> This patch series implements DT polarity support for the 1st level interrupt
>> controller.
>>
>> Stefan Wahren (3):
>> dt-bindings: bcm2836-l1-intc: add interrupt polarity support
>> irqchip: irq-bcm2836: add support for DT interrupt polarity
>> ARM: dts: bcm283x: Define polarity of per-cpu interrupts
>>
>> .../interrupt-controller/brcm,bcm2836-l1-intc.txt | 4 +-
>> arch/arm/boot/dts/bcm2836.dtsi | 14 +++----
>> arch/arm/boot/dts/bcm2837.dtsi | 12 +++---
>> arch/arm/boot/dts/bcm283x.dtsi | 1 +
>> drivers/irqchip/irq-bcm2836.c | 46 +++++++++++++---------
>> 5 files changed, 44 insertions(+), 33 deletions(-)
>>
>
> is this series okay?
Yes, it does look good. I'll queue that for 4.16.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU
From: Robin Murphy @ 2017-12-19 16:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513696436-31834-1-git-send-email-tomasz.nowicki@caviumnetworks.com>
Hi Tomasz,
On 19/12/17 15:13, Tomasz Nowicki wrote:
> Here is my lspci output of ThunderX2 for which I am observing kernel panic coming from
> SMMUv3 driver -> arm_smmu_write_strtab_ent() -> BUG_ON(ste_live):
>
> # lspci -vt
> -[0000:00]-+-00.0-[01-1f]--+ [...]
> + [...]
> \-00.0-[1e-1f]----00.0-[1f]----00.0 ASPEED Technology, Inc. ASPEED Graphics Family
>
> ASP device -> 1f:00.0 VGA compatible controller: ASPEED Technology, Inc. ASPEED Graphics Family
> PCI-Express to PCI/PCI-X Bridge -> 1e:00.0 PCI bridge: ASPEED Technology, Inc. AST1150 PCI-to-PCI Bridge
>
> While setting up ASP device SID in IORT dirver:
> iort_iommu_configure() -> pci_for_each_dma_alias()
> we need to walk up and iterate over each device which alias transaction from
> downstream devices.
>
> AST device (1f:00.0) gets BDF=0x1f00 and corresponding SID=0x1f00 from IORT.
> Bridge (1e:00.0) is the first alias. Following PCI Express to PCI/PCI-X Bridge
> spec: PCIe-to-PCI/X bridges alias transactions from downstream devices using
> the subordinate bus number. For bridge (1e:00.0), the subordinate is equal
> to 0x1f. This gives BDF=0x1f00 and SID=1f00 which is the same as downstream
> device. So it is possible to have two identical SIDs. The question is what we
> should do about such case. Presented patch prevents from registering the same
> ID so that SMMUv3 is not complaining later on.
Ooh, subtle :( There is logic in arm_smmu_attach_device() to tolerate
grouped devices aliasing to the same ID, but I guess I overlooked the
distinction of a device sharing an alias ID with itself. I'm not sure
I really like trying to work around this in generic code, since
fwspec->ids is essentially opaque data in a driver-specific format - in
theory a driver is free to encode a single logical ID into multiple
fwspec elements (I think I did that in an early draft of SMMUv2 SMR
support), at which point this approach might corrupt things massively.
Does the (untested) diff below suffice?
Robin.
----->8-----diff --git a/drivers/iommu/arm-smmu-v3.c
b/drivers/iommu/arm-smmu-v3.c
index f122071688fd..d8a730d83401 100644
--- a/drivers/iommu/arm-smmu-v3.c
+++ b/drivers/iommu/arm-smmu-v3.c
@@ -1731,7 +1731,7 @@ static __le64 *arm_smmu_get_step_for_sid(struct
arm_smmu_device *smmu, u32 sid)
static void arm_smmu_install_ste_for_dev(struct iommu_fwspec *fwspec)
{
- int i;
+ int i, j;
struct arm_smmu_master_data *master = fwspec->iommu_priv;
struct arm_smmu_device *smmu = master->smmu;
@@ -1739,6 +1739,13 @@ static void arm_smmu_install_ste_for_dev(struct
iommu_fwspec *fwspec)
u32 sid = fwspec->ids[i];
__le64 *step = arm_smmu_get_step_for_sid(smmu, sid);
+ /* Bridged PCI devices may end up with duplicated IDs */
+ for (j = 0; j < i; j++)
+ if (fwspec->ids[j] == sid)
+ break;
+ if (j < i)
+ continue;
+
arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
}
}
^ permalink raw reply related
* [PATCH 1/4] pci: dwc: pci-dra7xx: Enable errata i870 for both EP and RC mode
From: Lorenzo Pieralisi @ 2017-12-19 16:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201061311.16691-2-vigneshr@ti.com>
On Fri, Dec 01, 2017 at 11:43:08AM +0530, Vignesh R wrote:
> Errata i870 is applicable in both EP and RC mode. Therefore rename
> function dra7xx_pcie_ep_unaligned_memaccess(), that implements errata
> workaround, to dra7xx_pcie_unaligned_memaccess() and call it from a
> common place. So, that errata workaround is applied for both modes of
> operation.
>
> Reported-by: Chris Welch <Chris.Welch@viavisolutions.com>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
> ---
> drivers/pci/dwc/pci-dra7xx.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
I need Kishon's ACK to apply it, thanks.
Lorenzo
> diff --git a/drivers/pci/dwc/pci-dra7xx.c b/drivers/pci/dwc/pci-dra7xx.c
> index e77a4ceed74c..53f721d1cc40 100644
> --- a/drivers/pci/dwc/pci-dra7xx.c
> +++ b/drivers/pci/dwc/pci-dra7xx.c
> @@ -546,7 +546,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
> };
>
> /*
> - * dra7xx_pcie_ep_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
> + * dra7xx_pcie_unaligned_memaccess: workaround for AM572x/AM571x Errata i870
> * @dra7xx: the dra7xx device where the workaround should be applied
> *
> * Access to the PCIe slave port that are not 32-bit aligned will result
> @@ -556,7 +556,7 @@ static const struct of_device_id of_dra7xx_pcie_match[] = {
> *
> * To avoid this issue set PCIE_SS1_AXI2OCP_LEGACY_MODE_ENABLE to 1.
> */
> -static int dra7xx_pcie_ep_unaligned_memaccess(struct device *dev)
> +static int dra7xx_pcie_unaligned_memaccess(struct device *dev)
> {
> int ret;
> struct device_node *np = dev->of_node;
> @@ -703,6 +703,10 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
> if (dra7xx->link_gen < 0 || dra7xx->link_gen > 2)
> dra7xx->link_gen = 2;
>
> + ret = dra7xx_pcie_unaligned_memaccess(dev);
> + if (ret)
> + goto err_gpio;
> +
> switch (mode) {
> case DW_PCIE_RC_TYPE:
> dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
> @@ -715,10 +719,6 @@ static int __init dra7xx_pcie_probe(struct platform_device *pdev)
> dra7xx_pcie_writel(dra7xx, PCIECTRL_TI_CONF_DEVICE_TYPE,
> DEVICE_TYPE_EP);
>
> - ret = dra7xx_pcie_ep_unaligned_memaccess(dev);
> - if (ret)
> - goto err_gpio;
> -
> ret = dra7xx_add_pcie_ep(dra7xx, pdev);
> if (ret < 0)
> goto err_gpio;
> --
> 2.15.0
>
^ permalink raw reply
* [PATCH v4] staging: fsl-mc: move bus driver out of staging
From: Greg KH @ 2017-12-19 16:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5A3932BF.80106@nxp.com>
On Tue, Dec 19, 2017 at 03:39:44PM +0000, Laurentiu Tudor wrote:
> On 12/19/2017 05:29 PM, Greg KH wrote:
> > On Tue, Dec 19, 2017 at 03:21:19PM +0000, Laurentiu Tudor wrote:
> >>
> >>
> >> On 12/19/2017 04:48 PM, Greg KH wrote:
> >>> On Wed, Nov 29, 2017 at 12:08:44PM +0200, laurentiu.tudor at nxp.com wrote:
> >>>> From: Stuart Yoder <stuart.yoder@nxp.com>
> >>>>
> >>>> Move the source files out of staging into their final locations:
> >>>> -include files in drivers/staging/fsl-mc/include go to include/linux/fsl
> >>>> -irq-gic-v3-its-fsl-mc-msi.c goes to drivers/irqchip
> >>>> -source in drivers/staging/fsl-mc/bus goes to drivers/bus/fsl-mc
> >>>> -README.txt, providing and overview of DPAA goes to
> >>>> Documentation/dpaa2/overview.txt
> >>>>
> >>>> Update or delete other remaining staging files-- Makefile, Kconfig, TODO.
> >>>> Update dpaa2_eth and dpio staging drivers.
> >>>>
> >>>> Signed-off-by: Stuart Yoder <stuyoder@gmail.com>
> >>>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> >>>> [Laurentiu: rebased, add dpaa2_eth and dpio #include updates]
> >>>> Cc: Thomas Gleixner <tglx@linutronix.de>
> >>>> Cc: Jason Cooper <jason@lakedaemon.net>
> >>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
> >>>> ---
> >>>> Notes:
> >>>> -v4:
> >>>> - regenerated patch with renames detection disabled (Andrew Lunn)
> >>>> -v3:
> >>>> - rebased
> >>>
> >>> Ok, meta-comments on the structure of the code.
> >>>
> >>> You have 8 .h files that are "private" to your bus logic. That's 7 too
> >>> many, some of them have a bigger license header than actual content :)
> >>>
> >>> Please consolidate into 1.
> >>>
> >>> Also, the headers should be moved to SPDX format to get rid of the
> >>> boilerplate. I _think_ it's BSD/GPL, right? Hard to tell :(
> >>
> >> It's 3-clause BSD and GPLv2. Will make it clear when moving to SPDX.
> >
> > Thanks.
> >
> >>> Your "public" .h file does not need to go into a subdirectory, just name
> >>> it fsl-mc.h and put it in include/linux/.
> >>
> >> There's already a "fsl" subdirectory in include/linux/ so it seemed to
> >> make sense to use it.
> >
> > Ah, missed that. Ok, nevermind :)`
> >
> >>> One comment on the fields in your .h file, all of the user/kernel
> >>> crossing boundry structures need to use the "__" variant of types, like
> >>> "__u8" and the like. You mix and match them for some reason, you need
> >>> to be consistent.
> >>>
> >>> Also, what's up with the .h files in drivers/staging/fsl-bus/include?
> >>> You didn't touch those with this movement, right? Why?
> >>
> >> Those are not part of the bus "core". Some of them are part of the DPBP
> >> and DPCON device types APIs and are used by drivers probing on this bus
> >> and the rest are part of the DPIO driver which is also used by other
> >> drivers. Since these devices (DPBP, DPCON, DPIO) are interfaces used by
> >> all the other drivers it made sense to group them together with the bus.
> >
> > But all of these .h files are only used by the code in this specific
> > directory, no where else.
>
> They are also used by our ethernet driver, see:
> drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
Ick, really? Then they should not be buried in a bus-specific
location, but rather be in include/linux/SOMEWHERE, right?
thanks,
greg k-h
^ permalink raw reply
* [PATCH v9 2/2] media: i2c: Add the ov7740 image sensor driver
From: Sakari Ailus @ 2017-12-19 16:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOMZO5DYWA8O5N=CRm2uR3_7qZ4U1M8u8F-oBU8bJfnKXD4DSA@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:31:46PM -0200, Fabio Estevam wrote:
> On Tue, Dec 19, 2017 at 11:43 AM, Sakari Ailus <sakari.ailus@iki.fi> wrote:
>
> > Both seem to exist. See e.g. c3a3d1d6b8b363a02234e5564692db3647f183e6 .
>
> This patch fixes .h files to use /* SPDX style comment, which is the
> recommendation.
>
> .c files should use // SPDX style.
Agreed. I reverted the changes.
Thanks.
--
Sakari Ailus
e-mail: sakari.ailus at iki.fi
^ permalink raw reply
* [PATCH v5 15/15] devicetree: bindings: Document qcom,pvs
From: Sricharan R @ 2017-12-19 15:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698900-10638-1-git-send-email-sricharan@codeaurora.org>
From: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
.../devicetree/bindings/arm/msm/qcom,pvs.txt | 91 ++++++++++++++++++++++
1 file changed, 91 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt b/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
new file mode 100644
index 0000000..260f537
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/msm/qcom,pvs.txt
@@ -0,0 +1,91 @@
+Qualcomm Process Voltage Scaling Tables
+
+The node name is required to be "qcom,pvs". There shall only be one
+such node present in the root of the tree.
+
+PROPERTIES
+
+- qcom,pvs-format-a or qcom,pvs-format-b:
+ Usage: required
+ Value type: <empty>
+ Definition: Indicates where and how to read and interpret the efuse registers.
+ Based on that the opp-microvolt-<name> is extended with the right
+ speedXX-PVSXX-versionXX string. The cpu opp-table should be populated
+ with the operating-points-v2 binding and each opp must have the voltage
+ specified for all combinations of opp-microvolt-<speedXX-pvsXX-versionXX>.
+
+Example:
+
+ cpu at 0 {
+ compatible = "qcom,krait";
+ enable-method = "qcom,kpss-acc-v1";
+ device_type = "cpu";
+ reg = <0>;
+ qcom,acc = <&acc0>;
+ qcom,saw = <&saw0>;
+ clocks = <&kraitcc 0>;
+ clock-names = "cpu";
+ cpu-supply = <&smb208_s2a>;
+ operating-points-v2 = <&cpu_opp_table>;
+ };
+
+ qcom,pvs {
+ qcom,pvs-format-a;
+ };
+
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+
+ /*
+ * Missing opp-shared property means CPUs switch DVFS states
+ * independently.
+ */
+
+ opp-1400000000 {
+ opp-hz = /bits/ 64 <1400000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1250000>;
+ opp-microvolt-speed0-pvs1-v0 = <1175000>;
+ opp-microvolt-speed0-pvs2-v0 = <1125000>;
+ opp-microvolt-speed0-pvs3-v0 = <1050000>;
+
+ };
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1100000>;
+ opp-microvolt-speed0-pvs1-v0 = <1025000>;
+ opp-microvolt-speed0-pvs2-v0 = <995000>;
+ opp-microvolt-speed0-pvs3-v0 = <900000>;
+
+ };
+ opp-384000000 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1000000>;
+ opp-microvolt-speed0-pvs1-v0 = <925000>;
+ opp-microvolt-speed0-pvs2-v0 = <875000>;
+ opp-microvolt-speed0-pvs3-v0 = <800000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1150000>;
+ opp-microvolt-speed0-pvs1-v0 = <1075000>;
+ opp-microvolt-speed0-pvs2-v0 = <1025000>;
+ opp-microvolt-speed0-pvs3-v0 = <950000>;
+
+ };
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1050000>;
+ opp-microvolt-speed0-pvs1-v0 = <975000>;
+ opp-microvolt-speed0-pvs2-v0 = <925000>;
+ opp-microvolt-speed0-pvs3-v0 = <850000>;
+ };
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ opp-microvolt-speed0-pvs0-v0 = <1200000>;
+ opp-microvolt-speed0-pvs1-v0 = <1125000>;
+ opp-microvolt-speed0-pvs2-v0 = <1075000>;
+ opp-microvolt-speed0-pvs3-v0 = <1000000>;
+ };
+ };
+
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v5 14/15] cpufreq: Add module to register cpufreq on Krait CPUs
From: Sricharan R @ 2017-12-19 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698900-10638-1-git-send-email-sricharan@codeaurora.org>
From: Stephen Boyd <sboyd@codeaurora.org>
Register a cpufreq-generic device whenever we detect that a
"qcom,krait" compatible CPU is present in DT.
Cc: <devicetree@vger.kernel.org>
[Sricharan: updated to use dev_pm_opp_set_prop_name]
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/cpufreq/Kconfig.arm | 9 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/cpufreq-dt-platdev.c | 3 +-
drivers/cpufreq/qcom-cpufreq.c | 171 +++++++++++++++++++++++++++++++++++
4 files changed, 183 insertions(+), 1 deletion(-)
create mode 100644 drivers/cpufreq/qcom-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index bdce448..60f28e7 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -100,6 +100,15 @@ config ARM_OMAP2PLUS_CPUFREQ
depends on ARCH_OMAP2PLUS
default ARCH_OMAP2PLUS
+config ARM_QCOM_CPUFREQ
+ tristate "Qualcomm based"
+ depends on ARCH_QCOM
+ select PM_OPP
+ help
+ This adds the CPUFreq driver for Qualcomm SoC based boards.
+
+ If in doubt, say N.
+
config ARM_S3C_CPUFREQ
bool
help
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 812f9e0..1496464 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -62,6 +62,7 @@ obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
+obj-$(CONFIG_ARM_QCOM_CPUFREQ) += qcom-cpufreq.o
obj-$(CONFIG_ARM_S3C24XX_CPUFREQ) += s3c24xx-cpufreq.o
obj-$(CONFIG_ARM_S3C24XX_CPUFREQ_DEBUGFS) += s3c24xx-cpufreq-debugfs.o
obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
index ecc56e2..032ac4f 100644
--- a/drivers/cpufreq/cpufreq-dt-platdev.c
+++ b/drivers/cpufreq/cpufreq-dt-platdev.c
@@ -118,7 +118,7 @@
{ .compatible = "ti,am33xx", },
{ .compatible = "ti,am43", },
{ .compatible = "ti,dra7", },
-
+ { .compatible = "qcom,ipq8064", },
{ }
};
@@ -157,6 +157,7 @@ static int __init cpufreq_dt_platdev_init(void)
create_pdev:
of_node_put(np);
+
return PTR_ERR_OR_ZERO(platform_device_register_data(NULL, "cpufreq-dt",
-1, data,
sizeof(struct cpufreq_dt_platform_data)));
diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
new file mode 100644
index 0000000..3e5583d
--- /dev/null
+++ b/drivers/cpufreq/qcom-cpufreq.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2013-2015, The Linux Foundation. All rights reserved.
+
+#include <linux/cpu.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/slab.h>
+#include "cpufreq-dt.h"
+
+static void __init get_krait_bin_format_a(int *speed, int *pvs, int *pvs_ver)
+{
+ void __iomem *base;
+ u32 pte_efuse;
+
+ *speed = *pvs = *pvs_ver = 0;
+
+ base = ioremap(0x007000c0, 4);
+ if (!base) {
+ pr_warn("Unable to read efuse data. Defaulting to 0!\n");
+ return;
+ }
+
+ pte_efuse = readl_relaxed(base);
+ iounmap(base);
+
+ *speed = pte_efuse & 0xf;
+ if (*speed == 0xf)
+ *speed = (pte_efuse >> 4) & 0xf;
+
+ if (*speed == 0xf) {
+ *speed = 0;
+ pr_warn("Speed bin: Defaulting to %d\n", *speed);
+ } else {
+ pr_info("Speed bin: %d\n", *speed);
+ }
+
+ *pvs = (pte_efuse >> 10) & 0x7;
+ if (*pvs == 0x7)
+ *pvs = (pte_efuse >> 13) & 0x7;
+
+ if (*pvs == 0x7) {
+ *pvs = 0;
+ pr_warn("PVS bin: Defaulting to %d\n", *pvs);
+ } else {
+ pr_info("PVS bin: %d\n", *pvs);
+ }
+}
+
+static void __init get_krait_bin_format_b(int *speed, int *pvs, int *pvs_ver)
+{
+ u32 pte_efuse, redundant_sel;
+ void __iomem *base;
+
+ *speed = 0;
+ *pvs = 0;
+ *pvs_ver = 0;
+
+ base = ioremap(0xfc4b80b0, 8);
+ if (!base) {
+ pr_warn("Unable to read efuse data. Defaulting to 0!\n");
+ return;
+ }
+
+ pte_efuse = readl_relaxed(base);
+ redundant_sel = (pte_efuse >> 24) & 0x7;
+ *speed = pte_efuse & 0x7;
+ /* 4 bits of PVS are in efuse register bits 31, 8-6. */
+ *pvs = ((pte_efuse >> 28) & 0x8) | ((pte_efuse >> 6) & 0x7);
+ *pvs_ver = (pte_efuse >> 4) & 0x3;
+
+ switch (redundant_sel) {
+ case 1:
+ *speed = (pte_efuse >> 27) & 0xf;
+ break;
+ case 2:
+ *pvs = (pte_efuse >> 27) & 0xf;
+ break;
+ }
+
+ /* Check SPEED_BIN_BLOW_STATUS */
+ if (pte_efuse & BIT(3)) {
+ pr_info("Speed bin: %d\n", *speed);
+ } else {
+ pr_warn("Speed bin not set. Defaulting to 0!\n");
+ *speed = 0;
+ }
+
+ /* Check PVS_BLOW_STATUS */
+ pte_efuse = readl_relaxed(base + 0x4) & BIT(21);
+ if (pte_efuse) {
+ pr_info("PVS bin: %d\n", *pvs);
+ } else {
+ pr_warn("PVS bin not set. Defaulting to 0!\n");
+ *pvs = 0;
+ }
+
+ pr_info("PVS version: %d\n", *pvs_ver);
+ iounmap(base);
+}
+
+static int __init qcom_cpufreq_populate_opps(void)
+{
+ int speed, pvs, pvs_ver;
+ struct device_node *np;
+ struct device *dev;
+ int cpu = 0;
+ char pvs_name[] = "speedXX-pvsXX-vXX";
+
+ np = of_find_node_by_name(NULL, "qcom,pvs");
+ if (!np)
+ return -ENODEV;
+
+ if (of_property_read_bool(np, "qcom,pvs-format-a"))
+ get_krait_bin_format_a(&speed, &pvs, &pvs_ver);
+ else if (of_property_read_bool(np, "qcom,pvs-format-b"))
+ get_krait_bin_format_b(&speed, &pvs, &pvs_ver);
+ else
+ return -ENODEV;
+
+ snprintf(pvs_name, sizeof(pvs_name), "speed%d-pvs%d-v%d",
+ speed, pvs, pvs_ver);
+
+ for (cpu = 0; cpu < num_possible_cpus(); cpu++) {
+ dev = get_cpu_device(cpu);
+ if (!dev)
+ return -ENODEV;
+
+ if (IS_ERR(dev_pm_opp_set_prop_name(dev, pvs_name)))
+ pr_warn("failed to add OPP name %s\n", pvs_name);
+ }
+
+ return 0;
+}
+
+static int __init qcom_cpufreq_driver_init(void)
+{
+ struct device *cpu_dev;
+ struct device_node *np;
+ int ret;
+
+ cpu_dev = get_cpu_device(0);
+ if (!cpu_dev)
+ return -ENODEV;
+
+ np = of_node_get(cpu_dev->of_node);
+ if (!np)
+ return -ENOENT;
+
+ if (!of_device_is_compatible(np, "qcom,krait")) {
+ of_node_put(np);
+ return -ENODEV;
+ }
+ of_node_put(np);
+
+ ret = qcom_cpufreq_populate_opps();
+ if (ret)
+ return ret;
+
+ return PTR_ERR(platform_device_register_simple("cpufreq-dt",
+ -1, NULL, 0));
+}
+module_init(qcom_cpufreq_driver_init);
+
+MODULE_DESCRIPTION("Qualcomm CPUfreq driver");
+MODULE_LICENSE("GPL v2");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v5 13/15] clk: qcom: Add safe switch hook for krait mux clocks
From: Sricharan R @ 2017-12-19 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698900-10638-1-git-send-email-sricharan@codeaurora.org>
When the Hfplls are reprogrammed during the rate change,
the primary muxes which are sourced from the same hfpll
for higher frequencies, needs to be switched to the 'safe
secondary mux' as the parent for that small window. This
is done by registering a clk notifier for the muxes and
switching to the safe parent in the PRE_RATE_CHANGE notifier
and back to the original parent in the POST_RATE_CHANGE notifier.
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
drivers/clk/qcom/clk-krait.c | 2 ++
drivers/clk/qcom/clk-krait.h | 3 +++
drivers/clk/qcom/krait-cc.c | 56 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 61 insertions(+)
diff --git a/drivers/clk/qcom/clk-krait.c b/drivers/clk/qcom/clk-krait.c
index 361c701..f9744f1 100644
--- a/drivers/clk/qcom/clk-krait.c
+++ b/drivers/clk/qcom/clk-krait.c
@@ -50,6 +50,8 @@ static int krait_mux_set_parent(struct clk_hw *hw, u8 index)
if (__clk_is_enabled(hw->clk))
__krait_mux_set_sel(mux, sel);
+ mux->reparent = true;
+
return 0;
}
diff --git a/drivers/clk/qcom/clk-krait.h b/drivers/clk/qcom/clk-krait.h
index d5c9c60..6e2d4f4 100644
--- a/drivers/clk/qcom/clk-krait.h
+++ b/drivers/clk/qcom/clk-krait.h
@@ -13,6 +13,9 @@ struct krait_mux_clk {
u32 shift;
u32 en_mask;
bool lpl;
+ u8 safe_sel;
+ u8 old_index;
+ bool reparent;
struct clk_hw hw;
struct notifier_block clk_nb;
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
index ee864fa..2d82c5f 100644
--- a/drivers/clk/qcom/krait-cc.c
+++ b/drivers/clk/qcom/krait-cc.c
@@ -26,6 +26,49 @@
0,
};
+/*
+ * Notifier function for switching the muxes to safe parent
+ * while the hfpll is getting reprogrammed.
+ */
+static int krait_notifier_cb(struct notifier_block *nb,
+ unsigned long event,
+ void *data)
+{
+ int ret = 0;
+ struct krait_mux_clk *mux = container_of(nb, struct krait_mux_clk,
+ clk_nb);
+ /* Switch to safe parent */
+ if (event == PRE_RATE_CHANGE) {
+ mux->old_index = krait_mux_clk_ops.get_parent(&mux->hw);
+ ret = krait_mux_clk_ops.set_parent(&mux->hw, mux->safe_sel);
+ mux->reparent = false;
+ /*
+ * By the time POST_RATE_CHANGE notifier is called,
+ * clk framework itself would have changed the parent for the new rate.
+ * Only otherwise, put back to the old parent.
+ */
+ } else if (event == POST_RATE_CHANGE) {
+ if (!mux->reparent)
+ ret = krait_mux_clk_ops.set_parent(&mux->hw,
+ mux->old_index);
+ }
+
+ return notifier_from_errno(ret);
+}
+
+static int krait_notifier_register(struct device *dev, struct clk *clk,
+ struct krait_mux_clk *mux)
+{
+ int ret = 0;
+
+ mux->clk_nb.notifier_call = krait_notifier_cb;
+ ret = clk_notifier_register(clk, &mux->clk_nb);
+ if (ret)
+ dev_err(dev, "failed to register clock notifier: %d\n", ret);
+
+ return ret;
+}
+
static int
krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
{
@@ -70,6 +113,7 @@
krait_add_sec_mux(struct device *dev, int id, const char *s,
unsigned int offset, bool unique_aux)
{
+ int ret;
struct krait_mux_clk *mux;
static const char *sec_mux_list[] = {
"acpu_aux",
@@ -93,6 +137,7 @@
mux->shift = 2;
mux->parent_map = sec_mux_map;
mux->hw.init = &init;
+ mux->safe_sel = 0;
init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
if (!init.name)
@@ -108,6 +153,11 @@
clk = devm_clk_register(dev, &mux->hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto unique_aux;
+
+unique_aux:
if (unique_aux)
kfree(sec_mux_list[0]);
err_aux:
@@ -119,6 +169,7 @@
krait_add_pri_mux(struct device *dev, int id, const char *s,
unsigned int offset)
{
+ int ret;
struct krait_mux_clk *mux;
const char *p_names[3];
struct clk_init_data init = {
@@ -139,6 +190,7 @@
mux->lpl = id >= 0;
mux->parent_map = pri_mux_map;
mux->hw.init = &init;
+ mux->safe_sel = 2;
init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
if (!init.name)
@@ -164,6 +216,10 @@
clk = devm_clk_register(dev, &mux->hw);
+ ret = krait_notifier_register(dev, clk, mux);
+ if (ret)
+ goto err_p3;
+err_p3:
kfree(p_names[2]);
err_p2:
kfree(p_names[1]);
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH v5 12/15] devicetree: bindings: Document qcom,krait-cc
From: Sricharan R @ 2017-12-19 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698900-10638-1-git-send-email-sricharan@codeaurora.org>
From: Stephen Boyd <sboyd@codeaurora.org>
The Krait clock controller controls the krait CPU and the L2 clocks
consisting a primary mux and secondary mux. Add document for that.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
.../devicetree/bindings/clock/qcom,krait-cc.txt | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
diff --git a/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
new file mode 100644
index 0000000..874138f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
@@ -0,0 +1,22 @@
+Krait Clock Controller
+
+PROPERTIES
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be one of:
+ "qcom,krait-cc-v1"
+ "qcom,krait-cc-v2"
+
+- #clock-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 1
+
+Example:
+
+ kraitcc: clock-controller {
+ compatible = "qcom,krait-cc-v1";
+ #clock-cells = <1>;
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V2 3/9] ARM: stm32: prepare stm32 family to welcome armv7 architecture
From: Ludovic BARRE @ 2017-12-19 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a3X1icDWmVng8w0Yd58nAcViJQ9oZc4xm-dEycVPe+5pg@mail.gmail.com>
On 12/19/2017 04:26 PM, Arnd Bergmann wrote:
> On Tue, Dec 19, 2017 at 3:43 PM, Ludovic BARRE <ludovic.barre@st.com> wrote:
>>
>>
>> On 12/18/2017 09:24 PM, Arnd Bergmann wrote:
>>>
>>> On Mon, Dec 18, 2017 at 4:17 PM, Ludovic Barre <ludovic.Barre@st.com>
>>> wrote:
>>>>
>>>> From: Ludovic Barre <ludovic.barre@st.com>
>>>>
>>>> This patch prepares the STM32 machine for the integration of Cortex-A
>>>> based microprocessor (MPU), on top of the existing Cortex-M
>>>> microcontroller family (MCU). Since both MCUs and MPUs are sharing
>>>> common hardware blocks we can keep using ARCH_STM32 flag for most of
>>>> them. If a hardware block is specific to one family we can use either
>>>> ARM_SINGLE_ARMV7M or ARCH_MULTI_V7 flag.
>>>>
>>>> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
>>>
>>>
>>> Looks good overall. Two more small comments:
>>>
>>>
>>>>
>>>> +if ARCH_STM32
>>>> +
>>>> config MACH_STM32F429
>>>> - bool "STMicrolectronics STM32F429"
>>>> - depends on ARCH_STM32
>>>> + bool "STMicroelectronics STM32F429"
>>>> + depends on ARM_SINGLE_ARMV7M
>>>> default y
>>>
>>>
>>> Instead of the explicit dependency for each board, I'd leave the
>>> surrounding
>>> 'if ARM_SINGLE_ARMV7M'. I think you had in v1.
>>
>>
>> As you suggest, I follow mach-at91 example.
>> The point is on "depends on ARM_SINGLE_ARMV7M" ?
>> You prefer this way:
>> config MACH_STM32F429
>> bool "STMicroelectronics STM32F429" if ARM_SINGLE_ARMV7M
>> default y
>>
>
> No, that would be wrong, that way you would always enable
> MACH_STM32F429 when ARM_SINGLE_ARMV7M is turned
> off, which is exactly the wrong way round. What I meant is
>
> if ARCH_STM32
>
> if ARM_SINGLE_ARMV7M
>
> config MACH_STM32F429
> bool "STMicrolectronics STM32F429"
>
> config MACH_STM32...
> ...
>
> endif # ARMv7-M
>
> if ARCH_MULTI_V7
>
> config MACH_STM32...
> ...
>
> endif # ARMv7-A
>
> endif # STM32
>
> Arnd
>
Ok, it's clear :-)
^ permalink raw reply
* [PATCH v5 11/15] clk: qcom: Add Krait clock controller driver
From: Sricharan R @ 2017-12-19 15:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513698900-10638-1-git-send-email-sricharan@codeaurora.org>
From: Stephen Boyd <sboyd@codeaurora.org>
The Krait CPU clocks are made up of a primary mux and secondary
mux for each CPU and the L2, controlled via cp15 accessors. For
Kraits within KPSSv1 each secondary mux accepts a different aux
source, but on KPSSv2 each secondary mux accepts the same aux
source.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/clk/qcom/Kconfig | 8 ++
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/krait-cc.c | 341 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 350 insertions(+)
create mode 100644 drivers/clk/qcom/krait-cc.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 17dcb88..de6b60d 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -222,6 +222,14 @@ config KPSS_XCC
if you want to support CPU frequency scaling on devices such
as MSM8960, APQ8064, etc.
+config KRAITCC
+ tristate "Krait Clock Controller"
+ depends on COMMON_CLK_QCOM && ARM
+ select KRAIT_CLOCKS
+ help
+ Support for the Krait CPU clocks on Qualcomm devices.
+ Say Y if you want to support CPU frequency scaling.
+
config KRAIT_CLOCKS
bool
select KRAIT_L2_ACCESSORS
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 7ad2302..6e6c700 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -39,3 +39,4 @@ obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
+obj-$(CONFIG_KRAITCC) += krait-cc.o
diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c
new file mode 100644
index 0000000..ee864fa
--- /dev/null
+++ b/drivers/clk/qcom/krait-cc.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2017, The Linux Foundation. All rights reserved.
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+
+#include "clk-krait.h"
+
+static unsigned int sec_mux_map[] = {
+ 2,
+ 0,
+};
+
+static unsigned int pri_mux_map[] = {
+ 1,
+ 2,
+ 0,
+};
+
+static int
+krait_add_div(struct device *dev, int id, const char *s, unsigned int offset)
+{
+ struct krait_div2_clk *div;
+ struct clk_init_data init = {
+ .num_parents = 1,
+ .ops = &krait_div2_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ const char *p_names[1];
+ struct clk *clk;
+
+ div = devm_kzalloc(dev, sizeof(*div), GFP_KERNEL);
+ if (!div)
+ return -ENOMEM;
+
+ div->width = 2;
+ div->shift = 6;
+ div->lpl = id >= 0;
+ div->offset = offset;
+ div->hw.init = &init;
+
+ init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+ if (!init.name)
+ return -ENOMEM;
+
+ init.parent_names = p_names;
+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+ if (!p_names[0]) {
+ kfree(init.name);
+ return -ENOMEM;
+ }
+
+ clk = devm_clk_register(dev, &div->hw);
+ kfree(p_names[0]);
+ kfree(init.name);
+
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static int
+krait_add_sec_mux(struct device *dev, int id, const char *s,
+ unsigned int offset, bool unique_aux)
+{
+ struct krait_mux_clk *mux;
+ static const char *sec_mux_list[] = {
+ "acpu_aux",
+ "qsb",
+ };
+ struct clk_init_data init = {
+ .parent_names = sec_mux_list,
+ .num_parents = ARRAY_SIZE(sec_mux_list),
+ .ops = &krait_mux_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ struct clk *clk;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return -ENOMEM;
+
+ mux->offset = offset;
+ mux->lpl = id >= 0;
+ mux->mask = 0x3;
+ mux->shift = 2;
+ mux->parent_map = sec_mux_map;
+ mux->hw.init = &init;
+
+ init.name = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+ if (!init.name)
+ return -ENOMEM;
+
+ if (unique_aux) {
+ sec_mux_list[0] = kasprintf(GFP_KERNEL, "acpu%s_aux", s);
+ if (!sec_mux_list[0]) {
+ clk = ERR_PTR(-ENOMEM);
+ goto err_aux;
+ }
+ }
+
+ clk = devm_clk_register(dev, &mux->hw);
+
+ if (unique_aux)
+ kfree(sec_mux_list[0]);
+err_aux:
+ kfree(init.name);
+ return PTR_ERR_OR_ZERO(clk);
+}
+
+static struct clk *
+krait_add_pri_mux(struct device *dev, int id, const char *s,
+ unsigned int offset)
+{
+ struct krait_mux_clk *mux;
+ const char *p_names[3];
+ struct clk_init_data init = {
+ .parent_names = p_names,
+ .num_parents = ARRAY_SIZE(p_names),
+ .ops = &krait_mux_clk_ops,
+ .flags = CLK_SET_RATE_PARENT,
+ };
+ struct clk *clk;
+
+ mux = devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ mux->mask = 0x3;
+ mux->shift = 0;
+ mux->offset = offset;
+ mux->lpl = id >= 0;
+ mux->parent_map = pri_mux_map;
+ mux->hw.init = &init;
+
+ init.name = kasprintf(GFP_KERNEL, "krait%s_pri_mux", s);
+ if (!init.name)
+ return ERR_PTR(-ENOMEM);
+
+ p_names[0] = kasprintf(GFP_KERNEL, "hfpll%s", s);
+ if (!p_names[0]) {
+ clk = ERR_PTR(-ENOMEM);
+ goto err_p0;
+ }
+
+ p_names[1] = kasprintf(GFP_KERNEL, "hfpll%s_div", s);
+ if (!p_names[1]) {
+ clk = ERR_PTR(-ENOMEM);
+ goto err_p1;
+ }
+
+ p_names[2] = kasprintf(GFP_KERNEL, "krait%s_sec_mux", s);
+ if (!p_names[2]) {
+ clk = ERR_PTR(-ENOMEM);
+ goto err_p2;
+ }
+
+ clk = devm_clk_register(dev, &mux->hw);
+
+ kfree(p_names[2]);
+err_p2:
+ kfree(p_names[1]);
+err_p1:
+ kfree(p_names[0]);
+err_p0:
+ kfree(init.name);
+ return clk;
+}
+
+/* id < 0 for L2, otherwise id == physical CPU number */
+static struct clk *krait_add_clks(struct device *dev, int id, bool unique_aux)
+{
+ int ret;
+ unsigned int offset;
+ void *p = NULL;
+ const char *s;
+ struct clk *clk;
+
+ if (id >= 0) {
+ offset = 0x4501 + (0x1000 * id);
+ s = p = kasprintf(GFP_KERNEL, "%d", id);
+ if (!s)
+ return ERR_PTR(-ENOMEM);
+ } else {
+ offset = 0x500;
+ s = "_l2";
+ }
+
+ ret = krait_add_div(dev, id, s, offset);
+ if (ret) {
+ clk = ERR_PTR(ret);
+ goto err;
+ }
+
+ ret = krait_add_sec_mux(dev, id, s, offset, unique_aux);
+ if (ret) {
+ clk = ERR_PTR(ret);
+ goto err;
+ }
+
+ clk = krait_add_pri_mux(dev, id, s, offset);
+err:
+ kfree(p);
+ return clk;
+}
+
+static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data)
+{
+ unsigned int idx = clkspec->args[0];
+ struct clk **clks = data;
+
+ if (idx >= 5) {
+ pr_err("%s: invalid clock index %d\n", __func__, idx);
+ return ERR_PTR(-EINVAL);
+ }
+
+ return clks[idx] ? : ERR_PTR(-ENODEV);
+}
+
+static const struct of_device_id krait_cc_match_table[] = {
+ { .compatible = "qcom,krait-cc-v1", (void *)1UL },
+ { .compatible = "qcom,krait-cc-v2" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, krait_cc_match_table);
+
+static int krait_cc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ const struct of_device_id *id;
+ unsigned long cur_rate, aux_rate;
+ int cpu;
+ struct clk *clk;
+ struct clk **clks;
+ struct clk *l2_pri_mux_clk;
+
+ id = of_match_device(krait_cc_match_table, dev);
+ if (!id)
+ return -ENODEV;
+
+ /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */
+ clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+
+ if (!id->data) {
+ clk = clk_register_fixed_factor(dev, "acpu_aux",
+ "gpll0_vote", 0, 1, 2);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ }
+
+ /* Krait configurations have at most 4 CPUs and one L2 */
+ clks = devm_kcalloc(dev, 5, sizeof(*clks), GFP_KERNEL);
+ if (!clks)
+ return -ENOMEM;
+
+ for_each_possible_cpu(cpu) {
+ clk = krait_add_clks(dev, cpu, id->data);
+ if (IS_ERR(clk))
+ return PTR_ERR(clk);
+ clks[cpu] = clk;
+ }
+
+ l2_pri_mux_clk = krait_add_clks(dev, -1, id->data);
+ if (IS_ERR(l2_pri_mux_clk))
+ return PTR_ERR(l2_pri_mux_clk);
+ clks[4] = l2_pri_mux_clk;
+
+ /*
+ * We don't want the CPU or L2 clocks to be turned off at late init
+ * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the
+ * refcount of these clocks. Any cpufreq/hotplug manager can assume
+ * that the clocks have already been prepared and enabled by the time
+ * they take over.
+ */
+ for_each_online_cpu(cpu) {
+ clk_prepare_enable(l2_pri_mux_clk);
+ WARN(clk_prepare_enable(clks[cpu]),
+ "Unable to turn on CPU%d clock", cpu);
+ }
+
+ /*
+ * Force reinit of HFPLLs and muxes to overwrite any potential
+ * incorrect configuration of HFPLLs and muxes by the bootloader.
+ * While at it, also make sure the cores are running at known rates
+ * and print the current rate.
+ *
+ * The clocks are set to aux clock rate first to make sure the
+ * secondary mux is not sourcing off of QSB. The rate is then set to
+ * two different rates to force a HFPLL reinit under all
+ * circumstances.
+ */
+ cur_rate = clk_get_rate(l2_pri_mux_clk);
+ aux_rate = 384000000;
+ if (cur_rate == 1) {
+ pr_info("L2 @ QSB rate. Forcing new rate.\n");
+ cur_rate = aux_rate;
+ }
+ clk_set_rate(l2_pri_mux_clk, aux_rate);
+ clk_set_rate(l2_pri_mux_clk, 2);
+ clk_set_rate(l2_pri_mux_clk, cur_rate);
+ pr_info("L2 @ %lu KHz\n", clk_get_rate(l2_pri_mux_clk) / 1000);
+ for_each_possible_cpu(cpu) {
+ clk = clks[cpu];
+ cur_rate = clk_get_rate(clk);
+ if (cur_rate == 1) {
+ pr_info("CPU%d @ QSB rate. Forcing new rate.\n", cpu);
+ cur_rate = aux_rate;
+ }
+
+ clk_set_rate(clk, aux_rate);
+ clk_set_rate(clk, 2);
+ clk_set_rate(clk, cur_rate);
+ pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000);
+ }
+
+ of_clk_add_provider(dev->of_node, krait_of_get, clks);
+
+ return 0;
+}
+
+static struct platform_driver krait_cc_driver = {
+ .probe = krait_cc_probe,
+ .driver = {
+ .name = "krait-cc",
+ .of_match_table = krait_cc_match_table,
+ },
+};
+module_platform_driver(krait_cc_driver);
+
+MODULE_DESCRIPTION("Krait CPU Clock Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:krait-cc");
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
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