* [PATCH] clk: samsung: s3c: Remove unneeded enumeration
From: Chanwoo Choi @ 2017-12-20 9:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1511749908-29777-1-git-send-email-cw00.choi@samsung.com>
Dear Sylwester,
Gently Ping.
Regards,
Chanwoo Choi
On 2017? 11? 27? 11:31, Chanwoo Choi wrote:
> This patch just removes the unneeded enumeration for PLL index.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> drivers/clk/samsung/clk-s3c2412.c | 11 ++---------
> drivers/clk/samsung/clk-s3c2443.c | 17 ++++-------------
> drivers/clk/samsung/clk-s3c64xx.c | 17 ++++++-----------
> 3 files changed, 12 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-s3c2412.c b/drivers/clk/samsung/clk-s3c2412.c
> index b8340a49921b..1555e407529e 100644
> --- a/drivers/clk/samsung/clk-s3c2412.c
> +++ b/drivers/clk/samsung/clk-s3c2412.c
> @@ -27,11 +27,6 @@
> #define CLKSRC 0x1c
> #define SWRST 0x30
>
> -/* list of PLLs to be registered */
> -enum s3c2412_plls {
> - mpll, upll,
> -};
> -
> static void __iomem *reg_base;
>
> #ifdef CONFIG_PM_SLEEP
> @@ -144,10 +139,8 @@ struct samsung_mux_clock s3c2412_muxes[] __initdata = {
> };
>
> static struct samsung_pll_clock s3c2412_plls[] __initdata = {
> - [mpll] = PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti",
> - LOCKTIME, MPLLCON, NULL),
> - [upll] = PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk",
> - LOCKTIME, UPLLCON, NULL),
> + PLL(pll_s3c2440_mpll, MPLL, "mpll", "xti", LOCKTIME, MPLLCON, NULL),
> + PLL(pll_s3c2410_upll, UPLL, "upll", "urefclk", LOCKTIME, UPLLCON, NULL),
> };
>
> struct samsung_gate_clock s3c2412_gates[] __initdata = {
> diff --git a/drivers/clk/samsung/clk-s3c2443.c b/drivers/clk/samsung/clk-s3c2443.c
> index d94b85a42356..9580a6baf4d7 100644
> --- a/drivers/clk/samsung/clk-s3c2443.c
> +++ b/drivers/clk/samsung/clk-s3c2443.c
> @@ -41,11 +41,6 @@ enum supported_socs {
> S3C2450,
> };
>
> -/* list of PLLs to be registered */
> -enum s3c2443_plls {
> - mpll, epll,
> -};
> -
> static void __iomem *reg_base;
>
> #ifdef CONFIG_PM_SLEEP
> @@ -225,10 +220,8 @@ struct samsung_clock_alias s3c2443_common_aliases[] __initdata = {
> /* S3C2416 specific clocks */
>
> static struct samsung_pll_clock s3c2416_pll_clks[] __initdata = {
> - [mpll] = PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref",
> - LOCKCON0, MPLLCON, NULL),
> - [epll] = PLL(pll_6553, EPLL, "epll", "epllref",
> - LOCKCON1, EPLLCON, NULL),
> + PLL(pll_6552_s3c2416, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
> + PLL(pll_6553, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
> };
>
> PNAME(s3c2416_hsmmc0_p) = { "sclk_hsmmc0", "sclk_hsmmcext" };
> @@ -279,10 +272,8 @@ struct samsung_clock_alias s3c2416_aliases[] __initdata = {
> /* S3C2443 specific clocks */
>
> static struct samsung_pll_clock s3c2443_pll_clks[] __initdata = {
> - [mpll] = PLL(pll_3000, MPLL, "mpll", "mpllref",
> - LOCKCON0, MPLLCON, NULL),
> - [epll] = PLL(pll_2126, EPLL, "epll", "epllref",
> - LOCKCON1, EPLLCON, NULL),
> + PLL(pll_3000, MPLL, "mpll", "mpllref", LOCKCON0, MPLLCON, NULL),
> + PLL(pll_2126, EPLL, "epll", "epllref", LOCKCON1, EPLLCON, NULL),
> };
>
> static struct clk_div_table armdiv_s3c2443_d[] = {
> diff --git a/drivers/clk/samsung/clk-s3c64xx.c b/drivers/clk/samsung/clk-s3c64xx.c
> index 7306867a0ab8..6db01cf5ab83 100644
> --- a/drivers/clk/samsung/clk-s3c64xx.c
> +++ b/drivers/clk/samsung/clk-s3c64xx.c
> @@ -56,11 +56,6 @@
> #define GATE_ON(_id, cname, pname, o, b) \
> GATE(_id, cname, pname, o, b, CLK_IGNORE_UNUSED, 0)
>
> -/* list of PLLs to be registered */
> -enum s3c64xx_plls {
> - apll, mpll, epll,
> -};
> -
> static void __iomem *reg_base;
> static bool is_s3c6400;
>
> @@ -364,12 +359,12 @@ static void __init s3c64xx_clk_sleep_init(void) {}
>
> /* List of PLL clocks. */
> static struct samsung_pll_clock s3c64xx_pll_clks[] __initdata = {
> - [apll] = PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
> - APLL_LOCK, APLL_CON, NULL),
> - [mpll] = PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
> - MPLL_LOCK, MPLL_CON, NULL),
> - [epll] = PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
> - EPLL_LOCK, EPLL_CON0, NULL),
> + PLL(pll_6552, FOUT_APLL, "fout_apll", "fin_pll",
> + APLL_LOCK, APLL_CON, NULL),
> + PLL(pll_6552, FOUT_MPLL, "fout_mpll", "fin_pll",
> + MPLL_LOCK, MPLL_CON, NULL),
> + PLL(pll_6553, FOUT_EPLL, "fout_epll", "fin_pll",
> + EPLL_LOCK, EPLL_CON0, NULL),
> };
>
> /* Aliases for common s3c64xx clocks. */
>
^ permalink raw reply
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Ganapatrao Kulkarni @ 2017-12-20 9:15 UTC (permalink / raw)
To: linux-arm-kernel
When an interrupt is moved, it is possible that an implementation that
supports caching might still have cached data for a previous
(no longer valid) mapping of the interrupt. In particular, in a distributed
GIC implementation like multi-socket SoC platfroms. Hence it is necessary
to flush cached entries after cross node collection migration.
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
---
drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 4039e64..ea849a1 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
if (cpu != its_dev->event_map.col_map[id]) {
target_col = &its_dev->its->collections[cpu];
its_send_movi(its_dev, target_col, id);
+ /* Issue INV for cross node collection move on
+ * multi socket systems.
+ */
+ if (cpu_to_node(cpu) !=
+ cpu_to_node(its_dev->event_map.col_map[id]))
+ its_send_inv(its_dev, id);
its_dev->event_map.col_map[id] = cpu;
irq_data_update_effective_affinity(d, cpumask_of(cpu));
}
--
2.9.4
^ permalink raw reply related
* [PATCH V2 9/9] ARM: dts: stm32: add initial support of stm32mp157c eval board
From: Alexandre Torgue @ 2017-12-20 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZaEjdGB2k6HdPt1_E0jRXEimEUxT9NmMwMw7OiyeqGLA@mail.gmail.com>
Hi Linus
On 12/20/2017 08:44 AM, Linus Walleij wrote:
> On Mon, Dec 18, 2017 at 4:17 PM, Ludovic Barre <ludovic.Barre@st.com> wrote:
>
>> From: Ludovic Barre <ludovic.barre@st.com>
>>
>> Add support of stm32mp157c evaluation board (part number: STM32MP157C-EV1)
>> split in 2 elements:
>> -Daughter board (part number: STM32MP157C-ED1)
>> which includes CPU, memory and power supply
>> -Mother board (part number: STM32MP157C-EM1)
>> which includes external peripherals (like display, camera,...)
>> and extension connectors.
>>
>> The daughter board can run alone, this is why the device tree files
>> are split in two layers, for the complete evaluation board (ev1)
>> and for the daughter board alone (ed1).
>>
>> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
>> Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
> (...)
>> diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
>
> Evaluation boards are important because they set a pattern that customers
> will use.
>
> Please consider to include nodes for all GPIO blocks used in this
> evaluation board, and add:
>
> gpio-line-names = "foo", "bar" ...;
>
> See for example
> arch/arm/boot/dts/bcm2835-rpi-a.dts
> arch/arm/boot/dts/ste-snowball.dts
>
> It's good to have because probably you guys have proper schematics and
> know rail names of the stuff connected to those GPIO lines and so on,
> so you can give the lines proper names.
It looks like useful for pins used as gpio line. Are you saying that we
also have to describe pins used as Alternate Function ? Currently for
stm32 MCU we add (for each pins in a group) a comment in
stm32xxx-pinctrl.dtsi file to describe the pinmux (to help developers).
On driver side for each stm32 pinctrl driver (ex:
drivers/pinctrl/stm32/pinctrl-stm32f429.c) we add for each possible
muxing a name:
STM32_PIN(
PINCTRL_PIN(0, "PA0"),
STM32_FUNCTION(0, "GPIOA0"),
STM32_FUNCTION(2, "TIM2_CH1 TIM2_ETR"),
STM32_FUNCTION(3, "TIM5_CH1"),
STM32_FUNCTION(4, "TIM8_ETR"),
STM32_FUNCTION(8, "USART2_CTS"),
STM32_FUNCTION(9, "UART4_TX"),
STM32_FUNCTION(12, "ETH_MII_CRS"),
STM32_FUNCTION(16, "EVENTOUT"),
STM32_FUNCTION(17, "ANALOG")
),
To be honest, currently there is a an issue to printout the name :) but
I have a patch to send for that.
regards
Alex
>
> It will be helpful for people using the reference design, especially with the
> new character device, and also sets a pattern for people doing devices
> based on the reference design and we really want to do that.
>
> Yours,
> Linus Walleij
>
^ permalink raw reply
* [PATCH v2 3/3] ARM: dts: r8a7745: Add CMT SoC specific support
From: Simon Horman @ 2017-12-20 9:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdV-sM833JqN-UD8sBYc-bVS-3zWanaQTL-OUgpvKh_uXA@mail.gmail.com>
On Tue, Dec 19, 2017 at 12:21:12PM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 6:39 PM, Fabrizio Castro
> <fabrizio.castro@bp.renesas.com> wrote:
> > Add CMT[01] support to SoC DT.
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> > Reviewed-by: Biju Das <biju.das@bp.renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Marc Zyngier @ 2017-12-20 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220091544.4467-1-ganapatrao.kulkarni@cavium.com>
On 20/12/17 09:15, Ganapatrao Kulkarni wrote:
> When an interrupt is moved, it is possible that an implementation that
> supports caching might still have cached data for a previous
> (no longer valid) mapping of the interrupt. In particular, in a distributed
> GIC implementation like multi-socket SoC platfroms. Hence it is necessary
> to flush cached entries after cross node collection migration.
>
> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
> ---
> drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> index 4039e64..ea849a1 100644
> --- a/drivers/irqchip/irq-gic-v3-its.c
> +++ b/drivers/irqchip/irq-gic-v3-its.c
> @@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
> if (cpu != its_dev->event_map.col_map[id]) {
> target_col = &its_dev->its->collections[cpu];
> its_send_movi(its_dev, target_col, id);
> + /* Issue INV for cross node collection move on
> + * multi socket systems.
> + */
> + if (cpu_to_node(cpu) !=
> + cpu_to_node(its_dev->event_map.col_map[id]))
> + its_send_inv(its_dev, id);
> its_dev->event_map.col_map[id] = cpu;
> irq_data_update_effective_affinity(d, cpumask_of(cpu));
> }
>
The MOVI command doesn't have any such requirement (it only mandates
synchronization), and doesn't say anything about distributed vs monolithic.
What am I missing?
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH 1/2] ARM: dts: r8a7745: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 9:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdWunJqU2b4e6XDc8MwnDc6WzxJPJumREM=X=MPSMN3e6A@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:44:38AM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 10:50 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Sort root sub-nodes alphabetically for allow for easier maintenance
>
> to allow for
>
> > of this file.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied with the changelog fix.
^ permalink raw reply
* [PATCH 2/2] ARM: dts: r8a7745: move timer node out of bus
From: Simon Horman @ 2017-12-20 9:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdUELsg=qPrho-SmekY_d24q9waUwGS90HFEKQsSV1w7=w@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:45:05AM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 10:50 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > The timer node does not have any register properties and thus shouldn't be
> > placed on the bus.
> >
> > This problem is flagged by the compiler as follows:
> > $ make dtbs W=1
> > ...
> > arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm/boot/dts/r8a7745-iwg22d-sodimm-dbhd-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > DTC arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb
> > arch/arm/boot/dts/r8a7745-sk-rzg1e.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied.
^ permalink raw reply
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Ganapatrao Kulkarni @ 2017-12-20 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a2754c68-0a6b-e23d-1ed7-693ce4f7f89c@arm.com>
Hi Marc,
On Wed, Dec 20, 2017 at 2:56 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
> On 20/12/17 09:15, Ganapatrao Kulkarni wrote:
>> When an interrupt is moved, it is possible that an implementation that
>> supports caching might still have cached data for a previous
>> (no longer valid) mapping of the interrupt. In particular, in a distributed
>> GIC implementation like multi-socket SoC platfroms. Hence it is necessary
>> to flush cached entries after cross node collection migration.
>>
>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>> ---
>> drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
>> 1 file changed, 6 insertions(+)
>>
>> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
>> index 4039e64..ea849a1 100644
>> --- a/drivers/irqchip/irq-gic-v3-its.c
>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>> @@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
>> if (cpu != its_dev->event_map.col_map[id]) {
>> target_col = &its_dev->its->collections[cpu];
>> its_send_movi(its_dev, target_col, id);
>> + /* Issue INV for cross node collection move on
>> + * multi socket systems.
>> + */
>> + if (cpu_to_node(cpu) !=
>> + cpu_to_node(its_dev->event_map.col_map[id]))
>> + its_send_inv(its_dev, id);
>> its_dev->event_map.col_map[id] = cpu;
>> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>> }
>>
>
> The MOVI command doesn't have any such requirement (it only mandates
> synchronization), and doesn't say anything about distributed vs monolithic.
GIC-v3 spec do mention to issue ITS INV command or a write to GICR_INVLPIR.
pasting below snippet of MOVI command description.
"When an interrupt is moved to a collection, it is possible that an
implementation that supports speculative caching
might still have cached data for a previous (no longer valid) mapping
of the interrupt. Hence, implementations
must take care to invalidate any data associated with an interrupt
when it is moved. In particular, in a distributed
implementation, the ITS must write to the appropriate GICR_* register
to perform the invalidation in the redistributor."
>
> What am I missing?
>
> M.
> --
> Jazz is not dead. It just smells funny...
thanks
Ganapat
^ permalink raw reply
* [PATCH 1/2] ARM: dts: r8a7792: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 9:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <14c60234-3755-3b06-64fc-e3943d8b5293@cogentembedded.com>
On Tue, Dec 19, 2017 at 12:27:48PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 12/19/2017 12:32 AM, Simon Horman wrote:
>
> > Sort root sub-nodes alphabetically for allow for easier maintenance
>
> s/for/to/?
>
> > of this file.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> > arch/arm/boot/dts/r8a7792.dtsi | 48 +++++++++++++++++++++---------------------
> > 1 file changed, 24 insertions(+), 24 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
> > index ac05fdb91798..d31258958c36 100644
> > --- a/arch/arm/boot/dts/r8a7792.dtsi
> > +++ b/arch/arm/boot/dts/r8a7792.dtsi
> > @@ -36,6 +36,22 @@
> > vin5 = &vin5;
> > };
> > + /* External root clock */
> > + extal_clk: extal {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board. */
> > + clock-frequency = <0>;
> > + };
> > +
> > + /* External CAN clock */
> > + can_clk: can {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + /* This value must be overridden by the board. */
> > + clock-frequency = <0>;
> > + };
> > +
>
> C predates E in my alphabet. :-)
Thanks, I have applied the following:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7792: sort root sub-nodes alphabetically
Sort root sub-nodes alphabetically to allow for easier maintenance
of this file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7792.dtsi | 48 +++++++++++++++++++++---------------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7792.dtsi b/arch/arm/boot/dts/r8a7792.dtsi
index 7b394273031e..b0013e5fcf47 100644
--- a/arch/arm/boot/dts/r8a7792.dtsi
+++ b/arch/arm/boot/dts/r8a7792.dtsi
@@ -36,6 +36,14 @@
vin5 = &vin5;
};
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -69,6 +77,22 @@
};
};
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -832,28 +856,4 @@
#power-domain-cells = <0>;
};
};
-
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
};
--
2.11.0
^ permalink raw reply related
* [-next PATCH 0/4] sysfs and DEVICE_ATTR_<foo>
From: Felipe Balbi @ 2017-12-20 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513706701.git.joe@perches.com>
Hi,
Joe Perches <joe@perches.com> writes:
> drivers/usb/phy/phy-tahvo.c | 2 +-
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
--
balbi
^ permalink raw reply
* [PATCH net 1/2] dt-bindings: net: mediatek: add condition to property mediatek, pctl
From: sean.wang at mediatek.com @ 2017-12-20 9:47 UTC (permalink / raw)
To: linux-arm-kernel
From: Sean Wang <sean.wang@mediatek.com>
The property "mediatek,pctl" is only required for SoCs such as MT2701 and
MT7623, so adding a few words for stating the condition.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/net/mediatek-net.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
index 214eaa9..53c13ee 100644
--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
@@ -28,7 +28,7 @@ Required properties:
- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
which is required for those SoCs equipped with SGMII such as MT7622 SoC.
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
- and driver current
+ and driver current: only for MT2701 and MT7623 SoC
Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
--
2.7.4
^ permalink raw reply related
* [PATCH net 2/2] net: mediatek: remove superfluous pin setup for MT7622 SoC
From: sean.wang at mediatek.com @ 2017-12-20 9:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e366efc29985d3292c8a1afb1389b5eac57c9037.1513762066.git.sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
Remove superfluous pin setup to get out of accessing invalid I/O pin
registers because the way for pin configuring tends to be different from
various SoCs and thus it should be better being managed and controlled by
the pinctrl driver which MT7622 already can support.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index fc67e35..29826dd 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1952,14 +1952,16 @@ static int mtk_hw_init(struct mtk_eth *eth)
}
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
- /* Set GE2 driving and slew rate */
- regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
+ if (eth->pctl) {
+ /* Set GE2 driving and slew rate */
+ regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
- /* set GE2 TDSEL */
- regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
+ /* set GE2 TDSEL */
+ regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
- /* set GE2 TUNE */
- regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
+ /* set GE2 TUNE */
+ regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
+ }
/* Set linkdown as the default for each GMAC. Its own MCR would be set
* up with the more appropriate value when mtk_phy_link_adjust call is
@@ -2538,11 +2540,13 @@ static int mtk_probe(struct platform_device *pdev)
}
}
- eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
- "mediatek,pctl");
- if (IS_ERR(eth->pctl)) {
- dev_err(&pdev->dev, "no pctl regmap found\n");
- return PTR_ERR(eth->pctl);
+ if (eth->soc->required_pctl) {
+ eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,pctl");
+ if (IS_ERR(eth->pctl)) {
+ dev_err(&pdev->dev, "no pctl regmap found\n");
+ return PTR_ERR(eth->pctl);
+ }
}
for (i = 0; i < 3; i++) {
@@ -2668,17 +2672,20 @@ static int mtk_remove(struct platform_device *pdev)
static const struct mtk_soc_data mt2701_data = {
.caps = MTK_GMAC1_TRGMII,
- .required_clks = MT7623_CLKS_BITMAP
+ .required_clks = MT7623_CLKS_BITMAP,
+ .required_pctl = true,
};
static const struct mtk_soc_data mt7622_data = {
.caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
- .required_clks = MT7622_CLKS_BITMAP
+ .required_clks = MT7622_CLKS_BITMAP,
+ .required_pctl = false,
};
static const struct mtk_soc_data mt7623_data = {
.caps = MTK_GMAC1_TRGMII,
- .required_clks = MT7623_CLKS_BITMAP
+ .required_clks = MT7623_CLKS_BITMAP,
+ .required_pctl = true,
};
const struct of_device_id of_mtk_match[] = {
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index a3af466..672b8c3 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -573,10 +573,13 @@ struct mtk_rx_ring {
* @caps Flags shown the extra capability for the SoC
* @required_clks Flags shown the bitmap for required clocks on
* the target SoC
+ * @required_pctl A bool value to show whether the SoC requires
+ * the extra setup for those pins used by GMAC.
*/
struct mtk_soc_data {
u32 caps;
u32 required_clks;
+ bool required_pctl;
};
/* currently no SoC has more than 2 macs */
--
2.7.4
^ permalink raw reply related
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Marc Zyngier @ 2017-12-20 9:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKTKpr47HZmoShXvAG5d4DZQORvrMccdaL8-mEWmpEsNMX5_3w@mail.gmail.com>
On 20/12/17 09:34, Ganapatrao Kulkarni wrote:
> Hi Marc,
>
> On Wed, Dec 20, 2017 at 2:56 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 20/12/17 09:15, Ganapatrao Kulkarni wrote:
>>> When an interrupt is moved, it is possible that an implementation that
>>> supports caching might still have cached data for a previous
>>> (no longer valid) mapping of the interrupt. In particular, in a distributed
>>> GIC implementation like multi-socket SoC platfroms. Hence it is necessary
>>> to flush cached entries after cross node collection migration.
>>>
>>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>>> ---
>>> drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
>>> 1 file changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
>>> index 4039e64..ea849a1 100644
>>> --- a/drivers/irqchip/irq-gic-v3-its.c
>>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>>> @@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
>>> if (cpu != its_dev->event_map.col_map[id]) {
>>> target_col = &its_dev->its->collections[cpu];
>>> its_send_movi(its_dev, target_col, id);
>>> + /* Issue INV for cross node collection move on
>>> + * multi socket systems.
>>> + */
>>> + if (cpu_to_node(cpu) !=
>>> + cpu_to_node(its_dev->event_map.col_map[id]))
>>> + its_send_inv(its_dev, id);
>>> its_dev->event_map.col_map[id] = cpu;
>>> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>>> }
>>>
>>
>> The MOVI command doesn't have any such requirement (it only mandates
>> synchronization), and doesn't say anything about distributed vs monolithic.
>
> GIC-v3 spec do mention to issue ITS INV command or a write to GICR_INVLPIR.
> pasting below snippet of MOVI command description.
>
> "When an interrupt is moved to a collection, it is possible that an
> implementation that supports speculative caching
> might still have cached data for a previous (no longer valid) mapping
> of the interrupt. Hence, implementations
> must take care to invalidate any data associated with an interrupt
> when it is moved. In particular, in a distributed
> implementation, the ITS must write to the appropriate GICR_* register
> to perform the invalidation in the redistributor."
Which document is that from? The only official document that should be
used is the GICv3/v4 Architecture Specification[1], which doesn't
contain that text.
Thanks,
M.
[1]:
https://developer.arm.com/products/architecture/a-profile/docs/ihi0069/latest/arm-generic-interrupt-controller-architecture-specification-gic-architecture-version-30-and-40
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH 0/2] pinctrl/nomadik/abx500: Adjustments for abx500_gpio_probe()
From: SF Markus Elfring @ 2017-12-20 9:50 UTC (permalink / raw)
To: linux-arm-kernel
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Wed, 20 Dec 2017 10:45:01 +0100
Two update suggestions were taken into account
from static source code analysis.
Markus Elfring (2):
Delete an error message for a failed memory allocation
Improve a size determination
drivers/pinctrl/nomadik/pinctrl-abx500.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
--
2.15.1
^ permalink raw reply
* [PATCH 1/2] pinctrl/nomadik/abx500: Delete an error message for a failed memory allocation in abx500_gpio_probe()
From: SF Markus Elfring @ 2017-12-20 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e5be1da7-460d-a47d-59b8-c1902907f5a4@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Wed, 20 Dec 2017 10:12:56 +0100
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/pinctrl/nomadik/pinctrl-abx500.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index b32c0d602024..feb030d1ea63 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -1157,11 +1157,8 @@ static int abx500_gpio_probe(struct platform_device *pdev)
pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
GFP_KERNEL);
- if (pct == NULL) {
- dev_err(&pdev->dev,
- "failed to allocate memory for pct\n");
+ if (!pct)
return -ENOMEM;
- }
pct->dev = &pdev->dev;
pct->parent = dev_get_drvdata(pdev->dev.parent);
--
2.15.1
^ permalink raw reply related
* [PATCH 2/2] pinctrl/nomadik/abx500: Improve a size determination in abx500_gpio_probe()
From: SF Markus Elfring @ 2017-12-20 9:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e5be1da7-460d-a47d-59b8-c1902907f5a4@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Wed, 20 Dec 2017 10:22:53 +0100
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/pinctrl/nomadik/pinctrl-abx500.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index feb030d1ea63..7d00a5d864f5 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -1155,8 +1155,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
return -ENODEV;
}
- pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
- GFP_KERNEL);
+ pct = devm_kzalloc(&pdev->dev, sizeof(*pct), GFP_KERNEL);
if (!pct)
return -ENOMEM;
--
2.15.1
^ permalink raw reply related
* [PATCH] ARM: NOMMU: Setup VBAR/Hivecs for secondaries cores
From: Vladimir Murzin @ 2017-12-20 9:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220045219.GA6416@afzalpc>
Hi,
On 20/12/17 04:52, afzal mohammed wrote:
> Hi,
>
> On Tue, Dec 19, 2017 at 02:44:01PM +0000, Vladimir Murzin wrote:
>
>>> Was the issue observed on Cortex-R ?, and was it occuring with
>>> CONFIG_CPU_HIGH_VECTOR enabled or disabled ?
>>
>> I caught it when was trying to setup VBAR and after code inspection I
>> noticed that setting of Hivecs were changed as well.
>
> Thinking again about this, should the Hivecs setting on secondary
> CPU's be done (till a requirement comes) ?
>
> ARM ARM deprecates using Hivecs setting on ARMv7-R, so this issue
> might not be hit in practice for R class. While pre-ARMv7, lack of
> Hivecs setting for secondaries, it seems can affect only ARMv6k
> (multi-processing support added here ?) and i am making a guess that
> even if there are ARMv6k with more than one core available, they might
> not yet have run with MMU disabled to hit this case, probably the
> reason no one has reported issue for long.
I've just reported an issue, no? :)
>
> Perhaps, we can avoid configuring Hivecs for secondaries until some
> one needs it ?
Well, before ad475117d201, Hivec would be enabled for secondaries via
secondary_startup
-> __after_proc_init
after that commit it is not true, so it is kind of regression.
Additionally, patch is not about Hivec only, but VBAR as well and TBH I
don't follow what is your proposal...
Cheers
Vladimir
>
> afzal
>
^ permalink raw reply
* [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
From: Simon Horman @ 2017-12-20 9:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513103111-45830-6-git-send-email-biju.das@bp.renesas.com>
On Tue, Dec 12, 2017 at 06:25:11PM +0000, Biju Das wrote:
> This patch enables SGTL5000 audio codec on the carrier board.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Somehow I missed applying this one.
I have now done so with the minor update noted below.
> ---
> arch/arm/boot/dts/iwg20d-q7-common.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> index 54470c6..2070b14 100644
> --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> @@ -20,6 +20,20 @@
> stdout-path = "serial0:115200n8";
> };
>
> + audio_clock: audio_clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> +
> + reg_1p5v: 1p5v {
> + compatible = "regulator-fixed";
> + regulator-name = "1P5V";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> +
> vcc_sdhi1: regulator-vcc-sdhi1 {
> compatible = "regulator-fixed";
>
> @@ -83,6 +97,16 @@
> compatible = "ti,bq32000";
> reg = <0x68>;
> };
> +
> + sgtl5000: codec at 0a {
s/@0a/@a/
Base addresses should not have a leading 0.
# make dtbs W=1
DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (unit_address_format): Node /soc/i2c at e6530000/codec at 0a unit name should not have leading 0s
> + compatible = "fsl,sgtl5000";
> + #sound-dai-cells = <0>;
> + reg = <0x0a>;
> + clocks = <&audio_clock>;
> + VDDA-supply = <®_3p3v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p5v>;
> + };
> };
>
> &pci0 {
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH] ARM: dts: at91: sama5d2_ptc_ek: use TCB0 as timers
From: Alexandre Belloni @ 2017-12-20 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220090440.18153-1-nicolas.ferre@microchip.com>
On 20/12/2017 at 10:04:40 +0100, Nicolas Ferre wrote:
> Use tcb0 for timers as selected in sama5_defconfig.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> ---
> Hi Alex,
>
> Adding the newly added sama5d2_ptc_ek to the series.
> Not tested though.
>
> Regards,
> Nicolas
>
> arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
Applied, thanks.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: r8a7743: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdVNCyW=QU08eg=1j8Xyq1wBhsY6KxmpjCLi8X7mZD8YCw@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:43:06AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Sort root sub-nodes alphabetically for allow for easier maintenance
>
> to allow for
>
> > of this file.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/arch/arm/boot/dts/r8a7743.dtsi
> > +++ b/arch/arm/boot/dts/r8a7743.dtsi
>
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -79,6 +102,37 @@
> > };
> > };
> >
> > + /* External CAN clock */
> > + can_clk: can {
>
> Doesn't look alphabetically to me...
Thanks, I have applied the following:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7743: sort root sub-nodes alphabetically
Sort root sub-nodes alphabetically to allow for easier maintenance
of this file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7743.dtsi | 100 ++++++++++++++++++++++-------------------
1 file changed, 54 insertions(+), 46 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index f24f36d50e40..067e339f6646 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -37,6 +37,37 @@
vin2 = &vin2;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -79,6 +110,29 @@
};
};
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -1629,56 +1683,10 @@
clock-frequency = <0>;
};
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
};
--
2.11.0
^ permalink raw reply related
* [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
From: Biju Das @ 2017-12-20 10:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220095806.jqtkmximxybsq6tr@verge.net.au>
Thanks Simon for this information.
Next time I will make sure that compiler won't give any warning message with make dtbs W=1
Regards,
Biju
> -----Original Message-----
> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 20 December 2017 09:58
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Russell King <linux@armlinux.org.uk>; Magnus
> Damm <magnus.damm@gmail.com>; Chris Paterson
> <Chris.Paterson2@renesas.com>; devicetree at vger.kernel.org; linux-renesas-
> soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000
> audio codec
>
> On Tue, Dec 12, 2017 at 06:25:11PM +0000, Biju Das wrote:
> > This patch enables SGTL5000 audio codec on the carrier board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Somehow I missed applying this one.
> I have now done so with the minor update noted below.
>
> > ---
> > arch/arm/boot/dts/iwg20d-q7-common.dtsi | 24
> ++++++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > index 54470c6..2070b14 100644
> > --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > @@ -20,6 +20,20 @@
> > stdout-path = "serial0:115200n8";
> > };
> >
> > +audio_clock: audio_clock {
> > +compatible = "fixed-clock";
> > +#clock-cells = <0>;
> > +clock-frequency = <26000000>;
> > +};
> > +
> > +reg_1p5v: 1p5v {
> > +compatible = "regulator-fixed";
> > +regulator-name = "1P5V";
> > +regulator-min-microvolt = <1500000>;
> > +regulator-max-microvolt = <1500000>;
> > +regulator-always-on;
> > +};
> > +
> > vcc_sdhi1: regulator-vcc-sdhi1 {
> > compatible = "regulator-fixed";
> >
> > @@ -83,6 +97,16 @@
> > compatible = "ti,bq32000";
> > reg = <0x68>;
> > };
> > +
> > +sgtl5000: codec at 0a {
>
> s/@0a/@a/
>
> Base addresses should not have a leading 0.
>
> # make dtbs W=1
> DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
> arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (unit_address_format):
> Node /soc/i2c at e6530000/codec at 0a unit name should not have leading 0s
>
> > +compatible = "fsl,sgtl5000";
> > +#sound-dai-cells = <0>;
> > +reg = <0x0a>;
> > +clocks = <&audio_clock>;
> > +VDDA-supply = <®_3p3v>;
> > +VDDIO-supply = <®_3p3v>;
> > +VDDD-supply = <®_1p5v>;
> > +};
> > };
> >
> > &pci0 {
> > --
> > 1.9.1
> >
[https://www2.renesas.eu/media/email/unicef_2017.jpg]
This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: r8a7743: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 10:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220100131.u5bjyce3mp2rj7cx@verge.net.au>
On Wed, Dec 20, 2017 at 11:01:32AM +0100, Simon Horman wrote:
> On Tue, Dec 19, 2017 at 09:43:06AM +0100, Geert Uytterhoeven wrote:
> > Hi Simon,
> >
> > On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
> > <horms+renesas@verge.net.au> wrote:
> > > Sort root sub-nodes alphabetically for allow for easier maintenance
> >
> > to allow for
> >
> > > of this file.
> > >
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > > --- a/arch/arm/boot/dts/r8a7743.dtsi
> > > +++ b/arch/arm/boot/dts/r8a7743.dtsi
> >
> > > cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > @@ -79,6 +102,37 @@
> > > };
> > > };
> > >
> > > + /* External CAN clock */
> > > + can_clk: can {
> >
> > Doesn't look alphabetically to me...
>
> Thanks, I have applied the following:
Yikes, that left a duplicate extal node.
I now have this:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7743: sort root sub-nodes alphabetically
Sort root sub-nodes alphabetically to allow for easier maintenance
of this file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7743.dtsi | 108 ++++++++++++++++++++---------------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index f24f36d50e40..ecbd39e5f630 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -37,6 +37,37 @@
vin2 = &vin2;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -79,6 +110,29 @@
};
};
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -1621,64 +1675,10 @@
};
};
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
};
--
2.11.0
^ permalink raw reply related
* [PATCH v2 2/2] ARM: dts: r8a7743: move timer node out of bus
From: Simon Horman @ 2017-12-20 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdXtfMnSQ90GsDQtK0ApM0ijtV44rQFBC86mj2Aj0S_ArQ@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:43:53AM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > The timer node does not have any register properties and thus shouldn't be
> > placed on the bus.
> >
> > This problem is flagged by the compiler as follows:
> > $ make
> > DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
> > arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > DTC arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb
> > arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks. I took the liberty of updating the patch to also move the
thermal-zones node, which was added by another patch earlier today.
The result I have queued up is as follows:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7743: move timer and thermal-zones nodes out of
bus
The timer and thermal-zones nodes do not have any register properties and
thus shouldn't be placed on the bus.
This problem is flagged by the compiler as follows:
$ make
DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
DTC arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb
arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7743.dtsi | 60 ++++++++++++++++++++----------------------
1 file changed, 28 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index ecbd39e5f630..0b74c6c7d21d 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -316,38 +316,6 @@
#thermal-sensor-cells = <0>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
-
- cooling-maps {
- };
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>;
- };
-
cmt0: timer at ffca0000 {
compatible = "renesas,r8a7743-cmt0",
"renesas,rcar-gen2-cmt0";
@@ -1675,6 +1643,34 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
--
2.11.0
^ permalink raw reply related
* [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
From: Simon Horman @ 2017-12-20 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <KL1PR06MB1702453058AFB66AA8110825B80C0@KL1PR06MB1702.apcprd06.prod.outlook.com>
On Wed, Dec 20, 2017 at 10:02:54AM +0000, Biju Das wrote:
> Thanks Simon for this information.
>
> Next time I will make sure that compiler won't give any warning message with make dtbs W=1
Thanks, I've been on a bit of a mission to clean up such warnings of late.
^ permalink raw reply
* [GIT PULL] ARM: at91: Fixes for 4.15
From: Alexandre Belloni @ 2017-12-20 10:16 UTC (permalink / raw)
To: linux-arm-kernel
Arnd, Olof,
A single fix for 4.15. The driver part of it will land in 4.15 through
the hwmon tree.
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git tags/at91-ab-4.15-dt-fixes
for you to fetch changes up to bc53e3aa88e8240823c1c440e6bab3c3a5ba5f59:
ARM: dts: at91: disable the nxp,se97b SMBUS timeout on the TSE-850 (2017-12-04 20:30:38 +0100)
----------------------------------------------------------------
Fixes for 4.15:
- tse850-3: fix an i2c timeout issue
----------------------------------------------------------------
Peter Rosin (1):
ARM: dts: at91: disable the nxp,se97b SMBUS timeout on the TSE-850
arch/arm/boot/dts/at91-tse850-3.dts | 1 +
1 file changed, 1 insertion(+)
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
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