* [PATCH 1/2] mmc: sunxi: Reorder the headers
From: Maxime Ripard @ 2017-12-20 10:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.ac66a754953bedbb7529436b40a7996f4ba3cb95.1513766964.git-series.maxime.ripard@free-electrons.com>
Our headers sort algorithm has had pretty chaotic results. Let's fix that.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
---
drivers/mmc/host/sunxi-mmc.c | 43 +++++++++++++++++--------------------
1 file changed, 20 insertions(+), 23 deletions(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index cc98355dbdb9..3ce46ebd3488 100644
--- a/drivers/mmc/host/sunxi-mmc.c
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -13,36 +13,33 @@
* the License, or (at your option) any later version.
*/
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/io.h>
-#include <linux/device.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/err.h>
-
#include <linux/clk.h>
#include <linux/clk/sunxi-ng.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/spinlock.h>
-#include <linux/scatterlist.h>
+#include <linux/delay.h>
+#include <linux/device.h>
#include <linux/dma-mapping.h>
-#include <linux/slab.h>
-#include <linux/reset.h>
-#include <linux/regulator/consumer.h>
-
-#include <linux/of_address.h>
-#include <linux/of_gpio.h>
-#include <linux/of_platform.h>
-
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/mmc.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sd.h>
#include <linux/mmc/sdio.h>
-#include <linux/mmc/mmc.h>
-#include <linux/mmc/core.h>
-#include <linux/mmc/card.h>
#include <linux/mmc/slot-gpio.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/consumer.h>
+#include <linux/reset.h>
+#include <linux/scatterlist.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
/* register offset definitions */
#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
--
git-series 0.9.1
^ permalink raw reply related
* [PATCH 0/2] mmc: sunxi: Add runtime PM support
From: Maxime Ripard @ 2017-12-20 10:50 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Since it's introduction, our MMC controller has had its external clocks
running all the time.
While that was working great, the power usage and most importantly the EMI
that it generated was pretty bad.
Let's implement some runtime_pm hooks with an autosuspend to cut the
external clock when the MMC is not active.
I didn't get all the way to also shutdown the bus clocks since on some
older SoCs (before the A31), it also means that the controler will be reset
which has some quite important implications obviously. And I couldn't make
it work reliably at the moment. Anyway, it can always be implemented as a
second step if needed.
(Quite simple) benchmarks have shown no noticeable regressions since the
controller state is maintained.
Let me know what you think,
Maxime
Maxime Ripard (2):
mmc: sunxi: Reorder the headers
mmc: sunxi: Add runtime_pm support
drivers/mmc/host/sunxi-mmc.c | 133 +++++++++++++++++++++---------------
1 file changed, 80 insertions(+), 53 deletions(-)
base-commit: 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323
--
git-series 0.9.1
^ permalink raw reply
* [PATCH v4] staging: fsl-mc: move bus driver out of staging
From: Greg KH @ 2017-12-20 10:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5A3A3AE6.6080905@nxp.com>
On Wed, Dec 20, 2017 at 10:26:49AM +0000, Laurentiu Tudor wrote:
> On 12/19/2017 06:10 PM, Greg KH wrote:
> >>> But all of these .h files are only used by the code in this specific
> >>> directory, no where else.
> >>
> >> They are also used by our ethernet driver, see:
> >> drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
> >
> > Ick, really? Then they should not be buried in a bus-specific
> > location, but rather be in include/linux/SOMEWHERE, right?
>
> Right. The goal is that in the end, all headers be moved to the already
> existing include/linux/fsl/. For now I've left these in staging because
> they are not part of the bus "core" infrastructure.
Then shouldn't they be in the drivers/staging/fsl-mc/include/ directory
now to show this?
thanks,
greg k-h
^ permalink raw reply
* Linux Kernel handling AXI DECERR/SLVERR
From: Bharat Kumar Gogada @ 2017-12-20 10:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219113848.6dpb3fosbznguala@lakrids.cambridge.arm.com>
On Tue, Dec 19, 2017 at 11:28:49AM +0000, Bharat Kumar Gogada wrote:
> In our case the peripheral returns SLVERR first time and we see the following print but kernel do not hang.
> [ 231.484186] Unhandled fault: synchronous external abort
> (0x92000210) at 0x0000007f9241f880 Bus error
>
> And from simulation we know that subsequent access to peripheral
> returns OKAY response, however we see subsequent access fail with same
> above bus error when we boot Linux.
>
> Is there a way to handle these synchronous abort gracefully in Linux
> or are these fatal ?
We don't currently have any mechanism to handle these, though it might be possible for synchronous abort.
Since currently there is no mechanism to handle, if once synchronous abort is received from a peripheral,
consecutive access will show up same error even peripheral responds with OKAY ?
What are the possible ways for handling these ?
Do you know why the device is returning SLVERR in this case?
There is an error being detected by the device.
Bharat
^ permalink raw reply
* [PATCH V1 1/1] iommu: Make sure device's ID array elements are unique
From: Tomasz Nowicki @ 2017-12-20 10:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219093726.432e16e7@t450s.home>
On 19.12.2017 17:37, Alex Williamson wrote:
> On Tue, 19 Dec 2017 16:20:21 +0100
> Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com> wrote:
>
>> While iterating over DMA aliases for a PCI device, for some rare cases
>> (i.e. PCIe-to-PCI/X bridges) we may get exactly the same ID as initial child
>> device. In turn, the same ID may get registered for a device multiple times.
>> Eventually IOMMU driver may try to configure the same ID within domain
>> multiple times too which for some IOMMU drivers is illegal and causes kernel
>> panic.
>>
>> Rule out ID duplication prior to device ID array registration.
>>
>> CC: stable at vger.kernel.org # v4.14+
>
> You've identified a release, is there a specific commit this fixes?
Yes, it was triggered by converting drm_pci_init() to
pci_register_driver() in ast_drv.c
Fixes: 10631d724def ("drm/pci: Deprecate drm_pci_init/exit completely
")
>
>> Signed-off-by: Tomasz Nowicki <tomasz.nowicki@caviumnetworks.com>
>> ---
>> drivers/iommu/iommu.c | 28 ++++++++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>>
>> diff --git a/drivers/iommu/iommu.c b/drivers/iommu/iommu.c
>> index 3de5c0b..9b2c138 100644
>> --- a/drivers/iommu/iommu.c
>> +++ b/drivers/iommu/iommu.c
>> @@ -1945,6 +1945,31 @@ void iommu_fwspec_free(struct device *dev)
>> }
>> EXPORT_SYMBOL_GPL(iommu_fwspec_free);
>>
>> +static void iommu_fwspec_remove_ids_dup(struct device *dev, u32 *ids,
>> + int *num_ids)
>> +{
>> + struct iommu_fwspec *fwspec = dev->iommu_fwspec;
>> + int i, j, k, valid_ids = *num_ids;
>> +
>> + for (i = 0; i < valid_ids; i++) {
>> + for (j = 0; j < fwspec->num_ids; j++) {
>> + if (ids[i] != fwspec->ids[j])
>> + continue;
>> +
>> + dev_info(dev, "found 0x%x ID duplication, skipped\n",
>> + ids[i]);
>> +
>> + for (k = i + 1; k < valid_ids; k++)
>> + ids[k - 1] = ids[k];
>
> Use memmove()?
Right.
>
>> +
>> + valid_ids--;
>> + break;
>
> At this point ids[i] is not the ids[i] that we tested for dupes, it's
> what was ids[i + 1], but we're going to i++ on the next iteration and
> we therefore never test that entry.
Good point.
Now the fundamental question is where we should put the patch, here or
in SMMUv3 driver as per Robin suggestion.
Thanks,
Tomasz
^ permalink raw reply
* [PATCH V1 0/1] Fix kernel panic caused by device ID duplication presented to the IOMMU
From: Tomasz Nowicki @ 2017-12-20 10:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <7f7fca76-88f8-6ee7-c402-fe4300c62253@arm.com>
Hi Robin,
On 19.12.2017 17:34, Robin Murphy wrote:
> Hi Tomasz,
>
> On 19/12/17 15:13, Tomasz Nowicki wrote:
>> Here is my lspci output of ThunderX2 for which I am observing kernel
>> panic coming from
>> SMMUv3 driver -> arm_smmu_write_strtab_ent() -> BUG_ON(ste_live):
>>
>> # lspci -vt
>> -[0000:00]-+-00.0-[01-1f]--+ [...]
>> ??????????????????????????? + [...]
>> ??????????????????????????? \-00.0-[1e-1f]----00.0-[1f]----00.0
>> ASPEED Technology, Inc. ASPEED Graphics Family
>>
>> ASP device -> 1f:00.0 VGA compatible controller: ASPEED Technology,
>> Inc. ASPEED Graphics Family
>> PCI-Express to PCI/PCI-X Bridge -> 1e:00.0 PCI bridge: ASPEED
>> Technology, Inc. AST1150 PCI-to-PCI Bridge
>> While setting up ASP device SID in IORT dirver:
>> iort_iommu_configure() -> pci_for_each_dma_alias()
>> we need to walk up and iterate over each device which alias
>> transaction from
>> downstream devices.
>>
>> AST device (1f:00.0) gets BDF=0x1f00 and corresponding SID=0x1f00 from
>> IORT.
>> Bridge (1e:00.0) is the first alias. Following PCI Express to
>> PCI/PCI-X Bridge
>> spec: PCIe-to-PCI/X bridges alias transactions from downstream devices
>> using
>> the subordinate bus number. For bridge (1e:00.0), the subordinate is
>> equal
>> to 0x1f. This gives BDF=0x1f00 and SID=1f00 which is the same as
>> downstream
>> device. So it is possible to have two identical SIDs. The question is
>> what we
>> should do about such case. Presented patch prevents from registering
>> the same
>> ID so that SMMUv3 is not complaining later on.
>
> Ooh, subtle :( There is logic in arm_smmu_attach_device() to tolerate
> grouped devices aliasing to the same ID, but I guess I overlooked the
> distinction of a device sharing an alias ID with itself. I'm not sure
> I really like trying to work around this in generic code, since
> fwspec->ids is essentially opaque data in a driver-specific format - in
> theory a driver is free to encode a single logical ID into multiple
> fwspec elements (I think I did that in an early draft of SMMUv2 SMR
> support), at which point this approach might corrupt things massively.
I don't have strong favourite here, the fix in SMMUv3 driver would work
too. Initially we can fix things for SMMUv3 only and if ever face the
same issue for other IOMMU driver, then we can move it to generic layer.
>
> Does the (untested) diff below suffice?
>
> Robin.
>
> ----->8-----diff --git a/drivers/iommu/arm-smmu-v3.c
> b/drivers/iommu/arm-smmu-v3.c
> index f122071688fd..d8a730d83401 100644
> --- a/drivers/iommu/arm-smmu-v3.c
> +++ b/drivers/iommu/arm-smmu-v3.c
> @@ -1731,7 +1731,7 @@ static __le64 *arm_smmu_get_step_for_sid(struct
> arm_smmu_device *smmu, u32 sid)
>
> ?static void arm_smmu_install_ste_for_dev(struct iommu_fwspec *fwspec)
> ?{
> -??? int i;
> +??? int i, j;
> ???? struct arm_smmu_master_data *master = fwspec->iommu_priv;
> ???? struct arm_smmu_device *smmu = master->smmu;
>
> @@ -1739,6 +1739,13 @@ static void arm_smmu_install_ste_for_dev(struct
> iommu_fwspec *fwspec)
> ???????? u32 sid = fwspec->ids[i];
> ???????? __le64 *step = arm_smmu_get_step_for_sid(smmu, sid);
>
> +??????? /* Bridged PCI devices may end up with duplicated IDs */
> +??????? for (j = 0; j < i; j++)
> +??????????? if (fwspec->ids[j] == sid)
> +??????????????? break;
> +??????? if (j < i)
> +??????????? continue;
> +
> ???????? arm_smmu_write_strtab_ent(smmu, sid, step, &master->ste);
> ???? }
> ?}
Yes, worked for me.
Thanks,
Tomasz
^ permalink raw reply
* [PATCH v5 06/11] thermal: armada: Add support for Armada AP806
From: Gregory CLEMENT @ 2017-12-20 10:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219135719.9531-7-miquel.raynal@free-electrons.com>
Hi Miquel,
On mar., d?c. 19 2017, Miquel Raynal <miquel.raynal@free-electrons.com> wrote:
> From: Baruch Siach <baruch@tkos.co.il>
>
> The AP806 component is integrated in the Armada 8K and 7K lines of
> processors.
>
> The thermal sensor sample field on the status register is a signed
> value. Extend armada_get_temp() and the driver structure to handle
> signed values.
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> [<miquel.raynal@free-electrons.com>: Changes when applying over the
> previous patches, including the register names changes, also switched
> the coefficients values to s64 instead of unsigned long to deal with
> negative values and used do_div instead of the traditionnal '/']
> Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
> Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
> ---
> drivers/thermal/armada_thermal.c | 74 ++++++++++++++++++++++++++++++++--------
> 1 file changed, 59 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/thermal/armada_thermal.c b/drivers/thermal/armada_thermal.c
> index ceebabf45c53..c7dcac39cbf9 100644
> --- a/drivers/thermal/armada_thermal.c
> +++ b/drivers/thermal/armada_thermal.c
> @@ -47,6 +47,11 @@
> #define CONTROL0_OFFSET 0x0
> #define CONTROL1_OFFSET 0x4
>
> +/* TSEN refers to the temperature sensors within the AP */
> +#define CONTROL0_TSEN_START BIT(0)
> +#define CONTROL0_TSEN_RESET BIT(1)
> +#define CONTROL0_TSEN_ENABLE BIT(2)
> +
> struct armada_thermal_data;
>
> /* Marvell EBU Thermal Sensor Dev Structure */
> @@ -66,10 +71,11 @@ struct armada_thermal_data {
> bool (*is_valid)(struct armada_thermal_priv *);
>
> /* Formula coeficients: temp = (b - m * reg) / div */
> - unsigned long coef_b;
> - unsigned long coef_m;
> - unsigned long coef_div;
> + s64 coef_b;
> + s64 coef_m;
> + u32 coef_div;
> bool inverted;
> + bool signed_sample;
>
> /* Register shift and mask to access the sensor temperature */
> unsigned int temp_shift;
> @@ -155,6 +161,18 @@ static void armada380_init_sensor(struct platform_device *pdev,
> }
> }
>
> +static void armada_ap806_init_sensor(struct platform_device *pdev,
> + struct armada_thermal_priv *priv)
> +{
> + u32 reg;
> +
> + reg = readl_relaxed(priv->control0);
> + reg &= ~CONTROL0_TSEN_RESET;
> + reg |= CONTROL0_TSEN_START | CONTROL0_TSEN_ENABLE;
> + writel(reg, priv->control0);
> + msleep(10);
> +}
> +
> static bool armada_is_valid(struct armada_thermal_priv *priv)
> {
> u32 reg = readl_relaxed(priv->status);
> @@ -166,8 +184,8 @@ static int armada_get_temp(struct thermal_zone_device *thermal,
> int *temp)
> {
> struct armada_thermal_priv *priv = thermal->devdata;
> - unsigned long reg;
> - unsigned long m, b, div;
> + u32 reg, div;
> + s64 sample, b, m;
>
> /* Valid check */
> if (priv->data->is_valid && !priv->data->is_valid(priv)) {
> @@ -178,6 +196,11 @@ static int armada_get_temp(struct thermal_zone_device *thermal,
>
> reg = readl_relaxed(priv->status);
> reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
> + if (priv->data->signed_sample)
> + /* The most significant bit is the sign bit */
> + sample = sign_extend32(reg, fls(priv->data->temp_mask) - 1);
> + else
> + sample = reg;
>
> /* Get formula coeficients */
> b = priv->data->coef_b;
> @@ -185,9 +208,12 @@ static int armada_get_temp(struct thermal_zone_device *thermal,
> div = priv->data->coef_div;
>
> if (priv->data->inverted)
> - *temp = ((m * reg) - b) / div;
> + *temp = (m * sample) - b;
> else
> - *temp = (b - (m * reg)) / div;
> + *temp = b - (m * sample);
> +
> + do_div(*temp, div);
I wanted to test in on ARMv7 and this line failed to compile:
In file included from arch/arm/include/asm/div64.h:127:0,
from include/linux/kernel.h:173,
from include/linux/list.h:9,
from include/linux/kobject.h:20,
from include/linux/device.h:17,
from drivers/thermal/armada_thermal.c:16:
drivers/thermal/armada_thermal.c: In function ?armada_get_temp?:
include/asm-generic/div64.h:208:28: warning: comparison of distinct pointer types lacks a cast
(void)(((typeof((n)) *)0) == ((uint64_t *)0)); \
^
drivers/thermal/armada_thermal.c:247:2: note: in expansion of macro ?do_div?
do_div(*temp, div);
^~~~~~
In file included from include/linux/ioport.h:13:0,
from include/linux/device.h:16,
from drivers/thermal/armada_thermal.c:16:
include/asm-generic/div64.h:221:25: warning: right shift count >= width of type [-Wshift-count-overflow]
} else if (likely(((n) >> 32) == 0)) { \
^
include/linux/compiler.h:175:40: note: in definition of macro ?likely?
# define likely(x) __builtin_expect(!!(x), 1)
^
drivers/thermal/armada_thermal.c:247:2: note: in expansion of macro ?do_div?
do_div(*temp, div);
^~~~~~
In file included from arch/arm/include/asm/div64.h:127:0,
from include/linux/kernel.h:173,
from include/linux/list.h:9,
from include/linux/kobject.h:20,
from include/linux/device.h:17,
from drivers/thermal/armada_thermal.c:16:
include/asm-generic/div64.h:225:22: error: passing argument 1 of ?__div64_32? from incompatible pointer type [-Werror=incompatible-pointer-types]
__rem = __div64_32(&(n), __base); \
^
drivers/thermal/armada_thermal.c:247:2: note: in expansion of macro ?do_div?
do_div(*temp, div);
^~~~~~
In file included from include/linux/kernel.h:173:0,
from include/linux/list.h:9,
from include/linux/kobject.h:20,
from include/linux/device.h:17,
from drivers/thermal/armada_thermal.c:16:
arch/arm/include/asm/div64.h:33:24: note: expected ?uint64_t * {aka long long unsigned int *}? but argument is of type ?int *?
static inline uint32_t __div64_32(uint64_t *n, uint32_t base)
Gregory
> +
> return 0;
> }
>
> @@ -199,8 +225,8 @@ static const struct armada_thermal_data armadaxp_data = {
> .init_sensor = armadaxp_init_sensor,
> .temp_shift = 10,
> .temp_mask = 0x1ff,
> - .coef_b = 3153000000UL,
> - .coef_m = 10000000UL,
> + .coef_b = 3153000000ULL,
> + .coef_m = 10000000ULL,
> .coef_div = 13825,
> };
>
> @@ -210,8 +236,8 @@ static const struct armada_thermal_data armada370_data = {
> .is_valid_bit = BIT(9),
> .temp_shift = 10,
> .temp_mask = 0x1ff,
> - .coef_b = 3153000000UL,
> - .coef_m = 10000000UL,
> + .coef_b = 3153000000ULL,
> + .coef_m = 10000000ULL,
> .coef_div = 13825,
> };
>
> @@ -221,8 +247,8 @@ static const struct armada_thermal_data armada375_data = {
> .is_valid_bit = BIT(10),
> .temp_shift = 0,
> .temp_mask = 0x1ff,
> - .coef_b = 3171900000UL,
> - .coef_m = 10000000UL,
> + .coef_b = 3171900000ULL,
> + .coef_m = 10000000ULL,
> .coef_div = 13616,
> .needs_control0 = true,
> };
> @@ -233,12 +259,26 @@ static const struct armada_thermal_data armada380_data = {
> .is_valid_bit = BIT(10),
> .temp_shift = 0,
> .temp_mask = 0x3ff,
> - .coef_b = 1172499100UL,
> - .coef_m = 2000096UL,
> + .coef_b = 1172499100ULL,
> + .coef_m = 2000096ULL,
> .coef_div = 4201,
> .inverted = true,
> };
>
> +static const struct armada_thermal_data armada_ap806_data = {
> + .is_valid = armada_is_valid,
> + .init_sensor = armada_ap806_init_sensor,
> + .is_valid_bit = BIT(16),
> + .temp_shift = 0,
> + .temp_mask = 0x3ff,
> + .coef_b = -150000LL,
> + .coef_m = 423ULL,
> + .coef_div = 1,
> + .inverted = true,
> + .signed_sample = true,
> + .needs_control0 = true,
> +};
> +
> static const struct of_device_id armada_thermal_id_table[] = {
> {
> .compatible = "marvell,armadaxp-thermal",
> @@ -257,6 +297,10 @@ static const struct of_device_id armada_thermal_id_table[] = {
> .data = &armada380_data,
> },
> {
> + .compatible = "marvell,armada-ap806-thermal",
> + .data = &armada_ap806_data,
> + },
> + {
> /* sentinel */
> },
> };
> --
> 2.11.0
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH v4] staging: fsl-mc: move bus driver out of staging
From: Laurentiu Tudor @ 2017-12-20 10:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219161045.GA18839@kroah.com>
On 12/19/2017 06:10 PM, Greg KH wrote:
> On Tue, Dec 19, 2017 at 03:39:44PM +0000, Laurentiu Tudor wrote:
>> On 12/19/2017 05:29 PM, Greg KH wrote:
>>> On Tue, Dec 19, 2017 at 03:21:19PM +0000, Laurentiu Tudor wrote:
>>>>
>>>>
>>>> On 12/19/2017 04:48 PM, Greg KH wrote:
>>>>> On Wed, Nov 29, 2017 at 12:08:44PM +0200, laurentiu.tudor at nxp.com wrote:
>>>>>> From: Stuart Yoder <stuart.yoder@nxp.com>
>>>>>>
>>>>>> Move the source files out of staging into their final locations:
>>>>>> -include files in drivers/staging/fsl-mc/include go to include/linux/fsl
>>>>>> -irq-gic-v3-its-fsl-mc-msi.c goes to drivers/irqchip
>>>>>> -source in drivers/staging/fsl-mc/bus goes to drivers/bus/fsl-mc
>>>>>> -README.txt, providing and overview of DPAA goes to
>>>>>> Documentation/dpaa2/overview.txt
>>>>>>
>>>>>> Update or delete other remaining staging files-- Makefile, Kconfig, TODO.
>>>>>> Update dpaa2_eth and dpio staging drivers.
>>>>>>
>>>>>> Signed-off-by: Stuart Yoder <stuyoder@gmail.com>
>>>>>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>>>>> [Laurentiu: rebased, add dpaa2_eth and dpio #include updates]
>>>>>> Cc: Thomas Gleixner <tglx@linutronix.de>
>>>>>> Cc: Jason Cooper <jason@lakedaemon.net>
>>>>>> Cc: Marc Zyngier <marc.zyngier@arm.com>
>>>>>> ---
>>>>>> Notes:
>>>>>> -v4:
>>>>>> - regenerated patch with renames detection disabled (Andrew Lunn)
>>>>>> -v3:
>>>>>> - rebased
>>>>>
>>>>> Ok, meta-comments on the structure of the code.
>>>>>
>>>>> You have 8 .h files that are "private" to your bus logic. That's 7 too
>>>>> many, some of them have a bigger license header than actual content :)
>>>>>
>>>>> Please consolidate into 1.
>>>>>
>>>>> Also, the headers should be moved to SPDX format to get rid of the
>>>>> boilerplate. I _think_ it's BSD/GPL, right? Hard to tell :(
>>>>
>>>> It's 3-clause BSD and GPLv2. Will make it clear when moving to SPDX.
>>>
>>> Thanks.
>>>
>>>>> Your "public" .h file does not need to go into a subdirectory, just name
>>>>> it fsl-mc.h and put it in include/linux/.
>>>>
>>>> There's already a "fsl" subdirectory in include/linux/ so it seemed to
>>>> make sense to use it.
>>>
>>> Ah, missed that. Ok, nevermind :)`
>>>
>>>>> One comment on the fields in your .h file, all of the user/kernel
>>>>> crossing boundry structures need to use the "__" variant of types, like
>>>>> "__u8" and the like. You mix and match them for some reason, you need
>>>>> to be consistent.
>>>>>
>>>>> Also, what's up with the .h files in drivers/staging/fsl-bus/include?
>>>>> You didn't touch those with this movement, right? Why?
>>>>
>>>> Those are not part of the bus "core". Some of them are part of the DPBP
>>>> and DPCON device types APIs and are used by drivers probing on this bus
>>>> and the rest are part of the DPIO driver which is also used by other
>>>> drivers. Since these devices (DPBP, DPCON, DPIO) are interfaces used by
>>>> all the other drivers it made sense to group them together with the bus.
>>>
>>> But all of these .h files are only used by the code in this specific
>>> directory, no where else.
>>
>> They are also used by our ethernet driver, see:
>> drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h
>
> Ick, really? Then they should not be buried in a bus-specific
> location, but rather be in include/linux/SOMEWHERE, right?
Right. The goal is that in the end, all headers be moved to the already
existing include/linux/fsl/. For now I've left these in staging because
they are not part of the bus "core" infrastructure.
---
Best Regards, Laurentiu
^ permalink raw reply
* [PATCH 00/13] replace print_symbol() with printk()-s
From: Sergey Senozhatsky @ 2017-12-20 10:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171211125025.2270-1-sergey.senozhatsky@gmail.com>
On (12/11/17 21:50), Sergey Senozhatsky wrote:
>
> A rather automatic replacement of print_symbol()
> with direct printk() calls. print_symbol() uses extra stack
> buffer (KSYM_SYMBOL_LEN 128 bytes) and, basically, should
> be identical to printk(%pS).
>
> I can't test all of the patches, because I don't
> own any of those exotic arch-s. Sorry for the inconvenience.
>
> Sergey Senozhatsky (13):
> arm: do not use print_symbol()
> arm64: do not use print_symbol()
> c6x: do not use print_symbol()
> ia64: do not use print_symbol()
> mn10300: do not use print_symbol()
> sh: do not use print_symbol()
> unicore32: do not use print_symbol()
> x86: do not use print_symbol()
> drivers: do not use print_symbol()
> sysfs: do not use print_symbol()
> irq debug: do not use print_symbol()
> lib: do not use print_symbol()
> arc: do not use __print_symbol()
Hello,
can we please have more reviews/acks/etc?
-ss
^ permalink raw reply
* [GIT PULL] ARM: at91: Fixes for 4.15
From: Alexandre Belloni @ 2017-12-20 10:16 UTC (permalink / raw)
To: linux-arm-kernel
Arnd, Olof,
A single fix for 4.15. The driver part of it will land in 4.15 through
the hwmon tree.
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git tags/at91-ab-4.15-dt-fixes
for you to fetch changes up to bc53e3aa88e8240823c1c440e6bab3c3a5ba5f59:
ARM: dts: at91: disable the nxp,se97b SMBUS timeout on the TSE-850 (2017-12-04 20:30:38 +0100)
----------------------------------------------------------------
Fixes for 4.15:
- tse850-3: fix an i2c timeout issue
----------------------------------------------------------------
Peter Rosin (1):
ARM: dts: at91: disable the nxp,se97b SMBUS timeout on the TSE-850
arch/arm/boot/dts/at91-tse850-3.dts | 1 +
1 file changed, 1 insertion(+)
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
From: Simon Horman @ 2017-12-20 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <KL1PR06MB1702453058AFB66AA8110825B80C0@KL1PR06MB1702.apcprd06.prod.outlook.com>
On Wed, Dec 20, 2017 at 10:02:54AM +0000, Biju Das wrote:
> Thanks Simon for this information.
>
> Next time I will make sure that compiler won't give any warning message with make dtbs W=1
Thanks, I've been on a bit of a mission to clean up such warnings of late.
^ permalink raw reply
* [PATCH v2 2/2] ARM: dts: r8a7743: move timer node out of bus
From: Simon Horman @ 2017-12-20 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdXtfMnSQ90GsDQtK0ApM0ijtV44rQFBC86mj2Aj0S_ArQ@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:43:53AM +0100, Geert Uytterhoeven wrote:
> On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > The timer node does not have any register properties and thus shouldn't be
> > placed on the bus.
> >
> > This problem is flagged by the compiler as follows:
> > $ make
> > DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
> > arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> > DTC arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb
> > arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks. I took the liberty of updating the patch to also move the
thermal-zones node, which was added by another patch earlier today.
The result I have queued up is as follows:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7743: move timer and thermal-zones nodes out of
bus
The timer and thermal-zones nodes do not have any register properties and
thus shouldn't be placed on the bus.
This problem is flagged by the compiler as follows:
$ make
DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
DTC arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb
arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/thermal-zones missing or empty reg/ranges property
arch/arm/boot/dts/r8a7743-sk-rzg1m.dtb: Warning (simple_bus_reg): Node /soc/timer missing or empty reg/ranges property
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7743.dtsi | 60 ++++++++++++++++++++----------------------
1 file changed, 28 insertions(+), 32 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index ecbd39e5f630..0b74c6c7d21d 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -316,38 +316,6 @@
#thermal-sensor-cells = <0>;
};
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <0>;
- polling-delay = <0>;
-
- thermal-sensors = <&thermal>;
-
- trips {
- cpu-crit {
- temperature = <95000>;
- hysteresis = <0>;
- type = "critical";
- };
- };
-
- cooling-maps {
- };
- };
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_LOW)>;
- };
-
cmt0: timer at ffca0000 {
compatible = "renesas,r8a7743-cmt0",
"renesas,rcar-gen2-cmt0";
@@ -1675,6 +1643,34 @@
};
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu-crit {
+ temperature = <95000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ };
+ };
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
+ <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
--
2.11.0
^ permalink raw reply related
* [PATCH v2 1/2] ARM: dts: r8a7743: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 10:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220100131.u5bjyce3mp2rj7cx@verge.net.au>
On Wed, Dec 20, 2017 at 11:01:32AM +0100, Simon Horman wrote:
> On Tue, Dec 19, 2017 at 09:43:06AM +0100, Geert Uytterhoeven wrote:
> > Hi Simon,
> >
> > On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
> > <horms+renesas@verge.net.au> wrote:
> > > Sort root sub-nodes alphabetically for allow for easier maintenance
> >
> > to allow for
> >
> > > of this file.
> > >
> > > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> >
> > Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > > --- a/arch/arm/boot/dts/r8a7743.dtsi
> > > +++ b/arch/arm/boot/dts/r8a7743.dtsi
> >
> > > cpus {
> > > #address-cells = <1>;
> > > #size-cells = <0>;
> > > @@ -79,6 +102,37 @@
> > > };
> > > };
> > >
> > > + /* External CAN clock */
> > > + can_clk: can {
> >
> > Doesn't look alphabetically to me...
>
> Thanks, I have applied the following:
Yikes, that left a duplicate extal node.
I now have this:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7743: sort root sub-nodes alphabetically
Sort root sub-nodes alphabetically to allow for easier maintenance
of this file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7743.dtsi | 108 ++++++++++++++++++++---------------------
1 file changed, 54 insertions(+), 54 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index f24f36d50e40..ecbd39e5f630 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -37,6 +37,37 @@
vin2 = &vin2;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -79,6 +110,29 @@
};
};
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -1621,64 +1675,10 @@
};
};
- /* External root clock */
- extal_clk: extal {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
};
--
2.11.0
^ permalink raw reply related
* [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
From: Biju Das @ 2017-12-20 10:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220095806.jqtkmximxybsq6tr@verge.net.au>
Thanks Simon for this information.
Next time I will make sure that compiler won't give any warning message with make dtbs W=1
Regards,
Biju
> -----Original Message-----
> From: Simon Horman [mailto:horms at verge.net.au]
> Sent: 20 December 2017 09:58
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: Rob Herring <robh+dt@kernel.org>; Mark Rutland
> <mark.rutland@arm.com>; Russell King <linux@armlinux.org.uk>; Magnus
> Damm <magnus.damm@gmail.com>; Chris Paterson
> <Chris.Paterson2@renesas.com>; devicetree at vger.kernel.org; linux-renesas-
> soc at vger.kernel.org; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000
> audio codec
>
> On Tue, Dec 12, 2017 at 06:25:11PM +0000, Biju Das wrote:
> > This patch enables SGTL5000 audio codec on the carrier board.
> >
> > Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> > Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
>
> Somehow I missed applying this one.
> I have now done so with the minor update noted below.
>
> > ---
> > arch/arm/boot/dts/iwg20d-q7-common.dtsi | 24
> ++++++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > index 54470c6..2070b14 100644
> > --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> > @@ -20,6 +20,20 @@
> > stdout-path = "serial0:115200n8";
> > };
> >
> > +audio_clock: audio_clock {
> > +compatible = "fixed-clock";
> > +#clock-cells = <0>;
> > +clock-frequency = <26000000>;
> > +};
> > +
> > +reg_1p5v: 1p5v {
> > +compatible = "regulator-fixed";
> > +regulator-name = "1P5V";
> > +regulator-min-microvolt = <1500000>;
> > +regulator-max-microvolt = <1500000>;
> > +regulator-always-on;
> > +};
> > +
> > vcc_sdhi1: regulator-vcc-sdhi1 {
> > compatible = "regulator-fixed";
> >
> > @@ -83,6 +97,16 @@
> > compatible = "ti,bq32000";
> > reg = <0x68>;
> > };
> > +
> > +sgtl5000: codec at 0a {
>
> s/@0a/@a/
>
> Base addresses should not have a leading 0.
>
> # make dtbs W=1
> DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
> arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (unit_address_format):
> Node /soc/i2c at e6530000/codec at 0a unit name should not have leading 0s
>
> > +compatible = "fsl,sgtl5000";
> > +#sound-dai-cells = <0>;
> > +reg = <0x0a>;
> > +clocks = <&audio_clock>;
> > +VDDA-supply = <®_3p3v>;
> > +VDDIO-supply = <®_3p3v>;
> > +VDDD-supply = <®_1p5v>;
> > +};
> > };
> >
> > &pci0 {
> > --
> > 1.9.1
> >
[https://www2.renesas.eu/media/email/unicef_2017.jpg]
This Christmas, instead of sending out cards, Renesas Electronics Europe have decided to support Unicef with a donation. For further details click here<https://www.unicef.org/> to find out about the valuable work they do, helping children all over the world.
We would like to take this opportunity to wish you a Merry Christmas and a prosperous New Year.
Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. Registered in England & Wales under Registered No. 04586709.
^ permalink raw reply
* [PATCH v2 1/2] ARM: dts: r8a7743: sort root sub-nodes alphabetically
From: Simon Horman @ 2017-12-20 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMuHMdVNCyW=QU08eg=1j8Xyq1wBhsY6KxmpjCLi8X7mZD8YCw@mail.gmail.com>
On Tue, Dec 19, 2017 at 09:43:06AM +0100, Geert Uytterhoeven wrote:
> Hi Simon,
>
> On Mon, Dec 18, 2017 at 10:40 PM, Simon Horman
> <horms+renesas@verge.net.au> wrote:
> > Sort root sub-nodes alphabetically for allow for easier maintenance
>
> to allow for
>
> > of this file.
> >
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> > --- a/arch/arm/boot/dts/r8a7743.dtsi
> > +++ b/arch/arm/boot/dts/r8a7743.dtsi
>
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> > @@ -79,6 +102,37 @@
> > };
> > };
> >
> > + /* External CAN clock */
> > + can_clk: can {
>
> Doesn't look alphabetically to me...
Thanks, I have applied the following:
From: Simon Horman <horms+renesas@verge.net.au>
Subject: [PATCH] ARM: dts: r8a7743: sort root sub-nodes alphabetically
Sort root sub-nodes alphabetically to allow for easier maintenance
of this file.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
arch/arm/boot/dts/r8a7743.dtsi | 100 ++++++++++++++++++++++-------------------
1 file changed, 54 insertions(+), 46 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index f24f36d50e40..067e339f6646 100644
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -37,6 +37,37 @@
vin2 = &vin2;
};
+ /*
+ * The external audio clocks are configured as 0 Hz fixed frequency
+ * clocks by default.
+ * Boards that provide audio clocks should override them.
+ */
+ audio_clk_a: audio_clk_a {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_b: audio_clk_b {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ audio_clk_c: audio_clk_c {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External CAN clock */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -79,6 +110,29 @@
};
};
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External PCIe clock - can be overridden by the board */
+ pcie_bus_clk: pcie_bus {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
soc {
compatible = "simple-bus";
interrupt-parent = <&gic>;
@@ -1629,56 +1683,10 @@
clock-frequency = <0>;
};
- /*
- * The external audio clocks are configured as 0 Hz fixed frequency
- * clocks by default.
- * Boards that provide audio clocks should override them.
- */
- audio_clk_a: audio_clk_a {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_b: audio_clk_b {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- audio_clk_c: audio_clk_c {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
-
- /* External CAN clock */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
-
- /* External PCIe clock - can be overridden by the board */
- pcie_bus_clk: pcie_bus {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
- /* External SCIF clock */
- scif_clk: scif {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board. */
- clock-frequency = <0>;
- };
};
--
2.11.0
^ permalink raw reply related
* [PATCH] ARM: dts: at91: sama5d2_ptc_ek: use TCB0 as timers
From: Alexandre Belloni @ 2017-12-20 10:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220090440.18153-1-nicolas.ferre@microchip.com>
On 20/12/2017 at 10:04:40 +0100, Nicolas Ferre wrote:
> Use tcb0 for timers as selected in sama5_defconfig.
>
> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
> ---
> Hi Alex,
>
> Adding the newly added sama5d2_ptc_ek to the series.
> Not tested though.
>
> Regards,
> Nicolas
>
> arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
Applied, thanks.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH 5/5] ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
From: Simon Horman @ 2017-12-20 9:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513103111-45830-6-git-send-email-biju.das@bp.renesas.com>
On Tue, Dec 12, 2017 at 06:25:11PM +0000, Biju Das wrote:
> This patch enables SGTL5000 audio codec on the carrier board.
>
> Signed-off-by: Biju Das <biju.das@bp.renesas.com>
> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Somehow I missed applying this one.
I have now done so with the minor update noted below.
> ---
> arch/arm/boot/dts/iwg20d-q7-common.dtsi | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm/boot/dts/iwg20d-q7-common.dtsi b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> index 54470c6..2070b14 100644
> --- a/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> +++ b/arch/arm/boot/dts/iwg20d-q7-common.dtsi
> @@ -20,6 +20,20 @@
> stdout-path = "serial0:115200n8";
> };
>
> + audio_clock: audio_clock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + };
> +
> + reg_1p5v: 1p5v {
> + compatible = "regulator-fixed";
> + regulator-name = "1P5V";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> +
> vcc_sdhi1: regulator-vcc-sdhi1 {
> compatible = "regulator-fixed";
>
> @@ -83,6 +97,16 @@
> compatible = "ti,bq32000";
> reg = <0x68>;
> };
> +
> + sgtl5000: codec at 0a {
s/@0a/@a/
Base addresses should not have a leading 0.
# make dtbs W=1
DTC arch/arm/boot/dts/r8a7743-iwg20d-q7-dbcm-ca.dtb
arch/arm/boot/dts/r8a7743-iwg20d-q7.dtb: Warning (unit_address_format): Node /soc/i2c at e6530000/codec at 0a unit name should not have leading 0s
> + compatible = "fsl,sgtl5000";
> + #sound-dai-cells = <0>;
> + reg = <0x0a>;
> + clocks = <&audio_clock>;
> + VDDA-supply = <®_3p3v>;
> + VDDIO-supply = <®_3p3v>;
> + VDDD-supply = <®_1p5v>;
> + };
> };
>
> &pci0 {
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH] ARM: NOMMU: Setup VBAR/Hivecs for secondaries cores
From: Vladimir Murzin @ 2017-12-20 9:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220045219.GA6416@afzalpc>
Hi,
On 20/12/17 04:52, afzal mohammed wrote:
> Hi,
>
> On Tue, Dec 19, 2017 at 02:44:01PM +0000, Vladimir Murzin wrote:
>
>>> Was the issue observed on Cortex-R ?, and was it occuring with
>>> CONFIG_CPU_HIGH_VECTOR enabled or disabled ?
>>
>> I caught it when was trying to setup VBAR and after code inspection I
>> noticed that setting of Hivecs were changed as well.
>
> Thinking again about this, should the Hivecs setting on secondary
> CPU's be done (till a requirement comes) ?
>
> ARM ARM deprecates using Hivecs setting on ARMv7-R, so this issue
> might not be hit in practice for R class. While pre-ARMv7, lack of
> Hivecs setting for secondaries, it seems can affect only ARMv6k
> (multi-processing support added here ?) and i am making a guess that
> even if there are ARMv6k with more than one core available, they might
> not yet have run with MMU disabled to hit this case, probably the
> reason no one has reported issue for long.
I've just reported an issue, no? :)
>
> Perhaps, we can avoid configuring Hivecs for secondaries until some
> one needs it ?
Well, before ad475117d201, Hivec would be enabled for secondaries via
secondary_startup
-> __after_proc_init
after that commit it is not true, so it is kind of regression.
Additionally, patch is not about Hivec only, but VBAR as well and TBH I
don't follow what is your proposal...
Cheers
Vladimir
>
> afzal
>
^ permalink raw reply
* [PATCH 2/2] pinctrl/nomadik/abx500: Improve a size determination in abx500_gpio_probe()
From: SF Markus Elfring @ 2017-12-20 9:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e5be1da7-460d-a47d-59b8-c1902907f5a4@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Wed, 20 Dec 2017 10:22:53 +0100
Replace the specification of a data structure by a pointer dereference
as the parameter for the operator "sizeof" to make the corresponding size
determination a bit safer according to the Linux coding style convention.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/pinctrl/nomadik/pinctrl-abx500.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index feb030d1ea63..7d00a5d864f5 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -1155,8 +1155,7 @@ static int abx500_gpio_probe(struct platform_device *pdev)
return -ENODEV;
}
- pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
- GFP_KERNEL);
+ pct = devm_kzalloc(&pdev->dev, sizeof(*pct), GFP_KERNEL);
if (!pct)
return -ENOMEM;
--
2.15.1
^ permalink raw reply related
* [PATCH 1/2] pinctrl/nomadik/abx500: Delete an error message for a failed memory allocation in abx500_gpio_probe()
From: SF Markus Elfring @ 2017-12-20 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e5be1da7-460d-a47d-59b8-c1902907f5a4@users.sourceforge.net>
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Wed, 20 Dec 2017 10:12:56 +0100
Omit an extra message for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/pinctrl/nomadik/pinctrl-abx500.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/pinctrl/nomadik/pinctrl-abx500.c b/drivers/pinctrl/nomadik/pinctrl-abx500.c
index b32c0d602024..feb030d1ea63 100644
--- a/drivers/pinctrl/nomadik/pinctrl-abx500.c
+++ b/drivers/pinctrl/nomadik/pinctrl-abx500.c
@@ -1157,11 +1157,8 @@ static int abx500_gpio_probe(struct platform_device *pdev)
pct = devm_kzalloc(&pdev->dev, sizeof(struct abx500_pinctrl),
GFP_KERNEL);
- if (pct == NULL) {
- dev_err(&pdev->dev,
- "failed to allocate memory for pct\n");
+ if (!pct)
return -ENOMEM;
- }
pct->dev = &pdev->dev;
pct->parent = dev_get_drvdata(pdev->dev.parent);
--
2.15.1
^ permalink raw reply related
* [PATCH 0/2] pinctrl/nomadik/abx500: Adjustments for abx500_gpio_probe()
From: SF Markus Elfring @ 2017-12-20 9:50 UTC (permalink / raw)
To: linux-arm-kernel
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Wed, 20 Dec 2017 10:45:01 +0100
Two update suggestions were taken into account
from static source code analysis.
Markus Elfring (2):
Delete an error message for a failed memory allocation
Improve a size determination
drivers/pinctrl/nomadik/pinctrl-abx500.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
--
2.15.1
^ permalink raw reply
* [PATCH] irqchip/gic-v3-its: Flush GICR caching for a cross node collection move of an irq
From: Marc Zyngier @ 2017-12-20 9:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKTKpr47HZmoShXvAG5d4DZQORvrMccdaL8-mEWmpEsNMX5_3w@mail.gmail.com>
On 20/12/17 09:34, Ganapatrao Kulkarni wrote:
> Hi Marc,
>
> On Wed, Dec 20, 2017 at 2:56 PM, Marc Zyngier <marc.zyngier@arm.com> wrote:
>> On 20/12/17 09:15, Ganapatrao Kulkarni wrote:
>>> When an interrupt is moved, it is possible that an implementation that
>>> supports caching might still have cached data for a previous
>>> (no longer valid) mapping of the interrupt. In particular, in a distributed
>>> GIC implementation like multi-socket SoC platfroms. Hence it is necessary
>>> to flush cached entries after cross node collection migration.
>>>
>>> Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
>>> ---
>>> drivers/irqchip/irq-gic-v3-its.c | 6 ++++++
>>> 1 file changed, 6 insertions(+)
>>>
>>> diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
>>> index 4039e64..ea849a1 100644
>>> --- a/drivers/irqchip/irq-gic-v3-its.c
>>> +++ b/drivers/irqchip/irq-gic-v3-its.c
>>> @@ -1119,6 +1119,12 @@ static int its_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
>>> if (cpu != its_dev->event_map.col_map[id]) {
>>> target_col = &its_dev->its->collections[cpu];
>>> its_send_movi(its_dev, target_col, id);
>>> + /* Issue INV for cross node collection move on
>>> + * multi socket systems.
>>> + */
>>> + if (cpu_to_node(cpu) !=
>>> + cpu_to_node(its_dev->event_map.col_map[id]))
>>> + its_send_inv(its_dev, id);
>>> its_dev->event_map.col_map[id] = cpu;
>>> irq_data_update_effective_affinity(d, cpumask_of(cpu));
>>> }
>>>
>>
>> The MOVI command doesn't have any such requirement (it only mandates
>> synchronization), and doesn't say anything about distributed vs monolithic.
>
> GIC-v3 spec do mention to issue ITS INV command or a write to GICR_INVLPIR.
> pasting below snippet of MOVI command description.
>
> "When an interrupt is moved to a collection, it is possible that an
> implementation that supports speculative caching
> might still have cached data for a previous (no longer valid) mapping
> of the interrupt. Hence, implementations
> must take care to invalidate any data associated with an interrupt
> when it is moved. In particular, in a distributed
> implementation, the ITS must write to the appropriate GICR_* register
> to perform the invalidation in the redistributor."
Which document is that from? The only official document that should be
used is the GICv3/v4 Architecture Specification[1], which doesn't
contain that text.
Thanks,
M.
[1]:
https://developer.arm.com/products/architecture/a-profile/docs/ihi0069/latest/arm-generic-interrupt-controller-architecture-specification-gic-architecture-version-30-and-40
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH net 2/2] net: mediatek: remove superfluous pin setup for MT7622 SoC
From: sean.wang at mediatek.com @ 2017-12-20 9:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e366efc29985d3292c8a1afb1389b5eac57c9037.1513762066.git.sean.wang@mediatek.com>
From: Sean Wang <sean.wang@mediatek.com>
Remove superfluous pin setup to get out of accessing invalid I/O pin
registers because the way for pin configuring tends to be different from
various SoCs and thus it should be better being managed and controlled by
the pinctrl driver which MT7622 already can support.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 35 +++++++++++++++++------------
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 3 +++
2 files changed, 24 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index fc67e35..29826dd 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
@@ -1952,14 +1952,16 @@ static int mtk_hw_init(struct mtk_eth *eth)
}
regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
- /* Set GE2 driving and slew rate */
- regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
+ if (eth->pctl) {
+ /* Set GE2 driving and slew rate */
+ regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
- /* set GE2 TDSEL */
- regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
+ /* set GE2 TDSEL */
+ regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
- /* set GE2 TUNE */
- regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
+ /* set GE2 TUNE */
+ regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
+ }
/* Set linkdown as the default for each GMAC. Its own MCR would be set
* up with the more appropriate value when mtk_phy_link_adjust call is
@@ -2538,11 +2540,13 @@ static int mtk_probe(struct platform_device *pdev)
}
}
- eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
- "mediatek,pctl");
- if (IS_ERR(eth->pctl)) {
- dev_err(&pdev->dev, "no pctl regmap found\n");
- return PTR_ERR(eth->pctl);
+ if (eth->soc->required_pctl) {
+ eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
+ "mediatek,pctl");
+ if (IS_ERR(eth->pctl)) {
+ dev_err(&pdev->dev, "no pctl regmap found\n");
+ return PTR_ERR(eth->pctl);
+ }
}
for (i = 0; i < 3; i++) {
@@ -2668,17 +2672,20 @@ static int mtk_remove(struct platform_device *pdev)
static const struct mtk_soc_data mt2701_data = {
.caps = MTK_GMAC1_TRGMII,
- .required_clks = MT7623_CLKS_BITMAP
+ .required_clks = MT7623_CLKS_BITMAP,
+ .required_pctl = true,
};
static const struct mtk_soc_data mt7622_data = {
.caps = MTK_DUAL_GMAC_SHARED_SGMII | MTK_GMAC1_ESW,
- .required_clks = MT7622_CLKS_BITMAP
+ .required_clks = MT7622_CLKS_BITMAP,
+ .required_pctl = false,
};
static const struct mtk_soc_data mt7623_data = {
.caps = MTK_GMAC1_TRGMII,
- .required_clks = MT7623_CLKS_BITMAP
+ .required_clks = MT7623_CLKS_BITMAP,
+ .required_pctl = true,
};
const struct of_device_id of_mtk_match[] = {
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.h b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
index a3af466..672b8c3 100644
--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
@@ -573,10 +573,13 @@ struct mtk_rx_ring {
* @caps Flags shown the extra capability for the SoC
* @required_clks Flags shown the bitmap for required clocks on
* the target SoC
+ * @required_pctl A bool value to show whether the SoC requires
+ * the extra setup for those pins used by GMAC.
*/
struct mtk_soc_data {
u32 caps;
u32 required_clks;
+ bool required_pctl;
};
/* currently no SoC has more than 2 macs */
--
2.7.4
^ permalink raw reply related
* [PATCH net 1/2] dt-bindings: net: mediatek: add condition to property mediatek, pctl
From: sean.wang at mediatek.com @ 2017-12-20 9:47 UTC (permalink / raw)
To: linux-arm-kernel
From: Sean Wang <sean.wang@mediatek.com>
The property "mediatek,pctl" is only required for SoCs such as MT2701 and
MT7623, so adding a few words for stating the condition.
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
---
Documentation/devicetree/bindings/net/mediatek-net.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/net/mediatek-net.txt b/Documentation/devicetree/bindings/net/mediatek-net.txt
index 214eaa9..53c13ee 100644
--- a/Documentation/devicetree/bindings/net/mediatek-net.txt
+++ b/Documentation/devicetree/bindings/net/mediatek-net.txt
@@ -28,7 +28,7 @@ Required properties:
- mediatek,sgmiisys: phandle to the syscon node that handles the SGMII setup
which is required for those SoCs equipped with SGMII such as MT7622 SoC.
- mediatek,pctl: phandle to the syscon node that handles the ports slew rate
- and driver current
+ and driver current: only for MT2701 and MT7623 SoC
Optional properties:
- interrupt-parent: Should be the phandle for the interrupt controller
--
2.7.4
^ permalink raw reply related
* [-next PATCH 0/4] sysfs and DEVICE_ATTR_<foo>
From: Felipe Balbi @ 2017-12-20 9:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513706701.git.joe@perches.com>
Hi,
Joe Perches <joe@perches.com> writes:
> drivers/usb/phy/phy-tahvo.c | 2 +-
Acked-by: Felipe Balbi <felipe.balbi@linux.intel.com>
--
balbi
^ permalink raw reply
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