* [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes
From: Matthias Brugger @ 2017-12-20 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1511854102-23195-7-git-send-email-weiyi.lu@mediatek.com>
On 11/28/2017 08:28 AM, Weiyi Lu wrote:
> Add clock controller nodes for MT2712, include topckgen, infracfg,
> pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
> provide clocks for MT2712.
>
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++++++++++++++++++++++++++++++
> 1 file changed, 115 insertions(+)
I fixed the subject line for you, but the next time please take care to start
the line with "arm64" instead of "arm"
Thanks,
Matthias
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> index 5d4e406..5703793 100644
> --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -5,6 +5,7 @@
> * SPDX-License-Identifier: (GPL-2.0 OR MIT)
> */
>
> +#include <dt-bindings/clock/mt2712-clk.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
>
> @@ -98,6 +99,48 @@
> #clock-cells = <0>;
> };
>
> + clk26m: oscillator at 0 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <26000000>;
> + clock-output-names = "clk26m";
> + };
> +
> + clk32k: oscillator at 1 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <32768>;
> + clock-output-names = "clk32k";
> + };
> +
> + clkfpc: oscillator at 2 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + clock-output-names = "clkfpc";
> + };
> +
> + clkaud_ext_i_0: oscillator at 3 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <6500000>;
> + clock-output-names = "clkaud_ext_i_0";
> + };
> +
> + clkaud_ext_i_1: oscillator at 4 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <196608000>;
> + clock-output-names = "clkaud_ext_i_1";
> + };
> +
> + clkaud_ext_i_2: oscillator at 5 {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <180633600>;
> + clock-output-names = "clkaud_ext_i_2";
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupt-parent = <&gic>;
> @@ -111,6 +154,24 @@
> (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
> };
>
> + topckgen: syscon at 10000000 {
> + compatible = "mediatek,mt2712-topckgen", "syscon";
> + reg = <0 0x10000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + infracfg: syscon at 10001000 {
> + compatible = "mediatek,mt2712-infracfg", "syscon";
> + reg = <0 0x10001000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + pericfg: syscon at 10003000 {
> + compatible = "mediatek,mt2712-pericfg", "syscon";
> + reg = <0 0x10003000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> uart5: serial at 1000f000 {
> compatible = "mediatek,mt2712-uart",
> "mediatek,mt6577-uart";
> @@ -121,6 +182,18 @@
> status = "disabled";
> };
>
> + apmixedsys: syscon at 10209000 {
> + compatible = "mediatek,mt2712-apmixedsys", "syscon";
> + reg = <0 0x10209000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mcucfg: syscon at 10220000 {
> + compatible = "mediatek,mt2712-mcucfg", "syscon";
> + reg = <0 0x10220000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> sysirq: interrupt-controller at 10220a80 {
> compatible = "mediatek,mt2712-sysirq",
> "mediatek,mt6577-sysirq";
> @@ -192,5 +265,47 @@
> clock-names = "baud", "bus";
> status = "disabled";
> };
> +
> + mfgcfg: syscon at 13000000 {
> + compatible = "mediatek,mt2712-mfgcfg", "syscon";
> + reg = <0 0x13000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + mmsys: syscon at 14000000 {
> + compatible = "mediatek,mt2712-mmsys", "syscon";
> + reg = <0 0x14000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + imgsys: syscon at 15000000 {
> + compatible = "mediatek,mt2712-imgsys", "syscon";
> + reg = <0 0x15000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + bdpsys: syscon at 15010000 {
> + compatible = "mediatek,mt2712-bdpsys", "syscon";
> + reg = <0 0x15010000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vdecsys: syscon at 16000000 {
> + compatible = "mediatek,mt2712-vdecsys", "syscon";
> + reg = <0 0x16000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + vencsys: syscon at 18000000 {
> + compatible = "mediatek,mt2712-vencsys", "syscon";
> + reg = <0 0x18000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + jpgdecsys: syscon at 19000000 {
> + compatible = "mediatek,mt2712-jpgdecsys", "syscon";
> + reg = <0 0x19000000 0 0x1000>;
> + #clock-cells = <1>;
> + };
> };
>
>
^ permalink raw reply
* [PATCH] ARM: dts: imx: Add memory node unit name
From: Fabio Estevam @ 2017-12-20 18:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1512575989-15627-1-git-send-email-marcofrk@gmail.com>
On Wed, Dec 6, 2017 at 1:59 PM, Marco Franchi <marcofrk@gmail.com> wrote:
> Fix the following warnings from dtc by adding the unit name to memory
> nodes:
>
> Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
>
> Converted using the following command:
>
> perl -p0777i -e 's/memory \{\n\t\treg = \<0x+([0-9a-f])/memory\@$1$\0000000 \{\n\t\treg = <0x$1/m' `find ./arch/arm/boot/dts -name "imx*"`
>
> The files below were manually fixed:
> -imx1-ads.dts
> -imx1-apf9328.dts
>
> Signed-off-by: Marco Franchi <marcofrk@gmail.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH 1/9] dt-bindings: ti-sysc: Update binding for timers and capabilities
From: Rob Herring @ 2017-12-20 18:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171216192222.GH3875@atomide.com>
On Sat, Dec 16, 2017 at 11:22:22AM -0800, Tony Lindgren wrote:
> * Rob Herring <robh@kernel.org> [171216 18:33]:
> > > Optional properties:
> > >
> > > +- ti,sysc-mask shall contain mask of supported register bits for the
> > > + SYSCONFIG register as documented in the Technical Reference
> > > + Manual (TRM) for the interconnect target module
> > > +
> > > +- ti,sysc-midle list of master idle modes supported by the interconnect
> > > + target module as documented in the TRM for SYSCONFIG
> > > + register MIDLEMODE bits
> > > +
> > > +- ti,sysc-sidle list of slave idle modes supported by the interconnect
> > > + target module as documented in the TRM for SYSCONFIG
> > > + register SIDLEMODE bits
> > > +
> > > +- ti,sysc-delay-us delay needed after OCP softreset before accssing
> > > + SYSCONFIG register again
> > > +
> > > +- ti,syss-mask optional mask of reset done status bits as described in the
> > > + TRM for SYSSTATUS registers, typically 1 with some devices
> > > + having separate reset done bits for children like OHCI and
> > > + EHCI
> > > +
> >
> > Seems like a lot of this should be implied by specific compatible
> > strings.
>
> Unfortunately that would still explode the permutations to almost
> one compatible per module especially for types "ti,sysc-omap2" and
> "ti,sysc-omap4". And the features and idle modes supported by the
> module are all over the place for "ti,sysc-mask", "ti,sysc-midle",
> "ti,sysc-sidle" and "ti,syss-mask"..
Okay.
> I was planning to have "ti,sysc-delay-us" only in the driver, but
> the same IP needs it set on dm814x while not on omap4 for OTG
> for example. I could add SoC specific quirks to the driver
> for that one if you prefer that instead?
No, I don't have a preference.
> I do have a patch also I'm testing to use the revision register
> value for handling further quirks, but unfortunately that
> register is not populated or updated for many modules. And it's
> only usable after the module is already configured to accessible :)
>
> > Are the bits you've defined all of them or there's more?
>
> That's it, with this binding I've allocated the data from dts
> for the tests I've done. So that should allow us to replace the
> static data to start with as seen with the following command:
>
> $ git grep -A10 "struct omap_hwmod_class_sysconfig" \
> arch/arm/*hwmod*data*.c
> ...
>
> So that's to configure a big pile of different module
> configurations we currently have as can be seen with:
>
> $ git grep "struct omap_hwmod_class_sysconfig" \
> arch/arm/*hwmod*data*.c | wc -l
> 194
>
> I'm sure there's still few duplicates there though..
Okay, then I guess I'm okay with this.
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v4 1/4] dt-bindings: rtc: add bindings for i.MX53 SRTC
From: Rob Herring @ 2017-12-20 18:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218115133.16371-2-linux-kernel-dev@beckhoff.com>
On Mon, Dec 18, 2017 at 12:51:30PM +0100, linux-kernel-dev at beckhoff.com wrote:
> From: Patrick Bruenn <p.bruenn@beckhoff.com>
>
> Document the binding for i.MX53 SRTC implemented by rtc-mxc_v2
>
> Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v4 10/16] dt-bindings: Document the Rockchip ISP1 bindings
From: Rob Herring @ 2017-12-20 18:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218121445.6086-7-jacob-chen@iotwrt.com>
On Mon, Dec 18, 2017 at 08:14:39PM +0800, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
>
> Add DT bindings documentation for Rockchip ISP1
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> .../devicetree/bindings/media/rockchip-isp1.txt | 69 ++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp1.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v4 11/16] dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
From: Rob Herring @ 2017-12-20 18:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171218121445.6086-8-jacob-chen@iotwrt.com>
On Mon, Dec 18, 2017 at 08:14:40PM +0800, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
>
> Add DT bindings documentation for Rockchip MIPI D-PHY RX
>
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
> .../bindings/media/rockchip-mipi-dphy.txt | 88 ++++++++++++++++++++++
> 1 file changed, 88 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH] crypto: stm32 - Use standard CONFIG name
From: Corentin Labbe @ 2017-12-20 18:19 UTC (permalink / raw)
To: linux-arm-kernel
All hardware crypto devices have their CONFIG names using the following
convention:
CRYPTO_DEV_name_algo
This patch apply this conventions on STM32 CONFIG names.
Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
drivers/crypto/stm32/Kconfig | 6 +++---
drivers/crypto/stm32/Makefile | 6 +++---
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 61ef00b6bf45..63aa78c0b12b 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -1,4 +1,4 @@
-config CRC_DEV_STM32
+config CRYPTO_DEV_STM32_CRC
tristate "Support for STM32 crc accelerators"
depends on ARCH_STM32
select CRYPTO_HASH
@@ -6,7 +6,7 @@ config CRC_DEV_STM32
This enables support for the CRC32 hw accelerator which can be found
on STMicroelectronics STM32 SOC.
-config HASH_DEV_STM32
+config CRYPTO_DEV_STM32_HASH
tristate "Support for STM32 hash accelerators"
depends on ARCH_STM32
depends on HAS_DMA
@@ -19,7 +19,7 @@ config HASH_DEV_STM32
This enables support for the HASH hw accelerator which can be found
on STMicroelectronics STM32 SOC.
-config CRYP_DEV_STM32
+config CRYPTO_DEV_STM32_CRYP
tristate "Support for STM32 cryp accelerators"
depends on ARCH_STM32
select CRYPTO_HASH
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 2c19fc155bfd..53d1bb94b221 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,3 +1,3 @@
-obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
-obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
+obj-$(CONFIG_CRYPTO_DEV_STM32_CRC) += stm32_crc32.o
+obj-$(CONFIG_CRYPTO_DEV_STM32_HASH) += stm32-hash.o
+obj-$(CONFIG_CRYPTO_DEV_STM32_CRYP) += stm32-cryp.o
--
2.13.6
^ permalink raw reply related
* [PATCH 0/2] drm/rockchip: Fix sleeping function called from invalid context
From: Enric Balletbo i Serra @ 2017-12-20 18:20 UTC (permalink / raw)
To: linux-arm-kernel
Dear all,
After enable the debug option to check sleep inside atomic section I got
lots of messages from the drm/rockchip driver using current 4.15-rc4
BUG: sleeping function called from invalid context at kernel/locking/mutex.c:238
in_atomic(): 1, irqs_disabled(): 128, pid: 3457, name: Xorg
CPU: 3 PID: 3457 Comm: Xorg Tainted: G W 4.15.0-rc4+ #56
Hardware name: Google Kevin (DT)
Call trace:
dump_backtrace+0x0/0x1a8
show_stack+0x24/0x30
dump_stack+0xb8/0xf0
___might_sleep+0x110/0x140
__might_sleep+0x58/0x90
mutex_lock+0x2c/0x68
analogix_dp_psr_set+0x78/0x100
rockchip_drm_do_flush+0x6c/0x88
rockchip_drm_psr_flush_all+0x48/0x70
rockchip_drm_fb_dirty+0x20/0x30
drm_mode_dirtyfb_ioctl+0x1c4/0x1f8
drm_ioctl_kernel+0x74/0xd0
drm_ioctl+0x2b8/0x3c0
do_vfs_ioctl+0xb0/0x818
SyS_ioctl+0x94/0xa8
el0_svc_naked+0x20/0x24
The two patches in this patchset were sent by Sean Paul some time ago
([1][2]) but never landed in mainline, the patches in question can fix the
issue reported and I think that could be interesting include both in this
release cycle, hence I'm resending it. The patches were rebased on top of
mainline.
[1] https://patchwork.kernel.org/patch/9382847/
[2] https://patchwork.kernel.org/patch/9614679/
Best regards,
Enric
Sean Paul (2):
drm/rockchip: Don't use atomic constructs for psr
drm/rockchip: Remove analogix psr worker.
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 30 +-----------
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_psr.c | 63 +++++++++++--------------
4 files changed, 31 insertions(+), 66 deletions(-)
--
2.9.3
^ permalink raw reply
* [PATCH 1/2] drm/rockchip: Don't use atomic constructs for psr
From: Enric Balletbo i Serra @ 2017-12-20 18:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220182044.20331-1-enric.balletbo@collabora.com>
From: Sean Paul <seanpaul@chromium.org>
Instead of using timer and spinlocks, use delayed_work and
mutexes for rockchip psr. This allows us to make blocking
calls when enabling/disabling psr (which is sort of important
given we're talking over dpcd to the display).
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
drivers/gpu/drm/rockchip/rockchip_drm_drv.c | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 2 +-
drivers/gpu/drm/rockchip/rockchip_drm_psr.c | 63 +++++++++++++----------------
3 files changed, 29 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index 76d63de..cd7ae12 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -134,7 +134,7 @@ static int rockchip_drm_bind(struct device *dev)
drm_dev->dev_private = private;
INIT_LIST_HEAD(&private->psr_list);
- spin_lock_init(&private->psr_list_lock);
+ mutex_init(&private->psr_list_lock);
ret = rockchip_drm_init_iommu(drm_dev);
if (ret)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 498dfbc..9c064a4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -55,7 +55,7 @@ struct rockchip_drm_private {
struct mutex mm_lock;
struct drm_mm mm;
struct list_head psr_list;
- spinlock_t psr_list_lock;
+ struct mutex psr_list_lock;
};
int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
index 3acfd57..a3f6ec0 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
@@ -18,7 +18,7 @@
#include "rockchip_drm_drv.h"
#include "rockchip_drm_psr.h"
-#define PSR_FLUSH_TIMEOUT msecs_to_jiffies(100)
+#define PSR_FLUSH_TIMEOUT_MS 100
enum psr_state {
PSR_FLUSH,
@@ -30,11 +30,11 @@ struct psr_drv {
struct list_head list;
struct drm_encoder *encoder;
- spinlock_t lock;
+ struct mutex lock;
bool active;
enum psr_state state;
- struct timer_list flush_timer;
+ struct delayed_work flush_work;
void (*set)(struct drm_encoder *encoder, bool enable);
};
@@ -43,9 +43,8 @@ static struct psr_drv *find_psr_by_crtc(struct drm_crtc *crtc)
{
struct rockchip_drm_private *drm_drv = crtc->dev->dev_private;
struct psr_drv *psr;
- unsigned long flags;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry(psr, &drm_drv->psr_list, list) {
if (psr->encoder->crtc == crtc)
goto out;
@@ -53,7 +52,7 @@ static struct psr_drv *find_psr_by_crtc(struct drm_crtc *crtc)
psr = ERR_PTR(-ENODEV);
out:
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
return psr;
}
@@ -94,23 +93,21 @@ static void psr_set_state_locked(struct psr_drv *psr, enum psr_state state)
static void psr_set_state(struct psr_drv *psr, enum psr_state state)
{
- unsigned long flags;
-
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
psr_set_state_locked(psr, state);
- spin_unlock_irqrestore(&psr->lock, flags);
+ mutex_unlock(&psr->lock);
}
-static void psr_flush_handler(struct timer_list *t)
+static void psr_flush_handler(struct work_struct *work)
{
- struct psr_drv *psr = from_timer(psr, t, flush_timer);
- unsigned long flags;
+ struct psr_drv *psr = container_of(to_delayed_work(work),
+ struct psr_drv, flush_work);
/* If the state has changed since we initiated the flush, do nothing */
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
if (psr->state == PSR_FLUSH)
psr_set_state_locked(psr, PSR_ENABLE);
- spin_unlock_irqrestore(&psr->lock, flags);
+ mutex_unlock(&psr->lock);
}
/**
@@ -123,14 +120,13 @@ static void psr_flush_handler(struct timer_list *t)
int rockchip_drm_psr_activate(struct drm_crtc *crtc)
{
struct psr_drv *psr = find_psr_by_crtc(crtc);
- unsigned long flags;
if (IS_ERR(psr))
return PTR_ERR(psr);
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
psr->active = true;
- spin_unlock_irqrestore(&psr->lock, flags);
+ mutex_unlock(&psr->lock);
return 0;
}
@@ -146,15 +142,14 @@ EXPORT_SYMBOL(rockchip_drm_psr_activate);
int rockchip_drm_psr_deactivate(struct drm_crtc *crtc)
{
struct psr_drv *psr = find_psr_by_crtc(crtc);
- unsigned long flags;
if (IS_ERR(psr))
return PTR_ERR(psr);
- spin_lock_irqsave(&psr->lock, flags);
+ mutex_lock(&psr->lock);
psr->active = false;
- spin_unlock_irqrestore(&psr->lock, flags);
- del_timer_sync(&psr->flush_timer);
+ mutex_unlock(&psr->lock);
+ cancel_delayed_work_sync(&psr->flush_work);
return 0;
}
@@ -162,8 +157,7 @@ EXPORT_SYMBOL(rockchip_drm_psr_deactivate);
static void rockchip_drm_do_flush(struct psr_drv *psr)
{
- mod_timer(&psr->flush_timer,
- round_jiffies_up(jiffies + PSR_FLUSH_TIMEOUT));
+ schedule_delayed_work(&psr->flush_work, PSR_FLUSH_TIMEOUT_MS);
psr_set_state(psr, PSR_FLUSH);
}
@@ -201,12 +195,11 @@ void rockchip_drm_psr_flush_all(struct drm_device *dev)
{
struct rockchip_drm_private *drm_drv = dev->dev_private;
struct psr_drv *psr;
- unsigned long flags;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry(psr, &drm_drv->psr_list, list)
rockchip_drm_do_flush(psr);
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
}
EXPORT_SYMBOL(rockchip_drm_psr_flush_all);
@@ -223,7 +216,6 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
{
struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
struct psr_drv *psr;
- unsigned long flags;
if (!encoder || !psr_set)
return -EINVAL;
@@ -232,17 +224,17 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
if (!psr)
return -ENOMEM;
- timer_setup(&psr->flush_timer, psr_flush_handler, 0);
- spin_lock_init(&psr->lock);
+ INIT_DELAYED_WORK(&psr->flush_work, psr_flush_handler);
+ mutex_init(&psr->lock);
psr->active = true;
psr->state = PSR_DISABLE;
psr->encoder = encoder;
psr->set = psr_set;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_add_tail(&psr->list, &drm_drv->psr_list);
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
return 0;
}
@@ -260,16 +252,15 @@ void rockchip_drm_psr_unregister(struct drm_encoder *encoder)
{
struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
struct psr_drv *psr, *n;
- unsigned long flags;
- spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+ mutex_lock(&drm_drv->psr_list_lock);
list_for_each_entry_safe(psr, n, &drm_drv->psr_list, list) {
if (psr->encoder == encoder) {
- del_timer(&psr->flush_timer);
+ cancel_delayed_work_sync(&psr->flush_work);
list_del(&psr->list);
kfree(psr);
}
}
- spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+ mutex_unlock(&drm_drv->psr_list_lock);
}
EXPORT_SYMBOL(rockchip_drm_psr_unregister);
--
2.9.3
^ permalink raw reply related
* [PATCH 2/2] drm/rockchip: Remove analogix psr worker.
From: Enric Balletbo i Serra @ 2017-12-20 18:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220182044.20331-1-enric.balletbo@collabora.com>
From: Sean Paul <seanpaul@chromium.org>
Now that the spinlocks and timers are gone, we can remove the psr
worker located in rockchip's analogix driver and do the enable/disable
directly. This should simplify the code and remove races on disable.
Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 30 ++-----------------------
1 file changed, 2 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 93b7102..d32c9b3 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -71,10 +71,6 @@ struct rockchip_dp_device {
struct regmap *grf;
struct reset_control *rst;
- struct work_struct psr_work;
- struct mutex psr_lock;
- unsigned int psr_state;
-
const struct rockchip_dp_chip_data *data;
struct analogix_dp_plat_data plat_data;
@@ -83,27 +79,13 @@ struct rockchip_dp_device {
static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
{
struct rockchip_dp_device *dp = to_dp(encoder);
+ int ret;
if (!analogix_dp_psr_supported(dp->dev))
return;
DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
- mutex_lock(&dp->psr_lock);
- if (enabled)
- dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
- else
- dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
-
- schedule_work(&dp->psr_work);
- mutex_unlock(&dp->psr_lock);
-}
-
-static void analogix_dp_psr_work(struct work_struct *work)
-{
- struct rockchip_dp_device *dp =
- container_of(work, typeof(*dp), psr_work);
- int ret;
ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
@@ -112,12 +94,10 @@ static void analogix_dp_psr_work(struct work_struct *work)
return;
}
- mutex_lock(&dp->psr_lock);
- if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
+ if (enabled)
analogix_dp_enable_psr(dp->dev);
else
analogix_dp_disable_psr(dp->dev);
- mutex_unlock(&dp->psr_lock);
}
static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
@@ -134,8 +114,6 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
struct rockchip_dp_device *dp = to_dp(plat_data);
int ret;
- cancel_work_sync(&dp->psr_work);
-
ret = clk_prepare_enable(dp->pclk);
if (ret < 0) {
DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
@@ -379,10 +357,6 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
dp->plat_data.power_off = rockchip_dp_powerdown;
dp->plat_data.get_modes = rockchip_dp_get_modes;
- mutex_init(&dp->psr_lock);
- dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
- INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
-
rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
--
2.9.3
^ permalink raw reply related
* [PATCH V2 4/9] devicetree: bindings: stm32: add support of STM32MP157
From: Rob Herring @ 2017-12-20 18:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513610272-7824-5-git-send-email-ludovic.Barre@st.com>
On Mon, Dec 18, 2017 at 04:17:47PM +0100, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
>
> This patch adds STM32MP157 SoC bindings.
>
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> ---
> Documentation/devicetree/bindings/arm/stm32.txt | 1 +
> 1 file changed, 1 insertion(+)
"dt-bindings: ..." is the preferred subject prefix. Otherwise,
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH 1/3] dt-bindings: i2c: Add MediaTek MT2712 i2c binding
From: Rob Herring @ 2017-12-20 18:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513666263-6443-2-git-send-email-jun.gao@mediatek.com>
On Tue, Dec 19, 2017 at 02:51:01PM +0800, Jun Gao wrote:
> From: Jun Gao <jun.gao@mediatek.com>
>
> Add MT2712 i2c binding to binding file. Compare to MT8173 i2c
> controller, MT2712 has timing adjust registers which can adjust
> the internal divider of i2c source clock, SCL duty cycle, SCL
> compare point, start(repeated start) and stop time, SDA change
> time.
>
> Signed-off-by: Jun Gao <jun.gao@mediatek.com>
> ---
> Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
From: Rob Herring @ 2017-12-20 18:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219080747.4507-3-embed3d@gmail.com>
On Tue, Dec 19, 2017 at 09:07:43AM +0100, Philipp Rossak wrote:
> This patch updates documentation for Device-Tree bindings for sunxi IR
> controller and adds the new optional property for the base clock
> frequency.
>
> Signed-off-by: Philipp Rossak <embed3d@gmail.com>
> ---
> Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH 0/3] [v11] pinctrl: qcom: add support for sparse GPIOs
From: Timur Tabi @ 2017-12-20 19:10 UTC (permalink / raw)
To: linux-arm-kernel
A series of patches that add support for GPIO maps that have holes in
them. That is, even though a client driver has N consecutive GPIOs,
some are just unavailable for whatever reason, and the hardware should
not be accessed for those GPIOs.
Patch 1 reverts an old patch that triggers a get_direction of every
pin upon init, without attempting to request the pins first. The
direction is already being queried when the pin is requested.
Patch 2 adds support to pinctrl-msm for "unavailable" GPIOs.
Patch 3 extends that support to pinctrl-qdf2xxx. A recent ACPI change
on QDF2400 platforms blocks access to most pins, so the driver can only
register a subset.
This version drops the availability check in gpiolib, because it's no
necessary. Instead, just having pinctrl-msm return -EACCES is enough
to block all unavailable GPIOs. Patch 1 removes the only instance where
an unrequested GPIO is being accessed.
v11:
Drop support for QCOM8001
Timur Tabi (3):
[v2] Revert "gpio: set up initial state from .get_direction()"
[v8] pinctrl: qcom: disable GPIO groups with no pins
[v7] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002
drivers/gpio/gpiolib.c | 31 +++--------
drivers/pinctrl/qcom/pinctrl-msm.c | 28 ++++++++--
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 96 ++++++++++++++++++++++------------
3 files changed, 94 insertions(+), 61 deletions(-)
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply
* [PATCH 1/3] [v2] Revert "gpio: set up initial state from .get_direction()"
From: Timur Tabi @ 2017-12-20 19:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513797033-9494-1-git-send-email-timur@codeaurora.org>
This reverts commit 72d3200061776264941be1b5a9bb8e926b3b30a5.
We cannot blindly query the direction of all GPIOs when the pins are
first registered. The get_direction callback normally triggers a
read/write to hardware, but we shouldn't be touching the hardware for
an individual GPIO until after it's been properly claimed.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/gpio/gpiolib.c | 31 +++++++------------------------
1 file changed, 7 insertions(+), 24 deletions(-)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index aad84a6306c4..d21ad0bbbd0d 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1207,31 +1207,14 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
struct gpio_desc *desc = &gdev->descs[i];
desc->gdev = gdev;
- /*
- * REVISIT: most hardware initializes GPIOs as inputs
- * (often with pullups enabled) so power usage is
- * minimized. Linux code should set the gpio direction
- * first thing; but until it does, and in case
- * chip->get_direction is not set, we may expose the
- * wrong direction in sysfs.
- */
-
- if (chip->get_direction) {
- /*
- * If we have .get_direction, set up the initial
- * direction flag from the hardware.
- */
- int dir = chip->get_direction(chip, i);
- if (!dir)
- set_bit(FLAG_IS_OUT, &desc->flags);
- } else if (!chip->direction_input) {
- /*
- * If the chip lacks the .direction_input callback
- * we logically assume all lines are outputs.
- */
- set_bit(FLAG_IS_OUT, &desc->flags);
- }
+ /* REVISIT: most hardware initializes GPIOs as inputs (often
+ * with pullups enabled) so power usage is minimized. Linux
+ * code should set the gpio direction first thing; but until
+ * it does, and in case chip->get_direction is not set, we may
+ * expose the wrong direction in sysfs.
+ */
+ desc->flags = !chip->direction_input ? (1 << FLAG_IS_OUT) : 0;
}
#ifdef CONFIG_PINCTRL
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [PATCH 2/3] [v8] pinctrl: qcom: disable GPIO groups with no pins
From: Timur Tabi @ 2017-12-20 19:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513797033-9494-1-git-send-email-timur@codeaurora.org>
pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects
each group to support have only one pin (npins == 1).
We can support "sparse" GPIO maps if we allow for some groups to have zero
pins (npins == 0). These pins are "hidden" from the rest of the driver
and gpiolib.
Access to unavailable GPIOs is blocked via a request callback. If the
requested GPIO is unavailable, -EACCES is returned, which prevents
further access to that GPIO.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 28 +++++++++++++++++++++++-----
1 file changed, 23 insertions(+), 5 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7a960590ecaa..d45b4c2b5af1 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -507,6 +507,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
};
g = &pctrl->soc->groups[offset];
+
+ /* If the GPIO group has no pins, then don't show it. */
+ if (!g->npins)
+ return;
+
ctl_reg = readl(pctrl->regs + g->ctl_reg);
is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -516,7 +521,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
seq_printf(s, " %dmA", msm_regval_to_drive(drive));
- seq_printf(s, " %s", pulls[pull]);
+ seq_printf(s, " %s\n", pulls[pull]);
}
static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -524,23 +529,36 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
unsigned gpio = chip->base;
unsigned i;
- for (i = 0; i < chip->ngpio; i++, gpio++) {
+ for (i = 0; i < chip->ngpio; i++, gpio++)
msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
- seq_puts(s, "\n");
- }
}
#else
#define msm_gpio_dbg_show NULL
#endif
+/*
+ * If the requested GPIO has no pins, then treat it as unavailable.
+ * Otherwise, call the standard request function.
+ */
+static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+ struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
+ const struct msm_pingroup *g = &pctrl->soc->groups[offset];
+
+ if (!g->npins)
+ return -EACCES;
+
+ return gpiochip_generic_request(chip, offset);
+}
+
static const struct gpio_chip msm_gpio_template = {
.direction_input = msm_gpio_direction_input,
.direction_output = msm_gpio_direction_output,
.get_direction = msm_gpio_get_direction,
.get = msm_gpio_get,
.set = msm_gpio_set,
- .request = gpiochip_generic_request,
+ .request = msm_gpio_request,
.free = gpiochip_generic_free,
.dbg_show = msm_gpio_dbg_show,
};
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [PATCH 3/3] [v7] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002
From: Timur Tabi @ 2017-12-20 19:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513797033-9494-1-git-send-email-timur@codeaurora.org>
Newer versions of the firmware for the Qualcomm Datacenter Technologies
QDF2400 restricts access to a subset of the GPIOs on the TLMM. To
prevent older kernels from accidentally accessing the restricted GPIOs,
we change the ACPI HID for the TLMM block from QCOM8001 to QCOM8002,
and introduce a new property "gpios". This property is an array of
specific GPIOs that are accessible. When an older kernel boots on
newer (restricted) firmware, it will fail to probe.
To implement the sparse GPIO map, we register all of the GPIOs, but set
the pin count for the unavailable GPIOs to zero. The pinctrl-msm
driver will block those unavailable GPIOs from being accessed.
Support for QCOM8001 is removed as there is no longer any firmware that
implements it.
Signed-off-by: Timur Tabi <timur@codeaurora.org>
---
drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 96 ++++++++++++++++++++++------------
1 file changed, 64 insertions(+), 32 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
index bb3ce5c3e18b..f8ba58dd4d07 100644
--- a/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
+++ b/drivers/pinctrl/qcom/pinctrl-qdf2xxx.c
@@ -32,7 +32,7 @@
static struct msm_pinctrl_soc_data qdf2xxx_pinctrl;
-/* A reasonable limit to the number of GPIOS */
+/* A maximum of 256 allows us to use a u8 array to hold the GPIO numbers */
#define MAX_GPIOS 256
/* maximum size of each gpio name (enough room for "gpioXXX" + null) */
@@ -45,59 +45,91 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
char (*names)[NAME_SIZE];
unsigned int i;
u32 num_gpios;
+ unsigned int avail_gpios; /* The number of GPIOs we support */
+ u8 gpios[MAX_GPIOS]; /* An array of supported GPIOs */
int ret;
/* Query the number of GPIOs from ACPI */
ret = device_property_read_u32(&pdev->dev, "num-gpios", &num_gpios);
if (ret < 0) {
- dev_warn(&pdev->dev, "missing num-gpios property\n");
+ dev_err(&pdev->dev, "missing 'num-gpios' property\n");
return ret;
}
-
if (!num_gpios || num_gpios > MAX_GPIOS) {
- dev_warn(&pdev->dev, "invalid num-gpios property\n");
+ dev_err(&pdev->dev, "invalid 'num-gpios' property\n");
+ return -ENODEV;
+ }
+
+ /* The number of GPIOs in the approved list */
+ ret = device_property_read_u8_array(&pdev->dev, "gpios", NULL, 0);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "missing 'gpios' property\n");
+ return ret;
+ }
+ /*
+ * The number of available GPIOs should be non-zero, and no
+ * more than the total number of GPIOS.
+ */
+ if (!ret || ret > num_gpios) {
+ dev_err(&pdev->dev, "invalid 'gpios' property\n");
return -ENODEV;
}
+ avail_gpios = ret;
+
+ ret = device_property_read_u8_array(&pdev->dev, "gpios", gpios,
+ avail_gpios);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "could not read list of GPIOs\n");
+ return ret;
+ }
pins = devm_kcalloc(&pdev->dev, num_gpios,
sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
groups = devm_kcalloc(&pdev->dev, num_gpios,
sizeof(struct msm_pingroup), GFP_KERNEL);
- names = devm_kcalloc(&pdev->dev, num_gpios, NAME_SIZE, GFP_KERNEL);
+ names = devm_kcalloc(&pdev->dev, avail_gpios, NAME_SIZE, GFP_KERNEL);
if (!pins || !groups || !names)
return -ENOMEM;
+ /*
+ * Initialize the array. GPIOs not listed in the 'gpios' array
+ * still need a number, but nothing else.
+ */
for (i = 0; i < num_gpios; i++) {
- snprintf(names[i], NAME_SIZE, "gpio%u", i);
-
pins[i].number = i;
- pins[i].name = names[i];
-
- groups[i].npins = 1;
- groups[i].name = names[i];
groups[i].pins = &pins[i].number;
+ }
- groups[i].ctl_reg = 0x10000 * i;
- groups[i].io_reg = 0x04 + 0x10000 * i;
- groups[i].intr_cfg_reg = 0x08 + 0x10000 * i;
- groups[i].intr_status_reg = 0x0c + 0x10000 * i;
- groups[i].intr_target_reg = 0x08 + 0x10000 * i;
-
- groups[i].mux_bit = 2;
- groups[i].pull_bit = 0;
- groups[i].drv_bit = 6;
- groups[i].oe_bit = 9;
- groups[i].in_bit = 0;
- groups[i].out_bit = 1;
- groups[i].intr_enable_bit = 0;
- groups[i].intr_status_bit = 0;
- groups[i].intr_target_bit = 5;
- groups[i].intr_target_kpss_val = 1;
- groups[i].intr_raw_status_bit = 4;
- groups[i].intr_polarity_bit = 1;
- groups[i].intr_detection_bit = 2;
- groups[i].intr_detection_width = 2;
+ /* Populate the entries that are meant to be exposed as GPIOs. */
+ for (i = 0; i < avail_gpios; i++) {
+ unsigned int gpio = gpios[i];
+
+ groups[gpio].npins = 1;
+ snprintf(names[i], NAME_SIZE, "gpio%u", gpio);
+ pins[gpio].name = names[i];
+ groups[gpio].name = names[i];
+
+ groups[gpio].ctl_reg = 0x10000 * gpio;
+ groups[gpio].io_reg = 0x04 + 0x10000 * gpio;
+ groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio;
+ groups[gpio].intr_status_reg = 0x0c + 0x10000 * gpio;
+ groups[gpio].intr_target_reg = 0x08 + 0x10000 * gpio;
+
+ groups[gpio].mux_bit = 2;
+ groups[gpio].pull_bit = 0;
+ groups[gpio].drv_bit = 6;
+ groups[gpio].oe_bit = 9;
+ groups[gpio].in_bit = 0;
+ groups[gpio].out_bit = 1;
+ groups[gpio].intr_enable_bit = 0;
+ groups[gpio].intr_status_bit = 0;
+ groups[gpio].intr_target_bit = 5;
+ groups[gpio].intr_target_kpss_val = 1;
+ groups[gpio].intr_raw_status_bit = 4;
+ groups[gpio].intr_polarity_bit = 1;
+ groups[gpio].intr_detection_bit = 2;
+ groups[gpio].intr_detection_width = 2;
}
qdf2xxx_pinctrl.pins = pins;
@@ -110,7 +142,7 @@ static int qdf2xxx_pinctrl_probe(struct platform_device *pdev)
}
static const struct acpi_device_id qdf2xxx_acpi_ids[] = {
- {"QCOM8001"},
+ {"QCOM8002"},
{},
};
MODULE_DEVICE_TABLE(acpi, qdf2xxx_acpi_ids);
--
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc. Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.
^ permalink raw reply related
* [GIT PULL] arm: Updates of soc drivers for v4.15-next
From: Matthias Brugger @ 2017-12-20 19:16 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd and Olof,
Please take the following patches into account.
Thanks,
Matthias
---
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git
tags/v4.15-next-soc
for you to fetch changes up to 579c60686a086f250c82c76778eb1839394e54ef:
soc: mediatek: add MT2712 scpsys support (2017-12-20 18:30:29 +0100)
----------------------------------------------------------------
- change kconfig entry for armv7 SoCs to be more generic
- add support for mt2701 scpsys driver
binding documentation
extend driver to allow the bus protection to overwrite the register
----------------------------------------------------------------
Sean Wang (1):
ARM: mediatek: use more generic prompts for SoCs with ARMv7
weiyi.lu at mediatek.com (4):
dt-bindings: soc: add MT2712 power dt-bindings
soc: mediatek: extend bus protection API
soc: mediatek: add dependent clock jpgdec/audio for scpsys
soc: mediatek: add MT2712 scpsys support
.../devicetree/bindings/soc/mediatek/scpsys.txt | 3 +
arch/arm/mach-mediatek/Kconfig | 2 +-
drivers/soc/mediatek/mtk-infracfg.c | 26 +++-
drivers/soc/mediatek/mtk-scpsys.c | 140 ++++++++++++++++++---
include/dt-bindings/power/mt2712-power.h | 26 ++++
include/linux/soc/mediatek/infracfg.h | 7 +-
6 files changed, 181 insertions(+), 23 deletions(-)
create mode 100644 include/dt-bindings/power/mt2712-power.h
^ permalink raw reply
* [GIT PULL] arm: Updates of armv7 DTS for v4.15-next
From: Matthias Brugger @ 2017-12-20 19:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd and Olof,
Please feel free to pull the following patches.
Thanks,
Matthias
---
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git
tags/v4.15-next-dts64
for you to fetch changes up to c0c3333daba6617b44228a8dffb8184b2fd1931d:
arm64: dts: Add power controller device node of MT2712 (2017-12-20 20:02:50 +0100)
----------------------------------------------------------------
- mt8173 add cpufreq related nodes
supply nodes
frequency/voltage operation table
- mt2712 add cpufreq related nodes
fixed regulator
supply nodes
frequency/voltage operation table
- mt2712 add clock contoller nodes
- mt2712 add scpsys node
----------------------------------------------------------------
Andrew-sh Cheng (2):
arm64: dts: mediatek: add mt8173 cpufreq related device nodes
arm64: dts: mediatek: add mt2712 cpufreq related device nodes
weiyi.lu at mediatek.com (2):
arm64: dts: mt2712: Add clock controller device nodes
arm64: dts: Add power controller device node of MT2712
arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 27 ++++
arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 188 ++++++++++++++++++++++++++++
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 +++
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 90 +++++++++++++
4 files changed, 323 insertions(+)
^ permalink raw reply
* [GIT PULL 1/5] dt-bindings: Updates for v4.16-rc1
From: Thierry Reding @ 2017-12-20 19:18 UTC (permalink / raw)
To: linux-arm-kernel
Hi ARM SoC maintainers,
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.16-dt-bindings
for you to fetch changes up to 029ab5eaf091ce5eaa1f3017f66fd1d10f431d61:
dt-bindings: memory: Add Tegra186 support (2017-12-13 12:53:43 +0100)
Thanks,
Thierry
----------------------------------------------------------------
dt-bindings: Updates for v4.16-rc1
This contains a set of patches that extend existing bindings with support
for Tegra186.
----------------------------------------------------------------
Thierry Reding (2):
dt-bindings: misc: Add Tegra186 MISC registers bindings
dt-bindings: memory: Add Tegra186 support
.../memory-controllers/nvidia,tegra30-mc.txt | 2 +
.../bindings/misc/nvidia,tegra186-misc.txt | 12 +++
include/dt-bindings/memory/tegra186-mc.h | 111 +++++++++++++++++++++
3 files changed, 125 insertions(+)
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
create mode 100644 include/dt-bindings/memory/tegra186-mc.h
^ permalink raw reply
* [GIT PULL 2/5] soc/tegra: Changes for v4.16-rc1
From: Thierry Reding @ 2017-12-20 19:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220191900.757-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.16-soc
for you to fetch changes up to c641ec6eab8587a78160d37f085a5ed6e542ca88:
soc/tegra: pmc: Consolidate Tegra186 support (2017-12-13 13:06:44 +0100)
Thanks,
Thierry
----------------------------------------------------------------
soc/tegra: Changes for v4.16-rc1
Fuse and chip ID support for Tegra186 is added in this set of changes,
followed by some unification work for the PMC driver in order to avoid
code duplication between Tegra186 and prior chips.
----------------------------------------------------------------
Thierry Reding (7):
dt-bindings: misc: Add Tegra186 MISC registers bindings
Merge branch 'for-4.16/dt-bindings' into for-4.16/soc
soc/tegra: fuse: Move register mapping check
soc/tegra: fuse: Warn if accessing unmapped registers
soc/tegra: fuse: Add Tegra186 chip ID support
soc/tegra: pmc: Parameterize driver
soc/tegra: pmc: Consolidate Tegra186 support
Timo Alho (1):
soc/tegra: fuse: Add Tegra186 support
.../bindings/misc/nvidia,tegra186-misc.txt | 12 +
drivers/soc/tegra/Kconfig | 5 +-
drivers/soc/tegra/Makefile | 1 -
drivers/soc/tegra/fuse/fuse-tegra.c | 3 +
drivers/soc/tegra/fuse/fuse-tegra30.c | 24 +-
drivers/soc/tegra/fuse/fuse.h | 4 +
drivers/soc/tegra/fuse/tegra-apbmisc.c | 11 +-
drivers/soc/tegra/pmc-tegra186.c | 169 ------------
drivers/soc/tegra/pmc.c | 304 +++++++++++++++++----
include/soc/tegra/pmc.h | 12 +
10 files changed, 310 insertions(+), 235 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
delete mode 100644 drivers/soc/tegra/pmc-tegra186.c
^ permalink raw reply
* [GIT PULL 3/5] memory: tegra: Changes for v4.16-rc1
From: Thierry Reding @ 2017-12-20 19:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220191900.757-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.16-memory
for you to fetch changes up to 83476bfaf6ac1cebf0cc5a3bdcf5031ef875cf42:
iommu/tegra-smmu: Fix return value check in tegra_smmu_group_get() (2017-12-20 18:32:08 +0100)
Thanks,
Thierry
----------------------------------------------------------------
memory: tegra: Changes for v4.16-rc1
The Tegra memory controller driver will now instruct the SMMU driver to
create groups, which will make it easier for device drivers to share an
IOMMU domain between multiple devices.
Initial Tegra186 support is also added in a separate driver.
----------------------------------------------------------------
Thierry Reding (6):
dt-bindings: misc: Add Tegra186 MISC registers bindings
dt-bindings: memory: Add Tegra186 support
Merge branch 'for-4.16/dt-bindings' into for-4.16/memory
memory: tegra: Add Tegra186 support
memory: tegra: Create SMMU display groups
iommu/tegra: Allow devices to be grouped
Wei Yongjun (1):
iommu/tegra-smmu: Fix return value check in tegra_smmu_group_get()
.../memory-controllers/nvidia,tegra30-mc.txt | 2 +
.../bindings/misc/nvidia,tegra186-misc.txt | 12 +
drivers/iommu/tegra-smmu.c | 124 ++++-
drivers/memory/tegra/Makefile | 1 +
drivers/memory/tegra/tegra114.c | 15 +
drivers/memory/tegra/tegra124.c | 17 +
drivers/memory/tegra/tegra186.c | 600 +++++++++++++++++++++
drivers/memory/tegra/tegra210.c | 15 +
drivers/memory/tegra/tegra30.c | 15 +
include/dt-bindings/memory/tegra186-mc.h | 111 ++++
include/soc/tegra/mc.h | 9 +
11 files changed, 917 insertions(+), 4 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
create mode 100644 drivers/memory/tegra/tegra186.c
create mode 100644 include/dt-bindings/memory/tegra186-mc.h
^ permalink raw reply
* [GIT PULL 4/5] ARM: tegra: Device tree changes for v4.16-rc1
From: Thierry Reding @ 2017-12-20 19:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220191900.757-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.16-arm-dt
for you to fetch changes up to bb768f28b29e7c72875d8521e2d5b09337561365:
ARM: tegra: Add video decoder on Tegra20 (2017-12-20 19:57:20 +0100)
Thanks,
Thierry
----------------------------------------------------------------
ARM: tegra: Device tree changes for v4.16-rc1
These changes enable the video decoder engine found on Tegra20 SoCs.
----------------------------------------------------------------
Dmitry Osipenko (1):
ARM: tegra: Add video decoder on Tegra20
Vladimir Zapolskiy (1):
ARM: tegra: Add device tree node to describe IRAM on Tegra20
arch/arm/boot/dts/tegra20.dtsi | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
^ permalink raw reply
* [GIT PULL 5/5] arm64: tegra: Changes for v4.16-rc1
From: Thierry Reding @ 2017-12-20 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220191900.757-1-thierry.reding@gmail.com>
Hi ARM SoC maintainers,
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tags/tegra-for-4.16-arm64-dt
for you to fetch changes up to 50f5b841ba06f4dfb739e7a5ab9b87e8173d5915:
arm64: tegra: Use sor1_out clock (2017-12-15 10:14:17 +0100)
Thanks,
Thierry
----------------------------------------------------------------
arm64: tegra: Changes for v4.16-rc1
This set of patches enables a bunch of new features on Jetson TX2 that
were finally unblocked by the GPIO driver getting merged for v4.15.
----------------------------------------------------------------
Jon Hunter (1):
arm64: tegra: Add CPU and PSCI nodes for NVIDIA Tegra210 platforms
Thierry Reding (12):
dt-bindings: misc: Add Tegra186 MISC registers bindings
dt-bindings: memory: Add Tegra186 support
arm64: tegra: Add MISC registers on Tegra186
arm64: tegra: Add FUSE block on Tegra186
arm64: tegra: Add memory controller on Tegra186
arm64: tegra: Enable memory controller on P3310
arm64: tegra: Add SMMU node for Tegra186
arm64: tegra: Add display nodes on Tegra186
arm64: tegra: Mark I2C4 as DDC on P3310
arm64: tegra: Enable HDMI on Jetson TX2
arm64: tegra: Fix SD write-protect polarity on Jetson TX2
arm64: tegra: Use sor1_out clock
.../memory-controllers/nvidia,tegra30-mc.txt | 2 +
.../bindings/misc/nvidia,tegra186-misc.txt | 12 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-0000.dts | 51 +++
arch/arm64/boot/dts/nvidia/tegra186-p3310.dtsi | 10 +-
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 351 +++++++++++++++++++++
arch/arm64/boot/dts/nvidia/tegra210-p2180.dtsi | 23 ++
arch/arm64/boot/dts/nvidia/tegra210-p2530.dtsi | 23 ++
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 4 +-
include/dt-bindings/memory/tegra186-mc.h | 111 +++++++
9 files changed, 582 insertions(+), 5 deletions(-)
create mode 100644 Documentation/devicetree/bindings/misc/nvidia,tegra186-misc.txt
create mode 100644 include/dt-bindings/memory/tegra186-mc.h
^ permalink raw reply
* [RFC PATCH v2 1/3] PCI: rockchip: Add support for pcie wake irq
From: Tony Lindgren @ 2017-12-20 19:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171219004811.GA216620@google.com>
Hi,
* Brian Norris <briannorris@chromium.org> [171219 00:50]:
> On Wed, Aug 23, 2017 at 09:32:39AM +0800, Jeffy Chen wrote:
>
> Did this problem ever get resolved? To be clear, I believe the problem
> at hand is:
>
> (a) in suspend/resume (not runtime PM; we may not even have runtime PM
> support for most PCI devices)
It seems it should be enough to implement runtime PM in the PCI
controller. Isn't each PCI WAKE# line is wired from each PCI device
to the PCI controller?
Then the PCI controller can figure out from which PCI device the
WAKE# came from.
> Options I can think of:
> (1) implement runtime PM callbacks for all PCI devices, where we clear
> any PME status and ensure WAKE# stops asserting [1]
I don't think this is needed, it should be enough to have just
the PCI controller implement runtime PM :)
Regards,
Tony
^ permalink raw reply
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