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* [PATCH 2/3] [v8] pinctrl: qcom: disable GPIO groups with no pins
From: Timur Tabi @ 2017-12-20 19:10 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1513797033-9494-1-git-send-email-timur@codeaurora.org>

pinctrl-msm only accepts an array of GPIOs from 0 to n-1, and it expects
each group to support have only one pin (npins == 1).

We can support "sparse" GPIO maps if we allow for some groups to have zero
pins (npins == 0).  These pins are "hidden" from the rest of the driver
and gpiolib.

Access to unavailable GPIOs is blocked via a request callback.  If the
requested GPIO is unavailable, -EACCES is returned, which prevents
further access to that GPIO.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 drivers/pinctrl/qcom/pinctrl-msm.c | 28 +++++++++++++++++++++++-----
 1 file changed, 23 insertions(+), 5 deletions(-)

diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 7a960590ecaa..d45b4c2b5af1 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -507,6 +507,11 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 	};
 
 	g = &pctrl->soc->groups[offset];
+
+	/* If the GPIO group has no pins, then don't show it. */
+	if (!g->npins)
+		return;
+
 	ctl_reg = readl(pctrl->regs + g->ctl_reg);
 
 	is_out = !!(ctl_reg & BIT(g->oe_bit));
@@ -516,7 +521,7 @@ static void msm_gpio_dbg_show_one(struct seq_file *s,
 
 	seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
 	seq_printf(s, " %dmA", msm_regval_to_drive(drive));
-	seq_printf(s, " %s", pulls[pull]);
+	seq_printf(s, " %s\n", pulls[pull]);
 }
 
 static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
@@ -524,23 +529,36 @@ static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
 	unsigned gpio = chip->base;
 	unsigned i;
 
-	for (i = 0; i < chip->ngpio; i++, gpio++) {
+	for (i = 0; i < chip->ngpio; i++, gpio++)
 		msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
-		seq_puts(s, "\n");
-	}
 }
 
 #else
 #define msm_gpio_dbg_show NULL
 #endif
 
+/*
+ * If the requested GPIO has no pins, then treat it as unavailable.
+ * Otherwise, call the standard request function.
+ */
+static int msm_gpio_request(struct gpio_chip *chip, unsigned int offset)
+{
+	struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
+	const struct msm_pingroup *g = &pctrl->soc->groups[offset];
+
+	if (!g->npins)
+		return -EACCES;
+
+	return gpiochip_generic_request(chip, offset);
+}
+
 static const struct gpio_chip msm_gpio_template = {
 	.direction_input  = msm_gpio_direction_input,
 	.direction_output = msm_gpio_direction_output,
 	.get_direction    = msm_gpio_get_direction,
 	.get              = msm_gpio_get,
 	.set              = msm_gpio_set,
-	.request          = gpiochip_generic_request,
+	.request          = msm_gpio_request,
 	.free             = gpiochip_generic_free,
 	.dbg_show         = msm_gpio_dbg_show,
 };
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

^ permalink raw reply related

* [PATCH 1/3] [v2] Revert "gpio: set up initial state from .get_direction()"
From: Timur Tabi @ 2017-12-20 19:10 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1513797033-9494-1-git-send-email-timur@codeaurora.org>

This reverts commit 72d3200061776264941be1b5a9bb8e926b3b30a5.

We cannot blindly query the direction of all GPIOs when the pins are
first registered.  The get_direction callback normally triggers a
read/write to hardware, but we shouldn't be touching the hardware for
an individual GPIO until after it's been properly claimed.

Signed-off-by: Timur Tabi <timur@codeaurora.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
---
 drivers/gpio/gpiolib.c | 31 +++++++------------------------
 1 file changed, 7 insertions(+), 24 deletions(-)

diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index aad84a6306c4..d21ad0bbbd0d 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1207,31 +1207,14 @@ int gpiochip_add_data_with_key(struct gpio_chip *chip, void *data,
 		struct gpio_desc *desc = &gdev->descs[i];
 
 		desc->gdev = gdev;
-		/*
-		 * REVISIT: most hardware initializes GPIOs as inputs
-		 * (often with pullups enabled) so power usage is
-		 * minimized. Linux code should set the gpio direction
-		 * first thing; but until it does, and in case
-		 * chip->get_direction is not set, we may expose the
-		 * wrong direction in sysfs.
-		 */
-
-		if (chip->get_direction) {
-			/*
-			 * If we have .get_direction, set up the initial
-			 * direction flag from the hardware.
-			 */
-			int dir = chip->get_direction(chip, i);
 
-			if (!dir)
-				set_bit(FLAG_IS_OUT, &desc->flags);
-		} else if (!chip->direction_input) {
-			/*
-			 * If the chip lacks the .direction_input callback
-			 * we logically assume all lines are outputs.
-			 */
-			set_bit(FLAG_IS_OUT, &desc->flags);
-		}
+		/* REVISIT: most hardware initializes GPIOs as inputs (often
+		 * with pullups enabled) so power usage is minimized. Linux
+		 * code should set the gpio direction first thing; but until
+		 * it does, and in case chip->get_direction is not set, we may
+		 * expose the wrong direction in sysfs.
+		 */
+		desc->flags = !chip->direction_input ? (1 << FLAG_IS_OUT) : 0;
 	}
 
 #ifdef CONFIG_PINCTRL
-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

^ permalink raw reply related

* [PATCH 0/3] [v11] pinctrl: qcom: add support for sparse GPIOs
From: Timur Tabi @ 2017-12-20 19:10 UTC (permalink / raw)
  To: linux-arm-kernel

A series of patches that add support for GPIO maps that have holes in
them.  That is, even though a client driver has N consecutive GPIOs,
some are just unavailable for whatever reason, and the hardware should
not be accessed for those GPIOs.

Patch 1 reverts an old patch that triggers a get_direction of every
pin upon init, without attempting to request the pins first.  The
direction is already being queried when the pin is requested.

Patch 2 adds support to pinctrl-msm for "unavailable" GPIOs.

Patch 3 extends that support to pinctrl-qdf2xxx.  A recent ACPI change
on QDF2400 platforms blocks access to most pins, so the driver can only
register a subset.

This version drops the availability check in gpiolib, because it's no
necessary.  Instead, just having pinctrl-msm return -EACCES is enough
to block all unavailable GPIOs.  Patch 1 removes the only instance where
an unrequested GPIO is being accessed.

v11:
  Drop support for QCOM8001

Timur Tabi (3):
  [v2] Revert "gpio: set up initial state from .get_direction()"
  [v8] pinctrl: qcom: disable GPIO groups with no pins
  [v7] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002

 drivers/gpio/gpiolib.c                 | 31 +++--------
 drivers/pinctrl/qcom/pinctrl-msm.c     | 28 ++++++++--
 drivers/pinctrl/qcom/pinctrl-qdf2xxx.c | 96 ++++++++++++++++++++++------------
 3 files changed, 94 insertions(+), 61 deletions(-)

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

^ permalink raw reply

* [PATCH v3 2/6] media: dt: bindings: Update binding documentation for sunxi IR controller
From: Rob Herring @ 2017-12-20 18:44 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171219080747.4507-3-embed3d@gmail.com>

On Tue, Dec 19, 2017 at 09:07:43AM +0100, Philipp Rossak wrote:
> This patch updates documentation for Device-Tree bindings for sunxi IR
> controller and adds the new optional property for the base clock
> frequency.
> 
> Signed-off-by: Philipp Rossak <embed3d@gmail.com>
> ---
>  Documentation/devicetree/bindings/media/sunxi-ir.txt | 3 +++
>  1 file changed, 3 insertions(+)

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* [PATCH 1/3] dt-bindings: i2c: Add MediaTek MT2712 i2c binding
From: Rob Herring @ 2017-12-20 18:43 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1513666263-6443-2-git-send-email-jun.gao@mediatek.com>

On Tue, Dec 19, 2017 at 02:51:01PM +0800, Jun Gao wrote:
> From: Jun Gao <jun.gao@mediatek.com>
> 
> Add MT2712 i2c binding to binding file. Compare to MT8173 i2c
> controller, MT2712 has timing adjust registers which can adjust
> the internal divider of i2c source clock, SCL duty cycle, SCL
> compare point, start(repeated start) and stop time, SDA change
> time.
> 
> Signed-off-by: Jun Gao <jun.gao@mediatek.com>
> ---
>  Documentation/devicetree/bindings/i2c/i2c-mtk.txt | 1 +
>  1 file changed, 1 insertion(+)

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* [PATCH V2 4/9] devicetree: bindings: stm32: add support of STM32MP157
From: Rob Herring @ 2017-12-20 18:24 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1513610272-7824-5-git-send-email-ludovic.Barre@st.com>

On Mon, Dec 18, 2017 at 04:17:47PM +0100, Ludovic Barre wrote:
> From: Ludovic Barre <ludovic.barre@st.com>
> 
> This patch adds STM32MP157 SoC bindings.
> 
> Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
> ---
>  Documentation/devicetree/bindings/arm/stm32.txt | 1 +
>  1 file changed, 1 insertion(+)

"dt-bindings: ..." is the preferred subject prefix. Otherwise,

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* [PATCH 2/2] drm/rockchip: Remove analogix psr worker.
From: Enric Balletbo i Serra @ 2017-12-20 18:20 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171220182044.20331-1-enric.balletbo@collabora.com>

From: Sean Paul <seanpaul@chromium.org>

Now that the spinlocks and timers are gone, we can remove the psr
worker located in rockchip's analogix driver and do the enable/disable
directly. This should simplify the code and remove races on disable.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 30 ++-----------------------
 1 file changed, 2 insertions(+), 28 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
index 93b7102..d32c9b3 100644
--- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
+++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c
@@ -71,10 +71,6 @@ struct rockchip_dp_device {
 	struct regmap            *grf;
 	struct reset_control     *rst;
 
-	struct work_struct	 psr_work;
-	struct mutex             psr_lock;
-	unsigned int             psr_state;
-
 	const struct rockchip_dp_chip_data *data;
 
 	struct analogix_dp_plat_data plat_data;
@@ -83,27 +79,13 @@ struct rockchip_dp_device {
 static void analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
 {
 	struct rockchip_dp_device *dp = to_dp(encoder);
+	int ret;
 
 	if (!analogix_dp_psr_supported(dp->dev))
 		return;
 
 	DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
 
-	mutex_lock(&dp->psr_lock);
-	if (enabled)
-		dp->psr_state = EDP_VSC_PSR_STATE_ACTIVE;
-	else
-		dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
-
-	schedule_work(&dp->psr_work);
-	mutex_unlock(&dp->psr_lock);
-}
-
-static void analogix_dp_psr_work(struct work_struct *work)
-{
-	struct rockchip_dp_device *dp =
-				container_of(work, typeof(*dp), psr_work);
-	int ret;
 
 	ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
 					 PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
@@ -112,12 +94,10 @@ static void analogix_dp_psr_work(struct work_struct *work)
 		return;
 	}
 
-	mutex_lock(&dp->psr_lock);
-	if (dp->psr_state == EDP_VSC_PSR_STATE_ACTIVE)
+	if (enabled)
 		analogix_dp_enable_psr(dp->dev);
 	else
 		analogix_dp_disable_psr(dp->dev);
-	mutex_unlock(&dp->psr_lock);
 }
 
 static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
@@ -134,8 +114,6 @@ static int rockchip_dp_poweron(struct analogix_dp_plat_data *plat_data)
 	struct rockchip_dp_device *dp = to_dp(plat_data);
 	int ret;
 
-	cancel_work_sync(&dp->psr_work);
-
 	ret = clk_prepare_enable(dp->pclk);
 	if (ret < 0) {
 		DRM_DEV_ERROR(dp->dev, "failed to enable pclk %d\n", ret);
@@ -379,10 +357,6 @@ static int rockchip_dp_bind(struct device *dev, struct device *master,
 	dp->plat_data.power_off = rockchip_dp_powerdown;
 	dp->plat_data.get_modes = rockchip_dp_get_modes;
 
-	mutex_init(&dp->psr_lock);
-	dp->psr_state = ~EDP_VSC_PSR_STATE_ACTIVE;
-	INIT_WORK(&dp->psr_work, analogix_dp_psr_work);
-
 	rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
 
 	return analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
-- 
2.9.3

^ permalink raw reply related

* [PATCH 1/2] drm/rockchip: Don't use atomic constructs for psr
From: Enric Balletbo i Serra @ 2017-12-20 18:20 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171220182044.20331-1-enric.balletbo@collabora.com>

From: Sean Paul <seanpaul@chromium.org>

Instead of using timer and spinlocks, use delayed_work and
mutexes for rockchip psr. This allows us to make blocking
calls when enabling/disabling psr (which is sort of important
given we're talking over dpcd to the display).

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_psr.c | 63 +++++++++++++----------------
 3 files changed, 29 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
index 76d63de..cd7ae12 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.c
@@ -134,7 +134,7 @@ static int rockchip_drm_bind(struct device *dev)
 	drm_dev->dev_private = private;
 
 	INIT_LIST_HEAD(&private->psr_list);
-	spin_lock_init(&private->psr_list_lock);
+	mutex_init(&private->psr_list_lock);
 
 	ret = rockchip_drm_init_iommu(drm_dev);
 	if (ret)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
index 498dfbc..9c064a4 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h
@@ -55,7 +55,7 @@ struct rockchip_drm_private {
 	struct mutex mm_lock;
 	struct drm_mm mm;
 	struct list_head psr_list;
-	spinlock_t psr_list_lock;
+	struct mutex psr_list_lock;
 };
 
 int rockchip_drm_dma_attach_device(struct drm_device *drm_dev,
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
index 3acfd57..a3f6ec0 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_psr.c
@@ -18,7 +18,7 @@
 #include "rockchip_drm_drv.h"
 #include "rockchip_drm_psr.h"
 
-#define PSR_FLUSH_TIMEOUT	msecs_to_jiffies(100)
+#define PSR_FLUSH_TIMEOUT_MS	100
 
 enum psr_state {
 	PSR_FLUSH,
@@ -30,11 +30,11 @@ struct psr_drv {
 	struct list_head	list;
 	struct drm_encoder	*encoder;
 
-	spinlock_t		lock;
+	struct mutex		lock;
 	bool			active;
 	enum psr_state		state;
 
-	struct timer_list	flush_timer;
+	struct delayed_work	flush_work;
 
 	void (*set)(struct drm_encoder *encoder, bool enable);
 };
@@ -43,9 +43,8 @@ static struct psr_drv *find_psr_by_crtc(struct drm_crtc *crtc)
 {
 	struct rockchip_drm_private *drm_drv = crtc->dev->dev_private;
 	struct psr_drv *psr;
-	unsigned long flags;
 
-	spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+	mutex_lock(&drm_drv->psr_list_lock);
 	list_for_each_entry(psr, &drm_drv->psr_list, list) {
 		if (psr->encoder->crtc == crtc)
 			goto out;
@@ -53,7 +52,7 @@ static struct psr_drv *find_psr_by_crtc(struct drm_crtc *crtc)
 	psr = ERR_PTR(-ENODEV);
 
 out:
-	spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+	mutex_unlock(&drm_drv->psr_list_lock);
 	return psr;
 }
 
@@ -94,23 +93,21 @@ static void psr_set_state_locked(struct psr_drv *psr, enum psr_state state)
 
 static void psr_set_state(struct psr_drv *psr, enum psr_state state)
 {
-	unsigned long flags;
-
-	spin_lock_irqsave(&psr->lock, flags);
+	mutex_lock(&psr->lock);
 	psr_set_state_locked(psr, state);
-	spin_unlock_irqrestore(&psr->lock, flags);
+	mutex_unlock(&psr->lock);
 }
 
-static void psr_flush_handler(struct timer_list *t)
+static void psr_flush_handler(struct work_struct *work)
 {
-	struct psr_drv *psr = from_timer(psr, t, flush_timer);
-	unsigned long flags;
+	struct psr_drv *psr = container_of(to_delayed_work(work),
+					   struct psr_drv, flush_work);
 
 	/* If the state has changed since we initiated the flush, do nothing */
-	spin_lock_irqsave(&psr->lock, flags);
+	mutex_lock(&psr->lock);
 	if (psr->state == PSR_FLUSH)
 		psr_set_state_locked(psr, PSR_ENABLE);
-	spin_unlock_irqrestore(&psr->lock, flags);
+	mutex_unlock(&psr->lock);
 }
 
 /**
@@ -123,14 +120,13 @@ static void psr_flush_handler(struct timer_list *t)
 int rockchip_drm_psr_activate(struct drm_crtc *crtc)
 {
 	struct psr_drv *psr = find_psr_by_crtc(crtc);
-	unsigned long flags;
 
 	if (IS_ERR(psr))
 		return PTR_ERR(psr);
 
-	spin_lock_irqsave(&psr->lock, flags);
+	mutex_lock(&psr->lock);
 	psr->active = true;
-	spin_unlock_irqrestore(&psr->lock, flags);
+	mutex_unlock(&psr->lock);
 
 	return 0;
 }
@@ -146,15 +142,14 @@ EXPORT_SYMBOL(rockchip_drm_psr_activate);
 int rockchip_drm_psr_deactivate(struct drm_crtc *crtc)
 {
 	struct psr_drv *psr = find_psr_by_crtc(crtc);
-	unsigned long flags;
 
 	if (IS_ERR(psr))
 		return PTR_ERR(psr);
 
-	spin_lock_irqsave(&psr->lock, flags);
+	mutex_lock(&psr->lock);
 	psr->active = false;
-	spin_unlock_irqrestore(&psr->lock, flags);
-	del_timer_sync(&psr->flush_timer);
+	mutex_unlock(&psr->lock);
+	cancel_delayed_work_sync(&psr->flush_work);
 
 	return 0;
 }
@@ -162,8 +157,7 @@ EXPORT_SYMBOL(rockchip_drm_psr_deactivate);
 
 static void rockchip_drm_do_flush(struct psr_drv *psr)
 {
-	mod_timer(&psr->flush_timer,
-		  round_jiffies_up(jiffies + PSR_FLUSH_TIMEOUT));
+	schedule_delayed_work(&psr->flush_work, PSR_FLUSH_TIMEOUT_MS);
 	psr_set_state(psr, PSR_FLUSH);
 }
 
@@ -201,12 +195,11 @@ void rockchip_drm_psr_flush_all(struct drm_device *dev)
 {
 	struct rockchip_drm_private *drm_drv = dev->dev_private;
 	struct psr_drv *psr;
-	unsigned long flags;
 
-	spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+	mutex_lock(&drm_drv->psr_list_lock);
 	list_for_each_entry(psr, &drm_drv->psr_list, list)
 		rockchip_drm_do_flush(psr);
-	spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+	mutex_unlock(&drm_drv->psr_list_lock);
 }
 EXPORT_SYMBOL(rockchip_drm_psr_flush_all);
 
@@ -223,7 +216,6 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
 {
 	struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
 	struct psr_drv *psr;
-	unsigned long flags;
 
 	if (!encoder || !psr_set)
 		return -EINVAL;
@@ -232,17 +224,17 @@ int rockchip_drm_psr_register(struct drm_encoder *encoder,
 	if (!psr)
 		return -ENOMEM;
 
-	timer_setup(&psr->flush_timer, psr_flush_handler, 0);
-	spin_lock_init(&psr->lock);
+	INIT_DELAYED_WORK(&psr->flush_work, psr_flush_handler);
+	mutex_init(&psr->lock);
 
 	psr->active = true;
 	psr->state = PSR_DISABLE;
 	psr->encoder = encoder;
 	psr->set = psr_set;
 
-	spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+	mutex_lock(&drm_drv->psr_list_lock);
 	list_add_tail(&psr->list, &drm_drv->psr_list);
-	spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+	mutex_unlock(&drm_drv->psr_list_lock);
 
 	return 0;
 }
@@ -260,16 +252,15 @@ void rockchip_drm_psr_unregister(struct drm_encoder *encoder)
 {
 	struct rockchip_drm_private *drm_drv = encoder->dev->dev_private;
 	struct psr_drv *psr, *n;
-	unsigned long flags;
 
-	spin_lock_irqsave(&drm_drv->psr_list_lock, flags);
+	mutex_lock(&drm_drv->psr_list_lock);
 	list_for_each_entry_safe(psr, n, &drm_drv->psr_list, list) {
 		if (psr->encoder == encoder) {
-			del_timer(&psr->flush_timer);
+			cancel_delayed_work_sync(&psr->flush_work);
 			list_del(&psr->list);
 			kfree(psr);
 		}
 	}
-	spin_unlock_irqrestore(&drm_drv->psr_list_lock, flags);
+	mutex_unlock(&drm_drv->psr_list_lock);
 }
 EXPORT_SYMBOL(rockchip_drm_psr_unregister);
-- 
2.9.3

^ permalink raw reply related

* [PATCH 0/2] drm/rockchip: Fix sleeping function called from invalid context
From: Enric Balletbo i Serra @ 2017-12-20 18:20 UTC (permalink / raw)
  To: linux-arm-kernel

Dear all,

After enable the debug option to check sleep inside atomic section I got
lots of messages from the drm/rockchip driver using current 4.15-rc4

 BUG: sleeping function called from invalid context at kernel/locking/mutex.c:238
 in_atomic(): 1, irqs_disabled(): 128, pid: 3457, name: Xorg
 CPU: 3 PID: 3457 Comm: Xorg Tainted: G        W        4.15.0-rc4+ #56
 Hardware name: Google Kevin (DT)
 Call trace:
  dump_backtrace+0x0/0x1a8
  show_stack+0x24/0x30
  dump_stack+0xb8/0xf0
  ___might_sleep+0x110/0x140
  __might_sleep+0x58/0x90
  mutex_lock+0x2c/0x68
  analogix_dp_psr_set+0x78/0x100
  rockchip_drm_do_flush+0x6c/0x88
  rockchip_drm_psr_flush_all+0x48/0x70
  rockchip_drm_fb_dirty+0x20/0x30
  drm_mode_dirtyfb_ioctl+0x1c4/0x1f8
  drm_ioctl_kernel+0x74/0xd0
  drm_ioctl+0x2b8/0x3c0
  do_vfs_ioctl+0xb0/0x818
  SyS_ioctl+0x94/0xa8
  el0_svc_naked+0x20/0x24

The two patches in this patchset were sent by Sean Paul some time ago
([1][2]) but never landed in mainline, the patches in question can fix the
issue reported and I think that could be interesting include both in this
release cycle, hence I'm resending it. The patches were rebased on top of
mainline.

[1] https://patchwork.kernel.org/patch/9382847/
[2] https://patchwork.kernel.org/patch/9614679/

Best regards,
 Enric

Sean Paul (2):
  drm/rockchip: Don't use atomic constructs for psr
  drm/rockchip: Remove analogix psr worker.

 drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 30 +-----------
 drivers/gpu/drm/rockchip/rockchip_drm_drv.c     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_drv.h     |  2 +-
 drivers/gpu/drm/rockchip/rockchip_drm_psr.c     | 63 +++++++++++--------------
 4 files changed, 31 insertions(+), 66 deletions(-)

-- 
2.9.3

^ permalink raw reply

* [PATCH] crypto: stm32 - Use standard CONFIG name
From: Corentin Labbe @ 2017-12-20 18:19 UTC (permalink / raw)
  To: linux-arm-kernel

All hardware crypto devices have their CONFIG names using the following
convention:
CRYPTO_DEV_name_algo

This patch apply this conventions on STM32 CONFIG names.

Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
---
 drivers/crypto/stm32/Kconfig  | 6 +++---
 drivers/crypto/stm32/Makefile | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/drivers/crypto/stm32/Kconfig b/drivers/crypto/stm32/Kconfig
index 61ef00b6bf45..63aa78c0b12b 100644
--- a/drivers/crypto/stm32/Kconfig
+++ b/drivers/crypto/stm32/Kconfig
@@ -1,4 +1,4 @@
-config CRC_DEV_STM32
+config CRYPTO_DEV_STM32_CRC
 	tristate "Support for STM32 crc accelerators"
 	depends on ARCH_STM32
 	select CRYPTO_HASH
@@ -6,7 +6,7 @@ config CRC_DEV_STM32
           This enables support for the CRC32 hw accelerator which can be found
 	  on STMicroelectronics STM32 SOC.
 
-config HASH_DEV_STM32
+config CRYPTO_DEV_STM32_HASH
 	tristate "Support for STM32 hash accelerators"
 	depends on ARCH_STM32
 	depends on HAS_DMA
@@ -19,7 +19,7 @@ config HASH_DEV_STM32
           This enables support for the HASH hw accelerator which can be found
 	  on STMicroelectronics STM32 SOC.
 
-config CRYP_DEV_STM32
+config CRYPTO_DEV_STM32_CRYP
 	tristate "Support for STM32 cryp accelerators"
 	depends on ARCH_STM32
 	select CRYPTO_HASH
diff --git a/drivers/crypto/stm32/Makefile b/drivers/crypto/stm32/Makefile
index 2c19fc155bfd..53d1bb94b221 100644
--- a/drivers/crypto/stm32/Makefile
+++ b/drivers/crypto/stm32/Makefile
@@ -1,3 +1,3 @@
-obj-$(CONFIG_CRC_DEV_STM32) += stm32_crc32.o
-obj-$(CONFIG_HASH_DEV_STM32) += stm32-hash.o
-obj-$(CONFIG_CRYP_DEV_STM32) += stm32-cryp.o
+obj-$(CONFIG_CRYPTO_DEV_STM32_CRC) += stm32_crc32.o
+obj-$(CONFIG_CRYPTO_DEV_STM32_HASH) += stm32-hash.o
+obj-$(CONFIG_CRYPTO_DEV_STM32_CRYP) += stm32-cryp.o
-- 
2.13.6

^ permalink raw reply related

* [PATCH v4 11/16] dt-bindings: Document the Rockchip MIPI RX D-PHY bindings
From: Rob Herring @ 2017-12-20 18:16 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171218121445.6086-8-jacob-chen@iotwrt.com>

On Mon, Dec 18, 2017 at 08:14:40PM +0800, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
> 
> Add DT bindings documentation for Rockchip MIPI D-PHY RX
> 
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
>  .../bindings/media/rockchip-mipi-dphy.txt          | 88 ++++++++++++++++++++++
>  1 file changed, 88 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/rockchip-mipi-dphy.txt

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* [PATCH v4 10/16] dt-bindings: Document the Rockchip ISP1 bindings
From: Rob Herring @ 2017-12-20 18:14 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171218121445.6086-7-jacob-chen@iotwrt.com>

On Mon, Dec 18, 2017 at 08:14:39PM +0800, Jacob Chen wrote:
> From: Jacob Chen <jacob2.chen@rock-chips.com>
> 
> Add DT bindings documentation for Rockchip ISP1
> 
> Signed-off-by: Jacob Chen <jacob2.chen@rock-chips.com>
> ---
>  .../devicetree/bindings/media/rockchip-isp1.txt    | 69 ++++++++++++++++++++++
>  1 file changed, 69 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/media/rockchip-isp1.txt

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* [PATCH v4 1/4] dt-bindings: rtc: add bindings for i.MX53 SRTC
From: Rob Herring @ 2017-12-20 18:13 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171218115133.16371-2-linux-kernel-dev@beckhoff.com>

On Mon, Dec 18, 2017 at 12:51:30PM +0100, linux-kernel-dev at beckhoff.com wrote:
> From: Patrick Bruenn <p.bruenn@beckhoff.com>
> 
> Document the binding for i.MX53 SRTC implemented by rtc-mxc_v2
> 
> Signed-off-by: Patrick Bruenn <p.bruenn@beckhoff.com>

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* [PATCH 1/9] dt-bindings: ti-sysc: Update binding for timers and capabilities
From: Rob Herring @ 2017-12-20 18:10 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171216192222.GH3875@atomide.com>

On Sat, Dec 16, 2017 at 11:22:22AM -0800, Tony Lindgren wrote:
> * Rob Herring <robh@kernel.org> [171216 18:33]:
> > >  Optional properties:
> > >  
> > > +- ti,sysc-mask	shall contain mask of supported register bits for the
> > > +		SYSCONFIG register as documented in the Technical Reference
> > > +		Manual (TRM) for the interconnect target module
> > > +
> > > +- ti,sysc-midle	list of master idle modes supported by the interconnect
> > > +		target module as documented in the TRM for SYSCONFIG
> > > +		register MIDLEMODE bits
> > > +
> > > +- ti,sysc-sidle	list of slave idle modes supported by the interconnect
> > > +		target module as documented in the TRM for SYSCONFIG
> > > +		register SIDLEMODE bits
> > > +
> > > +- ti,sysc-delay-us	delay needed after OCP softreset before accssing
> > > +			SYSCONFIG register again
> > > +
> > > +- ti,syss-mask	optional mask of reset done status bits as described in the
> > > +		TRM for SYSSTATUS registers, typically 1 with some devices
> > > +		having separate reset done bits for children like OHCI and
> > > +		EHCI
> > > +
> > 
> > Seems like a lot of this should be implied by specific compatible 
> > strings.
> 
> Unfortunately that would still explode the permutations to almost
> one compatible per module especially for types "ti,sysc-omap2" and
> "ti,sysc-omap4". And the features and idle modes supported by the
> module are all over the place for "ti,sysc-mask", "ti,sysc-midle",
> "ti,sysc-sidle" and "ti,syss-mask"..

Okay.

> I was planning to have "ti,sysc-delay-us" only in the driver, but
> the same IP needs it set on dm814x while not on omap4 for OTG
> for example. I could add SoC specific quirks to the driver
> for that one if you prefer that instead?

No, I don't have a preference.

> I do have a patch also I'm testing to use the revision register
> value for handling further quirks, but unfortunately that
> register is not populated or updated for many modules. And it's
> only usable after the module is already configured to accessible :)
> 
> > Are the bits you've defined all of them or there's more?
> 
> That's it, with this binding I've allocated the data from dts
> for the tests I've done. So that should allow us to replace the
> static data to start with as seen with the following command:
> 
> $ git grep -A10 "struct omap_hwmod_class_sysconfig" \
> 	arch/arm/*hwmod*data*.c
> ...
> 
> So that's to configure a big pile of different module
> configurations we currently have as can be seen with:
> 
> $ git grep "struct omap_hwmod_class_sysconfig" \
> 	arch/arm/*hwmod*data*.c | wc -l
> 194
> 
> I'm sure there's still few duplicates there though..

Okay, then I guess I'm okay with this.

Reviewed-by: Rob Herring <robh@kernel.org>

^ permalink raw reply

* [PATCH] ARM: dts: imx: Add memory node unit name
From: Fabio Estevam @ 2017-12-20 18:05 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1512575989-15627-1-git-send-email-marcofrk@gmail.com>

On Wed, Dec 6, 2017 at 1:59 PM, Marco Franchi <marcofrk@gmail.com> wrote:
> Fix the following warnings from dtc by adding the unit name to memory
> nodes:
>
> Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
>
> Converted using the following command:
>
> perl -p0777i -e 's/memory \{\n\t\treg = \<0x+([0-9a-f])/memory\@$1$\0000000 \{\n\t\treg = <0x$1/m' `find ./arch/arm/boot/dts -name "imx*"`
>
> The files below were manually fixed:
> -imx1-ads.dts
> -imx1-apf9328.dts
>
> Signed-off-by: Marco Franchi <marcofrk@gmail.com>

Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>

^ permalink raw reply

* [PATCH v7 5/6] arm: dts: mt2712: Add clock controller device nodes
From: Matthias Brugger @ 2017-12-20 18:03 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1511854102-23195-7-git-send-email-weiyi.lu@mediatek.com>



On 11/28/2017 08:28 AM, Weiyi Lu wrote:
> Add clock controller nodes for MT2712, include topckgen, infracfg,
> pericfg, mcucfg and apmixedsys. This patch also add six oscillators that
> provide clocks for MT2712.
> 
> Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> ---
>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 115 ++++++++++++++++++++++++++++++
>  1 file changed, 115 insertions(+)

I fixed the subject line for you, but the next time please take care to start
the line with "arm64" instead of "arm"

Thanks,
Matthias

> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> index 5d4e406..5703793 100644
> --- a/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt2712e.dtsi
> @@ -5,6 +5,7 @@
>   * SPDX-License-Identifier: (GPL-2.0 OR MIT)
>   */
>  
> +#include <dt-bindings/clock/mt2712-clk.h>
>  #include <dt-bindings/interrupt-controller/irq.h>
>  #include <dt-bindings/interrupt-controller/arm-gic.h>
>  
> @@ -98,6 +99,48 @@
>  		#clock-cells = <0>;
>  	};
>  
> +	clk26m: oscillator at 0 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <26000000>;
> +		clock-output-names = "clk26m";
> +	};
> +
> +	clk32k: oscillator at 1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <32768>;
> +		clock-output-names = "clk32k";
> +	};
> +
> +	clkfpc: oscillator at 2 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <50000000>;
> +		clock-output-names = "clkfpc";
> +	};
> +
> +	clkaud_ext_i_0: oscillator at 3 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <6500000>;
> +		clock-output-names = "clkaud_ext_i_0";
> +	};
> +
> +	clkaud_ext_i_1: oscillator at 4 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <196608000>;
> +		clock-output-names = "clkaud_ext_i_1";
> +	};
> +
> +	clkaud_ext_i_2: oscillator at 5 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <180633600>;
> +		clock-output-names = "clkaud_ext_i_2";
> +	};
> +
>  	timer {
>  		compatible = "arm,armv8-timer";
>  		interrupt-parent = <&gic>;
> @@ -111,6 +154,24 @@
>  			      (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>;
>  	};
>  
> +	topckgen: syscon at 10000000 {
> +		compatible = "mediatek,mt2712-topckgen", "syscon";
> +		reg = <0 0x10000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	infracfg: syscon at 10001000 {
> +		compatible = "mediatek,mt2712-infracfg", "syscon";
> +		reg = <0 0x10001000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	pericfg: syscon at 10003000 {
> +		compatible = "mediatek,mt2712-pericfg", "syscon";
> +		reg = <0 0x10003000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
>  	uart5: serial at 1000f000 {
>  		compatible = "mediatek,mt2712-uart",
>  			     "mediatek,mt6577-uart";
> @@ -121,6 +182,18 @@
>  		status = "disabled";
>  	};
>  
> +	apmixedsys: syscon at 10209000 {
> +		compatible = "mediatek,mt2712-apmixedsys", "syscon";
> +		reg = <0 0x10209000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	mcucfg: syscon at 10220000 {
> +		compatible = "mediatek,mt2712-mcucfg", "syscon";
> +		reg = <0 0x10220000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
>  	sysirq: interrupt-controller at 10220a80 {
>  		compatible = "mediatek,mt2712-sysirq",
>  			     "mediatek,mt6577-sysirq";
> @@ -192,5 +265,47 @@
>  		clock-names = "baud", "bus";
>  		status = "disabled";
>  	};
> +
> +	mfgcfg: syscon at 13000000 {
> +		compatible = "mediatek,mt2712-mfgcfg", "syscon";
> +		reg = <0 0x13000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	mmsys: syscon at 14000000 {
> +		compatible = "mediatek,mt2712-mmsys", "syscon";
> +		reg = <0 0x14000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	imgsys: syscon at 15000000 {
> +		compatible = "mediatek,mt2712-imgsys", "syscon";
> +		reg = <0 0x15000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	bdpsys: syscon at 15010000 {
> +		compatible = "mediatek,mt2712-bdpsys", "syscon";
> +		reg = <0 0x15010000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	vdecsys: syscon at 16000000 {
> +		compatible = "mediatek,mt2712-vdecsys", "syscon";
> +		reg = <0 0x16000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	vencsys: syscon at 18000000 {
> +		compatible = "mediatek,mt2712-vencsys", "syscon";
> +		reg = <0 0x18000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
> +
> +	jpgdecsys: syscon at 19000000 {
> +		compatible = "mediatek,mt2712-jpgdecsys", "syscon";
> +		reg = <0 0x19000000 0 0x1000>;
> +		#clock-cells = <1>;
> +	};
>  };
>  
> 

^ permalink raw reply

* [PATCH v7 0/6] Mediatek MT2712 clock and scpsys support
From: Matthias Brugger @ 2017-12-20 18:02 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <1513317052.30745.1.camel@mtksdaap41>



On 12/15/2017 06:50 AM, Weiyi Lu wrote:
> On Tue, 2017-11-28 at 15:28 +0800, Weiyi Lu wrote:
> 
> Hi Matthias,
> Just gentle ping. Many thanks.
> 

Now pushed to v4.15-next thanks


>> This series is based on v4.15-rc1 and composed of
>> scpsys control (PATCH 1-4) and device tree (PATCH 5-6)
>>
>> changes since v6:
>> - Rebase to v4.15-rc1.
>>
>> changes since v5:
>> - Refine bus protection with proper variable name
>>   and better implementation for the if statement.
>>
>> changes since v4:
>> - Refine scpsys and infracfg for bus protection by passing
>>   a boolean flag to determine the register update method
>>
>> changes since v3:
>> - Rebase to v4.14-rc1.
>>
>> changes since v2:
>> - ensure the clocks used by clocksource driver are registered
>>   before clocksource init() by using CLK_OF_DECLARE()
>> - correct the frequency of clk32k/clkrtc_ext/clkrtc_int
>>
>> changes since v1:
>> - Rebase to v4.13-next-soc.
>> - Refine scpsys and infracfg for bus protection.
>>
>> *** BLURB HERE ***
>>
>> Weiyi Lu (6):
>>   dt-bindings: soc: add MT2712 power dt-bindings
>>   soc: mediatek: extend bus protection API
>>   soc: mediatek: add dependent clock jpgdec/audio for scpsys
>>   soc: mediatek: add MT2712 scpsys support
>>   arm: dts: mt2712: Add clock controller device nodes
>>   arm: dts: Add power controller device node of MT2712
>>
>>  .../devicetree/bindings/soc/mediatek/scpsys.txt    |   3 +
>>  arch/arm64/boot/dts/mediatek/mt2712e.dtsi          | 131 +++++++++++++++++++
>>  drivers/soc/mediatek/mtk-infracfg.c                |  26 +++-
>>  drivers/soc/mediatek/mtk-scpsys.c                  | 140 ++++++++++++++++++---
>>  include/dt-bindings/power/mt2712-power.h           |  26 ++++
>>  include/linux/soc/mediatek/infracfg.h              |   7 +-
>>  6 files changed, 311 insertions(+), 22 deletions(-)
>>  create mode 100644 include/dt-bindings/power/mt2712-power.h
>>
> 
> 

^ permalink raw reply

* [PATCH 3/3] [v6] pinctrl: qcom: qdf2xxx: add support for new ACPI HID QCOM8002
From: Timur Tabi @ 2017-12-20 17:46 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171220081556.GA30524@codeaurora.org>

On 12/20/2017 02:15 AM, Stephen Boyd wrote:
> Here's the patch. I get a hang when dumping debugfs, but at least
> sysfs expose fails when trying to request blocked gpios. I need
> to check if we need to say "yes" to pins that are above the gpio
> max for pinctrl. I'll do that tomorrow.

Sorry, I just don't see how this is better than my patches.  I don't 
understand the need for involving the IRQ valid mask.  I also don't see 
the value in adding code to look for a property that exists only in one 
ACPI HID (QCOM8002) as if it were generic.  The "num-gpios" and "gpios" 
DSDs are not supposed to exist in any other HID, so there should be no 
code that reads it in pinctrl-msm.

I'm going on vacation soon.  I will post a v11 that eliminates support 
for QCOM8001.  Maybe that version is "good enough" for now and you can 
add DT and/or IRQ support on top of it.

-- 
Qualcomm Datacenter Technologies, Inc. as an affiliate of Qualcomm
Technologies, Inc.  Qualcomm Technologies, Inc. is a member of the
Code Aurora Forum, a Linux Foundation Collaborative Project.

^ permalink raw reply

* [GIT PULL 2/3] arm64: dts: exynos: DTS for v4.16
From: Krzysztof Kozlowski @ 2017-12-20 17:36 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171220173643.5840-1-krzk@kernel.org>


The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt64-4.16

for you to fetch changes up to 3808354701090723b53c73afaccfcafdeb8a5bfe:

  arm64: dts: exynos: Increase bus frequency for MHL chip (2017-12-04 17:51:10 +0100)

----------------------------------------------------------------
Samsung DTS ARM64 changes for v4.16

1. Add CPU perf counters to Exynos5433.
2. Add missing power domains to Exynos5433.
3. Add NFC chip to Exynos5433 TM2/TM2E.
4. Fix obscure bugs on I2C transfers to MHL chip on TM2/TM2E.

----------------------------------------------------------------
Andrzej Hajda (1):
      arm64: dts: exynos: Increase bus frequency for MHL chip

Marek Szyprowski (8):
      arm64: dts: exynos: Add CPU performance counters to Exynos5433 boards
      arm64: dts: exynos: Add support for S3FWRN5 NFC chip to TM2(e) boards
      arm64: dts: exynos: Add GSCL power domain to Exynos 5433 SoC
      arm64: dts: exynos: Add DISP power domain to Exynos 5433 SoC
      arm64: dts: exynos: Add MSCL power domain to Exynos 5433 SoC
      arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC
      arm64: dts: exynos: Add AUD power domain to Exynos5433 SoC
      arm64: dts: exynos: Add remaining power domains to Exynos5433 SoC

 .../boot/dts/exynos/exynos5433-tm2-common.dtsi     |  14 +++
 arch/arm64/boot/dts/exynos/exynos5433.dtsi         | 132 +++++++++++++++++++++
 2 files changed, 146 insertions(+)

^ permalink raw reply

* [GIT PULL 1/3] ARM: dts: exynos: DTS for v4.16
From: Krzysztof Kozlowski @ 2017-12-20 17:36 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171220173643.5840-1-krzk@kernel.org>


The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt-4.16

for you to fetch changes up to 3be1ecf291df8191f5ea395d363acc8fa029b5fd:

  ARM: dts: exynos: Use lower case hex addresses in node unit addresses (2017-12-18 18:15:51 +0100)

----------------------------------------------------------------
Samsung DTS ARM changes for 4.16

1. Add sound support to Odroid XU4 (and adjustments to Odroid XU3).
2. Enable WiFi on Trats2.
3. Add CPU perf counters to Exynos54xx.
4. Add power domains to certain chipsets.
5. Add Exynos4412 ISP clock controller which finally solves freezes when
   accessing ISP clocks while having the ISP power domain turned off.
6. Add Pseudo and True RNG to Exynos5.
7. Minor fixes for Trats2, Odroid XU3/XU4, Exynos5410.
8. Cleanup of some of DTC warnings

----------------------------------------------------------------
Dongjin Kim (1):
      ARM: dts: exynos: Fix property values of LDO15/17 for Odroid XU3/XU4

Krzysztof Kozlowski (2):
      ARM: dts: exynos: Add missing interrupt-controller properties to Exynos5410 PMU
      ARM: dts: exynos: Use lower case hex addresses in node unit addresses

Marek Szyprowski (5):
      ARM: dts: exynos: Add Exynos4412 ISP clock controller
      ARM: dts: exynos: Add audio power domain support to Exynos542x SoCs
      ARM: dts: exynos: Fix power domain node names for Exynos5250
      ARM: dts: exynos: Add audio power domain to Exynos5250
      ARM: dts: exynos: Add G3D power domain to Exynos5250

Marian Mihailescu (1):
      ARM: dts: exynos: Add CPU perf counters to Exynos54xx boards

Simon Shields (2):
      ARM: dts: exynos: Correct Trats2 panel reset line
      ARM: dts: exynos: Add bcm4334 device node to Trats2

Sylwester Nawrocki (2):
      ARM: dts: exynos: Switch to dedicated Odroid XU3 sound card binding
      ARM: dts: exynos: Add sound support for Odroid XU4

Tobias Jakobi (1):
      ARM: dts: exynos: Move G2D node to exynos5.dtsi

?ukasz Stelmach (3):
      ARM: dts: exynos: Remove duplicate definitions of SSS nodes for Exynos5
      ARM: dts: exynos: Add DT nodes for PRNG in Exynos5 SoCs
      ARM: dts: exynos: Add nodes for True Random Number Generator

 arch/arm/boot/dts/exynos3250.dtsi                 |  34 +++---
 arch/arm/boot/dts/exynos4.dtsi                    |  57 +++++-----
 arch/arm/boot/dts/exynos4210.dtsi                 |   8 +-
 arch/arm/boot/dts/exynos4412-pinctrl.dtsi         |   2 +-
 arch/arm/boot/dts/exynos4412-trats2.dts           |  29 ++++-
 arch/arm/boot/dts/exynos4412.dtsi                 |  93 +++++++++-------
 arch/arm/boot/dts/exynos5.dtsi                    |  45 ++++++--
 arch/arm/boot/dts/exynos5250.dtsi                 | 126 +++++++++++++---------
 arch/arm/boot/dts/exynos5260.dtsi                 |  26 ++---
 arch/arm/boot/dts/exynos5410.dtsi                 |  18 ++++
 arch/arm/boot/dts/exynos5420-cpus.dtsi            |  10 ++
 arch/arm/boot/dts/exynos5420.dtsi                 |  71 ++++++++----
 arch/arm/boot/dts/exynos5422-cpus.dtsi            |  10 ++
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi     |   6 +-
 arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi |  60 +++++++----
 arch/arm/boot/dts/exynos5422-odroidxu4.dts        |  52 +++++++++
 arch/arm/boot/dts/exynos5440.dtsi                 |  14 +--
 arch/arm/boot/dts/exynos54xx.dtsi                 |  26 +++--
 18 files changed, 464 insertions(+), 223 deletions(-)

^ permalink raw reply

* [GIT PULL 3/3] ARM: defconfig: exynos: config for v4.16
From: Krzysztof Kozlowski @ 2017-12-20 17:36 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171220173643.5840-1-krzk@kernel.org>


The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:

  Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)

are available in the git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-defconfig-4.16

for you to fetch changes up to 6b732dfb698991b5f518be1ddf329c1c2eb3d7cb:

  ARM: exynos_defconfig: Enable CONFIG_EXYNOS_IOMMU (2017-12-14 18:57:38 +0100)

----------------------------------------------------------------
Samsung defconfig changes for v4.16

1. Enable missing drivers for supported Exynos boards (PMU, CEC, MHL
   bridge, ASoC for Odroid XU3/XU4).
2. Enable Exynos IOMMU driver on exynos_defconfig.

----------------------------------------------------------------
Marek Szyprowski (2):
      ARM: exynos_defconfig: Enable missing drivers for supported Exynos boards
      ARM: multi_v7_defconfig: Enable missing drivers for supported Exynos boards

Shuah Khan (1):
      ARM: exynos_defconfig: Enable CONFIG_EXYNOS_IOMMU

 arch/arm/configs/exynos_defconfig   | 7 +++++++
 arch/arm/configs/multi_v7_defconfig | 5 +++++
 2 files changed, 12 insertions(+)

^ permalink raw reply

* [GIT PULL 0/3] ARM: exynos: Pull for v4.16
From: Krzysztof Kozlowski @ 2017-12-20 17:36 UTC (permalink / raw)
  To: linux-arm-kernel

Hi,

Nothing special, no specific order of pulls, no dependencies.

Best regards,
Krzysztof

^ permalink raw reply

* [PATCH net 0/3] Few mvneta fixes
From: David Miller @ 2017-12-20 17:26 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171219165947.28516-1-gregory.clement@free-electrons.com>

From: Gregory CLEMENT <gregory.clement@free-electrons.com>
Date: Tue, 19 Dec 2017 17:59:44 +0100

> here it is a small series of fixes found on the mvneta driver. They
> had been already used in the vendor kernel and are now ported to
> mainline.

Series applied, thanks Gregory.

^ permalink raw reply

* [PATCH 1/3] dt-bindings: ARM: Mediatek: Fix ethsys documentation
From: Matthias Brugger @ 2017-12-20 17:13 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <20171219013222.GZ7997@codeaurora.org>



On 12/19/2017 02:32 AM, Stephen Boyd wrote:
> On 12/14, Matthias Brugger wrote:
>> Hi Stephen, Michael,
>>
>> On 12/01/2017 01:07 PM, Matthias Brugger wrote:
>>> The ethsys registers a reset controller, so we need to specify a
>>> reset cell. This patch fixes the documentation.
>>>
>>> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
>>> ---
>>>  Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
>>>  1 file changed, 1 insertion(+)
>>>
>>> diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
>>> index 7aa3fa167668..6cc7840ff37a 100644
>>> --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
>>> +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
>>> @@ -20,4 +20,5 @@ ethsys: clock-controller at 1b000000 {
>>>  	compatible = "mediatek,mt2701-ethsys", "syscon";
>>>  	reg = <0 0x1b000000 0 0x1000>;
>>>  	#clock-cells = <1>;
>>> +	#reset-cells = <1>;
>>>  };
>>>
>>
>> Will you take this patch through the clk tree, or shall I take it through my SoC
>> tree?
>>
> 
> It's resets, we are clk maintainers. I'm clkfused.
> 
> You can take it, along with my
> 
> Acked-by: Stephen Boyd <sboyd@codeaurora.org>
> 
> if you like/expect conflicts.
> 

These are resets in the clock IP-block. I'll take it through my branch, I don't
expect any conflicts.

Regards,
Matthias

^ permalink raw reply

* PROBLEM: Hard lockup on Armada-385 with mvebu-mbus driver
From: Gregory CLEMENT @ 2017-12-20 17:12 UTC (permalink / raw)
  To: linux-arm-kernel
In-Reply-To: <e120203dd2d847e0844133f8fa460fa5@svr-chch-ex1.atlnz.lc>

Hi Joshua,
 
 On mar., d?c. 19 2017, Joshua Scott <Joshua.Scott@alliedtelesis.co.nz> wrote:

> Hard lockup on Armada-385 with mvebu-mbus driver.
>
>
> Hi,
>
>
> We've come across an issue where we get a hard lockup (no more console output, JTAG debugger unable to connect) after receiving CPU traffic from a Marvell switch-chip (connected via PCI). The issue usually occurs within a minute of beginning the traffic stream. The issue only occurs when both cores of the processor are enabled, switching to single-core, the issue is unreproducible.
>
>
> Comparing the kernel we are using (4.4.6) to the one supplied by Marvell (where the issue does not occur), we were able to narrow the minimal change to fix the issue to the following:
>
>
> diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
> index c43c3d2baf..9e6b94cdef 100644
> --- a/drivers/bus/mvebu-mbus.c
> +++ b/drivers/bus/mvebu-mbus.c
> @@ -349,8 +349,6 @@ static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
>                 (attr << WIN_CTRL_ATTR_SHIFT)    |
>                 (target << WIN_CTRL_TGT_SHIFT)   |
>                 WIN_CTRL_ENABLE;
> -       if (mbus->hw_io_coherency)
> -               ctrl |= WIN_CTRL_SYNCBARRIER;
>

Without this then you have no more assurance that the dma transfer will
be coherent. I might be wrong but I am pretty sure it was the reason of
this bit. In the vendor kernel there are other changes around the MMU
configuration (that are not possible in mainline) that allow to not use
this bit. Maybe Thomas will be able to say more about it.


>         writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
>         writel(ctrl, addr + WIN_CTRL_OFF);
> @@ -1082,10 +1080,6 @@ static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
>         mbus->soc->setup_cpu_target(mbus);
>         mvebu_mbus_setup_cpu_target_nooverlap(mbus);
>  
> -       if (is_coherent)
> -               writel(UNIT_SYNC_BARRIER_ALL,
> -                      mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
> -
>         register_syscore_ops(&mvebu_mbus_syscore_ops);
>  
>         return 0;
>
>
> While we're not currently running the latest upstream kernel, it does appear that the offending lines above are still present in the latest upstream kernel. We're not yet sure exactly why this fixes the issue, but on our platform at least it does resolve the issue we were seeing.
>
>
> The main purpose of this email is to get the ball rolling on having
> this fix upstreamed, and perhaps to hear back from anyone involved
> with this code.


Recently I submitted some fixes in the dts to configure the L2 cache in
order to avoid the hard lockup. Did you try it?

cda80a82ac3e ("ARM: dts: mvebu: pl310-cache disable double-linefill")

It was merged at the end of the 4.14-rc released and is part of the 4.14
release now.

This patch is very ea sly backportable.

Gregory

>
>
>
> Cheers,
>
> Joshua Scott
>
>
>
> Environment:
>
>
> [root at awplus flash]# cat /proc/cpuinfo
> processor       : 0
> model name      : ARMv7 Processor rev 1 (v7l)
> BogoMIPS        : 50.00
> Features        : half thumb fastmult vfp edsp vfpv3 tls vfpd32
> CPU implementer : 0x41
> CPU architecture: 7
> CPU variant     : 0x4
> CPU part        : 0xc09
> CPU revision    : 1
>
> processor       : 1
> model name      : ARMv7 Processor rev 1 (v7l)
> BogoMIPS        : 50.00
> Features        : half thumb fastmult vfp edsp vfpv3 tls vfpd32
> CPU implementer : 0x41
> CPU architecture: 7
> CPU variant     : 0x4
> CPU part        : 0xc09
> CPU revision    : 1
>
> Hardware        : Marvell Armada 380/385 (Device Tree)
> Revision        : 0000
> Serial          : 0000000000000000
>
>
>
> [root at awplus flash]# cat /proc/modules
> tipc 115327 248 - Live 0x7f0c3000
> ip6_udp_tunnel 1679 1 tipc, Live 0x7f0bf000
> udp_tunnel 2053 1 tipc, Live 0x7f0bb000
> br_netfilter 12045 0 - Live 0x7f0b5000
> sha256_generic 8941 0 - Live 0x7f0af000
> jitterentropy_rng 5909 0 - Live 0x7f0aa000
> echainiv 2007 0 - Live 0x7f0a6000
> drbg 13108 0 - Live 0x7f09f000
> platform_driver 98540 1 - Live 0x7f048000 (O)
> ipifwd 239474 18 platform_driver,[permanent], Live 0x7f000000 (PO)
>
>
>
> [root at awplus flash]# cat /proc/ioports
> 00001000-000fffff : PCI I/O
>
>
>
> [root at awplus flash]# cat /proc/iomem
> 00000000-3fffffff : System RAM
>   00008000-00628aab : Kernel code
>   00666000-006b3087 : Kernel data
> a0000000-dfffffff : PCI MEM
>   a0000000-a5ffffff : PCI Bus 0000:01
>     a0000000-a3ffffff : 0000:01:00.0
>       a0000000-a3ffffff : prestera
>     a4000000-a47fffff : 0000:01:00.0
>       a4000000-a47fffff : prestera
>     a4800000-a48fffff : 0000:01:00.0
>       a4800000-a48fffff : prestera
> f1010410-f1010417 : /soc/devbus-cs1
> f1010680-f10106cf : /soc/internal-regs/spi at 10680
> f1011000-f101101f : /soc/internal-regs/i2c at 11000
> f1012000-f101201f : serial
> f1018000-f101801f : /soc/internal-regs/pinctrl at 18000
> f1018100-f101813f : /soc/internal-regs/gpio at 18100
> f1018140-f101817f : /soc/internal-regs/gpio at 18140
> f1020704-f1020707 : /soc/internal-regs/watchdog at 20300
> f1020800-f102080f : /soc/internal-regs/cpurst at 20800
> f1020a00-f1020ccf : /soc/internal-regs/interrupt-controller at 20a00
> f1021070-f10210c7 : /soc/internal-regs/interrupt-controller at 20a00
> f1022000-f1022fff : /soc/internal-regs/pmsu at 22000
> f1058000-f10584ff : /soc/internal-regs/usb at 58000
> f1080000-f1081fff : /soc/pcie-controller/pcie at 1,0
> f10d0000-f10d0053 : /soc/internal-regs/flash at d0000
> f4800000-f487ffff : f4800000.nvs
>
>
> [root at awplus flash]# lspci -vvv
> 00:01.0 Class 0604: Device 11ab:6820 (rev 04)
>         Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
>         Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
>         Latency: 0, Cache Line Size: 64 bytes
>         Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
>         I/O behind bridge: 0000f000-00000fff [empty]
>         Memory behind bridge: a0000000-a5ffffff [size=96M]
>         Prefetchable memory behind bridge: 00000000-000fffff [size=1M]
>         Secondary status: 66MHz- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- <SERR- <PERR-
>         BridgeCtl: Parity- SERR- NoISA- VGA- MAbort- >Reset- FastB2B-
>                 PriDiscTmr- SecDiscTmr- DiscTmrStat- DiscTmrSERREn-
>         Capabilities: [40] Express (v2) Root Port (Slot+), MSI 00
>                 DevCap: MaxPayload 128 bytes, PhantFunc 0
>                         ExtTag- RBE+
>                 DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>                         RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
>                         MaxPayload 128 bytes, MaxReadReq 512 bytes
>                 DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
>                 LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 unlimited
>                         ClockPM- Surprise- LLActRep- BwNot- ASPMOptComp-
>                 LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk+
>                         ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
>                 LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
>                 SltCap: AttnBtn- PwrCtrl- MRL- AttnInd- PwrInd- HotPlug- Surprise-
>                         Slot #0, PowerLimit 0.000W; Interlock- NoCompl-
>                 SltCtl: Enable: AttnBtn- PwrFlt- MRL- PresDet- CmdCplt- HPIrq- LinkChg-
>                         Control: AttnInd Unknown, PwrInd Unknown, Power- Interlock-
>                 SltSta: Status: AttnBtn- PowerFlt- MRL- CmdCplt- PresDet+ Interlock-
>                         Changed: MRL- PresDet- LinkState-
>                 RootCtl: ErrCorrectable- ErrNon-Fatal- ErrFatal- PMEIntEna- CRSVisible-
>                 RootCap: CRSVisible-
>                 RootSta: PME ReqID 0000, PMEStatus- PMEPending-
>                 DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported ARIFwd-
>                 AtomicOpsCap: Routing- 32bit- 64bit- 128bitCAS-
>                 DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled ARIFwd-
>                 AtomicOpsCtl: ReqEn- EgressBlck-
>                 LnkCtl2: Target Link Speed: 2.5GT/s, EnterCompliance- SpeedDis-
>                          Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
>                          Compliance De-emphasis: -6dB
>                 LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
>                          EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
>
> 01:00.0 Class 0200: Device 11ab:c804
>         Subsystem: Device 11ab:11ab
>         Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr+ Stepping- SERR+ FastB2B- DisINTx-
>         Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
>         Latency: 0, Cache Line Size: 64 bytes
>         Interrupt: pin A routed to IRQ 101
>         Region 0: Memory at a4800000 (64-bit, prefetchable) [size=1M]
>         Region 2: Memory at a0000000 (64-bit, prefetchable) [size=64M]
>         Region 4: Memory at a4000000 (64-bit, prefetchable) [size=8M]
>         Capabilities: [40] Power Management version 3
>                 Flags: PMEClk- DSI- D1+ D2+ AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot-,D3cold-)
>                 Status: D0 NoSoftRst- PME-Enable- DSel=0 DScale=0 PME-
>         Capabilities: [50] MSI: Enable- Count=1/1 Maskable- 64bit+
>                 Address: 0000000000000000  Data: 0000
>         Capabilities: [60] Express (v2) Legacy Endpoint, MSI 00
>                 DevCap: MaxPayload 128 bytes, PhantFunc 0, Latency L0s <256ns, L1 <1us
>                         ExtTag- AttnBtn- AttnInd- PwrInd- RBE+ FLReset-
>                 DevCtl: Report errors: Correctable- Non-Fatal- Fatal- Unsupported-
>                         RlxdOrd- ExtTag- PhantFunc- AuxPwr- NoSnoop-
>                         MaxPayload 128 bytes, MaxReadReq 512 bytes
>                 DevSta: CorrErr- UncorrErr- FatalErr- UnsuppReq- AuxPwr- TransPend-
>                 LnkCap: Port #0, Speed 5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s <256ns, L1 unlimited
>                         ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp-
>                 LnkCtl: ASPM Disabled; RCB 64 bytes Disabled- CommClk-
>                         ExtSynch- ClockPM- AutWidDis- BWInt- AutBWInt-
>                 LnkSta: Speed 5GT/s, Width x1, TrErr- Train- SlotClk+ DLActive- BWMgmt- ABWMgmt-
>                 DevCap2: Completion Timeout: Not Supported, TimeoutDis-, LTR-, OBFF Not Supported
>                 AtomicOpsCap: 32bit- 64bit- 128bitCAS-
>                 DevCtl2: Completion Timeout: 50us to 50ms, TimeoutDis-, LTR-, OBFF Disabled
>                 AtomicOpsCtl: ReqEn-
>                 LnkCtl2: Target Link Speed: 5GT/s, EnterCompliance- SpeedDis-
>                          Transmit Margin: Normal Operating Range, EnterModifiedCompliance- ComplianceSOS-
>                          Compliance De-emphasis: -6dB
>                 LnkSta2: Current De-emphasis Level: -6dB, EqualizationComplete-, EqualizationPhase1-
>                          EqualizationPhase2-, EqualizationPhase3-, LinkEqualizationRequest-
>         Capabilities: [100 v1] Advanced Error Reporting
>                 UESta:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
>                 UEMsk:  DLP- SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF- MalfTLP- ECRC- UnsupReq- ACSViol-
>                 UESvrt: DLP+ SDES- TLP- FCP- CmpltTO- CmpltAbrt- UnxCmplt- RxOF+ MalfTLP+ ECRC- UnsupReq- ACSViol-
>                 CESta:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr-
>                 CEMsk:  RxErr- BadTLP- BadDLLP- Rollover- Timeout- NonFatalErr+
>                 AERCap: First Error Pointer: 00, GenCap- CGenEn- ChkCap- ChkEn-
>         Kernel driver in use: ATL Marvell CPSS PCI
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

^ permalink raw reply


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