* [PATCH v4 2/2] ARM: dts: TS-7970: add basic device tree
From: Shawn Guo @ 2017-12-21 9:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207160550.2782-2-sebastien.bourdelin@savoirfairelinux.com>
On Thu, Dec 07, 2017 at 11:05:50AM -0500, Sebastien Bourdelin wrote:
> These device trees add support for TS-7970 by Technologic Systems.
>
> More details here:
> https://wiki.embeddedarm.com/wiki/TS-7970
>
> Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
Applied both, thanks.
^ permalink raw reply
* [PATCH v9 1/2] of: documentation: add bindings documentation for TS-4600
From: Shawn Guo @ 2017-12-21 9:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171207171118.5448-1-sebastien.bourdelin@savoirfairelinux.com>
On Thu, Dec 07, 2017 at 12:11:17PM -0500, Sebastien Bourdelin wrote:
> This adds the documentation for the TS-4600 by Technologic Systems.
>
> Signed-off-by: Sebastien Bourdelin <sebastien.bourdelin@savoirfairelinux.com>
> Acked-by: Rob Herring <robh@kernel.org>
Applied both, thanks.
^ permalink raw reply
* [PATCH 4/4] ARM: dts: vf610-zii-dev-rev-b: add interrupts for 88e1545 PHY
From: Andrew Lunn @ 2017-12-21 9:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1eRnWr-0006VS-1m@rmk-PC.armlinux.org.uk>
On Wed, Dec 20, 2017 at 11:12:01PM +0000, Russell King wrote:
> The 88e1545 PHY has its interrupts wired to the VF610, so we might as
> well use them.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> ---
> This is certainly not correct, as all PHYs on this device share the
> same interrupt line, but we can't specify the pinmux settings
> individually on each PHY. How should this be handled?
Hi Russell
You could put it as a hog on the gpio controller node. However, i
don't think that is much better.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Andrew
^ permalink raw reply
* [PATCH 04/12] mmc: sdhci-omap: Add tuning support
From: Adrian Hunter @ 2017-12-21 9:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-5-kishon@ti.com>
On 14/12/17 15:09, Kishon Vijay Abraham I wrote:
> MMC tuning procedure is required to support SD card
> UHS1-SDR104 mode and EMMC HS200 mode.
>
> SDR104/HS200 DLL Tuning Procedure for AM572x platform is mentioned
> in Figure 25-51. SDR104/HS200 DLL Tuning Procedure of
> AM572x Sitara Processors Silicon Revision 2.0, 1.1 TRM
> (SPRUHZ6I - October 2014?Revised April 2017 [1]).
>
> The tuning function sdhci_omap_execute_tuning() will only be
> called by the MMC/SD core if the corresponding speed modes
> are supported by the OMAP silicon which is set in the mmc
> host "caps" field.
>
> [1] -> http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Apart from 1 minor comment below:
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-omap.c | 130 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 130 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
> index 8f7239e2edc2..df8a0a472996 100644
> --- a/drivers/mmc/host/sdhci-omap.c
> +++ b/drivers/mmc/host/sdhci-omap.c
> @@ -37,6 +37,13 @@
> #define CON_INIT BIT(1)
> #define CON_OD BIT(0)
>
> +#define SDHCI_OMAP_DLL 0x0134
> +#define DLL_SWT BIT(20)
> +#define DLL_FORCE_SR_C_SHIFT 13
> +#define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
> +#define DLL_FORCE_VALUE BIT(12)
> +#define DLL_CALIB BIT(1)
> +
> #define SDHCI_OMAP_CMD 0x20c
>
> #define SDHCI_OMAP_PSTATE 0x0224
> @@ -66,12 +73,16 @@
>
> #define SDHCI_OMAP_AC12 0x23c
> #define AC12_V1V8_SIGEN BIT(19)
> +#define AC12_SCLK_SEL BIT(23)
>
> #define SDHCI_OMAP_CAPA 0x240
> #define CAPA_VS33 BIT(24)
> #define CAPA_VS30 BIT(25)
> #define CAPA_VS18 BIT(26)
>
> +#define SDHCI_OMAP_CAPA2 0x0244
> +#define CAPA2_TSDR50 BIT(13)
> +
> #define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
>
> #define SYSCTL_CLKD_MAX 0x3FF
> @@ -80,6 +91,8 @@
> #define IOV_3V0 3000000 /* 300000 uV */
> #define IOV_3V3 3300000 /* 330000 uV */
>
> +#define MAX_PHASE_DELAY 0x7C
> +
> struct sdhci_omap_data {
> u32 offset;
> };
> @@ -204,6 +217,120 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
> }
> }
>
> +static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
> + int count)
> +{
> + int i;
> + u32 reg;
> +
> + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
> + reg |= DLL_FORCE_VALUE;
> + reg &= ~DLL_FORCE_SR_C_MASK;
> + reg |= (count << DLL_FORCE_SR_C_SHIFT);
> + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
> +
> + reg |= DLL_CALIB;
> + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
> + for (i = 0; i < 1000; i++) {
> + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
> + if (reg & DLL_CALIB)
> + break;
> + }
> + reg &= ~DLL_CALIB;
> + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
> +}
> +
> +static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
> +{
> + u32 reg;
> +
> + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
> + reg &= ~AC12_SCLK_SEL;
> + sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
> +
> + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
> + reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
> + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
> +}
> +
> +static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
> +{
> + u32 reg;
> + int ret = 0;
> + u8 cur_match, prev_match = 0;
> + u32 phase_delay = 0;
> + u32 start_window = 0, max_window = 0;
> + u32 length = 0, max_len = 0;
> + struct mmc_ios *ios = &mmc->ios;
> + struct sdhci_host *host = mmc_priv(mmc);
> + struct sdhci_pltfm_host *pltfm_host;
> + struct sdhci_omap_host *omap_host;
> + struct device *dev;
> +
> + pltfm_host = sdhci_priv(host);
> + omap_host = sdhci_pltfm_priv(pltfm_host);
> + dev = omap_host->dev;
These initializations can be combined with the declarations. Also try to
arrange local variable declaration lines in descending order of length e.g.
struct sdhci_host *host = mmc_priv(mmc);
struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
struct device *dev = omap_host->dev;
struct mmc_ios *ios = &mmc->ios;
u32 start_window = 0, max_window = 0;
u8 cur_match, prev_match = 0;
u32 length = 0, max_len = 0;
u32 phase_delay = 0;
int ret = 0;
u32 reg;
> +
> + /* clock tuning is not needed for upto 52MHz */
> + if (ios->clock <= 52000000)
> + return 0;
> +
> + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
> + if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
> + return 0;
> +
> + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
> + reg |= DLL_SWT;
> + sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
> +
> + while (phase_delay <= MAX_PHASE_DELAY) {
> + sdhci_omap_set_dll(omap_host, phase_delay);
> +
> + cur_match = !mmc_send_tuning(mmc, opcode, NULL);
> + if (cur_match) {
> + if (prev_match) {
> + length++;
> + } else {
> + start_window = phase_delay;
> + length = 1;
> + }
> + }
> +
> + if (length > max_len) {
> + max_window = start_window;
> + max_len = length;
> + }
> +
> + prev_match = cur_match;
> + phase_delay += 4;
> + }
> +
> + if (!max_len) {
> + dev_err(dev, "Unable to find match\n");
> + ret = -EIO;
> + goto tuning_error;
> + }
> +
> + reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
> + if (!(reg & AC12_SCLK_SEL)) {
> + ret = -EIO;
> + goto tuning_error;
> + }
> +
> + phase_delay = max_window + 4 * (max_len >> 1);
> + sdhci_omap_set_dll(omap_host, phase_delay);
> +
> + goto ret;
> +
> +tuning_error:
> + dev_err(dev, "Tuning failed\n");
> + sdhci_omap_disable_tuning(omap_host);
> +
> +ret:
> + sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
> + return ret;
> +}
> +
> static int sdhci_omap_card_busy(struct mmc_host *mmc)
> {
> int i;
> @@ -312,6 +439,8 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
> static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
> u8 power_mode)
> {
> + if (omap_host->bus_mode == MMC_POWER_OFF)
> + sdhci_omap_disable_tuning(omap_host);
> omap_host->power_mode = power_mode;
> }
>
> @@ -648,6 +777,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
> sdhci_omap_start_signal_voltage_switch;
> host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
> host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
> + host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
>
> sdhci_read_caps(host);
> host->caps |= SDHCI_CAN_DO_ADMA2;
>
^ permalink raw reply
* [PATCH 05/12] mmc: sdhci-omap: Workaround for Errata i802
From: Adrian Hunter @ 2017-12-21 9:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-6-kishon@ti.com>
On 14/12/17 15:09, Kishon Vijay Abraham I wrote:
> Errata i802 in AM572x Sitara Processors Silicon Revision 2.0, 1.1
> (SPRZ429K July 2014?Revised March 2017 [1]) mentions
> DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
> during the tuning procedure and it has to be disabled during the
> tuning procedure Implement workaround for Errata i802 here..
>
> [1] -> http://www.ti.com/lit/er/sprz429k/sprz429k.pdf
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-omap.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
> index df8a0a472996..b20f4c79ccc6 100644
> --- a/drivers/mmc/host/sdhci-omap.c
> +++ b/drivers/mmc/host/sdhci-omap.c
> @@ -266,6 +266,7 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_omap_host *omap_host;
> struct device *dev;
> + u32 ier = host->ier;
>
> pltfm_host = sdhci_priv(host);
> omap_host = sdhci_pltfm_priv(pltfm_host);
> @@ -283,6 +284,16 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
> reg |= DLL_SWT;
> sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
>
> + /*
> + * OMAP5/DRA74X/DRA72x Errata i802:
> + * DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur
> + * during the tuning procedure. So disable it during the
> + * tuning procedure.
> + */
> + ier &= ~SDHCI_INT_DATA_CRC;
> + sdhci_writel(host, ier, SDHCI_INT_ENABLE);
> + sdhci_writel(host, ier, SDHCI_SIGNAL_ENABLE);
> +
> while (phase_delay <= MAX_PHASE_DELAY) {
> sdhci_omap_set_dll(omap_host, phase_delay);
>
> @@ -328,6 +339,8 @@ static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
>
> ret:
> sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
> + sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);
> + sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);
> return ret;
> }
>
>
^ permalink raw reply
* [PATCH 07/12] mmc: sdhci_omap: Fix sdhci-omap quirks
From: Adrian Hunter @ 2017-12-21 9:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-8-kishon@ti.com>
On 14/12/17 15:09, Kishon Vijay Abraham I wrote:
> Remove SDHCI_QUIRK_BROKEN_CARD_DETECTION quirk as gpio card detection
> is supported in sdhci-omap.
SDHCI_QUIRK_BROKEN_CARD_DETECTION is for native card detection not gpio card
detection.
>
> Add SDHCI_QUIRK2_PRESET_VALUE_BROKEN quirk as setting preset values loads
> incorrect CLKD values (for UHS modes).
>
> Remove SDHCI_QUIRK2_NO_1_8_V quirk as sdhci-omap now supports UHS modes.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/mmc/host/sdhci-omap.c | 7 +++----
> 1 file changed, 3 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
> index 594e41200d8a..6dee275b2e57 100644
> --- a/drivers/mmc/host/sdhci-omap.c
> +++ b/drivers/mmc/host/sdhci-omap.c
> @@ -755,13 +755,12 @@ static int sdhci_omap_set_capabilities(struct sdhci_omap_host *omap_host)
> }
>
> static const struct sdhci_pltfm_data sdhci_omap_pdata = {
> - .quirks = SDHCI_QUIRK_BROKEN_CARD_DETECTION |
> - SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> + .quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
> SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN |
> SDHCI_QUIRK_NO_HISPD_BIT |
> SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC,
> - .quirks2 = SDHCI_QUIRK2_NO_1_8_V |
> - SDHCI_QUIRK2_ACMD23_BROKEN |
> + .quirks2 = SDHCI_QUIRK2_ACMD23_BROKEN |
> + SDHCI_QUIRK2_PRESET_VALUE_BROKEN |
> SDHCI_QUIRK2_RSP_136_HAS_CRC,
> .ops = &sdhci_omap_ops,
> };
>
^ permalink raw reply
* [PATCH 08/12] mmc: sdhci-omap: Add support to override f_max and iodelay from pdata
From: Adrian Hunter @ 2017-12-21 9:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-9-kishon@ti.com>
On 14/12/17 15:09, Kishon Vijay Abraham I wrote:
> DRA74x EVM Rev H EVM comes with revision 2.0 silicon. However, earlier
> versions of EVM can come with either revision 1.1 or revision 1.0 of
> silicon.
>
> The device-tree file is written to support rev 2.0 of silicon.
> pdata-quirks are used to then override the settings needed for
> PG 1.1 silicon.
>
> PG 1.1 silicon has limitations w.r.t frequencies at which MMC1/2/3
> can operate as well as different IOdelay numbers.
>
> Add support in sdhci-omap driver to get platform data if available
> (added using pdata quirks) and override the data (max-frequency and
> iodelay data) obtained from device tree.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> drivers/mmc/host/sdhci-omap.c | 17 ++++++++++++++++
> include/linux/platform_data/sdhci-omap.h | 35 ++++++++++++++++++++++++++++++++
> 2 files changed, 52 insertions(+)
> create mode 100644 include/linux/platform_data/sdhci-omap.h
>
> diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
> index 6dee275b2e57..cddc3ad1331f 100644
> --- a/drivers/mmc/host/sdhci-omap.c
> +++ b/drivers/mmc/host/sdhci-omap.c
> @@ -22,6 +22,7 @@
> #include <linux/module.h>
> #include <linux/of.h>
> #include <linux/of_device.h>
> +#include <linux/platform_data/sdhci-omap.h>
> #include <linux/platform_device.h>
> #include <linux/pm_runtime.h>
> #include <linux/regulator/consumer.h>
> @@ -102,6 +103,7 @@ struct sdhci_omap_data {
> };
>
> struct sdhci_omap_host {
> + char *version;
> void __iomem *base;
> struct device *dev;
> struct regulator *pbias;
> @@ -781,11 +783,18 @@ static struct pinctrl_state
> u32 *caps, u32 capmask)
> {
> struct device *dev = omap_host->dev;
> + char *version = omap_host->version;
> struct pinctrl_state *pinctrl_state = ERR_PTR(-ENODEV);
> + char str[20];
>
> if (!(*caps & capmask))
> goto ret;
>
> + if (version) {
> + sprintf(str, "%s-%s", mode, version);
snprintf please
> + pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, str);
Doesn't look like this 'pinctrl_state' is used?
> + }
> +
> pinctrl_state = pinctrl_lookup_state(omap_host->pinctrl, mode);
> if (IS_ERR(pinctrl_state)) {
> dev_err(dev, "no pinctrl state for %s mode", mode);
> @@ -879,6 +888,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
> struct mmc_host *mmc;
> const struct of_device_id *match;
> struct sdhci_omap_data *data;
> + struct sdhci_omap_platform_data *platform_data;
>
> match = of_match_device(omap_sdhci_match, dev);
> if (!match)
> @@ -913,6 +923,13 @@ static int sdhci_omap_probe(struct platform_device *pdev)
> if (ret)
> goto err_pltfm_free;
>
> + platform_data = dev_get_platdata(dev);
> + if (platform_data) {
> + omap_host->version = platform_data->version;
> + if (platform_data->max_freq)
> + mmc->f_max = platform_data->max_freq;
> + }
> +
> pltfm_host->clk = devm_clk_get(dev, "fck");
> if (IS_ERR(pltfm_host->clk)) {
> ret = PTR_ERR(pltfm_host->clk);
> diff --git a/include/linux/platform_data/sdhci-omap.h b/include/linux/platform_data/sdhci-omap.h
> new file mode 100644
> index 000000000000..a46e1240956a
> --- /dev/null
> +++ b/include/linux/platform_data/sdhci-omap.h
> @@ -0,0 +1,35 @@
> +/**
> + * SDHCI Controller Platform Data for TI's OMAP SoCs
> + *
> + * Copyright (C) 2017 Texas Instruments
> + * Author: Kishon Vijay Abraham I <kishon@ti.com>
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 of
> + * the License as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef __SDHCI_OMAP_PDATA_H__
> +#define __SDHCI_OMAP_PDATA_H__
> +
> +struct sdhci_omap_platform_data {
> + const char *name;
> +
> + /*
> + * set if your board has components or wiring that limits the
> + * maximum frequency on the MMC bus
> + */
> + unsigned int max_freq;
> +
> + /* string specifying a particular variant of hardware */
> + char *version;
> +};
> +
> +#endif
>
^ permalink raw reply
* [PATCH 11/12] mmc: sdhci-omap: Add support for MMC/SD controller in k2g SoC
From: Adrian Hunter @ 2017-12-21 9:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171214130941.26666-12-kishon@ti.com>
On 14/12/17 15:09, Kishon Vijay Abraham I wrote:
> Add support for the new compatible added specifically to support
> k2g's MMC/SD controller.
>
> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/sdhci-omap.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/mmc/host/sdhci-omap.c b/drivers/mmc/host/sdhci-omap.c
> index cddc3ad1331f..5e81e29383d9 100644
> --- a/drivers/mmc/host/sdhci-omap.c
> +++ b/drivers/mmc/host/sdhci-omap.c
> @@ -767,6 +767,10 @@ static const struct sdhci_pltfm_data sdhci_omap_pdata = {
> .ops = &sdhci_omap_ops,
> };
>
> +static const struct sdhci_omap_data k2g_data = {
> + .offset = 0x200,
> +};
> +
> static const struct sdhci_omap_data dra7_data = {
> .offset = 0x200,
> .flags = SDHCI_OMAP_REQUIRE_IODELAY,
> @@ -774,6 +778,7 @@ static const struct sdhci_omap_data dra7_data = {
>
> static const struct of_device_id omap_sdhci_match[] = {
> { .compatible = "ti,dra7-sdhci", .data = &dra7_data },
> + { .compatible = "ti,k2g-sdhci", .data = &k2g_data },
> {},
> };
> MODULE_DEVICE_TABLE(of, omap_sdhci_match);
> @@ -882,6 +887,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
> int ret;
> u32 offset;
> struct device *dev = &pdev->dev;
> + struct device_node *node = dev->of_node;
> struct sdhci_host *host;
> struct sdhci_pltfm_host *pltfm_host;
> struct sdhci_omap_host *omap_host;
> @@ -908,6 +914,9 @@ static int sdhci_omap_probe(struct platform_device *pdev)
> return PTR_ERR(host);
> }
>
> + if (of_device_is_compatible(node, "ti,k2g-sdhci"))
> + host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V;
> +
> pltfm_host = sdhci_priv(host);
> omap_host = sdhci_pltfm_priv(pltfm_host);
> omap_host->host = host;
>
^ permalink raw reply
* [PATCH] KVM: arm/arm64: don't set vtimer->cnt_ctl in kvm_arch_timer_handler
From: Jia He @ 2017-12-21 9:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171215100451.GY910@cbox>
Hi Christoffer
Sorry for the late, I ever thought you would send out v2 with isb(). It
seems not.
On 12/15/2017 6:04 PM, Christoffer Dall Wrote:
> On Fri, Dec 15, 2017 at 10:27:02AM +0800, Jia He wrote:
>
> [...]
[...]
>
> Meanwhile, I think I thought of a cleaner way to do this. Could you
> test the following two patches on your platform as well?
>
> >From 3a594a3aa222bd64a86f6c6afcb209c9be20d5c5 Mon Sep 17 00:00:00 2001
> From: Christoffer Dall <christoffer.dall@linaro.org>
> Date: Thu, 14 Dec 2017 19:54:50 +0100
> Subject: [PATCH 1/2] KVM: arm/arm64: Properly handle arch-timer IRQs after
> vtimer_save_state
>
> The recent timer rework was assuming that once the timer was disabled,
> we should no longer see any interrupts from the timer. This assumption
> turns out to not be true, and instead we have to handle the case when
> the timer ISR runs even after the timer has been disabled.
>
> This requires a couple of changes:
>
> First, we should never overwrite the cached guest state of the timer
> control register when the ISR runs, because KVM may have disabled its
> timers when doing vcpu_put(), even though the guest still had the timer
> enabled.
>
> Second, we shouldn't assume that the timer is actually firing just
> because we see an ISR, but we should check the ISTATUS field of the
> timer control register to understand if the hardware timer is really
> firing or not.
>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Jia He <jia.he@hxt-semitech.com>
> ---
> virt/kvm/arm/arch_timer.c | 19 ++++++++++++-------
> 1 file changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index aa9adfafe12b..792bcf6277b6 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -92,16 +92,21 @@ static irqreturn_t kvm_arch_timer_handler(int irq, void *dev_id)
> {
> struct kvm_vcpu *vcpu = *(struct kvm_vcpu **)dev_id;
> struct arch_timer_context *vtimer;
> + u32 cnt_ctl;
>
> - if (!vcpu) {
> - pr_warn_once("Spurious arch timer IRQ on non-VCPU thread\n");
> - return IRQ_NONE;
> - }
> - vtimer = vcpu_vtimer(vcpu);
> + /*
> + * We may see a timer interrupt after vcpu_put() has been called which
> + * sets the CPU's vcpu pointer to NULL, because even though the timer
> + * has been disabled in vtimer_save_state(), the singal may not have
> + * been retired from the interrupt controller yet.
> + */
> + if (!vcpu)
> + return IRQ_HANDLED;
>
> + vtimer = vcpu_vtimer(vcpu);
> if (!vtimer->irq.level) {
> - vtimer->cnt_ctl = read_sysreg_el0(cntv_ctl);
> - if (kvm_timer_irq_can_fire(vtimer))
> + cnt_ctl = read_sysreg_el0(cntv_ctl);
> + if (cnt_ctl & ARCH_TIMER_CTRL_IT_STAT)
> kvm_timer_update_irq(vcpu, true, vtimer);
> }
>
>
>
> >From ed96302b47d209024814df116994f64dc8f07c96 Mon Sep 17 00:00:00 2001
> From: Christoffer Dall <christoffer.dall@linaro.org>
> Date: Fri, 15 Dec 2017 00:30:12 +0100
> Subject: [PATCH 2/2] KVM: arm/arm64: Fix timer enable flow
>
> When enabling the timer on the first run, we fail to ever restore the
> state and mark it as loaded. That means, that in the initial entry to
> the VCPU ioctl, unless we exit to userspace for some reason such as a
> pending signal, if the guest programs a timer and blocks, we will wait
> forever, because we never read back the hardware state (the loaded flag
> is not set), and so we think the timer is disabled, and we never
> schedule a background soft timer.
>
> The end result? The VCPU blocks forever, and the only solution is to
> kill the thread.
>
> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
> ---
> virt/kvm/arm/arch_timer.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/virt/kvm/arm/arch_timer.c b/virt/kvm/arm/arch_timer.c
> index 792bcf6277b6..8869658e6983 100644
> --- a/virt/kvm/arm/arch_timer.c
> +++ b/virt/kvm/arm/arch_timer.c
> @@ -843,10 +843,7 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
> no_vgic:
> preempt_disable();
> timer->enabled = 1;
> - if (!irqchip_in_kernel(vcpu->kvm))
> - kvm_timer_vcpu_load_user(vcpu);
> - else
> - kvm_timer_vcpu_load_vgic(vcpu);
> + kvm_timer_vcpu_load(vcpu);
> preempt_enable();
>
> return 0;
>
>
> Thanks,
> -Christoffer
>
I have tested your 2 patches in my QDF2400 server for 10 times, the
guest can be boot up without any issues.
Without this patch, the guest will always hang in booting stages.
--
Cheers,
Jia
^ permalink raw reply
* [PATCH V2 9/9] ARM: dts: stm32: add initial support of stm32mp157c eval board
From: Linus Walleij @ 2017-12-21 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <27a339f7-33a7-eb73-27fe-9927838729d6@st.com>
On Wed, Dec 20, 2017 at 10:19 AM, Alexandre Torgue
<alexandre.torgue@st.com> wrote:
> On 12/20/2017 08:44 AM, Linus Walleij wrote:
>> gpio-line-names = "foo", "bar" ...;
>>
>> See for example
>> arch/arm/boot/dts/bcm2835-rpi-a.dts
>> arch/arm/boot/dts/ste-snowball.dts
(...)
>
> It looks like useful for pins used as gpio line. Are you saying that we also
> have to describe pins used as Alternate Function ?
No. The use of the names is up to the platform maintainer (you),
leaving a blank string for non-GPIO lines is just fine.
Some platforms add the name of the actual function used by the
line on the design, if it is not GPIO, sometimes something in
brachets like "[i2c0-SDA]" that says what it is used for and explains
why you can't use it for GPIO on this setup.
But just leaving it blank is just as good.
Yours,
Linus Walleij
^ permalink raw reply
* [kernel-hardening] [PATCH] arm: kernel: implement fast refcount checking
From: Ard Biesheuvel @ 2017-12-21 9:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171221075036.GA32158@pjb1027-Latitude-E5410>
On 21 December 2017 at 07:50, Jinbum Park <jinb.park7@gmail.com> wrote:
> This adds support to arm for fast refcount checking.
> It's heavily based on x86, arm64 implementation.
> (7a46ec0e2f48 ("locking/refcounts,
> x86/asm: Implement fast refcount overflow protection)
>
> This doesn't support under-ARMv6, thumb2-kernel yet.
>
> Test result of this patch is as follows.
>
> 1. LKDTM test
>
> - All REFCOUNT_* tests in LKDTM have passed.
>
> 2. Performance test
>
> - Cortex-A7, Quad Core, 450 MHz
> - Case with CONFIG_ARCH_HAS_REFCOUNT,
>
> perf stat -B -- echo ATOMIC_TIMING \
> >/sys/kernel/debug/provoke-crash/DIRECT
> 204.364247057 seconds time elapsed
>
> perf stat -B -- echo REFCOUNT_TIMING \
> >/sys/kernel/debug/provoke-crash/DIRECT
> 208.006062212 seconds time elapsed
>
> - Case with CONFIG_REFCOUNT_FULL,
>
> perf stat -B -- echo REFCOUNT_TIMING \
> >/sys/kernel/debug/provoke-crash/DIRECT
> 369.256523453 seconds time elapsed
>
This is a nice result. However, without any insight into the presence
of actual refcount hot spots, it is not obvious that we need this
patch. This is the reason we ended up enabling CONFIG_REFCOUNT_FULL
for arm64. I will let others comment on whether we want this patch in
the first place, and I will give some feedback on the implementation
below.
> Signed-off-by: Jinbum Park <jinb.park7@gmail.com>
> ---
> arch/arm/Kconfig | 1 +
> arch/arm/include/asm/atomic.h | 82 +++++++++++++++++++++++++++++++++++++++++
> arch/arm/include/asm/refcount.h | 55 +++++++++++++++++++++++++++
> arch/arm/kernel/traps.c | 44 ++++++++++++++++++++++
> 4 files changed, 182 insertions(+)
> create mode 100644 arch/arm/include/asm/refcount.h
>
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index 3ea00d6..e07b986 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -7,6 +7,7 @@ config ARM
> select ARCH_HAS_DEBUG_VIRTUAL
> select ARCH_HAS_DEVMEM_IS_ALLOWED
> select ARCH_HAS_ELF_RANDOMIZE
> + select ARCH_HAS_REFCOUNT if __LINUX_ARM_ARCH__ >= 6 && (!THUMB2_KERNEL)
> select ARCH_HAS_SET_MEMORY
> select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
> select ARCH_HAS_STRICT_MODULE_RWX if MMU
> diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
> index 66d0e21..b203396 100644
> --- a/arch/arm/include/asm/atomic.h
> +++ b/arch/arm/include/asm/atomic.h
> @@ -17,6 +17,7 @@
> #include <linux/irqflags.h>
> #include <asm/barrier.h>
> #include <asm/cmpxchg.h>
> +#include <asm/opcodes.h>
>
> #define ATOMIC_INIT(i) { (i) }
>
> @@ -32,6 +33,87 @@
>
> #if __LINUX_ARM_ARCH__ >= 6
>
> +#ifdef CONFIG_ARCH_HAS_REFCOUNT
> +
> +#define REFCOUNT_ARM_BKPT_INSTR 0xfff001fc
> +
> +/*
> + * 1) encode call site that detect overflow in dummy b instruction.
> + * 2) overflow handler can decode dummy b, and get call site.
> + * 3) "(call site + 4) == strex" is always true.
> + * 4) the handler can get counter address via decoding strex.
> + */
> +#define REFCOUNT_TRIGGER_BKPT \
> + __inst_arm(REFCOUNT_ARM_BKPT_INSTR) \
> +" b 22b\n"
In my arm64 implementation, I used a cbz instruction so I could encode
both a register number and a relative offset easily. In your case, you
only need to encode the offset, so it is much better to use '.long 22b
- .' instead.
> +
> +/* If bkpt is triggered, skip strex routines after handling overflow */
> +#define REFCOUNT_CHECK_TAIL \
> +" strex %1, %0, [%3]\n" \
> +" teq %1, #0\n" \
> +" bne 1b\n" \
> +" .subsection 1\n" \
> +"33:\n" \
> + REFCOUNT_TRIGGER_BKPT \
> +" .previous\n"
> +
> +#define REFCOUNT_POST_CHECK_NEG \
> +"22: bmi 33f\n" \
It may be better to put the label on the 'strex' instruction directly,
to make things less confusing.
> + REFCOUNT_CHECK_TAIL
> +
> +#define REFCOUNT_POST_CHECK_NEG_OR_ZERO \
> +" beq 33f\n" \
> + REFCOUNT_POST_CHECK_NEG
> +
> +#define REFCOUNT_SMP_MB smp_mb()
> +#define REFCOUNT_SMP_NONE_MB
> +
> +#define REFCOUNT_OP(op, c_op, asm_op, post, mb) \
> +static inline int __refcount_##op(int i, atomic_t *v) \
> +{ \
> + unsigned long tmp; \
> + int result; \
> +\
> + REFCOUNT_SMP_ ## mb; \
> + prefetchw(&v->counter); \
> + __asm__ __volatile__("@ __refcount_" #op "\n" \
> +"1: ldrex %0, [%3]\n" \
> +" " #asm_op " %0, %0, %4\n" \
> + REFCOUNT_POST_CHECK_ ## post \
> + : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
> + : "r" (&v->counter), "Ir" (i) \
> + : "cc"); \
> +\
> + REFCOUNT_SMP_ ## mb; \
> + return result; \
> +} \
> +
> +REFCOUNT_OP(add_lt, +=, adds, NEG_OR_ZERO, NONE_MB);
> +REFCOUNT_OP(sub_lt, -=, subs, NEG, MB);
> +REFCOUNT_OP(sub_le, -=, subs, NEG_OR_ZERO, NONE_MB);
> +
> +static inline int __refcount_add_not_zero(int i, atomic_t *v)
> +{
> + unsigned long tmp;
> + int result;
> +
> + prefetchw(&v->counter);
> + __asm__ __volatile__("@ __refcount_add_not_zero\n"
> +"1: ldrex %0, [%3]\n"
> +" teq %0, #0\n"
> +" beq 2f\n"
> +" adds %0, %0, %4\n"
> + REFCOUNT_POST_CHECK_NEG
> +"2:"
> + : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
> + : "r" (&v->counter), "Ir" (i)
> + : "cc");
> +
> + return result;
> +}
> +
> +#endif /* CONFIG_ARCH_HAS_REFCOUNT */
> +
> /*
> * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
> * store exclusive to ensure that these are atomic. We may loop
> diff --git a/arch/arm/include/asm/refcount.h b/arch/arm/include/asm/refcount.h
> new file mode 100644
> index 0000000..300a2d5
> --- /dev/null
> +++ b/arch/arm/include/asm/refcount.h
> @@ -0,0 +1,55 @@
> +/*
> + * arm-specific implementation of refcount_t. Based on x86 version and
> + * PAX_REFCOUNT from PaX/grsecurity.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#ifndef __ASM_REFCOUNT_H
> +#define __ASM_REFCOUNT_H
> +
> +#include <linux/refcount.h>
> +
> +#include <asm/atomic.h>
> +#include <asm/uaccess.h>
> +
> +static __always_inline void refcount_add(int i, refcount_t *r)
> +{
> + __refcount_add_lt(i, &r->refs);
> +}
> +
> +static __always_inline void refcount_inc(refcount_t *r)
> +{
> + __refcount_add_lt(1, &r->refs);
> +}
> +
> +static __always_inline void refcount_dec(refcount_t *r)
> +{
> + __refcount_sub_le(1, &r->refs);
> +}
> +
> +static __always_inline __must_check bool refcount_sub_and_test(unsigned int i,
> + refcount_t *r)
> +{
> + return __refcount_sub_lt(i, &r->refs) == 0;
> +}
> +
> +static __always_inline __must_check bool refcount_dec_and_test(refcount_t *r)
> +{
> + return __refcount_sub_lt(1, &r->refs) == 0;
> +}
> +
> +static __always_inline __must_check bool refcount_add_not_zero(unsigned int i,
> + refcount_t *r)
> +{
> + return __refcount_add_not_zero(i, &r->refs) != 0;
> +}
> +
> +static __always_inline __must_check bool refcount_inc_not_zero(refcount_t *r)
> +{
> + return __refcount_add_not_zero(1, &r->refs) != 0;
> +}
> +
> +#endif
> diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
> index 5cf0488..a309215 100644
> --- a/arch/arm/kernel/traps.c
> +++ b/arch/arm/kernel/traps.c
> @@ -795,8 +795,52 @@ void abort(void)
> }
> EXPORT_SYMBOL(abort);
>
> +#ifdef CONFIG_ARCH_HAS_REFCOUNT
> +
> +static int refcount_overflow_handler(struct pt_regs *regs, unsigned int instr)
> +{
> + u32 dummy_b = le32_to_cpup((__le32 *)(regs->ARM_pc + 4));
> + u32 strex;
> + u32 rt;
> + bool zero = regs->ARM_cpsr & PSR_Z_BIT;
> +
> + /* point pc to the branch instruction that detected the overflow */
> + regs->ARM_pc += 4 + (((s32)dummy_b << 8) >> 6) + 8;
> +
This would become something like
s32 offset = *(s32 *)(regs->ARM_pc + 4);
/* point pc to the strex instruction that will overflow the refcount */
regs->ARM_pc += offset + 4;
> + /* decode strex to set refcount */
> + strex = le32_to_cpup((__le32 *)(regs->ARM_pc + 4));
> + rt = (strex << 12) >> 28;
> +
Don't we have better ways to decode an instruction? Also, could you
add a Thumb2 variant here? (and for the breakpoint instruction)
> + /* unconditionally saturate the refcount */
> + *(int *)regs->uregs[rt] = INT_MIN / 2;
> +
> + /* report error */
> + refcount_error_report(regs, zero ? "hit zero" : "overflow");
> +
> + /* advance pc and proceed, skip "strex" routine */
> + regs->ARM_pc += 16;
Please use a macro here to clarify that you are skipping the remaining
instructions in REFCOUNT_CHECK_TAIL
> + return 0;
> +}
> +
> +static struct undef_hook refcount_break_hook = {
> + .instr_mask = 0xffffffff,
> + .instr_val = REFCOUNT_ARM_BKPT_INSTR,
> + .cpsr_mask = 0,
> + .cpsr_val = 0,
> + .fn = refcount_overflow_handler,
> +};
> +
> +#define register_refcount_break_hook() register_undef_hook(&refcount_break_hook)
> +
> +#else /* !CONFIG_ARCH_HAS_REFCOUNT */
> +
> +#define register_refcount_break_hook()
> +
> +#endif /* CONFIG_ARCH_HAS_REFCOUNT */
> +
> void __init trap_init(void)
> {
> + register_refcount_break_hook();
> return;
> }
>
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH 1/2] pinctrl/nomadik/abx500: Delete an error message for a failed memory allocation in abx500_gpio_probe()
From: Linus Walleij @ 2017-12-21 9:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1fa81c02-0b51-16d1-b713-971f7f44eb31@users.sourceforge.net>
On Wed, Dec 20, 2017 at 10:51 AM, SF Markus Elfring
<elfring@users.sourceforge.net> wrote:
> From: Markus Elfring <elfring@users.sourceforge.net>
> Date: Wed, 20 Dec 2017 10:12:56 +0100
>
> Omit an extra message for a memory allocation failure in this function.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [kernel-hardening] [PATCH] arm: kernel: implement fast refcount checking
From: Ard Biesheuvel @ 2017-12-21 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu_wcy=VG8CK_qScY5Pw+=1k4NTHPsbP=ALEExs4anoFTQ@mail.gmail.com>
(add Dave)
On 21 December 2017 at 09:18, Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 21 December 2017 at 07:50, Jinbum Park <jinb.park7@gmail.com> wrote:
>> This adds support to arm for fast refcount checking.
>> It's heavily based on x86, arm64 implementation.
>> (7a46ec0e2f48 ("locking/refcounts,
>> x86/asm: Implement fast refcount overflow protection)
>>
>> This doesn't support under-ARMv6, thumb2-kernel yet.
>>
>> Test result of this patch is as follows.
>>
>> 1. LKDTM test
>>
>> - All REFCOUNT_* tests in LKDTM have passed.
>>
>> 2. Performance test
>>
>> - Cortex-A7, Quad Core, 450 MHz
>> - Case with CONFIG_ARCH_HAS_REFCOUNT,
>>
>> perf stat -B -- echo ATOMIC_TIMING \
>> >/sys/kernel/debug/provoke-crash/DIRECT
>> 204.364247057 seconds time elapsed
>>
>> perf stat -B -- echo REFCOUNT_TIMING \
>> >/sys/kernel/debug/provoke-crash/DIRECT
>> 208.006062212 seconds time elapsed
>>
>> - Case with CONFIG_REFCOUNT_FULL,
>>
>> perf stat -B -- echo REFCOUNT_TIMING \
>> >/sys/kernel/debug/provoke-crash/DIRECT
>> 369.256523453 seconds time elapsed
>>
>
> This is a nice result. However, without any insight into the presence
> of actual refcount hot spots, it is not obvious that we need this
> patch. This is the reason we ended up enabling CONFIG_REFCOUNT_FULL
> for arm64. I will let others comment on whether we want this patch in
> the first place, and I will give some feedback on the implementation
> below.
>
>> Signed-off-by: Jinbum Park <jinb.park7@gmail.com>
>> ---
>> arch/arm/Kconfig | 1 +
>> arch/arm/include/asm/atomic.h | 82 +++++++++++++++++++++++++++++++++++++++++
>> arch/arm/include/asm/refcount.h | 55 +++++++++++++++++++++++++++
>> arch/arm/kernel/traps.c | 44 ++++++++++++++++++++++
>> 4 files changed, 182 insertions(+)
>> create mode 100644 arch/arm/include/asm/refcount.h
>>
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index 3ea00d6..e07b986 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -7,6 +7,7 @@ config ARM
>> select ARCH_HAS_DEBUG_VIRTUAL
>> select ARCH_HAS_DEVMEM_IS_ALLOWED
>> select ARCH_HAS_ELF_RANDOMIZE
>> + select ARCH_HAS_REFCOUNT if __LINUX_ARM_ARCH__ >= 6 && (!THUMB2_KERNEL)
>> select ARCH_HAS_SET_MEMORY
>> select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
>> select ARCH_HAS_STRICT_MODULE_RWX if MMU
>> diff --git a/arch/arm/include/asm/atomic.h b/arch/arm/include/asm/atomic.h
>> index 66d0e21..b203396 100644
>> --- a/arch/arm/include/asm/atomic.h
>> +++ b/arch/arm/include/asm/atomic.h
>> @@ -17,6 +17,7 @@
>> #include <linux/irqflags.h>
>> #include <asm/barrier.h>
>> #include <asm/cmpxchg.h>
>> +#include <asm/opcodes.h>
>>
>> #define ATOMIC_INIT(i) { (i) }
>>
>> @@ -32,6 +33,87 @@
>>
>> #if __LINUX_ARM_ARCH__ >= 6
>>
>> +#ifdef CONFIG_ARCH_HAS_REFCOUNT
>> +
>> +#define REFCOUNT_ARM_BKPT_INSTR 0xfff001fc
>> +
>> +/*
>> + * 1) encode call site that detect overflow in dummy b instruction.
>> + * 2) overflow handler can decode dummy b, and get call site.
>> + * 3) "(call site + 4) == strex" is always true.
>> + * 4) the handler can get counter address via decoding strex.
>> + */
>> +#define REFCOUNT_TRIGGER_BKPT \
>> + __inst_arm(REFCOUNT_ARM_BKPT_INSTR) \
>> +" b 22b\n"
>
> In my arm64 implementation, I used a cbz instruction so I could encode
> both a register number and a relative offset easily. In your case, you
> only need to encode the offset, so it is much better to use '.long 22b
> - .' instead.
>
>> +
>> +/* If bkpt is triggered, skip strex routines after handling overflow */
>> +#define REFCOUNT_CHECK_TAIL \
>> +" strex %1, %0, [%3]\n" \
>> +" teq %1, #0\n" \
>> +" bne 1b\n" \
>> +" .subsection 1\n" \
>> +"33:\n" \
>> + REFCOUNT_TRIGGER_BKPT \
>> +" .previous\n"
>> +
>> +#define REFCOUNT_POST_CHECK_NEG \
>> +"22: bmi 33f\n" \
>
> It may be better to put the label on the 'strex' instruction directly,
> to make things less confusing.
>
>> + REFCOUNT_CHECK_TAIL
>> +
>> +#define REFCOUNT_POST_CHECK_NEG_OR_ZERO \
>> +" beq 33f\n" \
>> + REFCOUNT_POST_CHECK_NEG
>> +
>> +#define REFCOUNT_SMP_MB smp_mb()
>> +#define REFCOUNT_SMP_NONE_MB
>> +
>> +#define REFCOUNT_OP(op, c_op, asm_op, post, mb) \
>> +static inline int __refcount_##op(int i, atomic_t *v) \
>> +{ \
>> + unsigned long tmp; \
>> + int result; \
>> +\
>> + REFCOUNT_SMP_ ## mb; \
>> + prefetchw(&v->counter); \
>> + __asm__ __volatile__("@ __refcount_" #op "\n" \
>> +"1: ldrex %0, [%3]\n" \
>> +" " #asm_op " %0, %0, %4\n" \
>> + REFCOUNT_POST_CHECK_ ## post \
>> + : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter) \
>> + : "r" (&v->counter), "Ir" (i) \
>> + : "cc"); \
>> +\
>> + REFCOUNT_SMP_ ## mb; \
>> + return result; \
>> +} \
>> +
>> +REFCOUNT_OP(add_lt, +=, adds, NEG_OR_ZERO, NONE_MB);
>> +REFCOUNT_OP(sub_lt, -=, subs, NEG, MB);
>> +REFCOUNT_OP(sub_le, -=, subs, NEG_OR_ZERO, NONE_MB);
>> +
>> +static inline int __refcount_add_not_zero(int i, atomic_t *v)
>> +{
>> + unsigned long tmp;
>> + int result;
>> +
>> + prefetchw(&v->counter);
>> + __asm__ __volatile__("@ __refcount_add_not_zero\n"
>> +"1: ldrex %0, [%3]\n"
>> +" teq %0, #0\n"
>> +" beq 2f\n"
>> +" adds %0, %0, %4\n"
>> + REFCOUNT_POST_CHECK_NEG
>> +"2:"
>> + : "=&r" (result), "=&r" (tmp), "+Qo" (v->counter)
>> + : "r" (&v->counter), "Ir" (i)
>> + : "cc");
>> +
>> + return result;
>> +}
>> +
>> +#endif /* CONFIG_ARCH_HAS_REFCOUNT */
>> +
>> /*
>> * ARMv6 UP and SMP safe atomic ops. We use load exclusive and
>> * store exclusive to ensure that these are atomic. We may loop
>> diff --git a/arch/arm/include/asm/refcount.h b/arch/arm/include/asm/refcount.h
>> new file mode 100644
>> index 0000000..300a2d5
>> --- /dev/null
>> +++ b/arch/arm/include/asm/refcount.h
>> @@ -0,0 +1,55 @@
>> +/*
>> + * arm-specific implementation of refcount_t. Based on x86 version and
>> + * PAX_REFCOUNT from PaX/grsecurity.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#ifndef __ASM_REFCOUNT_H
>> +#define __ASM_REFCOUNT_H
>> +
>> +#include <linux/refcount.h>
>> +
>> +#include <asm/atomic.h>
>> +#include <asm/uaccess.h>
>> +
>> +static __always_inline void refcount_add(int i, refcount_t *r)
>> +{
>> + __refcount_add_lt(i, &r->refs);
>> +}
>> +
>> +static __always_inline void refcount_inc(refcount_t *r)
>> +{
>> + __refcount_add_lt(1, &r->refs);
>> +}
>> +
>> +static __always_inline void refcount_dec(refcount_t *r)
>> +{
>> + __refcount_sub_le(1, &r->refs);
>> +}
>> +
>> +static __always_inline __must_check bool refcount_sub_and_test(unsigned int i,
>> + refcount_t *r)
>> +{
>> + return __refcount_sub_lt(i, &r->refs) == 0;
>> +}
>> +
>> +static __always_inline __must_check bool refcount_dec_and_test(refcount_t *r)
>> +{
>> + return __refcount_sub_lt(1, &r->refs) == 0;
>> +}
>> +
>> +static __always_inline __must_check bool refcount_add_not_zero(unsigned int i,
>> + refcount_t *r)
>> +{
>> + return __refcount_add_not_zero(i, &r->refs) != 0;
>> +}
>> +
>> +static __always_inline __must_check bool refcount_inc_not_zero(refcount_t *r)
>> +{
>> + return __refcount_add_not_zero(1, &r->refs) != 0;
>> +}
>> +
>> +#endif
>> diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
>> index 5cf0488..a309215 100644
>> --- a/arch/arm/kernel/traps.c
>> +++ b/arch/arm/kernel/traps.c
>> @@ -795,8 +795,52 @@ void abort(void)
>> }
>> EXPORT_SYMBOL(abort);
>>
>> +#ifdef CONFIG_ARCH_HAS_REFCOUNT
>> +
>> +static int refcount_overflow_handler(struct pt_regs *regs, unsigned int instr)
>> +{
>> + u32 dummy_b = le32_to_cpup((__le32 *)(regs->ARM_pc + 4));
>> + u32 strex;
>> + u32 rt;
>> + bool zero = regs->ARM_cpsr & PSR_Z_BIT;
>> +
>> + /* point pc to the branch instruction that detected the overflow */
>> + regs->ARM_pc += 4 + (((s32)dummy_b << 8) >> 6) + 8;
>> +
>
> This would become something like
>
> s32 offset = *(s32 *)(regs->ARM_pc + 4);
>
> /* point pc to the strex instruction that will overflow the refcount */
> regs->ARM_pc += offset + 4;
>
>
>> + /* decode strex to set refcount */
>> + strex = le32_to_cpup((__le32 *)(regs->ARM_pc + 4));
>> + rt = (strex << 12) >> 28;
>> +
>
> Don't we have better ways to decode an instruction? Also, could you
> add a Thumb2 variant here? (and for the breakpoint instruction)
>
>
>> + /* unconditionally saturate the refcount */
>> + *(int *)regs->uregs[rt] = INT_MIN / 2;
>> +
>> + /* report error */
>> + refcount_error_report(regs, zero ? "hit zero" : "overflow");
>> +
>> + /* advance pc and proceed, skip "strex" routine */
>> + regs->ARM_pc += 16;
>
> Please use a macro here to clarify that you are skipping the remaining
> instructions in REFCOUNT_CHECK_TAIL
>
>> + return 0;
>> +}
>> +
>> +static struct undef_hook refcount_break_hook = {
>> + .instr_mask = 0xffffffff,
>> + .instr_val = REFCOUNT_ARM_BKPT_INSTR,
>> + .cpsr_mask = 0,
>> + .cpsr_val = 0,
>> + .fn = refcount_overflow_handler,
>> +};
>> +
>> +#define register_refcount_break_hook() register_undef_hook(&refcount_break_hook)
>> +
>> +#else /* !CONFIG_ARCH_HAS_REFCOUNT */
>> +
>> +#define register_refcount_break_hook()
>> +
>> +#endif /* CONFIG_ARCH_HAS_REFCOUNT */
>> +
>> void __init trap_init(void)
>> {
>> + register_refcount_break_hook();
>> return;
>> }
>>
>> --
>> 1.9.1
>>
^ permalink raw reply
* [PATCH 2/2] pinctrl/nomadik/abx500: Improve a size determination in abx500_gpio_probe()
From: Linus Walleij @ 2017-12-21 9:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <93beb4d9-99e2-e7f2-e752-2d7228a8df46@users.sourceforge.net>
On Wed, Dec 20, 2017 at 10:52 AM, SF Markus Elfring
<elfring@users.sourceforge.net> wrote:
> From: Markus Elfring <elfring@users.sourceforge.net>
> Date: Wed, 20 Dec 2017 10:22:53 +0100
>
> Replace the specification of a data structure by a pointer dereference
> as the parameter for the operator "sizeof" to make the corresponding size
> determination a bit safer according to the Linux coding style convention.
>
> This issue was detected by using the Coccinelle software.
>
> Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v5 05/15] devicetree: bindings: Document qcom,hfpll
From: Sricharan R @ 2017-12-21 9:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220211147.p555i5eest3ycsbc@rob-hp-laptop>
Hi Rob,
On 12/21/2017 2:41 AM, Rob Herring wrote:
> On Tue, Dec 19, 2017 at 09:24:50PM +0530, Sricharan R wrote:
>> From: Stephen Boyd <sboyd@codeaurora.org>
>>
>> Adds bindings document for qcom,hfpll instantiated within
>> the Krait processor subsystem as separate register region.
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> .../devicetree/bindings/clock/qcom,hfpll.txt | 46 ++++++++++++++++++++++
>> 1 file changed, 46 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,hfpll.txt
>
> "dt-bindings: " is the preferred subject prefix. Otherwise,
>
ok, will update for the next version.
> Reviewed-by: Rob Herring <robh@kernel.org>
Thanks.
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v5 10/15] devicetree: bindings: Document qcom,kpss-gcc
From: Sricharan R @ 2017-12-21 9:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220211328.wbhaxcisz6bzxxql@rob-hp-laptop>
On 12/21/2017 2:43 AM, Rob Herring wrote:
> On Tue, Dec 19, 2017 at 09:24:55PM +0530, Sricharan R wrote:
>> From: Stephen Boyd <sboyd@codeaurora.org>
>>
>> The ACC and GCC regions present in KPSSv1 contain registers to
>> control clocks and power to each Krait CPU and L2. Documenting
>> the bindings here.
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> .../devicetree/bindings/arm/msm/qcom,kpss-acc.txt | 7 +++++
>> .../devicetree/bindings/arm/msm/qcom,kpss-gcc.txt | 32 ++++++++++++++++++++++
>> 2 files changed, 39 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,kpss-gcc.txt
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Thanks !!
Regards,
Sricharan
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v5 12/15] devicetree: bindings: Document qcom,krait-cc
From: Sricharan R @ 2017-12-21 9:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220211450.z2v54bfk53ktpfkz@rob-hp-laptop>
On 12/21/2017 2:44 AM, Rob Herring wrote:
> On Tue, Dec 19, 2017 at 09:24:57PM +0530, Sricharan R wrote:
>> From: Stephen Boyd <sboyd@codeaurora.org>
>>
>> The Krait clock controller controls the krait CPU and the L2 clocks
>> consisting a primary mux and secondary mux. Add document for that.
>>
>> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
>> ---
>> .../devicetree/bindings/clock/qcom,krait-cc.txt | 22 ++++++++++++++++++++++
>> 1 file changed, 22 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/clock/qcom,krait-cc.txt
>
> Reviewed-by: Rob Herring <robh@kernel.org>
Thanks !!
--
"QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH v2] ARM: NOMMU: Setup VBAR/Hivecs for secondaries cores
From: Vladimir Murzin @ 2017-12-21 9:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171221042342.GA5700@afzalpc>
On 21/12/17 04:23, afzal mohammed wrote:
> Hi,
>
> On Tue, Dec 19, 2017 at 02:38:13PM +0000, Vladimir Murzin wrote:
>> With switch to dynamic exception base address setting, VBAR/Hivecs
>> set only for boot CPU, but secondaries stay unaware of that. That
>> might lead to weird effects when trying up to bring up secondaries.
>>
>> Fixes: ad475117d201 ("ARM: 8649/2: nommu: remove Hivecs configuration is asm")
>> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
>
>> +#ifndef CONFIG_MMU
>> + setup_vectors_base();
>> +#endif
>
> i would have preferred instead,
>
> if (!IS_ENABLED(CONFIG_MMU))
> setup_vectors_base();
I agree that IS_ENABLED() macro is a nice feature, especially for block of
code, but not here, IMO. First, I wanted to keep consistent with a existing
style in smp.c; the second, I find it easier to read if_not_defined rather
than if_not_is_enabled.
@Russell, do you have any preference?
>
> either way,
>
> Acked-by: afzal mohammed <afzal.mohd.ma@gmail.com>
Thanks!
Vladimir
>
> afzal
>
^ permalink raw reply
* [GIT PULL] arm: Updates of armv7 DTS for v4.15-next
From: Matthias Brugger @ 2017-12-21 9:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8bf16d56-579c-1579-142f-121990ec0572@gmail.com>
On 12/20/2017 08:18 PM, Matthias Brugger wrote:
> Hi Arnd and Olof,
>
> Please feel free to pull the following patches.
Please ignore this pull request.
It has several issues. I'll send a new one soon.
Sorry for the inconvenience.
Matthias
>
> Thanks,
> Matthias
>
> ---
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the Git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git
> tags/v4.15-next-dts64
>
> for you to fetch changes up to c0c3333daba6617b44228a8dffb8184b2fd1931d:
>
> arm64: dts: Add power controller device node of MT2712 (2017-12-20 20:02:50 +0100)
>
> ----------------------------------------------------------------
> - mt8173 add cpufreq related nodes
> supply nodes
> frequency/voltage operation table
>
> - mt2712 add cpufreq related nodes
> fixed regulator
> supply nodes
> frequency/voltage operation table
> - mt2712 add clock contoller nodes
> - mt2712 add scpsys node
>
> ----------------------------------------------------------------
> Andrew-sh Cheng (2):
> arm64: dts: mediatek: add mt8173 cpufreq related device nodes
> arm64: dts: mediatek: add mt2712 cpufreq related device nodes
>
> weiyi.lu at mediatek.com (2):
> arm64: dts: mt2712: Add clock controller device nodes
> arm64: dts: Add power controller device node of MT2712
>
> arch/arm64/boot/dts/mediatek/mt2712-evb.dts | 27 ++++
> arch/arm64/boot/dts/mediatek/mt2712e.dtsi | 188 ++++++++++++++++++++++++++++
> arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 18 +++
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 90 +++++++++++++
> 4 files changed, 323 insertions(+)
>
^ permalink raw reply
* [GIT PULL] arm64: Updates of aarch64 DTS files for v4.15-next
From: Matthias Brugger @ 2017-12-21 9:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513821882.15465.4.camel@mtkswgap22>
On 12/21/2017 03:04 AM, Sean Wang wrote:
> Hi, Matthias
>
> title and content seems not consistent, and the other git pull for armv7
> does too.
>
Thanks for noting. Olof, Arnd, I'll resend both dts32 and dts64 soon.
Please ignore this pull request for now.
Regards,
Matthias
> Sean
>
> On Wed, 2017-12-20 at 20:19 +0100, Matthias Brugger wrote:
>> Hi Olof, hi Arnd,
>>
>> Please take the patches below into consideration.
>>
>> Thanks a lot,
>> Matthias
>>
>> ---
>> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>>
>> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>>
>> are available in the Git repository at:
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux.git
>> tags/v4.15-next-dts32
>>
>> for you to fetch changes up to a227cf4dfd74a873857c9cc017100168d01539ed:
>>
>> dt-bindings: ARM: Mediatek: Fix ethsys documentation (2017-12-20 18:10:12 +0100)
>>
>> ----------------------------------------------------------------
>> - add reset cells mt2701 and mt7623 ethsys
>> - update mmc nodes for mt7623
>> - mt7623 change mmc card detection pin to active low
>> - mt7623 set unit address to lower case
>>
>> ----------------------------------------------------------------
>> Mathieu Malaterre (1):
>> arm: mt7: dts: Remove leading 0x and 0s from bindings notation
>>
>> Matthias Brugger (3):
>> arm: dts: mt7623: Update ethsys binding
>> arm: dts: mt2701: Add reset-cells
>> dt-bindings: ARM: Mediatek: Fix ethsys documentation
>>
>> Sean Wang (2):
>> arm: dts: mt7623: update mmc related nodes with the appropriate fallback
>> arm: dts: mt7623: fix card detection issue on bananapi-r2
>
>> Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt | 1 +
>> arch/arm/boot/dts/mt2701.dtsi | 2 ++
>> arch/arm/boot/dts/mt7623.dtsi | 5 +++--
>> arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts | 2 +-
>> arch/arm/boot/dts/mt7623n-rfb-nand.dts | 2 +-
>> 5 files changed, 8 insertions(+), 4 deletions(-)
>
>
^ permalink raw reply
* [PATCH 1/2] thermal: mtk: Cleanup unused defines
From: Matthias Brugger @ 2017-12-21 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171201104321.8410-1-matthias.bgg@gmail.com>
On 12/01/2017 11:43 AM, Matthias Brugger wrote:
> The mtk_thermal has some defiens which are never used within the driver.
> This patch delets them.
>
> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
> ---
Rui, Eduardo, do you have any comments on this patch?
Regards,
Matthias
> drivers/thermal/mtk_thermal.c | 9 +--------
> 1 file changed, 1 insertion(+), 8 deletions(-)
>
> diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c
> index 1e61c09153c9..c75661a3801a 100644
> --- a/drivers/thermal/mtk_thermal.c
> +++ b/drivers/thermal/mtk_thermal.c
> @@ -32,15 +32,10 @@
> #include <linux/types.h>
>
> /* AUXADC Registers */
> -#define AUXADC_CON0_V 0x000
> -#define AUXADC_CON1_V 0x004
> #define AUXADC_CON1_SET_V 0x008
> #define AUXADC_CON1_CLR_V 0x00c
> #define AUXADC_CON2_V 0x010
> #define AUXADC_DATA(channel) (0x14 + (channel) * 4)
> -#define AUXADC_MISC_V 0x094
> -
> -#define AUXADC_CON1_CHANNEL(x) BIT(x)
>
> #define APMIXED_SYS_TS_CON1 0x604
>
> @@ -158,8 +153,6 @@
> /* The number of sensing points per bank */
> #define MT2712_NUM_SENSORS_PER_ZONE 4
>
> -#define THERMAL_NAME "mtk-thermal"
> -
> struct mtk_thermal;
>
> struct thermal_bank_cfg {
> @@ -765,7 +758,7 @@ static struct platform_driver mtk_thermal_driver = {
> .probe = mtk_thermal_probe,
> .remove = mtk_thermal_remove,
> .driver = {
> - .name = THERMAL_NAME,
> + .name = "mtk-thermal",
> .of_match_table = mtk_thermal_of_match,
> },
> };
>
^ permalink raw reply
* [LINUX PATCH 0/4] dmaengine: xilinx_dma: Bug fixes
From: Kedareswara rao Appana @ 2017-12-21 10:11 UTC (permalink / raw)
To: linux-arm-kernel
This patch series does the below
--> Fixes sparse warnings in the driver.
--> Fixes race conditions in the driver for cdma.
--> Fixes issues with the dma_get_slave_caps() API failures.
This patch series got created on top of below commit
in the slave-dma.git topic/xilinx branch.
"dmaengine: xilinx_dma: Fix typos"
Kedareswara rao Appana (4):
dmaengine: xilinx_dma: Fix dma_get_slave_caps() API failures
dmaengine: xilinx_dma: Fix race condition in the driver for cdma
dmaengine: xilinx_dma: Fix compilation warning
dmaengine: xilinx_dma: Free BD consistent memory
drivers/dma/xilinx/xilinx_dma.c | 23 ++++++++++++++++++++---
1 file changed, 20 insertions(+), 3 deletions(-)
--
2.7.4
^ permalink raw reply
* [LINUX PATCH 1/4] dmaengine: xilinx_dma: Fix dma_get_slave_caps() API failures
From: Kedareswara rao Appana @ 2017-12-21 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513851098-15787-1-git-send-email-appanad@xilinx.com>
When client driver uses dma_get_slave_caps() api,
it checks for certain fields of dma_device struct
currently driver is not settings few fields resulting
dma_get_slave_caps() returning failure.
This patch fixes this issue by populating proper values
to the struct dma_device fields.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
---
drivers/dma/xilinx/xilinx_dma.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 88d317d..21ac954 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -2398,6 +2398,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
chan->direction = DMA_MEM_TO_DEV;
chan->id = chan_id;
chan->tdest = chan_id;
+ xdev->common.directions = BIT(DMA_MEM_TO_DEV);
chan->ctrl_offset = XILINX_DMA_MM2S_CTRL_OFFSET;
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
@@ -2415,6 +2416,7 @@ static int xilinx_dma_chan_probe(struct xilinx_dma_device *xdev,
chan->direction = DMA_DEV_TO_MEM;
chan->id = chan_id;
chan->tdest = chan_id - xdev->nr_channels;
+ xdev->common.directions |= BIT(DMA_DEV_TO_MEM);
chan->ctrl_offset = XILINX_DMA_S2MM_CTRL_OFFSET;
if (xdev->dma_config->dmatype == XDMA_TYPE_VDMA) {
@@ -2629,6 +2631,8 @@ static int xilinx_dma_probe(struct platform_device *pdev)
dma_cap_set(DMA_PRIVATE, xdev->common.cap_mask);
}
+ xdev->common.dst_addr_widths = BIT(addr_width / 8);
+ xdev->common.src_addr_widths = BIT(addr_width / 8);
xdev->common.device_alloc_chan_resources =
xilinx_dma_alloc_chan_resources;
xdev->common.device_free_chan_resources =
--
2.7.4
^ permalink raw reply related
* [LINUX PATCH 2/4] dmaengine: xilinx_dma: Fix race condition in the driver for cdma
From: Kedareswara rao Appana @ 2017-12-21 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513851098-15787-1-git-send-email-appanad@xilinx.com>
when hardware is idle we need to toggle the SG bit
in the control register, inorder to update new value to the
current descriptor register other wise undefined
results will occur.
This patch updates the same.
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
---
drivers/dma/xilinx/xilinx_dma.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 21ac954..8467671 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1204,6 +1204,12 @@ static void xilinx_cdma_start_transfer(struct xilinx_dma_chan *chan)
}
if (chan->has_sg) {
+ dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
+ XILINX_CDMA_CR_SGMODE);
+
+ dma_ctrl_set(chan, XILINX_DMA_REG_DMACR,
+ XILINX_CDMA_CR_SGMODE);
+
xilinx_write(chan, XILINX_DMA_REG_CURDESC,
head_desc->async_tx.phys);
@@ -2052,6 +2058,10 @@ static int xilinx_dma_terminate_all(struct dma_chan *dchan)
chan->cyclic = false;
}
+ if ((chan->xdev->dma_config->dmatype == XDMA_TYPE_CDMA) && chan->has_sg)
+ dma_ctrl_clr(chan, XILINX_DMA_REG_DMACR,
+ XILINX_CDMA_CR_SGMODE);
+
return 0;
}
--
2.7.4
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* [LINUX PATCH 3/4] dmaengine: xilinx_dma: Fix compilation warning
From: Kedareswara rao Appana @ 2017-12-21 10:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513851098-15787-1-git-send-email-appanad@xilinx.com>
This patch fixes the below sparse warning in the driver
drivers/dma/xilinx/xilinx_dma.c: In function ?xilinx_vdma_dma_prep_interleaved?:
drivers/dma/xilinx/xilinx_dma.c:1614:43: warning: variable ?prev? set but not used [-Wunused-but-set-variable]
struct xilinx_vdma_tx_segment *segment, *prev = NULL;
Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com>
---
drivers/dma/xilinx/xilinx_dma.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c
index 8467671..845e638 100644
--- a/drivers/dma/xilinx/xilinx_dma.c
+++ b/drivers/dma/xilinx/xilinx_dma.c
@@ -1611,7 +1611,7 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
{
struct xilinx_dma_chan *chan = to_xilinx_chan(dchan);
struct xilinx_dma_tx_descriptor *desc;
- struct xilinx_vdma_tx_segment *segment, *prev = NULL;
+ struct xilinx_vdma_tx_segment *segment;
struct xilinx_vdma_desc_hw *hw;
if (!is_slave_direction(xt->dir))
@@ -1665,8 +1665,6 @@ xilinx_vdma_dma_prep_interleaved(struct dma_chan *dchan,
/* Insert the segment into the descriptor segments list. */
list_add_tail(&segment->node, &desc->segments);
- prev = segment;
-
/* Link the last hardware descriptor with the first. */
segment = list_first_entry(&desc->segments,
struct xilinx_vdma_tx_segment, node);
--
2.7.4
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