* [PATCH v2 4/5] ARM: dts: Add support for emtrion emCON-MX6 series
From: Alexandre Belloni @ 2017-12-22 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b41bc779-28e8-5a87-6f66-f5874dba8d1e@suse.de>
+ Philippe
On 22/12/2017 at 11:43:33 +0100, Andreas F?rber wrote:
> >> I'll change it for v3 of this patch however it will end up like this:
> >> //SPDX-License...
> >
> > That should be /* SPDX-License */, // is for c files.
>
> Got any reference for that? Since we're using the C preprocessor before
> feeding them to dtc, we can use the same // style for both, builds fine.
>
> Only for my private DT overlay files that I use directly with dtc I
> couldn't adopt that style.
>
The doc states:
If a specific tool cannot handle the standard comment style, then the
appropriate comment mechanism which the tool accepts shall be used. This
is the reason for having the "/\* \*/" style comment in C header
files.
I interpreted that as dtc doesn't handle // comments, use /**/
But I agree it also states:
.dts{i}: // SPDX-License-Identifier: <SPDX License Expression>
So I think we will end up with a mix of both.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [linux-sunxi] [PATCH v4 2/2] media: V3s: Add support for Allwinner CSI.
From: Yong @ 2017-12-22 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222102156.cfemen6ouxxxbrem@plaes.org>
Hi,
On Fri, 22 Dec 2017 10:21:56 +0000
Priit Laes <plaes@plaes.org> wrote:
> On Fri, Dec 22, 2017 at 05:47:00PM +0800, Yong Deng wrote:
> > Allwinner V3s SoC have two CSI module. CSI0 is used for MIPI interface
> > and CSI1 is used for parallel interface. This is not documented in
> > datasheet but by testing and guess.
> >
> > This patch implement a v4l2 framework driver for it.
...
> > + if ((sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_PARALLEL
> > + || sdev->csi.v4l2_ep.bus_type == V4L2_MBUS_BT656)
> > + && sdev->csi.v4l2_ep.bus.parallel.bus_width == 16) {
> > + switch (pixformat) {
> > + case V4L2_PIX_FMT_HM12:
> > + case V4L2_PIX_FMT_NV12:
> > + case V4L2_PIX_FMT_NV21:
> > + case V4L2_PIX_FMT_NV16:
> > + case V4L2_PIX_FMT_NV61:
> > + case V4L2_PIX_FMT_YUV420:
> > + case V4L2_PIX_FMT_YVU420:
> > + case V4L2_PIX_FMT_YUV422P:
> > + switch (mbus_code) {
> > + case MEDIA_BUS_FMT_UYVY8_1X16:
> > + case MEDIA_BUS_FMT_VYUY8_1X16:
> > + case MEDIA_BUS_FMT_YUYV8_1X16:
> > + case MEDIA_BUS_FMT_YVYU8_1X16:
> > + return true;
> > + }
> > + break;
> > + }
> Should we add default cases and warning messages here for debug purposes?
OK. I will add all the default cases and messages.
Thanks,
Yong
^ permalink raw reply
* [GIT PULL] ARM: mvebu: arm64 for v4.16 (#1)
From: Gregory CLEMENT @ 2017-12-22 10:52 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for arm64 for mvebu for v4.16.
Gregory
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-arm64-4.16-1
for you to fetch changes up to ee0b915ba83212dc2288b08f1120c27c694a0d9b:
arm64: defconfig: enable ARM_ARMADA_37XX_CPUFREQ (2017-12-21 12:11:57 +0100)
----------------------------------------------------------------
mvebu arm64 for 4.16 (part 1)
Adding the cpu frequency scaling support for Armada 37xx
----------------------------------------------------------------
Gregory CLEMENT (1):
arm64: defconfig: enable ARM_ARMADA_37XX_CPUFREQ
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt64 for v4.16 (#1)
From: Gregory CLEMENT @ 2017-12-22 10:51 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for dt64 for mvebu for v4.16.
Gregory
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-dt64-4.16-1
for you to fetch changes up to 4cada03801992d09ccceaf5f462e9dadb75a9613:
ARM64: dts: marvell: Add thermal support for A7K/A8K (2017-12-18 17:13:17 +0100)
----------------------------------------------------------------
mvebu dt64 for 4.16 (part 1)
Add the NAND support on the Marvell 8040-DB board
Add the thermal support for Martvell A7K/A8K Socs
Add nodes allowing cpufreq support on Aramda 3700 SoCs
----------------------------------------------------------------
Gregory CLEMENT (1):
arm64: dts: marvell: armada-37xx: add nodes allowing cpufreq support
Miquel Raynal (2):
arm64: dts: marvell: add NAND support on the 8040-DB board
ARM64: dts: marvell: Add thermal support for A7K/A8K
arch/arm64/boot/dts/marvell/armada-372x.dtsi | 1 +
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 7 ++++++
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 28 ++++++++++++++++++++++
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 17 +++++++++++++
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 6 +++++
.../boot/dts/marvell/armada-cp110-master.dtsi | 6 +++++
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 9 ++++++-
7 files changed, 73 insertions(+), 1 deletion(-)
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt for v4.16 (#1)
From: Gregory CLEMENT @ 2017-12-22 10:51 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Here is the first pull request for dt for mvebu for v4.16.
Gregory
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.infradead.org/linux-mvebu.git tags/mvebu-dt-4.16-1
for you to fetch changes up to cea96bf1836f22d2586f650a0299bd37abf2d42e:
arm: kirkwood: dts: Use lower case for bindings notation (2017-12-18 17:44:48 +0100)
----------------------------------------------------------------
mvebu dt for 4.16 (part 1)
Fix potential dtc warnings on kirkwoods files
Declare a new pin (RB) usbale for NAND controller on Armada 38x
----------------------------------------------------------------
Mathieu Malaterre (1):
arm: kirkwood: dts: Use lower case for bindings notation
Sean Nyekjaer (1):
ARM: dts: armada-38x: Add NAND RB pinctrl information
arch/arm/boot/dts/armada-38x.dtsi | 5 +++++
arch/arm/boot/dts/kirkwood-linksys-viper.dts | 10 +++++-----
2 files changed, 10 insertions(+), 5 deletions(-)
^ permalink raw reply
* [PATCH v6 06/11] thermal: armada: Add support for Armada AP806
From: Miquel RAYNAL @ 2017-12-22 10:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222101426.yujvg2xbca3ghpyc@tarshish>
Hi Baruch,
On Fri, 22 Dec 2017 12:14:26 +0200
Baruch Siach <baruch@tkos.co.il> wrote:
> Hi Miqu?l,
>
> On Fri, Dec 22, 2017 at 10:32:21AM +0100, Miquel Raynal wrote:
> > From: Baruch Siach <baruch@tkos.co.il>
> >
> > The AP806 component is integrated in the Armada 8K and 7K lines of
> > processors.
> >
> > The thermal sensor sample field on the status register is a signed
> > value. Extend armada_get_temp() and the driver structure to handle
> > signed values.
> >
> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> > [<miquel.raynal@free-electrons.com>: Changes when applying over the
> > previous patches, including the register names changes, also
> > switched the coefficients values to s64 instead of unsigned long to
> > deal with negative values and used do_div instead of the
> > traditionnal '/'] Signed-off-by: Miquel Raynal
> > <miquel.raynal@free-electrons.com> Reviewed-by: Gregory CLEMENT
> > <gregory.clement@free-electrons.com> Tested-by: Gregory CLEMENT
> > <gregory.clement@free-electrons.com> ---
>
> [..]
>
> > static int armada_get_temp(struct thermal_zone_device *thermal,
> > - int *temp)
> > + int *temperature)
> > {
> > struct armada_thermal_priv *priv = thermal->devdata;
> > - unsigned long reg;
> > - unsigned long m, b, div;
> > + u32 reg, div;
> > + s64 sample, b, m;
> > + u64 tmp;
> >
> > /* Valid check */
> > if (priv->data->is_valid && !priv->data->is_valid(priv)) {
> > @@ -178,6 +197,11 @@ static int armada_get_temp(struct
> > thermal_zone_device *thermal,
> > reg = readl_relaxed(priv->status);
> > reg = (reg >> priv->data->temp_shift) &
> > priv->data->temp_mask;
> > + if (priv->data->signed_sample)
> > + /* The most significant bit is the sign bit */
> > + sample = sign_extend32(reg,
> > fls(priv->data->temp_mask) - 1);
> > + else
> > + sample = reg;
> >
> > /* Get formula coeficients */
> > b = priv->data->coef_b;
> > @@ -185,9 +209,13 @@ static int armada_get_temp(struct
> > thermal_zone_device *thermal, div = priv->data->coef_div;
> >
> > if (priv->data->inverted)
> > - *temp = ((m * reg) - b) / div;
> > + tmp = (m * sample) - b;
> > else
> > - *temp = (b - (m * reg)) / div;
> > + tmp = b - (m * sample);
> > +
> > + do_div(tmp, div);
> > + *temperature = (int)tmp;
>
> Nitpick: why not (untested)
>
> #include <linux/math64.h>
>
> if (priv->data->inverted)
> *temp = div_s64((m * sample) - b, div);
> else
> *temp = div_s64(b - (m * sample), div);
Indeed I could also use div_s64, but the result must be unsigned anyway.
But this does all the operations on the same line, maybe this is more
readable, I will update it and send (hopefully) the last version :)
Cheers,
Miqu?l
>
> baruch
>
> > +
> > return 0;
> > }
>
--
Miquel Raynal, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v2 4/5] ARM: dts: Add support for emtrion emCON-MX6 series
From: Andreas Färber @ 2017-12-22 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <95F51F4B902CAC40AF459205F6322F01B7FDFECC3C@BMK019S01.emtrion.local>
Am 22.12.2017 um 11:34 schrieb T?rk, Jan:
>> On Wed, Dec 20, 2017 at 02:47:04PM +0100, jan.tuerk at emtrion.com wrote:
>>> + * SPDX-License-Identifier: GPL-2.0
>>
>> You have this.
>>
>> Also, the rules around this are getting a bit stricter saying the SPDX
>> tag should be the first line of the file using a C++ style comment.
>>
> I'll change it for v3 of this patch however it will end up like this:
> //SPDX-License...
I would've expected:
// SPDX-License...
> /*
> * Copyright
Cheers,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [PATCH v2 4/5] ARM: dts: Add support for emtrion emCON-MX6 series
From: Andreas Färber @ 2017-12-22 10:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222104028.GC18255@piout.net>
Hi,
Am 22.12.2017 um 11:40 schrieb Alexandre Belloni:
> On 22/12/2017 at 11:34:31 +0100, T?rk, Jan wrote:
>>>> diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-
>>> emcon.dtsi
>>>> new file mode 100644
>>>> index 000000000000..64fc0cd74c05
>>>> --- /dev/null
>>>> +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi
>>>> @@ -0,0 +1,37 @@
>>>> +/*
>>>> + * Copyright (C) 2017 emtrion GmbH
>>>> + * Author: Jan Tuerk <jan.tuerk@emtrion.com>
>>>> + *
>>>> + * The code contained herein is licensed under the GNU General Public
>>>> + * License. You may obtain a copy of the GNU General Public License
>>>> + * Version 2 or later at the following locations:
>>>> + *
>>>> + * http://www.opensource.org/licenses/gpl-license.html
>>>> + * http://www.gnu.org/copyleft/gpl.html
>>>
>>> You don't need this if...
>>
>> I've got a little different point of view on this since the OSS Europe 2017 - part of gpl2 following.
>>
>> GPLv2-Para1 (=>highlighted<=) :
>> 1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium,
>> provided that you conspicuously and appropriately publish on each copy an
>> => appropriate copyright notice and disclaimer of warranty; <=
>> keep intact all the notices that refer to this License and to the absence of any warranty;
>> and give any other recipients of the Program a copy of this License along with the Program.
>>
>> After reviewing this I think apparently I should include the Warranty disclaimer as well.
>> Examples could be found in:
>> arch/arm/boot/dts/imx6q-tbs2910.dts
>> and
>> arch/arm/boot/dts/imx6q-zii-rdu2.dts
>>
>
> The license is already fully included in COPYING with the warranty
> disclaimer.
>
>>>
>>>> + *
>>>> + * SPDX-License-Identifier: GPL-2.0
>>>
>>> You have this.
>>>
>>> Also, the rules around this are getting a bit stricter saying the SPDX
>>> tag should be the first line of the file using a C++ style comment.
>>>
>> I'll change it for v3 of this patch however it will end up like this:
>> //SPDX-License...
>
> That should be /* SPDX-License */, // is for c files.
Got any reference for that? Since we're using the C preprocessor before
feeding them to dtc, we can use the same // style for both, builds fine.
Only for my private DT overlay files that I use directly with dtc I
couldn't adopt that style.
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [PATCH v2 4/5] ARM: dts: Add support for emtrion emCON-MX6 series
From: Alexandre Belloni @ 2017-12-22 10:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <95F51F4B902CAC40AF459205F6322F01B7FDFECC3C@BMK019S01.emtrion.local>
Hi,
On 22/12/2017 at 11:34:31 +0100, T?rk, Jan wrote:
> > > diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-
> > emcon.dtsi
> > > new file mode 100644
> > > index 000000000000..64fc0cd74c05
> > > --- /dev/null
> > > +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi
> > > @@ -0,0 +1,37 @@
> > > +/*
> > > + * Copyright (C) 2017 emtrion GmbH
> > > + * Author: Jan Tuerk <jan.tuerk@emtrion.com>
> > > + *
> > > + * The code contained herein is licensed under the GNU General Public
> > > + * License. You may obtain a copy of the GNU General Public License
> > > + * Version 2 or later at the following locations:
> > > + *
> > > + * http://www.opensource.org/licenses/gpl-license.html
> > > + * http://www.gnu.org/copyleft/gpl.html
> >
> > You don't need this if...
>
> I've got a little different point of view on this since the OSS Europe 2017 - part of gpl2 following.
>
> GPLv2-Para1 (=>highlighted<=) :
> 1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium,
> provided that you conspicuously and appropriately publish on each copy an
> => appropriate copyright notice and disclaimer of warranty; <=
> keep intact all the notices that refer to this License and to the absence of any warranty;
> and give any other recipients of the Program a copy of this License along with the Program.
>
> After reviewing this I think apparently I should include the Warranty disclaimer as well.
> Examples could be found in:
> arch/arm/boot/dts/imx6q-tbs2910.dts
> and
> arch/arm/boot/dts/imx6q-zii-rdu2.dts
>
The license is already fully included in COPYING with the warranty
disclaimer.
> >
> > > + *
> > > + * SPDX-License-Identifier: GPL-2.0
> >
> > You have this.
> >
> > Also, the rules around this are getting a bit stricter saying the SPDX
> > tag should be the first line of the file using a C++ style comment.
> >
> I'll change it for v3 of this patch however it will end up like this:
> //SPDX-License...
That should be /* SPDX-License */, // is for c files.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] clk: divider: fix incorrect usage of container_of
From: Alexandre Belloni @ 2017-12-22 10:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171221163054.13600-1-jbrunet@baylibre.com>
On 21/12/2017 at 17:30:54 +0100, Jerome Brunet wrote:
> divider_recalc_rate() is an helper function used by clock divider of
> different types, so the structure containing the 'hw' pointer is not
> always a 'struct clk_divider'
>
> At the following line:
> > div = _get_div(table, val, flags, divider->width);
>
> in several cases, the value of 'divider->width' is garbage as the actual
> structure behind this memory is not a 'struct clk_divider'
>
> Fortunately, this width value is used by _get_val() only when
> CLK_DIVIDER_MAX_AT_ZERO flag is set. This has never been the case so
> far when the structure is not a 'struct clk_divider'. This is probably
> why we did not notice this bug before
>
> Fixes: afe76c8fd030 ("clk: allow a clk divider with max divisor when zero")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
For RTC:
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> Hi Stephen, Mike,
>
> In addition to clock, this patch also touch the rtc and drm directories.
> As it is changing the API of the helper function, I have this fix in a
> single commit to avoid breaking bisect.
>
> Please let me know if you prefer to do differently.
>
> Cheers
> Jerome
>
> drivers/clk/clk-divider.c | 7 +++----
> drivers/clk/hisilicon/clkdivider-hi6220.c | 2 +-
> drivers/clk/nxp/clk-lpc32xx.c | 2 +-
> drivers/clk/qcom/clk-regmap-divider.c | 2 +-
> drivers/clk/sunxi-ng/ccu_div.c | 2 +-
> drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 2 +-
> drivers/rtc/rtc-ac100.c | 6 ++++--
> include/linux/clk-provider.h | 2 +-
> 8 files changed, 13 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
> index 4ed516cb7276..b49942b9fe50 100644
> --- a/drivers/clk/clk-divider.c
> +++ b/drivers/clk/clk-divider.c
> @@ -118,12 +118,11 @@ static unsigned int _get_val(const struct clk_div_table *table,
> unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
> unsigned int val,
> const struct clk_div_table *table,
> - unsigned long flags)
> + unsigned long flags, unsigned long width)
> {
> - struct clk_divider *divider = to_clk_divider(hw);
> unsigned int div;
>
> - div = _get_div(table, val, flags, divider->width);
> + div = _get_div(table, val, flags, width);
> if (!div) {
> WARN(!(flags & CLK_DIVIDER_ALLOW_ZERO),
> "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
> @@ -145,7 +144,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> val &= div_mask(divider->width);
>
> return divider_recalc_rate(hw, parent_rate, val, divider->table,
> - divider->flags);
> + divider->flags, divider->width);
> }
>
> static bool _is_valid_table_div(const struct clk_div_table *table,
> diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c
> index a1c1f684ad58..9f46cf9dcc65 100644
> --- a/drivers/clk/hisilicon/clkdivider-hi6220.c
> +++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
> @@ -56,7 +56,7 @@ static unsigned long hi6220_clkdiv_recalc_rate(struct clk_hw *hw,
> val &= div_mask(dclk->width);
>
> return divider_recalc_rate(hw, parent_rate, val, dclk->table,
> - CLK_DIVIDER_ROUND_CLOSEST);
> + CLK_DIVIDER_ROUND_CLOSEST, dclk->width);
> }
>
> static long hi6220_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate,
> diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
> index b669a5c10fee..f5d815f577e0 100644
> --- a/drivers/clk/nxp/clk-lpc32xx.c
> +++ b/drivers/clk/nxp/clk-lpc32xx.c
> @@ -956,7 +956,7 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
> val &= div_mask(divider->width);
>
> return divider_recalc_rate(hw, parent_rate, val, divider->table,
> - divider->flags);
> + divider->flags, divider->width);
> }
>
> static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
> diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
> index 53484912301e..928fcc16ee27 100644
> --- a/drivers/clk/qcom/clk-regmap-divider.c
> +++ b/drivers/clk/qcom/clk-regmap-divider.c
> @@ -59,7 +59,7 @@ static unsigned long div_recalc_rate(struct clk_hw *hw,
> div &= BIT(divider->width) - 1;
>
> return divider_recalc_rate(hw, parent_rate, div, NULL,
> - CLK_DIVIDER_ROUND_CLOSEST);
> + CLK_DIVIDER_ROUND_CLOSEST, divider->width);
> }
>
> const struct clk_ops clk_regmap_div_ops = {
> diff --git a/drivers/clk/sunxi-ng/ccu_div.c b/drivers/clk/sunxi-ng/ccu_div.c
> index baa3cf96507b..302a18efd39f 100644
> --- a/drivers/clk/sunxi-ng/ccu_div.c
> +++ b/drivers/clk/sunxi-ng/ccu_div.c
> @@ -71,7 +71,7 @@ static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
> parent_rate);
>
> val = divider_recalc_rate(hw, parent_rate, val, cd->div.table,
> - cd->div.flags);
> + cd->div.flags, cd->div.width);
>
> if (cd->common.features & CCU_FEATURE_FIXED_POSTDIV)
> val /= cd->fixed_post_div;
> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> index fe15aa64086f..71fe60e5f01f 100644
> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
> @@ -698,7 +698,7 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
> val &= div_mask(width);
>
> return divider_recalc_rate(hw, parent_rate, val, NULL,
> - postdiv->flags);
> + postdiv->flags, width);
> }
>
> static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
> diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
> index 9e336184491c..0282ccc6181c 100644
> --- a/drivers/rtc/rtc-ac100.c
> +++ b/drivers/rtc/rtc-ac100.c
> @@ -137,13 +137,15 @@ static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
> div = (reg >> AC100_CLKOUT_PRE_DIV_SHIFT) &
> ((1 << AC100_CLKOUT_PRE_DIV_WIDTH) - 1);
> prate = divider_recalc_rate(hw, prate, div,
> - ac100_clkout_prediv, 0);
> + ac100_clkout_prediv, 0,
> + AC100_CLKOUT_PRE_DIV_WIDTH);
> }
>
> div = (reg >> AC100_CLKOUT_DIV_SHIFT) &
> (BIT(AC100_CLKOUT_DIV_WIDTH) - 1);
> return divider_recalc_rate(hw, prate, div, NULL,
> - CLK_DIVIDER_POWER_OF_TWO);
> + CLK_DIVIDER_POWER_OF_TWO,
> + AC100_CLKOUT_DIV_WIDTH);
> }
>
> static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
> diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
> index 73ac87f34df9..4c4001086447 100644
> --- a/include/linux/clk-provider.h
> +++ b/include/linux/clk-provider.h
> @@ -412,7 +412,7 @@ extern const struct clk_ops clk_divider_ro_ops;
>
> unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
> unsigned int val, const struct clk_div_table *table,
> - unsigned long flags);
> + unsigned long flags, unsigned long width);
> long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
> unsigned long rate, unsigned long *prate,
> const struct clk_div_table *table,
> --
> 2.14.3
>
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH 1/1] soc: renesas: rcar-sysc: Keep wakeup sources active during system suspend
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513936182.git.horms+renesas@verge.net.au>
From: Geert Uytterhoeven <geert+renesas@glider.be>
If an R-Car SYSC slave device is part of the CPG/MSTP or CPG/MSSR Clock
Domain and to be used as a wakeup source, it must be kept active during
system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
drivers/soc/renesas/rcar-sysc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/renesas/rcar-sysc.c b/drivers/soc/renesas/rcar-sysc.c
index 55a47e509e49..52c25a5e2646 100644
--- a/drivers/soc/renesas/rcar-sysc.c
+++ b/drivers/soc/renesas/rcar-sysc.c
@@ -224,7 +224,7 @@ static void __init rcar_sysc_pd_setup(struct rcar_sysc_pd *pd)
if (!(pd->flags & (PD_CPU | PD_SCU))) {
/* Enable Clock Domain for I/O devices */
- genpd->flags |= GENPD_FLAG_PM_CLK;
+ genpd->flags |= GENPD_FLAG_PM_CLK | GENPD_FLAG_ACTIVE_WAKEUP;
if (has_cpg_mstp) {
genpd->attach_dev = cpg_mstp_attach_dev;
genpd->detach_dev = cpg_mstp_detach_dev;
--
2.11.0
^ permalink raw reply related
* [GIT PULL] Second Round of Renesas ARM Based SoC Updates for v4.16
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM based SoC updates for v4.16.
This pull request is based on the previous round of
such requests, tagged as renesas-soc-for-v4.16,
which I have already sent a pull-request for.
The following changes since commit 90f0d2b344313a8a4c366ef60d0df33008d2be84:
soc: renesas: Identify R-Car M3-W ES1.1 (2017-11-27 11:40:57 +0100)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc2-for-v4.16
for you to fetch changes up to 91c719f5ec6671f7b63762d78897af5583dd7693:
soc: renesas: rcar-sysc: Keep wakeup sources active during system suspend (2017-12-20 11:16:05 +0100)
----------------------------------------------------------------
Second Round of Renesas ARM Based SoC Updates for v4.16
* rcar-sysc: Keep wakeup sources active during system suspend
Geert Uytterhoeven says "If an R-Car SYSC slave device is part of the
CPG/MSTP or CPG/MSSR Clock Domain and to be used as a wakeup source, it
must be kept active during system suspend.
Currently this is handled in device-specific drivers by explicitly
increasing the use count of the module clock when the device is
configured as a wakeup source. However, the proper way to prevent the
device from being stopped is to inform this requirement to the genpd
core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
Note that this will only affect devices configured as wakeup sources."
----------------------------------------------------------------
Geert Uytterhoeven (1):
soc: renesas: rcar-sysc: Keep wakeup sources active during system suspend
drivers/soc/renesas/rcar-sysc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
^ permalink raw reply
* [PATCH 2/2] arm64: dts: renesas: ulcb: Remove renesas, no-ether-link property
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938447.git.horms+renesas@verge.net.au>
From: Bogdan Mirea <Bogdan-Stefan_Mirea@mentor.com>
The present change is a bug fix for AVB link iteratively up/down.
Steps to reproduce:
- start AVB TX stream (Using aplay via MSE),
- disconnect+reconnect the eth cable,
- after a reconnection the eth connection goes iteratively up/down
without user interaction,
- this may heal after some seconds or even stay for minutes.
As the documentation specifies, the "renesas,no-ether-link" option
should be used when a board does not provide a proper AVB_LINK signal.
There is no need for this option enabled on RCAR H3/M3 Salvator-X/XS
and ULCB starter kits since the AVB_LINK is correctly handled by HW.
Choosing to keep or remove the "renesas,no-ether-link" option will
have impact on the code flow in the following ways:
- keeping this option enabled may lead to unexpected behavior since
the RX & TX are enabled/disabled directly from adjust_link function
without any HW interrogation,
- removing this option, the RX & TX will only be enabled/disabled after
HW interrogation. The HW check is made through the LMON pin in PSR
register which specifies AVB_LINK signal value (0 - at low level;
1 - at high level).
In conclusion, the present change is also a safety improvement because
it removes the "renesas,no-ether-link" option leading to a proper way
of detecting the link state based on HW interrogation and not on
software heuristic.
Fixes: dc36965a8905 ("arm64: dts: r8a7796: salvator-x: Enable EthernetAVB")
Fixes: 6fa501c549aa ("arm64: dts: r8a7795: enable EthernetAVB on Salvator-X")
Signed-off-by: Bogdan Mirea <Bogdan-Stefan_Mirea@mentor.com>
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/ulcb.dtsi b/arch/arm64/boot/dts/renesas/ulcb.dtsi
index 0d85b315ce71..73439cf48659 100644
--- a/arch/arm64/boot/dts/renesas/ulcb.dtsi
+++ b/arch/arm64/boot/dts/renesas/ulcb.dtsi
@@ -145,7 +145,6 @@
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
- renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
--
2.11.0
^ permalink raw reply related
* [PATCH 1/2] arm64: dts: renesas: salvator-x: Remove renesas, no-ether-link property
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938447.git.horms+renesas@verge.net.au>
From: Bogdan Mirea <Bogdan-Stefan_Mirea@mentor.com>
The present change is a bug fix for AVB link iteratively up/down.
Steps to reproduce:
- start AVB TX stream (Using aplay via MSE),
- disconnect+reconnect the eth cable,
- after a reconnection the eth connection goes iteratively up/down
without user interaction,
- this may heal after some seconds or even stay for minutes.
As the documentation specifies, the "renesas,no-ether-link" option
should be used when a board does not provide a proper AVB_LINK signal.
There is no need for this option enabled on RCAR H3/M3 Salvator-X/XS
and ULCB starter kits since the AVB_LINK is correctly handled by HW.
Choosing to keep or remove the "renesas,no-ether-link" option will
have impact on the code flow in the following ways:
- keeping this option enabled may lead to unexpected behavior since
the RX & TX are enabled/disabled directly from adjust_link function
without any HW interrogation,
- removing this option, the RX & TX will only be enabled/disabled after
HW interrogation. The HW check is made through the LMON pin in PSR
register which specifies AVB_LINK signal value (0 - at low level;
1 - at high level).
In conclusion, the present change is also a safety improvement because
it removes the "renesas,no-ether-link" option leading to a proper way
of detecting the link state based on HW interrogation and not on
software heuristic.
Fixes: dc36965a8905 ("arm64: dts: r8a7796: salvator-x: Enable EthernetAVB")
Fixes: 6fa501c549aa ("arm64: dts: r8a7795: enable EthernetAVB on Salvator-X")
Signed-off-by: Bogdan Mirea <Bogdan-Stefan_Mirea@mentor.com>
Signed-off-by: Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/salvator-common.dtsi b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
index a298df74ca6c..dbe2648649db 100644
--- a/arch/arm64/boot/dts/renesas/salvator-common.dtsi
+++ b/arch/arm64/boot/dts/renesas/salvator-common.dtsi
@@ -255,7 +255,6 @@
&avb {
pinctrl-0 = <&avb_pins>;
pinctrl-names = "default";
- renesas,no-ether-link;
phy-handle = <&phy0>;
status = "okay";
--
2.11.0
^ permalink raw reply related
* [GIT PULL] Renesas ARM Based SoC Fixes for v4.15
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these Renesas ARM based SoC fixes for v4.15.
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-fixes-for-v4.15
for you to fetch changes up to 7d2901f809c110bd9a261e879d59efe62e3bc758:
arm64: dts: renesas: ulcb: Remove renesas, no-ether-link property (2017-12-22 09:39:17 +0100)
----------------------------------------------------------------
Renesas ARM Based SoC Fixes for v4.15
Vladimir Zapolskiy says:
The present change is a bug fix for AVB link iteratively up/down.
Steps to reproduce:
- start AVB TX stream (Using aplay via MSE),
- disconnect+reconnect the eth cable,
- after a reconnection the eth connection goes iteratively up/down
without user interaction,
- this may heal after some seconds or even stay for minutes.
As the documentation specifies, the "renesas,no-ether-link" option
should be used when a board does not provide a proper AVB_LINK signal.
There is no need for this option enabled on RCAR H3/M3 Salvator-X/XS
and ULCB starter kits since the AVB_LINK is correctly handled by HW.
Choosing to keep or remove the "renesas,no-ether-link" option will
have impact on the code flow in the following ways:
- keeping this option enabled may lead to unexpected behavior since
the RX & TX are enabled/disabled directly from adjust_link function
without any HW interrogation,
- removing this option, the RX & TX will only be enabled/disabled after
HW interrogation. The HW check is made through the LMON pin in PSR
register which specifies AVB_LINK signal value (0 - at low level;
1 - at high level).
In conclusion, the change is also a safety improvement because it
removes the "renesas,no-ether-link" option leading to a proper way
of detecting the link state based on HW interrogation and not on
software heuristic.
Note that DTS files for V3M Starter Kit, Draak and Eagle boards
contain the same property, the files are untouched due to unavailable
schematics to verify if the fix applies to these boards as well.
----------------------------------------------------------------
Bogdan Mirea (2):
arm64: dts: renesas: salvator-x: Remove renesas, no-ether-link property
arm64: dts: renesas: ulcb: Remove renesas, no-ether-link property
arch/arm64/boot/dts/renesas/salvator-common.dtsi | 1 -
arch/arm64/boot/dts/renesas/ulcb.dtsi | 1 -
2 files changed, 2 deletions(-)
^ permalink raw reply
* [PATCH 37/37] ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Add the missing clock to CA7 CPU1 node.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Chris Paterson <Chris.Paterson2@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 835a2821477b..ae918e9cce21 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -84,6 +84,7 @@
compatible = "arm,cortex-a7";
reg = <1>;
clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
power-domains = <&sysc R8A7745_PD_CA7_CPU1>;
next-level-cache = <&L2_CA7>;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 36/37] ARM: dts: iwg22d-sodimm: Sound DMA support via DVC on DTS
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
DMA transfer uses DVC
DMA DMApp
[MEM] -> [SRC] -> [DVC] -> [SSIU] -> [SSI]
DMA DMApp
[MEM] <- [DVC] <- [SRC] <- [SSIU] <- [SSI]
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 2cac57c7c44d..a4058f4cfbcd 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -8,6 +8,29 @@
* kind, whether express or implied.
*/
+/*
+ * SSI-SGTL5000
+ *
+ * This command is required when Playback/Capture
+ *
+ * amixer set "DVC Out" 100%
+ * amixer set "DVC In" 100%
+ *
+ * You can use Mute
+ *
+ * amixer set "DVC Out Mute" on
+ * amixer set "DVC In Mute" on
+ *
+ * You can use Volume Ramp
+ *
+ * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
+ * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
+ * amixer set "DVC Out Ramp" on
+ * aplay xxx.wav &
+ * amixer set "DVC Out" 80% // Volume Down
+ * amixer set "DVC Out" 100% // Volume Up
+ */
+
/dts-v1/;
#include "r8a7745-iwg22m.dtsi"
@@ -183,8 +206,8 @@
rcar_sound,dai {
dai0 {
- playback = <&ssi3 &src3>;
- capture = <&ssi4 &src4>;
+ playback = <&ssi3 &src3 &dvc0>;
+ capture = <&ssi4 &src4 &dvc1>;
};
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 35/37] ARM: dts: iwg22d-sodimm: Sound DMA support via SRC on DTS
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
DMA transfer to/from SRC
DMA DMApp
[MEM] -> [SRC] -> [SSIU] -> [SSI]
DMA DMApp
[MEM] <- [SRC] <- [SSIU] <- [SSI]
Current sound driver is supporting SSI/SRC random connection.
So, this patch is trying
SSI3 -> SRC3
SSI4 <- SRC4
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 0f880c1e7afa..2cac57c7c44d 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -183,8 +183,8 @@
rcar_sound,dai {
dai0 {
- playback = <&ssi3>;
- capture = <&ssi4>;
+ playback = <&ssi3 &src3>;
+ capture = <&ssi4 &src4>;
};
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 34/37] ARM: dts: iwg22d-sodimm: Sound DMA support via BUSIF on DTS
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
DMA transfer to/from SSIU
DMA
[MEM] -> [SSIU] -> [SSI]
DMA
[MEM] <- [SSIU] <- [SSI]
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index a9ba46d804bc..0f880c1e7afa 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -206,12 +206,7 @@
status = "okay";
};
-&ssi3 {
- no-busif;
-};
-
&ssi4 {
- no-busif;
shared-pin;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 33/37] ARM: dts: iwg22d-sodimm: Sound DMA support on DTS
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
DMA transfer to/from SSI
DMA
[MEM] -> [SSI]
DMA
[MEM] <- [SSI]
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index b6521da8b766..a9ba46d804bc 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -207,11 +207,11 @@
};
&ssi3 {
- pio-transfer;
+ no-busif;
};
&ssi4 {
- pio-transfer;
+ no-busif;
shared-pin;
};
--
2.11.0
^ permalink raw reply related
* [PATCH 32/37] ARM: dts: iwg22d-sodimm: Sound PIO support
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Enable sound PIO support on carrier board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 46 +++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 5d4b7d203f8d..b6521da8b766 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -32,6 +32,21 @@
clock-frequency = <26000000>;
};
+ rsnd_sgtl5000: sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&sndcodec>;
+ simple-audio-card,frame-master = <&sndcodec>;
+
+ sndcpu: simple-audio-card,cpu {
+ sound-dai = <&rcar_sound>;
+ };
+
+ sndcodec: simple-audio-card,codec {
+ sound-dai = <&sgtl5000>;
+ };
+ };
+
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@@ -141,6 +156,11 @@
power-source = <3300>;
};
+ sound_pins: sound {
+ groups = "ssi34_ctrl", "ssi3_data", "ssi4_data";
+ function = "ssi";
+ };
+
usb0_pins: usb0 {
groups = "usb0";
function = "usb0";
@@ -152,6 +172,23 @@
};
};
+&rcar_sound {
+ pinctrl-0 = <&sound_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /* Single DAI */
+
+ #sound-dai-cells = <0>;
+
+ rcar_sound,dai {
+ dai0 {
+ playback = <&ssi3>;
+ capture = <&ssi4>;
+ };
+ };
+};
+
&scif4 {
pinctrl-0 = <&scif4_pins>;
pinctrl-names = "default";
@@ -169,6 +206,15 @@
status = "okay";
};
+&ssi3 {
+ pio-transfer;
+};
+
+&ssi4 {
+ pio-transfer;
+ shared-pin;
+};
+
&usbphy {
status = "okay";
};
--
2.11.0
^ permalink raw reply related
* [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.16
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi Olof, Hi Kevin, Hi Arnd,
Please consider these second round of Renesas ARM based SoC DT updates for
v4.16.
This pull request is based on the previous round of
such requests, tagged as renesas-dt-for-v4.16,
which you have already pulled.
The following changes since commit 7f32eddb81ecc06131a643babe2d0f961fbd7f08:
ARM: dts: alt: Convert to named i2c-gpio bindings (2017-12-04 09:34:53 +0100)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-dt2-for-v4.16
for you to fetch changes up to 5b062010675b3d74c9a6c6896e2becf932a4ca74:
ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core (2017-12-22 09:24:00 +0100)
----------------------------------------------------------------
Second Round of Renesas ARM Based SoC DT Updates for v4.16
* r8a7745 (RZ/G1E) SoC
- Enable SMP
Fabrizio Castro says "Add DT node for the Advanced Power Management
Unit (APMU), add the second CPU core, and use "renesas,apmu" as
"enable-method"."
* r8a7743 (RZ/G1M) SoC
- Add node for thermal sensor module with thermal-zone support
* r8a7743 (RZ/G1M) and r8a7745 (RZ/G1E) SoCs
- Add:
+ Renesas Core Match Timer (CMT) support
+ Renesas Timer Pulse Unit PWM Controller (TPU) support
+ Renesas PWM Timer Controller (PWM) support
* r8a7743 (RZ/G1M) iW-RainboW-G20D-Qseven and
r8a7745 (RZ/G1E) iW-RainboW-G22D development platforms
- Add sound support
* r8a7743 (RZ/G1M), r8a7745 (RZ/G1E) and r8a7792 (R-Car V2H) SoCs
- Allow DTBs of boards of these SoCs to build without any warnings when
compiled with W=1 using gcc-linaro-5.4.1-2017.05
+ Move nodes which have no reg property out of bus, they don't belong there
+ Also sort sub-nodes of root node to allow for easier maintenance
* r8a7790 (R-Car H2), r8a7791 (R-Car M2-W) and r8a7793 (R-Car M2-N) SoCs
- Correct critical CPU temperature
Chris Paterson says "The current R-Car Gen2 device trees define the CPU
critical temperature as 115?C.
The R-Car hardware manuals state that Tc = ?40?C to +105?C. The thermal
sensor has an accuracy of ?5?C and there can be a temperature
difference of 1 or 2 degrees between Tjmax and the thermal sensor due
to the location of the latter.
This means that 95?C is a safer value to use.
This value should also apply to r8a7792 but thermal sensor support has
not been added yet."
* r8a7740 (R-Mobile A1) SoC
- Correct TPU register block size
Geert Uytterhoven says "The Timer Pulse Unit has registers that lie
outside the declared register block. Enlarge the register block size to
fix this.
This was probably based on the old platform code, which also assumed a
register block size of 0x100."
----------------------------------------------------------------
Biju Das (20):
ARM: dts: r8a7743: Add audio clocks
ARM: dts: r8a7743: Add audio DMAC support
ARM: dts: r8a7743: Add sound support
ARM: dts: r8a7743: Add thermal device to DT
ARM: dts: iwg20d-q7-common: Enable SGTL5000 audio codec
ARM: dts: iwg20d-q7-common: Sound PIO support
ARM: dts: iwg20d-q7-common: Sound DMA support on DTS
ARM: dts: iwg20d-q7-common: Sound DMA support via BUSIF on DTS
ARM: dts: iwg20d-q7-common: Sound DMA support via SRC on DTS
ARM: dts: iwg20d-q7-common: Sound DMA support via DVC on DTS
ARM: dts: r8a7745: Add audio clocks
ARM: dts: r8a7745: Add audio DMAC support
ARM: dts: r8a7745: Add sound support
ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec
ARM: dts: iwg22d-sodimm: Sound PIO support
ARM: dts: iwg22d-sodimm: Sound DMA support on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via BUSIF on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via SRC on DTS
ARM: dts: iwg22d-sodimm: Sound DMA support via DVC on DTS
ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core
Chris Paterson (3):
ARM: dts: r8a7790: Correct critical CPU temperature
ARM: dts: r8a7791: Correct critical CPU temperature
ARM: dts: r8a7793: Correct critical CPU temperature
Fabrizio Castro (7):
ARM: dts: r8a7745: Add APMU node and second CPU core
ARM: dts: r8a7743: Add PWM SoC support
ARM: dts: r8a7743: Add TPU support
ARM: dts: r8a7745: Add PWM SoC support
ARM: dts: r8a7745: Add TPU support
ARM: dts: r8a7743: Add CMT SoC specific support
ARM: dts: r8a7745: Add CMT SoC specific support
Geert Uytterhoeven (1):
ARM: dts: r8a7740: Correct TPU register block size
Simon Horman (6):
ARM: dts: r8a7745: sort root sub-nodes alphabetically
ARM: dts: r8a7745: move timer node out of bus
ARM: dts: r8a7792: sort root sub-nodes alphabetically
ARM: dts: r8a7792: move timer node out of bus
ARM: dts: r8a7743: sort root sub-nodes alphabetically
ARM: dts: r8a7743: move timer and thermal-zones nodes out of bus
arch/arm/boot/dts/iwg20d-q7-common.dtsi | 88 +++++
arch/arm/boot/dts/r8a7740.dtsi | 2 +-
arch/arm/boot/dts/r8a7743.dtsi | 486 +++++++++++++++++++++++++---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 92 ++++++
arch/arm/boot/dts/r8a7745.dtsi | 421 ++++++++++++++++++++++--
arch/arm/boot/dts/r8a7790.dtsi | 2 +-
arch/arm/boot/dts/r8a7791.dtsi | 2 +-
arch/arm/boot/dts/r8a7792.dtsi | 64 ++--
arch/arm/boot/dts/r8a7793.dtsi | 2 +-
9 files changed, 1051 insertions(+), 108 deletions(-)
^ permalink raw reply
* [PATCH 31/37] ARM: dts: iwg22d-sodimm: Enable SGTL5000 audio codec
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
This patch enables SGTL5000 audio codec on the carrier board.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts | 28 ++++++++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
index 39ce7e7101c7..5d4b7d203f8d 100644
--- a/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
+++ b/arch/arm/boot/dts/r8a7745-iwg22d-sodimm.dts
@@ -26,6 +26,12 @@
stdout-path = "serial3:115200n8";
};
+ audio_clock: audio_clock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ };
+
vccq_sdhi0: regulator-vccq-sdhi0 {
compatible = "regulator-gpio";
@@ -80,6 +86,23 @@
pinctrl-names = "default";
};
+&i2c5 {
+ pinctrl-0 = <&i2c5_pins>;
+ pinctrl-names = "default";
+
+ status = "okay";
+ clock-frequency = <400000>;
+
+ sgtl5000: codec at a {
+ compatible = "fsl,sgtl5000";
+ #sound-dai-cells = <0>;
+ reg = <0x0a>;
+ clocks = <&audio_clock>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ };
+};
+
&pci1 {
status = "okay";
pinctrl-0 = <&usb1_pins>;
@@ -102,6 +125,11 @@
function = "hscif1";
};
+ i2c5_pins: i2c5 {
+ groups = "i2c5_b";
+ function = "i2c5";
+ };
+
scif4_pins: scif4 {
groups = "scif4_data_b";
function = "scif4";
--
2.11.0
^ permalink raw reply related
* [PATCH 30/37] ARM: dts: r8a7745: Add sound support
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Define the generic r8a7745(RZ/G1E) part of the sound device node.
This patch is based on the r8a7794 sound work by Sergei Shtylyov.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 180 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 180 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index d9488a116236..835a2821477b 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -1293,6 +1293,186 @@
resets = <&cpg 915>;
status = "disabled";
};
+
+ rcar_sound: sound at ec500000 {
+ /*
+ * #sound-dai-cells is required
+ *
+ * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
+ * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
+ */
+ compatible = "renesas,rcar_sound-r8a7745",
+ "renesas,rcar_sound-gen2";
+ reg = <0 0xec500000 0 0x1000>, /* SCU */
+ <0 0xec5a0000 0 0x100>, /* ADG */
+ <0 0xec540000 0 0x1000>, /* SSIU */
+ <0 0xec541000 0 0x280>, /* SSI */
+ <0 0xec740000 0 0x200>; /* Audio DMAC peri peri */
+ reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
+
+ clocks = <&cpg CPG_MOD 1005>,
+ <&cpg CPG_MOD 1006>, <&cpg CPG_MOD 1007>,
+ <&cpg CPG_MOD 1008>, <&cpg CPG_MOD 1009>,
+ <&cpg CPG_MOD 1010>, <&cpg CPG_MOD 1011>,
+ <&cpg CPG_MOD 1012>, <&cpg CPG_MOD 1013>,
+ <&cpg CPG_MOD 1014>, <&cpg CPG_MOD 1015>,
+ <&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
+ <&cpg CPG_MOD 1027>, <&cpg CPG_MOD 1028>,
+ <&cpg CPG_MOD 1029>, <&cpg CPG_MOD 1030>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1021>, <&cpg CPG_MOD 1020>,
+ <&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
+ <&audio_clka>, <&audio_clkb>, <&audio_clkc>,
+ <&cpg CPG_CORE R8A7745_CLK_M2>;
+ clock-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0",
+ "src.6", "src.5", "src.4", "src.3",
+ "src.2", "src.1",
+ "ctu.0", "ctu.1",
+ "mix.0", "mix.1",
+ "dvc.0", "dvc.1",
+ "clk_a", "clk_b", "clk_c", "clk_i";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 1005>,
+ <&cpg 1006>, <&cpg 1007>, <&cpg 1008>,
+ <&cpg 1009>, <&cpg 1010>, <&cpg 1011>,
+ <&cpg 1012>, <&cpg 1013>, <&cpg 1014>,
+ <&cpg 1015>;
+ reset-names = "ssi-all",
+ "ssi.9", "ssi.8", "ssi.7", "ssi.6",
+ "ssi.5", "ssi.4", "ssi.3", "ssi.2",
+ "ssi.1", "ssi.0";
+
+ status = "disabled";
+
+ rcar_sound,dvc {
+ dvc0: dvc-0 {
+ dmas = <&audma0 0xbc>;
+ dma-names = "tx";
+ };
+ dvc1: dvc-1 {
+ dmas = <&audma0 0xbe>;
+ dma-names = "tx";
+ };
+ };
+
+ rcar_sound,mix {
+ mix0: mix-0 { };
+ mix1: mix-1 { };
+ };
+
+ rcar_sound,ctu {
+ ctu00: ctu-0 { };
+ ctu01: ctu-1 { };
+ ctu02: ctu-2 { };
+ ctu03: ctu-3 { };
+ ctu10: ctu-4 { };
+ ctu11: ctu-5 { };
+ ctu12: ctu-6 { };
+ ctu13: ctu-7 { };
+ };
+
+ rcar_sound,src {
+ src-0 {
+ status = "disabled";
+ };
+ src1: src-1 {
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x87>, <&audma0 0x9c>;
+ dma-names = "rx", "tx";
+ };
+ src2: src-2 {
+ interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x89>, <&audma0 0x9e>;
+ dma-names = "rx", "tx";
+ };
+ src3: src-3 {
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8b>, <&audma0 0xa0>;
+ dma-names = "rx", "tx";
+ };
+ src4: src-4 {
+ interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8d>, <&audma0 0xb0>;
+ dma-names = "rx", "tx";
+ };
+ src5: src-5 {
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x8f>, <&audma0 0xb2>;
+ dma-names = "rx", "tx";
+ };
+ src6: src-6 {
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x91>, <&audma0 0xb4>;
+ dma-names = "rx", "tx";
+ };
+ };
+
+ rcar_sound,ssi {
+ ssi0: ssi-0 {
+ interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x01>, <&audma0 0x02>,
+ <&audma0 0x15>, <&audma0 0x16>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi1: ssi-1 {
+ interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x03>, <&audma0 0x04>,
+ <&audma0 0x49>, <&audma0 0x4a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi2: ssi-2 {
+ interrupts = <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x05>, <&audma0 0x06>,
+ <&audma0 0x63>, <&audma0 0x64>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi3: ssi-3 {
+ interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x07>, <&audma0 0x08>,
+ <&audma0 0x6f>, <&audma0 0x70>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi4: ssi-4 {
+ interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x09>, <&audma0 0x0a>,
+ <&audma0 0x71>, <&audma0 0x72>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi5: ssi-5 {
+ interrupts = <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0b>, <&audma0 0x0c>,
+ <&audma0 0x73>, <&audma0 0x74>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi6: ssi-6 {
+ interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0d>, <&audma0 0x0e>,
+ <&audma0 0x75>, <&audma0 0x76>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi7: ssi-7 {
+ interrupts = <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x0f>, <&audma0 0x10>,
+ <&audma0 0x79>, <&audma0 0x7a>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi8: ssi-8 {
+ interrupts = <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x11>, <&audma0 0x12>,
+ <&audma0 0x7b>, <&audma0 0x7c>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ ssi9: ssi-9 {
+ interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>;
+ dmas = <&audma0 0x13>, <&audma0 0x14>,
+ <&audma0 0x7d>, <&audma0 0x7e>;
+ dma-names = "rx", "tx", "rxu", "txu";
+ };
+ };
+ };
};
timer {
--
2.11.0
^ permalink raw reply related
* [PATCH 29/37] ARM: dts: r8a7745: Add audio DMAC support
From: Simon Horman @ 2017-12-22 10:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
From: Biju Das <biju.das@bp.renesas.com>
Instantiate the audio DMA controller on the r8a7745 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm/boot/dts/r8a7745.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi
index 6d085f004721..d9488a116236 100644
--- a/arch/arm/boot/dts/r8a7745.dtsi
+++ b/arch/arm/boot/dts/r8a7745.dtsi
@@ -397,6 +397,37 @@
dma-channels = <15>;
};
+ audma0: dma-controller at ec700000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xec700000 0 0x10000>;
+ interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12";
+ clocks = <&cpg CPG_MOD 502>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ resets = <&cpg 502>;
+ #dma-cells = <1>;
+ dma-channels = <13>;
+ };
+
usb_dmac0: dma-controller at e65a0000 {
compatible = "renesas,r8a7745-usb-dmac",
"renesas,usb-dmac";
--
2.11.0
^ permalink raw reply related
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