* [PATCH] ARM: dts: imx51-zii-rdu1: Add missing #phy-cells to usb-nop-xceiv
From: Fabio Estevam @ 2017-12-26 18:04 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
Commit 915fbe59cbf2fe6 ("ARM: dts: imx: Add missing #phy-cells to
usb-nop-xceiv") missed to update imx51-zii-rdu1.dts probably due to a
merge timing issue, so add #phy-cells here too.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx51-zii-rdu1.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts
index 70fdcdd..5306b78 100644
--- a/arch/arm/boot/dts/imx51-zii-rdu1.dts
+++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts
@@ -271,6 +271,7 @@
clock-names = "main_clk";
reset-gpios = <&gpio4 8 GPIO_ACTIVE_LOW>;
vcc-supply = <&vusb_reg>;
+ #phy-cells = <0>;
};
usbh2phy: usbphy2 {
@@ -281,6 +282,7 @@
clock-names = "main_clk";
reset-gpios = <&gpio4 7 GPIO_ACTIVE_LOW>;
vcc-supply = <&vusb_reg>;
+ #phy-cells = <0>;
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH] ARM: dts: imx: Add memory node unit name
From: Fabio Estevam @ 2017-12-26 18:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAM4PwSVzVn3=wWpFohw2q23Oiwp1FimCkdHPq=BfG-QzuuPtfQ@mail.gmail.com>
Hi Rob,
On Thu, Dec 21, 2017 at 12:26 PM, Marco Franchi <marcofrk@gmail.com> wrote:
> Hi Lothar,
>
> 2017-12-21 6:07 GMT-02:00 Lothar Wa?mann <LW@karo-electronics.de>:
>> Hi,
>>
>> On Wed, 6 Dec 2017 13:59:49 -0200 Marco Franchi wrote:
>>> Fix the following warnings from dtc by adding the unit name to memory
>>> nodes:
>>>
>>> Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
>>>
>>> Converted using the following command:
>>>
>>> perl -p0777i -e 's/memory \{\n\t\treg = \<0x+([0-9a-f])/memory\@$1$\0000000 \{\n\t\treg = <0x$1/m' `find ./arch/arm/boot/dts -name "imx*"`
>>>
>>> The files below were manually fixed:
>>> -imx1-ads.dts
>>> -imx1-apf9328.dts
>>>
>> The imx*.dtsi files all have this:
>> | memory { device_type = "memory"; reg = <0 0>; };
>> Thus you will end up with a 'memory' node with a reg = <0 0> entry and
>> an additional 'memory at ...' node with the correct 'reg' values.
>
> You are right. The .dtb files were composed by two different memory nodes.
> Do you have some recommendation to take off this specific warning?
Currently the only dtc warnings we have with imx_v6_v7_defconfig are:
Warning (unit_address_vs_reg): Node /memory has a reg or ranges
property, but no unit name
What is the recommended way to fix these warnings?
Thanks
^ permalink raw reply
* [PATCH] pinctrl: samsung: Add SPDX license identifiers
From: Krzysztof Kozlowski @ 2017-12-26 18:09 UTC (permalink / raw)
To: linux-arm-kernel
Replace GPL license statements with SPDX GPL-2.0+ license identifiers.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/pinctrl/samsung/Kconfig | 1 +
drivers/pinctrl/samsung/pinctrl-exynos-arm.c | 33 ++++++++++-------------
drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 33 ++++++++++-------------
drivers/pinctrl/samsung/pinctrl-exynos.c | 33 ++++++++++-------------
drivers/pinctrl/samsung/pinctrl-exynos.h | 6 +----
drivers/pinctrl/samsung/pinctrl-exynos5440.c | 21 ++++++---------
drivers/pinctrl/samsung/pinctrl-s3c24xx.c | 23 +++++++---------
drivers/pinctrl/samsung/pinctrl-s3c64xx.c | 27 ++++++++-----------
drivers/pinctrl/samsung/pinctrl-samsung.c | 37 +++++++++++---------------
drivers/pinctrl/samsung/pinctrl-samsung.h | 6 +----
10 files changed, 89 insertions(+), 131 deletions(-)
diff --git a/drivers/pinctrl/samsung/Kconfig b/drivers/pinctrl/samsung/Kconfig
index ecfb90059eeb..11b5eeb14c4a 100644
--- a/drivers/pinctrl/samsung/Kconfig
+++ b/drivers/pinctrl/samsung/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
#
# Samsung Pin control drivers
#
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
index 071084d3ee9c..c32399faff57 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm.c
@@ -1,22 +1,17 @@
-/*
- * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- * Copyright (c) 2012 Linaro Ltd
- * http://www.linaro.org
- *
- * Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This file contains the Samsung Exynos specific information required by the
- * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
- * external gpio and wakeup interrupt support.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
+//
+// Copyright (c) 2012 Samsung Electronics Co., Ltd.
+// http://www.samsung.com
+// Copyright (c) 2012 Linaro Ltd
+// http://www.linaro.org
+//
+// Author: Thomas Abraham <thomas.ab@samsung.com>
+//
+// This file contains the Samsung Exynos specific information required by the
+// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
+// external gpio and wakeup interrupt support.
#include <linux/device.h>
#include <linux/of_address.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
index 08e9fdb58fd2..fc8f7833bec0 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c
@@ -1,22 +1,17 @@
-/*
- * Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
- * with eint support.
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- * Copyright (c) 2012 Linaro Ltd
- * http://www.linaro.org
- * Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This file contains the Samsung Exynos specific information required by the
- * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
- * external gpio and wakeup interrupt support.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Exynos ARMv8 specific support for Samsung pinctrl/gpiolib driver
+// with eint support.
+//
+// Copyright (c) 2012 Samsung Electronics Co., Ltd.
+// http://www.samsung.com
+// Copyright (c) 2012 Linaro Ltd
+// http://www.linaro.org
+// Copyright (c) 2017 Krzysztof Kozlowski <krzk@kernel.org>
+//
+// This file contains the Samsung Exynos specific information required by the
+// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
+// external gpio and wakeup interrupt support.
#include <linux/slab.h>
#include <linux/soc/samsung/exynos-regs-pmu.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/samsung/pinctrl-exynos.c
index c8d0de7ea160..0a625a64ff5d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.c
@@ -1,22 +1,17 @@
-/*
- * Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- * Copyright (c) 2012 Linaro Ltd
- * http://www.linaro.org
- *
- * Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This file contains the Samsung Exynos specific information required by the
- * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
- * external gpio and wakeup interrupt support.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
+//
+// Copyright (c) 2012 Samsung Electronics Co., Ltd.
+// http://www.samsung.com
+// Copyright (c) 2012 Linaro Ltd
+// http://www.linaro.org
+//
+// Author: Thomas Abraham <thomas.ab@samsung.com>
+//
+// This file contains the Samsung Exynos specific information required by the
+// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
+// external gpio and wakeup interrupt support.
#include <linux/device.h>
#include <linux/interrupt.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/samsung/pinctrl-exynos.h
index 7639b926c5c1..abd43aa7eb0d 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos.h
+++ b/drivers/pinctrl/samsung/pinctrl-exynos.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Exynos specific definitions for Samsung pinctrl and gpiolib driver.
*
@@ -10,11 +11,6 @@
* pinctrl/gpiolib interface drivers.
*
* Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
#ifndef __PINCTRL_SAMSUNG_EXYNOS_H
diff --git a/drivers/pinctrl/samsung/pinctrl-exynos5440.c b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
index 32a3a9fd65c4..3d8d5e812839 100644
--- a/drivers/pinctrl/samsung/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/samsung/pinctrl-exynos5440.c
@@ -1,16 +1,11 @@
-/*
- * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
- *
- * Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// pin-controller/pin-mux/pin-config/gpio-driver for Samsung's EXYNOS5440 SoC.
+//
+// Author: Thomas Abraham <thomas.ab@samsung.com>
+//
+// Copyright (c) 2012 Samsung Electronics Co., Ltd.
+// http://www.samsung.com
#include <linux/init.h>
#include <linux/platform_device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
index edf27264b603..10187cb0e9b9 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c24xx.c
@@ -1,17 +1,12 @@
-/*
- * S3C24XX specific support for Samsung pinctrl/gpiolib driver.
- *
- * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This file contains the SamsungS3C24XX specific information required by the
- * Samsung pinctrl/gpiolib driver. It also includes the implementation of
- * external gpio and wakeup interrupt support.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// S3C24XX specific support for Samsung pinctrl/gpiolib driver.
+//
+// Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
+//
+// This file contains the SamsungS3C24XX specific information required by the
+// Samsung pinctrl/gpiolib driver. It also includes the implementation of
+// external gpio and wakeup interrupt support.
#include <linux/init.h>
#include <linux/device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
index e63663b32907..679628ac4b31 100644
--- a/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
+++ b/drivers/pinctrl/samsung/pinctrl-s3c64xx.c
@@ -1,19 +1,14 @@
-/*
- * S3C64xx specific support for pinctrl-samsung driver.
- *
- * Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
- *
- * Based on pinctrl-exynos.c, please see the file for original copyrights.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This file contains the Samsung S3C64xx specific information required by the
- * the Samsung pinctrl/gpiolib driver. It also includes the implementation of
- * external gpio and wakeup interrupt support.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// S3C64xx specific support for pinctrl-samsung driver.
+//
+// Copyright (c) 2013 Tomasz Figa <tomasz.figa@gmail.com>
+//
+// Based on pinctrl-exynos.c, please see the file for original copyrights.
+//
+// This file contains the Samsung S3C64xx specific information required by the
+// the Samsung pinctrl/gpiolib driver. It also includes the implementation of
+// external gpio and wakeup interrupt support.
#include <linux/init.h>
#include <linux/device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/samsung/pinctrl-samsung.c
index e04f7fe0a65d..da58e4554137 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.c
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.c
@@ -1,24 +1,19 @@
-/*
- * pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
- *
- * Copyright (c) 2012 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- * Copyright (c) 2012 Linaro Ltd
- * http://www.linaro.org
- *
- * Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This driver implements the Samsung pinctrl driver. It supports setting up of
- * pinmux and pinconf configurations. The gpiolib interface is also included.
- * External interrupt (gpio and wakeup) support are not included in this driver
- * but provides extensions to which platform specific implementation of the gpio
- * and wakeup interrupts can be hooked to.
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
+//
+// Copyright (c) 2012 Samsung Electronics Co., Ltd.
+// http://www.samsung.com
+// Copyright (c) 2012 Linaro Ltd
+// http://www.linaro.org
+//
+// Author: Thomas Abraham <thomas.ab@samsung.com>
+//
+// This driver implements the Samsung pinctrl driver. It supports setting up of
+// pinmux and pinconf configurations. The gpiolib interface is also included.
+// External interrupt (gpio and wakeup) support are not included in this driver
+// but provides extensions to which platform specific implementation of the gpio
+// and wakeup interrupts can be hooked to.
#include <linux/init.h>
#include <linux/platform_device.h>
diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/samsung/pinctrl-samsung.h
index 9af07af6cad6..e204f609823b 100644
--- a/drivers/pinctrl/samsung/pinctrl-samsung.h
+++ b/drivers/pinctrl/samsung/pinctrl-samsung.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* pin-controller/pin-mux/pin-config/gpio-driver for Samsung's SoC's.
*
@@ -7,11 +8,6 @@
* http://www.linaro.org
*
* Author: Thomas Abraham <thomas.ab@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
*/
#ifndef __PINCTRL_SAMSUNG_H
--
2.7.4
^ permalink raw reply related
* [PATCH 10/11 v2] ARM: s3c24xx/s3c64xx: constify gpio_led
From: arvindY @ 2017-12-26 18:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJKOXPdz+SZVxJ2y_aWdZsCjujhPAqMa3O-bqenOnk-iygow_w@mail.gmail.com>
Hi,
On Tuesday 26 December 2017 11:12 PM, Krzysztof Kozlowski wrote:
> On Tue, Dec 26, 2017 at 7:37 AM, Arvind Yadav <arvind.yadav.cs@gmail.com> wrote:
>> Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
> Please write one-sentence long, easy to understand message describing
> the change.
>
> Best regards,
> Krzysztof
Thanks for review comment. I will add.
>
>> ---
>> changes in v2:
>> The GPIO LED driver can be built as a module, it can
>> be loaded after the init sections have gone away.
>> So removed '__initconst'.
>>
>> arch/arm/mach-s3c24xx/mach-h1940.c | 2 +-
>> arch/arm/mach-s3c24xx/mach-rx1950.c | 2 +-
>> arch/arm/mach-s3c64xx/mach-hmt.c | 2 +-
>> arch/arm/mach-s3c64xx/mach-smartq5.c | 2 +-
>> arch/arm/mach-s3c64xx/mach-smartq7.c | 2 +-
>> arch/arm/mach-s3c64xx/mach-smdk6410.c | 2 +-
>> 6 files changed, 6 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/arm/mach-s3c24xx/mach-h1940.c b/arch/arm/mach-s3c24xx/mach-h1940.c
>> index 7ed7861..6a3e0e6 100644
>> --- a/arch/arm/mach-s3c24xx/mach-h1940.c
>> +++ b/arch/arm/mach-s3c24xx/mach-h1940.c
>> @@ -413,7 +413,7 @@ int h1940_led_blink_set(struct gpio_desc *desc, int state,
>> }
>> EXPORT_SYMBOL(h1940_led_blink_set);
>>
>> -static struct gpio_led h1940_leds_desc[] = {
>> +static const struct gpio_led h1940_leds_desc[] = {
>> {
>> .name = "Green",
>> .default_trigger = "main-battery-full",
>> diff --git a/arch/arm/mach-s3c24xx/mach-rx1950.c b/arch/arm/mach-s3c24xx/mach-rx1950.c
>> index e86ad6a..97bb6a5 100644
>> --- a/arch/arm/mach-s3c24xx/mach-rx1950.c
>> +++ b/arch/arm/mach-s3c24xx/mach-rx1950.c
>> @@ -295,7 +295,7 @@ static int rx1950_led_blink_set(struct gpio_desc *desc, int state,
>> return 0;
>> }
>>
>> -static struct gpio_led rx1950_leds_desc[] = {
>> +static const struct gpio_led rx1950_leds_desc[] = {
>> {
>> .name = "Green",
>> .default_trigger = "main-battery-full",
>> diff --git a/arch/arm/mach-s3c64xx/mach-hmt.c b/arch/arm/mach-s3c64xx/mach-hmt.c
>> index 59b5531..f8d644f 100644
>> --- a/arch/arm/mach-s3c64xx/mach-hmt.c
>> +++ b/arch/arm/mach-s3c64xx/mach-hmt.c
>> @@ -207,7 +207,7 @@ static struct s3c2410_platform_nand hmt_nand_info = {
>> .ecc_mode = NAND_ECC_SOFT,
>> };
>>
>> -static struct gpio_led hmt_leds[] = {
>> +static const struct gpio_led hmt_leds[] = {
>> { /* left function keys */
>> .name = "left:blue",
>> .gpio = S3C64XX_GPO(12),
>> diff --git a/arch/arm/mach-s3c64xx/mach-smartq5.c b/arch/arm/mach-s3c64xx/mach-smartq5.c
>> index 0972b6c..5a7cd8f 100644
>> --- a/arch/arm/mach-s3c64xx/mach-smartq5.c
>> +++ b/arch/arm/mach-s3c64xx/mach-smartq5.c
>> @@ -35,7 +35,7 @@
>> #include "common.h"
>> #include "mach-smartq.h"
>>
>> -static struct gpio_led smartq5_leds[] = {
>> +static const struct gpio_led smartq5_leds[] = {
>> {
>> .name = "smartq5:green",
>> .active_low = 1,
>> diff --git a/arch/arm/mach-s3c64xx/mach-smartq7.c b/arch/arm/mach-s3c64xx/mach-smartq7.c
>> index 51ac1c6..9de9fc2 100644
>> --- a/arch/arm/mach-s3c64xx/mach-smartq7.c
>> +++ b/arch/arm/mach-s3c64xx/mach-smartq7.c
>> @@ -35,7 +35,7 @@
>> #include "common.h"
>> #include "mach-smartq.h"
>>
>> -static struct gpio_led smartq7_leds[] = {
>> +static const struct gpio_led smartq7_leds[] = {
>> {
>> .name = "smartq7:red",
>> .active_low = 1,
>> diff --git a/arch/arm/mach-s3c64xx/mach-smdk6410.c b/arch/arm/mach-s3c64xx/mach-smdk6410.c
>> index 92ec8c3..be9d98f 100644
>> --- a/arch/arm/mach-s3c64xx/mach-smdk6410.c
>> +++ b/arch/arm/mach-s3c64xx/mach-smdk6410.c
>> @@ -497,7 +497,7 @@ static struct wm8350_platform_data __initdata smdk6410_wm8350_pdata = {
>> #endif
>>
>> #ifdef CONFIG_SMDK6410_WM1192_EV1
>> -static struct gpio_led wm1192_pmic_leds[] = {
>> +static const struct gpio_led wm1192_pmic_leds[] = {
>> {
>> .name = "PMIC:red:power",
>> .gpio = GPIO_BOARD_START + 3,
>> --
>> 2.7.4
>>
^ permalink raw reply
* [PATCH v3 01/11] dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
From: Rob Herring @ 2017-12-26 19:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222122243.25735-2-icenowy@aosc.io>
On Fri, Dec 22, 2017 at 6:22 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> The DE2 CCU is different on A83T and H3 -- the parent of the clocks on
> A83T is PLL_DE but on H3 it's the DE module clock. This is not noticed
> when I develop the DE2 CCU driver.
>
> Fix the binding by using different compatibles for A83T and H3, adding
> notes for the PLL_DE usage on A83T, and change the binding example's
> compatible from A83T to H3 (as it specifies the DE module clock).
>
> Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Please add acks when posting new versions.
Rob
^ permalink raw reply
* [arm:phy 15/66] drivers/net/dsa/mv88e6xxx/global2.h:449: multiple definition of `mv88e6xxx_g2_scratch_gpio_set_ext_smi'
From: kbuild test robot @ 2017-12-26 19:39 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git phy
head: 73c2c610e10e5b83922c0be529c000a9506d0630
commit: 4520555b93f27772482e7e0ae714641633c8bf16 [15/66] net: dsa: mv88e6xxx: Enable external MDIO bus
config: x86_64-randconfig-s1-12270141 (attached as .config)
compiler: gcc-6 (Debian 6.4.0-9) 6.4.0 20171026
reproduce:
git checkout 4520555b93f27772482e7e0ae714641633c8bf16
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
drivers/net/dsa/mv88e6xxx/serdes.o: In function `mv88e6xxx_g2_scratch_gpio_set_ext_smi':
>> drivers/net/dsa/mv88e6xxx/global2.h:449: multiple definition of `mv88e6xxx_g2_scratch_gpio_set_ext_smi'
drivers/net/dsa/mv88e6xxx/chip.o:drivers/net/dsa/mv88e6xxx/global2.h:449: first defined here
vim +449 drivers/net/dsa/mv88e6xxx/global2.h
446
447 int mv88e6xxx_g2_scratch_gpio_set_ext_smi(struct mv88e6xxx_chip *chip,
448 bool external)
> 449 {
450 return -EOPNOTSUPP;
451 }
452
---
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^ permalink raw reply
* [PATCH] ARM: dts: imx7s: Avoid using label in unit address and reg
From: Fabio Estevam @ 2017-12-26 19:59 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
As recommended by Rob Herring [1] labels should not be used in unit address
and reg, so use its real value directly instead.
[1] https://www.spinics.net/lists/devicetree/msg206567.html
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx7s.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index 2ceb37d..9aa2bb9 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -600,9 +600,9 @@
#address-cells = <1>;
#size-cells = <0>;
- pgc_pcie_phy: pgc-power-domain at IMX7_POWER_DOMAIN_PCIE_PHY {
+ pgc_pcie_phy: pgc-power-domain at 1 {
#power-domain-cells = <0>;
- reg = <IMX7_POWER_DOMAIN_PCIE_PHY>;
+ reg = <1>;
power-supply = <®_1p0d>;
};
};
--
2.7.4
^ permalink raw reply related
* [arm:csi-v6 5/15] drivers/media/i2c/imx219.c:1190:37: sparse: cast to restricted __be16
From: kbuild test robot @ 2017-12-26 20:09 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git csi-v6
head: ed3a8e14cfa42d5bb506326186c2092cc69d2899
commit: d63078ff2c761da0b393889c2f909fd379c1fa5b [5/15] media: i2c: imx219 camera driver
reproduce:
# apt-get install sparse
git checkout d63078ff2c761da0b393889c2f909fd379c1fa5b
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
vim +1190 drivers/media/i2c/imx219.c
1086
1087 /*
1088 * The line length in conjunction with the VT clock determines the
1089 * start of transmission of each line on the CSI bus.
1090 *
1091 * The frame length in conjunction with the line length and VT clock
1092 * determines the start of transmission of each frame on the CSI bus.
1093 *
1094 * Note: these two parameters have nothing to do with the pixel array
1095 * addressing parameters.
1096 */
1097 static void imx219_update_frame_size(struct imx219_private *priv)
1098 {
1099 unsigned long vt_pixclk = imx219_get_vt_pixclk(priv);
1100 unsigned long op_sysclk;
1101 unsigned int div, lane_line_bits;
1102 unsigned int line_clk, line_length, line_blank;
1103 unsigned int min_frame_length, frame_length, frame_blank;
1104
1105 /* see comments above, this is definitely wrong */
1106 unsigned int width = be16_to_cpu(priv->params.x_output_size);
1107 unsigned int height = be16_to_cpu(priv->params.y_output_size);
1108
1109 dev_info(priv->root.sd.dev, "%s() for %ux%u %ubpp fi=%u/%u:\n", __func__,
1110 width, height, priv->bits_per_pixel,
1111 priv->frame_interval.numerator,
1112 priv->frame_interval.denominator);
1113
1114 /*
1115 * This works for calculating a working line length, but is
1116 * less than ideal, as we always run the VT block at maximum,
1117 * and wind the output block up to maximum for large widths.
1118 */
1119 lane_line_bits = imx219_calc_lane_line_bits(priv);
1120
1121 line_clk = 2 * vt_pixclk / priv->min_line_length_pck;
1122
1123 dev_info(priv->root.sd.dev, "VT: pixclk=%luHz line=%uHz\n",
1124 vt_pixclk, line_clk);
1125
1126 /* Calculate the required output sysclk */
1127 op_sysclk = line_clk * lane_line_bits;
1128
1129 /*
1130 * Try to find a sysclk divisor that gives us the highest PLL
1131 * speed - otherwise errors seem to occur at the CSI2 receiver:
1132 * i.MX6 CS2 error 2/1 registers = 0x00000120/0x11000113
1133 * - header ecc contains 2 errors
1134 * - crc error on vc0
1135 * - incorrect frame sequence on vc0
1136 * - error matching frame start with frame end on vc0
1137 * - sot sync failed on lane 1
1138 * - sot sync failed on lane 0
1139 * - sot error on lane 1
1140 * - header error detected and corrected on vc0
1141 * Note: docs say 432MHz as the PLL low bound, hardware says 400MHz,
1142 * experimentation with my imx219 is stable at 464MHz but not 456MHz.
1143 */
1144 for (div = priv->pll[PLL_OP].clk[CLK_SYS].max_div;
1145 div > priv->pll[PLL_OP].clk[CLK_SYS].min_div; div--)
1146 if (op_sysclk * div <= priv->pll[PLL_OP].clk[CLK_SYS].max_freq)
1147 break;
1148
1149 priv->op_sys_div = div;
1150 op_sysclk *= div;
1151
1152 dev_info(priv->root.sd.dev, "OP: sysclk=%luHz/%u for %u bits/line/lane\n",
1153 op_sysclk, div, lane_line_bits);
1154
1155 priv->op_mpy = clamp_val(DIV_ROUND_UP(op_sysclk,
1156 priv->pll_ip_freq),
1157 priv->pll[PLL_OP].min_mpy,
1158 priv->pll[PLL_OP].max_mpy);
1159
1160 /* Now calculate the real output sysclk */
1161 op_sysclk = priv->pll_ip_freq * priv->op_mpy / div;
1162
1163 /* ... and the resulting line clock for the output */
1164 line_clk = op_sysclk / lane_line_bits;
1165
1166 dev_info(priv->root.sd.dev, "OP: real sysclk %luHz line %uHz\n",
1167 op_sysclk, line_clk);
1168
1169 /* ... and the final line length */
1170 line_length = clamp_val(DIV_ROUND_UP(2 * vt_pixclk, line_clk),
1171 priv->min_line_length_pck,
1172 priv->max_line_length_pck);
1173
1174 priv->params.line_length = cpu_to_be16(line_length);
1175
1176 /* ... and the final line rate */
1177 line_clk = 2 * vt_pixclk / line_length;
1178
1179 /*
1180 * Calculate the frame length required to give the requested
1181 * frame interval.
1182 */
1183 min_frame_length = imx219_calc_total_lines(priv);
1184 frame_length = div_u64((u64)line_clk * priv->frame_interval.numerator,
1185 priv->frame_interval.denominator);
1186
1187 frame_length = clamp_val(frame_length, min_frame_length,
1188 priv->max_frame_lines);
1189
> 1190 priv->params.frame_length = be16_to_cpu(frame_length);
1191
1192 dev_info(priv->root.sd.dev, "VT: line length %u frame length %u line %uHz\n",
1193 line_length, frame_length, line_clk);
1194
1195
1196
1197 /* See comments above, this is definitely wrong. */
1198 line_blank = line_length - width;
1199 frame_blank = frame_length - height;
1200
1201 v4l2_ctrl_s_ctrl_int64(priv->pixel.ctrls[CTRL_P_PIXEL_RATE],
1202 2 * vt_pixclk);
1203
1204 v4l2_ctrl_modify_range(priv->pixel.ctrls[CTRL_P_HBLANK],
1205 max_t(s32, priv->min_line_length_pck - width,
1206 priv->min_line_blank_pck),
1207 priv->max_line_length_pck - width, 1,
1208 line_blank);
1209 v4l2_ctrl_s_ctrl(priv->pixel.ctrls[CTRL_P_HBLANK], line_blank);
1210
1211 v4l2_ctrl_modify_range(priv->pixel.ctrls[CTRL_P_VBLANK],
1212 max_t(s32, priv->min_frame_lines - height,
1213 priv->min_frame_blank_lines),
1214 priv->max_frame_lines - height, 1, frame_blank);
1215 v4l2_ctrl_s_ctrl(priv->pixel.ctrls[CTRL_P_VBLANK], frame_blank);
1216
1217 imx219_set_exposure_limits(priv);
1218 }
1219
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [RESEND][PATCH 1/4] of: platform: populate /firmware/ node from of_platform_default_populate_init()
From: Bjorn Andersson @ 2017-12-26 21:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1506595562-10592-2-git-send-email-sudeep.holla@arm.com>
On Thu, Sep 28, 2017 at 3:45 AM, Sudeep Holla <sudeep.holla@arm.com> wrote:
> Since "/firmware" does not have its own "compatible" property as it's
> just collection of nodes representing firmware interface, it's sub-nodes
> are not populated during system initialization.
>
> Currently different firmware drivers search the /firmware/ node and
> populate the sub-node devices selectively. Instead we can populate
> the /firmware/ node during init to avoid more drivers continuing to
> populate the devices selectively.
>
> To generalize the solution this patch populates the /firmware/ node
> explicitly from of_platform_default_populate_init().
>
> Cc: Arnd Bergmann <arnd@arndb.de>
> Cc: Rob Herring <robh@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Bjorn Andersson <bjorn.andersson@linaro.org>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
Andy, as you picked patch 2/4 into your v4.16 -next branch we no
longer probe the qcom_scm device, causing various breakage. Can you
please pick this patch as well (it has Rob's ack).
Regards,
Bjorn
> drivers/of/platform.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/of/platform.c b/drivers/of/platform.c
> index ac15d0e3d27d..3a213a6aee89 100644
> --- a/drivers/of/platform.c
> +++ b/drivers/of/platform.c
> @@ -515,6 +515,10 @@ static int __init of_platform_default_populate_init(void)
> of_platform_device_create(node, NULL, NULL);
> }
>
> + node = of_find_node_by_path("/firmware");
> + if (node)
> + of_platform_populate(node, NULL, NULL, NULL);
> +
> /* Populate everything else. */
> of_platform_default_populate(NULL, NULL, NULL);
>
> --
> 2.7.4
>
^ permalink raw reply
* [linux-sunxi] [PATCH v4 1/2] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)
From: Rob Herring @ 2017-12-26 21:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222100008.nmmzwhtmputizn7d@plaes.org>
On Fri, Dec 22, 2017 at 10:00:08AM +0000, Priit Laes wrote:
> On Fri, Dec 22, 2017 at 05:41:29PM +0800, Yong Deng wrote:
> > Add binding documentation for Allwinner V3s CSI.
> >
> > Signed-off-by: Yong Deng <yong.deng@magewell.com>
> > ---
> > .../devicetree/bindings/media/sun6i-csi.txt | 51 ++++++++++++++++++++++
> > 1 file changed, 51 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/media/sun6i-csi.txt
> >
> > diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> > new file mode 100644
> > index 0000000..b5bfe3f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> > @@ -0,0 +1,51 @@
> > +Allwinner V3s Camera Sensor Interface
> > +------------------------------
>
> Not sure whether syntax for these files is proper reStructuredText/Markdown,
> but the underline-ish style expects the title and underline having same length.
The binding files are not rst/md format, but still the comment is just
good style.
Rob
^ permalink raw reply
* [PATCH v4 1/2] dt-bindings: media: Add Allwinner V3s Camera Sensor Interface (CSI)
From: Rob Herring @ 2017-12-26 21:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513935689-35415-1-git-send-email-yong.deng@magewell.com>
On Fri, Dec 22, 2017 at 05:41:29PM +0800, Yong Deng wrote:
> Add binding documentation for Allwinner V3s CSI.
>
> Signed-off-by: Yong Deng <yong.deng@magewell.com>
> ---
> .../devicetree/bindings/media/sun6i-csi.txt | 51 ++++++++++++++++++++++
> 1 file changed, 51 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/media/sun6i-csi.txt
>
> diff --git a/Documentation/devicetree/bindings/media/sun6i-csi.txt b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> new file mode 100644
> index 0000000..b5bfe3f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/sun6i-csi.txt
> @@ -0,0 +1,51 @@
> +Allwinner V3s Camera Sensor Interface
> +------------------------------
> +
> +Required properties:
> + - compatible: value must be "allwinner,sun8i-v3s-csi"
> + - reg: base address and size of the memory-mapped region.
> + - interrupts: interrupt associated to this IP
> + - clocks: phandles to the clocks feeding the CSI
> + * bus: the CSI interface clock
> + * mod: the CSI module clock
> + * ram: the CSI DRAM clock
> + - clock-names: the clock names mentioned above
> + - resets: phandles to the reset line driving the CSI
> +
> +- ports: A ports node with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt.
> + Currently, the driver only support the parallel interface. So, a single port
> + node with one endpoint and parallel bus is supported.
What the driver supports is not relevant. Please document what the h/w
has.
> +
> +Example:
> +
> + csi1: csi at 1cb4000 {
> + compatible = "allwinner,sun8i-v3s-csi";
> + reg = <0x01cb4000 0x1000>;
> + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_CSI>,
> + <&ccu CLK_CSI1_SCLK>,
> + <&ccu CLK_DRAM_CSI>;
> + clock-names = "bus", "mod", "ram";
> + resets = <&ccu RST_BUS_CSI>;
> +
> + port {
> + #address-cells = <1>;
> + #size-cells = <0>;
These are not needed with a single endpoint.
> +
> + /* Parallel bus endpoint */
> + csi1_ep: endpoint {
> + remote-endpoint = <&adv7611_ep>;
> + bus-width = <16>;
> + data-shift = <0>;
> +
> + /* If hsync-active/vsync-active are missing,
> + embedded BT.656 sync is used */
> + hsync-active = <0>; /* Active low */
> + vsync-active = <0>; /* Active low */
> + data-active = <1>; /* Active high */
> + pclk-sample = <1>; /* Rising */
> + };
> + };
> + };
> +
> --
> 1.8.3.1
>
^ permalink raw reply
* [PATCH 1/1] power: reset: remove unused imx-snvs-poweroff driver
From: Rob Herring @ 2017-12-26 21:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513938539-20873-1-git-send-email-aisheng.dong@nxp.com>
On Fri, Dec 22, 2017 at 06:28:59PM +0800, Dong Aisheng wrote:
> There's no user of it in kernel now and it basically functions the same
> as the generic syscon-poweroff.c to which we have already switched.
> So let's remove it.
>
> Cc: Robin Gong <yibin.gong@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> .../bindings/power/reset/imx-snvs-poweroff.txt | 23 --------
Acked-by: Rob Herring <robh@kernel.org>
> drivers/power/reset/Kconfig | 9 ---
> drivers/power/reset/Makefile | 1 -
> drivers/power/reset/imx-snvs-poweroff.c | 66 ----------------------
> 4 files changed, 99 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/power/reset/imx-snvs-poweroff.txt
> delete mode 100644 drivers/power/reset/imx-snvs-poweroff.c
^ permalink raw reply
* [PATCH] dt: psci: Update DT bindings to support hierarchical PSCI states
From: Rob Herring @ 2017-12-26 22:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513953127-3321-1-git-send-email-ulf.hansson@linaro.org>
On Fri, Dec 22, 2017 at 03:32:07PM +0100, Ulf Hansson wrote:
> From: Lina Iyer <lina.iyer@linaro.org>
>
> Update DT bindings to represent hierarchical CPU and CPU domain idle states
> for PSCI. Also update the PSCI examples to clearly show how flattened and
> hierarchical idle states can be represented in DT.
>
> Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
> ---
>
> For your information, I have picked up the work from Lina Iyer around the so
> called CPU cluster idling series [1,2] and I working on new versions. However,
> I decided to post the updates to the PSCI DT bindings first, as they will be
> needed to be agreed upon before further changes can be done to the PSCI firmware
> driver.
>
> Note, these bindings have been discussed over and over again, at LKML, but
> especially also at various Linux conferences, like LPC and Linaro Connect. We
> finally came to a conclusion and the changes we agreed upon, should be reflected
> in this update.
>
> Of course, it's a while ago since the latest discussions, but hopefully people
> don't have too hard time to remember.
Vaguely...
>
> Kind regards
> Uffe
>
> [1]
> https://www.spinics.net/lists/arm-kernel/msg566200.html
>
> [2]
> https://lwn.net/Articles/716300/
>
> ---
> Documentation/devicetree/bindings/arm/psci.txt | 152 +++++++++++++++++++++++++
> 1 file changed, 152 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
> index a2c4f1d..5a8f11b 100644
> --- a/Documentation/devicetree/bindings/arm/psci.txt
> +++ b/Documentation/devicetree/bindings/arm/psci.txt
> @@ -105,7 +105,159 @@ Case 3: PSCI v0.2 and PSCI v0.1.
> ...
> };
>
> +PSCI v1.0 onwards, supports OS-Initiated mode for powering off CPUs and CPU
> +clusters from the firmware. For such topologies the PSCI firmware driver acts
> +as pseudo-controller, which may be specified in the psci DT node. The
> +definitions of the CPU and the CPU cluster topology, must conform to the domain
> +idle state specification [3]. The domain idle states themselves, must be
> +compatible with the defined 'domain-idle-state' binding [1], and also need to
> +specify the arm,psci-suspend-param property for each idle state.
> +
> +DT allows representing CPU and CPU cluster idle states in two different ways -
> +
> +The flattened model as given in Example 1, lists CPU's idle states followed by
> +the domain idle state that the CPUs may choose. This is the general practice
> +followed in PSCI firmwares that support Platform Coordinated mode. Note that
> +the idle states are all compatible with "arm,idle-state".
> +
> +Example 2 represents the hierarchical model of CPU and domain idle states.
> +CPUs define their domain provider in their DT node. The domain controls the
> +power to the CPU and possibly other h/w blocks that would be powered off when
> +the CPU is powered off. The CPU's idle states may therefore be considered as
> +the domain's idle states and have the compatible "arm,idle-state". Such domains
> +may be embedded within another domain that represents common h/w blocks between
> +these CPUs viz. the cluster. The idle states of the cluster would be
> +represented as the domain's idle states. In order to use OS-Initiated mode of
> +PSCI in the firmware, the hierarchical representation must be used.
> +
> +Example 1: Flattened representation of CPU and domain idle states
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>,
> + <&CLUSTER_PWR_DWN>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + reg = <0x100>;
> + enable-method = "psci";
> + cpu-idle-states = <&CPU_PWRDN>, <&CLUSTER_RET>,
> + <&CLUSTER_PWR_DWN>;
> + };
> +
> + idle-states {
> + CPU_PWRDN: cpu_power_down{
Use '-' rather than '_'. dtc has more warnings since last time...
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x000001>;
> + entry-latency-us = <10>;
> + exit-latency-us = <10>;
> + min-residency-us = <100>;
> + };
> +
> + CLUSTER_RET: domain_ret {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x1000010>;
> + entry-latency-us = <500>;
> + exit-latency-us = <500>;
> + min-residency-us = <2000>;
> + };
> +
> + CLUSTER_PWR_DWN: domain_off {
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x1000030>;
> + entry-latency-us = <2000>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6000>;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-0.2";
> + method = "smc";
> + };
> +
> +Example 2: Hierarchical representation of CPU and domain idle states
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD0>;
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + reg = <0x100>;
> + enable-method = "psci";
> + power-domains = <&CPU_PD1>;
> + };
> +
> + idle-states {
> + CPU_PWRDN: cpu_power_down{
> + compatible = "arm,idle-state";
> + arm,psci-suspend-param = <0x000001>;
> + entry-latency-us = <10>;
> + exit-latency-us = <10>;
> + min-residency-us = <100>;
> + };
> +
> + CLUSTER_RET: domain_ret {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x1000010>;
> + entry-latency-us = <500>;
> + exit-latency-us = <500>;
> + min-residency-us = <2000>;
> + };
> +
> + CLUSTER_PWR_DWN: domain_off {
> + compatible = "domain-idle-state";
> + arm,psci-suspend-param = <0x1000030>;
> + entry-latency-us = <2000>;
> + exit-latency-us = <2000>;
> + min-residency-us = <6000>;
> + };
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> +
> + CPU_PD0: cpu-pd at 0 {
A unit address without reg property is now a warning.
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CPU_PWRDN>;
> + power-domains = <&CLUSTER_PD>;
> + };
> +
> + CPU_PD1: cpu-pd at 1 {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CPU_PWRDN>;
> + power-domains = <&CLUSTER_PD>;
Could this node be a child of CLUSTER_PD rather than having a phandle?
Doesn't matter so much here, but when you have 3 levels?
> + };
These 2 nodes are identical, so why do you need both?
> +
> + CLUSTER_PD: cluster-pd at 0 {
> + #power-domain-cells = <0>;
> + domain-idle-states = <&CLUSTER_RET>, <&CLUSTER_PWR_DWN>;
> + };
> + };
> +
> [1] Kernel documentation - ARM idle states bindings
> Documentation/devicetree/bindings/arm/idle-states.txt
> [2] Power State Coordination Interface (PSCI) specification
> http://infocenter.arm.com/help/topic/com.arm.doc.den0022c/DEN0022C_Power_State_Coordination_Interface.pdf
> +[3]. PM Domains description
> + Documentation/devicetree/bindings/power/power_domain.txt
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 03/14] dt-bindings: iio: add binding support for iio trigger provider/consumer
From: Rob Herring @ 2017-12-26 22:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513955241-10985-4-git-send-email-eugen.hristev@microchip.com>
On Fri, Dec 22, 2017 at 05:07:10PM +0200, Eugen Hristev wrote:
> Add bindings for producer/consumer for iio triggers.
>
> Similar with iio channels, the iio triggers can be connected between drivers:
> one driver will be a producer by registering iio triggers, and another driver
> will connect as a consumer.
>
> Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
> ---
> .../devicetree/bindings/iio/iio-bindings.txt | 52 +++++++++++++++++++++-
> 1 file changed, 51 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/iio/iio-bindings.txt b/Documentation/devicetree/bindings/iio/iio-bindings.txt
> index 68d6f8c..d861f0df 100644
> --- a/Documentation/devicetree/bindings/iio/iio-bindings.txt
> +++ b/Documentation/devicetree/bindings/iio/iio-bindings.txt
> @@ -11,6 +11,10 @@ value of a #io-channel-cells property in the IIO provider node.
>
> [1] http://marc.info/?l=linux-iio&m=135902119507483&w=2
>
> +Moreover, the provider can have a set of triggers that can be attached to
> +from the consumer drivers.
> +
> +
> ==IIO providers==
>
> Required properties:
> @@ -18,6 +22,11 @@ Required properties:
> with a single IIO output and 1 for nodes with multiple
> IIO outputs.
>
> +Optional properties:
> +#io-trigger-cells: Number of cells for the IIO trigger specifier. Typically 0
> + for nodes with a single IIO trigger and 1 for nodes with
> + multiple IIO triggers.
> +
> Example for a simple configuration with no trigger:
>
> adc: voltage-sensor at 35 {
> @@ -26,7 +35,7 @@ Example for a simple configuration with no trigger:
> #io-channel-cells = <1>;
> };
>
> -Example for a configuration with trigger:
> +Example for a configuration with channels provided by trigger:
>
> adc at 35 {
> compatible = "some-vendor,some-adc";
> @@ -42,6 +51,17 @@ Example for a configuration with trigger:
> };
> };
>
> +Example for a configuration for a trigger provider:
> +
> + adc: sensor-with-trigger at 35 {
> + compatible = "some-vendor,some-adc";
> + reg = <0x35>;
> + #io-channel-cells = <1>;
> + #io-trigger-cells = <1>;
> + /* other properties */
> + };
> +
> +
> ==IIO consumers==
>
> Required properties:
> @@ -61,16 +81,38 @@ io-channel-ranges:
> IIO channels from this node. Useful for bus nodes to provide
> and IIO channel to their children.
>
> +io-triggers: List of phandle and IIO specifier pairs, one pair
> + for each trigger input to the device. Note: if the
> + IIO trigger provider specifies '0' for #io-trigger-cells,
> + then only the phandle portion of the pair will appear.
> +
> +io-trigger-names:
> + List of IIO trigger input name strings sorted in the same
> + order as the io-triggers property. Consumers drivers
> + will use io-trigger-names to match IIO trigger input names
> + with IIO specifiers.
> +
> +io-trigger-ranges:
> + Empty property indicating that child nodes can inherit named
> + IIO triggers from this node. Useful for bus nodes to provide
> + IIO triggers to their children.
I think it would be better to be explicit in the child nodes. What's the
use you had in mind?
Rob
^ permalink raw reply
* [PATCH 13/14] input: touchscreen: sama5d2_rts: SAMA5D2 Resistive touchscreen driver
From: Rob Herring @ 2017-12-26 22:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513955241-10985-14-git-send-email-eugen.hristev@microchip.com>
On Fri, Dec 22, 2017 at 05:07:20PM +0200, Eugen Hristev wrote:
> This is the implementation of the Microchip SAMA5D2 SOC resistive
> touchscreen driver.
> The driver registers an input device and connects to the give IIO device
> from devicetree. It requires an IIO trigger (acting as a consumer) and
> three IIO channels : one for X position, one for Y position and one
> for pressure.
> It the reports the values to the input subsystem.
>
> Some parts of this driver are based on the initial original work by
> Mohamed Jamsheeth Hajanajubudeen and Bandaru Venkateswara Swamy
This doesn't appear to have anything specific to SAMA5D2 SoC, but is
rather just a generic ADC (IIO based) resistive touchscreen driver.
Perhaps the binding can also be just an "adc-resistive-touchscreen".
Rob
^ permalink raw reply
* [PATCHv3 RESEND 1/3] Documentation: dt: memory: ti-emif: add edac support under emif
From: Rob Herring @ 2017-12-26 22:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513959834-27901-1-git-send-email-t-kristo@ti.com>
On Fri, Dec 22, 2017 at 06:23:54PM +0200, Tero Kristo wrote:
> Certain revisions of the TI EMIF IP contain ECC support in them. Reflect
> this in the DT binding.
"dt-bindings: edac: ..." is the preferred subject prefix.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> ---
> Just resending this patch, missed adding devicetree list on this previously
> and it got lost.
>
> .../devicetree/bindings/memory-controllers/ti/emif.txt | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> index 0db6047..f56a347 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> @@ -3,12 +3,16 @@
> EMIF - External Memory Interface - is an SDRAM controller used in
> TI SoCs. EMIF supports, based on the IP revision, one or more of
> DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
> -of the EMIF IP and memory parts attached to it.
> +of the EMIF IP and memory parts attached to it. Certain revisions
> +of the EMIF IP controller also contain optional ECC support, which
> +corrects one bit errors and detects two bit errors.
>
> Required properties:
> - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
> is the IP revision of the specific EMIF instance.
> For am437x should be ti,emif-am4372.
> + For dra7xx should be ti,emif-dra7xx.
> + For k2x family, should be ti,emif-keystone.
>
> - phy-type : <u32> indicating the DDR phy type. Following are the
> allowed values
> @@ -42,6 +46,10 @@ Optional properties:
> - hw-caps-temp-alert : Have this property if the controller
> has capability for generating SDRAM temperature alerts
>
> +- interrupts : A list of interrupt specifiers for memory
> + controller interrupts, if available. Required for EMIF instances
> + that support ECC.
Be explicit as to which compatibles have an interrupt. Is it really
optional for for those controllers? The interrupt is in the h/w whether
you use ECC or not.
> +
> Example:
>
> emif1: emif at 0x4c000000 {
> @@ -54,3 +62,9 @@ emif1: emif at 0x4c000000 {
> hw-caps-ll-interface;
> hw-caps-temp-alert;
> };
> +
> +emif1: emif at 4c000000 {
> + compatible = "ti,emif-dra7";
> + reg = <0x4c000000 0x200>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +};
> --
> 1.9.1
>
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply
* [PATCHv3 RESEND 1/3] Documentation: dt: memory: ti-emif: add edac support under emif
From: Rob Herring @ 2017-12-26 22:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226224819.6uekbnbd5tllaxb5@rob-hp-laptop>
On Tue, Dec 26, 2017 at 4:48 PM, Rob Herring <robh@kernel.org> wrote:
> On Fri, Dec 22, 2017 at 06:23:54PM +0200, Tero Kristo wrote:
>> Certain revisions of the TI EMIF IP contain ECC support in them. Reflect
>> this in the DT binding.
>
> "dt-bindings: edac: ..." is the preferred subject prefix.
Err, I mean "dt-bindings: memory-controllers: ..."
Rob
^ permalink raw reply
* [PATCH 09/11 v2] ARM: orion5x: constify gpio_led
From: kbuild test robot @ 2017-12-26 23:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed1e5c5986f45d1fffc87781b655ae8cc3603c21.1514267721.git.arvind.yadav.cs@gmail.com>
Hi Arvind,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on arm-soc/for-next]
[also build test ERROR on v4.15-rc5 next-20171222]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Arvind-Yadav/MIPS-Alchemy-constify-gpio_led/20171227-043658
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git for-next
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
arch/arm/mach-orion5x/dns323-setup.c: In function 'dns323_init':
>> arch/arm/mach-orion5x/dns323-setup.c:577:32: error: assignment of member 'active_low' in read-only object
dns323ab_leds[0].active_low = 1;
^
vim +/active_low +577 arch/arm/mach-orion5x/dns323-setup.c
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 536
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 537 static void __init dns323_init(void)
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 538 {
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 539 /* Setup basic Orion functions. Need to be called early. */
9dd0b194 arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-03-27 540 orion5x_init();
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 541
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 542 /* Identify revision */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 543 system_rev = dns323_identify_rev();
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 544 pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 545
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 546 /* Just to be tricky, the 5182 has a completely different
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 547 * set of MPP modes to the 5181.
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 548 */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 549 switch(system_rev) {
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 550 case DNS323_REV_A1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 551 orion5x_mpp_conf(dns323a_mpp_modes);
79e90dd5 arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-05-28 552 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 553 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 554 case DNS323_REV_B1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 555 orion5x_mpp_conf(dns323b_mpp_modes);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 556 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 557 case DNS323_REV_C1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 558 orion5x_mpp_conf(dns323c_mpp_modes);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 559 break;
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 560 }
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 561
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 562 /* setup flash mapping
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 563 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 564 */
4ca2c040 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-07-26 565 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
4ca2c040 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-07-26 566 ORION_MBUS_DEVBUS_BOOT_ATTR,
4ca2c040 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-07-26 567 DNS323_NOR_BOOT_BASE,
5d1190ea arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-03-21 568 DNS323_NOR_BOOT_SIZE);
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 569 platform_device_register(&dns323_nor_flash);
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 570
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 571 /* Sort out LEDs, Buttons and i2c devices */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 572 switch(system_rev) {
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 573 case DNS323_REV_A1:
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 574 /* The 5181 power LED is active low and requires
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 575 * DNS323_GPIO_LED_POWER1 to also be low.
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 576 */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 @577 dns323ab_leds[0].active_low = 1;
5ccc8dab arch/arm/mach-orion5x/dns323-setup.c Arnaud Patard 2010-04-03 578 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 579 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 580 /* Fall through */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 581 case DNS323_REV_B1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 582 i2c_register_board_info(0, dns323ab_i2c_devices,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 583 ARRAY_SIZE(dns323ab_i2c_devices));
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 584 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 585 case DNS323_REV_C1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 586 /* Hookup LEDs & Buttons */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 587 dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 588 dns323_button_device.dev.platform_data = &dns323c_button_data;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 589
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 590 /* Hookup i2c devices and fan driver */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 591 i2c_register_board_info(0, dns323c_i2c_devices,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 592 ARRAY_SIZE(dns323c_i2c_devices));
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 593 platform_device_register_simple("dns323c-fan", 0, NULL, 0);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 594
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 595 /* Register fixup for the PHY LEDs */
32ff4971 arch/arm/mach-orion5x/dns323-setup.c Arnd Bergmann 2014-03-13 596 if (!IS_BUILTIN(CONFIG_PHYLIB))
32ff4971 arch/arm/mach-orion5x/dns323-setup.c Arnd Bergmann 2014-03-13 597 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 598 phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 599 MARVELL_PHY_ID_MASK,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 600 dns323c_phy_fixup);
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 601 }
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 602
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 603 platform_device_register(&dns323_gpio_leds);
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 604 platform_device_register(&dns323_button_device);
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 605
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 606 /*
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 607 * Configure peripherals.
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 608 */
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 609 if (dns323_read_mac_addr() < 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 610 printk("DNS-323: Failed to read MAC address\n");
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 611 orion5x_ehci0_init();
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 612 orion5x_eth_init(&dns323_eth_data);
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 613 orion5x_i2c_init();
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 614 orion5x_uart0_init();
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 615
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 616 /* Remaining GPIOs */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 617 switch(system_rev) {
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 618 case DNS323_REV_A1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 619 /* Poweroff GPIO */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 620 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 621 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 622 pr_err("DNS-323: failed to setup power-off GPIO\n");
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 623 pm_power_off = dns323a_power_off;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 624 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 625 case DNS323_REV_B1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 626 /* 5182 built-in SATA init */
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 627 orion5x_sata_init(&dns323_sata_data);
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 628
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 629 /* The DNS323 rev B1 has flag to indicate the system is up.
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 630 * Without this flag set, power LED will flash and cannot be
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 631 * controlled via leds-gpio.
cf11052a arch/arm/mach-orion5x/dns323-setup.c Erik Benada 2010-01-24 632 */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 633 if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 634 gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
cf11052a arch/arm/mach-orion5x/dns323-setup.c Erik Benada 2010-01-24 635
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 636 /* Poweroff GPIO */
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 637 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 638 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 639 pr_err("DNS-323: failed to setup power-off GPIO\n");
cf11052a arch/arm/mach-orion5x/dns323-setup.c Erik Benada 2010-01-24 640 pm_power_off = dns323b_power_off;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 641 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 642 case DNS323_REV_C1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 643 /* 5182 built-in SATA init */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 644 orion5x_sata_init(&dns323_sata_data);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 645
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 646 /* Poweroff GPIO */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 647 if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 648 gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 649 pr_err("DNS-323: failed to setup power-off GPIO\n");
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 650 pm_power_off = dns323c_power_off;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 651
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 652 /* Now, -this- should theorically be done by the sata_mv driver
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 653 * once I figure out what's going on there. Maybe the behaviour
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 654 * of the LEDs should be somewhat passed via the platform_data.
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 655 * for now, just whack the register and make the LEDs happy
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 656 *
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 657 * Note: AFAIK, rev B1 needs the same treatement but I'll let
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 658 * somebody else test it.
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 659 */
3904a393 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2012-09-11 660 writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 661 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 662 }
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 663 }
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 664
:::::: The code at line 577 was first introduced by commit
:::::: 6e2daa49420777190c133d7097dd8d5c05b475ac [ARM] orion5x: Base support for DNS-323 rev C1
:::::: TO: Benjamin Herrenschmidt <benh@kernel.crashing.org>
:::::: CC: Nicolas Pitre <nico@fluxnic.net>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [RFC PATCH v12 0/5] PCI: rockchip: Move PCIe WAKE# handling into pci core
From: Rafael J. Wysocki @ 2017-12-27 0:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226023646.17722-1-jeffy.chen@rock-chips.com>
On Tuesday, December 26, 2017 3:36:41 AM CET Jeffy Chen wrote:
>
> Currently we are handling wake irq in mrvl wifi driver. Move it into
> pci core.
>
> Tested on my chromebook bob(with cros 4.4 kernel and mrvl wifi).
>
>
> Changes in v13:
> Fix compiler error reported by kbuild test robot <fengguang.wu@intel.com>
>
> Changes in v12:
> Only add irq definitions for PCI devices and rewrite the commit message.
> Enable the wake irq in noirq stage to avoid possible irq storm.
>
> Changes in v11:
> Address Brian's comments.
> Only support 1-per-device PCIe WAKE# pin as suggested.
> Move to pcie port as Brian suggested.
>
> Changes in v10:
> Use device_set_wakeup_capable() instead of device_set_wakeup_enable(),
> since dedicated wakeirq will be lost in device_set_wakeup_enable(false).
>
> Changes in v9:
> Add section for PCI devices and rewrite the commit message.
> Fix check error in .cleanup().
> Move dedicated wakeirq setup to setup() callback and use
> device_set_wakeup_enable() to enable/disable.
> Rewrite the commit message.
>
> Changes in v8:
> Add optional "pci", and rewrite commit message.
> Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal.
> Rewrite the commit message.
>
> Changes in v7:
> Move PCIE_WAKE handling into pci core.
>
> Changes in v6:
> Fix device_init_wake error handling, and add some comments.
>
> Changes in v5:
> Move to pci.txt
> Rebase.
> Use "wakeup" instead of "wake"
>
> Changes in v3:
> Fix error handling.
>
> Changes in v2:
> Use dev_pm_set_dedicated_wake_irq.
>
> Jeffy Chen (5):
> dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq
> of/irq: Adjust of_pci_irq parsing for multiple interrupts
> mwifiex: Disable wakeup irq handling for pcie
> PCI / PM: Add support for the PCIe WAKE# signal for OF
> arm64: dts: rockchip: Move PCIe WAKE# irq to pcie port for Gru
>
> Documentation/devicetree/bindings/pci/pci.txt | 10 ++++
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 11 ++--
> drivers/net/wireless/marvell/mwifiex/main.c | 4 ++
> drivers/of/of_pci_irq.c | 71 +++++++++++++++++++++++--
> drivers/pci/Makefile | 1 +
> drivers/pci/pci-driver.c | 10 ++++
> drivers/pci/pci-of.c | 75 +++++++++++++++++++++++++++
> include/linux/of_pci.h | 9 ++++
> 8 files changed, 183 insertions(+), 8 deletions(-)
> create mode 100644 drivers/pci/pci-of.c
I'm going to ignore this version till the discussion on the previous one is
over.
Thanks,
Rafael
^ permalink raw reply
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Peng Fan @ 2017-12-27 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226102038.GB11724@b29396-OptiPlex-7040>
> -----Original Message-----
> From: Dong Aisheng [mailto:dongas86 at gmail.com]
> Sent: Tuesday, December 26, 2017 6:21 PM
> To: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; A.s. Dong <aisheng.dong@nxp.com>;
> linux-kernel at vger.kernel.org; Russell King <linux@armlinux.org.uk>; Fabio
> Estevam <fabio.estevam@nxp.com>; Sascha Hauer <kernel@pengutronix.de>;
> van.freenix at gmail.com; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH] arm: imx: suspend/resume: use outer_disable/resume
>
> On Tue, Dec 26, 2017 at 10:11:41AM +0000, Peng Fan wrote:
> >
> > Hi Aisheng,
> >
> > > -----Original Message-----
> > > From: Dong Aisheng [mailto:dongas86 at gmail.com]
> > > Sent: Tuesday, December 26, 2017 6:04 PM
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>; A.s. Dong
> > > <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org; Russell King
> > > <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> > > Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com;
> > > linux-arm-kernel at lists.infradead.org
> > > Subject: Re: [PATCH] arm: imx: suspend/resume: use
> > > outer_disable/resume
> > >
> > > On Tue, Dec 26, 2017 at 09:49:01AM +0000, Peng Fan wrote:
> > > > Hi Shawn
> > > >
> > > > > -----Original Message-----
> > > > > From: Shawn Guo [mailto:shawnguo at kernel.org]
> > > > > Sent: Tuesday, December 26, 2017 5:13 PM
> > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > Cc: A.s. Dong <aisheng.dong@nxp.com>;
> > > > > linux-kernel at vger.kernel.org; Russell King
> > > > > <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > > Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com;
> > > > > linux-arm- kernel at lists.infradead.org
> > > > > Subject: Re: [PATCH] arm: imx: suspend/resume: use
> > > > > outer_disable/resume
> > > > >
> > > > > On Sun, Dec 10, 2017 at 08:07:18PM +0800, Peng Fan wrote:
> > > > > > Use outer_disable/resume for suspend/resume.
> > > > > > With the two APIs used, code could be simplified and easy to
> > > > > > extend to introduce l2c_write_sec for i.MX platforms when
> > > > > > moving Linux Kernel runs in non-secure world.
> > > > > >
> > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > > > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > > > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > > > > Cc: Russell King <linux@armlinux.org.uk>
> > > > > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> > > > >
> > > > > Changed 'arm: ' prefix to 'ARM: ', and applied patch.
> > > >
> > > > I just tested it on 6sx-sdb, seems this patch breaks 6sx. Could
> > > > you first drop this patch? I'll send out v2 fix the 6sx issue soon.
> > > >
> > >
> > > Yes, i tested mx6ul/mx6sl ok but mx6sx sdb failed.
> >
> > Thanks for the test.
> >
> > >
> > > After a few debug, it seems you removed the l2c310_early_resume in
> > > v7_cpu_resume which is shared between lower power idle and suspend.
> > >
> > > Current only mx6sx/mx6ul supports low power idle in upstream, but
> > > mx6ul is
> > > A7 with internal L2, that's probably why only mx6sx showed the issue.
> > >
> > > I did the following quick try to restore L2 after exit lower power
> > > idle, but still can meet occasional crash during booting.
> > >
> > > diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-
> > > imx/cpuidle-imx6sx.c index c5a5c3a..edce5bd 100644
> > > --- a/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > @@ -26,7 +26,7 @@ static int imx6sx_idle_finish(unsigned long val)
> > > * to adding conditional code for L2 cache type,
> > > * just call flush_cache_all() is fine.
> > > */
> > > - flush_cache_all();
> > > +// flush_cache_all();
> >
> > I think flush_cache_all is still needed, to flush L1 data, right?
> >
>
> I thought it will be done in generic cpu_suspend.
> See: __cpu_suspend_save()
>
> So we still need it?
After remove flush_cache_all, seems 6sx-sdb suspend/resume and low power idle both works.
Alought __cpu_suspend_save flush data, my understanding is there is chance to cache data/inst
before "wfi". Then we better keep flush_cache_all here?
Thanks,
Peng.
>
>
> Regards
> Dong Aisheng
> > > cpu_do_idle();
> > >
> > > return 0;
> > > @@ -49,7 +49,9 @@ static int imx6sx_enter_wait(struct cpuidle_device
> *dev,
> > > cpu_pm_enter();
> > > cpu_cluster_pm_enter();
> > >
> > > + outer_disable();
> > > cpu_suspend(0, imx6sx_idle_finish);
> > > + outer_resume();
> >
> > Yes, this is in my V2 patch.
> >
> > >
> > > cpu_cluster_pm_exit();
> > > cpu_pm_exit();
> > >
> > > As this changed the order to L2 restore and cpu resume, so i'm not
> > > quite sure if lower power idle still requres L2 restore before CPU
> > > resume or something else we're missing.
> >
> > In low power idle, L2 may also lose power, so outer_disable/resume is
> needed, I think.
> >
> > Thanks,
> > Peng.
> >
> > >
> > > Regards
> > > Dong Aisheng
> > >
> > > > Thanks,
> > > > Peng.
> > > >
> > > > >
> > > > > Shawn
^ permalink raw reply
* [PATCH v5 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code
From: honghui.zhang at mediatek.com @ 2017-12-27 0:59 UTC (permalink / raw)
To: linux-arm-kernel
From: Honghui Zhang <honghui.zhang@mediatek.com>
Two fixups for mediatek's host bridge:
The first patch fixup the IRQ handle routine to avoid IRQ reentry which
may exist for both MT2712 and MT7622.
The second patch fixup class type for MT7622.
Change since v4:
- Only setup vendor ID for MT7622, igorning the device ID since mediatek's
host bridge driver does not cares about the device ID.
Change since v3:
- Setup the class type and vendor ID at the beginning of startup instead
of in a quirk.
- Add mediatek's vendor ID, it could be found in:
https://pcisig.com/membership/member-companies?combine=&page=4
Change since v2:
- Move the initialize of the iterate before the loop to fix an
INTx IRQ issue in the first patch
Change since v1:
- Add the second patch.
- Make the first patch's commit message more standard.
Honghui Zhang (2):
PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry
PCI: mediatek: Set up class type and vendor ID for MT7622
drivers/pci/host/pcie-mediatek.c | 23 ++++++++++++++++++-----
include/linux/pci_ids.h | 2 ++
2 files changed, 20 insertions(+), 5 deletions(-)
--
2.6.4
^ permalink raw reply
* [PATCH v5 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry
From: honghui.zhang at mediatek.com @ 2017-12-27 0:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514336394-17747-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
There maybe a same IRQ reentry scenario after IRQ received in current
IRQ handle flow:
EP device PCIe host driver EP driver
1. issue an IRQ
2. received IRQ
3. clear IRQ status
4. dispatch IRQ
5. clear IRQ source
The IRQ status was not successfully cleared at step 2 since the IRQ
source was not cleared yet. So the PCIe host driver may receive the
same IRQ after step 5. Then there's an IRQ reentry occurred.
Even worse, if the reentry IRQ was not an IRQ that EP driver expected,
it may not handle the IRQ. Then we may run into the infinite loop from
step 2 to step 4.
Clear the IRQ status after IRQ have been dispatched to avoid the IRQ
reentry.
This patch also fix another INTx IRQ issue by initialize the iterate
before the loop. If an INTx IRQ re-occurred while we are dispatching
the INTx IRQ, then iterate may start from PCI_NUM_INTX + INTX_SHIFT
instead of INTX_SHIFT for the second time entering the
for_each_set_bit_from() loop.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pci/host/pcie-mediatek.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index db93efd..fc29a9a 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -601,15 +601,16 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
unsigned long status;
u32 virq;
- u32 bit = INTX_SHIFT;
+ u32 bit;
while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
+ bit = INTX_SHIFT;
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
- /* Clear the INTx */
- writel(1 << bit, port->base + PCIE_INT_STATUS);
virq = irq_find_mapping(port->irq_domain,
bit - INTX_SHIFT);
generic_handle_irq(virq);
+ /* Clear the INTx */
+ writel(1 << bit, port->base + PCIE_INT_STATUS);
}
}
@@ -619,10 +620,10 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
- /* Clear the MSI */
- writel(1 << bit, port->base + PCIE_IMSI_STATUS);
virq = irq_find_mapping(port->msi_domain, bit);
generic_handle_irq(virq);
+ /* Clear the MSI */
+ writel(1 << bit, port->base + PCIE_IMSI_STATUS);
}
}
/* Clear MSI interrupt status */
--
2.6.4
^ permalink raw reply related
* [PATCH v5 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622
From: honghui.zhang at mediatek.com @ 2017-12-27 0:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514336394-17747-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
The hardware default value of IDs and class type is not correct,
fix that by setup the correct values before start up.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
drivers/pci/host/pcie-mediatek.c | 12 ++++++++++++
include/linux/pci_ids.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index fc29a9a..62aac0ea 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -74,6 +74,10 @@
/* PCIe V2 per-port registers */
#define PCIE_MSI_VECTOR 0x0c0
+
+#define PCIE_CONF_ID 0x100
+#define PCIE_CONF_CLASS 0x104
+
#define PCIE_INT_MASK 0x420
#define INTX_MASK GENMASK(19, 16)
#define INTX_SHIFT 16
@@ -393,6 +397,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
val |= PCIE_CSR_LTSSM_EN(port->slot) |
PCIE_CSR_ASPM_L1_EN(port->slot);
writel(val, pcie->base + PCIE_SYS_CFG_V2);
+
+ /* Set up vendor ID and device ID for MT7622*/
+ val = PCI_VENDOR_ID_MEDIATEK;
+ writel(val, port->base + PCIE_CONF_ID);
+
+ /* Set up class code for MT7622 */
+ val = PCI_CLASS_BRIDGE_PCI << 16;
+ writel(val, port->base + PCIE_CONF_CLASS);
}
/* Assert all reset signals */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5..2480b0e 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2113,6 +2113,8 @@
#define PCI_VENDOR_ID_MYRICOM 0x14c1
+#define PCI_VENDOR_ID_MEDIATEK 0x14c3
+
#define PCI_VENDOR_ID_TITAN 0x14D2
#define PCI_DEVICE_ID_TITAN_010L 0x8001
#define PCI_DEVICE_ID_TITAN_100L 0x8010
--
2.6.4
^ permalink raw reply related
* [PATCH 1/2] clk: rename clk_core_get_boundaries() to clk_hw_get_boundaries() and expose
From: Stephen Boyd @ 2017-12-27 1:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8EC4D15B-4A89-43FA-953E-95AF81417067@gmail.com>
On 12/25, Alexander Kochetkov wrote:
>
> > 21 ???. 2017 ?., ? 23:07, Stephen Boyd <sboyd@codeaurora.org> ???????(?):
> >
> > Can you convert to the determine_rate op instead of round_rate?
> > That function should tell you the min/max limits so that you
> > don't need to query that information from the core.
>
> I converted rockchip_fractional_approximation() to rockchip_determine_rate() (see the patch attached).
> If it increase parent?s clock for out of limits value, than clock request will fail with -EINVAL, like
> with round_rate() approach.
>
> The problem is that min/max limits provided to determine_rate() is for clock for which the determine_rate()
> was called. While rockchip_determine_rate() (rockchip_fractional_approximation()) requires information
> about parent clock limits.
Are these limits the min/max limits that the parent clk can
output at? Or the min/max limits that software has constrained on
the clk?
>
> How can I know parents clock limits for current clock? Implement determine_rate() for each parent clocks
> the same way I did for this one clock?
If the parent can change rate, then the idea is that the child
will calculate the limits that it can handle based on what it can
do with the incoming min/max constraints, and then call
__clk_determine_rate() on its parent with a request structure
that has limits for whatever the child clk is able to handle. The
parent can then determine a rate it can output that's within that
range and tell the child clk if it will satisfy the constraints
or not along with the resulting rate it will output when the
__clk_determine_rate() function returns. I would expect the
constraints to get closer together the higher in the tree we go.
I haven't looked in detail at this
rockchip_fractional_approximation() code, but it shouldn't be
doing the work of both the child rate determination and the
parent rate determination in one place. It should work with the
parent to figure out the rate the parent can provide and then
figure out how to achieve the desired rate from there.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [RFC PATCH V1 2/2] clk: add lock for clk_core_is_enabled
From: Stephen Boyd @ 2017-12-27 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513935965-12909-2-git-send-email-aisheng.dong@nxp.com>
On 12/22, Dong Aisheng wrote:
> According to design doc, .is_enabled should be protected by enable lock.
> Then users don't have to protect it against enable/disable operation
> in clock drivers.
>
> See: Documentation/clk.txt
> "The enable lock is a spinlock and is held across calls to the .enable,
> .disable and .is_enabled operations."
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> drivers/clk/clk.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index e24968f..d6e2d5c 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -198,14 +198,19 @@ static bool clk_core_is_prepared(struct clk_core *core)
>
> static bool clk_core_is_enabled(struct clk_core *core)
> {
> + unsigned long flags;
> bool ret = false;
>
> + flags = clk_enable_lock();
> +
> /*
> * .is_enabled is only mandatory for clocks that gate
> * fall back to software usage counter if .is_enabled is missing
> */
> - if (!core->ops->is_enabled)
> + if (!core->ops->is_enabled) {
> + clk_enable_unlock(flags);
> return core->enable_count;
> + }
>
> /*
> * Check if clock controller's device is runtime active before
> @@ -230,6 +235,8 @@ static bool clk_core_is_enabled(struct clk_core *core)
> if (core->dev)
> pm_runtime_put(core->dev);
>
> + clk_enable_unlock(flags);
> +
> return ret;
> }
It doesn't really make any sense to hold the enable lock inside
the clk_core_is_enabled() function, unless you want to do
something else with the information of the enable state with that
lock held. Otherwise, seeing if a clk is enabled is a one-shot
read of the enabled state, which could just as easily change
after the function returns because the lock is released.
We should update the documentation.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
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