* [PATCHv3 RESEND 1/3] Documentation: dt: memory: ti-emif: add edac support under emif
From: Rob Herring @ 2017-12-26 22:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513959834-27901-1-git-send-email-t-kristo@ti.com>
On Fri, Dec 22, 2017 at 06:23:54PM +0200, Tero Kristo wrote:
> Certain revisions of the TI EMIF IP contain ECC support in them. Reflect
> this in the DT binding.
"dt-bindings: edac: ..." is the preferred subject prefix.
>
> Signed-off-by: Tero Kristo <t-kristo@ti.com>
> Cc: Tony Lindgren <tony@atomide.com>
> Cc: Rob Herring <robh+dt@kernel.org>
> ---
> Just resending this patch, missed adding devicetree list on this previously
> and it got lost.
>
> .../devicetree/bindings/memory-controllers/ti/emif.txt | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> index 0db6047..f56a347 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> +++ b/Documentation/devicetree/bindings/memory-controllers/ti/emif.txt
> @@ -3,12 +3,16 @@
> EMIF - External Memory Interface - is an SDRAM controller used in
> TI SoCs. EMIF supports, based on the IP revision, one or more of
> DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
> -of the EMIF IP and memory parts attached to it.
> +of the EMIF IP and memory parts attached to it. Certain revisions
> +of the EMIF IP controller also contain optional ECC support, which
> +corrects one bit errors and detects two bit errors.
>
> Required properties:
> - compatible : Should be of the form "ti,emif-<ip-rev>" where <ip-rev>
> is the IP revision of the specific EMIF instance.
> For am437x should be ti,emif-am4372.
> + For dra7xx should be ti,emif-dra7xx.
> + For k2x family, should be ti,emif-keystone.
>
> - phy-type : <u32> indicating the DDR phy type. Following are the
> allowed values
> @@ -42,6 +46,10 @@ Optional properties:
> - hw-caps-temp-alert : Have this property if the controller
> has capability for generating SDRAM temperature alerts
>
> +- interrupts : A list of interrupt specifiers for memory
> + controller interrupts, if available. Required for EMIF instances
> + that support ECC.
Be explicit as to which compatibles have an interrupt. Is it really
optional for for those controllers? The interrupt is in the h/w whether
you use ECC or not.
> +
> Example:
>
> emif1: emif at 0x4c000000 {
> @@ -54,3 +62,9 @@ emif1: emif at 0x4c000000 {
> hw-caps-ll-interface;
> hw-caps-temp-alert;
> };
> +
> +emif1: emif at 4c000000 {
> + compatible = "ti,emif-dra7";
> + reg = <0x4c000000 0x200>;
> + interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
> +};
> --
> 1.9.1
>
> --
> Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply
* [PATCHv3 RESEND 1/3] Documentation: dt: memory: ti-emif: add edac support under emif
From: Rob Herring @ 2017-12-26 22:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226224819.6uekbnbd5tllaxb5@rob-hp-laptop>
On Tue, Dec 26, 2017 at 4:48 PM, Rob Herring <robh@kernel.org> wrote:
> On Fri, Dec 22, 2017 at 06:23:54PM +0200, Tero Kristo wrote:
>> Certain revisions of the TI EMIF IP contain ECC support in them. Reflect
>> this in the DT binding.
>
> "dt-bindings: edac: ..." is the preferred subject prefix.
Err, I mean "dt-bindings: memory-controllers: ..."
Rob
^ permalink raw reply
* [PATCH 09/11 v2] ARM: orion5x: constify gpio_led
From: kbuild test robot @ 2017-12-26 23:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ed1e5c5986f45d1fffc87781b655ae8cc3603c21.1514267721.git.arvind.yadav.cs@gmail.com>
Hi Arvind,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on arm-soc/for-next]
[also build test ERROR on v4.15-rc5 next-20171222]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Arvind-Yadav/MIPS-Alchemy-constify-gpio_led/20171227-043658
base: https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git for-next
config: arm-multi_v5_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
arch/arm/mach-orion5x/dns323-setup.c: In function 'dns323_init':
>> arch/arm/mach-orion5x/dns323-setup.c:577:32: error: assignment of member 'active_low' in read-only object
dns323ab_leds[0].active_low = 1;
^
vim +/active_low +577 arch/arm/mach-orion5x/dns323-setup.c
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 536
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 537 static void __init dns323_init(void)
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 538 {
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 539 /* Setup basic Orion functions. Need to be called early. */
9dd0b194 arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-03-27 540 orion5x_init();
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 541
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 542 /* Identify revision */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 543 system_rev = dns323_identify_rev();
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 544 pr_info("DNS-323: Identified HW revision %c1\n", 'A' + system_rev);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 545
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 546 /* Just to be tricky, the 5182 has a completely different
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 547 * set of MPP modes to the 5181.
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 548 */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 549 switch(system_rev) {
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 550 case DNS323_REV_A1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 551 orion5x_mpp_conf(dns323a_mpp_modes);
79e90dd5 arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-05-28 552 writel(0, MPP_DEV_CTRL); /* DEV_D[31:16] */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 553 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 554 case DNS323_REV_B1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 555 orion5x_mpp_conf(dns323b_mpp_modes);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 556 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 557 case DNS323_REV_C1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 558 orion5x_mpp_conf(dns323c_mpp_modes);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 559 break;
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 560 }
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 561
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 562 /* setup flash mapping
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 563 * CS3 holds a 8 MB Spansion S29GL064M90TFIR4
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 564 */
4ca2c040 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-07-26 565 mvebu_mbus_add_window_by_id(ORION_MBUS_DEVBUS_BOOT_TARGET,
4ca2c040 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-07-26 566 ORION_MBUS_DEVBUS_BOOT_ATTR,
4ca2c040 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-07-26 567 DNS323_NOR_BOOT_BASE,
5d1190ea arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2013-03-21 568 DNS323_NOR_BOOT_SIZE);
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 569 platform_device_register(&dns323_nor_flash);
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 570
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 571 /* Sort out LEDs, Buttons and i2c devices */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 572 switch(system_rev) {
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 573 case DNS323_REV_A1:
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 574 /* The 5181 power LED is active low and requires
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 575 * DNS323_GPIO_LED_POWER1 to also be low.
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 576 */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 @577 dns323ab_leds[0].active_low = 1;
5ccc8dab arch/arm/mach-orion5x/dns323-setup.c Arnaud Patard 2010-04-03 578 gpio_request(DNS323_GPIO_LED_POWER1, "Power Led Enable");
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 579 gpio_direction_output(DNS323_GPIO_LED_POWER1, 0);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 580 /* Fall through */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 581 case DNS323_REV_B1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 582 i2c_register_board_info(0, dns323ab_i2c_devices,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 583 ARRAY_SIZE(dns323ab_i2c_devices));
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 584 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 585 case DNS323_REV_C1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 586 /* Hookup LEDs & Buttons */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 587 dns323_gpio_leds.dev.platform_data = &dns323c_led_data;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 588 dns323_button_device.dev.platform_data = &dns323c_button_data;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 589
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 590 /* Hookup i2c devices and fan driver */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 591 i2c_register_board_info(0, dns323c_i2c_devices,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 592 ARRAY_SIZE(dns323c_i2c_devices));
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 593 platform_device_register_simple("dns323c-fan", 0, NULL, 0);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 594
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 595 /* Register fixup for the PHY LEDs */
32ff4971 arch/arm/mach-orion5x/dns323-setup.c Arnd Bergmann 2014-03-13 596 if (!IS_BUILTIN(CONFIG_PHYLIB))
32ff4971 arch/arm/mach-orion5x/dns323-setup.c Arnd Bergmann 2014-03-13 597 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 598 phy_register_fixup_for_uid(MARVELL_PHY_ID_88E1118,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 599 MARVELL_PHY_ID_MASK,
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 600 dns323c_phy_fixup);
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 601 }
b2a731aa arch/arm/mach-orion5x/dns323-setup.c Laurie Bradshaw 2010-02-10 602
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 603 platform_device_register(&dns323_gpio_leds);
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 604 platform_device_register(&dns323_button_device);
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 605
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 606 /*
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 607 * Configure peripherals.
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 608 */
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 609 if (dns323_read_mac_addr() < 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 610 printk("DNS-323: Failed to read MAC address\n");
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 611 orion5x_ehci0_init();
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 612 orion5x_eth_init(&dns323_eth_data);
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 613 orion5x_i2c_init();
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 614 orion5x_uart0_init();
a93f44c1 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-19 615
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 616 /* Remaining GPIOs */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 617 switch(system_rev) {
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 618 case DNS323_REV_A1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 619 /* Poweroff GPIO */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 620 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 621 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 622 pr_err("DNS-323: failed to setup power-off GPIO\n");
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 623 pm_power_off = dns323a_power_off;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 624 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 625 case DNS323_REV_B1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 626 /* 5182 built-in SATA init */
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 627 orion5x_sata_init(&dns323_sata_data);
f93e4159 arch/arm/mach-orion5x/dns323-setup.c Matt Palmer 2008-10-22 628
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 629 /* The DNS323 rev B1 has flag to indicate the system is up.
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 630 * Without this flag set, power LED will flash and cannot be
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 631 * controlled via leds-gpio.
cf11052a arch/arm/mach-orion5x/dns323-setup.c Erik Benada 2010-01-24 632 */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 633 if (gpio_request(DNS323_GPIO_SYSTEM_UP, "SYS_READY") == 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 634 gpio_direction_output(DNS323_GPIO_SYSTEM_UP, 1);
cf11052a arch/arm/mach-orion5x/dns323-setup.c Erik Benada 2010-01-24 635
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 636 /* Poweroff GPIO */
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 637 if (gpio_request(DNS323_GPIO_POWER_OFF, "POWEROFF") != 0 ||
044f6c7c arch/arm/mach-orion5x/dns323-setup.c Lennert Buytenhek 2008-04-22 638 gpio_direction_output(DNS323_GPIO_POWER_OFF, 0) != 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 639 pr_err("DNS-323: failed to setup power-off GPIO\n");
cf11052a arch/arm/mach-orion5x/dns323-setup.c Erik Benada 2010-01-24 640 pm_power_off = dns323b_power_off;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 641 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 642 case DNS323_REV_C1:
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 643 /* 5182 built-in SATA init */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 644 orion5x_sata_init(&dns323_sata_data);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 645
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 646 /* Poweroff GPIO */
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 647 if (gpio_request(DNS323C_GPIO_POWER_OFF, "POWEROFF") != 0 ||
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 648 gpio_direction_output(DNS323C_GPIO_POWER_OFF, 0) != 0)
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 649 pr_err("DNS-323: failed to setup power-off GPIO\n");
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 650 pm_power_off = dns323c_power_off;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 651
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 652 /* Now, -this- should theorically be done by the sata_mv driver
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 653 * once I figure out what's going on there. Maybe the behaviour
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 654 * of the LEDs should be somewhat passed via the platform_data.
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 655 * for now, just whack the register and make the LEDs happy
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 656 *
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 657 * Note: AFAIK, rev B1 needs the same treatement but I'll let
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 658 * somebody else test it.
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 659 */
3904a393 arch/arm/mach-orion5x/dns323-setup.c Thomas Petazzoni 2012-09-11 660 writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 661 break;
6e2daa49 arch/arm/mach-orion5x/dns323-setup.c Benjamin Herrenschmidt 2010-06-21 662 }
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 663 }
555a3656 arch/arm/mach-orion/dns323-setup.c Herbert Valerio Riedel 2007-11-12 664
:::::: The code at line 577 was first introduced by commit
:::::: 6e2daa49420777190c133d7097dd8d5c05b475ac [ARM] orion5x: Base support for DNS-323 rev C1
:::::: TO: Benjamin Herrenschmidt <benh@kernel.crashing.org>
:::::: CC: Nicolas Pitre <nico@fluxnic.net>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [RFC PATCH v12 0/5] PCI: rockchip: Move PCIe WAKE# handling into pci core
From: Rafael J. Wysocki @ 2017-12-27 0:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226023646.17722-1-jeffy.chen@rock-chips.com>
On Tuesday, December 26, 2017 3:36:41 AM CET Jeffy Chen wrote:
>
> Currently we are handling wake irq in mrvl wifi driver. Move it into
> pci core.
>
> Tested on my chromebook bob(with cros 4.4 kernel and mrvl wifi).
>
>
> Changes in v13:
> Fix compiler error reported by kbuild test robot <fengguang.wu@intel.com>
>
> Changes in v12:
> Only add irq definitions for PCI devices and rewrite the commit message.
> Enable the wake irq in noirq stage to avoid possible irq storm.
>
> Changes in v11:
> Address Brian's comments.
> Only support 1-per-device PCIe WAKE# pin as suggested.
> Move to pcie port as Brian suggested.
>
> Changes in v10:
> Use device_set_wakeup_capable() instead of device_set_wakeup_enable(),
> since dedicated wakeirq will be lost in device_set_wakeup_enable(false).
>
> Changes in v9:
> Add section for PCI devices and rewrite the commit message.
> Fix check error in .cleanup().
> Move dedicated wakeirq setup to setup() callback and use
> device_set_wakeup_enable() to enable/disable.
> Rewrite the commit message.
>
> Changes in v8:
> Add optional "pci", and rewrite commit message.
> Add pci-of.c and use platform_pm_ops to handle the PCIe WAKE# signal.
> Rewrite the commit message.
>
> Changes in v7:
> Move PCIE_WAKE handling into pci core.
>
> Changes in v6:
> Fix device_init_wake error handling, and add some comments.
>
> Changes in v5:
> Move to pci.txt
> Rebase.
> Use "wakeup" instead of "wake"
>
> Changes in v3:
> Fix error handling.
>
> Changes in v2:
> Use dev_pm_set_dedicated_wake_irq.
>
> Jeffy Chen (5):
> dt-bindings: PCI: Add definition of PCIe WAKE# irq and PCI irq
> of/irq: Adjust of_pci_irq parsing for multiple interrupts
> mwifiex: Disable wakeup irq handling for pcie
> PCI / PM: Add support for the PCIe WAKE# signal for OF
> arm64: dts: rockchip: Move PCIe WAKE# irq to pcie port for Gru
>
> Documentation/devicetree/bindings/pci/pci.txt | 10 ++++
> arch/arm64/boot/dts/rockchip/rk3399-gru.dtsi | 11 ++--
> drivers/net/wireless/marvell/mwifiex/main.c | 4 ++
> drivers/of/of_pci_irq.c | 71 +++++++++++++++++++++++--
> drivers/pci/Makefile | 1 +
> drivers/pci/pci-driver.c | 10 ++++
> drivers/pci/pci-of.c | 75 +++++++++++++++++++++++++++
> include/linux/of_pci.h | 9 ++++
> 8 files changed, 183 insertions(+), 8 deletions(-)
> create mode 100644 drivers/pci/pci-of.c
I'm going to ignore this version till the discussion on the previous one is
over.
Thanks,
Rafael
^ permalink raw reply
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Peng Fan @ 2017-12-27 0:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226102038.GB11724@b29396-OptiPlex-7040>
> -----Original Message-----
> From: Dong Aisheng [mailto:dongas86 at gmail.com]
> Sent: Tuesday, December 26, 2017 6:21 PM
> To: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; A.s. Dong <aisheng.dong@nxp.com>;
> linux-kernel at vger.kernel.org; Russell King <linux@armlinux.org.uk>; Fabio
> Estevam <fabio.estevam@nxp.com>; Sascha Hauer <kernel@pengutronix.de>;
> van.freenix at gmail.com; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH] arm: imx: suspend/resume: use outer_disable/resume
>
> On Tue, Dec 26, 2017 at 10:11:41AM +0000, Peng Fan wrote:
> >
> > Hi Aisheng,
> >
> > > -----Original Message-----
> > > From: Dong Aisheng [mailto:dongas86 at gmail.com]
> > > Sent: Tuesday, December 26, 2017 6:04 PM
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>; A.s. Dong
> > > <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org; Russell King
> > > <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> > > Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com;
> > > linux-arm-kernel at lists.infradead.org
> > > Subject: Re: [PATCH] arm: imx: suspend/resume: use
> > > outer_disable/resume
> > >
> > > On Tue, Dec 26, 2017 at 09:49:01AM +0000, Peng Fan wrote:
> > > > Hi Shawn
> > > >
> > > > > -----Original Message-----
> > > > > From: Shawn Guo [mailto:shawnguo at kernel.org]
> > > > > Sent: Tuesday, December 26, 2017 5:13 PM
> > > > > To: Peng Fan <peng.fan@nxp.com>
> > > > > Cc: A.s. Dong <aisheng.dong@nxp.com>;
> > > > > linux-kernel at vger.kernel.org; Russell King
> > > > > <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> > > > > Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com;
> > > > > linux-arm- kernel at lists.infradead.org
> > > > > Subject: Re: [PATCH] arm: imx: suspend/resume: use
> > > > > outer_disable/resume
> > > > >
> > > > > On Sun, Dec 10, 2017 at 08:07:18PM +0800, Peng Fan wrote:
> > > > > > Use outer_disable/resume for suspend/resume.
> > > > > > With the two APIs used, code could be simplified and easy to
> > > > > > extend to introduce l2c_write_sec for i.MX platforms when
> > > > > > moving Linux Kernel runs in non-secure world.
> > > > > >
> > > > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > > > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > > > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > > > > Cc: Russell King <linux@armlinux.org.uk>
> > > > > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> > > > >
> > > > > Changed 'arm: ' prefix to 'ARM: ', and applied patch.
> > > >
> > > > I just tested it on 6sx-sdb, seems this patch breaks 6sx. Could
> > > > you first drop this patch? I'll send out v2 fix the 6sx issue soon.
> > > >
> > >
> > > Yes, i tested mx6ul/mx6sl ok but mx6sx sdb failed.
> >
> > Thanks for the test.
> >
> > >
> > > After a few debug, it seems you removed the l2c310_early_resume in
> > > v7_cpu_resume which is shared between lower power idle and suspend.
> > >
> > > Current only mx6sx/mx6ul supports low power idle in upstream, but
> > > mx6ul is
> > > A7 with internal L2, that's probably why only mx6sx showed the issue.
> > >
> > > I did the following quick try to restore L2 after exit lower power
> > > idle, but still can meet occasional crash during booting.
> > >
> > > diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-
> > > imx/cpuidle-imx6sx.c index c5a5c3a..edce5bd 100644
> > > --- a/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > @@ -26,7 +26,7 @@ static int imx6sx_idle_finish(unsigned long val)
> > > * to adding conditional code for L2 cache type,
> > > * just call flush_cache_all() is fine.
> > > */
> > > - flush_cache_all();
> > > +// flush_cache_all();
> >
> > I think flush_cache_all is still needed, to flush L1 data, right?
> >
>
> I thought it will be done in generic cpu_suspend.
> See: __cpu_suspend_save()
>
> So we still need it?
After remove flush_cache_all, seems 6sx-sdb suspend/resume and low power idle both works.
Alought __cpu_suspend_save flush data, my understanding is there is chance to cache data/inst
before "wfi". Then we better keep flush_cache_all here?
Thanks,
Peng.
>
>
> Regards
> Dong Aisheng
> > > cpu_do_idle();
> > >
> > > return 0;
> > > @@ -49,7 +49,9 @@ static int imx6sx_enter_wait(struct cpuidle_device
> *dev,
> > > cpu_pm_enter();
> > > cpu_cluster_pm_enter();
> > >
> > > + outer_disable();
> > > cpu_suspend(0, imx6sx_idle_finish);
> > > + outer_resume();
> >
> > Yes, this is in my V2 patch.
> >
> > >
> > > cpu_cluster_pm_exit();
> > > cpu_pm_exit();
> > >
> > > As this changed the order to L2 restore and cpu resume, so i'm not
> > > quite sure if lower power idle still requres L2 restore before CPU
> > > resume or something else we're missing.
> >
> > In low power idle, L2 may also lose power, so outer_disable/resume is
> needed, I think.
> >
> > Thanks,
> > Peng.
> >
> > >
> > > Regards
> > > Dong Aisheng
> > >
> > > > Thanks,
> > > > Peng.
> > > >
> > > > >
> > > > > Shawn
^ permalink raw reply
* [PATCH v5 0/2] PCI: mediatek: Fixups for the IRQ handle routine and MT7622's class code
From: honghui.zhang at mediatek.com @ 2017-12-27 0:59 UTC (permalink / raw)
To: linux-arm-kernel
From: Honghui Zhang <honghui.zhang@mediatek.com>
Two fixups for mediatek's host bridge:
The first patch fixup the IRQ handle routine to avoid IRQ reentry which
may exist for both MT2712 and MT7622.
The second patch fixup class type for MT7622.
Change since v4:
- Only setup vendor ID for MT7622, igorning the device ID since mediatek's
host bridge driver does not cares about the device ID.
Change since v3:
- Setup the class type and vendor ID at the beginning of startup instead
of in a quirk.
- Add mediatek's vendor ID, it could be found in:
https://pcisig.com/membership/member-companies?combine=&page=4
Change since v2:
- Move the initialize of the iterate before the loop to fix an
INTx IRQ issue in the first patch
Change since v1:
- Add the second patch.
- Make the first patch's commit message more standard.
Honghui Zhang (2):
PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry
PCI: mediatek: Set up class type and vendor ID for MT7622
drivers/pci/host/pcie-mediatek.c | 23 ++++++++++++++++++-----
include/linux/pci_ids.h | 2 ++
2 files changed, 20 insertions(+), 5 deletions(-)
--
2.6.4
^ permalink raw reply
* [PATCH v5 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry
From: honghui.zhang at mediatek.com @ 2017-12-27 0:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514336394-17747-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
There maybe a same IRQ reentry scenario after IRQ received in current
IRQ handle flow:
EP device PCIe host driver EP driver
1. issue an IRQ
2. received IRQ
3. clear IRQ status
4. dispatch IRQ
5. clear IRQ source
The IRQ status was not successfully cleared at step 2 since the IRQ
source was not cleared yet. So the PCIe host driver may receive the
same IRQ after step 5. Then there's an IRQ reentry occurred.
Even worse, if the reentry IRQ was not an IRQ that EP driver expected,
it may not handle the IRQ. Then we may run into the infinite loop from
step 2 to step 4.
Clear the IRQ status after IRQ have been dispatched to avoid the IRQ
reentry.
This patch also fix another INTx IRQ issue by initialize the iterate
before the loop. If an INTx IRQ re-occurred while we are dispatching
the INTx IRQ, then iterate may start from PCI_NUM_INTX + INTX_SHIFT
instead of INTX_SHIFT for the second time entering the
for_each_set_bit_from() loop.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
Acked-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pci/host/pcie-mediatek.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index db93efd..fc29a9a 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -601,15 +601,16 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
unsigned long status;
u32 virq;
- u32 bit = INTX_SHIFT;
+ u32 bit;
while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
+ bit = INTX_SHIFT;
for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
- /* Clear the INTx */
- writel(1 << bit, port->base + PCIE_INT_STATUS);
virq = irq_find_mapping(port->irq_domain,
bit - INTX_SHIFT);
generic_handle_irq(virq);
+ /* Clear the INTx */
+ writel(1 << bit, port->base + PCIE_INT_STATUS);
}
}
@@ -619,10 +620,10 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
- /* Clear the MSI */
- writel(1 << bit, port->base + PCIE_IMSI_STATUS);
virq = irq_find_mapping(port->msi_domain, bit);
generic_handle_irq(virq);
+ /* Clear the MSI */
+ writel(1 << bit, port->base + PCIE_IMSI_STATUS);
}
}
/* Clear MSI interrupt status */
--
2.6.4
^ permalink raw reply related
* [PATCH v5 2/2] PCI: mediatek: Set up class type and vendor ID for MT7622
From: honghui.zhang at mediatek.com @ 2017-12-27 0:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514336394-17747-1-git-send-email-honghui.zhang@mediatek.com>
From: Honghui Zhang <honghui.zhang@mediatek.com>
The hardware default value of IDs and class type is not correct,
fix that by setup the correct values before start up.
Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
---
drivers/pci/host/pcie-mediatek.c | 12 ++++++++++++
include/linux/pci_ids.h | 2 ++
2 files changed, 14 insertions(+)
diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
index fc29a9a..62aac0ea 100644
--- a/drivers/pci/host/pcie-mediatek.c
+++ b/drivers/pci/host/pcie-mediatek.c
@@ -74,6 +74,10 @@
/* PCIe V2 per-port registers */
#define PCIE_MSI_VECTOR 0x0c0
+
+#define PCIE_CONF_ID 0x100
+#define PCIE_CONF_CLASS 0x104
+
#define PCIE_INT_MASK 0x420
#define INTX_MASK GENMASK(19, 16)
#define INTX_SHIFT 16
@@ -393,6 +397,14 @@ static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
val |= PCIE_CSR_LTSSM_EN(port->slot) |
PCIE_CSR_ASPM_L1_EN(port->slot);
writel(val, pcie->base + PCIE_SYS_CFG_V2);
+
+ /* Set up vendor ID and device ID for MT7622*/
+ val = PCI_VENDOR_ID_MEDIATEK;
+ writel(val, port->base + PCIE_CONF_ID);
+
+ /* Set up class code for MT7622 */
+ val = PCI_CLASS_BRIDGE_PCI << 16;
+ writel(val, port->base + PCIE_CONF_CLASS);
}
/* Assert all reset signals */
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index ab20dc5..2480b0e 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2113,6 +2113,8 @@
#define PCI_VENDOR_ID_MYRICOM 0x14c1
+#define PCI_VENDOR_ID_MEDIATEK 0x14c3
+
#define PCI_VENDOR_ID_TITAN 0x14D2
#define PCI_DEVICE_ID_TITAN_010L 0x8001
#define PCI_DEVICE_ID_TITAN_100L 0x8010
--
2.6.4
^ permalink raw reply related
* [PATCH 1/2] clk: rename clk_core_get_boundaries() to clk_hw_get_boundaries() and expose
From: Stephen Boyd @ 2017-12-27 1:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <8EC4D15B-4A89-43FA-953E-95AF81417067@gmail.com>
On 12/25, Alexander Kochetkov wrote:
>
> > 21 ???. 2017 ?., ? 23:07, Stephen Boyd <sboyd@codeaurora.org> ???????(?):
> >
> > Can you convert to the determine_rate op instead of round_rate?
> > That function should tell you the min/max limits so that you
> > don't need to query that information from the core.
>
> I converted rockchip_fractional_approximation() to rockchip_determine_rate() (see the patch attached).
> If it increase parent?s clock for out of limits value, than clock request will fail with -EINVAL, like
> with round_rate() approach.
>
> The problem is that min/max limits provided to determine_rate() is for clock for which the determine_rate()
> was called. While rockchip_determine_rate() (rockchip_fractional_approximation()) requires information
> about parent clock limits.
Are these limits the min/max limits that the parent clk can
output at? Or the min/max limits that software has constrained on
the clk?
>
> How can I know parents clock limits for current clock? Implement determine_rate() for each parent clocks
> the same way I did for this one clock?
If the parent can change rate, then the idea is that the child
will calculate the limits that it can handle based on what it can
do with the incoming min/max constraints, and then call
__clk_determine_rate() on its parent with a request structure
that has limits for whatever the child clk is able to handle. The
parent can then determine a rate it can output that's within that
range and tell the child clk if it will satisfy the constraints
or not along with the resulting rate it will output when the
__clk_determine_rate() function returns. I would expect the
constraints to get closer together the higher in the tree we go.
I haven't looked in detail at this
rockchip_fractional_approximation() code, but it shouldn't be
doing the work of both the child rate determination and the
parent rate determination in one place. It should work with the
parent to figure out the rate the parent can provide and then
figure out how to achieve the desired rate from there.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [RFC PATCH V1 2/2] clk: add lock for clk_core_is_enabled
From: Stephen Boyd @ 2017-12-27 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513935965-12909-2-git-send-email-aisheng.dong@nxp.com>
On 12/22, Dong Aisheng wrote:
> According to design doc, .is_enabled should be protected by enable lock.
> Then users don't have to protect it against enable/disable operation
> in clock drivers.
>
> See: Documentation/clk.txt
> "The enable lock is a spinlock and is held across calls to the .enable,
> .disable and .is_enabled operations."
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> drivers/clk/clk.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index e24968f..d6e2d5c 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -198,14 +198,19 @@ static bool clk_core_is_prepared(struct clk_core *core)
>
> static bool clk_core_is_enabled(struct clk_core *core)
> {
> + unsigned long flags;
> bool ret = false;
>
> + flags = clk_enable_lock();
> +
> /*
> * .is_enabled is only mandatory for clocks that gate
> * fall back to software usage counter if .is_enabled is missing
> */
> - if (!core->ops->is_enabled)
> + if (!core->ops->is_enabled) {
> + clk_enable_unlock(flags);
> return core->enable_count;
> + }
>
> /*
> * Check if clock controller's device is runtime active before
> @@ -230,6 +235,8 @@ static bool clk_core_is_enabled(struct clk_core *core)
> if (core->dev)
> pm_runtime_put(core->dev);
>
> + clk_enable_unlock(flags);
> +
> return ret;
> }
It doesn't really make any sense to hold the enable lock inside
the clk_core_is_enabled() function, unless you want to do
something else with the information of the enable state with that
lock held. Otherwise, seeing if a clk is enabled is a one-shot
read of the enabled state, which could just as easily change
after the function returns because the lock is released.
We should update the documentation.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH v6 4/5] clk: aspeed: Register gated clocks
From: Stephen Boyd @ 2017-12-27 1:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513910633.2743.79.camel@kernel.crashing.org>
On 12/22, Benjamin Herrenschmidt wrote:
> On Fri, 2017-12-22 at 13:36 +1100, Benjamin Herrenschmidt wrote:
> >
> > > No you can't sleep here. It needs to delay because this is inside
> > > spinlock_irqsave.
> >
> > Additionally you really don't want to delay for 10ms with interrupts
> > off :-(
> >
> > Sadly, it looks like the clk framework already calls you with spinlock
> > irqsafe, which is a rather major suckage.
> >
> > Stephen, why is that so ? That pretty much makes it impossible to
> > do sleeping things, which prevents things like i2c based clock
> > controllers etc...
>
> I noticed we do have a few i2c based clock drivers... how are they ever
> supposed to work ? i2c bus controllers are allowed to sleep and the i2c
> core takes mutexes...
We have clk_prepare()/clk_unprepare() for sleeping suckage. You
can use that, and i2c based clk drivers do that today.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Shawn Guo @ 2017-12-27 1:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR04MB3221C1B5362775C72B34B01088060@DB6PR04MB3221.eurprd04.prod.outlook.com>
On Tue, Dec 26, 2017 at 09:49:01AM +0000, Peng Fan wrote:
> Hi Shawn
>
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo at kernel.org]
> > Sent: Tuesday, December 26, 2017 5:13 PM
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: A.s. Dong <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org; Russell
> > King <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> > Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com; linux-arm-
> > kernel at lists.infradead.org
> > Subject: Re: [PATCH] arm: imx: suspend/resume: use outer_disable/resume
> >
> > On Sun, Dec 10, 2017 at 08:07:18PM +0800, Peng Fan wrote:
> > > Use outer_disable/resume for suspend/resume.
> > > With the two APIs used, code could be simplified and easy to extend to
> > > introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
> > > runs in non-secure world.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > Cc: Russell King <linux@armlinux.org.uk>
> > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Changed 'arm: ' prefix to 'ARM: ', and applied patch.
>
> I just tested it on 6sx-sdb, seems this patch breaks 6sx. Could you first drop this
> patch? I'll send out v2 fix the 6sx issue soon.
Patch dropped.
^ permalink raw reply
* [RFC PATCH V1 1/2] clk: use atomic runtime pm api in clk_core_is_enabled
From: Stephen Boyd @ 2017-12-27 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513935965-12909-1-git-send-email-aisheng.dong@nxp.com>
On 12/22, Dong Aisheng wrote:
> Current clk_pm_runtime_put is using pm_runtime_put_sync which
> is not safe to be called in clk_core_is_enabled as it should
> be able to run in atomic context.
>
> Thus use pm_runtime_put instead which is atomic safe.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> Fixes: 9a34b45397e5 ("clk: Add support for runtime PM")
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH net-next v8 1/2] dt-bindings: net: add DT bindings for Socionext UniPhier AVE
From: Masahiro Yamada @ 2017-12-27 1:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514164238-28901-2-git-send-email-hayashi.kunihiko@socionext.com>
2017-12-25 10:10 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> DT bindings for the AVE ethernet controller found on Socionext's
> UniPhier platforms.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/net/socionext,uniphier-ave4.txt | 47 ++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
>
> diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
> new file mode 100644
> index 0000000..8b03668
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
> @@ -0,0 +1,47 @@
> +* Socionext AVE ethernet controller
> +
> +This describes the devicetree bindings for AVE ethernet controller
> +implemented on Socionext UniPhier SoCs.
> +
> +Required properties:
> + - compatible: Should be
> + - "socionext,uniphier-pro4-ave4" : for Pro4 SoC
> + - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
> + - "socionext,uniphier-ld11-ave4" : for LD11 SoC
> + - "socionext,uniphier-ld20-ave4" : for LD20 SoC
> + - reg: Address where registers are mapped and size of region.
> + - interrupts: Should contain the MAC interrupt.
> + - phy-mode: See ethernet.txt in the same directory. Allow to choose
> + "rgmii", "rmii", or "mii" according to the PHY.
> + - phy-handle: Should point to the external phy device.
> + See ethernet.txt file in the same directory.
> + - clocks: A phandle to the clock for the MAC.
> +
> +Optional properties:
> + - resets: A phandle to the reset control for the MAC.
> + - local-mac-address: See ethernet.txt in the same directory.
> +
> +Required subnode:
> + - mdio: A container for child nodes representing phy nodes.
> + See phy.txt in the same directory.
> +
> +Example:
> +
> + ether: ethernet at 65000000 {
> + compatible = "socionext,uniphier-ld20-ave4";
> + reg = <0x65000000 0x8500>;
> + interrupts = <0 66 4>;
> + phy-mode = "rgmii";
> + phy-handle = <ðphy>;
> + clocks = <&sys_clk 6>;
> + resets = <&sys_rst 6>;
> + local-mac-address = [00 00 00 00 00 00];
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ethphy: ethphy at 1 {
> + reg = <1>;
> + };
> + };
Andrew Lunn suggested to put a blank line before the "mdio" subnode in v7:
https://patchwork.kernel.org/patch/10127461/
Does it apply to the "ethphy" subnode, too?
Looks like you have a chance for v9. Please consider it.
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: Peng Fan @ 2017-12-27 1:57 UTC (permalink / raw)
To: linux-arm-kernel
Use outer_disable/resume for suspend/resume.
With the two APIs used, code could be simplified and easy to extend
to introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
runs in non-secure world.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
---
V2:
Fix 6SX booting. The V1 patch does not take 6SX low power idle into
consideration.
Tested on 6Q-SDB and 6SX-SDB.
arch/arm/mach-imx/cpuidle-imx6sx.c | 2 ++
arch/arm/mach-imx/pm-imx6.c | 2 ++
arch/arm/mach-imx/suspend-imx6.S | 24 ------------------------
3 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c
index c5a5c3a70ab1..b35841d133dc 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -49,7 +49,9 @@ static int imx6sx_enter_wait(struct cpuidle_device *dev,
cpu_pm_enter();
cpu_cluster_pm_enter();
+ outer_disable();
cpu_suspend(0, imx6sx_idle_finish);
+ outer_resume();
cpu_cluster_pm_exit();
cpu_pm_exit();
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index ecdf071653d4..153a0afc7645 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -392,8 +392,10 @@ static int imx6q_pm_enter(suspend_state_t state)
imx6_enable_rbc(true);
imx_gpc_pre_suspend(true);
imx_anatop_pre_suspend();
+ outer_disable();
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
+ outer_resume();
if (cpu_is_imx6q() || cpu_is_imx6dl())
imx_smp_prepare();
imx_anatop_post_resume();
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 76ee2ceec8d5..324f6b165e82 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -74,24 +74,6 @@
.align 3
- .macro sync_l2_cache
-
- /* sync L2 cache to drain L2's buffers to DRAM. */
-#ifdef CONFIG_CACHE_L2X0
- ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
- teq r11, #0
- beq 6f
- mov r6, #0x0
- str r6, [r11, #L2X0_CACHE_SYNC]
-1:
- ldr r6, [r11, #L2X0_CACHE_SYNC]
- ands r6, r6, #0x1
- bne 1b
-6:
-#endif
-
- .endm
-
.macro resume_mmdc
/* restore MMDC IO */
@@ -185,9 +167,6 @@ ENTRY(imx6_suspend)
str r9, [r11, #MX6Q_SRC_GPR1]
str r1, [r11, #MX6Q_SRC_GPR2]
- /* need to sync L2 cache before DSM. */
- sync_l2_cache
-
ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
/*
* put DDR explicitly into self-refresh and
@@ -342,8 +321,5 @@ ENDPROC(imx6_suspend)
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
-#ifdef CONFIG_CACHE_L2X0
- bl l2c310_early_resume
-#endif
b cpu_resume
ENDPROC(v7_cpu_resume)
--
2.14.1
^ permalink raw reply related
* [PATCH] ARM: make ARCH_S3C24XX select USE_OF and clean-up boot/dts/Makefile
From: Masahiro Yamada @ 2017-12-27 2:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJKOXPfd+R0z-RcNLWn=rS6U0uBhDsZS8d-f-b4+jUeQBruc5Q@mail.gmail.com>
2017-12-26 2:39 GMT+09:00 Krzysztof Kozlowski <krzk@kernel.org>:
> On Sun, Dec 24, 2017 at 6:19 PM, Masahiro Yamada
> <yamada.masahiro@socionext.com> wrote:
>> 2017-12-22 21:41 GMT+09:00 Krzysztof Kozlowski <krzk@kernel.org>:
>>> On Mon, Nov 27, 2017 at 3:19 AM, Masahiro Yamada
>>> <yamada.masahiro@socionext.com> wrote:
>>>> ARCH_S3C24XX is a very exceptional platform that some DT files in
>>>> arch/arm/boot/dts/, but does not select USE_OF.
>>>
>>> Not entirely. The platform does select USE_OF - when MACH_S3C2416_DT
>>> is chosen. For other boards USE_OF is not necessary because they do
>>> not use DT. Why you need to select it for entire arch?
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>>
>> The reason is simple - to avoid compile error.
>>
>>
>> If I simply drop ifeq ($(CONFIG_OF),y)
>> but do not select ARCH_S3C24XX,
>> s3c2410_defconfig failed to build.
>>
>>
>> $ make -s ARCH=arm mrproper
>> $ make -s ARCH=arm s3c2410_defconfig
>> $ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- dtbs
>> ...
>>
>> DTC arch/arm/boot/dts/s3c2416-smdk2416.dtb
>> /bin/sh: 1: ./scripts/dtc/dtc: not found
>> scripts/Makefile.lib:310: recipe for target
>> 'arch/arm/boot/dts/s3c2416-smdk2416.dtb' failed
>> make[1]: *** [arch/arm/boot/dts/s3c2416-smdk2416.dtb] Error 127
>> arch/arm/Makefile:349: recipe for target 'dtbs' failed
>> make: *** [dtbs] Error 2
>>
>>
>> Another solution would be to enable dtb by CONFIG_MACH_S3C2416_DT.
>>
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index d0381e9..950b5dd 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -800,7 +798,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>> rk3288-veyron-pinky.dtb \
>> rk3288-veyron-speedy.dtb \
>> rk3288-vyasa.dtb
>> -dtb-$(CONFIG_ARCH_S3C24XX) += \
>> +dtb-$(CONFIG_MACH_S3C2416_DT) += \
>> s3c2416-smdk2416.dtb
>> dtb-$(CONFIG_ARCH_S3C64XX) += \
>> s3c6410-mini6410.dtb \
>>
>>
>>
>> If you migrate S3C24XX platform to DT,
>> per-board CONFIG option will go away.
>>
>> So, I think dtb-$(CONFIG_ARCH_S3C24XX) is OK.
>
> I think this second solution - using CONFIG_MACH_S3C2416_DT - makes
> more sense because:
> 1, S3C24xx will not be converted to DT. This is a legacy platform.
> 2. DT version supports only part of boards and peripherals so most of
> existing platforms will use non-DT boardfiles. Enabling OF on all of
> them is not useful for them.
I do not care this much.
I leave this up to you (and ARM-SOC maintainers).
> 3. The same error and solution probably applies to MACH_S3C64XX.
Maybe no.
Looking at arch/arm/mach-s3c64xx/Kconfig,
ARCH_S3C64XX depends on ARCH_MULTI_V6.
Multiplatform selects USE_OF.
>
> Best regards,
> Krzysztof
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH 0/3] [v11] pinctrl: qcom: add support for sparse GPIOs
From: Stephen Boyd @ 2017-12-27 2:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYtMbACG0D2zjgw-kN_3pb_VDGH_3DDhyMQD92eE5P0Gw@mail.gmail.com>
On 12/21, Linus Walleij wrote:
> Hi Timur,
>
> thank you for your perseverance. I am sorry that I am sometimes not
> fast to respond :(
>
> On Wed, Dec 20, 2017 at 8:10 PM, Timur Tabi <timur@codeaurora.org> wrote:
>
> > Patch 1 reverts an old patch that triggers a get_direction of every
> > pin upon init, without attempting to request the pins first. The
> > direction is already being queried when the pin is requested.
> >
> > Patch 2 adds support to pinctrl-msm for "unavailable" GPIOs.
>
> I have applied both of these to the pinctrl "devel" branch so we
> can see if all is fine.
>
> They have Stephen's ACK so I am happy with them, I am just
> still slightly worried about possible regressions because of
> patch 1.
>
> > Patch 3 extends that support to pinctrl-qdf2xxx. A recent ACPI change
> > on QDF2400 platforms blocks access to most pins, so the driver can only
> > register a subset.
>
> I see this one is still under discussion.
>
> If nothing drastic happens with patch 1/2 in linux-next
> it should be fine if you just resend this single patch in subsequent
> submissions.
>
If we go with my suggestion, patch 2 is not necessary and should
be dropped. The different approaches come down to expressing
which pins are available through the gpio valid mask, or through
the npins field of the msm pinctrl driver. Also, my approach
covers more than just GPIOs, it covers irqs and adjusts the
pinctrl pin request function so that pinctrl can't request
unavailable pins.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] arm64: dts: ls1088a: add DT node of watchdog
From: ying.zhang at freescale.com @ 2017-12-27 2:02 UTC (permalink / raw)
To: linux-arm-kernel
From: Zhang Ying-22455 <ying.zhang22455@nxp.com>
There are eight cores in ls1088a and each core has an watchdog,
ls1088a can use sp805-wdt driver, so we just add DT node for it.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 56 ++++++++++++++++++++++++
1 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index f5f29a2..49366d1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -369,6 +369,62 @@
status = "disabled";
};
+ cluster1_core0_watchdog: wdt at c000000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc000000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core1_watchdog: wdt at c010000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core2_watchdog: wdt at c020000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc020000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core3_watchdog: wdt at c030000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc030000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core0_watchdog: wdt at c100000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc100000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core1_watchdog: wdt at c110000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc110000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core2_watchdog: wdt at c120000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc120000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core3_watchdog: wdt at c130000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc130000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
gpio0: gpio at 2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
--
1.7.1
^ permalink raw reply related
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Shawn Guo @ 2017-12-27 2:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226103629.GC11724@b29396-OptiPlex-7040>
On Tue, Dec 26, 2017 at 06:36:29PM +0800, Dong Aisheng wrote:
> > > > diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-
> > > > imx/cpuidle-imx6sx.c
> > > > index c5a5c3a..edce5bd 100644
> > > > --- a/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > > +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > > @@ -26,7 +26,7 @@ static int imx6sx_idle_finish(unsigned long val)
> > > > * to adding conditional code for L2 cache type,
> > > > * just call flush_cache_all() is fine.
> > > > */
> > > > - flush_cache_all();
> > > > +// flush_cache_all();
> > >
> > > I think flush_cache_all is still needed, to flush L1 data, right?
> > >
> >
> > I thought it will be done in generic cpu_suspend.
> > See: __cpu_suspend_save()
> >
> > So we still need it?
> >
>
> Shawn,
>
> Do you have comments about it?
It seems that there are comments about this flush_cache_all() call right
above it. To be safe, I would suggest to keep it as it is.
Shawn
^ permalink raw reply
* [PATCH v3 1/6] ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM
From: Shawn Guo @ 2017-12-27 2:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513940353-6145-2-git-send-email-s.riedmueller@phytec.de>
On Fri, Dec 22, 2017 at 11:59:08AM +0100, Stefan Riedmueller wrote:
> This patch adds basic support for PHYTEC phyCORE-i.MX 6 SOM with i.MX
> 6Quad/Dual or i.MX 6DualLight/Solo.
>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> Signed-off-by: Stefan Christ <s.christ@phytec.de>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
> arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 282 ++++++++++++++++++++++
> 1 file changed, 282 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
> new file mode 100644
> index 0000000..8501ac6
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
> @@ -0,0 +1,282 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2017 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp <c.hemp@phytec.de>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "PHYTEC phyCORE-i.MX 6";
> + compatible = "phytec,imx6qdl-pcm058", "fsl,imx6qdl";
> +
> + aliases {
> + rtc1 = &da9062_rtc;
> + rtc2 = &snvs_rtc;
> + };
> +
> + /*
> + * Set the minimum memory size here and
> + * let the bootloader set the real size.
> + */
> + memory at 10000000 {
> + device_type = "memory";
> + reg = <0x10000000 0x8000000>;
> + };
> +
> + gpio_leds_som: somleds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpioleds_som>;
> +
> + som_green {
We generally use hyphen rather than underscore in node name. Also I
would suggest to have 'led' in the name to tell what the device is,
maybe 'led-green'?
> + label = "phycore:green";
> + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&ecspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + flash: flash at 0 {
While it's all good to name the node in a general way, the label can be
specific, like:
m25p80: flash at 0 {
...
}
Even better, if the label is not really needed, just drop it.
> + compatible = "m25p80";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
> + status = "disabled";
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-handle = <ðphy>;
> + phy-mode = "rgmii";
> + phy-supply = <&vdd_eth_io>;
> + phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
> + status = "disabled";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy: ethernet-phy at 3 {
> + reg = <3>;
> + txc-skew-ps = <1680>;
> + rxc-skew-ps = <1860>;
> + };
> + };
> +};
> +
> +&gpmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpmi_nand>;
> + nand-on-flash-bbt;
> + status = "disabled";
> +};
> +
> +&i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + eeprom: eeprom at 50 {
Is the label used at all?
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> +
> + pmic0: pmic at 58 {
Ditto
> + compatible = "dlg,da9062";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + reg = <0x58>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> +
> + da9062_rtc: rtc {
> + compatible = "dlg,da9062-rtc";
> + };
> +
> + da9062_wdt: watchdog {
Ditto
> + compatible = "dlg,da9062-watchdog";
> + };
> +
> + da9062_reg: regulators {
Ditto
Shawn
> + vdd_arm: buck1 {
> + regulator-name = "vdd_arm";
> + regulator-min-microvolt = <730000>;
> + regulator-max-microvolt = <1380000>;
> + regulator-always-on;
> + };
> +
> + vdd_soc: buck2 {
> + regulator-name = "vdd_soc";
> + regulator-min-microvolt = <730000>;
> + regulator-max-microvolt = <1380000>;
> + regulator-always-on;
> + };
> +
> + vdd_ddr3_1p5: buck3 {
> + regulator-name = "vdd_ddr3";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> +
> + vdd_eth_1p2: buck4 {
> + regulator-name = "vdd_eth";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + vdd_snvs: ldo1 {
> + regulator-name = "vdd_snvs";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-always-on;
> + };
> +
> + vdd_high: ldo2 {
> + regulator-name = "vdd_high";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-always-on;
> + };
> +
> + vdd_eth_io: ldo3 {
> + regulator-name = "vdd_eth_io";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + };
> +
> + vdd_emmc_1p8: ldo4 {
> + regulator-name = "vdd_emmc";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> + };
> + };
> +};
> +
> +®_arm {
> + vin-supply = <&vdd_arm>;
> +};
> +
> +®_pu {
> + vin-supply = <&vdd_soc>;
> +};
> +
> +®_soc {
> + vin-supply = <&vdd_soc>;
> +};
> +
> +&snvs_poweroff {
> + status = "okay";
> +};
> +
> +&usdhc4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc4>;
> + bus-width = <8>;
> + non-removable;
> + vmmc-supply = <&vdd_emmc_1p8>;
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
> + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpioleds_som: gpioledssomgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpmi_nand: gpminandgrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
> + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
> + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
> + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
> + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
> + MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
> + MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
> + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
> + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
> + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
> + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
> + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
> + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
> + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
> + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
> + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
> + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
> + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + >;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Peng Fan @ 2017-12-27 2:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR04MB3221C1B5362775C72B34B01088060@DB6PR04MB3221.eurprd04.prod.outlook.com>
Hi Shawn,
> >
> > On Sun, Dec 10, 2017 at 08:07:18PM +0800, Peng Fan wrote:
> > > Use outer_disable/resume for suspend/resume.
> > > With the two APIs used, code could be simplified and easy to extend
> > > to introduce l2c_write_sec for i.MX platforms when moving Linux
> > > Kernel runs in non-secure world.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > Cc: Russell King <linux@armlinux.org.uk>
> > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Changed 'arm: ' prefix to 'ARM: ', and applied patch.
>
> I just tested it on 6sx-sdb, seems this patch breaks 6sx. Could you first drop this
> patch? I'll send out v2 fix the 6sx issue soon.
I just send out V2 patch to fix the 6sx issue. Sorry for the inconvenience about V1
that break 6sx. Please review.
Thanks,
Peng.
.
>
> Thanks,
> Peng.
>
> >
> > Shawn
^ permalink raw reply
* [PATCH 1/1] power: reset: remove unused imx-snvs-poweroff driver
From: Fabio Estevam @ 2017-12-27 2:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513938539-20873-1-git-send-email-aisheng.dong@nxp.com>
On Fri, Dec 22, 2017 at 8:28 AM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> There's no user of it in kernel now and it basically functions the same
> as the generic syscon-poweroff.c to which we have already switched.
> So let's remove it.
>
> Cc: Robin Gong <yibin.gong@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH v3 2/6] ARM: dts: imx6: Add initial support for phyBOARD-Mira
From: Shawn Guo @ 2017-12-27 2:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513940353-6145-3-git-send-email-s.riedmueller@phytec.de>
On Fri, Dec 22, 2017 at 11:59:09AM +0100, Stefan Riedmueller wrote:
> This patch adds basic support for PHYTEC phyBOARD-Mira as carrier board
> for PHYTEC phyCORE-i.MX 6.
>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> Signed-off-by: Stefan Christ <s.christ@phytec.de>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
> arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi | 390 +++++++++++++++++++++++++++++
> 1 file changed, 390 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
> new file mode 100644
> index 0000000..45d8c0c
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
> @@ -0,0 +1,390 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2017 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp <c.hemp@phytec.de>
> + */
> +
> +
> +/ {
> + aliases {
> + rtc0 = &i2c_rtc;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <7>;
> + power-supply = <®_backlight>;
> + pwms = <&pwm1 0 5000000>;
> + status = "okay";
> + };
> +
> + gpio_leds: leds {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpioleds>;
> + status = "disabled";
> +
Generally we do not have newlines in middle of property list.
> + compatible = "gpio-leds";
Please put 'compatible' at the beginning of property list and always
have 'status' be the end of list.
> +
> + red {
> + label = "phyboard-mira:red";
> + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
> + };
> +
> + green {
> + label = "phyboard-mira:green";
> + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
> + };
> +
> + blue {
> + label = "phyboard-mira:blue";
> + gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "mmc0";
> + };
> + };
> +
> + reg_backlight: regulator-backlight {
> + compatible = "regulator-fixed";
> + regulator-name = "backlight_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_en_switch: regulator-en-switch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_en_switch>;
> + compatible = "regulator-fixed";
Move the 'compatible' forward.
> + regulator-name = "Enable Switch";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
> + regulator-always-on;
> + };
> +
> + reg_flexcan1: regulator-flexcan1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1_en>;
> + compatible = "regulator-fixed";
> + regulator-name = "flexcan1-reg";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_panel: regulator-panel {
> + compatible = "regulator-fixed";
> + regulator-name = "panel-power-supply";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + regulator-always-on;
> + };
> +
> + reg_pcie: regulator-pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie_reg>;
> + compatible = "regulator-fixed";
> + regulator-name = "mPCIe_1V5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usb_h1_vbus: usb-h1-vbus {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbh1_vbus>;
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usbotg_vbus: usbotg-vbus {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg_vbus>;
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + panel {
> + compatible = "auo,g104sn02";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_en>;
> + power-supply = <®_panel>;
> + enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
> +
Drop the newline.
Shawn
> + backlight = <&backlight>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&lvds0_out>;
> + };
> + };
> + };
> +};
> +
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + xceiver-supply = <®_flexcan1>;
> + status = "disabled";
> +};
> +
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmicec>;
> + ddc-i2c-bus = <&i2c2>;
> + status = "disabled";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + clock-frequency = <400000>;
> + status = "disabled";
> +
> + stmpe: touchctrl at 44 {
> + compatible = "st,stmpe811";
> + reg = <0x44>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <12 IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_stmpe>;
> + status = "disabled";
> +
> + stmpe_touchscreen {
> + compatible = "st,stmpe-ts";
> + st,sample-time = <4>;
> + st,mod-12b = <1>;
> + st,ref-sel = <0>;
> + st,adc-freq = <1>;
> + st,ave-ctrl = <1>;
> + st,touch-det-delay = <2>;
> + st,settling = <2>;
> + st,fraction-z = <7>;
> + st,i-drive = <1>;
> + };
> + };
> +
> + i2c_rtc: rtc at 68 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc_int>;
> + compatible = "microcrystal,rv4162";
> + reg = <0x68>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + clock-frequency = <100000>;
> + status = "disabled";
> +};
> +
> +&ldb {
> + status = "okay";
> +
> + lvds-channel at 0 {
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> + status = "disabled";
> +
> + port at 4 {
> + reg = <4>;
> +
> + lvds0_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
> + vpcie-supply = <®_pcie>;
> + status = "disabled";
> +};
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +&usbh1 {
> + vbus-supply = <®_usb_h1_vbus>;
> + disable-over-current;
> + status = "disabled";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> + vbus-supply = <®_usbotg_vbus>;
> + disable-over-current;
> + status = "disabled";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl_panel_en: panelen1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
> + >;
> + };
> +
> + pinctrl_en_switch: enswitchgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan1_en: flexcan1engrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1
> + >;
> + };
> +
> + pinctrl_gpioleds: gpioledsgrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0
> + >;
> + };
> +
> + pinctrl_hdmicec: hdmicecgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
> + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1
> + >;
> + };
> +
> + pinctrl_pcie_reg: pciereggrp {
> + fsl,pins = <MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1>;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_rtc_int: rtcintgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
> + >;
> + };
> +
> + pinctrl_stmpe: stmpegrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbh1_vbus: usbh1vbusgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
> + >;
> + };
> +
> + pinctrl_usbotg_vbus: usbotgvbusgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */
> + >;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: Shawn Guo @ 2017-12-27 2:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514339867-28946-1-git-send-email-peng.fan@nxp.com>
On Wed, Dec 27, 2017 at 09:57:47AM +0800, Peng Fan wrote:
> Use outer_disable/resume for suspend/resume.
> With the two APIs used, code could be simplified and easy to extend
> to introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
> runs in non-secure world.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Dong Aisheng <aisheng.dong@nxp.com>
@Aisheng, can you please give it a test?
Shawn
^ permalink raw reply
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: A.s. Dong @ 2017-12-27 2:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171227023207.GX23070@X250>
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo at kernel.org]
> Sent: Wednesday, December 27, 2017 10:32 AM
> To: Peng Fan <peng.fan@nxp.com>
> Cc: A.s. Dong <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org; Russell
> King <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH V2] ARM: imx: suspend/resume: use
> outer_disable/resume
>
> On Wed, Dec 27, 2017 at 09:57:47AM +0800, Peng Fan wrote:
> > Use outer_disable/resume for suspend/resume.
> > With the two APIs used, code could be simplified and easy to extend to
> > introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
> > runs in non-secure world.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Cc: Russell King <linux@armlinux.org.uk>
> > Cc: Dong Aisheng <aisheng.dong@nxp.com>
>
> @Aisheng, can you please give it a test?
>
Yes, of course.
Regards
Dong Aisheng
> Shawn
^ permalink raw reply
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