* [PATCH 1/2] ARM: dts: imx6: RDU2: disable internal watchdog
From: Andrey Smirnov @ 2017-12-27 3:56 UTC (permalink / raw)
To: linux-arm-kernel
The system has an external watchdog in the environment processor
so the internal watchdog is of no use.
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel at lists.infradead.org
Cc: devicetree at vger.kernel.org
Cc: linux-kernel at vger.kernel.org
Cc: cphealy at gmail.com
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
---
arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
index 6bef9a98678e..818bfc8692a5 100644
--- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi
@@ -838,6 +838,10 @@
status = "okay";
};
+&wdog1 {
+ status = "disabled";
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
^ permalink raw reply related
* [PATCH 09/11 v3] ARM: orion5x: constify gpio_led
From: Arvind Yadav @ 2017-12-27 3:09 UTC (permalink / raw)
To: linux-arm-kernel
gpio_led are not supposed to change at runtime.
struct gpio_led_platform_data working with const gpio_led
provided by <linux/leds.h>. So mark the non-const structs
as const.
Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
---
changes in v2:
The GPIO LED driver can be built as a module, it can
be loaded after the init sections have gone away.
So removed '__initconst'.
changes in v3:
Fix build error.
arch/arm/mach-orion5x/board-d2net.c | 2 +-
arch/arm/mach-orion5x/dns323-setup.c | 2 +-
arch/arm/mach-orion5x/ls_hgl-setup.c | 2 +-
arch/arm/mach-orion5x/mv2120-setup.c | 2 +-
arch/arm/mach-orion5x/net2big-setup.c | 2 +-
arch/arm/mach-orion5x/rd88f5182-setup.c | 2 +-
arch/arm/mach-orion5x/ts409-setup.c | 2 +-
arch/arm/mach-orion5x/wrt350n-v2-setup.c | 2 +-
8 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/mach-orion5x/board-d2net.c b/arch/arm/mach-orion5x/board-d2net.c
index a89376a..55d6562 100644
--- a/arch/arm/mach-orion5x/board-d2net.c
+++ b/arch/arm/mach-orion5x/board-d2net.c
@@ -54,7 +54,7 @@
#define D2NET_GPIO_BLUE_LED_BLINK_CTRL 16
#define D2NET_GPIO_BLUE_LED_OFF 23
-static struct gpio_led d2net_leds[] = {
+static const struct gpio_led d2net_leds[] = {
{
.name = "d2net:blue:sata",
.default_trigger = "default-on",
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index cd483bf..792a56e 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -221,7 +221,7 @@ static struct gpio_led dns323ab_leds[] = {
};
-static struct gpio_led dns323c_leds[] = {
+static const struct gpio_led dns323c_leds[] = {
{
.name = "power:blue",
.gpio = DNS323C_GPIO_LED_POWER,
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 47ba6e0..c394281 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -86,7 +86,7 @@ static struct i2c_board_info __initdata ls_hgl_i2c_rtc = {
#define LS_HGL_GPIO_LED_PWR 0
-static struct gpio_led ls_hgl_led_pins[] = {
+static const struct gpio_led ls_hgl_led_pins[] = {
{
.name = "alarm:red",
.gpio = LS_HGL_GPIO_LED_ALARM,
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index 2bf8ec7..724c08a 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -136,7 +136,7 @@ static struct i2c_board_info __initdata mv2120_i2c_rtc = {
.irq = 0,
};
-static struct gpio_led mv2120_led_pins[] = {
+static const struct gpio_led mv2120_led_pins[] = {
{
.name = "mv2120:blue:health",
.gpio = 0,
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index bf6be4c..7d59888 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -214,7 +214,7 @@ static void __init net2big_sata_power_init(void)
#define NET2BIG_GPIO_SATA0_BLUE_LED 17
#define NET2BIG_GPIO_SATA1_BLUE_LED 13
-static struct gpio_led net2big_leds[] = {
+static const struct gpio_led net2big_leds[] = {
{
.name = "net2big:red:power",
.gpio = NET2BIG_GPIO_PWR_RED_LED,
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index fe3e67c..e2f280d 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -83,7 +83,7 @@ static struct platform_device rd88f5182_nor_flash = {
#define RD88F5182_GPIO_LED 0
-static struct gpio_led rd88f5182_gpio_led_pins[] = {
+static const struct gpio_led rd88f5182_gpio_led_pins[] = {
{
.name = "rd88f5182:cpu",
.default_trigger = "cpu0",
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index a77613b..a31f6848 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -169,7 +169,7 @@ static struct i2c_board_info __initdata qnap_ts409_i2c_rtc = {
* LEDs attached to GPIO
****************************************************************************/
-static struct gpio_led ts409_led_pins[] = {
+static const struct gpio_led ts409_led_pins[] = {
{
.name = "ts409:red:sata1",
.gpio = 4,
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index 9250bb2..5493d73 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -29,7 +29,7 @@
/*
* LEDs attached to GPIO
*/
-static struct gpio_led wrt350n_v2_led_pins[] = {
+static const struct gpio_led wrt350n_v2_led_pins[] = {
{
.name = "wrt350nv2:green:power",
.gpio = 0,
--
2.7.4
^ permalink raw reply related
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: Peng Fan @ 2017-12-27 2:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171227025055.GD11724@b29396-OptiPlex-7040>
> -----Original Message-----
> From: Dong Aisheng [mailto:dongas86 at gmail.com]
> Sent: Wednesday, December 27, 2017 10:51 AM
> To: A.s. Dong <aisheng.dong@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Peng Fan <peng.fan@nxp.com>;
> linux-kernel at vger.kernel.org; Russell King <linux@armlinux.org.uk>; Fabio
> Estevam <fabio.estevam@nxp.com>; Sascha Hauer <kernel@pengutronix.de>;
> van.freenix at gmail.com; linux-arm-kernel at lists.infradead.org
> Subject: Re: [PATCH V2] ARM: imx: suspend/resume: use
> outer_disable/resume
>
> On Wed, Dec 27, 2017 at 02:33:57AM +0000, A.s. Dong wrote:
> > > -----Original Message-----
> > > From: Shawn Guo [mailto:shawnguo at kernel.org]
> > > Sent: Wednesday, December 27, 2017 10:32 AM
> > > To: Peng Fan <peng.fan@nxp.com>
> > > Cc: A.s. Dong <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org;
> > > Russell King <linux@armlinux.org.uk>; Fabio Estevam
> > > <fabio.estevam@nxp.com>; Sascha Hauer <kernel@pengutronix.de>;
> > > van.freenix at gmail.com; linux-arm- kernel at lists.infradead.org
> > > Subject: Re: [PATCH V2] ARM: imx: suspend/resume: use
> > > outer_disable/resume
> > >
> > > On Wed, Dec 27, 2017 at 09:57:47AM +0800, Peng Fan wrote:
> > > > Use outer_disable/resume for suspend/resume.
> > > > With the two APIs used, code could be simplified and easy to
> > > > extend to introduce l2c_write_sec for i.MX platforms when moving
> > > > Linux Kernel runs in non-secure world.
> > > >
> > > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > > Cc: Russell King <linux@armlinux.org.uk>
> > > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> > >
> > > @Aisheng, can you please give it a test?
> > >
> >
> > Yes, of course.
> >
>
> Not sure but i can still meet booting crash on mx6sx sdb.
> Peng, you did not meet it, right?
>
> I tested with Shanw/for-next branch.
I use kernel master branch. I'll switch to shawn's for-next branch and give a test.
Thanks,
Peng.
>
> [ 4.840665] VFS: Mounted root (nfs filesystem) readonly on device 0:13.
> [ 4.853448] devtmpfs: mounted
> [ 4.858370] Freeing unused kernel memory: 1024K
> INIT: version 2.88 booting
> [ 6.835667] BUG: Bad rss-counter state mm:ecef66c0 idx:0 val:-1
> [ 6.841783] BUG: Bad rss-counter state mm:ecef66c0 idx:1 val:1
> Starting udev
> [ 7.792090] Unable to handle kernel NULL pointer dereference at virtual
> address 00000001
> [ 7.800500] pgd = ecbcc000
> [ 7.803884] [00000001] *pgd=ba0c1831
> [ 7.807541] Internal error: Oops: 17 [#1] SMP ARM
> [ 7.812268] Modules linked in:
> [ 7.815368] CPU: 0 PID: 175 Comm: S04udev Not tainted 4.15.0-rc1-00043-
> g7afb5ac-dirty #1891
> [ 7.823739] Hardware name: Freescale i.MX6 SoloX (Device Tree)
> [ 7.829595] task: ec79d940 task.stack: ec8bc000
> [ 7.834168] PC is at kmem_cache_alloc+0xf0/0x168
> [ 7.838808] LR is at 0x2e85d000
> [ 7.841971] pc : [<c0226ec0>] lr : [<2e85d000>] psr: 20000013
> [ 7.848257] sp : ec8bdef8 ip : ef7d9ee0 fp : ec8bdf2c
> [ 7.853502] r10: 00000b5e r9 : 00000001 r8 : a0000013
> [ 7.858748] r7 : 00000b5f r6 : c014a21c r5 : 014000c0 r4 : ec001d80
> [ 7.865295] r3 : 00000000 r2 : eca5b200 r1 : ec8bc000 r0 : c1009290
> [ 7.871848] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment
> none
> [ 7.879003] Control: 10c5387d Table: acbcc04a DAC: 00000051
> [ 7.884770] Process S04udev (pid: 175, stack limit = 0xec8bc210)
> [ 7.890798] Stack: (0xec8bdef8 to 0xec8be000)
> [ 7.895180] dee0: 00422030 00000000
> [ 7.903387] df00: 000000c3 00000004 ec79d940 ffffff9c 0178f780 c0108104
> ec8bc000 00000000
> [ 7.911592] df20: ec8bdf44 ec8bdf30 c014a21c c0226ddc 00000004 00000000
> ec8bdf94 ec8bdf48
> [ 7.919798] df40: c022bf2c c014a1fc 00422030 00000000 0000000d 00000004
> 000003e8 000003e8
> [ 7.928004] df60: 0000a990 00000000 5a41ff5b 00000004 00000000 0178f780
> 00000021 c0108104
> [ 7.936209] df80: ec8bc000 00000000 ec8bdfa4 ec8bdf98 c022c120 c022bf0c
> 00000000 ec8bdfa8
> [ 7.944414] dfa0: c0107f40 c022c110 00000004 00000000 0178f780 00000004
> be92eca8 00008000
> [ 7.952619] dfc0: 00000004 00000000 0178f780 00000021 00000000 00000000
> 00000024 be92edac
> [ 7.960826] dfe0: 000e51e4 be92eca4 b6eac97c b6eac87c 60000010 0178f780
> 00000000 00000000
> [ 7.969018] Backtrace:
> [ 7.971519] [<c0226dd0>] (kmem_cache_alloc) from [<c014a21c>]
> (prepare_creds+0x2c/0x120)
> [ 7.979642] r10:00000000 r9:ec8bc000 r8:c0108104 r7:0178f780 r6:ffffff9c
> r5:ec79d940
> [ 7.987492] r4:00000004
> [ 7.990060] [<c014a1f0>] (prepare_creds) from [<c022bf2c>]
> (SyS_faccessat+0x2c/0x204)
> [ 7.997911] r5:00000000 r4:00000004
> [ 8.001517] [<c022bf00>] (SyS_faccessat) from [<c022c120>]
> (SyS_access+0x1c/0x20)
> [ 8.009028] r10:00000000 r9:ec8bc000 r8:c0108104 r7:00000021 r6:0178f780
> r5:00000000
> [ 8.016875] r4:00000004
> [ 8.019448] [<c022c104>] (SyS_access) from [<c0107f40>]
> (ret_fast_syscall+0x0/0x28)
> [ 8.027135] Code: e121f008 e3590000 0a000002 e5943014 (e7993003)
> [ 8.033525] ---[ end trace 5829484d9a98b0fd ]---
> /etc/init.d/rc: line 45: 175 Se[ 8.042776] Unable to handle kernel NULL
> pointer dereference at virtual address 00000001
>
> Regards
> Dong Aisheng
>
> > Regards
> > Dong Aisheng
> >
> > > Shawn
^ permalink raw reply
* [PATCH] ARM: dts: imx7s: Avoid using label in unit address and reg
From: Shawn Guo @ 2017-12-27 2:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514318385-12135-1-git-send-email-festevam@gmail.com>
On Tue, Dec 26, 2017 at 05:59:45PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> As recommended by Rob Herring [1] labels should not be used in unit address
> and reg, so use its real value directly instead.
>
> [1] https://www.spinics.net/lists/devicetree/msg206567.html
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied, thanks.
^ permalink raw reply
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: Dong Aisheng @ 2017-12-27 2:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM3PR04MB3067ECFE7A7DAE48DFD124780070@AM3PR04MB306.eurprd04.prod.outlook.com>
On Wed, Dec 27, 2017 at 02:33:57AM +0000, A.s. Dong wrote:
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo at kernel.org]
> > Sent: Wednesday, December 27, 2017 10:32 AM
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: A.s. Dong <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org; Russell
> > King <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> > Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com; linux-arm-
> > kernel at lists.infradead.org
> > Subject: Re: [PATCH V2] ARM: imx: suspend/resume: use
> > outer_disable/resume
> >
> > On Wed, Dec 27, 2017 at 09:57:47AM +0800, Peng Fan wrote:
> > > Use outer_disable/resume for suspend/resume.
> > > With the two APIs used, code could be simplified and easy to extend to
> > > introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
> > > runs in non-secure world.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > Cc: Russell King <linux@armlinux.org.uk>
> > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > @Aisheng, can you please give it a test?
> >
>
> Yes, of course.
>
Not sure but i can still meet booting crash on mx6sx sdb.
Peng, you did not meet it, right?
I tested with Shanw/for-next branch.
[ 4.840665] VFS: Mounted root (nfs filesystem) readonly on device 0:13.
[ 4.853448] devtmpfs: mounted
[ 4.858370] Freeing unused kernel memory: 1024K
INIT: version 2.88 booting
[ 6.835667] BUG: Bad rss-counter state mm:ecef66c0 idx:0 val:-1
[ 6.841783] BUG: Bad rss-counter state mm:ecef66c0 idx:1 val:1
Starting udev
[ 7.792090] Unable to handle kernel NULL pointer dereference at virtual address 00000001
[ 7.800500] pgd = ecbcc000
[ 7.803884] [00000001] *pgd=ba0c1831
[ 7.807541] Internal error: Oops: 17 [#1] SMP ARM
[ 7.812268] Modules linked in:
[ 7.815368] CPU: 0 PID: 175 Comm: S04udev Not tainted 4.15.0-rc1-00043-g7afb5ac-dirty #1891
[ 7.823739] Hardware name: Freescale i.MX6 SoloX (Device Tree)
[ 7.829595] task: ec79d940 task.stack: ec8bc000
[ 7.834168] PC is at kmem_cache_alloc+0xf0/0x168
[ 7.838808] LR is at 0x2e85d000
[ 7.841971] pc : [<c0226ec0>] lr : [<2e85d000>] psr: 20000013
[ 7.848257] sp : ec8bdef8 ip : ef7d9ee0 fp : ec8bdf2c
[ 7.853502] r10: 00000b5e r9 : 00000001 r8 : a0000013
[ 7.858748] r7 : 00000b5f r6 : c014a21c r5 : 014000c0 r4 : ec001d80
[ 7.865295] r3 : 00000000 r2 : eca5b200 r1 : ec8bc000 r0 : c1009290
[ 7.871848] Flags: nzCv IRQs on FIQs on Mode SVC_32 ISA ARM Segment none
[ 7.879003] Control: 10c5387d Table: acbcc04a DAC: 00000051
[ 7.884770] Process S04udev (pid: 175, stack limit = 0xec8bc210)
[ 7.890798] Stack: (0xec8bdef8 to 0xec8be000)
[ 7.895180] dee0: 00422030 00000000
[ 7.903387] df00: 000000c3 00000004 ec79d940 ffffff9c 0178f780 c0108104 ec8bc000 00000000
[ 7.911592] df20: ec8bdf44 ec8bdf30 c014a21c c0226ddc 00000004 00000000 ec8bdf94 ec8bdf48
[ 7.919798] df40: c022bf2c c014a1fc 00422030 00000000 0000000d 00000004 000003e8 000003e8
[ 7.928004] df60: 0000a990 00000000 5a41ff5b 00000004 00000000 0178f780 00000021 c0108104
[ 7.936209] df80: ec8bc000 00000000 ec8bdfa4 ec8bdf98 c022c120 c022bf0c 00000000 ec8bdfa8
[ 7.944414] dfa0: c0107f40 c022c110 00000004 00000000 0178f780 00000004 be92eca8 00008000
[ 7.952619] dfc0: 00000004 00000000 0178f780 00000021 00000000 00000000 00000024 be92edac
[ 7.960826] dfe0: 000e51e4 be92eca4 b6eac97c b6eac87c 60000010 0178f780 00000000 00000000
[ 7.969018] Backtrace:
[ 7.971519] [<c0226dd0>] (kmem_cache_alloc) from [<c014a21c>] (prepare_creds+0x2c/0x120)
[ 7.979642] r10:00000000 r9:ec8bc000 r8:c0108104 r7:0178f780 r6:ffffff9c r5:ec79d940
[ 7.987492] r4:00000004
[ 7.990060] [<c014a1f0>] (prepare_creds) from [<c022bf2c>] (SyS_faccessat+0x2c/0x204)
[ 7.997911] r5:00000000 r4:00000004
[ 8.001517] [<c022bf00>] (SyS_faccessat) from [<c022c120>] (SyS_access+0x1c/0x20)
[ 8.009028] r10:00000000 r9:ec8bc000 r8:c0108104 r7:00000021 r6:0178f780 r5:00000000
[ 8.016875] r4:00000004
[ 8.019448] [<c022c104>] (SyS_access) from [<c0107f40>] (ret_fast_syscall+0x0/0x28)
[ 8.027135] Code: e121f008 e3590000 0a000002 e5943014 (e7993003)
[ 8.033525] ---[ end trace 5829484d9a98b0fd ]---
/etc/init.d/rc: line 45: 175 Se[ 8.042776] Unable to handle kernel NULL pointer dereference at virtual address 00000001
Regards
Dong Aisheng
> Regards
> Dong Aisheng
>
> > Shawn
^ permalink raw reply
* [PATCH] arm64: dts: ls1088a: add DT node of watchdog
From: Shawn Guo @ 2017-12-27 2:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171227020200.25542-1-ying.zhang@freescale.com>
On Wed, Dec 27, 2017 at 10:02:00AM +0800, ying.zhang at freescale.com wrote:
> From: Zhang Ying-22455 <ying.zhang22455@nxp.com>
>
> There are eight cores in ls1088a and each core has an watchdog,
> ls1088a can use sp805-wdt driver, so we just add DT node for it.
>
> Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 56 ++++++++++++++++++++++++
> 1 files changed, 56 insertions(+), 0 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> index f5f29a2..49366d1 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
> @@ -369,6 +369,62 @@
> status = "disabled";
> };
>
> + cluster1_core0_watchdog: wdt at c000000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc000000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
> + cluster1_core1_watchdog: wdt at c010000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc010000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
> + cluster1_core2_watchdog: wdt at c020000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc020000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
> + cluster1_core3_watchdog: wdt at c030000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc030000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
> + cluster2_core0_watchdog: wdt at c100000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc100000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
> + cluster2_core1_watchdog: wdt at c110000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc110000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
> + cluster2_core2_watchdog: wdt at c120000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc120000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
> + cluster2_core3_watchdog: wdt at c130000 {
> + compatible = "arm,sp805-wdt", "arm,primecell";
> + reg = <0x0 0xc130000 0x0 0x1000>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "apb_pclk", "wdog_clk";
> + };
> +
Please maintain the devices under simple-bus 'soc' node in order of
unit-address, when you add new device nodes. For example, wdt at c130000
shouldn't go before gpio at 2300000.
Shawn
> gpio0: gpio at 2300000 {
> compatible = "fsl,qoriq-gpio";
> reg = <0x0 0x2300000 0x0 0x10000>;
> --
> 1.7.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v2] arm64: dts: ls1088a: add DT node of watchdog
From: ying.zhang at freescale.com @ 2017-12-27 2:41 UTC (permalink / raw)
To: linux-arm-kernel
From: Zhang Ying-22455 <ying.zhang22455@nxp.com>
There are eight cores in ls1088a and each core has an watchdog,
ls1088a can use sp805-wdt driver, so we just add DT node for it.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 56 ++++++++++++++++++++++++
1 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index f5f29a2..fb1858a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -592,6 +592,62 @@
<0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ cluster1_core0_watchdog: wdt at c000000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc000000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core1_watchdog: wdt at c010000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core2_watchdog: wdt at c020000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc020000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core3_watchdog: wdt at c030000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc030000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core0_watchdog: wdt at c100000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc100000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core1_watchdog: wdt at c110000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc110000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core2_watchdog: wdt at c120000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc120000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core3_watchdog: wdt at c130000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc130000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
};
firmware {
--
1.7.1
^ permalink raw reply related
* [PATCH] ARM: dts: imx51-zii-rdu1: Add missing #phy-cells to usb-nop-xceiv
From: Shawn Guo @ 2017-12-27 2:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514311460-8840-1-git-send-email-festevam@gmail.com>
On Tue, Dec 26, 2017 at 04:04:20PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> Commit 915fbe59cbf2fe6 ("ARM: dts: imx: Add missing #phy-cells to
> usb-nop-xceiv") missed to update imx51-zii-rdu1.dts probably due to a
> merge timing issue, so add #phy-cells here too.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied, thanks.
^ permalink raw reply
* [PATCH] ARM: dts: imx6qdl-hummingboard2: Remove leading zero in unit address
From: Shawn Guo @ 2017-12-27 2:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514310958-3792-1-git-send-email-festevam@gmail.com>
On Tue, Dec 26, 2017 at 03:55:58PM -0200, Fabio Estevam wrote:
> From: Fabio Estevam <fabio.estevam@nxp.com>
>
> Remove the leading zero from unit address to fix the following build
> warning with W=1:
>
> arch/arm/boot/dts/imx6dl-hummingboard2.dtb: Warning (unit_address_format): Node /soc/aips-bus at 2100000/i2c at 21a0000/codec at 0a unit name should not have leading 0s
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Applied, thanks.
^ permalink raw reply
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: A.s. Dong @ 2017-12-27 2:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171227023207.GX23070@X250>
> -----Original Message-----
> From: Shawn Guo [mailto:shawnguo at kernel.org]
> Sent: Wednesday, December 27, 2017 10:32 AM
> To: Peng Fan <peng.fan@nxp.com>
> Cc: A.s. Dong <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org; Russell
> King <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH V2] ARM: imx: suspend/resume: use
> outer_disable/resume
>
> On Wed, Dec 27, 2017 at 09:57:47AM +0800, Peng Fan wrote:
> > Use outer_disable/resume for suspend/resume.
> > With the two APIs used, code could be simplified and easy to extend to
> > introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
> > runs in non-secure world.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Cc: Russell King <linux@armlinux.org.uk>
> > Cc: Dong Aisheng <aisheng.dong@nxp.com>
>
> @Aisheng, can you please give it a test?
>
Yes, of course.
Regards
Dong Aisheng
> Shawn
^ permalink raw reply
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: Shawn Guo @ 2017-12-27 2:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514339867-28946-1-git-send-email-peng.fan@nxp.com>
On Wed, Dec 27, 2017 at 09:57:47AM +0800, Peng Fan wrote:
> Use outer_disable/resume for suspend/resume.
> With the two APIs used, code could be simplified and easy to extend
> to introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
> runs in non-secure world.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Dong Aisheng <aisheng.dong@nxp.com>
@Aisheng, can you please give it a test?
Shawn
^ permalink raw reply
* [PATCH v3 2/6] ARM: dts: imx6: Add initial support for phyBOARD-Mira
From: Shawn Guo @ 2017-12-27 2:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513940353-6145-3-git-send-email-s.riedmueller@phytec.de>
On Fri, Dec 22, 2017 at 11:59:09AM +0100, Stefan Riedmueller wrote:
> This patch adds basic support for PHYTEC phyBOARD-Mira as carrier board
> for PHYTEC phyCORE-i.MX 6.
>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> Signed-off-by: Stefan Christ <s.christ@phytec.de>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
> arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi | 390 +++++++++++++++++++++++++++++
> 1 file changed, 390 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
> new file mode 100644
> index 0000000..45d8c0c
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi
> @@ -0,0 +1,390 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2017 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp <c.hemp@phytec.de>
> + */
> +
> +
> +/ {
> + aliases {
> + rtc0 = &i2c_rtc;
> + };
> +
> + backlight: backlight {
> + compatible = "pwm-backlight";
> + brightness-levels = <0 4 8 16 32 64 128 255>;
> + default-brightness-level = <7>;
> + power-supply = <®_backlight>;
> + pwms = <&pwm1 0 5000000>;
> + status = "okay";
> + };
> +
> + gpio_leds: leds {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpioleds>;
> + status = "disabled";
> +
Generally we do not have newlines in middle of property list.
> + compatible = "gpio-leds";
Please put 'compatible' at the beginning of property list and always
have 'status' be the end of list.
> +
> + red {
> + label = "phyboard-mira:red";
> + gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>;
> + };
> +
> + green {
> + label = "phyboard-mira:green";
> + gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>;
> + };
> +
> + blue {
> + label = "phyboard-mira:blue";
> + gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "mmc0";
> + };
> + };
> +
> + reg_backlight: regulator-backlight {
> + compatible = "regulator-fixed";
> + regulator-name = "backlight_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + reg_en_switch: regulator-en-switch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_en_switch>;
> + compatible = "regulator-fixed";
Move the 'compatible' forward.
> + regulator-name = "Enable Switch";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + enable-active-high;
> + gpio = <&gpio3 4 GPIO_ACTIVE_HIGH>;
> + regulator-always-on;
> + };
> +
> + reg_flexcan1: regulator-flexcan1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1_en>;
> + compatible = "regulator-fixed";
> + regulator-name = "flexcan1-reg";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&gpio2 20 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_panel: regulator-panel {
> + compatible = "regulator-fixed";
> + regulator-name = "panel-power-supply";
> + regulator-min-microvolt = <12000000>;
> + regulator-max-microvolt = <12000000>;
> + regulator-always-on;
> + };
> +
> + reg_pcie: regulator-pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie_reg>;
> + compatible = "regulator-fixed";
> + regulator-name = "mPCIe_1V5";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + gpio = <&gpio3 0 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usb_h1_vbus: usb-h1-vbus {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbh1_vbus>;
> + compatible = "regulator-fixed";
> + regulator-name = "usb_h1_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio2 18 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + reg_usbotg_vbus: usbotg-vbus {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg_vbus>;
> + compatible = "regulator-fixed";
> + regulator-name = "usb_otg_vbus";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> + };
> +
> + panel {
> + compatible = "auo,g104sn02";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_panel_en>;
> + power-supply = <®_panel>;
> + enable-gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
> +
Drop the newline.
Shawn
> + backlight = <&backlight>;
> +
> + port {
> + panel_in: endpoint {
> + remote-endpoint = <&lvds0_out>;
> + };
> + };
> + };
> +};
> +
> +&can1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_flexcan1>;
> + xceiver-supply = <®_flexcan1>;
> + status = "disabled";
> +};
> +
> +&hdmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_hdmicec>;
> + ddc-i2c-bus = <&i2c2>;
> + status = "disabled";
> +};
> +
> +&i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c1>;
> + clock-frequency = <400000>;
> + status = "disabled";
> +
> + stmpe: touchctrl at 44 {
> + compatible = "st,stmpe811";
> + reg = <0x44>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <12 IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_stmpe>;
> + status = "disabled";
> +
> + stmpe_touchscreen {
> + compatible = "st,stmpe-ts";
> + st,sample-time = <4>;
> + st,mod-12b = <1>;
> + st,ref-sel = <0>;
> + st,adc-freq = <1>;
> + st,ave-ctrl = <1>;
> + st,touch-det-delay = <2>;
> + st,settling = <2>;
> + st,fraction-z = <7>;
> + st,i-drive = <1>;
> + };
> + };
> +
> + i2c_rtc: rtc at 68 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_rtc_int>;
> + compatible = "microcrystal,rv4162";
> + reg = <0x68>;
> + interrupt-parent = <&gpio7>;
> + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +};
> +
> +&i2c2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c2>;
> + clock-frequency = <100000>;
> + status = "disabled";
> +};
> +
> +&ldb {
> + status = "okay";
> +
> + lvds-channel at 0 {
> + fsl,data-mapping = "spwg";
> + fsl,data-width = <24>;
> + status = "disabled";
> +
> + port at 4 {
> + reg = <4>;
> +
> + lvds0_out: endpoint {
> + remote-endpoint = <&panel_in>;
> + };
> + };
> + };
> +};
> +
> +&pcie {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pcie>;
> + reset-gpio = <&gpio2 25 GPIO_ACTIVE_LOW>;
> + vpcie-supply = <®_pcie>;
> + status = "disabled";
> +};
> +
> +&pwm1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pwm1>;
> + status = "okay";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart2>;
> + status = "okay";
> +};
> +
> +&uart3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_uart3>;
> + uart-has-rtscts;
> + status = "disabled";
> +};
> +
> +&usbh1 {
> + vbus-supply = <®_usb_h1_vbus>;
> + disable-over-current;
> + status = "disabled";
> +};
> +
> +&usbotg {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usbotg>;
> + vbus-supply = <®_usbotg_vbus>;
> + disable-over-current;
> + status = "disabled";
> +};
> +
> +&usdhc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc1>;
> + cd-gpios = <&gpio6 31 GPIO_ACTIVE_LOW>;
> + no-1-8-v;
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl_panel_en: panelen1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0xb0b1
> + >;
> + };
> +
> + pinctrl_en_switch: enswitchgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_DA4__GPIO3_IO04 0xb0b1
> + >;
> + };
> +
> + pinctrl_flexcan1: flexcan1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
> + MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
> + >;
> + };
> +
> + pinctrl_flexcan1_en: flexcan1engrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A18__GPIO2_IO20 0xb0b1
> + >;
> + };
> +
> + pinctrl_gpioleds: gpioledsgrp {
> + fsl,pins = <
> + MX6QDL_PAD_CSI0_DAT4__GPIO5_IO22 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT5__GPIO5_IO23 0x1b0b0
> + MX6QDL_PAD_CSI0_DAT6__GPIO5_IO24 0x1b0b0
> + >;
> + };
> +
> + pinctrl_hdmicec: hdmicecgrp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
> + >;
> + };
> +
> + pinctrl_i2c2: i2c2grp {
> + fsl,pins = <
> + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
> + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_i2c1: i2c1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
> + MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_pcie: pciegrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_OE__GPIO2_IO25 0xb0b1
> + >;
> + };
> +
> + pinctrl_pcie_reg: pciereggrp {
> + fsl,pins = <MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0xb0b1>;
> + };
> +
> + pinctrl_pwm1: pwm1grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
> + >;
> + };
> +
> + pinctrl_rtc_int: rtcintgrp {
> + fsl,pins = <
> + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0
> + >;
> + };
> +
> + pinctrl_stmpe: stmpegrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
> + >;
> + };
> +
> + pinctrl_uart2: uart2grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_uart3: uart3grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_EB3__UART3_CTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
> + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
> + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
> + >;
> + };
> +
> + pinctrl_usbh1_vbus: usbh1vbusgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0xb0b1
> + >;
> + };
> +
> + pinctrl_usbotg: usbotggrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
> + >;
> + };
> +
> + pinctrl_usbotg_vbus: usbotgvbusgrp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_A19__GPIO2_IO19 0xb0b1
> + >;
> + };
> +
> + pinctrl_usdhc1: usdhc1grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170f9
> + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100f9
> + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
> + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
> + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
> + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
> + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0xb0b1 /* CD */
> + >;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 1/1] power: reset: remove unused imx-snvs-poweroff driver
From: Fabio Estevam @ 2017-12-27 2:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513938539-20873-1-git-send-email-aisheng.dong@nxp.com>
On Fri, Dec 22, 2017 at 8:28 AM, Dong Aisheng <aisheng.dong@nxp.com> wrote:
> There's no user of it in kernel now and it basically functions the same
> as the generic syscon-poweroff.c to which we have already switched.
> So let's remove it.
>
> Cc: Robin Gong <yibin.gong@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Peng Fan @ 2017-12-27 2:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR04MB3221C1B5362775C72B34B01088060@DB6PR04MB3221.eurprd04.prod.outlook.com>
Hi Shawn,
> >
> > On Sun, Dec 10, 2017 at 08:07:18PM +0800, Peng Fan wrote:
> > > Use outer_disable/resume for suspend/resume.
> > > With the two APIs used, code could be simplified and easy to extend
> > > to introduce l2c_write_sec for i.MX platforms when moving Linux
> > > Kernel runs in non-secure world.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > Cc: Russell King <linux@armlinux.org.uk>
> > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Changed 'arm: ' prefix to 'ARM: ', and applied patch.
>
> I just tested it on 6sx-sdb, seems this patch breaks 6sx. Could you first drop this
> patch? I'll send out v2 fix the 6sx issue soon.
I just send out V2 patch to fix the 6sx issue. Sorry for the inconvenience about V1
that break 6sx. Please review.
Thanks,
Peng.
.
>
> Thanks,
> Peng.
>
> >
> > Shawn
^ permalink raw reply
* [PATCH v3 1/6] ARM: dts: imx6: Add initial support for phyCORE-i.MX 6 SOM
From: Shawn Guo @ 2017-12-27 2:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513940353-6145-2-git-send-email-s.riedmueller@phytec.de>
On Fri, Dec 22, 2017 at 11:59:08AM +0100, Stefan Riedmueller wrote:
> This patch adds basic support for PHYTEC phyCORE-i.MX 6 SOM with i.MX
> 6Quad/Dual or i.MX 6DualLight/Solo.
>
> Signed-off-by: Christian Hemp <c.hemp@phytec.de>
> Signed-off-by: Stefan Christ <s.christ@phytec.de>
> Signed-off-by: Christoph Fritz <chf.fritz@googlemail.com>
> Signed-off-by: Stefan Riedmueller <s.riedmueller@phytec.de>
> ---
> arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi | 282 ++++++++++++++++++++++
> 1 file changed, 282 insertions(+)
> create mode 100644 arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
>
> diff --git a/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
> new file mode 100644
> index 0000000..8501ac6
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6qdl-phytec-phycore-som.dtsi
> @@ -0,0 +1,282 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2017 PHYTEC Messtechnik GmbH
> + * Author: Christian Hemp <c.hemp@phytec.de>
> + */
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +/ {
> + model = "PHYTEC phyCORE-i.MX 6";
> + compatible = "phytec,imx6qdl-pcm058", "fsl,imx6qdl";
> +
> + aliases {
> + rtc1 = &da9062_rtc;
> + rtc2 = &snvs_rtc;
> + };
> +
> + /*
> + * Set the minimum memory size here and
> + * let the bootloader set the real size.
> + */
> + memory at 10000000 {
> + device_type = "memory";
> + reg = <0x10000000 0x8000000>;
> + };
> +
> + gpio_leds_som: somleds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpioleds_som>;
> +
> + som_green {
We generally use hyphen rather than underscore in node name. Also I
would suggest to have 'led' in the name to tell what the device is,
maybe 'led-green'?
> + label = "phycore:green";
> + gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>;
> + linux,default-trigger = "heartbeat";
> + };
> + };
> +};
> +
> +&ecspi1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_ecspi1>;
> + cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + flash: flash at 0 {
While it's all good to name the node in a general way, the label can be
specific, like:
m25p80: flash at 0 {
...
}
Even better, if the label is not really needed, just drop it.
> + compatible = "m25p80";
> + spi-max-frequency = <20000000>;
> + reg = <0>;
> + status = "disabled";
> + };
> +};
> +
> +&fec {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_enet>;
> + phy-handle = <ðphy>;
> + phy-mode = "rgmii";
> + phy-supply = <&vdd_eth_io>;
> + phy-reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
> + status = "disabled";
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethphy: ethernet-phy at 3 {
> + reg = <3>;
> + txc-skew-ps = <1680>;
> + rxc-skew-ps = <1860>;
> + };
> + };
> +};
> +
> +&gpmi {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_gpmi_nand>;
> + nand-on-flash-bbt;
> + status = "disabled";
> +};
> +
> +&i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_i2c3>;
> + clock-frequency = <400000>;
> + status = "okay";
> +
> + eeprom: eeprom at 50 {
Is the label used at all?
> + compatible = "atmel,24c32";
> + reg = <0x50>;
> + };
> +
> + pmic0: pmic at 58 {
Ditto
> + compatible = "dlg,da9062";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_pmic>;
> + reg = <0x58>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-controller;
> +
> + da9062_rtc: rtc {
> + compatible = "dlg,da9062-rtc";
> + };
> +
> + da9062_wdt: watchdog {
Ditto
> + compatible = "dlg,da9062-watchdog";
> + };
> +
> + da9062_reg: regulators {
Ditto
Shawn
> + vdd_arm: buck1 {
> + regulator-name = "vdd_arm";
> + regulator-min-microvolt = <730000>;
> + regulator-max-microvolt = <1380000>;
> + regulator-always-on;
> + };
> +
> + vdd_soc: buck2 {
> + regulator-name = "vdd_soc";
> + regulator-min-microvolt = <730000>;
> + regulator-max-microvolt = <1380000>;
> + regulator-always-on;
> + };
> +
> + vdd_ddr3_1p5: buck3 {
> + regulator-name = "vdd_ddr3";
> + regulator-min-microvolt = <1500000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> +
> + vdd_eth_1p2: buck4 {
> + regulator-name = "vdd_eth";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + vdd_snvs: ldo1 {
> + regulator-name = "vdd_snvs";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-always-on;
> + };
> +
> + vdd_high: ldo2 {
> + regulator-name = "vdd_high";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-always-on;
> + };
> +
> + vdd_eth_io: ldo3 {
> + regulator-name = "vdd_eth_io";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <2500000>;
> + };
> +
> + vdd_emmc_1p8: ldo4 {
> + regulator-name = "vdd_emmc";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> + };
> + };
> +};
> +
> +®_arm {
> + vin-supply = <&vdd_arm>;
> +};
> +
> +®_pu {
> + vin-supply = <&vdd_soc>;
> +};
> +
> +®_soc {
> + vin-supply = <&vdd_soc>;
> +};
> +
> +&snvs_poweroff {
> + status = "okay";
> +};
> +
> +&usdhc4 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usdhc4>;
> + bus-width = <8>;
> + non-removable;
> + vmmc-supply = <&vdd_emmc_1p8>;
> + status = "disabled";
> +};
> +
> +&iomuxc {
> + pinctrl_enet: enetgrp {
> + fsl,pins = <
> + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
> + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
> + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
> + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
> + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
> + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
> + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
> + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
> + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
> + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
> + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
> + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
> + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
> + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
> + MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
> + MX6QDL_PAD_SD2_DAT1__GPIO1_IO14 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpioleds_som: gpioledssomgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x1b0b0
> + >;
> + };
> +
> + pinctrl_gpmi_nand: gpminandgrp {
> + fsl,pins = <
> + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
> + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
> + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
> + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
> + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
> + MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
> + MX6QDL_PAD_NANDF_CS2__NAND_CE2_B 0xb0b1
> + MX6QDL_PAD_NANDF_CS3__NAND_CE3_B 0xb0b1
> + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
> + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
> + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
> + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
> + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
> + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
> + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
> + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
> + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
> + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
> + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
> + >;
> + };
> +
> + pinctrl_i2c3: i2c3grp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
> + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
> + >;
> + };
> +
> + pinctrl_ecspi1: ecspi1grp {
> + fsl,pins = <
> + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
> + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
> + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
> + MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x1b0b0
> + >;
> + };
> +
> + pinctrl_pmic: pmicgrp {
> + fsl,pins = <
> + MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
> + >;
> + };
> +
> + pinctrl_usdhc4: usdhc4grp {
> + fsl,pins = <
> + MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
> + MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
> + MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
> + MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
> + MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
> + MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
> + MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
> + MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
> + MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
> + MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
> + >;
> + };
> +};
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Shawn Guo @ 2017-12-27 2:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226103629.GC11724@b29396-OptiPlex-7040>
On Tue, Dec 26, 2017 at 06:36:29PM +0800, Dong Aisheng wrote:
> > > > diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-
> > > > imx/cpuidle-imx6sx.c
> > > > index c5a5c3a..edce5bd 100644
> > > > --- a/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > > +++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
> > > > @@ -26,7 +26,7 @@ static int imx6sx_idle_finish(unsigned long val)
> > > > * to adding conditional code for L2 cache type,
> > > > * just call flush_cache_all() is fine.
> > > > */
> > > > - flush_cache_all();
> > > > +// flush_cache_all();
> > >
> > > I think flush_cache_all is still needed, to flush L1 data, right?
> > >
> >
> > I thought it will be done in generic cpu_suspend.
> > See: __cpu_suspend_save()
> >
> > So we still need it?
> >
>
> Shawn,
>
> Do you have comments about it?
It seems that there are comments about this flush_cache_all() call right
above it. To be safe, I would suggest to keep it as it is.
Shawn
^ permalink raw reply
* [PATCH] arm64: dts: ls1088a: add DT node of watchdog
From: ying.zhang at freescale.com @ 2017-12-27 2:02 UTC (permalink / raw)
To: linux-arm-kernel
From: Zhang Ying-22455 <ying.zhang22455@nxp.com>
There are eight cores in ls1088a and each core has an watchdog,
ls1088a can use sp805-wdt driver, so we just add DT node for it.
Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 56 ++++++++++++++++++++++++
1 files changed, 56 insertions(+), 0 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index f5f29a2..49366d1 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -369,6 +369,62 @@
status = "disabled";
};
+ cluster1_core0_watchdog: wdt at c000000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc000000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core1_watchdog: wdt at c010000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc010000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core2_watchdog: wdt at c020000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc020000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster1_core3_watchdog: wdt at c030000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc030000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core0_watchdog: wdt at c100000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc100000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core1_watchdog: wdt at c110000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc110000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core2_watchdog: wdt at c120000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc120000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
+ cluster2_core3_watchdog: wdt at c130000 {
+ compatible = "arm,sp805-wdt", "arm,primecell";
+ reg = <0x0 0xc130000 0x0 0x1000>;
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "apb_pclk", "wdog_clk";
+ };
+
gpio0: gpio at 2300000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2300000 0x0 0x10000>;
--
1.7.1
^ permalink raw reply related
* [PATCH 0/3] [v11] pinctrl: qcom: add support for sparse GPIOs
From: Stephen Boyd @ 2017-12-27 2:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYtMbACG0D2zjgw-kN_3pb_VDGH_3DDhyMQD92eE5P0Gw@mail.gmail.com>
On 12/21, Linus Walleij wrote:
> Hi Timur,
>
> thank you for your perseverance. I am sorry that I am sometimes not
> fast to respond :(
>
> On Wed, Dec 20, 2017 at 8:10 PM, Timur Tabi <timur@codeaurora.org> wrote:
>
> > Patch 1 reverts an old patch that triggers a get_direction of every
> > pin upon init, without attempting to request the pins first. The
> > direction is already being queried when the pin is requested.
> >
> > Patch 2 adds support to pinctrl-msm for "unavailable" GPIOs.
>
> I have applied both of these to the pinctrl "devel" branch so we
> can see if all is fine.
>
> They have Stephen's ACK so I am happy with them, I am just
> still slightly worried about possible regressions because of
> patch 1.
>
> > Patch 3 extends that support to pinctrl-qdf2xxx. A recent ACPI change
> > on QDF2400 platforms blocks access to most pins, so the driver can only
> > register a subset.
>
> I see this one is still under discussion.
>
> If nothing drastic happens with patch 1/2 in linux-next
> it should be fine if you just resend this single patch in subsequent
> submissions.
>
If we go with my suggestion, patch 2 is not necessary and should
be dropped. The different approaches come down to expressing
which pins are available through the gpio valid mask, or through
the npins field of the msm pinctrl driver. Also, my approach
covers more than just GPIOs, it covers irqs and adjusts the
pinctrl pin request function so that pinctrl can't request
unavailable pins.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] ARM: make ARCH_S3C24XX select USE_OF and clean-up boot/dts/Makefile
From: Masahiro Yamada @ 2017-12-27 2:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJKOXPfd+R0z-RcNLWn=rS6U0uBhDsZS8d-f-b4+jUeQBruc5Q@mail.gmail.com>
2017-12-26 2:39 GMT+09:00 Krzysztof Kozlowski <krzk@kernel.org>:
> On Sun, Dec 24, 2017 at 6:19 PM, Masahiro Yamada
> <yamada.masahiro@socionext.com> wrote:
>> 2017-12-22 21:41 GMT+09:00 Krzysztof Kozlowski <krzk@kernel.org>:
>>> On Mon, Nov 27, 2017 at 3:19 AM, Masahiro Yamada
>>> <yamada.masahiro@socionext.com> wrote:
>>>> ARCH_S3C24XX is a very exceptional platform that some DT files in
>>>> arch/arm/boot/dts/, but does not select USE_OF.
>>>
>>> Not entirely. The platform does select USE_OF - when MACH_S3C2416_DT
>>> is chosen. For other boards USE_OF is not necessary because they do
>>> not use DT. Why you need to select it for entire arch?
>>>
>>> Best regards,
>>> Krzysztof
>>>
>>
>>
>> The reason is simple - to avoid compile error.
>>
>>
>> If I simply drop ifeq ($(CONFIG_OF),y)
>> but do not select ARCH_S3C24XX,
>> s3c2410_defconfig failed to build.
>>
>>
>> $ make -s ARCH=arm mrproper
>> $ make -s ARCH=arm s3c2410_defconfig
>> $ make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- dtbs
>> ...
>>
>> DTC arch/arm/boot/dts/s3c2416-smdk2416.dtb
>> /bin/sh: 1: ./scripts/dtc/dtc: not found
>> scripts/Makefile.lib:310: recipe for target
>> 'arch/arm/boot/dts/s3c2416-smdk2416.dtb' failed
>> make[1]: *** [arch/arm/boot/dts/s3c2416-smdk2416.dtb] Error 127
>> arch/arm/Makefile:349: recipe for target 'dtbs' failed
>> make: *** [dtbs] Error 2
>>
>>
>> Another solution would be to enable dtb by CONFIG_MACH_S3C2416_DT.
>>
>>
>> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
>> index d0381e9..950b5dd 100644
>> --- a/arch/arm/boot/dts/Makefile
>> +++ b/arch/arm/boot/dts/Makefile
>> @@ -800,7 +798,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
>> rk3288-veyron-pinky.dtb \
>> rk3288-veyron-speedy.dtb \
>> rk3288-vyasa.dtb
>> -dtb-$(CONFIG_ARCH_S3C24XX) += \
>> +dtb-$(CONFIG_MACH_S3C2416_DT) += \
>> s3c2416-smdk2416.dtb
>> dtb-$(CONFIG_ARCH_S3C64XX) += \
>> s3c6410-mini6410.dtb \
>>
>>
>>
>> If you migrate S3C24XX platform to DT,
>> per-board CONFIG option will go away.
>>
>> So, I think dtb-$(CONFIG_ARCH_S3C24XX) is OK.
>
> I think this second solution - using CONFIG_MACH_S3C2416_DT - makes
> more sense because:
> 1, S3C24xx will not be converted to DT. This is a legacy platform.
> 2. DT version supports only part of boards and peripherals so most of
> existing platforms will use non-DT boardfiles. Enabling OF on all of
> them is not useful for them.
I do not care this much.
I leave this up to you (and ARM-SOC maintainers).
> 3. The same error and solution probably applies to MACH_S3C64XX.
Maybe no.
Looking at arch/arm/mach-s3c64xx/Kconfig,
ARCH_S3C64XX depends on ARCH_MULTI_V6.
Multiplatform selects USE_OF.
>
> Best regards,
> Krzysztof
> --
> To unsubscribe from this list: send the line "unsubscribe devicetree" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [PATCH V2] ARM: imx: suspend/resume: use outer_disable/resume
From: Peng Fan @ 2017-12-27 1:57 UTC (permalink / raw)
To: linux-arm-kernel
Use outer_disable/resume for suspend/resume.
With the two APIs used, code could be simplified and easy to extend
to introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
runs in non-secure world.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
---
V2:
Fix 6SX booting. The V1 patch does not take 6SX low power idle into
consideration.
Tested on 6Q-SDB and 6SX-SDB.
arch/arm/mach-imx/cpuidle-imx6sx.c | 2 ++
arch/arm/mach-imx/pm-imx6.c | 2 ++
arch/arm/mach-imx/suspend-imx6.S | 24 ------------------------
3 files changed, 4 insertions(+), 24 deletions(-)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c b/arch/arm/mach-imx/cpuidle-imx6sx.c
index c5a5c3a70ab1..b35841d133dc 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -49,7 +49,9 @@ static int imx6sx_enter_wait(struct cpuidle_device *dev,
cpu_pm_enter();
cpu_cluster_pm_enter();
+ outer_disable();
cpu_suspend(0, imx6sx_idle_finish);
+ outer_resume();
cpu_cluster_pm_exit();
cpu_pm_exit();
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index ecdf071653d4..153a0afc7645 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -392,8 +392,10 @@ static int imx6q_pm_enter(suspend_state_t state)
imx6_enable_rbc(true);
imx_gpc_pre_suspend(true);
imx_anatop_pre_suspend();
+ outer_disable();
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
+ outer_resume();
if (cpu_is_imx6q() || cpu_is_imx6dl())
imx_smp_prepare();
imx_anatop_post_resume();
diff --git a/arch/arm/mach-imx/suspend-imx6.S b/arch/arm/mach-imx/suspend-imx6.S
index 76ee2ceec8d5..324f6b165e82 100644
--- a/arch/arm/mach-imx/suspend-imx6.S
+++ b/arch/arm/mach-imx/suspend-imx6.S
@@ -74,24 +74,6 @@
.align 3
- .macro sync_l2_cache
-
- /* sync L2 cache to drain L2's buffers to DRAM. */
-#ifdef CONFIG_CACHE_L2X0
- ldr r11, [r0, #PM_INFO_MX6Q_L2_V_OFFSET]
- teq r11, #0
- beq 6f
- mov r6, #0x0
- str r6, [r11, #L2X0_CACHE_SYNC]
-1:
- ldr r6, [r11, #L2X0_CACHE_SYNC]
- ands r6, r6, #0x1
- bne 1b
-6:
-#endif
-
- .endm
-
.macro resume_mmdc
/* restore MMDC IO */
@@ -185,9 +167,6 @@ ENTRY(imx6_suspend)
str r9, [r11, #MX6Q_SRC_GPR1]
str r1, [r11, #MX6Q_SRC_GPR2]
- /* need to sync L2 cache before DSM. */
- sync_l2_cache
-
ldr r11, [r0, #PM_INFO_MX6Q_MMDC_V_OFFSET]
/*
* put DDR explicitly into self-refresh and
@@ -342,8 +321,5 @@ ENDPROC(imx6_suspend)
ENTRY(v7_cpu_resume)
bl v7_invalidate_l1
-#ifdef CONFIG_CACHE_L2X0
- bl l2c310_early_resume
-#endif
b cpu_resume
ENDPROC(v7_cpu_resume)
--
2.14.1
^ permalink raw reply related
* [PATCH net-next v8 1/2] dt-bindings: net: add DT bindings for Socionext UniPhier AVE
From: Masahiro Yamada @ 2017-12-27 1:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514164238-28901-2-git-send-email-hayashi.kunihiko@socionext.com>
2017-12-25 10:10 GMT+09:00 Kunihiko Hayashi <hayashi.kunihiko@socionext.com>:
> DT bindings for the AVE ethernet controller found on Socionext's
> UniPhier platforms.
>
> Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
> Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/net/socionext,uniphier-ave4.txt | 47 ++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
>
> diff --git a/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
> new file mode 100644
> index 0000000..8b03668
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/socionext,uniphier-ave4.txt
> @@ -0,0 +1,47 @@
> +* Socionext AVE ethernet controller
> +
> +This describes the devicetree bindings for AVE ethernet controller
> +implemented on Socionext UniPhier SoCs.
> +
> +Required properties:
> + - compatible: Should be
> + - "socionext,uniphier-pro4-ave4" : for Pro4 SoC
> + - "socionext,uniphier-pxs2-ave4" : for PXs2 SoC
> + - "socionext,uniphier-ld11-ave4" : for LD11 SoC
> + - "socionext,uniphier-ld20-ave4" : for LD20 SoC
> + - reg: Address where registers are mapped and size of region.
> + - interrupts: Should contain the MAC interrupt.
> + - phy-mode: See ethernet.txt in the same directory. Allow to choose
> + "rgmii", "rmii", or "mii" according to the PHY.
> + - phy-handle: Should point to the external phy device.
> + See ethernet.txt file in the same directory.
> + - clocks: A phandle to the clock for the MAC.
> +
> +Optional properties:
> + - resets: A phandle to the reset control for the MAC.
> + - local-mac-address: See ethernet.txt in the same directory.
> +
> +Required subnode:
> + - mdio: A container for child nodes representing phy nodes.
> + See phy.txt in the same directory.
> +
> +Example:
> +
> + ether: ethernet at 65000000 {
> + compatible = "socionext,uniphier-ld20-ave4";
> + reg = <0x65000000 0x8500>;
> + interrupts = <0 66 4>;
> + phy-mode = "rgmii";
> + phy-handle = <ðphy>;
> + clocks = <&sys_clk 6>;
> + resets = <&sys_rst 6>;
> + local-mac-address = [00 00 00 00 00 00];
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + ethphy: ethphy at 1 {
> + reg = <1>;
> + };
> + };
Andrew Lunn suggested to put a blank line before the "mdio" subnode in v7:
https://patchwork.kernel.org/patch/10127461/
Does it apply to the "ethphy" subnode, too?
Looks like you have a chance for v9. Please consider it.
--
Best Regards
Masahiro Yamada
^ permalink raw reply
* [RFC PATCH V1 1/2] clk: use atomic runtime pm api in clk_core_is_enabled
From: Stephen Boyd @ 2017-12-27 1:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513935965-12909-1-git-send-email-aisheng.dong@nxp.com>
On 12/22, Dong Aisheng wrote:
> Current clk_pm_runtime_put is using pm_runtime_put_sync which
> is not safe to be called in clk_core_is_enabled as it should
> be able to run in atomic context.
>
> Thus use pm_runtime_put instead which is atomic safe.
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Ulf Hansson <ulf.hansson@linaro.org>
> Cc: Marek Szyprowski <m.szyprowski@samsung.com>
> Fixes: 9a34b45397e5 ("clk: Add support for runtime PM")
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
Applied to clk-fixes
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] arm: imx: suspend/resume: use outer_disable/resume
From: Shawn Guo @ 2017-12-27 1:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <DB6PR04MB3221C1B5362775C72B34B01088060@DB6PR04MB3221.eurprd04.prod.outlook.com>
On Tue, Dec 26, 2017 at 09:49:01AM +0000, Peng Fan wrote:
> Hi Shawn
>
> > -----Original Message-----
> > From: Shawn Guo [mailto:shawnguo at kernel.org]
> > Sent: Tuesday, December 26, 2017 5:13 PM
> > To: Peng Fan <peng.fan@nxp.com>
> > Cc: A.s. Dong <aisheng.dong@nxp.com>; linux-kernel at vger.kernel.org; Russell
> > King <linux@armlinux.org.uk>; Fabio Estevam <fabio.estevam@nxp.com>;
> > Sascha Hauer <kernel@pengutronix.de>; van.freenix at gmail.com; linux-arm-
> > kernel at lists.infradead.org
> > Subject: Re: [PATCH] arm: imx: suspend/resume: use outer_disable/resume
> >
> > On Sun, Dec 10, 2017 at 08:07:18PM +0800, Peng Fan wrote:
> > > Use outer_disable/resume for suspend/resume.
> > > With the two APIs used, code could be simplified and easy to extend to
> > > introduce l2c_write_sec for i.MX platforms when moving Linux Kernel
> > > runs in non-secure world.
> > >
> > > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>
> > > Cc: Sascha Hauer <kernel@pengutronix.de>
> > > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > > Cc: Russell King <linux@armlinux.org.uk>
> > > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> >
> > Changed 'arm: ' prefix to 'ARM: ', and applied patch.
>
> I just tested it on 6sx-sdb, seems this patch breaks 6sx. Could you first drop this
> patch? I'll send out v2 fix the 6sx issue soon.
Patch dropped.
^ permalink raw reply
* [PATCH v6 4/5] clk: aspeed: Register gated clocks
From: Stephen Boyd @ 2017-12-27 1:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513910633.2743.79.camel@kernel.crashing.org>
On 12/22, Benjamin Herrenschmidt wrote:
> On Fri, 2017-12-22 at 13:36 +1100, Benjamin Herrenschmidt wrote:
> >
> > > No you can't sleep here. It needs to delay because this is inside
> > > spinlock_irqsave.
> >
> > Additionally you really don't want to delay for 10ms with interrupts
> > off :-(
> >
> > Sadly, it looks like the clk framework already calls you with spinlock
> > irqsafe, which is a rather major suckage.
> >
> > Stephen, why is that so ? That pretty much makes it impossible to
> > do sleeping things, which prevents things like i2c based clock
> > controllers etc...
>
> I noticed we do have a few i2c based clock drivers... how are they ever
> supposed to work ? i2c bus controllers are allowed to sleep and the i2c
> core takes mutexes...
We have clk_prepare()/clk_unprepare() for sleeping suckage. You
can use that, and i2c based clk drivers do that today.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [RFC PATCH V1 2/2] clk: add lock for clk_core_is_enabled
From: Stephen Boyd @ 2017-12-27 1:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513935965-12909-2-git-send-email-aisheng.dong@nxp.com>
On 12/22, Dong Aisheng wrote:
> According to design doc, .is_enabled should be protected by enable lock.
> Then users don't have to protect it against enable/disable operation
> in clock drivers.
>
> See: Documentation/clk.txt
> "The enable lock is a spinlock and is held across calls to the .enable,
> .disable and .is_enabled operations."
>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com>
> ---
> drivers/clk/clk.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index e24968f..d6e2d5c 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -198,14 +198,19 @@ static bool clk_core_is_prepared(struct clk_core *core)
>
> static bool clk_core_is_enabled(struct clk_core *core)
> {
> + unsigned long flags;
> bool ret = false;
>
> + flags = clk_enable_lock();
> +
> /*
> * .is_enabled is only mandatory for clocks that gate
> * fall back to software usage counter if .is_enabled is missing
> */
> - if (!core->ops->is_enabled)
> + if (!core->ops->is_enabled) {
> + clk_enable_unlock(flags);
> return core->enable_count;
> + }
>
> /*
> * Check if clock controller's device is runtime active before
> @@ -230,6 +235,8 @@ static bool clk_core_is_enabled(struct clk_core *core)
> if (core->dev)
> pm_runtime_put(core->dev);
>
> + clk_enable_unlock(flags);
> +
> return ret;
> }
It doesn't really make any sense to hold the enable lock inside
the clk_core_is_enabled() function, unless you want to do
something else with the information of the enable state with that
lock held. Otherwise, seeing if a clk is enabled is a one-shot
read of the enabled state, which could just as easily change
after the function returns because the lock is released.
We should update the documentation.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
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