* [PATCH v2 1/2] Input: edt-ft5x06 - Add support for regulator
From: kbuild test robot @ 2017-12-30 3:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171228163336.28131-2-mylene.josserand@free-electrons.com>
Hi Myl?ne,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on robh/for-next]
[also build test WARNING on v4.15-rc5 next-20171222]
[cannot apply to input/next]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Myl-ne-Josserand/sun8i-a83t-Add-touchscreen-support-on-TBS-A711/20171230-091331
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
coccinelle warnings: (new ones prefixed by >>)
>> drivers/input/touchscreen/edt-ft5x06.c:1004:2-3: Unneeded semicolon
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [PATCH] Input: fix semicolon.cocci warnings
From: kbuild test robot @ 2017-12-30 3:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171228163336.28131-2-mylene.josserand@free-electrons.com>
From: Fengguang Wu <fengguang.wu@intel.com>
drivers/input/touchscreen/edt-ft5x06.c:1004:2-3: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
Fixes: 5969d946e8aa ("Input: edt-ft5x06 - Add support for regulator")
CC: Myl?ne Josserand <mylene.josserand@free-electrons.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
edt-ft5x06.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1001,7 +1001,7 @@ static int edt_ft5x06_ts_probe(struct i2
dev_err(&client->dev, "failed to request regulator: %d\n",
error);
return error;
- };
+ }
if (tsdata->vcc) {
error = regulator_enable(tsdata->vcc);
^ permalink raw reply
* [arm:sa1100 56/106] drivers/pcmcia/max1600.c:122:16: error: expected declaration specifiers or '...' before string constant
From: kbuild test robot @ 2017-12-30 4:36 UTC (permalink / raw)
To: linux-arm-kernel
tree: git://git.armlinux.org.uk/~rmk/linux-arm.git sa1100
head: 22477d17bcf5f08b49d983300fee15c873e4977e
commit: c7aab28ac27ad6cd70dd78dba8c53c419ed72172 [56/106] ARM: pxa/mainstone: convert PCMCIA to use MAX1600 driver and gpiod APIs
config: arm-pxa_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout c7aab28ac27ad6cd70dd78dba8c53c419ed72172
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
>> drivers/pcmcia/max1600.c:122:16: error: expected declaration specifiers or '...' before string constant
MODULE_LICENSE("GPL v2");
^~~~~~~~
vim +122 drivers/pcmcia/max1600.c
e35d50f0 Russell King 2016-08-31 121
e35d50f0 Russell King 2016-08-31 @122 MODULE_LICENSE("GPL v2");
:::::: The code at line 122 was first introduced by commit
:::::: e35d50f09779d13ee4508924c802f847f6907710 pcmcia: add MAX1600 driver
:::::: TO: Russell King <rmk+kernel@armlinux.org.uk>
:::::: CC: Russell King <rmk+kernel@armlinux.org.uk>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH 11/20] nvmem: meson-efuse: Convert to use devm_nvmem_register()
From: kbuild test robot @ 2017-12-30 6:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171227225956.14442-12-andrew.smirnov@gmail.com>
Hi Andrey,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[also build test ERROR on v4.15-rc5]
[cannot apply to next-20171222]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Andrey-Smirnov/Verbatim-device-names-and-devm_nvmem_-un-register/20171230-114930
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
>> drivers/nvmem/meson-efuse.c:72:12: error: 'meson_efuse_remove' undeclared here (not in a function); did you mean 'meson_efuse_probe'?
.remove = meson_efuse_remove,
^~~~~~~~~~~~~~~~~~
meson_efuse_probe
vim +72 drivers/nvmem/meson-efuse.c
ad855eae Carlo Caione 2016-08-27 69
ad855eae Carlo Caione 2016-08-27 70 static struct platform_driver meson_efuse_driver = {
ad855eae Carlo Caione 2016-08-27 71 .probe = meson_efuse_probe,
ad855eae Carlo Caione 2016-08-27 @72 .remove = meson_efuse_remove,
ad855eae Carlo Caione 2016-08-27 73 .driver = {
ad855eae Carlo Caione 2016-08-27 74 .name = "meson-efuse",
ad855eae Carlo Caione 2016-08-27 75 .of_match_table = meson_efuse_match,
ad855eae Carlo Caione 2016-08-27 76 },
ad855eae Carlo Caione 2016-08-27 77 };
ad855eae Carlo Caione 2016-08-27 78
:::::: The code at line 72 was first introduced by commit
:::::: ad855eae6caf0d1dd17bce5bcd8e07759adc9903 nvmem: amlogic: Add Amlogic Meson EFUSE driver
:::::: TO: Carlo Caione <carlo@endlessm.com>
:::::: CC: Kevin Hilman <khilman@baylibre.com>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
-------------- next part --------------
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^ permalink raw reply
* [PATCH] ARM: imx: introduce imx_l2c310_write_sec
From: Peng Fan @ 2017-12-30 7:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <201712291710.oGgg0Sre%fengguang.wu@intel.com>
On Fri, Dec 29, 2017 at 05:32:18PM +0800, kbuild test robot wrote:
>Hi Peng,
>
>Thank you for the patch! Yet something to improve:
>
>[auto build test ERROR on shawnguo/for-next]
>[also build test ERROR on v4.15-rc5 next-20171222]
>[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
>
>url: https://github.com/0day-ci/linux/commits/Peng-Fan/ARM-imx-introduce-imx_l2c310_write_sec/20171229-150558
>base: https://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git for-next
>config: arm-arm5 (attached as .config)
>compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
>reproduce:
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # save the attached .config to linux build tree
> make.cross ARCH=arm
>
>All errors (new ones prefixed by >>):
>
> arch/arm/mach-imx/system.o: In function `imx_l2c310_write_sec':
>>> system.c:(.text+0x44): undefined reference to `__arm_smccc_smc'
Thanks for the report. I should do compile test for ARMV4/5.
Thanks,
Peng.
>
>---
>0-DAY kernel test infrastructure Open Source Technology Center
>https://lists.01.org/pipermail/kbuild-all Intel Corporation
--
^ permalink raw reply
* consolidate direct dma mapping and swiotlb support
From: Christoph Hellwig @ 2017-12-30 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <23fee3bb-61ce-1735-b264-3acc0109c858@arm.com>
On Fri, Dec 29, 2017 at 10:52:14AM +0000, Vladimir Murzin wrote:
> Is it available in your dma-mapping.git or somewhere else?
git://git.infradead.org/users/hch/misc.git dma-direct
Gitweb:
http://git.infradead.org/users/hch/misc.git/shortlog/refs/heads/dma-direct
^ permalink raw reply
* [PATCH v4 0/6] Allwinner H3/H5/A64(DE2) SimpleFB support (Part 2)
From: Icenowy Zheng @ 2017-12-30 11:30 UTC (permalink / raw)
To: linux-arm-kernel
This patchset is the remaining part of Allwinner DE2 SimpleFB support in
Linux. Some H3/5-related patches are already applied into the sunxi
tree.
PATCH 1 adds the final SimpleFB nodes to the H3/H5 device tree. With it
applied the SimpleFB will be usable on H3/H5.
PATCH 2/3 are for the SRAM requirment of the A64 SoC; PATCH 2 is the
device tree binding of it and PATCH 3 is the implementation in DE2 CCU
of it.
PATCH 4/5 are A64 DTSI file parts; PATCH 4 adds DE2 CCU device node and
PATCH 5 adds SimpleFB device node.
PATCH 6 are A64 per-board DTS file changes, which keeps the regulator
for HVCC pin (a power supply pin on A64 SoC that is used by the HDMI
controller) on these boards.
Icenowy Zheng (6):
ARM: sunxi: h3/h5: add simplefb nodes
dt-bindings: add binding for A64 DE2 CCU SRAM
clk: sunxi-ng: add support for Allwinner A64 DE2 CCU
arm64: allwinner: a64: add DE2 CCU for A64 SoC
arm64: allwinner: a64: add simplefb for A64 SoC
arm64: allwinner: a64: add HDMI regulator to all DTs' simplefb_hdmi
.../devicetree/bindings/clock/sun8i-de2.txt | 5 +
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 24 +++++
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 4 +
.../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4 +
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 4 +
.../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 +
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4 +
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 4 +
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 60 +++++++++++
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 117 ++++++++++++++-------
10 files changed, 190 insertions(+), 40 deletions(-)
--
2.14.2
^ permalink raw reply
* [PATCH v4 1/6] ARM: sunxi: h3/h5: add simplefb nodes
From: Icenowy Zheng @ 2017-12-30 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230113043.30237-1-icenowy@aosc.io>
The H3/H5 SoCs have a HDMI output and a TV Composite output.
Add simplefb nodes for these outputs.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v4:
- Dropped extra clocks (bus clocks and HDMI DDC clocks), only keep the
clocks that are needed to display framebuffer to the monitor.
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
index fcb909658cf0..7a83b15225c7 100644
--- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi
+++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi
@@ -53,6 +53,30 @@
#address-cells = <1>;
#size-cells = <1>;
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ framebuffer-hdmi {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "mixer0-lcd0-hdmi";
+ clocks = <&display_clocks CLK_MIXER0>,
+ <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
+ status = "disabled";
+ };
+
+ framebuffer-tve {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "mixer1-lcd1-tve";
+ clocks = <&display_clocks CLK_MIXER1>,
+ <&ccu CLK_TVE>;
+ status = "disabled";
+ };
+ };
+
clocks {
#address-cells = <1>;
#size-cells = <1>;
--
2.14.2
^ permalink raw reply related
* [PATCH v4 2/6] dt-bindings: add binding for A64 DE2 CCU SRAM
From: Icenowy Zheng @ 2017-12-30 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230113043.30237-1-icenowy@aosc.io>
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed,
otherwise the whole DE2 memory zone cannot be accessed (kept to all 0).
Add binding for this, in order to make the DE2 CCU able to claim the
SRAM and enable access to the DE2 clock and reset registers.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v4:
- Added Rob's ACK.
Changes in v2:
- Adds description of the situation when the SRAM is not claimed.
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index f2fa87c4765c..a7d558a2b9b2 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -6,6 +6,7 @@ Required properties :
- "allwinner,sun8i-a83t-de2-clk"
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
+ - "allwinner,sun50i-a64-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
- reg: Must contain the registers base address and length
@@ -18,6 +19,10 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
+Additional required properties for "allwinner,sun50i-a64-de2-clk" :
+- allwinner,sram: See Documentation/devicetree/bindings/sram/sunxi-sram.txt,
+ should be the SRAM C section on A64 SoC.
+
Example:
de2_clocks: clock at 1000000 {
compatible = "allwinner,sun8i-h3-de2-clk";
--
2.14.2
^ permalink raw reply related
* [PATCH v4 3/6] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU
From: Icenowy Zheng @ 2017-12-30 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230113043.30237-1-icenowy@aosc.io>
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v4:
- Use a struct to maintain both ccu desc and quirks as Chen-Yu Tsai
suggested.
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 117 +++++++++++++++++++++++------------
1 file changed, 77 insertions(+), 40 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
index 468d1abaf0ee..b65953b32bd0 100644
--- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
+++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c
@@ -17,6 +17,7 @@
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/reset.h>
+#include <linux/soc/sunxi/sunxi_sram.h>
#include "ccu_common.h"
#include "ccu_div.h"
@@ -156,44 +157,70 @@ static struct ccu_reset_map sun50i_a64_de2_resets[] = {
[RST_WB] = { 0x08, BIT(2) },
};
-static const struct sunxi_ccu_desc sun8i_a83t_de2_clk_desc = {
- .ccu_clks = sun8i_a83t_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
+struct de2_ccu {
+ struct sunxi_ccu_desc desc;
+ bool sram_needed;
+};
+
+static const struct de2_ccu sun8i_a83t_de2_clk = {
+ .desc = {
+ .ccu_clks = sun8i_a83t_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_a83t_de2_clks),
+
+ .hw_clks = &sun8i_a83t_de2_hw_clks,
+
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ },
+};
+
+static const struct de2_ccu sun8i_h3_de2_clk = {
+ .desc = {
+ .ccu_clks = sun8i_h3_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
- .hw_clks = &sun8i_a83t_de2_hw_clks,
+ .hw_clks = &sun8i_h3_de2_hw_clks,
- .resets = sun8i_a83t_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ },
};
-static const struct sunxi_ccu_desc sun8i_h3_de2_clk_desc = {
- .ccu_clks = sun8i_h3_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
+static const struct de2_ccu sun50i_a64_de2_clk = {
+ .desc = {
+ .ccu_clks = sun8i_h3_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
- .hw_clks = &sun8i_h3_de2_hw_clks,
+ .hw_clks = &sun8i_h3_de2_hw_clks,
- .resets = sun8i_a83t_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ .resets = sun50i_a64_de2_resets,
+ .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
+ },
+ .sram_needed = true,
};
-static const struct sunxi_ccu_desc sun50i_a64_de2_clk_desc = {
- .ccu_clks = sun8i_h3_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
+static const struct de2_ccu sun50i_h5_de2_clk = {
+ .desc = {
+ .ccu_clks = sun8i_h3_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_h3_de2_clks),
- .hw_clks = &sun8i_h3_de2_hw_clks,
+ .hw_clks = &sun8i_h3_de2_hw_clks,
- .resets = sun50i_a64_de2_resets,
- .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
+ .resets = sun50i_a64_de2_resets,
+ .num_resets = ARRAY_SIZE(sun50i_a64_de2_resets),
+ },
};
-static const struct sunxi_ccu_desc sun8i_v3s_de2_clk_desc = {
- .ccu_clks = sun8i_v3s_de2_clks,
- .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
+static const struct de2_ccu sun8i_v3s_de2_clk = {
+ .desc = {
+ .ccu_clks = sun8i_v3s_de2_clks,
+ .num_ccu_clks = ARRAY_SIZE(sun8i_v3s_de2_clks),
- .hw_clks = &sun8i_v3s_de2_hw_clks,
+ .hw_clks = &sun8i_v3s_de2_hw_clks,
- .resets = sun8i_a83t_de2_resets,
- .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ .resets = sun8i_a83t_de2_resets,
+ .num_resets = ARRAY_SIZE(sun8i_a83t_de2_resets),
+ },
};
static int sunxi_de2_clk_probe(struct platform_device *pdev)
@@ -202,11 +229,11 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
struct clk *bus_clk, *mod_clk;
struct reset_control *rstc;
void __iomem *reg;
- const struct sunxi_ccu_desc *ccu_desc;
+ const struct de2_ccu *ccu;
int ret;
- ccu_desc = of_device_get_match_data(&pdev->dev);
- if (!ccu_desc)
+ ccu = of_device_get_match_data(&pdev->dev);
+ if (!ccu)
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -239,11 +266,20 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
return ret;
}
+ if (ccu->sram_needed) {
+ ret = sunxi_sram_claim(&pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "Error couldn't map SRAM to device\n");
+ return ret;
+ }
+ }
+
/* The clocks need to be enabled for us to access the registers */
ret = clk_prepare_enable(bus_clk);
if (ret) {
dev_err(&pdev->dev, "Couldn't enable bus clk: %d\n", ret);
- return ret;
+ goto err_release_sram;
}
ret = clk_prepare_enable(mod_clk);
@@ -260,7 +296,7 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
goto err_disable_mod_clk;
}
- ret = sunxi_ccu_probe(pdev->dev.of_node, reg, ccu_desc);
+ ret = sunxi_ccu_probe(pdev->dev.of_node, reg, &ccu->desc);
if (ret)
goto err_assert_reset;
@@ -272,33 +308,34 @@ static int sunxi_de2_clk_probe(struct platform_device *pdev)
clk_disable_unprepare(mod_clk);
err_disable_bus_clk:
clk_disable_unprepare(bus_clk);
+err_release_sram:
+ if (ccu->sram_needed)
+ sunxi_sram_release(&pdev->dev);
+
return ret;
}
static const struct of_device_id sunxi_de2_clk_ids[] = {
{
.compatible = "allwinner,sun8i-a83t-de2-clk",
- .data = &sun8i_a83t_de2_clk_desc,
+ .data = &sun8i_a83t_de2_clk,
},
{
.compatible = "allwinner,sun8i-h3-de2-clk",
- .data = &sun8i_h3_de2_clk_desc,
+ .data = &sun8i_h3_de2_clk,
},
{
.compatible = "allwinner,sun8i-v3s-de2-clk",
- .data = &sun8i_v3s_de2_clk_desc,
+ .data = &sun8i_v3s_de2_clk,
+ },
+ {
+ .compatible = "allwinner,sun50i-a64-de2-clk",
+ .data = &sun50i_a64_de2_clk,
},
{
.compatible = "allwinner,sun50i-h5-de2-clk",
- .data = &sun50i_a64_de2_clk_desc,
+ .data = &sun50i_h5_de2_clk,
},
- /*
- * The Allwinner A64 SoC needs some bit to be poke in syscon to make
- * DE2 really working.
- * So there's currently no A64 compatible here.
- * H5 shares the same reset line with A64, so here H5 is using the
- * clock description of A64.
- */
{ }
};
--
2.14.2
^ permalink raw reply related
* [PATCH v4 4/6] arm64: allwinner: a64: add DE2 CCU for A64 SoC
From: Icenowy Zheng @ 2017-12-30 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230113043.30237-1-icenowy@aosc.io>
The A64 SoC features a DE2 CCU like the one in H5, but needs to claim a
section of SRAM (SRAM C) to be accessed.
Adds the device tree nodes for the SRAM controller and the DE2 CCU.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v3:
- Fixed the alliwnner,sram property (the 1 after SRAM phadle is missing
in v2).
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 34 +++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index d783d164b9c3..fb8ea7c414e1 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -130,6 +130,40 @@
#size-cells = <1>;
ranges;
+ display_clocks: clock at 1000000 {
+ compatible = "allwinner,sun50i-a64-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ allwinner,sram = <&de2_sram 1>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ sram-controller at 1c00000 {
+ compatible = "allwinner,sun50i-a64-sram-controller";
+ reg = <0x01c00000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ sram_c: sram at 18000 {
+ compatible = "mmio-sram";
+ reg = <0x00018000 0x28000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x00018000 0x28000>;
+
+ de2_sram: sram-section at 0 {
+ compatible = "allwinner,sun50i-a64-sram-c";
+ reg = <0x0000 0x28000>;
+ };
+ };
+ };
+
syscon: syscon at 1c00000 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
--
2.14.2
^ permalink raw reply related
* [PATCH v4 5/6] arm64: allwinner: a64: add simplefb for A64 SoC
From: Icenowy Zheng @ 2017-12-30 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230113043.30237-1-icenowy@aosc.io>
The A64 SoC features two display pipelines, one has a LCD output, the
other has a HDMI output.
Add support for simplefb for these pipelines on A64 SoC.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
Changes in v4:
- Dropped extra clocks.
- Added labels to the SimpleFB device tree nodes as boards may have
extra regulator for display pipeline.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index fb8ea7c414e1..d803c115d362 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -42,9 +42,11 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun50i-a64-ccu.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/reset/sun8i-de2.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
/ {
@@ -52,6 +54,30 @@
#address-cells = <1>;
#size-cells = <1>;
+ chosen {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ simplefb_lcd: framebuffer-lcd {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "mixer0-lcd0";
+ clocks = <&display_clocks CLK_MIXER0>,
+ <&ccu CLK_TCON0>;
+ status = "disabled";
+ };
+
+ simplefb_hdmi: framebuffer-hdmi {
+ compatible = "allwinner,simple-framebuffer",
+ "simple-framebuffer";
+ allwinner,pipeline = "mixer1-lcd1-hdmi";
+ clocks = <&display_clocks CLK_MIXER1>,
+ <&ccu CLK_TCON1>, <&ccu CLK_HDMI>;
+ status = "disabled";
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.14.2
^ permalink raw reply related
* [PATCH v4 6/6] arm64: allwinner: a64: add HDMI regulator to all DTs' simplefb_hdmi
From: Icenowy Zheng @ 2017-12-30 11:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230113043.30237-1-icenowy@aosc.io>
On usual A64 board design the power of HDMI controller is connected to
DLDO1 of the AXP803 PMIC. If this regulator is shut down, the HDMI
output will be blank. Therefore the simplefb driver should keep this
regulator on.
Add the regulator to all currently available A64 boards' simplefb_hdmi
device node.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
New patch introduced in v4.
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4 ++++
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts | 4 ++++
6 files changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index a6975670cd1c..f98c496e1f30 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -283,6 +283,10 @@
regulator-name = "vcc-rtc";
};
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
index 2beef9e6cb88..7cbbbf238f4f 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts
@@ -196,6 +196,10 @@
regulator-name = "vcc-rtc";
};
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 8807664f363a..568de83427d0 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -215,6 +215,10 @@
regulator-name = "vcc-rtc";
};
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
index 240d35731d10..ce38080db324 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-orangepi-win.dts
@@ -192,6 +192,10 @@
regulator-name = "vcc-rtc";
};
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
index 604cdaedac38..40d9802959c4 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
@@ -230,6 +230,10 @@
regulator-name = "vcc-rtc";
};
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
/* On Exp and Euler connectors */
&uart0 {
pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
index abe179de35d7..c21f2331add6 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboard.dts
@@ -134,6 +134,10 @@
regulator-name = "vcc-wifi";
};
+&simplefb_hdmi {
+ vcc-hdmi-supply = <®_dldo1>;
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
--
2.14.2
^ permalink raw reply related
* [PATCH 1/6] phy: sun4i-usb: add support for R40 USB PHY
From: Icenowy Zheng @ 2017-12-30 11:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <020a2b04-dbcc-032a-89d1-75479dd436e7@ti.com>
? 2017?10?18???? CST ??7:46:08?Kishon Vijay Abraham I ???
> On Wednesday 18 October 2017 05:12 PM, Maxime Ripard wrote:
> > On Wed, Oct 18, 2017 at 05:09:00PM +0530, Kishon Vijay Abraham I wrote:
> >> Hi,
> >>
> >> On Tuesday 10 October 2017 02:28 AM, Maxime Ripard wrote:
> >>> On Sun, Oct 08, 2017 at 04:29:01AM +0000, Icenowy Zheng wrote:
> >>>> Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
> >>>>
> >>>> Add support for it.
> >>>>
> >>>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >>>
> >>> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >>
> >> Is this patch good to be merged? I see you have pending comments on the
> >> other patch in the series.
> >
> > Yeah, but I guess you can merge this one, it's pretty harmless, and it
> > will reduce the amount of patches to review / merge later on.
>
> Thank you for the quick reply.
>
> merged with Maxime's and Rob's Ack.
Sorry, but I didn't see the patch appears in linux-next for such long time.
Is it lost?
>
> Thanks
> Kishon
^ permalink raw reply
* [PATCH v5 03/12] dt-bindings: display: sun4i-drm: Add LVDS properties
From: Jernej Škrabec @ 2017-12-30 11:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <ddbde28fe2e4f21412974e4c69fbfe1c5ff9383f.1513854122.git-series.maxime.ripard@free-electrons.com>
Hi Maxime,
Dne ?etrtek, 21. december 2017 ob 12:02:29 CET je Maxime Ripard napisal(a):
> Some clocks and resets supposed to drive the LVDS logic in the display
> engine have been overlooked when the driver was first introduced.
>
> Add those additional resources to the binding, and we'll deal with the ABI
> stability in the code.
>
> Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> ---
> Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 9 +++++++-
> 1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> 50cc72ee1168..1e21cfaac9e2 100644
> --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> @@ -121,6 +121,15 @@ Required properties:
> On SoCs other than the A33 and V3s, there is one more clock required:
> - 'tcon-ch1': The clock driving the TCON channel 1
>
> +On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
> +need one more reset line:
> + - 'lvds': The reset line driving the LVDS logic
> +
> +And on the SoCs newer than the A31 (sun6i and sun8i families), you
> +need one more clock line:
> + - 'lvds-alt': An alternative clock source, separate from the TCON
> channel 0 + clock, that can be used to drive the LVDS clock
I think this wording is imprecise, since A83T is part of the sun8i family, but
from the code (patch 7) and DT changes (patch 9) you do, it doesn't need this
property.
Maybe it would be just easier to enumerate all compatibles which needs this
property?
Best regards,
Jernej
^ permalink raw reply
* [PATCH V2] ARM: imx: introduce imx_l2c310_write_sec
From: Peng Fan @ 2017-12-30 12:34 UTC (permalink / raw)
To: linux-arm-kernel
Some PL310 registers could only be wrote in secure world, so
introduce imx_l2c310_write_sec to support Linux running in
non-secure world configure PL310.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <kernel@pengutronix.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
---
V2:
Use SPDX Tag
Use CONFIG_HAVE_ARM_SMCCC to fix build error for armv5.
Add IS_ENABLED(CONFIG_OPTEE) check when assigning write_sec
arch/arm/mach-imx/system.c | 27 ++++++++++++++++++++++++++-
include/soc/imx/imx_sip_smc.h | 21 +++++++++++++++++++++
2 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 include/soc/imx/imx_sip_smc.h
diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
index c06af650e6b1..2c27e52d8c7d 100644
--- a/arch/arm/mach-imx/system.c
+++ b/arch/arm/mach-imx/system.c
@@ -23,11 +23,13 @@
#include <linux/delay.h>
#include <linux/of.h>
#include <linux/of_address.h>
+#include <soc/imx/imx_sip_smc.h>
#include <asm/system_misc.h>
#include <asm/proc-fns.h>
#include <asm/mach-types.h>
#include <asm/hardware/cache-l2x0.h>
+#include <asm/outercache.h>
#include "common.h"
#include "hardware.h"
@@ -92,6 +94,22 @@ void __init imx1_reset_init(void __iomem *base)
#endif
#ifdef CONFIG_CACHE_L2X0
+#ifdef CONFIG_HAVE_ARM_SMCCC
+void imx_l2c310_write_sec(unsigned long val, unsigned int reg)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(IMX_SIP_SMC_L2C310, val, reg, 0, 0, 0, 0, 0, &res);
+
+ if (res.a0 != 0)
+ pr_err("Failed to write l2c310 0x%x: 0x%lx\n", reg, res.a0);
+}
+#else
+void imx_l2c310_write_sec(unsigned long val, unsigned int reg)
+{
+}
+#endif
+
void __init imx_init_l2cache(void)
{
void __iomem *l2x0_base;
@@ -102,6 +120,10 @@ void __init imx_init_l2cache(void)
if (!np)
return;
+ if (IS_ENABLED(CONFIG_OPTEE) &&
+ of_find_compatible_node(NULL, NULL, "linaro,optee-tz"))
+ outer_cache.write_sec = imx_l2c310_write_sec;
+
l2x0_base = of_iomap(np, 0);
if (!l2x0_base)
goto put_node;
@@ -117,7 +139,10 @@ void __init imx_init_l2cache(void)
val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
val |= 15;
- writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
+ if (outer_cache.write_sec)
+ outer_cache.write_sec(val, L310_PREFETCH_CTRL);
+ else
+ writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
}
iounmap(l2x0_base);
diff --git a/include/soc/imx/imx_sip_smc.h b/include/soc/imx/imx_sip_smc.h
new file mode 100644
index 000000000000..c35ae69e0d2f
--- /dev/null
+++ b/include/soc/imx/imx_sip_smc.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright 2017 NXP
+ *
+ * SPDX-License-Identifier: GPL-2.0
+ */
+
+#ifndef __IMX_SIP_SMC_H_
+#define __IMX_SIP_SMC_H_
+
+#include <linux/arm-smccc.h>
+
+#define IMX_SIP_SMC_VAL(func) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
+ ARM_SMCCC_SMC_32, \
+ ARM_SMCCC_OWNER_SIP, \
+ (func))
+
+#define IMX_L2C310 0x1
+
+#define IMX_SIP_SMC_L2C310 IMX_SIP_SMC_VAL(IMX_L2C310)
+
+#endif
--
2.14.1
^ permalink raw reply related
* [PATCH 1/2] ARM: imx: no unmask/mask GINT for WAIT_CLOCKED
From: Peng Fan @ 2017-12-30 13:53 UTC (permalink / raw)
To: linux-arm-kernel
WAIT_CLOCKED is for RUN mode, there is no need to unmask/mask
IRQ32 in GPC.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V1:
This is to upstream patch:
http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git/commit/?h=imx_4.9.11_1.0.0_ga&id=0d980646ee068b92db71fd5e4e4efcbc33749cbd
arch/arm/mach-imx/pm-imx6.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 153a0afc7645..56bfd9b5229e 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -337,9 +337,11 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
*
* Note that IRQ #32 is GIC SPI #0.
*/
- imx_gpc_hwirq_unmask(0);
+ if (mode != WAIT_CLOCKED)
+ imx_gpc_hwirq_unmask(0);
writel_relaxed(val, ccm_base + CLPCR);
- imx_gpc_hwirq_mask(0);
+ if (mode != WAIT_CLOCKED)
+ imx_gpc_hwirq_mask(0);
return 0;
}
--
2.14.1
^ permalink raw reply related
* [PATCH 2/2] ARM: imx: cpuidle-imx6q: configure CCM to RUN mode when CPU is active
From: Peng Fan @ 2017-12-30 13:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514641999-20521-1-git-send-email-peng.fan@nxp.com>
There are two states in i.MX6Q cpuidle driver.
state[1]: ARM WFI mode
state[2]: i.MX6Q WAIT mode
Take i.MX6DL as example, think out such a case:
1. CPU0/1 both run at normal mode
2. On CPU0, `sleep 1` is executed. And there are no workload on CPU1.
3. CPU0 first runs into state[2] and 'wfi' instruction. Switched to use
GPT broadcast.
4. CPU1 runs into state[2] and configure CCM to WAIT MODE,
then 'wfi' instruction. Now arm_clk and local timer clock are
shutdown. Switched to use GPT broadcast
5. GPT broadcast timer interrupt comes to GPC/GIC, then CPU0 wakes up.
CPU0 switched to use arm local timer. CPU1 is still sleeping.
6. No workload on CPU0, CPU0 runs into state[1]. But CCM register
is still not restored to Normal RUN mode. 'wfi' + CCM WAIT will
cause arm_clk and arm core clk.
Now CPU0 stops, which is not correct.
So, need to make sure CCM configured to RUN mode when any cpu exit
state[2].
In this patch,
When CPU exits state[2], it configures CCM to RUN mode.
When all CPUs enters state[2], the last CPU needs to check
whether it's ok to configure CCM to WAIT mode or not.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
V1:
This is to upstream patch:
http://git.freescale.com/git/cgit.cgi/imx/linux-imx.git/commit/?h=imx_4.9.11_1.0.0_ga&id=0d980646ee068b92db71fd5e4e4efcbc33749cbd
arch/arm/mach-imx/cpuidle-imx6q.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index bfeb25aaf9a2..4d342e2fdfe6 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -30,6 +30,8 @@ static int imx6q_enter_wait(struct cpuidle_device *dev,
if (!spin_trylock(&master_lock))
goto idle;
imx6_set_lpm(WAIT_UNCLOCKED);
+ if (atomic_read(&master) != num_online_cpus())
+ imx6_set_lpm(WAIT_CLOCKED);
cpu_do_idle();
imx6_set_lpm(WAIT_CLOCKED);
spin_unlock(&master_lock);
@@ -41,6 +43,7 @@ static int imx6q_enter_wait(struct cpuidle_device *dev,
done:
atomic_dec(&master);
+ imx6_set_lpm(WAIT_CLOCKED);
return index;
}
--
2.14.1
^ permalink raw reply related
* [PATCH V2] ARM: imx: introduce imx_l2c310_write_sec
From: Philippe Ombredanne @ 2017-12-30 14:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514637243-20111-1-git-send-email-peng.fan@nxp.com>
On Sat, Dec 30, 2017 at 1:34 PM, Peng Fan <peng.fan@nxp.com> wrote:
> Some PL310 registers could only be wrote in secure world, so
> introduce imx_l2c310_write_sec to support Linux running in
> non-secure world configure PL310.
>
> Signed-off-by: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>
> Cc: Sascha Hauer <kernel@pengutronix.de>
> Cc: Fabio Estevam <fabio.estevam@nxp.com>
> Cc: Dong Aisheng <aisheng.dong@nxp.com>
> ---
>
> V2:
> Use SPDX Tag
> Use CONFIG_HAVE_ARM_SMCCC to fix build error for armv5.
> Add IS_ENABLED(CONFIG_OPTEE) check when assigning write_sec
>
> arch/arm/mach-imx/system.c | 27 ++++++++++++++++++++++++++-
> include/soc/imx/imx_sip_smc.h | 21 +++++++++++++++++++++
> 2 files changed, 47 insertions(+), 1 deletion(-)
> create mode 100644 include/soc/imx/imx_sip_smc.h
>
> diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
> index c06af650e6b1..2c27e52d8c7d 100644
> --- a/arch/arm/mach-imx/system.c
> +++ b/arch/arm/mach-imx/system.c
> @@ -23,11 +23,13 @@
> #include <linux/delay.h>
> #include <linux/of.h>
> #include <linux/of_address.h>
> +#include <soc/imx/imx_sip_smc.h>
>
> #include <asm/system_misc.h>
> #include <asm/proc-fns.h>
> #include <asm/mach-types.h>
> #include <asm/hardware/cache-l2x0.h>
> +#include <asm/outercache.h>
>
> #include "common.h"
> #include "hardware.h"
> @@ -92,6 +94,22 @@ void __init imx1_reset_init(void __iomem *base)
> #endif
>
> #ifdef CONFIG_CACHE_L2X0
> +#ifdef CONFIG_HAVE_ARM_SMCCC
> +void imx_l2c310_write_sec(unsigned long val, unsigned int reg)
> +{
> + struct arm_smccc_res res;
> +
> + arm_smccc_smc(IMX_SIP_SMC_L2C310, val, reg, 0, 0, 0, 0, 0, &res);
> +
> + if (res.a0 != 0)
> + pr_err("Failed to write l2c310 0x%x: 0x%lx\n", reg, res.a0);
> +}
> +#else
> +void imx_l2c310_write_sec(unsigned long val, unsigned int reg)
> +{
> +}
> +#endif
> +
> void __init imx_init_l2cache(void)
> {
> void __iomem *l2x0_base;
> @@ -102,6 +120,10 @@ void __init imx_init_l2cache(void)
> if (!np)
> return;
>
> + if (IS_ENABLED(CONFIG_OPTEE) &&
> + of_find_compatible_node(NULL, NULL, "linaro,optee-tz"))
> + outer_cache.write_sec = imx_l2c310_write_sec;
> +
> l2x0_base = of_iomap(np, 0);
> if (!l2x0_base)
> goto put_node;
> @@ -117,7 +139,10 @@ void __init imx_init_l2cache(void)
> val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
> val |= 15;
>
> - writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
> + if (outer_cache.write_sec)
> + outer_cache.write_sec(val, L310_PREFETCH_CTRL);
> + else
> + writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
> }
>
> iounmap(l2x0_base);
> diff --git a/include/soc/imx/imx_sip_smc.h b/include/soc/imx/imx_sip_smc.h
> new file mode 100644
> index 000000000000..c35ae69e0d2f
> --- /dev/null
> +++ b/include/soc/imx/imx_sip_smc.h
> @@ -0,0 +1,21 @@
> +/*
> + * Copyright 2017 NXP
> + *
> + * SPDX-License-Identifier: GPL-2.0
> + */
> +
Thanks! but the SPDX tag should be on the first line as its own
comment. So this would come out something like this
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/* Copyright 2017 NXP */
or
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright 2017 NXP
> + */
> +#ifndef __IMX_SIP_SMC_H_
> +#define __IMX_SIP_SMC_H_
> +
> +#include <linux/arm-smccc.h>
> +
> +#define IMX_SIP_SMC_VAL(func) ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
> + ARM_SMCCC_SMC_32, \
> + ARM_SMCCC_OWNER_SIP, \
> + (func))
> +
> +#define IMX_L2C310 0x1
> +
> +#define IMX_SIP_SMC_L2C310 IMX_SIP_SMC_VAL(IMX_L2C310)
> +
> +#endif
> --
> 2.14.1
>
--
Cordially
Philippe Ombredanne
^ permalink raw reply
* [PATCH V2] ARM: imx: introduce imx_l2c310_write_sec
From: Peng Fan @ 2017-12-30 14:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOFm3uGL=zyxj5VzKAKsAcU6bcL2bJQCcvP9eg4qYAKN00iwJg@mail.gmail.com>
> -----Original Message-----
> From: Philippe Ombredanne [mailto:pombredanne at nexb.com]
> Sent: Saturday, December 30, 2017 10:17 PM
> To: Peng Fan <peng.fan@nxp.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; moderated list:ARM/FREESCALE IMX
> / MXC ARM ARCHITECTURE <linux-arm-kernel@lists.infradead.org>; LKML
> <linux-kernel@vger.kernel.org>; Peng Fan <van.freenix@gmail.com>; Sascha
> Hauer <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>;
> A.s. Dong <aisheng.dong@nxp.com>
> Subject: Re: [PATCH V2] ARM: imx: introduce imx_l2c310_write_sec
>
> On Sat, Dec 30, 2017 at 1:34 PM, Peng Fan <peng.fan@nxp.com> wrote:
> > Some PL310 registers could only be wrote in secure world, so introduce
> > imx_l2c310_write_sec to support Linux running in non-secure world
> > configure PL310.
> >
> > Signed-off-by: Peng Fan <peng.fan@nxp.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>
> > Cc: Sascha Hauer <kernel@pengutronix.de>
> > Cc: Fabio Estevam <fabio.estevam@nxp.com>
> > Cc: Dong Aisheng <aisheng.dong@nxp.com>
> > ---
> >
> > V2:
> > Use SPDX Tag
> > Use CONFIG_HAVE_ARM_SMCCC to fix build error for armv5.
> > Add IS_ENABLED(CONFIG_OPTEE) check when assigning write_sec
> >
> > arch/arm/mach-imx/system.c | 27 ++++++++++++++++++++++++++-
> > include/soc/imx/imx_sip_smc.h | 21 +++++++++++++++++++++
> > 2 files changed, 47 insertions(+), 1 deletion(-) create mode 100644
> > include/soc/imx/imx_sip_smc.h
> >
> > diff --git a/arch/arm/mach-imx/system.c b/arch/arm/mach-imx/system.c
> > index c06af650e6b1..2c27e52d8c7d 100644
> > --- a/arch/arm/mach-imx/system.c
> > +++ b/arch/arm/mach-imx/system.c
> > @@ -23,11 +23,13 @@
> > #include <linux/delay.h>
> > #include <linux/of.h>
> > #include <linux/of_address.h>
> > +#include <soc/imx/imx_sip_smc.h>
> >
> > #include <asm/system_misc.h>
> > #include <asm/proc-fns.h>
> > #include <asm/mach-types.h>
> > #include <asm/hardware/cache-l2x0.h>
> > +#include <asm/outercache.h>
> >
> > #include "common.h"
> > #include "hardware.h"
> > @@ -92,6 +94,22 @@ void __init imx1_reset_init(void __iomem *base)
> > #endif
> >
> > #ifdef CONFIG_CACHE_L2X0
> > +#ifdef CONFIG_HAVE_ARM_SMCCC
> > +void imx_l2c310_write_sec(unsigned long val, unsigned int reg) {
> > + struct arm_smccc_res res;
> > +
> > + arm_smccc_smc(IMX_SIP_SMC_L2C310, val, reg, 0, 0, 0, 0, 0,
> > + &res);
> > +
> > + if (res.a0 != 0)
> > + pr_err("Failed to write l2c310 0x%x: 0x%lx\n", reg,
> > +res.a0); } #else void imx_l2c310_write_sec(unsigned long val,
> > +unsigned int reg) { } #endif
> > +
> > void __init imx_init_l2cache(void)
> > {
> > void __iomem *l2x0_base;
> > @@ -102,6 +120,10 @@ void __init imx_init_l2cache(void)
> > if (!np)
> > return;
> >
> > + if (IS_ENABLED(CONFIG_OPTEE) &&
> > + of_find_compatible_node(NULL, NULL, "linaro,optee-tz"))
> > + outer_cache.write_sec = imx_l2c310_write_sec;
> > +
> > l2x0_base = of_iomap(np, 0);
> > if (!l2x0_base)
> > goto put_node;
> > @@ -117,7 +139,10 @@ void __init imx_init_l2cache(void)
> > val &= ~L310_PREFETCH_CTRL_OFFSET_MASK;
> > val |= 15;
> >
> > - writel_relaxed(val, l2x0_base + L310_PREFETCH_CTRL);
> > + if (outer_cache.write_sec)
> > + outer_cache.write_sec(val, L310_PREFETCH_CTRL);
> > + else
> > + writel_relaxed(val, l2x0_base +
> > + L310_PREFETCH_CTRL);
> > }
> >
> > iounmap(l2x0_base);
> > diff --git a/include/soc/imx/imx_sip_smc.h
> > b/include/soc/imx/imx_sip_smc.h new file mode 100644 index
> > 000000000000..c35ae69e0d2f
> > --- /dev/null
> > +++ b/include/soc/imx/imx_sip_smc.h
> > @@ -0,0 +1,21 @@
> > +/*
> > + * Copyright 2017 NXP
> > + *
> > + * SPDX-License-Identifier: GPL-2.0
> > + */
> > +
>
> Thanks! but the SPDX tag should be on the first line as its own comment. So this
> would come out something like this
>
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/* Copyright 2017 NXP */
>
> or
>
> > +/* SPDX-License-Identifier: GPL-2.0 */
> > +/*
> > + * Copyright 2017 NXP
> > + */
>
Thanks. I'll correct in V3. Before that, I would like to see if more comments
about the code. Then I'll address them all in V3.
Thanks,
Peng.
>
>
> > +#ifndef __IMX_SIP_SMC_H_
> > +#define __IMX_SIP_SMC_H_
> > +
> > +#include <linux/arm-smccc.h>
> > +
> > +#define IMX_SIP_SMC_VAL(func)
> ARM_SMCCC_CALL_VAL(ARM_SMCCC_FAST_CALL, \
> > + ARM_SMCCC_SMC_32, \
> > + ARM_SMCCC_OWNER_SIP, \
> > + (func))
> > +
> > +#define IMX_L2C310 0x1
> > +
> > +#define IMX_SIP_SMC_L2C310 IMX_SIP_SMC_VAL(IMX_L2C310)
> > +
> > +#endif
> > --
> > 2.14.1
> >
>
>
>
> --
> Cordially
> Philippe Ombredanne
^ permalink raw reply
* [PATCH] arm64: Target aarch64elf emulation to allow bare-metal toolchains
From: Paul Kocialkowski @ 2017-12-30 15:08 UTC (permalink / raw)
To: linux-arm-kernel
This sets the LDFLAGS variable to target the aarch64elf emulation
instead of aarch64linux, which is incompatible with bare-metal
toolchains.
This change allows the kernel to build with bare-metal toolchains again.
Fixes: 3d6a7b99e3fa ("arm64: ensure the kernel is compiled for LP64")
Cc: stable at vger.kernel.org
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
---
arch/arm64/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/Makefile b/arch/arm64/Makefile
index b481b4a7c011..a249233edcd8 100644
--- a/arch/arm64/Makefile
+++ b/arch/arm64/Makefile
@@ -64,14 +64,14 @@ KBUILD_CPPFLAGS += -mbig-endian
CHECKFLAGS += -D__AARCH64EB__
AS += -EB
LD += -EB
-LDFLAGS += -maarch64linuxb
+LDFLAGS += -maarch64elfb
UTS_MACHINE := aarch64_be
else
KBUILD_CPPFLAGS += -mlittle-endian
CHECKFLAGS += -D__AARCH64EL__
AS += -EL
LD += -EL
-LDFLAGS += -maarch64linux
+LDFLAGS += -maarch64elf
UTS_MACHINE := aarch64
endif
--
2.15.1
^ permalink raw reply related
* [PATCH 0/3] axp20x backup battery charging
From: Paul Kocialkowski @ 2017-12-30 15:23 UTC (permalink / raw)
To: linux-arm-kernel
This series introduces support for axp20x backup battery charging, with
a dedicated device-tree property.
I wondered whether to include this in a power-supply driver or not.
Since it does not, in fact, supply power to the whole system and
because no status changes over time, I thought it would be inappropriate
to craft a power supply driver only for this.
I also wondered whether to stick this into an existing power-supply
driver, as is done by e.g. twl4030, but we have two distinct supply
drivers for the axp20x (ac and usb), that may be used together or not.
Also, the backup battery isn't tied to the power supply anyway.
This is why I thought it would make more sense to put this in the mfd
driver directly. What do you think?
^ permalink raw reply
* [PATCH 1/3] dt-bindings: mfd: axp20x: Document backup battery charging property
From: Paul Kocialkowski @ 2017-12-30 15:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230152330.28946-1-contact@paulk.fr>
This adds documentation for the "backup" property of the axp20x driver,
that controls the charging mechanism for the backup battery on axp20x.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt
index 9455503b0299..382776b29932 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -58,6 +58,11 @@ Optional properties:
See Documentation/devicetree/bindings/regulator/regulator.txt
for more information on standard regulator bindings.
+- backup: An array of two integers for backup battery charging (axp20x-only),
+ describing the charging voltage in mV first and the charging current
+ in uA second. Backup battery charging is only enabled when these two
+ fields are filled.
+
Optional properties for DCDC regulators:
- x-powers,dcdc-workmode: 1 for PWM mode, 0 for AUTO (PWM/PFM) mode
Default: Current hardware setting
@@ -256,4 +261,6 @@ axp209: pmic at 34 {
/* unused but preferred to be managed by OS */
};
};
+
+ backup = <3000 200>;
};
--
2.15.1
^ permalink raw reply related
* [PATCH 2/3] mfd: axp20x: Add support for backup battery charging
From: Paul Kocialkowski @ 2017-12-30 15:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230152330.28946-1-contact@paulk.fr>
This adds support for backup battery charging for axp20x PMICs, that is
configured through a dedicated device-tree property.
It supports 4 different charging voltages and as many charging currents.
This is especially useful to allow the on-chip RTC (on the SoC side) to
be powered when the rest of the system is off.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
diff --git a/drivers/mfd/axp20x.c b/drivers/mfd/axp20x.c
index 2468b431bb22..7847f5d0b979 100644
--- a/drivers/mfd/axp20x.c
+++ b/drivers/mfd/axp20x.c
@@ -34,6 +34,16 @@
#define AXP806_REG_ADDR_EXT_ADDR_MASTER_MODE 0
#define AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE BIT(4)
+#define AXP20X_CHRG_BAK_CTRL_ENABLE BIT(7)
+#define AXP20X_CHRG_BAK_VOLTAGE_3100_MV (0 << 5)
+#define AXP20X_CHRG_BAK_VOLTAGE_3000_MV (1 << 5)
+#define AXP20X_CHRG_BAK_VOLTAGE_3600_MV (2 << 5)
+#define AXP20X_CHRG_BAK_VOLTAGE_2500_MV (3 << 5)
+#define AXP20X_CHRG_BAK_CURRENT_50_UA (0 << 0)
+#define AXP20X_CHRG_BAK_CURRENT_100_UA (1 << 0)
+#define AXP20X_CHRG_BAK_CURRENT_200_UA (2 << 0)
+#define AXP20X_CHRG_BAK_CURRENT_400_UA (3 << 0)
+
static const char * const axp20x_model_names[] = {
"AXP152",
"AXP202",
@@ -894,6 +904,63 @@ static void axp20x_power_off(void)
msleep(500);
}
+static void axp20x_backup_setup(struct axp20x_dev *axp20x)
+{
+ u32 backup[2];
+ int reg;
+ int ret;
+
+ ret = of_property_read_u32_array(axp20x->dev->of_node, "backup", backup,
+ 2);
+ if (ret != 0)
+ return;
+
+ switch (axp20x->variant) {
+ case AXP202_ID:
+ case AXP209_ID:
+ reg = AXP20X_CHRG_BAK_CTRL_ENABLE;
+
+ /* Charging voltage. */
+ switch (backup[0]) {
+ case 2500:
+ reg |= AXP20X_CHRG_BAK_VOLTAGE_2500_MV;
+ break;
+ case 3000:
+ reg |= AXP20X_CHRG_BAK_VOLTAGE_3000_MV;
+ break;
+ case 3100:
+ reg |= AXP20X_CHRG_BAK_VOLTAGE_3100_MV;
+ break;
+ case 3600:
+ reg |= AXP20X_CHRG_BAK_VOLTAGE_3600_MV;
+ break;
+ default:
+ return;
+ }
+
+ /* Charging current. */
+ switch (backup[1]) {
+ case 50:
+ reg |= AXP20X_CHRG_BAK_CURRENT_50_UA;
+ break;
+ case 100:
+ reg |= AXP20X_CHRG_BAK_CURRENT_100_UA;
+ break;
+ case 200:
+ reg |= AXP20X_CHRG_BAK_CURRENT_200_UA;
+ break;
+ case 400:
+ reg |= AXP20X_CHRG_BAK_CURRENT_400_UA;
+ break;
+ default:
+ return;
+ }
+
+ regmap_write(axp20x->regmap, AXP20X_CHRG_BAK_CTRL, reg);
+ break;
+ }
+}
+
int axp20x_match_device(struct axp20x_dev *axp20x)
{
struct device *dev = axp20x->dev;
@@ -1023,6 +1090,9 @@ int axp20x_device_probe(struct axp20x_dev *axp20x)
AXP806_REG_ADDR_EXT_ADDR_SLAVE_MODE);
}
+ /* Backup RTC battery. */
+ axp20x_backup_setup(axp20x);
+
ret = regmap_add_irq_chip(axp20x->regmap, axp20x->irq,
IRQF_ONESHOT | IRQF_SHARED | axp20x->irq_flags,
-1, axp20x->regmap_irq_chip, &axp20x->regmap_irqc);
--
2.15.1
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: sun7i: lamobo-r1: Add backup battery charging property
From: Paul Kocialkowski @ 2017-12-30 15:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230152330.28946-1-contact@paulk.fr>
This adds the axp20x backup property to the lamobo-r1 device-tree,
that allows charging the backup battery attached to its AXP209.
It is especially useful since the battery is used for the RTC module.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
diff --git a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
index 442f3c755f36..e218fd8ea94f 100644
--- a/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
+++ b/arch/arm/boot/dts/sun7i-a20-lamobo-r1.dts
@@ -207,6 +207,8 @@
reg = <0x34>;
interrupt-parent = <&nmi_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+
+ backup = <3000 200>;
};
};
--
2.15.1
^ permalink raw reply related
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