* [PATCH 05/11] drm/bridge/synopsys: dw-hdmi: Add deinit callback
From: Jernej Skrabec @ 2017-12-30 21:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230210203.24115-1-jernej.skrabec@siol.net>
Some SoCs, like Allwinner A83T, have to do additional cleanup when
HDMI driver unloads. When using DW HDMI through DRM bridge API, there is
no place to store driver's private data so it can be accessed in unbind
function. Because of that, add deinit function which is called at the
very end, so drivers can do a proper cleanup.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
include/drm/bridge/dw_hdmi.h | 1 +
2 files changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
index 67467d0b683a..a6fe7a323c83 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
@@ -2592,6 +2592,9 @@ static void __dw_hdmi_remove(struct dw_hdmi *hdmi)
i2c_del_adapter(&hdmi->i2c->adap);
else
i2c_put_adapter(hdmi->ddc);
+
+ if (hdmi->plat_data->deinit)
+ hdmi->plat_data->deinit(hdmi->plat_data);
}
/* -----------------------------------------------------------------------------
diff --git a/include/drm/bridge/dw_hdmi.h b/include/drm/bridge/dw_hdmi.h
index f5cca4362154..a3218d3da61b 100644
--- a/include/drm/bridge/dw_hdmi.h
+++ b/include/drm/bridge/dw_hdmi.h
@@ -124,6 +124,7 @@ struct dw_hdmi_phy_ops {
struct dw_hdmi_plat_data {
struct regmap *regm;
+ void (*deinit)(const struct dw_hdmi_plat_data *pdata);
enum drm_mode_status (*mode_valid)(struct drm_connector *connector,
const struct drm_display_mode *mode);
unsigned long input_bus_format;
--
2.15.1
^ permalink raw reply related
* [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Jernej Skrabec @ 2017-12-30 21:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230210203.24115-1-jernej.skrabec@siol.net>
This commit adds all necessary compatibles and descriptions needed to
implement A83T HDMI pipeline.
Mixer is already properly described, so only compatible is added.
However, A83T TCON1, which is connected to HDMI, doesn't have channel 0,
contrary to all TCONs currently described. Because of that, TCON
documentation is extended.
A83T features Synopsys DW HDMI controller with a custom PHY which looks
like Synopsys Gen2 PHY with few additions. Since there is no
documentation, needed properties were found out through experimentation
and reading BSP code.
At the end, example is added for newer SoCs, which features DE2 and DW
HDMI.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
.../bindings/display/sunxi/sun4i-drm.txt | 188 ++++++++++++++++++++-
1 file changed, 181 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 9f073af4c711..3eca258096a5 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -64,6 +64,40 @@ Required properties:
first port should be the input endpoint. The second should be the
output, usually to an HDMI connector.
+DWC HDMI TX Encoder
+-----------------------------
+
+The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
+with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
+
+These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
+Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
+following device-specific properties.
+
+Required properties:
+
+ - compatible: value must be one of:
+ * "allwinner,sun8i-a83t-dw-hdmi"
+ - reg: two pairs of base address and size of memory-mapped region, first
+ for controller and second for PHY
+ registers.
+ - reg-io-width: See dw_hdmi.txt. Shall be 1.
+ - interrupts: HDMI interrupt number
+ - clocks: phandles to the clocks feeding the HDMI encoder
+ * iahb: the HDMI bus clock
+ * isfr: the HDMI register clock
+ * tmds: the HDMI tmds clock
+ - clock-names: the clock names mentioned above
+ - resets: phandles to the reset controllers driving the encoder
+ * ctrl: the reset line for the controller
+ * phy: the reset line for the PHY
+ - reset-names: the reset names mentioned above
+
+ - ports: A ports node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt. The
+ first port should be the input endpoint. The second should be the
+ output, usually to an HDMI connector.
+
TV Encoder
----------
@@ -94,18 +128,17 @@ Required properties:
* allwinner,sun7i-a20-tcon
* allwinner,sun8i-a33-tcon
* allwinner,sun8i-a83t-tcon-lcd
+ * allwinner,sun8i-a83t-tcon-tv
* allwinner,sun8i-v3s-tcon
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- - clocks: phandles to the clocks feeding the TCON. Three are needed:
+ - clocks: phandles to the clocks feeding the TCON. One is needed:
- 'ahb': the interface clocks
- - 'tcon-ch0': The clock driving the TCON channel 0
- resets: phandles to the reset controllers driving the encoder
- "lcd": the reset line for the TCON channel 0
- clock-names: the clock names mentioned above
- reset-names: the reset names mentioned above
- - clock-output-names: Name of the pixel clock created
- ports: A ports node with endpoint definitions as defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
@@ -119,11 +152,31 @@ Required properties:
channel the endpoint is associated to. If that property is not
present, the endpoint number will be used as the channel number.
-On SoCs other than the A33 and V3s, there is one more clock required:
+Following compatibles:
+ * allwinner,sun4i-a10-tcon
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun7i-a20-tcon
+ * allwinner,sun8i-a33-tcon
+ * allwinner,sun8i-a83t-tcon-lcd
+ * allwinner,sun8i-v3s-tcon
+have additional required properties:
+ - 'tcon-ch0': The clock driving the TCON channel 0
+ - clock-output-names: Name of the pixel clock created
+
+For following compatibles:
+ * allwinner,sun4i-a10-tcon
+ * allwinner,sun5i-a13-tcon
+ * allwinner,sun6i-a31-tcon
+ * allwinner,sun6i-a31s-tcon
+ * allwinner,sun7i-a20-tcon
+ * allwinner,sun8i-a83t-tcon-tv
+there is one more clock required:
- 'tcon-ch1': The clock driving the TCON channel 1
-On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
-need one more reset line:
+On TCONs that support LVDS (all TCONs except the ones found on A13, H3, H5, V3s
+and TCON1 on A83T), you need one more reset line:
- 'lvds': The reset line driving the LVDS logic
And on the SoCs newer than the A31 (sun6i and sun8i families), you
@@ -227,6 +280,7 @@ supported.
Required properties:
- compatible: value must be one of:
* allwinner,sun8i-a83t-de2-mixer-0
+ * allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-v3s-de2-mixer
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
@@ -262,7 +316,7 @@ Required properties:
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
-Example:
+Example 1:
panel: panel {
compatible = "olimex,lcd-olinuxino-43-ts";
@@ -461,3 +515,123 @@ display-engine {
compatible = "allwinner,sun5i-a13-display-engine";
allwinner,pipelines = <&fe0>;
};
+
+Example 2:
+
+connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+};
+
+de: display-engine {
+ compatible = "allwinner,sun8i-a83t-display-engine";
+ allwinner,pipelines = <&mixer1>;
+};
+
+mixer1: mixer at 1200000 {
+ compatible = "allwinner,sun8i-a83t-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon1_in_mixer1>;
+ };
+ };
+ };
+};
+
+tcon1: lcd-controller at 1c0d000 {
+ compatible = "allwinner,sun8i-a83t-tcon-tv";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON1>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_mixer1: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&mixer1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ };
+ };
+ };
+};
+
+hdmi: hdmi at 1ee0000 {
+ compatible = "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>,
+ <0x01ef0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;
+ reset-names = "phy", "ctrl";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon1: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+ };
+ };
+};
--
2.15.1
^ permalink raw reply related
* [PATCH 07/11] drm/sun4i: Add support for A83T second TCON
From: Jernej Skrabec @ 2017-12-30 21:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230210203.24115-1-jernej.skrabec@siol.net>
This TCON doesn't have channel 0, so quirk has_channel_0 is added in the
process.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun4i_tcon.c | 46 ++++++++++++++++++++++++++++----------
drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
2 files changed, 35 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
index b78fed809992..adfa39f372cf 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
@@ -84,6 +84,7 @@ static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel,
switch (channel) {
case 0:
+ WARN_ON(!tcon->quirks->has_channel_0);
regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG,
SUN4I_TCON0_CTL_TCON_ENABLE,
enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0);
@@ -276,6 +277,8 @@ static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon,
u8 clk_delay;
u32 reg, val = 0;
+ WARN_ON(!tcon->quirks->has_channel_0);
+
tcon->dclk_min_div = 7;
tcon->dclk_max_div = 7;
sun4i_tcon0_mode_set_common(tcon, mode);
@@ -344,6 +347,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
u8 clk_delay;
u32 val = 0;
+ WARN_ON(!tcon->quirks->has_channel_0);
+
tcon->dclk_min_div = 6;
tcon->dclk_max_div = 127;
sun4i_tcon0_mode_set_common(tcon, mode);
@@ -570,10 +575,12 @@ static int sun4i_tcon_init_clocks(struct device *dev,
}
clk_prepare_enable(tcon->clk);
- tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
- if (IS_ERR(tcon->sclk0)) {
- dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
- return PTR_ERR(tcon->sclk0);
+ if (tcon->quirks->has_channel_0) {
+ tcon->sclk0 = devm_clk_get(dev, "tcon-ch0");
+ if (IS_ERR(tcon->sclk0)) {
+ dev_err(dev, "Couldn't get the TCON channel 0 clock\n");
+ return PTR_ERR(tcon->sclk0);
+ }
}
if (tcon->quirks->has_channel_1) {
@@ -930,10 +937,12 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
goto err_free_clocks;
}
- ret = sun4i_dclk_create(dev, tcon);
- if (ret) {
- dev_err(dev, "Couldn't create our TCON dot clock\n");
- goto err_free_clocks;
+ if (tcon->quirks->has_channel_0) {
+ ret = sun4i_dclk_create(dev, tcon);
+ if (ret) {
+ dev_err(dev, "Couldn't create our TCON dot clock\n");
+ goto err_free_clocks;
+ }
}
ret = sun4i_tcon_init_irq(dev, tcon);
@@ -991,7 +1000,8 @@ static int sun4i_tcon_bind(struct device *dev, struct device *master,
return 0;
err_free_dotclock:
- sun4i_dclk_free(tcon);
+ if (tcon->quirks->has_channel_0)
+ sun4i_dclk_free(tcon);
err_free_clocks:
sun4i_tcon_free_clocks(tcon);
err_assert_reset:
@@ -1005,7 +1015,8 @@ static void sun4i_tcon_unbind(struct device *dev, struct device *master,
struct sun4i_tcon *tcon = dev_get_drvdata(dev);
list_del(&tcon->list);
- sun4i_dclk_free(tcon);
+ if (tcon->quirks->has_channel_0)
+ sun4i_dclk_free(tcon);
sun4i_tcon_free_clocks(tcon);
}
@@ -1102,16 +1113,19 @@ static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon,
}
static const struct sun4i_tcon_quirks sun4i_a10_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
.set_mux = sun4i_a10_tcon_set_mux,
};
static const struct sun4i_tcon_quirks sun5i_a13_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
.set_mux = sun5i_a13_tcon_set_mux,
};
static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
.has_lvds_alt = true,
.needs_de_be_mux = true,
@@ -1119,26 +1133,33 @@ static const struct sun4i_tcon_quirks sun6i_a31_quirks = {
};
static const struct sun4i_tcon_quirks sun6i_a31s_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
.needs_de_be_mux = true,
};
static const struct sun4i_tcon_quirks sun7i_a20_quirks = {
+ .has_channel_0 = true,
.has_channel_1 = true,
/* Same display pipeline structure as A10 */
.set_mux = sun4i_a10_tcon_set_mux,
};
static const struct sun4i_tcon_quirks sun8i_a33_quirks = {
+ .has_channel_0 = true,
.has_lvds_alt = true,
};
static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = {
- /* nothing is supported */
+ .has_channel_0 = true,
+};
+
+static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = {
+ .has_channel_1 = true,
};
static const struct sun4i_tcon_quirks sun8i_v3s_quirks = {
- /* nothing is supported */
+ .has_channel_0 = true,
};
/* sun4i_drv uses this list to check if a device node is a TCON */
@@ -1150,6 +1171,7 @@ const struct of_device_id sun4i_tcon_of_table[] = {
{ .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
{ .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
{ .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
+ { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
{ .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
{ }
};
diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
index b761c7b823c5..78d55e7cd2b3 100644
--- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
+++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
@@ -172,6 +172,7 @@
struct sun4i_tcon;
struct sun4i_tcon_quirks {
+ bool has_channel_0; /* a83t does not have channel 0 on second TCON */
bool has_channel_1; /* a33 does not have channel 1 */
bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */
bool needs_de_be_mux; /* sun6i needs mux to select backend */
--
2.15.1
^ permalink raw reply related
* [PATCH 08/11] drm/sun4i: Add support for A83T second DE2 mixer
From: Jernej Skrabec @ 2017-12-30 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230210203.24115-1-jernej.skrabec@siol.net>
It supports 1 VI and 1 UI plane and HW scaling on both planes.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/sun8i_mixer.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 2cbb2de6d39c..9b0256d31a61 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -485,6 +485,13 @@ static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = {
.vi_num = 1,
};
+static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = {
+ .ccsc = 1,
+ .scaler_mask = 0x3,
+ .ui_num = 1,
+ .vi_num = 1,
+};
+
static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.vi_num = 2,
.ui_num = 1,
@@ -498,6 +505,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
.data = &sun8i_a83t_mixer0_cfg,
},
+ {
+ .compatible = "allwinner,sun8i-a83t-de2-mixer-1",
+ .data = &sun8i_a83t_mixer1_cfg,
+ },
{
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,
--
2.15.1
^ permalink raw reply related
* [PATCH 09/11] drm/sun4i: Implement A83T HDMI driver
From: Jernej Skrabec @ 2017-12-30 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230210203.24115-1-jernej.skrabec@siol.net>
A83T has DW HDMI IP block with a custom PHY similar to Synopsys gen2
HDMI PHY.
Only video output was tested, while HW also supports audio and CEC.
Support for them will be added later.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
drivers/gpu/drm/sun4i/Kconfig | 9 +
drivers/gpu/drm/sun4i/Makefile | 1 +
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 367 ++++++++++++++++++++++++++++++++++
3 files changed, 377 insertions(+)
create mode 100644 drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
diff --git a/drivers/gpu/drm/sun4i/Kconfig b/drivers/gpu/drm/sun4i/Kconfig
index 882d85db9053..7327da3bc94f 100644
--- a/drivers/gpu/drm/sun4i/Kconfig
+++ b/drivers/gpu/drm/sun4i/Kconfig
@@ -40,6 +40,15 @@ config DRM_SUN4I_BACKEND
do some alpha blending and feed graphics to TCON. If M is
selected the module will be called sun4i-backend.
+config DRM_SUN8I_DW_HDMI
+ tristate "Support for Allwinner version of DesignWare HDMI"
+ depends on DRM_SUN4I
+ select DRM_DW_HDMI
+ help
+ Choose this option if you have an Allwinner SoC with the
+ DesignWare HDMI controller with custom HDMI PHY. If M is
+ selected the module will be called sun8i_dw_hdmi.
+
config DRM_SUN8I_MIXER
tristate "Support for Allwinner Display Engine 2.0 Mixer"
default MACH_SUN8I
diff --git a/drivers/gpu/drm/sun4i/Makefile b/drivers/gpu/drm/sun4i/Makefile
index 2b37a6abbb1d..d633d2b816fd 100644
--- a/drivers/gpu/drm/sun4i/Makefile
+++ b/drivers/gpu/drm/sun4i/Makefile
@@ -26,4 +26,5 @@ obj-$(CONFIG_DRM_SUN4I) += sun6i_drc.o
obj-$(CONFIG_DRM_SUN4I_BACKEND) += sun4i-backend.o
obj-$(CONFIG_DRM_SUN4I_HDMI) += sun4i-drm-hdmi.o
+obj-$(CONFIG_DRM_SUN8I_DW_HDMI) += sun8i_dw_hdmi.o
obj-$(CONFIG_DRM_SUN8I_MIXER) += sun8i-mixer.o
diff --git a/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
new file mode 100644
index 000000000000..462bb81f11ed
--- /dev/null
+++ b/drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c
@@ -0,0 +1,367 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Jernej Skrabec <jernej.skrabec@siol.net>
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+
+#include <drm/drm_of.h>
+#include <drm/drmP.h>
+#include <drm/drm_crtc_helper.h>
+#include <drm/drm_edid.h>
+#include <drm/bridge/dw_hdmi.h>
+
+#define SUN8I_HDMI_PHY_REG_UNK1 0x0000
+#define SUN8I_HDMI_PHY_REG_POL 0x0001
+#define SUN8I_HDMI_PHY_REG_UNK2 0x0002
+#define SUN8I_HDMI_PHY_REG_UNK3 0x0003
+#define SUN8I_HDMI_PHY_REG_UNK4 0x0007
+
+#define SUN8I_HDMI_PHY_REG_READ_EN 0x0010
+#define SUN8I_HDMI_PHY_REG_READ_EN_MAGIC 0x54524545
+
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE 0x0014
+#define SUN8I_HDMI_PHY_REG_UNSCRAMBLE_MAGIC 0x42494E47
+
+#define to_sun8i_dw_hdmi(x) container_of(x, struct sun8i_dw_hdmi, x)
+
+struct sun8i_dw_hdmi {
+ struct clk *clk_ahb;
+ struct clk *clk_sfr;
+ struct clk *clk_tmds;
+ struct device *dev;
+ struct drm_encoder encoder;
+ void __iomem *phy_base;
+ struct dw_hdmi_plat_data plat_data;
+ struct reset_control *rst_ctrl;
+ struct reset_control *rst_phy;
+};
+
+static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adj_mode)
+{
+ struct sun8i_dw_hdmi *hdmi = to_sun8i_dw_hdmi(encoder);
+
+ clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
+}
+
+static const struct drm_encoder_helper_funcs
+sun8i_dw_hdmi_encoder_helper_funcs = {
+ .mode_set = sun8i_dw_hdmi_encoder_mode_set,
+};
+
+static void sun8i_dw_hdmi_init(struct sun8i_dw_hdmi *hdmi)
+{
+ /* enable read access to HDMI controller */
+ writel(SUN8I_HDMI_PHY_REG_READ_EN_MAGIC,
+ hdmi->phy_base + SUN8I_HDMI_PHY_REG_READ_EN);
+
+ /*
+ * HDMI PHY settings are taken as-is from Allwinner BSP code.
+ * There is no documentation.
+ */
+ writeb(0x01, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK1);
+ writeb(0x00, hdmi->phy_base + SUN8I_HDMI_PHY_REG_POL);
+ writeb(0x69, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK2);
+ writeb(0x00, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK3);
+
+ /* unscramble register offsets */
+ writel(SUN8I_HDMI_PHY_REG_UNSCRAMBLE_MAGIC,
+ hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNSCRAMBLE);
+}
+
+static const struct drm_encoder_funcs sun8i_dw_hdmi_encoder_funcs = {
+ .destroy = drm_encoder_cleanup,
+};
+
+static int sun8i_dw_hdmi_phy_init(struct dw_hdmi *dw_hdmi, void *data,
+ struct drm_display_mode *mode)
+{
+ struct sun8i_dw_hdmi *hdmi = (struct sun8i_dw_hdmi *)data;
+ u8 val = 0;
+
+ if ((mode->flags & DRM_MODE_FLAG_NHSYNC) &&
+ (mode->flags & DRM_MODE_FLAG_NHSYNC)) {
+ val = 0x03;
+ }
+
+ writeb(0xa0, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK4);
+
+ writeb(val, hdmi->phy_base + SUN8I_HDMI_PHY_REG_POL);
+
+ dw_hdmi_phy_gen2_reset(dw_hdmi, 1);
+
+ dw_hdmi_phy_gen2_txpwron(dw_hdmi, 0);
+ dw_hdmi_phy_gen2_pddq(dw_hdmi, 1);
+
+ dw_hdmi_phy_gen2_reset(dw_hdmi, 0);
+ dw_hdmi_phy_gen2_pddq(dw_hdmi, 0);
+
+ dw_hdmi_phy_set_slave_addr(dw_hdmi);
+
+ if (mode->crtc_clock <= 27000) {
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x01e0, 0x06);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x15);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x08da, 0x10);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0007, 0x19);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0318, 0x0e);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x8009, 0x09);
+ } else if (mode->crtc_clock <= 74250) {
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0540, 0x06);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0005, 0x15);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x10);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0007, 0x19);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x02b5, 0x0e);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x8009, 0x09);
+ } else if (mode->crtc_clock <= 148500) {
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x04a0, 0x06);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x000a, 0x15);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x10);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0002, 0x19);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0021, 0x0e);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x8029, 0x09);
+ } else {
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x06);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x000f, 0x15);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x10);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0002, 0x19);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x0e);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x802b, 0x09);
+ }
+
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x1e);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x13);
+ dw_hdmi_phy_i2c_write(dw_hdmi, 0x0000, 0x17);
+
+ dw_hdmi_phy_gen2_txpwron(dw_hdmi, 1);
+
+ return 0;
+};
+
+static void sun8i_dw_hdmi_phy_disable(struct dw_hdmi *dw_hdmi, void *data)
+{
+ struct sun8i_dw_hdmi *hdmi = (struct sun8i_dw_hdmi *)data;
+
+ dw_hdmi_phy_gen2_txpwron(dw_hdmi, 0);
+ dw_hdmi_phy_gen2_pddq(dw_hdmi, 1);
+
+ writeb(0x20, hdmi->phy_base + SUN8I_HDMI_PHY_REG_UNK4);
+}
+
+static const struct dw_hdmi_phy_ops sun8i_dw_hdmi_phy_ops = {
+ .init = &sun8i_dw_hdmi_phy_init,
+ .disable = &sun8i_dw_hdmi_phy_disable,
+ .read_hpd = &dw_hdmi_phy_read_hpd,
+ .update_hpd = &dw_hdmi_phy_update_hpd,
+ .setup_hpd = &dw_hdmi_phy_setup_hpd,
+};
+
+static enum drm_mode_status
+sun8i_dw_hdmi_mode_valid(struct drm_connector *connector,
+ const struct drm_display_mode *mode)
+{
+ if (mode->clock > 297000)
+ return MODE_BAD;
+
+ return MODE_OK;
+}
+
+static void sun8i_dw_hdmi_deinit(const struct dw_hdmi_plat_data *plat_data)
+{
+ struct sun8i_dw_hdmi *hdmi = to_sun8i_dw_hdmi(plat_data);
+
+ clk_disable_unprepare(hdmi->clk_tmds);
+ clk_disable_unprepare(hdmi->clk_sfr);
+ clk_disable_unprepare(hdmi->clk_ahb);
+
+ reset_control_assert(hdmi->rst_phy);
+ reset_control_assert(hdmi->rst_ctrl);
+}
+
+static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
+ void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct dw_hdmi_plat_data *plat_data;
+ struct drm_device *drm = data;
+ struct drm_encoder *encoder;
+ struct sun8i_dw_hdmi *hdmi;
+ struct resource *res;
+ int ret;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
+ if (!hdmi)
+ return -ENOMEM;
+
+ plat_data = &hdmi->plat_data;
+ hdmi->dev = &pdev->dev;
+ encoder = &hdmi->encoder;
+
+ encoder->possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
+ /*
+ * If we failed to find the CRTC(s) which this encoder is
+ * supposed to be connected to, it's because the CRTC has
+ * not been registered yet. Defer probing, and hope that
+ * the required CRTC is added later.
+ */
+ if (encoder->possible_crtcs == 0)
+ return -EPROBE_DEFER;
+
+ /* resource 0 is the memory region for the core controller */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ hdmi->phy_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(hdmi->phy_base))
+ return PTR_ERR(hdmi->phy_base);
+
+ hdmi->clk_ahb = devm_clk_get(dev, "iahb");
+ if (IS_ERR(hdmi->clk_ahb)) {
+ dev_err(dev, "Could not get iahb clock\n");
+ return PTR_ERR(hdmi->clk_ahb);
+ }
+
+ hdmi->clk_sfr = devm_clk_get(dev, "isfr");
+ if (IS_ERR(hdmi->clk_sfr)) {
+ dev_err(dev, "Could not get isfr clock\n");
+ return PTR_ERR(hdmi->clk_sfr);
+ }
+
+ hdmi->clk_tmds = devm_clk_get(dev, "tmds");
+ if (IS_ERR(hdmi->clk_tmds)) {
+ dev_err(dev, "Could not get tmds clock\n");
+ return PTR_ERR(hdmi->clk_tmds);
+ }
+
+ hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
+ if (IS_ERR(hdmi->rst_ctrl)) {
+ dev_err(dev, "Could not get ctrl reset control\n");
+ return PTR_ERR(hdmi->rst_ctrl);
+ }
+
+ hdmi->rst_phy = devm_reset_control_get(dev, "phy");
+ if (IS_ERR(hdmi->rst_phy)) {
+ dev_err(dev, "Could not get phy reset control\n");
+ return PTR_ERR(hdmi->rst_phy);
+ }
+
+ ret = reset_control_deassert(hdmi->rst_ctrl);
+ if (ret) {
+ dev_err(dev, "Could not deassert ctrl reset control\n");
+ return ret;
+ }
+
+ ret = reset_control_deassert(hdmi->rst_phy);
+ if (ret) {
+ dev_err(dev, "Could not deassert phy reset control\n");
+ goto err_assert_ctrl_reset;
+ }
+
+ ret = clk_prepare_enable(hdmi->clk_ahb);
+ if (ret) {
+ dev_err(dev, "Cannot enable ahb clock: %d\n", ret);
+ goto err_assert_phy_reset;
+ }
+
+ ret = clk_prepare_enable(hdmi->clk_sfr);
+ if (ret) {
+ dev_err(dev, "Cannot enable isfr clock: %d\n", ret);
+ goto err_ahb_clk;
+ }
+
+ /* A83T defaults to 1188 MHz, which is a bit high */
+ clk_set_rate(hdmi->clk_tmds, 297000000);
+
+ ret = clk_prepare_enable(hdmi->clk_tmds);
+ if (ret) {
+ dev_err(dev, "Cannot enable tmds clock: %d\n", ret);
+ goto err_sfr_clk;
+ }
+
+ drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
+ drm_encoder_init(drm, encoder, &sun8i_dw_hdmi_encoder_funcs,
+ DRM_MODE_ENCODER_TMDS, NULL);
+
+ sun8i_dw_hdmi_init(hdmi);
+
+ plat_data->deinit = &sun8i_dw_hdmi_deinit;
+ plat_data->mode_valid = &sun8i_dw_hdmi_mode_valid;
+ plat_data->phy_ops = &sun8i_dw_hdmi_phy_ops;
+ plat_data->phy_name = "sun8i_dw_hdmi_phy";
+ plat_data->phy_data = hdmi;
+
+ ret = dw_hdmi_bind(pdev, encoder, plat_data);
+
+ /*
+ * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
+ * which would have called the encoder cleanup. Do it manually.
+ */
+ if (ret)
+ goto cleanup_encoder;
+
+ return 0;
+
+cleanup_encoder:
+ drm_encoder_cleanup(encoder);
+ clk_disable_unprepare(hdmi->clk_tmds);
+err_sfr_clk:
+ clk_disable_unprepare(hdmi->clk_sfr);
+err_ahb_clk:
+ clk_disable_unprepare(hdmi->clk_ahb);
+err_assert_phy_reset:
+ reset_control_assert(hdmi->rst_phy);
+err_assert_ctrl_reset:
+ reset_control_assert(hdmi->rst_ctrl);
+
+ return ret;
+}
+
+static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
+ void *data)
+{
+ return dw_hdmi_unbind(dev);
+}
+
+static const struct component_ops sun8i_dw_hdmi_ops = {
+ .bind = sun8i_dw_hdmi_bind,
+ .unbind = sun8i_dw_hdmi_unbind,
+};
+
+static int sun8i_dw_hdmi_probe(struct platform_device *pdev)
+{
+ return component_add(&pdev->dev, &sun8i_dw_hdmi_ops);
+}
+
+static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
+{
+ component_del(&pdev->dev, &sun8i_dw_hdmi_ops);
+
+ return 0;
+}
+
+static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
+ { .compatible = "allwinner,sun8i-a83t-dw-hdmi" },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
+
+struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
+ .probe = sun8i_dw_hdmi_probe,
+ .remove = sun8i_dw_hdmi_remove,
+ .driver = {
+ .name = "sun8i-dw-hdmi",
+ .of_match_table = sun8i_dw_hdmi_dt_ids,
+ },
+};
+module_platform_driver(sun8i_dw_hdmi_pltfm_driver);
+
+MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
+MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
+MODULE_LICENSE("GPL");
--
2.15.1
^ permalink raw reply related
* [PATCH 10/11] ARM: dts: sun8i: a83t: Add HDMI display pipeline
From: Jernej Skrabec @ 2017-12-30 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230210203.24115-1-jernej.skrabec@siol.net>
This commit adds all bits necessary for HDMI on A83T - mixer1, tcon1,
hdmi and hdmi pinctrl entries.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 108 +++++++++++++++++++++++++++++++++++++-
1 file changed, 107 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi
index 7f4955a5fab7..601d1eb5460e 100644
--- a/arch/arm/boot/dts/sun8i-a83t.dtsi
+++ b/arch/arm/boot/dts/sun8i-a83t.dtsi
@@ -155,7 +155,7 @@
de: display-engine {
compatible = "allwinner,sun8i-a83t-display-engine";
- allwinner,pipelines = <&mixer0>;
+ allwinner,pipelines = <&mixer0>, <&mixer1>;
status = "disabled";
};
@@ -208,6 +208,32 @@
};
};
+ mixer1: mixer at 1200000 {
+ compatible = "allwinner,sun8i-a83t-de2-mixer-1";
+ reg = <0x01200000 0x100000>;
+ clocks = <&display_clocks CLK_BUS_MIXER1>,
+ <&display_clocks CLK_MIXER1>;
+ clock-names = "bus",
+ "mod";
+ resets = <&display_clocks RST_WB>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mixer1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ mixer1_out_tcon1: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon1_in_mixer1>;
+ };
+ };
+ };
+ };
+
syscon: syscon at 1c00000 {
compatible = "allwinner,sun8i-a83t-system-controller",
"syscon";
@@ -256,6 +282,43 @@
};
};
+ tcon1: lcd-controller at 1c0d000 {
+ compatible = "allwinner,sun8i-a83t-tcon-tv";
+ reg = <0x01c0d000 0x1000>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
+ clock-names = "ahb", "tcon-ch1";
+ resets = <&ccu RST_BUS_TCON1>;
+ reset-names = "lcd";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ tcon1_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ tcon1_in_mixer1: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&mixer1_out_tcon1>;
+ };
+ };
+
+ tcon1_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ tcon1_out_hdmi: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&hdmi_in_tcon1>;
+ };
+ };
+ };
+ };
+
mmc0: mmc at 1c0f000 {
compatible = "allwinner,sun8i-a83t-mmc",
"allwinner,sun7i-a20-mmc";
@@ -427,6 +490,11 @@
drive-strength = <40>;
};
+ hdmi_pins: hdmi-pins {
+ pins = "PH6", "PH7", "PH8";
+ function = "hdmi";
+ };
+
i2c0_pins: i2c0-pins {
pins = "PH0", "PH1";
function = "i2c0";
@@ -685,6 +753,44 @@
interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
};
+ hdmi: hdmi at 1ee0000 {
+ compatible = "allwinner,sun8i-a83t-dw-hdmi";
+ reg = <0x01ee0000 0x10000>,
+ <0x01ef0000 0x10000>;
+ reg-io-width = <1>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
+ <&ccu CLK_HDMI>;
+ clock-names = "iahb", "isfr", "tmds";
+ resets = <&ccu RST_BUS_HDMI0>, <&ccu RST_BUS_HDMI1>;
+ reset-names = "phy", "ctrl";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pins>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ hdmi_in: port at 0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+
+ hdmi_in_tcon1: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&tcon1_out_hdmi>;
+ };
+ };
+
+ hdmi_out: port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ };
+ };
+ };
+
r_intc: interrupt-controller at 1f00c00 {
compatible = "allwinner,sun8i-a83t-r-intc",
"allwinner,sun6i-a31-r-intc";
--
2.15.1
^ permalink raw reply related
* [PATCH 11/11] ARM: dts: sun8i: a83t: Enable HDMI on BananaPi M3
From: Jernej Skrabec @ 2017-12-30 21:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230210203.24115-1-jernej.skrabec@siol.net>
BananaPi M3 includes HDMI connector, so add support for it.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 29 ++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
index 6550bf0e594b..2002d249e14c 100644
--- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
+++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
@@ -60,6 +60,17 @@
stdout-path = "serial0:115200n8";
};
+ connector {
+ compatible = "hdmi-connector";
+ type = "a";
+
+ port {
+ hdmi_con_in: endpoint {
+ remote-endpoint = <&hdmi_out_con>;
+ };
+ };
+ };
+
reg_usb1_vbus: reg-usb1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb1-vbus";
@@ -82,6 +93,10 @@
};
};
+&de {
+ status = "okay";
+};
+
&ehci0 {
/* Terminus Tech FE 1.1s 4-port USB 2.0 hub here */
status = "okay";
@@ -100,6 +115,16 @@
status = "okay";
};
+&hdmi {
+ status = "okay";
+};
+
+&hdmi_out {
+ hdmi_out_con: endpoint {
+ remote-endpoint = <&hdmi_con_in>;
+ };
+};
+
&mdio {
rgmii_phy: ethernet-phy at 1 {
compatible = "ethernet-phy-ieee802.3-c22";
@@ -306,6 +331,10 @@
regulator-name = "vcc-ephy";
};
+&tcon1 {
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pb_pins>;
--
2.15.1
^ permalink raw reply related
* [PATCH v2] i2c/ARM: davinci: Deep refactoring of I2C recovery
From: Wolfram Sang @ 2017-12-30 23:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220121749.12064-1-linus.walleij@linaro.org>
On Wed, Dec 20, 2017 at 01:17:49PM +0100, Linus Walleij wrote:
> Alter the DaVinci GPIO recovery fetch to use descriptors
> all the way down into the board files.
>
> Cc: arm at kernel.org
> Cc: Kevin Hilman <khilman@kernel.org>
> Cc: Keerthy <j-keerthy@ti.com>
> Cc: Sekhar Nori <nsekhar@ti.com>
> Acked-by: Sekhar Nori <nsekhar@ti.com>
> Tested-by: Sekhar Nori <nsekhar@ti.com>
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Applied to for-next, thanks!
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^ permalink raw reply
* [PATCH v2] PCI: imx6: Add PHY reference clock source support
From: Ilya Ledvich @ 2017-12-31 8:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <AM5PR0402MB28505BE42AB7774EC90927E18C040@AM5PR0402MB2850.eurprd04.prod.outlook.com>
i.MX7D variant of the IP can use either Crystal Oscillator input
or internal clock input as a Reference Clock input for PCIe PHY.
Add support for an optional property 'pcie-phy-refclk-internal'.
If present then an internal clock input is used as PCIe PHY
reference clock source. By default an external oscillator input
is still used.
Verified on Compulab SBC-iMX7 Single Board Computer.
Signed-off-by: Ilya Ledvich <ilya@compulab.co.il>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 5 +++++
drivers/pci/dwc/pci-imx6.c | 8 +++++++-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
index 7b1e48b..581bc09 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt
@@ -50,6 +50,11 @@ Additional required properties for imx7d-pcie:
- "pciephy"
- "apps"
+Additional optional properties for imx7d-pcie:
+- pcie-phy-refclk-internal: If present then an internal PLL input is used as
+ PCIe PHY reference clock source. By default an external oscillator input
+ is used.
+
Example:
pcie at 0x01000000 {
diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
index b734835..a616192 100644
--- a/drivers/pci/dwc/pci-imx6.c
+++ b/drivers/pci/dwc/pci-imx6.c
@@ -61,6 +61,7 @@ struct imx6_pcie {
u32 tx_swing_low;
int link_gen;
struct regulator *vpcie;
+ bool pciephy_refclk_sel;
};
/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
@@ -474,7 +475,9 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
switch (imx6_pcie->variant) {
case IMX7D:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
- IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
+ IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
+ imx6_pcie->pciephy_refclk_sel ?
+ IMX7D_GPR12_PCIE_PHY_REFCLK_SEL : 0);
break;
case IMX6SX:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -840,6 +843,9 @@ static int imx6_pcie_probe(struct platform_device *pdev)
imx6_pcie->vpcie = NULL;
}
+ imx6_pcie->pciephy_refclk_sel =
+ of_property_read_bool(node, "pcie-phy-refclk-internal");
+
platform_set_drvdata(pdev, imx6_pcie);
ret = imx6_add_pcie_port(imx6_pcie, pdev);
--
1.9.1
^ permalink raw reply related
* [bpf-next V3 PATCH 09/14] thunderx: setup xdp_rxq_info
From: Jesper Dangaard Brouer @ 2017-12-31 11:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <151471801977.30703.3258796879718706203.stgit@firesoul>
This driver uses a bool scheme for "enable"/"disable" when setting up
different resources. Thus, the hook points for xdp_rxq_info is done
in the same function call nicvf_rcv_queue_config(). This is activated
through enable/disable via nicvf_config_data_transfer(), which is tied
into nicvf_stop()/nicvf_open().
Extending driver packet handler call-path nicvf_rcv_pkt_handler() with
a pointer to the given struct rcv_queue, in-order to access the
xdp_rxq_info data area (in nicvf_xdp_rx()).
V2: Driver have no proper error path for failed XDP RX-queue info reg,
as nicvf_rcv_queue_config is a void function.
Cc: linux-arm-kernel at lists.infradead.org
Cc: Sunil Goutham <sgoutham@cavium.com>
Cc: Robert Richter <rric@kernel.org>
Signed-off-by: Jesper Dangaard Brouer <brouer@redhat.com>
---
drivers/net/ethernet/cavium/thunder/nicvf_main.c | 11 +++++++----
drivers/net/ethernet/cavium/thunder/nicvf_queues.c | 4 ++++
drivers/net/ethernet/cavium/thunder/nicvf_queues.h | 2 ++
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_main.c b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
index 52b3a6044f85..21618d0d694f 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_main.c
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_main.c
@@ -521,7 +521,7 @@ static void nicvf_unmap_page(struct nicvf *nic, struct page *page, u64 dma_addr)
static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
struct cqe_rx_t *cqe_rx, struct snd_queue *sq,
- struct sk_buff **skb)
+ struct rcv_queue *rq, struct sk_buff **skb)
{
struct xdp_buff xdp;
struct page *page;
@@ -545,6 +545,7 @@ static inline bool nicvf_xdp_rx(struct nicvf *nic, struct bpf_prog *prog,
xdp.data = (void *)cpu_addr;
xdp_set_data_meta_invalid(&xdp);
xdp.data_end = xdp.data + len;
+ xdp.rxq = &rq->xdp_rxq;
orig_data = xdp.data;
rcu_read_lock();
@@ -698,7 +699,8 @@ static inline void nicvf_set_rxhash(struct net_device *netdev,
static void nicvf_rcv_pkt_handler(struct net_device *netdev,
struct napi_struct *napi,
- struct cqe_rx_t *cqe_rx, struct snd_queue *sq)
+ struct cqe_rx_t *cqe_rx,
+ struct snd_queue *sq, struct rcv_queue *rq)
{
struct sk_buff *skb = NULL;
struct nicvf *nic = netdev_priv(netdev);
@@ -724,7 +726,7 @@ static void nicvf_rcv_pkt_handler(struct net_device *netdev,
/* For XDP, ignore pkts spanning multiple pages */
if (nic->xdp_prog && (cqe_rx->rb_cnt == 1)) {
/* Packet consumed by XDP */
- if (nicvf_xdp_rx(snic, nic->xdp_prog, cqe_rx, sq, &skb))
+ if (nicvf_xdp_rx(snic, nic->xdp_prog, cqe_rx, sq, rq, &skb))
return;
} else {
skb = nicvf_get_rcv_skb(snic, cqe_rx,
@@ -781,6 +783,7 @@ static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
struct cqe_rx_t *cq_desc;
struct netdev_queue *txq;
struct snd_queue *sq = &qs->sq[cq_idx];
+ struct rcv_queue *rq = &qs->rq[cq_idx];
unsigned int tx_pkts = 0, tx_bytes = 0, txq_idx;
spin_lock_bh(&cq->lock);
@@ -811,7 +814,7 @@ static int nicvf_cq_intr_handler(struct net_device *netdev, u8 cq_idx,
switch (cq_desc->cqe_type) {
case CQE_TYPE_RX:
- nicvf_rcv_pkt_handler(netdev, napi, cq_desc, sq);
+ nicvf_rcv_pkt_handler(netdev, napi, cq_desc, sq, rq);
work_done++;
break;
case CQE_TYPE_SEND:
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
index f38ea349aa00..14e62c6ac342 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.c
@@ -760,6 +760,7 @@ static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs,
if (!rq->enable) {
nicvf_reclaim_rcv_queue(nic, qs, qidx);
+ xdp_rxq_info_unreg(&rq->xdp_rxq);
return;
}
@@ -772,6 +773,9 @@ static void nicvf_rcv_queue_config(struct nicvf *nic, struct queue_set *qs,
/* all writes of RBDR data to be loaded into L2 Cache as well*/
rq->caching = 1;
+ /* Driver have no proper error path for failed XDP RX-queue info reg */
+ WARN_ON(xdp_rxq_info_reg(&rq->xdp_rxq, nic->netdev, qidx) < 0);
+
/* Send a mailbox msg to PF to config RQ */
mbx.rq.msg = NIC_MBOX_MSG_RQ_CFG;
mbx.rq.qs_num = qs->vnic_id;
diff --git a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
index 178ab6e8e3c5..7d1e4e2aaad0 100644
--- a/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
+++ b/drivers/net/ethernet/cavium/thunder/nicvf_queues.h
@@ -12,6 +12,7 @@
#include <linux/netdevice.h>
#include <linux/iommu.h>
#include <linux/bpf.h>
+#include <net/xdp.h>
#include "q_struct.h"
#define MAX_QUEUE_SET 128
@@ -255,6 +256,7 @@ struct rcv_queue {
u8 start_qs_rbdr_idx; /* RBDR idx in the above QS */
u8 caching;
struct rx_tx_queue_stats stats;
+ struct xdp_rxq_info xdp_rxq;
} ____cacheline_aligned_in_smp;
struct cmp_queue {
^ permalink raw reply related
* [net-next: PATCH v2 0/5] Armada 7k/8k PP2 ACPI support
From: Marcin Wojtas @ 2017-12-31 11:58 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
This a second version of a patchset, which introduces ACPI support
in mvpp2 driver. Comparing to the initial one, all patches
touching generic ACPI MDIO bus / PHY handling were removed
and after some modifications will be resend separately. They
may require a longer discussion in terms of phylink support
and ACPI specification extensions.
This way mvpp2 driver is able to operate using the link interrupt
capability (a.k.a. in-band management) on all ports, 1000BaseT RGMII
included. Driver operation was tested on top of the net-next branch
with both DT and ACPI on MacchiatoBin and Armada 7040 DB boards.
mvpp2 driver can work with the ACPI representation, as exposed
on a public branch:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/commits/marvell-armada-wip
It was compiled together with the most recent Tianocore EDK2 revision.
Please refer to the firmware build instruction on MacchiatoBin board:
http://wiki.macchiatobin.net/tiki-index.php?page=Build+from+source+-+UEFI+EDK+II
ACPI representation of PP2 controllers (withouth PHY support) can
be viewed in the github:
* MacchiatoBin:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/blob/marvell-armada-wip/Platforms/Marvell/Armada/AcpiTables/Armada80x0McBin/Dsdt.asl#L201
* Armada 7040 DB:
https://github.com/MarvellEmbeddedProcessors/edk2-open-platform/blob/marvell-armada-wip/Platforms/Marvell/Armada/AcpiTables/Armada70x0/Dsdt.asl#L131
I will appreciate any comments or remarks.
Best regards,
Marcin
Changelog:
v1 -> v2:
* Remove MDIO patches
* Use PP2 ports only with link interrupts
* Release second region resources in mvpp2 driver (code moved from
mvmdio), as explained in details in 5/5 commit message.
Marcin Wojtas (5):
device property: Introduce fwnode_get_mac_address()
device property: Introduce fwnode_get_phy_mode()
net: mvpp2: simplify maintaining enabled ports' list
net: mvpp2: use device_*/fwnode_* APIs instead of of_*
net: mvpp2: enable ACPI support in the driver
drivers/base/property.c | 52 +++--
drivers/net/ethernet/marvell/mvpp2.c | 222 ++++++++++++--------
include/linux/property.h | 3 +
3 files changed, 180 insertions(+), 97 deletions(-)
--
2.7.4
^ permalink raw reply
* [net-next: PATCH v2 1/5] device property: Introduce fwnode_get_mac_address()
From: Marcin Wojtas @ 2017-12-31 11:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514721520-18964-1-git-send-email-mw@semihalf.com>
Until now there were two almost identical functions for
obtaining MAC address - of_get_mac_address() and, more generic,
device_get_mac_address(). However it is not uncommon,
that the network interface is represented as a child
of the actual controller, hence it is not associated
directly to any struct device, required by the latter
routine.
This commit allows for getting the MAC address for
children nodes in the ACPI world by introducing a new function -
fwnode_get_mac_address(). This commit also changes
device_get_mac_address() routine to be its wrapper, in order
to prevent unnecessary duplication.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
drivers/base/property.c | 28 ++++++++++++++------
include/linux/property.h | 2 ++
2 files changed, 22 insertions(+), 8 deletions(-)
diff --git a/drivers/base/property.c b/drivers/base/property.c
index 851b1b6..f261d1a 100644
--- a/drivers/base/property.c
+++ b/drivers/base/property.c
@@ -1153,11 +1153,11 @@ int device_get_phy_mode(struct device *dev)
}
EXPORT_SYMBOL_GPL(device_get_phy_mode);
-static void *device_get_mac_addr(struct device *dev,
+static void *fwnode_get_mac_addr(struct fwnode_handle *fwnode,
const char *name, char *addr,
int alen)
{
- int ret = device_property_read_u8_array(dev, name, addr, alen);
+ int ret = fwnode_property_read_u8_array(fwnode, name, addr, alen);
if (ret == 0 && alen == ETH_ALEN && is_valid_ether_addr(addr))
return addr;
@@ -1165,8 +1165,8 @@ static void *device_get_mac_addr(struct device *dev,
}
/**
- * device_get_mac_address - Get the MAC for a given device
- * @dev: Pointer to the device
+ * fwnode_get_mac_address - Get the MAC from the firmware node
+ * @fwnode: Pointer to the firmware node
* @addr: Address of buffer to store the MAC in
* @alen: Length of the buffer pointed to by addr, should be ETH_ALEN
*
@@ -1187,19 +1187,31 @@ static void *device_get_mac_addr(struct device *dev,
* In this case, the real MAC is in 'local-mac-address', and 'mac-address'
* exists but is all zeros.
*/
-void *device_get_mac_address(struct device *dev, char *addr, int alen)
+void *fwnode_get_mac_address(struct fwnode_handle *fwnode, char *addr, int alen)
{
char *res;
- res = device_get_mac_addr(dev, "mac-address", addr, alen);
+ res = fwnode_get_mac_addr(fwnode, "mac-address", addr, alen);
if (res)
return res;
- res = device_get_mac_addr(dev, "local-mac-address", addr, alen);
+ res = fwnode_get_mac_addr(fwnode, "local-mac-address", addr, alen);
if (res)
return res;
- return device_get_mac_addr(dev, "address", addr, alen);
+ return fwnode_get_mac_addr(fwnode, "address", addr, alen);
+}
+EXPORT_SYMBOL(fwnode_get_mac_address);
+
+/**
+ * device_get_mac_address - Get the MAC for a given device
+ * @dev: Pointer to the device
+ * @addr: Address of buffer to store the MAC in
+ * @alen: Length of the buffer pointed to by addr, should be ETH_ALEN
+ */
+void *device_get_mac_address(struct device *dev, char *addr, int alen)
+{
+ return fwnode_get_mac_address(dev_fwnode(dev), addr, alen);
}
EXPORT_SYMBOL(device_get_mac_address);
diff --git a/include/linux/property.h b/include/linux/property.h
index f6189a3..35620e0 100644
--- a/include/linux/property.h
+++ b/include/linux/property.h
@@ -279,6 +279,8 @@ int device_get_phy_mode(struct device *dev);
void *device_get_mac_address(struct device *dev, char *addr, int alen);
+void *fwnode_get_mac_address(struct fwnode_handle *fwnode,
+ char *addr, int alen);
struct fwnode_handle *fwnode_graph_get_next_endpoint(
const struct fwnode_handle *fwnode, struct fwnode_handle *prev);
struct fwnode_handle *
--
2.7.4
^ permalink raw reply related
* [net-next: PATCH v2 2/5] device property: Introduce fwnode_get_phy_mode()
From: Marcin Wojtas @ 2017-12-31 11:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514721520-18964-1-git-send-email-mw@semihalf.com>
Until now there were two almost identical functions for
obtaining network PHY mode - of_get_phy_mode() and,
more generic, device_get_phy_mode(). However it is not uncommon,
that the network interface is represented as a child
of the actual controller, hence it is not associated
directly to any struct device, required by the latter
routine.
This commit allows for getting the PHY mode for
children nodes in the ACPI world by introducing a new function -
fwnode_get_phy_mode(). This commit also changes
device_get_phy_mode() routine to be its wrapper, in order
to prevent unnecessary duplication.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
drivers/base/property.c | 24 ++++++++++++++++----
include/linux/property.h | 1 +
2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/drivers/base/property.c b/drivers/base/property.c
index f261d1a..7c4a53d 100644
--- a/drivers/base/property.c
+++ b/drivers/base/property.c
@@ -1126,21 +1126,21 @@ enum dev_dma_attr device_get_dma_attr(struct device *dev)
EXPORT_SYMBOL_GPL(device_get_dma_attr);
/**
- * device_get_phy_mode - Get phy mode for given device
- * @dev: Pointer to the given device
+ * fwnode_get_phy_mode - Get phy mode for given firmware node
+ * @fwnode: Pointer to the given node
*
* The function gets phy interface string from property 'phy-mode' or
* 'phy-connection-type', and return its index in phy_modes table, or errno in
* error case.
*/
-int device_get_phy_mode(struct device *dev)
+int fwnode_get_phy_mode(struct fwnode_handle *fwnode)
{
const char *pm;
int err, i;
- err = device_property_read_string(dev, "phy-mode", &pm);
+ err = fwnode_property_read_string(fwnode, "phy-mode", &pm);
if (err < 0)
- err = device_property_read_string(dev,
+ err = fwnode_property_read_string(fwnode,
"phy-connection-type", &pm);
if (err < 0)
return err;
@@ -1151,6 +1151,20 @@ int device_get_phy_mode(struct device *dev)
return -ENODEV;
}
+EXPORT_SYMBOL_GPL(fwnode_get_phy_mode);
+
+/**
+ * device_get_phy_mode - Get phy mode for given device
+ * @dev: Pointer to the given device
+ *
+ * The function gets phy interface string from property 'phy-mode' or
+ * 'phy-connection-type', and return its index in phy_modes table, or errno in
+ * error case.
+ */
+int device_get_phy_mode(struct device *dev)
+{
+ return fwnode_get_phy_mode(dev_fwnode(dev));
+}
EXPORT_SYMBOL_GPL(device_get_phy_mode);
static void *fwnode_get_mac_addr(struct fwnode_handle *fwnode,
diff --git a/include/linux/property.h b/include/linux/property.h
index 35620e0..9b13332 100644
--- a/include/linux/property.h
+++ b/include/linux/property.h
@@ -279,6 +279,7 @@ int device_get_phy_mode(struct device *dev);
void *device_get_mac_address(struct device *dev, char *addr, int alen);
+int fwnode_get_phy_mode(struct fwnode_handle *fwnode);
void *fwnode_get_mac_address(struct fwnode_handle *fwnode,
char *addr, int alen);
struct fwnode_handle *fwnode_graph_get_next_endpoint(
--
2.7.4
^ permalink raw reply related
* [net-next: PATCH v2 3/5] net: mvpp2: simplify maintaining enabled ports' list
From: Marcin Wojtas @ 2017-12-31 11:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514721520-18964-1-git-send-email-mw@semihalf.com>
'port_count' field of the mvpp2 structure holds an overall amount
of available ports, based on DT nodes status. In order to be prepared
to support other HW description, obtain the value by incrementing it
upon each successful port initialization. This allowed for simplifying
port indexing in the controller's private array, whose size is now not
dynamically allocated, but fixed to MVPP2_MAX_PORTS.
This patch simplifies creating and filling list of enabled ports and
is a part of the preparation for adding ACPI support in the mvpp2 driver.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 32 +++++++-------------
1 file changed, 11 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index a197607..7f42d90 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -865,7 +865,7 @@ struct mvpp2 {
/* List of pointers to port structures */
int port_count;
- struct mvpp2_port **port_list;
+ struct mvpp2_port *port_list[MVPP2_MAX_PORTS];
/* Aggregated TXQs */
struct mvpp2_tx_queue *aggr_txqs;
@@ -7741,7 +7741,7 @@ static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
/* Ports initialization */
static int mvpp2_port_probe(struct platform_device *pdev,
struct device_node *port_node,
- struct mvpp2 *priv, int index)
+ struct mvpp2 *priv)
{
struct device_node *phy_node;
struct phy *comphy;
@@ -7934,7 +7934,8 @@ static int mvpp2_port_probe(struct platform_device *pdev,
}
netdev_info(dev, "Using %s mac address %pM\n", mac_from, dev->dev_addr);
- priv->port_list[index] = port;
+ priv->port_list[priv->port_count++] = port;
+
return 0;
err_free_port_pcpu:
@@ -8313,28 +8314,17 @@ static int mvpp2_probe(struct platform_device *pdev)
goto err_mg_clk;
}
- priv->port_count = of_get_available_child_count(dn);
- if (priv->port_count == 0) {
- dev_err(&pdev->dev, "no ports enabled\n");
- err = -ENODEV;
- goto err_mg_clk;
- }
-
- priv->port_list = devm_kcalloc(&pdev->dev, priv->port_count,
- sizeof(*priv->port_list),
- GFP_KERNEL);
- if (!priv->port_list) {
- err = -ENOMEM;
- goto err_mg_clk;
- }
-
/* Initialize ports */
- i = 0;
for_each_available_child_of_node(dn, port_node) {
- err = mvpp2_port_probe(pdev, port_node, priv, i);
+ err = mvpp2_port_probe(pdev, port_node, priv);
if (err < 0)
goto err_port_probe;
- i++;
+ }
+
+ if (priv->port_count == 0) {
+ dev_err(&pdev->dev, "no ports enabled\n");
+ err = -ENODEV;
+ goto err_mg_clk;
}
/* Statistics must be gathered regularly because some of them (like
--
2.7.4
^ permalink raw reply related
* [net-next: PATCH v2 4/5] net: mvpp2: use device_*/fwnode_* APIs instead of of_*
From: Marcin Wojtas @ 2017-12-31 11:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514721520-18964-1-git-send-email-mw@semihalf.com>
OF functions can be used only for the driver using DT.
As a preparation for introducing ACPI support in mvpp2
driver, use struct fwnode_handle in order to obtain
properties from the hardware description.
Because there is no equivalent for for_each_available_child_of_node(),
use device_for_each_child_node() and check the port availability
inside the mvpp2_port_probe() routine.
This patch replaces of_* function with device_*/fwnode_*
where possible in the mvpp2.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 47 +++++++++++---------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 7f42d90..537474f 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -932,6 +932,9 @@ struct mvpp2_port {
struct mvpp2 *priv;
+ /* Firmware node associated to the port */
+ struct fwnode_handle *fwnode;
+
/* Per-port registers' base address */
void __iomem *base;
void __iomem *stats_base;
@@ -7711,17 +7714,16 @@ static bool mvpp2_port_has_tx_irqs(struct mvpp2 *priv,
}
static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
- struct device_node *port_node,
+ struct fwnode_handle *fwnode,
char **mac_from)
{
struct mvpp2_port *port = netdev_priv(dev);
char hw_mac_addr[ETH_ALEN] = {0};
- const char *dt_mac_addr;
+ char fw_mac_addr[ETH_ALEN];
- dt_mac_addr = of_get_mac_address(port_node);
- if (dt_mac_addr && is_valid_ether_addr(dt_mac_addr)) {
- *mac_from = "device tree";
- ether_addr_copy(dev->dev_addr, dt_mac_addr);
+ if (fwnode_get_mac_address(fwnode, fw_mac_addr, ETH_ALEN)) {
+ *mac_from = "firmware node";
+ ether_addr_copy(dev->dev_addr, fw_mac_addr);
return;
}
@@ -7740,13 +7742,14 @@ static void mvpp2_port_copy_mac_addr(struct net_device *dev, struct mvpp2 *priv,
/* Ports initialization */
static int mvpp2_port_probe(struct platform_device *pdev,
- struct device_node *port_node,
+ struct fwnode_handle *port_fwnode,
struct mvpp2 *priv)
{
struct device_node *phy_node;
struct phy *comphy;
struct mvpp2_port *port;
struct mvpp2_port_pcpu *port_pcpu;
+ struct device_node *port_node = to_of_node(port_fwnode);
struct net_device *dev;
struct resource *res;
char *mac_from = "";
@@ -7757,6 +7760,10 @@ static int mvpp2_port_probe(struct platform_device *pdev,
int phy_mode;
int err, i, cpu;
+ /* Silently exit, if the port node turns out to be disabled. */
+ if (!fwnode_device_is_available(port_fwnode))
+ return 0;
+
has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node);
if (!has_tx_irqs)
@@ -7773,7 +7780,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
return -ENOMEM;
phy_node = of_parse_phandle(port_node, "phy", 0);
- phy_mode = of_get_phy_mode(port_node);
+ phy_mode = fwnode_get_phy_mode(port_fwnode);
if (phy_mode < 0) {
dev_err(&pdev->dev, "incorrect phy mode\n");
err = phy_mode;
@@ -7789,7 +7796,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
comphy = NULL;
}
- if (of_property_read_u32(port_node, "port-id", &id)) {
+ if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
err = -EINVAL;
dev_err(&pdev->dev, "missing port-id value\n");
goto err_free_netdev;
@@ -7820,7 +7827,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
/* the link irq is optional */
port->link_irq = 0;
- if (of_property_read_bool(port_node, "marvell,loopback"))
+ if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
port->flags |= MVPP2_F_LOOPBACK;
port->id = id;
@@ -7845,8 +7852,8 @@ static int mvpp2_port_probe(struct platform_device *pdev,
MVPP21_MIB_COUNTERS_OFFSET +
port->gop_id * MVPP21_MIB_COUNTERS_PORT_SZ;
} else {
- if (of_property_read_u32(port_node, "gop-port-id",
- &port->gop_id)) {
+ if (fwnode_property_read_u32(port_fwnode, "gop-port-id",
+ &port->gop_id)) {
err = -EINVAL;
dev_err(&pdev->dev, "missing gop-port-id value\n");
goto err_deinit_qvecs;
@@ -7876,7 +7883,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
mutex_init(&port->gather_stats_lock);
INIT_DELAYED_WORK(&port->stats_work, mvpp2_gather_hw_statistics);
- mvpp2_port_copy_mac_addr(dev, priv, port_node, &mac_from);
+ mvpp2_port_copy_mac_addr(dev, priv, port_fwnode, &mac_from);
port->tx_ring_size = MVPP2_MAX_TXD_DFLT;
port->rx_ring_size = MVPP2_MAX_RXD_DFLT;
@@ -8194,8 +8201,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
static int mvpp2_probe(struct platform_device *pdev)
{
- struct device_node *dn = pdev->dev.of_node;
- struct device_node *port_node;
+ struct fwnode_handle *port_fwnode;
struct mvpp2 *priv;
struct resource *res;
void __iomem *base;
@@ -8315,8 +8321,8 @@ static int mvpp2_probe(struct platform_device *pdev)
}
/* Initialize ports */
- for_each_available_child_of_node(dn, port_node) {
- err = mvpp2_port_probe(pdev, port_node, priv);
+ device_for_each_child_node(&pdev->dev, port_fwnode) {
+ err = mvpp2_port_probe(pdev, port_fwnode, priv);
if (err < 0)
goto err_port_probe;
}
@@ -8347,7 +8353,7 @@ static int mvpp2_probe(struct platform_device *pdev)
err_port_probe:
i = 0;
- for_each_available_child_of_node(dn, port_node) {
+ device_for_each_child_node(&pdev->dev, port_fwnode) {
if (priv->port_list[i])
mvpp2_port_remove(priv->port_list[i]);
i++;
@@ -8366,14 +8372,13 @@ static int mvpp2_probe(struct platform_device *pdev)
static int mvpp2_remove(struct platform_device *pdev)
{
struct mvpp2 *priv = platform_get_drvdata(pdev);
- struct device_node *dn = pdev->dev.of_node;
- struct device_node *port_node;
+ struct fwnode_handle *port_fwnode;
int i = 0;
flush_workqueue(priv->stats_queue);
destroy_workqueue(priv->stats_queue);
- for_each_available_child_of_node(dn, port_node) {
+ device_for_each_child_node(&pdev->dev, port_fwnode) {
if (priv->port_list[i]) {
mutex_destroy(&priv->port_list[i]->gather_stats_lock);
mvpp2_port_remove(priv->port_list[i]);
--
2.7.4
^ permalink raw reply related
* [net-next: PATCH v2 5/5] net: mvpp2: enable ACPI support in the driver
From: Marcin Wojtas @ 2017-12-31 11:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514721520-18964-1-git-send-email-mw@semihalf.com>
This patch introduces an alternative way of obtaining resources - via
ACPI tables provided by firmware. Enabling coexistence with the DT
support, in addition to the OF_*->device_*/fwnode_* API replacement,
required following steps to be taken:
* Add mvpp2_acpi_match table
* Omit clock configuration and obtain tclk from the property - in ACPI
world, the firmware is responsible for clock maintenance.
* Disable comphy and syscon handling as they are not available for ACPI.
* Modify way of obtaining interrupts - with ACPI they are resources
bound to struct platform_device and it's not possible to obtain
them directly from the child node. Hence a formula is used, depending
on the port_id and number of possible CPUs.
* Until proper MDIO bus and PHY handling with ACPI is established in the
kernel, use only link interrupts feature in the driver.
* When booting with ACPI MVPP2_QDIST_MULTI_MODE is picked by
default, as there is no need to keep any kind of the backward
compatibility.
Moreover, a memory region used by mvmdio driver is usually placed in
the middle of the address space of the PP2 network controller.
The MDIO base address is obtained without requesting memory region
(by devm_ioremap() call) in mvmdio.c, later overlapping resources are
requested by the network driver, which is responsible for avoiding
a concurrent access.
In case the MDIO memory region is declared in the ACPI, it can
already appear as 'in-use' in the OS. Because it is overlapped by second
region of the network controller, make sure it is released, before
requesting it again. The care is taken by mvpp2 driver to avoid
concurrent access to this memory region.
Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 147 ++++++++++++++------
1 file changed, 103 insertions(+), 44 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 537474f..8b1c9a3 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -10,6 +10,7 @@
* warranty of any kind, whether express or implied.
*/
+#include <linux/acpi.h>
#include <linux/kernel.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
@@ -7469,7 +7470,8 @@ static int mvpp2_simple_queue_vectors_init(struct mvpp2_port *port,
return 0;
}
-static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
+static int mvpp2_multi_queue_vectors_init(struct platform_device *pdev,
+ struct mvpp2_port *port,
struct device_node *port_node)
{
struct mvpp2_queue_vector *v;
@@ -7502,7 +7504,11 @@ static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
strncpy(irqname, "rx-shared", sizeof(irqname));
}
- v->irq = of_irq_get_byname(port_node, irqname);
+ if (port_node)
+ v->irq = of_irq_get_byname(port_node, irqname);
+ else
+ v->irq = platform_get_irq(pdev, port->id *
+ (port->nqvecs + 2) + i);
if (v->irq <= 0) {
ret = -EINVAL;
goto err;
@@ -7520,11 +7526,12 @@ static int mvpp2_multi_queue_vectors_init(struct mvpp2_port *port,
return ret;
}
-static int mvpp2_queue_vectors_init(struct mvpp2_port *port,
+static int mvpp2_queue_vectors_init(struct platform_device *pdev,
+ struct mvpp2_port *port,
struct device_node *port_node)
{
if (port->has_tx_irqs)
- return mvpp2_multi_queue_vectors_init(port, port_node);
+ return mvpp2_multi_queue_vectors_init(pdev, port, port_node);
else
return mvpp2_simple_queue_vectors_init(port, port_node);
}
@@ -7746,7 +7753,7 @@ static int mvpp2_port_probe(struct platform_device *pdev,
struct mvpp2 *priv)
{
struct device_node *phy_node;
- struct phy *comphy;
+ struct phy *comphy = NULL;
struct mvpp2_port *port;
struct mvpp2_port_pcpu *port_pcpu;
struct device_node *port_node = to_of_node(port_fwnode);
@@ -7764,7 +7771,12 @@ static int mvpp2_port_probe(struct platform_device *pdev,
if (!fwnode_device_is_available(port_fwnode))
return 0;
- has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node);
+ if (port_node) {
+ has_tx_irqs = mvpp2_port_has_tx_irqs(priv, port_node);
+ } else {
+ has_tx_irqs = true;
+ queue_mode = MVPP2_QDIST_MULTI_MODE;
+ }
if (!has_tx_irqs)
queue_mode = MVPP2_QDIST_SINGLE_MODE;
@@ -7779,7 +7791,11 @@ static int mvpp2_port_probe(struct platform_device *pdev,
if (!dev)
return -ENOMEM;
- phy_node = of_parse_phandle(port_node, "phy", 0);
+ if (port_node)
+ phy_node = of_parse_phandle(port_node, "phy", 0);
+ else
+ phy_node = NULL;
+
phy_mode = fwnode_get_phy_mode(port_fwnode);
if (phy_mode < 0) {
dev_err(&pdev->dev, "incorrect phy mode\n");
@@ -7787,13 +7803,15 @@ static int mvpp2_port_probe(struct platform_device *pdev,
goto err_free_netdev;
}
- comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
- if (IS_ERR(comphy)) {
- if (PTR_ERR(comphy) == -EPROBE_DEFER) {
- err = -EPROBE_DEFER;
- goto err_free_netdev;
+ if (port_node) {
+ comphy = devm_of_phy_get(&pdev->dev, port_node, NULL);
+ if (IS_ERR(comphy)) {
+ if (PTR_ERR(comphy) == -EPROBE_DEFER) {
+ err = -EPROBE_DEFER;
+ goto err_free_netdev;
+ }
+ comphy = NULL;
}
- comphy = NULL;
}
if (fwnode_property_read_u32(port_fwnode, "port-id", &id)) {
@@ -7813,12 +7831,18 @@ static int mvpp2_port_probe(struct platform_device *pdev,
port->nrxqs = nrxqs;
port->priv = priv;
port->has_tx_irqs = has_tx_irqs;
+ port->id = id;
- err = mvpp2_queue_vectors_init(port, port_node);
+ err = mvpp2_queue_vectors_init(pdev, port, port_node);
if (err)
goto err_free_netdev;
- port->link_irq = of_irq_get_byname(port_node, "link");
+ if (port_node)
+ port->link_irq = of_irq_get_byname(port_node, "link");
+ else
+ port->link_irq = platform_get_irq(pdev, port->id *
+ (port->nqvecs + 2) +
+ port->nqvecs + 1);
if (port->link_irq == -EPROBE_DEFER) {
err = -EPROBE_DEFER;
goto err_deinit_qvecs;
@@ -7830,7 +7854,6 @@ static int mvpp2_port_probe(struct platform_device *pdev,
if (fwnode_property_read_bool(port_fwnode, "marvell,loopback"))
port->flags |= MVPP2_F_LOOPBACK;
- port->id = id;
if (priv->hw_version == MVPP21)
port->first_rxq = port->id * port->nrxqs;
else
@@ -8201,6 +8224,7 @@ static int mvpp2_init(struct platform_device *pdev, struct mvpp2 *priv)
static int mvpp2_probe(struct platform_device *pdev)
{
+ const struct acpi_device_id *acpi_id;
struct fwnode_handle *port_fwnode;
struct mvpp2 *priv;
struct resource *res;
@@ -8212,8 +8236,14 @@ static int mvpp2_probe(struct platform_device *pdev)
if (!priv)
return -ENOMEM;
- priv->hw_version =
- (unsigned long)of_device_get_match_data(&pdev->dev);
+ if (has_acpi_companion(&pdev->dev)) {
+ acpi_id = acpi_match_device(pdev->dev.driver->acpi_match_table,
+ &pdev->dev);
+ priv->hw_version = (unsigned long)acpi_id->driver_data;
+ } else {
+ priv->hw_version =
+ (unsigned long)of_device_get_match_data(&pdev->dev);
+ }
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, res);
@@ -8227,10 +8257,23 @@ static int mvpp2_probe(struct platform_device *pdev)
return PTR_ERR(priv->lms_base);
} else {
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+ if (has_acpi_companion(&pdev->dev)) {
+ /* In case the MDIO memory region is declared in
+ * the ACPI, it can already appear as 'in-use'
+ * in the OS. Because it is overlapped by second
+ * region of the network controller, make
+ * sure it is released, before requesting it again.
+ * The care is taken by mvpp2 driver to avoid
+ * concurrent access to this memory region.
+ */
+ release_resource(res);
+ }
priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(priv->iface_base))
return PTR_ERR(priv->iface_base);
+ }
+ if (priv->hw_version == MVPP22 && dev_of_node(&pdev->dev)) {
priv->sysctrl_base =
syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
"marvell,system-controller");
@@ -8256,32 +8299,34 @@ static int mvpp2_probe(struct platform_device *pdev)
else
priv->max_port_rxqs = 32;
- priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
- if (IS_ERR(priv->pp_clk))
- return PTR_ERR(priv->pp_clk);
- err = clk_prepare_enable(priv->pp_clk);
- if (err < 0)
- return err;
-
- priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
- if (IS_ERR(priv->gop_clk)) {
- err = PTR_ERR(priv->gop_clk);
- goto err_pp_clk;
- }
- err = clk_prepare_enable(priv->gop_clk);
- if (err < 0)
- goto err_pp_clk;
+ if (dev_of_node(&pdev->dev)) {
+ priv->pp_clk = devm_clk_get(&pdev->dev, "pp_clk");
+ if (IS_ERR(priv->pp_clk))
+ return PTR_ERR(priv->pp_clk);
+ err = clk_prepare_enable(priv->pp_clk);
+ if (err < 0)
+ return err;
- if (priv->hw_version == MVPP22) {
- priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
- if (IS_ERR(priv->mg_clk)) {
- err = PTR_ERR(priv->mg_clk);
- goto err_gop_clk;
+ priv->gop_clk = devm_clk_get(&pdev->dev, "gop_clk");
+ if (IS_ERR(priv->gop_clk)) {
+ err = PTR_ERR(priv->gop_clk);
+ goto err_pp_clk;
}
-
- err = clk_prepare_enable(priv->mg_clk);
+ err = clk_prepare_enable(priv->gop_clk);
if (err < 0)
- goto err_gop_clk;
+ goto err_pp_clk;
+
+ if (priv->hw_version == MVPP22) {
+ priv->mg_clk = devm_clk_get(&pdev->dev, "mg_clk");
+ if (IS_ERR(priv->mg_clk)) {
+ err = PTR_ERR(priv->mg_clk);
+ goto err_gop_clk;
+ }
+
+ err = clk_prepare_enable(priv->mg_clk);
+ if (err < 0)
+ goto err_gop_clk;
+ }
priv->axi_clk = devm_clk_get(&pdev->dev, "axi_clk");
if (IS_ERR(priv->axi_clk)) {
@@ -8294,10 +8339,14 @@ static int mvpp2_probe(struct platform_device *pdev)
if (err < 0)
goto err_gop_clk;
}
- }
- /* Get system's tclk rate */
- priv->tclk = clk_get_rate(priv->pp_clk);
+ /* Get system's tclk rate */
+ priv->tclk = clk_get_rate(priv->pp_clk);
+ } else if (device_property_read_u32(&pdev->dev, "clock-frequency",
+ &priv->tclk)) {
+ dev_err(&pdev->dev, "missing clock-frequency value\n");
+ return -EINVAL;
+ }
if (priv->hw_version == MVPP22) {
err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(40));
@@ -8401,6 +8450,9 @@ static int mvpp2_remove(struct platform_device *pdev)
aggr_txq->descs_dma);
}
+ if (is_acpi_node(port_fwnode))
+ return 0;
+
clk_disable_unprepare(priv->axi_clk);
clk_disable_unprepare(priv->mg_clk);
clk_disable_unprepare(priv->pp_clk);
@@ -8422,12 +8474,19 @@ static const struct of_device_id mvpp2_match[] = {
};
MODULE_DEVICE_TABLE(of, mvpp2_match);
+static const struct acpi_device_id mvpp2_acpi_match[] = {
+ { "MRVL0110", MVPP22 },
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, mvpp2_acpi_match);
+
static struct platform_driver mvpp2_driver = {
.probe = mvpp2_probe,
.remove = mvpp2_remove,
.driver = {
.name = MVPP2_DRIVER_NAME,
.of_match_table = mvpp2_match,
+ .acpi_match_table = ACPI_PTR(mvpp2_acpi_match),
},
};
--
2.7.4
^ permalink raw reply related
* [PATCH 01/33] clk_ops: change round_rate() to return unsigned long
From: Bryan O'Donoghue @ 2017-12-31 13:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <9f4bef5a-8a71-6f30-5cfb-5e8fe133e3d3@kapsi.fi>
On 30/12/17 16:36, Mikko Perttunen wrote:
> FWIW, we had this problem some years ago with the Tegra CPU clock - then
> it was determined that a simpler solution was to have the determine_rate
> callback support unsigned long rates - so clock drivers that need to
> return rates higher than 2^31 can instead implement the determine_rate
> callback. That is what's currently implemented.
>
> Mikko
Granted we could work around it but, having both zero and less than zero
indicate error means you can't support larger than LONG_MAX which is I
think worth fixing.
---
bod
^ permalink raw reply
* [GIT PULL] ARM: at91: DT for 4.16
From: Alexandre Belloni @ 2017-12-31 15:11 UTC (permalink / raw)
To: linux-arm-kernel
Arnd, Olof,
This is the at91 DT pull request. The bulk of it is the switch to the
new TCB bindings that were acked a long time ago. These changes are
compatible with the current driver and taking them now will allow for a
smooth transition.
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git tags/at91-ab-4.16-dt
for you to fetch changes up to 34a7fc3147bcc14127d941f228ce3b1737e66381:
ARM: dts: at91: sama5d2_ptc_ek: use TCB0 as timers (2017-12-31 15:50:20 +0100)
----------------------------------------------------------------
DT for 4.16
- New boards:
- Axentia Nattis with Natte power
- sama5d2 PTC ek
- Document and use extended TCB bindings
----------------------------------------------------------------
Alexandre Belloni (45):
ARM: at91: Document new TCB bindings
ARM: dts: at91: at91rm9200: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91rm9200ek: use TCB0 for timers
ARM: dts: at91: mpa1600: use TCB0 as timers
ARM: dts: at91: at91sam9260: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91sam9260ek: use TCB0 as timers
ARM: dts: at91: sam9_l9260: use TCB0 as timers
ARM: dts: at91: ethernut5: use TCB0 as timers
ARM: dts: at91: foxg20: use TCB0 as timers
ARM: dts: at91: animeo_ip: use TCB0 as timers
ARM: dts: at91: kizbox: use TCB0 as timers
ARM: dts: at91: at91sam9g20ek: use TCB0 as timers
ARM: dts: at91: ge863-pro3: use TCB0 as timers
ARM: dts: at91: at91sam9261: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91sam9261ek: use TCB0 as timers
ARM: dts: at91: at91sam9263: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91sam9263ek: use TCB0 as timers
ARM: dts: at91: calao: use TCB0 as timers
ARM: dts: at91: at91sam9g45: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91sam9m10g45ek: use TCB0 as timers
ARM: dts: at91: pm9g45: use TCB0 as timers
ARM: dts: at91: at91sam9rl: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91sam9rlek: use TCB0 as timers
ARM: dts: at91: at91sam9n12: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91sam9n12ek: use TCB0 as timers
ARM: dts: at91: at91sam9x5: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: at91sam9x5cm: use TCB0 as timers
ARM: dts: at91: acme/g25: use TCB0 as timers
ARM: dts: at91: cosino: use TCB0 as timers
ARM: dts: at91: kizboxmini: use TCB0 as timers
ARM: dts: at91: sama5d3: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: sama5d3xek: use TCB0 as timers
ARM: dts: at91: sama5d3 Xplained: use TCB0 as timers
ARM: dts: at91: kizbox2: use TCB0 as timers
ARM: dts: at91: sama5d3xek_cmp: use TCB0 as timers
ARM: dts: at91: linea/tse850-3: use TCB0 as timers
ARM: dts: at91: sama5d4: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: sama5d4: Add TCB2
ARM: dts: at91: sama5d4ek: use TCB2 as timers
ARM: dts: at91: sama5d4 Xplained: use TCB2 as timers
ARM: dts: at91: ma5d4: use TCB2 as timers
ARM: dts: at91: vinco: use TCB2 as timers
ARM: dts: at91: sama5d2: TC blocks are also simple-mfd and syscon devices
ARM: dts: at91: sama5d2 Xplained: use TCB0 as timers
ARM: dts: at91: sama5d27_som1_ek: use TCB0 as timers
Eugen Hristev (1):
ARM: dts: at91: sama5d2: added dma property for ADC device
Ludovic Desroches (1):
ARM: dts: at91: introduce the sama5d2 ptc ek board
Mathieu Malaterre (1):
ARM: dts: at91: Remove leading 0x and 0s from bindings notation
Nicolas Ferre (1):
ARM: dts: at91: sama5d2_ptc_ek: use TCB0 as timers
Peter Rosin (1):
ARM: dts: at91: add devicetree for the Axentia Nattis with Natte power
.../devicetree/bindings/arm/atmel-at91.txt | 32 --
Documentation/devicetree/bindings/arm/axentia.txt | 9 +
.../devicetree/bindings/mfd/atmel-tcb.txt | 56 +++
MAINTAINERS | 2 +
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/animeo_ip.dts | 12 +
arch/arm/boot/dts/at91-ariag25.dts | 12 +
arch/arm/boot/dts/at91-ariettag25.dts | 12 +
arch/arm/boot/dts/at91-cosino.dtsi | 12 +
arch/arm/boot/dts/at91-foxg20.dts | 12 +
arch/arm/boot/dts/at91-kizbox.dts | 12 +
arch/arm/boot/dts/at91-kizbox2.dts | 12 +
arch/arm/boot/dts/at91-kizboxmini.dts | 12 +
arch/arm/boot/dts/at91-linea.dtsi | 12 +
arch/arm/boot/dts/at91-natte.dtsi | 244 ++++++++++++
arch/arm/boot/dts/at91-nattis-2-natte-2.dts | 258 +++++++++++++
arch/arm/boot/dts/at91-qil_a9260.dts | 12 +
arch/arm/boot/dts/at91-sam9_l9260.dts | 12 +
arch/arm/boot/dts/at91-sama5d27_som1_ek.dts | 12 +
arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts | 413 +++++++++++++++++++++
arch/arm/boot/dts/at91-sama5d2_xplained.dts | 12 +
arch/arm/boot/dts/at91-sama5d3_xplained.dts | 12 +
arch/arm/boot/dts/at91-sama5d4_ma5d4.dtsi | 12 +
arch/arm/boot/dts/at91-sama5d4_xplained.dts | 12 +
arch/arm/boot/dts/at91-sama5d4ek.dts | 12 +
arch/arm/boot/dts/at91-vinco.dts | 12 +
arch/arm/boot/dts/at91rm9200.dtsi | 8 +-
arch/arm/boot/dts/at91rm9200ek.dts | 12 +
arch/arm/boot/dts/at91sam9260.dtsi | 8 +-
arch/arm/boot/dts/at91sam9260ek.dts | 12 +
arch/arm/boot/dts/at91sam9261.dtsi | 6 +-
arch/arm/boot/dts/at91sam9261ek.dts | 22 +-
arch/arm/boot/dts/at91sam9263.dtsi | 6 +-
arch/arm/boot/dts/at91sam9263ek.dts | 14 +-
arch/arm/boot/dts/at91sam9g20ek_common.dtsi | 12 +
arch/arm/boot/dts/at91sam9g25ek.dts | 2 +-
arch/arm/boot/dts/at91sam9g45.dtsi | 10 +-
arch/arm/boot/dts/at91sam9m10g45ek.dts | 14 +-
arch/arm/boot/dts/at91sam9n12.dtsi | 8 +-
arch/arm/boot/dts/at91sam9n12ek.dts | 12 +
arch/arm/boot/dts/at91sam9rl.dtsi | 4 +-
arch/arm/boot/dts/at91sam9rlek.dts | 12 +
arch/arm/boot/dts/at91sam9x5.dtsi | 8 +-
arch/arm/boot/dts/at91sam9x5cm.dtsi | 12 +
arch/arm/boot/dts/ethernut5.dts | 12 +
arch/arm/boot/dts/ge863-pro3.dtsi | 12 +
arch/arm/boot/dts/mpa1600.dts | 12 +
arch/arm/boot/dts/pm9g45.dts | 12 +
arch/arm/boot/dts/sama5d2.dtsi | 10 +-
arch/arm/boot/dts/sama5d3.dtsi | 4 +-
arch/arm/boot/dts/sama5d3_tcb1.dtsi | 4 +-
arch/arm/boot/dts/sama5d3xcm.dtsi | 12 +
arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 12 +
arch/arm/boot/dts/sama5d3xmb.dtsi | 2 +-
arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 2 +-
arch/arm/boot/dts/sama5d4.dtsi | 18 +-
arch/arm/boot/dts/tny_a9260_common.dtsi | 12 +
arch/arm/boot/dts/tny_a9263.dts | 12 +
arch/arm/boot/dts/usb_a9260_common.dtsi | 12 +
arch/arm/boot/dts/usb_a9263.dts | 12 +
60 files changed, 1514 insertions(+), 60 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/atmel-tcb.txt
create mode 100644 arch/arm/boot/dts/at91-natte.dtsi
create mode 100644 arch/arm/boot/dts/at91-nattis-2-natte-2.dts
create mode 100644 arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: dts: bcm2837-rpi-3-b: fix pwm1 pin
From: Baruch Siach @ 2017-12-31 15:12 UTC (permalink / raw)
To: linux-arm-kernel
Raspberry Pi 3 uses GPIO45 for I2C SCL0. pwm1 is on GPIO41. Update the
DT description accordingly. Fix the following error that shows when
GPIO44 and GPIO45 are configured to I2C:
[ 1.751563] pinctrl-bcm2835 3f200000.gpio: pin gpio45 already requested by 3f205000.i2c; cannot claim for 3f20c000.pwm
[ 1.762474] pinctrl-bcm2835 3f200000.gpio: pin-45 (3f20c000.pwm) status -22
[ 1.775176] pinctrl-bcm2835 3f200000.gpio: could not request pin 45 (gpio45) from group gpio45 on device pinctrl-bcm2835
[ 1.786344] bcm2835-pwm 3f20c000.pwm: Error applying setting, reverse things back
[ 1.793980] bcm2835-pwm: probe of 3f20c000.pwm failed with error -22
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
---
arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
index a8844d033b3f..b44b3b5af00d 100644
--- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
+++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
@@ -60,3 +60,9 @@
status = "okay";
bus-width = <4>;
};
+
+&pwm {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
+ status = "okay";
+};
--
2.15.1
^ permalink raw reply related
* [GIT PULL] ARM: at91: drivers for 4.16
From: Alexandre Belloni @ 2017-12-31 15:34 UTC (permalink / raw)
To: linux-arm-kernel
Arnd, Olof,
A single harmless change for this pull request. I hope you'll enjoy this
New Year's Eve.
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git tags/at91-ab-4.16-drivers
for you to fetch changes up to 1203839290f151b84f5e54165d6d039e9514b236:
pcmcia: at91_cf: Use PTR_ERR_OR_ZERO() (2017-11-29 21:58:58 +0100)
----------------------------------------------------------------
drivers for 4.16
- use PTR_ERR_OR_ZERO were relevant in at91_cf
----------------------------------------------------------------
Vasyl Gomonovych (1):
pcmcia: at91_cf: Use PTR_ERR_OR_ZERO()
drivers/pcmcia/at91_cf.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: dts: bcm2837-rpi-3-b: fix pwm1 pin
From: Stefan Wahren @ 2017-12-31 16:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <da85c22315e08c7dc4dfdebae983278909cfee83.1514733168.git.baruch@tkos.co.il>
Hi Baruch,
> Baruch Siach <baruch@tkos.co.il> hat am 31. Dezember 2017 um 16:12 geschrieben:
>
>
> Raspberry Pi 3 uses GPIO45 for I2C SCL0. pwm1 is on GPIO41. Update the
> DT description accordingly. Fix the following error that shows when
> GPIO44 and GPIO45 are configured to I2C:
>
> [ 1.751563] pinctrl-bcm2835 3f200000.gpio: pin gpio45 already requested by 3f205000.i2c; cannot claim for 3f20c000.pwm
> [ 1.762474] pinctrl-bcm2835 3f200000.gpio: pin-45 (3f20c000.pwm) status -22
> [ 1.775176] pinctrl-bcm2835 3f200000.gpio: could not request pin 45 (gpio45) from group gpio45 on device pinctrl-bcm2835
> [ 1.786344] bcm2835-pwm 3f20c000.pwm: Error applying setting, reverse things back
> [ 1.793980] bcm2835-pwm: probe of 3f20c000.pwm failed with error -22
>
> Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> ---
> arch/arm/boot/dts/bcm2837-rpi-3-b.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
> index a8844d033b3f..b44b3b5af00d 100644
> --- a/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
> +++ b/arch/arm/boot/dts/bcm2837-rpi-3-b.dts
> @@ -60,3 +60,9 @@
> status = "okay";
> bus-width = <4>;
> };
> +
> +&pwm {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pwm0_gpio40 &pwm1_gpio41>;
> + status = "okay";
> +};
thanks for addressing this old issue. Unfortunately this is only a part of the solution. The real problem is the definition of pinctrl in a very common dtsi file (bcm2835-rpi.dtsi). Based on the Firmware dt-blob i created a pin usage map [1], which also shows a potential conflict on RPI Zero W.
So i think we should remove the pwm part from bcm2835-rpi.dtsi and define it on board level like in your patch, but also for the other boards. My suggestion would be the following (based on Firmware):
A Plus -> PWM on pin 40,45
A -> PWM on pin 40,45
B Plus -> PWM on pin 40,45
B Rev 2 -> PWM on pin 40,45
B -> PWM on pin 40,45
2 b -> PWM on pin 40,45
3 b -> PWM on pin 40,41
Zero -> No PWM
Zero W -> No PWM
But i think we should wait for Eric's opinion.
Regards
Stefan
[1] - https://github.com/raspberrypi/firmware/wiki/Pin-usage-reference
^ permalink raw reply
* [net-next: PATCH v2 4/5] net: mvpp2: use device_*/fwnode_* APIs instead of of_*
From: Andrew Lunn @ 2017-12-31 19:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514721520-18964-5-git-send-email-mw@semihalf.com>
On Sun, Dec 31, 2017 at 12:58:39PM +0100, Marcin Wojtas wrote:
Hi Marcin
> Because there is no equivalent for for_each_available_child_of_node(),
> use device_for_each_child_node() and check the port availability
> inside the mvpp2_port_probe() routine.
Could device_each_available_child_node() be added? I guess this will
not be the last driver converted in this way, and having that macro
will help with future ports.
Andrew
^ permalink raw reply
* [net-next: PATCH v2 5/5] net: mvpp2: enable ACPI support in the driver
From: Andrew Lunn @ 2017-12-31 19:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514721520-18964-6-git-send-email-mw@semihalf.com>
> * Modify way of obtaining interrupts - with ACPI they are resources
> bound to struct platform_device and it's not possible to obtain
> them directly from the child node. Hence a formula is used, depending
> on the port_id and number of possible CPUs.
Hi Marcin
I know nothing about ACPI. Is this limitation with respect to
interrupts fundamental to ACPI, or just that nobody has implemented
flexible interrupt support yet?
> * Until proper MDIO bus and PHY handling with ACPI is established in the
> kernel, use only link interrupts feature in the driver.
I think interrupts might be interesting with PHY devices, since they
are child nodes of the MDIO device....
Andrew
^ permalink raw reply
* [PATCH v4 0/7] ARM: davinci: convert to common clock framework
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
This series converts mach-davinci to use the common clock framework.
Basically, this series does some cleanup and rearranging to get things
ready for the conversion. Then there is a patch to add new driver in
drivers/clk and finally a patch to make the conversion from the mach
clock drivers to the new drivers.
I have tested this on LEGO MINDSTORMS EV3 (TI AM1808), so I am confident
that I haven't broken anything (too badly) in da850. But, I don't have
other hardware to test.
The one thing that I know I have broken is CPU frequency scaling on da850.
I don't think it was working with device tree anyway, so I can't really test
it with the hardware I have. I'm hoping that it will be OK to defer fixing
it and add device tree support at the same time.
Dependencies:
* This series applies on top of "ARM: davinici: move watchdog restart from
mach to drivers?" [1][2]
* On da850, you will also need a patch to prevent problems with the USB PHY
clocks [3]
* Or get it all at once:
git fetch https://github.com/dlech/ev3dev-kernel.git common-clk-v4
[1]: https://patchwork.kernel.org/patch/10105623/
[2]: https://patchwork.kernel.org/patch/10105613/
[3]: https://patchwork.kernel.org/patch/10133193/
v4 changes:
* Basically, the whole series is new/reworked except for the first patch.
* Instead of having an intermediate conversion of the clocks in mach-davinci,
new clock drivers are introduced in drivers/clk.
* There are a few more cleanup patches added before making the conversion.
v3 changes:
* Remove leftovers from rebasing in "ARM: davinci: don't use static clk_lookup"
(fixes compile error)
v2 changes:
* Dropped "ARM: davinci: clean up map_io functions" - will resend as separate
patch series
* Reworked remaining patches so that there is less shuffling around
David Lechner (7):
ARM: davinci: move davinci_clk_init() to init_time
ARM: davinci: don't use static clk_lookup
ARM: davinci: fix duplicate clocks
ARM: davinci: remove davinci_set_refclk_rate()
clk: Introduce davinci clocks
ARM: davinci: convert to common clock framework
ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS
arch/arm/Kconfig | 2 +-
arch/arm/configs/davinci_all_defconfig | 1 -
arch/arm/mach-davinci/Kconfig | 12 -
arch/arm/mach-davinci/Makefile | 2 +-
arch/arm/mach-davinci/board-da830-evm.c | 17 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 17 +-
arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 17 +-
arch/arm/mach-davinci/board-sffsdr.c | 2 +-
arch/arm/mach-davinci/clock.c | 745 --------------------------
arch/arm/mach-davinci/clock.h | 72 ---
arch/arm/mach-davinci/common.c | 1 -
arch/arm/mach-davinci/da830.c | 536 +++++--------------
arch/arm/mach-davinci/da850.c | 785 ++++++----------------------
arch/arm/mach-davinci/da8xx-dt.c | 17 +-
arch/arm/mach-davinci/davinci.h | 4 +
arch/arm/mach-davinci/devices-da8xx.c | 46 +-
arch/arm/mach-davinci/dm355.c | 452 ++++------------
arch/arm/mach-davinci/dm365.c | 594 ++++++---------------
arch/arm/mach-davinci/dm644x.c | 401 ++++----------
arch/arm/mach-davinci/dm646x.c | 451 +++++-----------
arch/arm/mach-davinci/include/mach/clock.h | 3 -
arch/arm/mach-davinci/include/mach/common.h | 9 -
arch/arm/mach-davinci/include/mach/da8xx.h | 11 +-
arch/arm/mach-davinci/psc.c | 137 -----
arch/arm/mach-davinci/psc.h | 14 -
arch/arm/mach-davinci/usb-da8xx.c | 225 +-------
drivers/clk/Makefile | 1 +
drivers/clk/davinci/Makefile | 3 +
drivers/clk/davinci/da8xx-cfgchip-clk.c | 380 ++++++++++++++
drivers/clk/davinci/pll.c | 333 ++++++++++++
drivers/clk/davinci/psc.c | 217 ++++++++
include/linux/clk/davinci.h | 46 ++
include/linux/platform_data/davinci_clk.h | 25 +
40 files changed, 1875 insertions(+), 3717 deletions(-)
delete mode 100644 arch/arm/mach-davinci/clock.c
delete mode 100644 arch/arm/mach-davinci/psc.c
create mode 100644 drivers/clk/davinci/Makefile
create mode 100644 drivers/clk/davinci/da8xx-cfgchip-clk.c
create mode 100644 drivers/clk/davinci/pll.c
create mode 100644 drivers/clk/davinci/psc.c
create mode 100644 include/linux/clk/davinci.h
create mode 100644 include/linux/platform_data/davinci_clk.h
--
2.7.4
^ permalink raw reply
* [PATCH v4 1/7] ARM: davinci: move davinci_clk_init() to init_time
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
This moves the call of davinci_clk_init() from map_io to init_time for all
boards.
This is the proper place to init clocks. This is also done in preparation
for moving to the common clock framework.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 2 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 11 +++++++----
arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 2 +-
arch/arm/mach-davinci/board-sffsdr.c | 2 +-
arch/arm/mach-davinci/da830.c | 4 ++++
arch/arm/mach-davinci/da850.c | 4 ++++
arch/arm/mach-davinci/da8xx-dt.c | 2 +-
arch/arm/mach-davinci/davinci.h | 4 ++++
arch/arm/mach-davinci/dm355.c | 5 +++++
arch/arm/mach-davinci/dm365.c | 5 +++++
arch/arm/mach-davinci/dm644x.c | 5 +++++
arch/arm/mach-davinci/dm646x.c | 5 +++++
arch/arm/mach-davinci/include/mach/da8xx.h | 3 +++
20 files changed, 53 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index a58bfca..7adf009 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -638,7 +638,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
.atag_offset = 0x100,
.map_io = da830_evm_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da830_init_time,
.init_machine = da830_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6039ec1..8602d0d 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1481,7 +1481,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
.atag_offset = 0x100,
.map_io = da850_evm_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = da850_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index d60d998..3c15cb7 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -416,7 +416,7 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.atag_offset = 0x100,
.map_io = dm355_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm355_init_time,
.init_machine = dm355_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 1e7e9b8..3ebc89d 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -271,7 +271,7 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.atag_offset = 0x100,
.map_io = dm355_leopard_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm355_init_time,
.init_machine = dm355_leopard_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 17b2c29..3daeac7 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -774,7 +774,7 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.atag_offset = 0x100,
.map_io = dm365_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm365_init_time,
.init_machine = dm365_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 5e1afc2..8d8c4ab 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -817,7 +817,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
.atag_offset = 0x100,
.map_io = davinci_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 003bbe5..dafc852 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -721,9 +721,12 @@ static void __init evm_init_i2c(void)
static void __init davinci_map_io(void)
{
dm646x_init();
+}
- if (machine_is_davinci_dm6467tevm())
- davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
+static void __init dm6467t_evm_init_time(void)
+{
+ dm646x_init_time();
+ davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
}
#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
@@ -797,7 +800,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm646x_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
@@ -807,7 +810,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm6467t_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 0b23cf3..f9a725a 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -570,7 +570,7 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
.atag_offset = 0x100,
.map_io = mityomapl138_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = mityomapl138_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 1e27baa..ff871a0 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -227,7 +227,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
.atag_offset = 0x100,
.map_io = davinci_ntosd2_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_ntosd2_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 88ab45c..bc8a747 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -334,7 +334,7 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
.atag_offset = 0x100,
.map_io = omapl138_hawk_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = omapl138_hawk_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 1f02d4e..2922da9 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -150,7 +150,7 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
.atag_offset = 0x100,
.map_io = davinci_sffsdr_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_sffsdr_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index ed0b700..6a8b6ff 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1220,6 +1220,10 @@ void __init da830_init(void)
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
+}
+void __init da830_init_time(void)
+{
davinci_clk_init(davinci_soc_info_da830.cpu_clks);
+ davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 04a58a3..4da5b25 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1392,6 +1392,10 @@ void __init da850_init(void)
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+}
+void __init da850_init_time(void)
+{
davinci_clk_init(davinci_soc_info_da850.cpu_clks);
+ davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 779e8ce..ab199f4 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -96,7 +96,7 @@ static const char *const da850_boards_compat[] __initconst = {
DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
.map_io = da850_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = da850_init_machine,
.dt_compat = da850_boards_compat,
.init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index c62b90c..d70f4d9 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -83,6 +83,7 @@ int davinci_init_wdt(void);
/* DM355 function declarations */
void dm355_init(void);
+void dm355_init_time(void);
void dm355_init_spi0(unsigned chipselect_mask,
const struct spi_board_info *info, unsigned len);
void dm355_init_asp1(u32 evt_enable);
@@ -91,6 +92,7 @@ int dm355_gpio_register(void);
/* DM365 function declarations */
void dm365_init(void);
+void dm365_init_time(void);
void dm365_init_asp(void);
void dm365_init_vc(void);
void dm365_init_ks(struct davinci_ks_platform_data *pdata);
@@ -102,12 +104,14 @@ int dm365_gpio_register(void);
/* DM644x function declarations */
void dm644x_init(void);
+void dm644x_init_time(void);
void dm644x_init_asp(void);
int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
int dm644x_gpio_register(void);
/* DM646x function declarations */
void dm646x_init(void);
+void dm646x_init_time(void);
void dm646x_init_mcasp0(struct snd_platform_data *pdata);
void dm646x_init_mcasp1(struct snd_platform_data *pdata);
int dm646x_init_edma(struct edma_rsv_info *rsv);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 938747f..40641c0 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1043,7 +1043,12 @@ void __init dm355_init(void)
{
davinci_common_init(&davinci_soc_info_dm355);
davinci_map_sysmod();
+}
+
+void __init dm355_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
+ davinci_timer_init();
}
int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 5d9f96d..0789ac6 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1168,7 +1168,12 @@ void __init dm365_init(void)
{
davinci_common_init(&davinci_soc_info_dm365);
davinci_map_sysmod();
+}
+
+void __init dm365_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
+ davinci_timer_init();
}
static struct resource dm365_vpss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 6b41e1c..a1a2433 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -931,7 +931,12 @@ void __init dm644x_init(void)
{
davinci_common_init(&davinci_soc_info_dm644x);
davinci_map_sysmod();
+}
+
+void __init dm644x_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
+ davinci_timer_init();
}
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 6fc06a6..c518403 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -956,7 +956,12 @@ void __init dm646x_init(void)
{
davinci_common_init(&davinci_soc_info_dm646x);
davinci_map_sysmod();
+}
+
+void __init dm646x_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
+ davinci_timer_init();
}
static int __init dm646x_init_devices(void)
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 751d2ac..3481a0d 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -87,7 +87,10 @@ extern unsigned int da850_max_speed;
#define DA8XX_ARM_RAM_BASE 0xffff0000
void da830_init(void);
+void da830_init_time(void);
+
void da850_init(void);
+void da850_init_time(void);
int da830_register_edma(struct edma_rsv_info *rsv);
int da850_register_edma(struct edma_rsv_info *rsv[2]);
--
2.7.4
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