* [PATCH v2 08/34] clk: bcm2835: change bcm2835_pll_rate_from_divisors to return unsigned long
From: Bryan O'Donoghue @ 2018-01-01 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514833681-30737-1-git-send-email-pure.logic@nexus-software.ie>
bcm2835_pll_rate_from_divisors() returns a value directly as the return
value to round_rate(). clk_ops->round_rate() has been changed to an
unsigned long so for the sake of completeness and neatness this patch
updates the helper function to return the same data-type.
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Eric Anholt <eric@anholt.net>
Cc: Stefan Wahren <stefan.wahren@i2se.com>
Cc: Florian Fainelli <f.fainelli@gmail.com>
Cc: Ray Jui <rjui@broadcom.com>
Cc: Scott Branden <sbranden@broadcom.com>
Cc: bcm-kernel-feedback-list at broadcom.com
Cc: Boris Brezillon <boris.brezillon@free-electrons.com>
Cc: Phil Elwell <phil@raspberrypi.org>
Cc: linux-clk at vger.kernel.org
Cc: linux-rpi-kernel at lists.infradead.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
drivers/clk/bcm/clk-bcm2835.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index c215dc9..fb2b012 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -541,8 +541,9 @@ static void bcm2835_pll_choose_ndiv_and_fdiv(unsigned long rate,
*fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
}
-static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
- u32 ndiv, u32 fdiv, u32 pdiv)
+static unsigned long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
+ u32 ndiv, u32 fdiv,
+ u32 pdiv)
{
u64 rate;
--
2.7.4
^ permalink raw reply related
* [PATCH v2 04/34] clk: omap2: change omap2_round_to_table_rate return logic
From: Bryan O'Donoghue @ 2018-01-01 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514833681-30737-1-git-send-email-pure.logic@nexus-software.ie>
This patch updates the round_rate() logic here to return zero instead of a
negative number on error.
In conjunction with higher-level changes associated with acting on the
return value of clk_ops->round_rate() it is then possible to have
clk_ops->round_rate() return values from 1 Hz to ULONG_MAX Hz instead of
the current limitation of 1 Hz to LONG_MAX Hz.
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-clk at vger.kernel.org
Cc: linux-omap at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index e024600..ce3a33f 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -75,9 +75,9 @@ unsigned long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
const struct prcm_config *ptr;
- long highest_rate;
+ unsigned long highest_rate;
- highest_rate = -EINVAL;
+ highest_rate = 0;
for (ptr = rate_table; ptr->mpu_speed; ptr++) {
if (!(ptr->flags & cpu_mask))
--
2.7.4
^ permalink raw reply related
* [PATCH v2 01/34] clk_ops: change round_rate() to return unsigned long
From: Bryan O'Donoghue @ 2018-01-01 19:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514833681-30737-1-git-send-email-pure.logic@nexus-software.ie>
Right now it is not possible to return a value larger than LONG_MAX on 32
bit systems. You can pass a rate of ULONG_MAX but can't return anything
past LONG_MAX due to the fact both the rounded_rate and negative error
codes are represented in the return value of round_rate().
Most implementations either return zero on error or don't return error
codes at all. A minority of implementations do return a negative number -
typically -EINVAL or -ENODEV.
At the higher level then callers of round_rate() typically and rightly
check for a value of <= 0.
It is possible then to convert round_rate() to an unsigned long return
value and change error code indication for the minority from -ERRORCODE to
a simple 0.
This patch is the first step in making it possible to scale round_rate past
LONG_MAX, later patches will change the previously mentioned minority of
round_rate() implementations to return zero only on error if those
implementations currently return a negative error number. Implementations
that do not return an error code of < 0 will be left as-is.
Signed-off-by: Bryan O'Donoghue <pure.logic@nexus-software.ie>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: linux-omap at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: linux-mips at linux-mips.org
Cc: linux-clk at vger.kernel.org
Cc: linux-rpi-kernel at lists.infradead.org
Cc: patches at opensource.cirrus.com
Cc: uclinux-h8-devel at lists.sourceforge.jp
Cc: linux-amlogic at lists.infradead.org
Cc: linux-arm-msm at vger.kernel.org
Cc: linux-soc at vger.kernel.org
Cc: linux-renesas-soc at vger.kernel.org
Cc: linux-rockchip at lists.infradead.org
Cc: linux-samsung-soc at vger.kernel.org
Cc: linux-tegra at vger.kernel.org
Cc: dri-devel at lists.freedesktop.org
Cc: linux-mediatek at lists.infradead.org
Cc: freedreno at lists.freedesktop.org
Cc: linux-media at vger.kernel.org
Cc: linux-rtc at vger.kernel.org
---
arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c | 4 ++--
arch/arm/mach-omap2/clock2xxx.h | 4 ++--
arch/arm/mach-vexpress/spc.c | 4 ++--
arch/mips/alchemy/common/clock.c | 2 +-
drivers/clk/at91/clk-audio-pll.c | 10 ++++++----
drivers/clk/at91/clk-h32mx.c | 5 +++--
drivers/clk/at91/clk-peripheral.c | 6 +++---
drivers/clk/at91/clk-pll.c | 2 +-
drivers/clk/at91/clk-plldiv.c | 5 +++--
drivers/clk/at91/clk-smd.c | 5 +++--
drivers/clk/at91/clk-usb.c | 5 +++--
drivers/clk/axs10x/i2s_pll_clock.c | 4 ++--
drivers/clk/axs10x/pll_clock.c | 5 +++--
drivers/clk/bcm/clk-bcm2835.c | 11 ++++++-----
drivers/clk/bcm/clk-iproc-asiu.c | 5 +++--
drivers/clk/bcm/clk-iproc-pll.c | 8 ++++----
drivers/clk/clk-axi-clkgen.c | 5 +++--
drivers/clk/clk-cdce706.c | 15 +++++++++------
drivers/clk/clk-cdce925.c | 15 +++++++++------
drivers/clk/clk-composite.c | 5 +++--
drivers/clk/clk-cs2000-cp.c | 4 ++--
drivers/clk/clk-divider.c | 5 +++--
drivers/clk/clk-fixed-factor.c | 5 +++--
drivers/clk/clk-fractional-divider.c | 4 ++--
drivers/clk/clk-gemini.c | 5 +++--
drivers/clk/clk-highbank.c | 10 ++++++----
drivers/clk/clk-hsdk-pll.c | 4 ++--
drivers/clk/clk-multiplier.c | 5 +++--
drivers/clk/clk-scpi.c | 8 ++++----
drivers/clk/clk-si514.c | 4 ++--
drivers/clk/clk-si5351.c | 15 +++++++++------
drivers/clk/clk-si570.c | 4 ++--
drivers/clk/clk-stm32f4.c | 15 +++++++++------
drivers/clk/clk-u300.c | 4 ++--
drivers/clk/clk-versaclock5.c | 16 ++++++++--------
drivers/clk/clk-vt8500.c | 9 +++++----
drivers/clk/clk-wm831x.c | 5 +++--
drivers/clk/clk-xgene.c | 9 +++++----
drivers/clk/h8300/clk-h8s2678.c | 4 ++--
drivers/clk/hisilicon/clk-hi6220-stub.c | 5 +++--
drivers/clk/hisilicon/clkdivider-hi6220.c | 5 +++--
drivers/clk/imx/clk-busy.c | 5 +++--
drivers/clk/imx/clk-cpu.c | 4 ++--
drivers/clk/imx/clk-fixup-div.c | 5 +++--
drivers/clk/imx/clk-pfd.c | 4 ++--
drivers/clk/imx/clk-pllv2.c | 4 ++--
drivers/clk/imx/clk-pllv3.c | 19 +++++++++++--------
drivers/clk/ingenic/cgu.c | 4 ++--
drivers/clk/ingenic/jz4780-cgu.c | 5 +++--
drivers/clk/mediatek/clk-pll.c | 4 ++--
drivers/clk/meson/clk-audio-divider.c | 6 +++---
drivers/clk/meson/clk-cpu.c | 5 +++--
drivers/clk/meson/clk-pll.c | 5 +++--
drivers/clk/meson/gxbb-aoclk-32k.c | 5 +++--
drivers/clk/microchip/clk-core.c | 12 ++++++------
drivers/clk/mmp/clk-frac.c | 5 +++--
drivers/clk/mvebu/clk-corediv.c | 5 +++--
drivers/clk/mvebu/clk-cpu.c | 5 +++--
drivers/clk/mvebu/dove-divider.c | 4 ++--
drivers/clk/mxs/clk-div.c | 4 ++--
drivers/clk/mxs/clk-frac.c | 4 ++--
drivers/clk/mxs/clk-ref.c | 4 ++--
drivers/clk/nxp/clk-lpc18xx-cgu.c | 5 +++--
drivers/clk/nxp/clk-lpc32xx.c | 15 +++++++++------
drivers/clk/pistachio/clk-pll.c | 4 ++--
drivers/clk/qcom/clk-alpha-pll.c | 7 ++++---
drivers/clk/qcom/clk-regmap-divider.c | 4 ++--
drivers/clk/qcom/clk-rpm.c | 4 ++--
drivers/clk/qcom/clk-smd-rpm.c | 5 +++--
drivers/clk/qcom/gcc-ipq4019.c | 5 +++--
drivers/clk/renesas/clk-div6.c | 5 +++--
drivers/clk/renesas/clk-rcar-gen2.c | 4 ++--
drivers/clk/renesas/rcar-gen2-cpg.c | 4 ++--
drivers/clk/renesas/rcar-gen3-cpg.c | 5 +++--
drivers/clk/rockchip/clk-ddr.c | 6 +++---
drivers/clk/rockchip/clk-pll.c | 5 +++--
drivers/clk/samsung/clk-cpu.c | 5 +++--
drivers/clk/samsung/clk-pll.c | 5 +++--
drivers/clk/sirf/clk-atlas7.c | 4 ++--
drivers/clk/sirf/clk-common.c | 12 ++++++------
drivers/clk/spear/clk-aux-synth.c | 4 ++--
drivers/clk/spear/clk-frac-synth.c | 4 ++--
drivers/clk/spear/clk-gpt-synth.c | 4 ++--
drivers/clk/spear/clk-vco-pll.c | 13 +++++++------
drivers/clk/spear/clk.c | 7 ++++---
drivers/clk/spear/clk.h | 7 ++++---
drivers/clk/st/clk-flexgen.c | 4 ++--
drivers/clk/st/clkgen-fsyn.c | 10 +++++-----
drivers/clk/st/clkgen-pll.c | 10 ++++++----
drivers/clk/sunxi-ng/ccu_nk.c | 4 ++--
drivers/clk/sunxi-ng/ccu_nkmp.c | 4 ++--
drivers/clk/sunxi-ng/ccu_nm.c | 4 ++--
drivers/clk/tegra/clk-audio-sync.c | 5 +++--
drivers/clk/tegra/clk-bpmp.c | 5 +++--
drivers/clk/tegra/clk-divider.c | 5 +++--
drivers/clk/tegra/clk-periph.c | 5 +++--
drivers/clk/tegra/clk-pll.c | 13 +++++++------
drivers/clk/tegra/clk-super.c | 4 ++--
drivers/clk/ti/clk-dra7-atl.c | 4 ++--
drivers/clk/ti/composite.c | 5 +++--
drivers/clk/ti/divider.c | 5 +++--
drivers/clk/ti/fapll.c | 9 +++++----
drivers/clk/ux500/clk-prcmu.c | 4 ++--
drivers/clk/versatile/clk-icst.c | 4 ++--
drivers/clk/versatile/clk-vexpress-osc.c | 5 +++--
drivers/clk/zte/clk.c | 13 +++++++------
drivers/clk/zynq/pll.c | 4 ++--
drivers/gpu/drm/imx/imx-tve.c | 5 +++--
drivers/gpu/drm/mediatek/mtk_mipi_tx.c | 5 +++--
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 5 +++--
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 5 +++--
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 5 +++--
drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c | 6 +++---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 5 +++--
drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 6 +++---
drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c | 4 ++--
drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_pll.c | 5 +++--
drivers/gpu/drm/pl111/pl111_display.c | 5 +++--
drivers/gpu/drm/sun4i/sun4i_dotclock.c | 5 +++--
drivers/media/platform/omap3isp/isp.c | 4 ++--
drivers/rtc/rtc-ac100.c | 5 +++--
drivers/rtc/rtc-ds1307.c | 5 +++--
drivers/rtc/rtc-hym8563.c | 5 +++--
drivers/rtc/rtc-m41t80.c | 5 +++--
drivers/rtc/rtc-pcf8563.c | 5 +++--
include/linux/clk-provider.h | 4 ++--
126 files changed, 419 insertions(+), 332 deletions(-)
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index b64d717..e024600 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -71,8 +71,8 @@ unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
* Some might argue L3-DDR, others ARM, others IVA. This code is simple and
* just uses the ARM rates.
*/
-long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+unsigned long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
const struct prcm_config *ptr;
long highest_rate;
diff --git a/arch/arm/mach-omap2/clock2xxx.h b/arch/arm/mach-omap2/clock2xxx.h
index a8408f9..a9b73bd 100644
--- a/arch/arm/mach-omap2/clock2xxx.h
+++ b/arch/arm/mach-omap2/clock2xxx.h
@@ -16,8 +16,8 @@ unsigned long omap2_table_mpu_recalc(struct clk_hw *clk,
unsigned long parent_rate);
int omap2_select_table_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate);
-long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate);
+unsigned long omap2_round_to_table_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate);
unsigned long omap2xxx_sys_clk_recalc(struct clk_hw *clk,
unsigned long parent_rate);
unsigned long omap2_osc_clk_recalc(struct clk_hw *clk,
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 21c0642..2d9a5a6 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -505,8 +505,8 @@ static unsigned long spc_recalc_rate(struct clk_hw *hw,
return freq * 1000;
}
-static long spc_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *parent_rate)
+static unsigned long spc_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *parent_rate)
{
struct clk_spc *spc = to_clk_spc(hw);
diff --git a/arch/mips/alchemy/common/clock.c b/arch/mips/alchemy/common/clock.c
index 6b6f685..8281e7d 100644
--- a/arch/mips/alchemy/common/clock.c
+++ b/arch/mips/alchemy/common/clock.c
@@ -204,7 +204,7 @@ static int alchemy_clk_aux_setr(struct clk_hw *hw,
return 0;
}
-static long alchemy_clk_aux_roundr(struct clk_hw *hw,
+static unsigned long alchemy_clk_aux_roundr(struct clk_hw *hw,
unsigned long rate,
unsigned long *parent_rate)
{
diff --git a/drivers/clk/at91/clk-audio-pll.c b/drivers/clk/at91/clk-audio-pll.c
index da7bafc..56227cb 100644
--- a/drivers/clk/at91/clk-audio-pll.c
+++ b/drivers/clk/at91/clk-audio-pll.c
@@ -273,8 +273,9 @@ static int clk_audio_pll_frac_determine_rate(struct clk_hw *hw,
return 0;
}
-static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_audio_pll_pad_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct clk_hw *pclk = clk_hw_get_parent(hw);
long best_rate = -EINVAL;
@@ -324,8 +325,9 @@ static long clk_audio_pll_pad_round_rate(struct clk_hw *hw, unsigned long rate,
return best_rate;
}
-static long clk_audio_pll_pmc_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_audio_pll_pmc_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct clk_hw *pclk = clk_hw_get_parent(hw);
long best_rate = -EINVAL;
diff --git a/drivers/clk/at91/clk-h32mx.c b/drivers/clk/at91/clk-h32mx.c
index e0daa4a..e74b551 100644
--- a/drivers/clk/at91/clk-h32mx.c
+++ b/drivers/clk/at91/clk-h32mx.c
@@ -45,8 +45,9 @@ static unsigned long clk_sama5d4_h32mx_recalc_rate(struct clk_hw *hw,
return parent_rate;
}
-static long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_sama5d4_h32mx_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long div;
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
index 7701183..c7b45f9 100644
--- a/drivers/clk/at91/clk-peripheral.c
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -249,9 +249,9 @@ clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
return parent_rate >> periph->div;
}
-static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
int shift = 0;
unsigned long best_rate;
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
index 7d3223f..4e7da3e 100644
--- a/drivers/clk/at91/clk-pll.c
+++ b/drivers/clk/at91/clk-pll.c
@@ -257,7 +257,7 @@ static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
return bestrate;
}
-static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+static unsigned long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct clk_pll *pll = to_clk_pll(hw);
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
index b4afaf2..25ccfc6 100644
--- a/drivers/clk/at91/clk-plldiv.c
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -38,8 +38,9 @@ static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
return parent_rate;
}
-static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_plldiv_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long div;
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
index 965c662..d096a37 100644
--- a/drivers/clk/at91/clk-smd.c
+++ b/drivers/clk/at91/clk-smd.c
@@ -43,8 +43,9 @@ static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
return parent_rate / (smddiv + 1);
}
-static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long div;
unsigned long bestrate;
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
index 791770a..e737d6e 100644
--- a/drivers/clk/at91/clk-usb.c
+++ b/drivers/clk/at91/clk-usb.c
@@ -273,8 +273,9 @@ static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
return 0;
}
-static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long at91rm9200_clk_usb_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
struct clk_hw *parent = clk_hw_get_parent(hw);
diff --git a/drivers/clk/axs10x/i2s_pll_clock.c b/drivers/clk/axs10x/i2s_pll_clock.c
index 02d3bcd..061260c 100644
--- a/drivers/clk/axs10x/i2s_pll_clock.c
+++ b/drivers/clk/axs10x/i2s_pll_clock.c
@@ -110,8 +110,8 @@ static unsigned long i2s_pll_recalc_rate(struct clk_hw *hw,
return ((parent_rate / idiv) * fbdiv) / odiv;
}
-static long i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long i2s_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct i2s_pll_clk *clk = to_i2s_pll_clk(hw);
const struct i2s_pll_cfg *pll_cfg = i2s_pll_get_cfg(*prate);
diff --git a/drivers/clk/axs10x/pll_clock.c b/drivers/clk/axs10x/pll_clock.c
index 25d8c24..27498eb 100644
--- a/drivers/clk/axs10x/pll_clock.c
+++ b/drivers/clk/axs10x/pll_clock.c
@@ -152,8 +152,9 @@ static unsigned long axs10x_pll_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long axs10x_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long axs10x_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
int i;
long best_rate;
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 44301a3..c215dc9 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -554,8 +554,9 @@ static long bcm2835_pll_rate_from_divisors(unsigned long parent_rate,
return rate >> A2W_PLL_FRAC_BITS;
}
-static long bcm2835_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long bcm2835_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct bcm2835_pll *pll = container_of(hw, struct bcm2835_pll, hw);
const struct bcm2835_pll_data *data = pll->data;
@@ -785,9 +786,9 @@ static int bcm2835_pll_divider_is_on(struct clk_hw *hw)
return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
}
-static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
return clk_divider_ops.round_rate(hw, rate, parent_rate);
}
diff --git a/drivers/clk/bcm/clk-iproc-asiu.c b/drivers/clk/bcm/clk-iproc-asiu.c
index 4360e48..ae40d08 100644
--- a/drivers/clk/bcm/clk-iproc-asiu.c
+++ b/drivers/clk/bcm/clk-iproc-asiu.c
@@ -108,8 +108,9 @@ static unsigned long iproc_asiu_clk_recalc_rate(struct clk_hw *hw,
return clk->rate;
}
-static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long iproc_asiu_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned int div;
diff --git a/drivers/clk/bcm/clk-iproc-pll.c b/drivers/clk/bcm/clk-iproc-pll.c
index 375d8dd..b5399b2 100644
--- a/drivers/clk/bcm/clk-iproc-pll.c
+++ b/drivers/clk/bcm/clk-iproc-pll.c
@@ -431,8 +431,8 @@ static unsigned long iproc_pll_recalc_rate(struct clk_hw *hw,
return clk->rate;
}
-static long iproc_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long iproc_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned i;
struct iproc_clk *clk = to_iproc_clk(hw);
@@ -535,8 +535,8 @@ static unsigned long iproc_clk_recalc_rate(struct clk_hw *hw,
return clk->rate;
}
-static long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long iproc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned int div;
diff --git a/drivers/clk/clk-axi-clkgen.c b/drivers/clk/clk-axi-clkgen.c
index 5e918e7..1da2ba4 100644
--- a/drivers/clk/clk-axi-clkgen.c
+++ b/drivers/clk/clk-axi-clkgen.c
@@ -294,8 +294,9 @@ static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
return 0;
}
-static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long axi_clkgen_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned int d, m, dout;
diff --git a/drivers/clk/clk-cdce706.c b/drivers/clk/clk-cdce706.c
index f21d909..998ad47 100644
--- a/drivers/clk/clk-cdce706.c
+++ b/drivers/clk/clk-cdce706.c
@@ -185,8 +185,9 @@ static unsigned long cdce706_pll_recalc_rate(struct clk_hw *hw,
return 0;
}
-static long cdce706_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cdce706_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct cdce706_hw_data *hwd = to_hw_data(hw);
unsigned long mul, div;
@@ -290,8 +291,9 @@ static unsigned long cdce706_divider_recalc_rate(struct clk_hw *hw,
return 0;
}
-static long cdce706_divider_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cdce706_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct cdce706_hw_data *hwd = to_hw_data(hw);
struct cdce706_dev_data *cdce = hwd->dev_data;
@@ -423,8 +425,9 @@ static unsigned long cdce706_clkout_recalc_rate(struct clk_hw *hw,
return parent_rate;
}
-static long cdce706_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cdce706_clkout_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
*parent_rate = rate;
return rate;
diff --git a/drivers/clk/clk-cdce925.c b/drivers/clk/clk-cdce925.c
index 0a7e7d5..341e744 100644
--- a/drivers/clk/clk-cdce925.c
+++ b/drivers/clk/clk-cdce925.c
@@ -142,8 +142,9 @@ static void cdce925_pll_find_rate(unsigned long rate,
}
}
-static long cdce925_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cdce925_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
u16 n, m;
@@ -434,8 +435,9 @@ static unsigned long cdce925_clk_best_parent_rate(
return rate * pdiv_best;
}
-static long cdce925_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cdce925_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long l_parent_rate = *parent_rate;
u16 divider = cdce925_calc_divider(rate, l_parent_rate);
@@ -487,8 +489,9 @@ static u16 cdce925_y1_calc_divider(unsigned long rate,
return (u16)divider;
}
-static long cdce925_clk_y1_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cdce925_clk_y1_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long l_parent_rate = *parent_rate;
u16 divider = cdce925_y1_calc_divider(rate, l_parent_rate);
diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
index 00269de..f3707c3 100644
--- a/drivers/clk/clk-composite.c
+++ b/drivers/clk/clk-composite.c
@@ -127,8 +127,9 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
}
}
-static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_composite_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *rate_ops = composite->rate_ops;
diff --git a/drivers/clk/clk-cs2000-cp.c b/drivers/clk/clk-cs2000-cp.c
index e8ea81c..d64178b 100644
--- a/drivers/clk/clk-cs2000-cp.c
+++ b/drivers/clk/clk-cs2000-cp.c
@@ -300,8 +300,8 @@ static unsigned long cs2000_recalc_rate(struct clk_hw *hw,
return cs2000_ratio_to_rate(ratio, parent_rate);
}
-static long cs2000_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cs2000_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
u32 ratio;
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 4ed516c..a26ec7c 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -345,8 +345,9 @@ long divider_round_rate_parent(struct clk_hw *hw, struct clk_hw *parent,
}
EXPORT_SYMBOL_GPL(divider_round_rate_parent);
-static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_divider *divider = to_clk_divider(hw);
int bestdiv;
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index a5d402d..40d32af 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -35,8 +35,9 @@ static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
return (unsigned long)rate;
}
-static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_factor_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index fdf625f..b7eb6a9 100644
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -70,8 +70,8 @@ static void clk_fd_general_approximation(struct clk_hw *hw, unsigned long rate,
m, n);
}
-static long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_fd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct clk_fractional_divider *fd = to_clk_fd(hw);
unsigned long m, n;
diff --git a/drivers/clk/clk-gemini.c b/drivers/clk/clk-gemini.c
index 5e66e6c..f385fc2 100644
--- a/drivers/clk/clk-gemini.c
+++ b/drivers/clk/clk-gemini.c
@@ -128,8 +128,9 @@ static unsigned long gemini_pci_recalc_rate(struct clk_hw *hw,
return 33000000;
}
-static long gemini_pci_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long gemini_pci_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
/* We support 33 and 66 MHz */
if (rate < 48000000)
diff --git a/drivers/clk/clk-highbank.c b/drivers/clk/clk-highbank.c
index 727ed8e..add1423 100644
--- a/drivers/clk/clk-highbank.c
+++ b/drivers/clk/clk-highbank.c
@@ -143,8 +143,9 @@ static void clk_pll_calc(unsigned long rate, unsigned long ref_freq,
*pdivf = divf;
}
-static long clk_pll_round_rate(struct clk_hw *hwclk, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_pll_round_rate(struct clk_hw *hwclk,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
u32 divq, divf;
unsigned long ref_freq = *parent_rate;
@@ -240,8 +241,9 @@ static unsigned long clk_periclk_recalc_rate(struct clk_hw *hwclk,
return parent_rate / div;
}
-static long clk_periclk_round_rate(struct clk_hw *hwclk, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_periclk_round_rate(struct clk_hw *hwclk,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
u32 div;
diff --git a/drivers/clk/clk-hsdk-pll.c b/drivers/clk/clk-hsdk-pll.c
index c4ee280..62c8e18 100644
--- a/drivers/clk/clk-hsdk-pll.c
+++ b/drivers/clk/clk-hsdk-pll.c
@@ -192,8 +192,8 @@ static unsigned long hsdk_pll_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long hsdk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
int i;
unsigned long best_rate;
diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
index dc037c9..b022707 100644
--- a/drivers/clk/clk-multiplier.c
+++ b/drivers/clk/clk-multiplier.c
@@ -98,8 +98,9 @@ static unsigned long __bestmult(struct clk_hw *hw, unsigned long rate,
return bestmult;
}
-static long clk_multiplier_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_multiplier_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct clk_multiplier *mult = to_clk_multiplier(hw);
unsigned long factor = __bestmult(hw, rate, parent_rate,
diff --git a/drivers/clk/clk-scpi.c b/drivers/clk/clk-scpi.c
index 2585472..303dc5e 100644
--- a/drivers/clk/clk-scpi.c
+++ b/drivers/clk/clk-scpi.c
@@ -44,8 +44,8 @@ static unsigned long scpi_clk_recalc_rate(struct clk_hw *hw,
return clk->scpi_ops->clk_get_val(clk->id);
}
-static long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long scpi_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
/*
* We can't figure out what rate it will be, so just return the
@@ -104,8 +104,8 @@ static unsigned long scpi_dvfs_recalc_rate(struct clk_hw *hw,
return opp->freq;
}
-static long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long scpi_dvfs_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct scpi_clk *clk = to_scpi_clk(hw);
diff --git a/drivers/clk/clk-si514.c b/drivers/clk/clk-si514.c
index 09b6718..8d940d0 100644
--- a/drivers/clk/clk-si514.c
+++ b/drivers/clk/clk-si514.c
@@ -209,8 +209,8 @@ static unsigned long si514_recalc_rate(struct clk_hw *hw,
return si514_calc_rate(&settings);
}
-static long si514_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long si514_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct clk_si514_muldiv settings;
int err;
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 20d9076..4a35acd 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -446,8 +446,9 @@ static unsigned long si5351_pll_recalc_rate(struct clk_hw *hw,
return (unsigned long)rate;
}
-static long si5351_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long si5351_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct si5351_hw_data *hwdata =
container_of(hw, struct si5351_hw_data, hw);
@@ -644,8 +645,9 @@ static unsigned long si5351_msynth_recalc_rate(struct clk_hw *hw,
return (unsigned long)rate;
}
-static long si5351_msynth_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long si5351_msynth_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct si5351_hw_data *hwdata =
container_of(hw, struct si5351_hw_data, hw);
@@ -1000,8 +1002,9 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
return parent_rate >> rdiv;
}
-static long si5351_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long si5351_clkout_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct si5351_hw_data *hwdata =
container_of(hw, struct si5351_hw_data, hw);
diff --git a/drivers/clk/clk-si570.c b/drivers/clk/clk-si570.c
index 646af1d..597e5d1 100644
--- a/drivers/clk/clk-si570.c
+++ b/drivers/clk/clk-si570.c
@@ -246,8 +246,8 @@ static unsigned long si570_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long si570_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long si570_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
int err;
u64 rfreq;
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 96c6b6b..19a7afa 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -354,8 +354,9 @@ static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
return parent_rate;
}
-static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_apb_mul_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_apb_mul *am = to_clk_apb_mul(hw);
unsigned long mult = 1;
@@ -570,8 +571,9 @@ static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
return parent_rate * n;
}
-static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long stm32f4_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_gate *gate = to_clk_gate(hw);
struct stm32f4_pll *pll = to_stm32f4_pll(gate);
@@ -636,8 +638,9 @@ static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
return clk_divider_ops.recalc_rate(hw, parent_rate);
}
-static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long stm32f4_pll_div_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
return clk_divider_ops.round_rate(hw, rate, prate);
}
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index 7b3e192..d988363 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -629,7 +629,7 @@ syscon_clk_recalc_rate(struct clk_hw *hw,
}
}
-static long
+static unsigned long
syscon_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
@@ -1039,7 +1039,7 @@ mclk_clk_recalc_rate(struct clk_hw *hw,
return parent_rate;
}
-static long
+static unsigned long
mclk_clk_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
diff --git a/drivers/clk/clk-versaclock5.c b/drivers/clk/clk-versaclock5.c
index decffb3..7c7b369 100644
--- a/drivers/clk/clk-versaclock5.c
+++ b/drivers/clk/clk-versaclock5.c
@@ -288,8 +288,8 @@ static unsigned long vc5_dbl_recalc_rate(struct clk_hw *hw,
return parent_rate;
}
-static long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long vc5_dbl_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
if ((*parent_rate == rate) || ((*parent_rate * 2) == rate))
return rate;
@@ -344,8 +344,8 @@ static unsigned long vc5_pfd_recalc_rate(struct clk_hw *hw,
return parent_rate / VC5_REF_DIVIDER_REF_DIV(div);
}
-static long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long vc5_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long idiv;
@@ -422,8 +422,8 @@ static unsigned long vc5_pll_recalc_rate(struct clk_hw *hw,
return (parent_rate * div_int) + ((parent_rate * div_frc) >> 24);
}
-static long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long vc5_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
u32 div_int;
@@ -500,8 +500,8 @@ static unsigned long vc5_fod_recalc_rate(struct clk_hw *hw,
return div64_u64((u64)f_in << 24ULL, ((u64)div_int << 24ULL) + div_frc);
}
-static long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long vc5_fod_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct vc5_hw_data *hwdata = container_of(hw, struct vc5_hw_data, hw);
/* VCO frequency is divided by two before entering FOD */
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index 4161a6f..43c88f6 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -137,8 +137,9 @@ static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
return parent_rate / div;
}
-static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long vt8500_dclk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_device *cdev = to_clk_device(hw);
u32 divisor;
@@ -603,8 +604,8 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
-static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_pll *pll = to_clk_pll(hw);
u32 filter, mul, div1, div2;
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index 1467695..be6f98b 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -138,8 +138,9 @@ static unsigned long wm831x_fll_recalc_rate(struct clk_hw *hw,
return 0;
}
-static long wm831x_fll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *unused)
+static unsigned long wm831x_fll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *unused)
{
int best = 0;
int i;
diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 531b030..7a93415 100644
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -286,8 +286,9 @@ static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw,
return ret;
}
-static long xgene_clk_pmd_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long xgene_clk_pmd_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct xgene_clk_pmd *fd = to_xgene_clk_pmd(hw);
u64 ret, scale;
@@ -609,8 +610,8 @@ static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return parent_rate / divider_save;
}
-static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct xgene_clk *pclk = to_xgene_clk(hw);
unsigned long parent_rate = *prate;
diff --git a/drivers/clk/h8300/clk-h8s2678.c b/drivers/clk/h8300/clk-h8s2678.c
index fc24b0b..e531612 100644
--- a/drivers/clk/h8300/clk-h8s2678.c
+++ b/drivers/clk/h8300/clk-h8s2678.c
@@ -33,8 +33,8 @@ static unsigned long pll_recalc_rate(struct clk_hw *hw,
return parent_rate * mul;
}
-static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
int i, m = -1;
long offset[3];
diff --git a/drivers/clk/hisilicon/clk-hi6220-stub.c b/drivers/clk/hisilicon/clk-hi6220-stub.c
index 329a092..1a2d64d 100644
--- a/drivers/clk/hisilicon/clk-hi6220-stub.c
+++ b/drivers/clk/hisilicon/clk-hi6220-stub.c
@@ -165,8 +165,9 @@ static int hi6220_stub_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return ret;
}
-static long hi6220_stub_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long hi6220_stub_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct hi6220_stub_clk *stub_clk = to_stub_clk(hw);
unsigned long new_rate = rate / 1000; /* kHz */
diff --git a/drivers/clk/hisilicon/clkdivider-hi6220.c b/drivers/clk/hisilicon/clkdivider-hi6220.c
index a1c1f68..5d771e9 100644
--- a/drivers/clk/hisilicon/clkdivider-hi6220.c
+++ b/drivers/clk/hisilicon/clkdivider-hi6220.c
@@ -59,8 +59,9 @@ static unsigned long hi6220_clkdiv_recalc_rate(struct clk_hw *hw,
CLK_DIVIDER_ROUND_CLOSEST);
}
-static long hi6220_clkdiv_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long hi6220_clkdiv_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct hi6220_clk_divider *dclk = to_hi6220_clk_divider(hw);
diff --git a/drivers/clk/imx/clk-busy.c b/drivers/clk/imx/clk-busy.c
index 6df3389..2ee1cd3 100644
--- a/drivers/clk/imx/clk-busy.c
+++ b/drivers/clk/imx/clk-busy.c
@@ -51,8 +51,9 @@ static unsigned long clk_busy_divider_recalc_rate(struct clk_hw *hw,
return busy->div_ops->recalc_rate(&busy->div.hw, parent_rate);
}
-static long clk_busy_divider_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_busy_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_busy_divider *busy = to_clk_busy_divider(hw);
diff --git a/drivers/clk/imx/clk-cpu.c b/drivers/clk/imx/clk-cpu.c
index 9d46eac..02db30a 100644
--- a/drivers/clk/imx/clk-cpu.c
+++ b/drivers/clk/imx/clk-cpu.c
@@ -35,8 +35,8 @@ static unsigned long clk_cpu_recalc_rate(struct clk_hw *hw,
return clk_get_rate(cpu->div);
}
-static long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_cpu *cpu = to_clk_cpu(hw);
diff --git a/drivers/clk/imx/clk-fixup-div.c b/drivers/clk/imx/clk-fixup-div.c
index ce572273..d6c98de 100644
--- a/drivers/clk/imx/clk-fixup-div.c
+++ b/drivers/clk/imx/clk-fixup-div.c
@@ -47,8 +47,9 @@ static unsigned long clk_fixup_div_recalc_rate(struct clk_hw *hw,
return fixup_div->ops->recalc_rate(&fixup_div->divider.hw, parent_rate);
}
-static long clk_fixup_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_fixup_div_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_fixup_div *fixup_div = to_clk_fixup_div(hw);
diff --git a/drivers/clk/imx/clk-pfd.c b/drivers/clk/imx/clk-pfd.c
index 04a3e78..4898469 100644
--- a/drivers/clk/imx/clk-pfd.c
+++ b/drivers/clk/imx/clk-pfd.c
@@ -67,8 +67,8 @@ static unsigned long clk_pfd_recalc_rate(struct clk_hw *hw,
return tmp;
}
-static long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pfd_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
u64 tmp = *prate;
u8 frac;
diff --git a/drivers/clk/imx/clk-pllv2.c b/drivers/clk/imx/clk-pllv2.c
index 85b5cbe..fe9c1fa 100644
--- a/drivers/clk/imx/clk-pllv2.c
+++ b/drivers/clk/imx/clk-pllv2.c
@@ -178,8 +178,8 @@ static int clk_pllv2_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
-static long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pllv2_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
u32 dp_op, dp_mfd, dp_mfn;
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c
index 9af62ee..b2d8dc5 100644
--- a/drivers/clk/imx/clk-pllv3.c
+++ b/drivers/clk/imx/clk-pllv3.c
@@ -121,8 +121,8 @@ static unsigned long clk_pllv3_recalc_rate(struct clk_hw *hw,
return (div == 1) ? parent_rate * 22 : parent_rate * 20;
}
-static long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pllv3_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
unsigned long parent_rate = *prate;
@@ -169,8 +169,9 @@ static unsigned long clk_pllv3_sys_recalc_rate(struct clk_hw *hw,
return parent_rate * div / 2;
}
-static long clk_pllv3_sys_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pllv3_sys_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
unsigned long parent_rate = *prate;
unsigned long min_rate = parent_rate * 54 / 2;
@@ -230,8 +231,9 @@ static unsigned long clk_pllv3_av_recalc_rate(struct clk_hw *hw,
return parent_rate * div + (unsigned long)temp64;
}
-static long clk_pllv3_av_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pllv3_av_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
unsigned long parent_rate = *prate;
unsigned long min_rate = parent_rate * 27;
@@ -359,8 +361,9 @@ static unsigned long clk_pllv3_vf610_recalc_rate(struct clk_hw *hw,
return clk_pllv3_vf610_mf_to_rate(parent_rate, mf);
}
-static long clk_pllv3_vf610_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pllv3_vf610_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_pllv3_vf610_mf mf = clk_pllv3_vf610_rate_to_mf(*prate, rate);
diff --git a/drivers/clk/ingenic/cgu.c b/drivers/clk/ingenic/cgu.c
index ab39363..3dee806 100644
--- a/drivers/clk/ingenic/cgu.c
+++ b/drivers/clk/ingenic/cgu.c
@@ -152,7 +152,7 @@ ingenic_pll_calc(const struct ingenic_cgu_clk_info *clk_info,
return div_u64((u64)parent_rate * m, n * od);
}
-static long
+static unsigned long
ingenic_pll_round_rate(struct clk_hw *hw, unsigned long req_rate,
unsigned long *prate)
{
@@ -357,7 +357,7 @@ ingenic_clk_calc_div(const struct ingenic_cgu_clk_info *clk_info,
return div;
}
-static long
+static unsigned long
ingenic_clk_round_rate(struct clk_hw *hw, unsigned long req_rate,
unsigned long *parent_rate)
{
diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c
index ac3585e..1f23173 100644
--- a/drivers/clk/ingenic/jz4780-cgu.c
+++ b/drivers/clk/ingenic/jz4780-cgu.c
@@ -150,8 +150,9 @@ static unsigned long jz4780_otg_phy_recalc_rate(struct clk_hw *hw,
return parent_rate;
}
-static long jz4780_otg_phy_round_rate(struct clk_hw *hw, unsigned long req_rate,
- unsigned long *parent_rate)
+static unsigned long jz4780_otg_phy_round_rate(struct clk_hw *hw,
+ unsigned long req_rate,
+ unsigned long *parent_rate)
{
if (req_rate < 15600000)
return 12000000;
diff --git a/drivers/clk/mediatek/clk-pll.c b/drivers/clk/mediatek/clk-pll.c
index f54e401..a068e55 100644
--- a/drivers/clk/mediatek/clk-pll.c
+++ b/drivers/clk/mediatek/clk-pll.c
@@ -199,8 +199,8 @@ static unsigned long mtk_pll_recalc_rate(struct clk_hw *hw,
return __mtk_pll_recalc_rate(pll, parent_rate, pcw, postdiv);
}
-static long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct mtk_clk_pll *pll = to_mtk_clk_pll(hw);
u32 pcw = 0;
diff --git a/drivers/clk/meson/clk-audio-divider.c b/drivers/clk/meson/clk-audio-divider.c
index 6c07db0..396a938 100644
--- a/drivers/clk/meson/clk-audio-divider.c
+++ b/drivers/clk/meson/clk-audio-divider.c
@@ -73,9 +73,9 @@ static unsigned long audio_divider_recalc_rate(struct clk_hw *hw,
return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
}
-static long audio_divider_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long audio_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct meson_clk_audio_divider *adiv =
to_meson_clk_audio_divider(hw);
diff --git a/drivers/clk/meson/clk-cpu.c b/drivers/clk/meson/clk-cpu.c
index f8b2b7e..83c36c6 100644
--- a/drivers/clk/meson/clk-cpu.c
+++ b/drivers/clk/meson/clk-cpu.c
@@ -54,8 +54,9 @@
#define to_meson_clk_cpu_hw(_hw) container_of(_hw, struct meson_clk_cpu, hw)
#define to_meson_clk_cpu_nb(_nb) container_of(_nb, struct meson_clk_cpu, clk_nb)
-static long meson_clk_cpu_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long meson_clk_cpu_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct meson_clk_cpu *clk_cpu = to_meson_clk_cpu_hw(hw);
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 0134155..3d5b663 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -87,8 +87,9 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
return rate_mhz * 1000000;
}
-static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long meson_clk_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct meson_clk_pll *pll = to_meson_clk_pll(hw);
const struct pll_rate_table *rate_table = pll->rate_table;
diff --git a/drivers/clk/meson/gxbb-aoclk-32k.c b/drivers/clk/meson/gxbb-aoclk-32k.c
index 491634d..0fd5b6c 100644
--- a/drivers/clk/meson/gxbb-aoclk-32k.c
+++ b/drivers/clk/meson/gxbb-aoclk-32k.c
@@ -120,8 +120,9 @@ static const struct cec_32k_freq_table *find_cec_32k_freq(unsigned long rate,
return NULL;
}
-static long aoclk_cec_32k_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long aoclk_cec_32k_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
const struct cec_32k_freq_table *freq = find_cec_32k_freq(rate,
*prate);
diff --git a/drivers/clk/microchip/clk-core.c b/drivers/clk/microchip/clk-core.c
index c3b3014..70665c8 100644
--- a/drivers/clk/microchip/clk-core.c
+++ b/drivers/clk/microchip/clk-core.c
@@ -162,8 +162,8 @@ static unsigned long pbclk_recalc_rate(struct clk_hw *hw,
return parent_rate / pbclk_read_pbdiv(pb);
}
-static long pbclk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long pbclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
return calc_best_divided_rate(rate, *parent_rate,
PB_DIV_MAX, PB_DIV_MIN);
@@ -377,8 +377,8 @@ static unsigned long roclk_recalc_rate(struct clk_hw *hw,
return roclk_calc_rate(parent_rate, rodiv, rotrim);
}
-static long roclk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long roclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
u32 rotrim, rodiv;
@@ -670,8 +670,8 @@ static unsigned long spll_clk_recalc_rate(struct clk_hw *hw,
return rate64;
}
-static long spll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long spll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct pic32_sys_pll *pll = clkhw_to_spll(hw);
diff --git a/drivers/clk/mmp/clk-frac.c b/drivers/clk/mmp/clk-frac.c
index cb43d54..af18643 100644
--- a/drivers/clk/mmp/clk-frac.c
+++ b/drivers/clk/mmp/clk-frac.c
@@ -24,8 +24,9 @@
#define to_clk_factor(hw) container_of(hw, struct mmp_clk_factor, hw)
-static long clk_factor_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate)
+static unsigned long clk_factor_round_rate(struct clk_hw *hw,
+ unsigned long drate,
+ unsigned long *prate)
{
struct mmp_clk_factor *factor = to_clk_factor(hw);
unsigned long rate = 0, prev_rate;
diff --git a/drivers/clk/mvebu/clk-corediv.c b/drivers/clk/mvebu/clk-corediv.c
index 8491979..fa47909 100644
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -136,8 +136,9 @@ static unsigned long clk_corediv_recalc_rate(struct clk_hw *hwclk,
return parent_rate / div;
}
-static long clk_corediv_round_rate(struct clk_hw *hwclk, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_corediv_round_rate(struct clk_hw *hwclk,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
/* Valid ratio are 1:4, 1:5, 1:6 and 1:8 */
u32 div;
diff --git a/drivers/clk/mvebu/clk-cpu.c b/drivers/clk/mvebu/clk-cpu.c
index 072aa38..2d9e7ab 100644
--- a/drivers/clk/mvebu/clk-cpu.c
+++ b/drivers/clk/mvebu/clk-cpu.c
@@ -58,8 +58,9 @@ static unsigned long clk_cpu_recalc_rate(struct clk_hw *hwclk,
return parent_rate / div;
}
-static long clk_cpu_round_rate(struct clk_hw *hwclk, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_cpu_round_rate(struct clk_hw *hwclk,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
/* Valid ratio are 1:1, 1:2 and 1:3 */
u32 div;
diff --git a/drivers/clk/mvebu/dove-divider.c b/drivers/clk/mvebu/dove-divider.c
index 7e35c89..234ba0a 100644
--- a/drivers/clk/mvebu/dove-divider.c
+++ b/drivers/clk/mvebu/dove-divider.c
@@ -108,8 +108,8 @@ static unsigned long dove_recalc_rate(struct clk_hw *hw, unsigned long parent)
return rate;
}
-static long dove_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent)
+static unsigned long dove_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent)
{
struct dove_clk *dc = to_dove_clk(hw);
unsigned long parent_rate = *parent;
diff --git a/drivers/clk/mxs/clk-div.c b/drivers/clk/mxs/clk-div.c
index ccebd01..60a8cc8 100644
--- a/drivers/clk/mxs/clk-div.c
+++ b/drivers/clk/mxs/clk-div.c
@@ -46,8 +46,8 @@ static unsigned long clk_div_recalc_rate(struct clk_hw *hw,
return div->ops->recalc_rate(&div->divider.hw, parent_rate);
}
-static long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_div *div = to_clk_div(hw);
diff --git a/drivers/clk/mxs/clk-frac.c b/drivers/clk/mxs/clk-frac.c
index 27b3372..f57281f 100644
--- a/drivers/clk/mxs/clk-frac.c
+++ b/drivers/clk/mxs/clk-frac.c
@@ -50,8 +50,8 @@ static unsigned long clk_frac_recalc_rate(struct clk_hw *hw,
return tmp_rate >> frac->width;
}
-static long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_frac_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_frac *frac = to_clk_frac(hw);
unsigned long parent_rate = *prate;
diff --git a/drivers/clk/mxs/clk-ref.c b/drivers/clk/mxs/clk-ref.c
index 495f99b..c3eb948 100644
--- a/drivers/clk/mxs/clk-ref.c
+++ b/drivers/clk/mxs/clk-ref.c
@@ -63,8 +63,8 @@ static unsigned long clk_ref_recalc_rate(struct clk_hw *hw,
return tmp;
}
-static long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_ref_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
unsigned long parent_rate = *prate;
u64 tmp = parent_rate;
diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index 2531174..e08bad9 100644
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -373,8 +373,9 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
return 0;
}
-static long lpc18xx_pll0_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long lpc18xx_pll0_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
unsigned long m;
diff --git a/drivers/clk/nxp/clk-lpc32xx.c b/drivers/clk/nxp/clk-lpc32xx.c
index 7b359af..81ab57d 100644
--- a/drivers/clk/nxp/clk-lpc32xx.c
+++ b/drivers/clk/nxp/clk-lpc32xx.c
@@ -583,8 +583,9 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return regmap_update_bits(clk_regmap, clk->reg, 0x1FFFF, val);
}
-static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_hclk_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
u64 m_i, o = rate, i = *parent_rate, d = (u64)rate << 6;
@@ -646,8 +647,9 @@ static long clk_hclk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
return o;
}
-static long clk_usb_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_usb_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct lpc32xx_pll_clk *clk = to_lpc32xx_pll_clk(hw);
struct clk_hw *usb_div_hw, *osc_hw;
@@ -959,8 +961,9 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
divider->flags);
}
-static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct lpc32xx_clk_div *divider = to_lpc32xx_div(hw);
unsigned int bestdiv;
diff --git a/drivers/clk/pistachio/clk-pll.c b/drivers/clk/pistachio/clk-pll.c
index 7e8daab..05fadea 100644
--- a/drivers/clk/pistachio/clk-pll.c
+++ b/drivers/clk/pistachio/clk-pll.c
@@ -142,8 +142,8 @@ pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,
return NULL;
}
-static long pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct pistachio_clk_pll *pll = to_pistachio_pll(hw);
unsigned int i;
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 47a1da3..4ddf8b31 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -411,8 +411,9 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
-static long clk_alpha_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_alpha_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
u32 l;
@@ -472,7 +473,7 @@ static const struct clk_div_table clk_alpha_div_table[] = {
{ }
};
-static long
+static unsigned long
clk_alpha_pll_postdiv_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
diff --git a/drivers/clk/qcom/clk-regmap-divider.c b/drivers/clk/qcom/clk-regmap-divider.c
index 5348491..21bf297 100644
--- a/drivers/clk/qcom/clk-regmap-divider.c
+++ b/drivers/clk/qcom/clk-regmap-divider.c
@@ -23,8 +23,8 @@ static inline struct clk_regmap_div *to_clk_regmap_div(struct clk_hw *hw)
return container_of(to_clk_regmap(hw), struct clk_regmap_div, clkr);
}
-static long div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long div_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c
index c60f61b..62c7597 100644
--- a/drivers/clk/qcom/clk-rpm.c
+++ b/drivers/clk/qcom/clk-rpm.c
@@ -354,8 +354,8 @@ static int clk_rpm_set_rate(struct clk_hw *hw,
return ret;
}
-static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
/*
* RPM handles rate rounding and we don't have a way to
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index c26d900..0ce935b 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -348,8 +348,9 @@ static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
return ret;
}
-static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_smd_rpm_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
/*
* RPM handles rate rounding and we don't have a way to
diff --git a/drivers/clk/qcom/gcc-ipq4019.c b/drivers/clk/qcom/gcc-ipq4019.c
index 46cb256..804231b 100644
--- a/drivers/clk/qcom/gcc-ipq4019.c
+++ b/drivers/clk/qcom/gcc-ipq4019.c
@@ -1258,8 +1258,9 @@ static const struct clk_fepll_vco gcc_fepll_vco = {
* It looks up the frequency table and returns the next higher frequency
* supported in hardware.
*/
-static long clk_cpu_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *p_rate)
+static unsigned long clk_cpu_div_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *p_rate)
{
struct clk_fepll *pll = to_clk_fepll(hw);
struct clk_hw *p_hw;
diff --git a/drivers/clk/renesas/clk-div6.c b/drivers/clk/renesas/clk-div6.c
index 151336d..260de92 100644
--- a/drivers/clk/renesas/clk-div6.c
+++ b/drivers/clk/renesas/clk-div6.c
@@ -105,8 +105,9 @@ static unsigned int cpg_div6_clock_calc_div(unsigned long rate,
return clamp_t(unsigned int, div, 1, 64);
}
-static long cpg_div6_clock_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cpg_div6_clock_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned int div = cpg_div6_clock_calc_div(rate, *parent_rate);
diff --git a/drivers/clk/renesas/clk-rcar-gen2.c b/drivers/clk/renesas/clk-rcar-gen2.c
index d14cbe1..485182b9 100644
--- a/drivers/clk/renesas/clk-rcar-gen2.c
+++ b/drivers/clk/renesas/clk-rcar-gen2.c
@@ -69,8 +69,8 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
return div_u64((u64)parent_rate * mult, 32);
}
-static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long prate = *parent_rate;
unsigned int mult;
diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar-gen2-cpg.c
index feb1457..594eff2 100644
--- a/drivers/clk/renesas/rcar-gen2-cpg.c
+++ b/drivers/clk/renesas/rcar-gen2-cpg.c
@@ -65,8 +65,8 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw,
return div_u64((u64)parent_rate * mult, 32);
}
-static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long prate = *parent_rate;
unsigned int mult;
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c
index 0904886..017b34f 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.c
+++ b/drivers/clk/renesas/rcar-gen3-cpg.c
@@ -175,8 +175,9 @@ static unsigned int cpg_sd_clock_calc_div(struct sd_clock *clock,
return clamp_t(unsigned int, div, clock->div_min, clock->div_max);
}
-static long cpg_sd_clock_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cpg_sd_clock_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct sd_clock *clock = to_sd_clock(hw);
unsigned int div = cpg_sd_clock_calc_div(clock, rate, *parent_rate);
diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index e807535..181053b 100644
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -64,9 +64,9 @@ rockchip_ddrclk_sip_recalc_rate(struct clk_hw *hw,
return res.a0;
}
-static long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *prate)
+static unsigned long rockchip_ddrclk_sip_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct arm_smccc_res res;
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index dd0433d..7963322 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -69,8 +69,9 @@ static const struct rockchip_pll_rate_table *rockchip_get_pll_settings(
return NULL;
}
-static long rockchip_pll_round_rate(struct clk_hw *hw,
- unsigned long drate, unsigned long *prate)
+static unsigned long rockchip_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate,
+ unsigned long *prate)
{
struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
const struct rockchip_pll_rate_table *rate_table = pll->rate_table;
diff --git a/drivers/clk/samsung/clk-cpu.c b/drivers/clk/samsung/clk-cpu.c
index d2c99d8..e94d5dd 100644
--- a/drivers/clk/samsung/clk-cpu.c
+++ b/drivers/clk/samsung/clk-cpu.c
@@ -104,8 +104,9 @@ static void wait_until_mux_stable(void __iomem *mux_reg, u32 mux_pos,
}
/* common round rate callback useable for all types of CPU clocks */
-static long exynos_cpuclk_round_rate(struct clk_hw *hw,
- unsigned long drate, unsigned long *prate)
+static unsigned long exynos_cpuclk_round_rate(struct clk_hw *hw,
+ unsigned long drate,
+ unsigned long *prate)
{
struct clk_hw *parent = clk_hw_get_parent(hw);
*prate = clk_hw_round_rate(parent, drate);
diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c
index 1c4c7a3..ebdddb0 100644
--- a/drivers/clk/samsung/clk-pll.c
+++ b/drivers/clk/samsung/clk-pll.c
@@ -48,8 +48,9 @@ static const struct samsung_pll_rate_table *samsung_get_pll_settings(
return NULL;
}
-static long samsung_pll_round_rate(struct clk_hw *hw,
- unsigned long drate, unsigned long *prate)
+static unsigned long samsung_pll_round_rate(struct clk_hw *hw,
+ unsigned long drate,
+ unsigned long *prate)
{
struct samsung_clk_pll *pll = to_clk_pll(hw);
const struct samsung_pll_rate_table *rate_table = pll->rate_table;
diff --git a/drivers/clk/sirf/clk-atlas7.c b/drivers/clk/sirf/clk-atlas7.c
index be012b4..99703d4 100644
--- a/drivers/clk/sirf/clk-atlas7.c
+++ b/drivers/clk/sirf/clk-atlas7.c
@@ -535,8 +535,8 @@ static unsigned long dto_clk_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long dto_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
u64 dividend = rate * DTO_RESL_DOUBLE;
diff --git a/drivers/clk/sirf/clk-common.c b/drivers/clk/sirf/clk-common.c
index d8f9efa..3ce6741 100644
--- a/drivers/clk/sirf/clk-common.c
+++ b/drivers/clk/sirf/clk-common.c
@@ -93,8 +93,8 @@ static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
}
}
-static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long fin, nf, nr, od;
u64 dividend;
@@ -160,8 +160,8 @@ static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
-static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
/*
* SiRF SoC has not cpu clock control,
@@ -349,8 +349,8 @@ static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
}
}
-static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long fin;
unsigned ratio, wait, hold;
diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c
index 9064104..536134d 100644
--- a/drivers/clk/spear/clk-aux-synth.c
+++ b/drivers/clk/spear/clk-aux-synth.c
@@ -52,8 +52,8 @@ static unsigned long aux_calc_rate(struct clk_hw *hw, unsigned long prate,
(rtbl[index].yscale * eq)) * 10000;
}
-static long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate)
+static unsigned long clk_aux_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *prate)
{
struct clk_aux *aux = to_clk_aux(hw);
int unused;
diff --git a/drivers/clk/spear/clk-frac-synth.c b/drivers/clk/spear/clk-frac-synth.c
index 229c96d..c9d551c 100644
--- a/drivers/clk/spear/clk-frac-synth.c
+++ b/drivers/clk/spear/clk-frac-synth.c
@@ -55,8 +55,8 @@ static unsigned long frac_calc_rate(struct clk_hw *hw, unsigned long prate,
return prate;
}
-static long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate)
+static unsigned long clk_frac_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *prate)
{
struct clk_frac *frac = to_clk_frac(hw);
int unused;
diff --git a/drivers/clk/spear/clk-gpt-synth.c b/drivers/clk/spear/clk-gpt-synth.c
index 28262f4..5cb8c69 100644
--- a/drivers/clk/spear/clk-gpt-synth.c
+++ b/drivers/clk/spear/clk-gpt-synth.c
@@ -42,8 +42,8 @@ static unsigned long gpt_calc_rate(struct clk_hw *hw, unsigned long prate,
return prate;
}
-static long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate)
+static unsigned long clk_gpt_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *prate)
{
struct clk_gpt *gpt = to_clk_gpt(hw);
int unused;
diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c
index c08dec3..d168897 100644
--- a/drivers/clk/spear/clk-vco-pll.c
+++ b/drivers/clk/spear/clk-vco-pll.c
@@ -81,8 +81,9 @@ static unsigned long pll_calc_rate(struct pll_rate_tbl *rtbl,
return rate * 10000;
}
-static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate, int *index)
+static unsigned long clk_pll_round_rate_index(struct clk_hw *hw,
+ unsigned long drate,
+ unsigned long *prate, int *index)
{
struct clk_pll *pll = to_clk_pll(hw);
unsigned long prev_rate, vco_prev_rate, rate = 0;
@@ -113,8 +114,8 @@ static long clk_pll_round_rate_index(struct clk_hw *hw, unsigned long drate,
return rate;
}
-static long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate)
+static unsigned long clk_pll_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *prate)
{
int unused;
@@ -179,8 +180,8 @@ static inline unsigned long vco_calc_rate(struct clk_hw *hw,
return pll_calc_rate(vco->rtbl, prate, index, NULL);
}
-static long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
- unsigned long *prate)
+static unsigned long clk_vco_round_rate(struct clk_hw *hw, unsigned long drate,
+ unsigned long *prate)
{
struct clk_vco *vco = to_clk_vco(hw);
int unused;
diff --git a/drivers/clk/spear/clk.c b/drivers/clk/spear/clk.c
index 157fe09..335af3b 100644
--- a/drivers/clk/spear/clk.c
+++ b/drivers/clk/spear/clk.c
@@ -13,9 +13,10 @@
#include <linux/types.h>
#include "clk.h"
-long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
- unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
- int *index)
+unsigned long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate,
+ clk_calc_rate calc_rate, u8 rtbl_cnt,
+ int *index)
{
unsigned long prev_rate, rate = 0;
diff --git a/drivers/clk/spear/clk.h b/drivers/clk/spear/clk.h
index af0e25f..c8b81f2 100644
--- a/drivers/clk/spear/clk.h
+++ b/drivers/clk/spear/clk.h
@@ -127,8 +127,9 @@ struct clk *clk_register_vco_pll(const char *vco_name, const char *pll_name,
spinlock_t *lock, struct clk **pll_clk,
struct clk **vco_gate_clk);
-long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
- unsigned long parent_rate, clk_calc_rate calc_rate, u8 rtbl_cnt,
- int *index);
+unsigned long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
+ unsigned long parent_rate,
+ clk_calc_rate calc_rate, u8 rtbl_cnt,
+ int *index);
#endif /* __SPEAR_CLK_H */
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 918ba31..682ba23 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -111,8 +111,8 @@ clk_best_div(unsigned long parent_rate, unsigned long rate)
return parent_rate / rate + ((rate > (2*(parent_rate % rate))) ? 0 : 1);
}
-static long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long flexgen_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
unsigned long div;
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 14819d9..f6a1a85 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -318,9 +318,9 @@ static int clk_fs660c32_vco_get_params(unsigned long input,
return 0;
}
-static long quadfs_pll_fs660c32_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *prate)
+static unsigned long quadfs_pll_fs660c32_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct stm_fs params;
@@ -757,8 +757,8 @@ static unsigned long quadfs_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long quadfs_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long quadfs_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct stm_fs params;
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 25bda48..64ac4e1 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -351,8 +351,9 @@ static unsigned long recalc_stm_pll3200c32(struct clk_hw *hw,
return rate;
}
-static long round_rate_stm_pll3200c32(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long round_rate_stm_pll3200c32(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct stm_pll params;
@@ -505,8 +506,9 @@ static unsigned long recalc_stm_pll4600c28(struct clk_hw *hw,
return rate;
}
-static long round_rate_stm_pll4600c28(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long round_rate_stm_pll4600c28(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct stm_pll params;
diff --git a/drivers/clk/sunxi-ng/ccu_nk.c b/drivers/clk/sunxi-ng/ccu_nk.c
index 2485bda..031f934 100644
--- a/drivers/clk/sunxi-ng/ccu_nk.c
+++ b/drivers/clk/sunxi-ng/ccu_nk.c
@@ -93,8 +93,8 @@ static unsigned long ccu_nk_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long ccu_nk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct ccu_nk *nk = hw_to_ccu_nk(hw);
struct _ccu_nk _nk;
diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c b/drivers/clk/sunxi-ng/ccu_nkmp.c
index e58c957..62fbba7 100644
--- a/drivers/clk/sunxi-ng/ccu_nkmp.c
+++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
@@ -110,8 +110,8 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
return (parent_rate * n * k >> p) / m;
}
-static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
diff --git a/drivers/clk/sunxi-ng/ccu_nm.c b/drivers/clk/sunxi-ng/ccu_nm.c
index 7620aa9..0f5beb4 100644
--- a/drivers/clk/sunxi-ng/ccu_nm.c
+++ b/drivers/clk/sunxi-ng/ccu_nm.c
@@ -101,8 +101,8 @@ static unsigned long ccu_nm_recalc_rate(struct clk_hw *hw,
return parent_rate * n / m;
}
-static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct ccu_nm *nm = hw_to_ccu_nm(hw);
struct _ccu_nm _nm;
diff --git a/drivers/clk/tegra/clk-audio-sync.c b/drivers/clk/tegra/clk-audio-sync.c
index 92d04ce..9784d58 100644
--- a/drivers/clk/tegra/clk-audio-sync.c
+++ b/drivers/clk/tegra/clk-audio-sync.c
@@ -28,8 +28,9 @@ static unsigned long clk_sync_source_recalc_rate(struct clk_hw *hw,
return sync->rate;
}
-static long clk_sync_source_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_sync_source_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct tegra_clk_sync_source *sync = to_clk_sync_source(hw);
diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c
index a896692..0c1197b 100644
--- a/drivers/clk/tegra/clk-bpmp.c
+++ b/drivers/clk/tegra/clk-bpmp.c
@@ -167,8 +167,9 @@ static unsigned long tegra_bpmp_clk_recalc_rate(struct clk_hw *hw,
return response.rate;
}
-static long tegra_bpmp_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long tegra_bpmp_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct tegra_bpmp_clk *clk = to_tegra_bpmp_clk(hw);
struct cmd_clk_round_rate_response response;
diff --git a/drivers/clk/tegra/clk-divider.c b/drivers/clk/tegra/clk-divider.c
index 16e0aee..d827943 100644
--- a/drivers/clk/tegra/clk-divider.c
+++ b/drivers/clk/tegra/clk-divider.c
@@ -84,8 +84,9 @@ static unsigned long clk_frac_div_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long clk_frac_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_frac_div_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct tegra_clk_frac_div *divider = to_clk_frac_div(hw);
int div, mul;
diff --git a/drivers/clk/tegra/clk-periph.c b/drivers/clk/tegra/clk-periph.c
index 9475c00..e68104c 100644
--- a/drivers/clk/tegra/clk-periph.c
+++ b/drivers/clk/tegra/clk-periph.c
@@ -55,8 +55,9 @@ static unsigned long clk_periph_recalc_rate(struct clk_hw *hw,
return div_ops->recalc_rate(div_hw, parent_rate);
}
-static long clk_periph_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_periph_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct tegra_clk_periph *periph = to_clk_periph(hw);
const struct clk_ops *div_ops = periph->div_ops;
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index 7c369e2..b4a7d30 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -824,8 +824,8 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return ret;
}
-static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg;
@@ -1307,8 +1307,9 @@ static int clk_pllxc_set_rate(struct clk_hw *hw, unsigned long rate,
return ret;
}
-static long clk_pll_ramp_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pll_ramp_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
struct tegra_clk_pll_freq_table cfg;
@@ -1549,8 +1550,8 @@ static unsigned long clk_pllre_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_pllre_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct tegra_clk_pll *pll = to_clk_pll(hw);
diff --git a/drivers/clk/tegra/clk-super.c b/drivers/clk/tegra/clk-super.c
index 84267cf..a8fa71e 100644
--- a/drivers/clk/tegra/clk-super.c
+++ b/drivers/clk/tegra/clk-super.c
@@ -126,8 +126,8 @@ const struct clk_ops tegra_clk_super_mux_ops = {
.set_parent = clk_super_set_parent,
};
-static long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_super_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct tegra_clk_super_mux *super = to_clk_super_mux(hw);
struct clk_hw *div_hw = &super->frac_div.hw;
diff --git a/drivers/clk/ti/clk-dra7-atl.c b/drivers/clk/ti/clk-dra7-atl.c
index 1488154..bd689ce 100644
--- a/drivers/clk/ti/clk-dra7-atl.c
+++ b/drivers/clk/ti/clk-dra7-atl.c
@@ -128,8 +128,8 @@ static unsigned long atl_clk_recalc_rate(struct clk_hw *hw,
return parent_rate / cdesc->divider;
}
-static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned divider;
diff --git a/drivers/clk/ti/composite.c b/drivers/clk/ti/composite.c
index beea894..2477cf1 100644
--- a/drivers/clk/ti/composite.c
+++ b/drivers/clk/ti/composite.c
@@ -34,8 +34,9 @@ static unsigned long ti_composite_recalc_rate(struct clk_hw *hw,
return ti_clk_divider_ops.recalc_rate(hw, parent_rate);
}
-static long ti_composite_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long ti_composite_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
return -EINVAL;
}
diff --git a/drivers/clk/ti/divider.c b/drivers/clk/ti/divider.c
index 77f93f6..a194250 100644
--- a/drivers/clk/ti/divider.c
+++ b/drivers/clk/ti/divider.c
@@ -227,8 +227,9 @@ static int ti_clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
return bestdiv;
}
-static long ti_clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long ti_clk_divider_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
int div;
div = ti_clk_divider_bestdiv(hw, rate, prate);
diff --git a/drivers/clk/ti/fapll.c b/drivers/clk/ti/fapll.c
index 071af44..2e74437 100644
--- a/drivers/clk/ti/fapll.c
+++ b/drivers/clk/ti/fapll.c
@@ -220,8 +220,8 @@ static int ti_fapll_set_div_mult(unsigned long rate,
return 0;
}
-static long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long ti_fapll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
u32 pre_div_p, mult_n;
int error;
@@ -405,8 +405,9 @@ static u32 ti_fapll_synth_set_frac_rate(struct fapll_synth *synth,
return post_div_m;
}
-static long ti_fapll_synth_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long ti_fapll_synth_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct fapll_synth *synth = to_synth(hw);
struct fapll_data *fd = synth->fd;
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 9d1f2d4..8eb7c7a 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -80,8 +80,8 @@ static unsigned long clk_prcmu_recalc_rate(struct clk_hw *hw,
return prcmu_clock_rate(clk->cg_sel);
}
-static long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long clk_prcmu_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
struct clk_prcmu *clk = to_clk_prcmu(hw);
return prcmu_round_clock_rate(clk->cg_sel, rate);
diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c
index dafe7a4..2fb3cdc 100644
--- a/drivers/clk/versatile/clk-icst.c
+++ b/drivers/clk/versatile/clk-icst.c
@@ -248,8 +248,8 @@ static unsigned long icst_recalc_rate(struct clk_hw *hw,
return icst->rate;
}
-static long icst_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long icst_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_icst *icst = to_icst(hw);
struct icst_vco vco;
diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c
index e7a868b..0d02097 100644
--- a/drivers/clk/versatile/clk-vexpress-osc.c
+++ b/drivers/clk/versatile/clk-vexpress-osc.c
@@ -39,8 +39,9 @@ static unsigned long vexpress_osc_recalc_rate(struct clk_hw *hw,
return rate;
}
-static long vexpress_osc_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long vexpress_osc_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct vexpress_osc *osc = to_vexpress_osc(hw);
diff --git a/drivers/clk/zte/clk.c b/drivers/clk/zte/clk.c
index b820317..df91842 100644
--- a/drivers/clk/zte/clk.c
+++ b/drivers/clk/zte/clk.c
@@ -78,8 +78,8 @@ static unsigned long zx_pll_recalc_rate(struct clk_hw *hw,
return zx_pll->lookup_table[idx].rate;
}
-static long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long zx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
struct clk_zx_pll *zx_pll = to_clk_zx_pll(hw);
int idx;
@@ -241,8 +241,8 @@ static unsigned long zx_audio_recalc_rate(struct clk_hw *hw,
return calc_rate(reg, parent_rate);
}
-static long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long zx_audio_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
u32 reg;
@@ -404,8 +404,9 @@ static unsigned long zx_audio_div_recalc_rate(struct clk_hw *hw,
return audio_calc_rate(zx_audio_div, reg_frac, reg_int, parent_rate);
}
-static long zx_audio_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long zx_audio_div_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct clk_zx_audio_divider *zx_audio_div = to_clk_zx_audio_div(hw);
struct zx_clk_audio_div_table divt;
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index 00d72fb..827a375 100644
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -60,8 +60,8 @@ struct zynq_pll {
* @prate: Clock frequency of parent clock
* Returns frequency closest to @rate the hardware can generate.
*/
-static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
u32 fbdiv;
diff --git a/drivers/gpu/drm/imx/imx-tve.c b/drivers/gpu/drm/imx/imx-tve.c
index bc27c26..8533bd5 100644
--- a/drivers/gpu/drm/imx/imx-tve.c
+++ b/drivers/gpu/drm/imx/imx-tve.c
@@ -402,8 +402,9 @@ static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
return 0;
}
-static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_tve_di_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
unsigned long div;
diff --git a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
index 90e9131..b7e920c 100644
--- a/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
+++ b/drivers/gpu/drm/mediatek/mtk_mipi_tx.c
@@ -289,8 +289,9 @@ static void mtk_mipi_tx_pll_unprepare(struct clk_hw *hw)
RG_DSI_MPPLL_DIV_MSK);
}
-static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
return clamp_val(rate, 50000000, 1250000000);
}
diff --git a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
index 51cb9cf..3a031bd 100644
--- a/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
+++ b/drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c
@@ -345,8 +345,9 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,
return 0;
}
-static long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long mtk_hdmi_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct mtk_hdmi_phy *hdmi_phy = to_mtk_hdmi_phy(hw);
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
index bc289f5..a8ceb80 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.c
@@ -56,8 +56,9 @@ static void dsi_pll_disable(struct msm_dsi_pll *pll)
/*
* DSI PLL Helper functions
*/
-long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
- unsigned long rate, unsigned long *parent_rate)
+unsigned long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
index f63e7ad..66e5a2a 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll.h
@@ -74,8 +74,9 @@ static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
*/
/* clock callbacks */
-long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
- unsigned long rate, unsigned long *parent_rate);
+unsigned long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate);
int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
/* misc */
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
index fe15aa6..eba0a32 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_14nm.c
@@ -701,9 +701,9 @@ static unsigned long dsi_pll_14nm_postdiv_recalc_rate(struct clk_hw *hw,
postdiv->flags);
}
-static long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *prate)
+static unsigned long dsi_pll_14nm_postdiv_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
struct dsi_pll_14nm_postdiv *postdiv = to_pll_14nm_postdiv(hw);
struct dsi_pll_14nm *pll_14nm = postdiv->pll;
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
index 4900845..f081731 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c
@@ -252,8 +252,9 @@ static unsigned int get_vco_mul_factor(unsigned long byte_clk_rate)
return 8;
}
-static long clk_bytediv_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long clk_bytediv_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
unsigned long best_parent;
unsigned int factor;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
index 0df504c..46ca7a5 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c
@@ -636,9 +636,9 @@ static int hdmi_8996_pll_prepare(struct clk_hw *hw)
return 0;
}
-static long hdmi_8996_pll_round_rate(struct clk_hw *hw,
- unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long hdmi_8996_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
if (rate < HDMI_PCLK_MIN_FREQ)
return HDMI_PCLK_MIN_FREQ;
diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
index 9959075..a0c3650 100644
--- a/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
+++ b/drivers/gpu/drm/msm/hdmi/hdmi_pll_8960.c
@@ -382,8 +382,8 @@ static unsigned long hdmi_pll_recalc_rate(struct clk_hw *hw,
return pll->pixclk;
}
-static long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
const struct pll_rate *pll_rate = find_rate(rate);
diff --git a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_pll.c b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_pll.c
index ce42459..fdbbef3 100644
--- a/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_pll.c
+++ b/drivers/gpu/drm/msm/mdp/mdp4/mdp4_lvds_pll.c
@@ -109,8 +109,9 @@ static unsigned long mpd4_lvds_pll_recalc_rate(struct clk_hw *hw,
return lvds_pll->pixclk;
}
-static long mpd4_lvds_pll_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long mpd4_lvds_pll_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
const struct pll_rate *pll_rate = find_rate(rate);
return pll_rate->rate;
diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
index 06c4bf7..d7e99d9 100644
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -338,8 +338,9 @@ static int pl111_clk_div_choose_div(struct clk_hw *hw, unsigned long rate,
return best_div;
}
-static long pl111_clk_div_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long pl111_clk_div_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
int div = pl111_clk_div_choose_div(hw, rate, prate, true);
diff --git a/drivers/gpu/drm/sun4i/sun4i_dotclock.c b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
index d401156..4bb7ae7 100644
--- a/drivers/gpu/drm/sun4i/sun4i_dotclock.c
+++ b/drivers/gpu/drm/sun4i/sun4i_dotclock.c
@@ -70,8 +70,9 @@ static unsigned long sun4i_dclk_recalc_rate(struct clk_hw *hw,
return parent_rate / val;
}
-static long sun4i_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long sun4i_dclk_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
{
unsigned long best_parent = 0;
u8 best_div = 1;
diff --git a/drivers/media/platform/omap3isp/isp.c b/drivers/media/platform/omap3isp/isp.c
index b7ff384..3461f9d 100644
--- a/drivers/media/platform/omap3isp/isp.c
+++ b/drivers/media/platform/omap3isp/isp.c
@@ -243,8 +243,8 @@ static u32 isp_xclk_calc_divider(unsigned long *rate, unsigned long parent_rate)
return divider;
}
-static long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate)
+static unsigned long isp_xclk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
{
isp_xclk_calc_divider(&rate, *parent_rate);
return rate;
diff --git a/drivers/rtc/rtc-ac100.c b/drivers/rtc/rtc-ac100.c
index 9e33618..0bd0685 100644
--- a/drivers/rtc/rtc-ac100.c
+++ b/drivers/rtc/rtc-ac100.c
@@ -146,8 +146,9 @@ static unsigned long ac100_clkout_recalc_rate(struct clk_hw *hw,
CLK_DIVIDER_POWER_OF_TWO);
}
-static long ac100_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long prate)
+static unsigned long ac100_clkout_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long prate)
{
unsigned long best_rate = 0, tmp_rate, tmp_prate;
int i;
diff --git a/drivers/rtc/rtc-ds1307.c b/drivers/rtc/rtc-ds1307.c
index 923dde9..d6fb29d 100644
--- a/drivers/rtc/rtc-ds1307.c
+++ b/drivers/rtc/rtc-ds1307.c
@@ -1166,8 +1166,9 @@ static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw,
return ds3231_clk_sqw_rates[rate_sel];
}
-static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long ds3231_clk_sqw_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
int i;
diff --git a/drivers/rtc/rtc-hym8563.c b/drivers/rtc/rtc-hym8563.c
index e5ad527..426b1f7 100644
--- a/drivers/rtc/rtc-hym8563.c
+++ b/drivers/rtc/rtc-hym8563.c
@@ -313,8 +313,9 @@ static unsigned long hym8563_clkout_recalc_rate(struct clk_hw *hw,
return clkout_rates[ret];
}
-static long hym8563_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long hym8563_clkout_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
int i;
diff --git a/drivers/rtc/rtc-m41t80.c b/drivers/rtc/rtc-m41t80.c
index c90fba3..40a89e3 100644
--- a/drivers/rtc/rtc-m41t80.c
+++ b/drivers/rtc/rtc-m41t80.c
@@ -469,8 +469,9 @@ static unsigned long m41t80_sqw_recalc_rate(struct clk_hw *hw,
return sqw_to_m41t80_data(hw)->freq;
}
-static long m41t80_sqw_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long m41t80_sqw_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
if (rate >= M41T80_SQW_MAX_FREQ)
return M41T80_SQW_MAX_FREQ;
diff --git a/drivers/rtc/rtc-pcf8563.c b/drivers/rtc/rtc-pcf8563.c
index 3efc86c..57b12cb 100644
--- a/drivers/rtc/rtc-pcf8563.c
+++ b/drivers/rtc/rtc-pcf8563.c
@@ -425,8 +425,9 @@ static unsigned long pcf8563_clkout_recalc_rate(struct clk_hw *hw,
return clkout_rates[buf];
}
-static long pcf8563_clkout_round_rate(struct clk_hw *hw, unsigned long rate,
- unsigned long *prate)
+static unsigned long pcf8563_clkout_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *prate)
{
int i;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 7c925e6..79b1d6e 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -200,8 +200,8 @@ struct clk_ops {
void (*disable_unused)(struct clk_hw *hw);
unsigned long (*recalc_rate)(struct clk_hw *hw,
unsigned long parent_rate);
- long (*round_rate)(struct clk_hw *hw, unsigned long rate,
- unsigned long *parent_rate);
+ unsigned long (*round_rate)(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate);
int (*determine_rate)(struct clk_hw *hw,
struct clk_rate_request *req);
int (*set_parent)(struct clk_hw *hw, u8 index);
--
2.7.4
^ permalink raw reply related
* [PATCH 01/33] clk_ops: change round_rate() to return unsigned long
From: kbuild test robot @ 2018-01-01 18:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514596392-22270-2-git-send-email-pure.logic@nexus-software.ie>
Hi Bryan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tegra/for-next]
[also build test WARNING on v4.15-rc6]
[cannot apply to clk/clk-next next-20171222]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Bryan-O-Donoghue/change-clk_ops-round_rate-to-scale-past-LONG_MAX/20180101-212907
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
reproduce:
# apt-get install sparse
make ARCH=x86_64 allmodconfig
make C=1 CF=-D__CHECK_ENDIAN__
sparse warnings: (new ones prefixed by >>)
vim +321 drivers/clk/clk-versaclock5.c
8c1ebe97 Marek Vasut 2017-07-09 318
8c1ebe97 Marek Vasut 2017-07-09 319 static const struct clk_ops vc5_dbl_ops = {
8c1ebe97 Marek Vasut 2017-07-09 320 .recalc_rate = vc5_dbl_recalc_rate,
8c1ebe97 Marek Vasut 2017-07-09 @321 .round_rate = vc5_dbl_round_rate,
8c1ebe97 Marek Vasut 2017-07-09 322 .set_rate = vc5_dbl_set_rate,
8c1ebe97 Marek Vasut 2017-07-09 323 };
8c1ebe97 Marek Vasut 2017-07-09 324
:::::: The code at line 321 was first introduced by commit
:::::: 8c1ebe9762670159ca982167131af63c94ff1571 clk: vc5: Add support for the input frequency doubler
:::::: TO: Marek Vasut <marek.vasut@gmail.com>
:::::: CC: Stephen Boyd <sboyd@codeaurora.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
^ permalink raw reply
* [PATCH] bcm63xx_enet: Delete two error messages for a failed memory allocation in bcm_enetsw_open()
From: SF Markus Elfring @ 2018-01-01 16:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Markus Elfring <elfring@users.sourceforge.net>
Date: Mon, 1 Jan 2018 17:30:04 +0100
Omit extra messages for a memory allocation failure in this function.
This issue was detected by using the Coccinelle software.
Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
---
drivers/net/ethernet/broadcom/bcm63xx_enet.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bcm63xx_enet.c b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
index d9346e2ac720..52a42e3058cf 100644
--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
@@ -2166,7 +2166,6 @@ static int bcm_enetsw_open(struct net_device *dev)
priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
GFP_KERNEL);
if (!priv->tx_skb) {
- dev_err(kdev, "cannot allocate rx skb queue\n");
ret = -ENOMEM;
goto out_free_tx_ring;
}
@@ -2180,7 +2179,6 @@ static int bcm_enetsw_open(struct net_device *dev)
priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
GFP_KERNEL);
if (!priv->rx_skb) {
- dev_err(kdev, "cannot allocate rx skb queue\n");
ret = -ENOMEM;
goto out_free_tx_skb;
}
--
2.15.1
^ permalink raw reply related
* [PATCH 01/33] clk_ops: change round_rate() to return unsigned long
From: kbuild test robot @ 2018-01-01 14:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514596392-22270-2-git-send-email-pure.logic@nexus-software.ie>
Hi Bryan,
I love your patch! Perhaps something to improve:
[auto build test WARNING on tegra/for-next]
[also build test WARNING on v4.15-rc6]
[cannot apply to clk/clk-next next-20171222]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Bryan-O-Donoghue/change-clk_ops-round_rate-to-scale-past-LONG_MAX/20180101-212907
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: i386-randconfig-b0-01011934 (attached as .config)
compiler: gcc-4.9 (Debian 4.9.4-2) 4.9.4
reproduce:
# save the attached .config to linux build tree
make ARCH=i386
All warnings (new ones prefixed by >>):
>> drivers/clk/clk-versaclock5.c:321:2: warning: initialization from incompatible pointer type
.round_rate = vc5_dbl_round_rate,
^
drivers/clk/clk-versaclock5.c:321:2: warning: (near initialization for 'vc5_dbl_ops.round_rate')
vim +321 drivers/clk/clk-versaclock5.c
8c1ebe97 Marek Vasut 2017-07-09 318
8c1ebe97 Marek Vasut 2017-07-09 319 static const struct clk_ops vc5_dbl_ops = {
8c1ebe97 Marek Vasut 2017-07-09 320 .recalc_rate = vc5_dbl_recalc_rate,
8c1ebe97 Marek Vasut 2017-07-09 @321 .round_rate = vc5_dbl_round_rate,
8c1ebe97 Marek Vasut 2017-07-09 322 .set_rate = vc5_dbl_set_rate,
8c1ebe97 Marek Vasut 2017-07-09 323 };
8c1ebe97 Marek Vasut 2017-07-09 324
:::::: The code at line 321 was first introduced by commit
:::::: 8c1ebe9762670159ca982167131af63c94ff1571 clk: vc5: Add support for the input frequency doubler
:::::: TO: Marek Vasut <marek.vasut@gmail.com>
:::::: CC: Stephen Boyd <sboyd@codeaurora.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH 01/33] clk_ops: change round_rate() to return unsigned long
From: kbuild test robot @ 2018-01-01 14:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514596392-22270-2-git-send-email-pure.logic@nexus-software.ie>
Hi Bryan,
I love your patch! Yet something to improve:
[auto build test ERROR on tegra/for-next]
[also build test ERROR on v4.15-rc6]
[cannot apply to clk/clk-next next-20171222]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Bryan-O-Donoghue/change-clk_ops-round_rate-to-scale-past-LONG_MAX/20180101-212907
base: https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git for-next
config: x86_64-randconfig-x016-201800 (attached as .config)
compiler: gcc-7 (Debian 7.2.0-12) 7.2.1 20171025
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
All errors (new ones prefixed by >>):
>> drivers//clk/clk-versaclock5.c:321:16: error: initialization from incompatible pointer type [-Werror=incompatible-pointer-types]
.round_rate = vc5_dbl_round_rate,
^~~~~~~~~~~~~~~~~~
drivers//clk/clk-versaclock5.c:321:16: note: (near initialization for 'vc5_dbl_ops.round_rate')
cc1: some warnings being treated as errors
vim +321 drivers//clk/clk-versaclock5.c
8c1ebe97 Marek Vasut 2017-07-09 318
8c1ebe97 Marek Vasut 2017-07-09 319 static const struct clk_ops vc5_dbl_ops = {
8c1ebe97 Marek Vasut 2017-07-09 320 .recalc_rate = vc5_dbl_recalc_rate,
8c1ebe97 Marek Vasut 2017-07-09 @321 .round_rate = vc5_dbl_round_rate,
8c1ebe97 Marek Vasut 2017-07-09 322 .set_rate = vc5_dbl_set_rate,
8c1ebe97 Marek Vasut 2017-07-09 323 };
8c1ebe97 Marek Vasut 2017-07-09 324
:::::: The code at line 321 was first introduced by commit
:::::: 8c1ebe9762670159ca982167131af63c94ff1571 clk: vc5: Add support for the input frequency doubler
:::::: TO: Marek Vasut <marek.vasut@gmail.com>
:::::: CC: Stephen Boyd <sboyd@codeaurora.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
-------------- next part --------------
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^ permalink raw reply
* [EXT] Re: [PATCH net-next 5/6] arm64: dts: marvell: mcbin: enable the fourth network interface
From: Russell King - ARM Linux @ 2018-01-01 13:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <616c2f3b0fe64184bc26d2de43442540@IL-EXCH01.marvell.com>
On Mon, Jan 01, 2018 at 10:35:25AM +0000, Stefan Chulski wrote:
>
> > -----Original Message-----
> > Hi Russell,
> >
> > Indeed. RGMII MAC behaves same way, although it shouldn't be named as 'in-
> > band' to be on par with the specifications. Anyway - this one is rather a stub for
> > being able to work with ACPI, so once the MDIO bus works there, this will be
> > out of any concerns.
>
> Hi Marcin,
>
> This is correct.
> "in-band" supported only for SGMII mode.
> IRQ link interrupt depend on "in-band"' auto negation only if "in-band"' enabled.
> But IRQ link interrupt could be triggered with "in-band", "out-band" or with specific fixed speed/duplex/flow_contol.
Hi Stefan,
How does this work in RGMII mode - is this handled by the PP2 polling
the PHY to get the speed, duplex and flow control settings?
Thanks.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [EXT] Re: [PATCH net-next 5/6] arm64: dts: marvell: mcbin: enable the fourth network interface
From: Stefan Chulski @ 2018-01-01 10:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPv3WKfn0=51CVtC8V5nWeiM+UV0BhqwFNewwRWUV3wy-9MtUg@mail.gmail.com>
> -----Original Message-----
> From: Marcin Wojtas [mailto:mw at semihalf.com]
> Sent: Monday, January 01, 2018 12:18 PM
> To: Russell King - ARM Linux <linux@armlinux.org.uk>
> Cc: Stefan Chulski <stefanc@marvell.com>; Thomas Petazzoni
> <thomas.petazzoni@free-electrons.com>; Andrew Lunn <andrew@lunn.ch>;
> Florian Fainelli <f.fainelli@gmail.com>; Yan Markman
> <ymarkman@marvell.com>; Jason Cooper <jason@lakedaemon.net>; netdev
> <netdev@vger.kernel.org>; Antoine Tenart <antoine.tenart@free-
> electrons.com>; linux-kernel at vger.kernel.org; kishon at ti.com; Nadav Haklai
> <nadavh@marvell.com>; Miqu?l Raynal <miquel.raynal@free-electrons.com>;
> Gregory Cl?ment <gregory.clement@free-electrons.com>; David S. Miller
> <davem@davemloft.net>; linux-arm-kernel at lists.infradead.org; Sebastian
> Hesselbarth <sebastian.hesselbarth@gmail.com>
> Subject: [EXT] Re: [PATCH net-next 5/6] arm64: dts: marvell: mcbin: enable the
> fourth network interface
>
> External Email
>
> ----------------------------------------------------------------------
> Hi Russell,
>
> 2017-12-30 18:31 GMT+01:00 Russell King - ARM Linux
> <linux@armlinux.org.uk>:
> > Hi Marcin,
> >
> > On Sat, Dec 30, 2017 at 05:34:23PM +0100, Marcin Wojtas wrote:
> >> Yes, I already split the series and will send first one right away. I
> >> will be followed by MDIO bus / PHY handling proposal, including the
> >> bits related to phylink. I'm looking forward to your opinion on that
> >> once sent.
> >
> > I'm looking forward to the patches. :)
> >
> >> This my understanding of how the PP2 HW works in terms of signalling
> >> the link interrupt:
> >>
> >> The full in-band management, similar to mvneta is supported only in
> >> the SGMII mode (1G, not sure how it looks like in 2.5G mode). Such
> >> handling is not yet implemented in the mvpp2.c
> >>
> >> 10G:
> >> The XGMII MAC (XLG) is capable of generating link status change
> >> interrupt upon information provided from the reconciliation layer
> >> (RS) of the interface.
> >>
> >> 2.5G/1G SGMII:
> >> Apart from the in-band management, the MAC is also capable of
> >> generating IRQ during link-status change.
> >>
> >> 1G RGMII:
> >> I was a bit surprised, but checked on my own - the link change IRQ
> >> can be generated here as well.
> >>
> >> In addition to above the clause 22 PHYs can be automatically polled
> >> via SMI bus and provide complete information about link status,
> >> speed, etc., reflecting it directly in GMAC status registers.
> >> However, this feature had to be disabled, in order not to conflict
> >> with SW PHY management of the phylib.
> >>
> >> Stefan, is above correct?
> >
> > This sounds very much like mvneta's 'managed = "in-band"' mode.
>
> Indeed. RGMII MAC behaves same way, although it shouldn't be named as 'in-
> band' to be on par with the specifications. Anyway - this one is rather a stub for
> being able to work with ACPI, so once the MDIO bus works there, this will be
> out of any concerns.
Hi Marcin,
This is correct.
"in-band" supported only for SGMII mode.
IRQ link interrupt depend on "in-band"' auto negation only if "in-band"' enabled.
But IRQ link interrupt could be triggered with "in-band", "out-band" or with specific fixed speed/duplex/flow_contol.
Best Regards.
^ permalink raw reply
* [PATCH net-next 5/6] arm64: dts: marvell: mcbin: enable the fourth network interface
From: Marcin Wojtas @ 2018-01-01 10:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171230173157.GC10595@n2100.armlinux.org.uk>
Hi Russell,
2017-12-30 18:31 GMT+01:00 Russell King - ARM Linux <linux@armlinux.org.uk>:
> Hi Marcin,
>
> On Sat, Dec 30, 2017 at 05:34:23PM +0100, Marcin Wojtas wrote:
>> Yes, I already split the series and will send first one right away. I
>> will be followed by MDIO bus / PHY handling proposal, including the
>> bits related to phylink. I'm looking forward to your opinion on that
>> once sent.
>
> I'm looking forward to the patches. :)
>
>> This my understanding of how the PP2 HW works in terms of signalling
>> the link interrupt:
>>
>> The full in-band management, similar to mvneta is supported only in
>> the SGMII mode (1G, not sure how it looks like in 2.5G mode). Such
>> handling is not yet implemented in the mvpp2.c
>>
>> 10G:
>> The XGMII MAC (XLG) is capable of generating link status change
>> interrupt upon information provided from the reconciliation layer (RS)
>> of the interface.
>>
>> 2.5G/1G SGMII:
>> Apart from the in-band management, the MAC is also capable of
>> generating IRQ during link-status change.
>>
>> 1G RGMII:
>> I was a bit surprised, but checked on my own - the link change IRQ can
>> be generated here as well.
>>
>> In addition to above the clause 22 PHYs can be automatically polled
>> via SMI bus and provide complete information about link status, speed,
>> etc., reflecting it directly in GMAC status registers. However, this
>> feature had to be disabled, in order not to conflict with SW PHY
>> management of the phylib.
>>
>> Stefan, is above correct?
>
> This sounds very much like mvneta's 'managed = "in-band"' mode.
Indeed. RGMII MAC behaves same way, although it shouldn't be named as
'in-band' to be on par with the specifications. Anyway - this one is
rather a stub for being able to work with ACPI, so once the MDIO bus
works there, this will be out of any concerns.
>
> Having done some research earlier this month on the "2.5G SGMII" I have
> a number of comments about this:
>
> 1. Beware of "SGMII" being used as a generic term for single lane serdes
> based ethernet. Marvell seem to use this for 802.3z BASE-X in their
> code, but it is not. SGMII is a modification of 802.3z BASE-X by
> Cisco. This leads to some confusion!
>
> 2. For Cisco SGMII running at 2.5G, PHYs such as those from Xilinx do not
> support the speed bits, because the speed is defined to be 2.5G. IOW,
> they do not support 250Mbps or 25Mbps speeds by data replication as is
> done with 100Mbps and 10Mbps over 1G SGMII.
>
> 3. There is also 1000BASE-X upclocked to 2.5G speeds, which mvneta and
> mvpp2 both support by appropriate configuration of the comphy. I've
> already tested this with 4.3Mbps Fiberchannel SFPs between clearfog
> and mcbin - but needing devmem2 to reconfigure the clearfog comphy.
As for 3. I tested 2.5G link on Clearfog (FreeBSD) and Armada 8040
(UEFI), so yes - the comphy is a crucial component here.
>
>> > If my guessing is correct, I have to wonder why mvpp2 invented a
>> > different way to represent this from mvneta? This makes it much more
>> > difficult to convert mvpp2 to phylink, and it also makes it difficult
>> > to add SFP support ignoring the phylink issue (since there is no phy
>> > handle there either.)
>>
>> Doesn't SFP require the fwnode handle to the sfp node? This is what I
>> understand at least from the phylink_register_sfp.
>
> Yes, internally within phylink. What I'm concerned about is the
> following disparity between mvneta and mvpp2 - I'll try to explain it
> more clearly with DT examples:
>
> 1.1. mvneta phy
> ð {
> phy = <&phy>;
> phy-mode = "whatever";
> };
> 1.2. mvneta fixed-link
> ð {
> fixed-link {
> speed = <1000>;
> full-duplex;
> };
> };
> 1.3. mvneta in-band
> ð {
> phy-mode = "sgmii";
> managed = "in-band-status";
> };
> 2.1. mvpp2 phy
> ð {
> phy = <&phy>;
> phy-mode = "whatever";
> };
> 2.2. mvpp2 fixed-link
> ð {
> fixed-link {
> speed = <1000>;
> full-duplex;
> };
> };
> 2.3. mvpp2 in-band (guess)
> ð {
> phy-mode = "sgmii";
> };
>
> In both cases, the representation for phy and fixed-link mode are the
> same, but the in-band are different. In mvneta in-band, the generic
> "managed" property must be specified as specified by
> Documentation/devicetree/bindings/net/ethernet.txt. However, for mvpp2,
> this mode is currently selected by omission of both a "phy" property and
> a "fixed-link" sub-node/property - and that goes against the description
> of the "managed" property in the ethernet.txt binding doc.
>
> Phylink won't recognise the mvpp2's style of "in-band" because phylink,
> being a piece of generic code, is written to follow the generic binding
> documentation, rather than accomodating driver's individual quirks.
>
> So, if what I think is correct (basically what I've said above) there is
> a problem converting mvpp2 to use phylink - any existing DT files that
> use the "2.3 mvpp2 in-band" method instantly break, and I think that's
> what Antoine referred to when I picked out that the previous patches
> avoided using phylink when there was no "phy" node present.
>
> However, I haven't spotted anything using the 2.3 method, but it's not
> that easy to find the lack of a property amongst the maze of .dts*
> files - trying to track down which use mvpp2 and which do not specify
> a phy or fixed-link node can't be done by grep alone due to the
> includes etc. I think the only possible way would be to build all DT
> files, then reverse them back to dts and search those for the mvpp2
> compatible strings, and then manually check each one.
>
Thanks for detailed explanation. I agree with you - for the link IRQ,
the 'managed' property should be used. IMO this change should be a
part of mvpp2 -> phylink conversion patchset.
Best regards,
Marcin
>> Anyway, once the phylink is introduced in mvpp2.c, its presence will
>> simply be detected by port->phylink pointer. In such case the link IRQ
>> will no be used. In longer perspective, link IRQ should be used only
>> by ACPI and once MDIO bus is supported in generic way in this world,
>> it could remain as the 'last resort' option.
>
> It's not though - there are SFP modules that are SGMII and we have no
> access to the PHY onboard, so the only way we know what they're doing
> is from the inband status sent as part of the SGMII in-band
> configuration. So, even when using phylink, we need the in-band
> stuff to work, and so we need those link IRQs.
>
> There's also additional complexities around Cisco SGMII and "extended"
> SGMII concerning the flow control settings - in Cisco SGMII, there
> are no bits in the 16-bit control word for communicating the flow
> control to the MAC. In extended SGMII (which appears in some Marvell
> devices) you can configure flow control to appear in the 16-bit
> control word, and in some cases, also EEE. When implemented correctly
> by the MAC, phylink supports the "Cisco" method when it knows that
> in-band AN is being used along with a PHY - it knows to read the
> settings from the MAC but combine the flow control with what has been
> read from the PHY. If this is not done, we're likely to end up with
> the link partner believing that FC is supported (eg, because the PHY
> has defaulted to advertising FC) but the local MAC having FC disabled.
>
> Note that there's another quirk as far as SGMII goes - some PHYs will
> not pass data until their "negotiation" (iow, passing and acknowledgement
> of the SGMII control word by the MAC) has completed. Disabling SGMII
> "AN" on the MAC causes some SGMII PHYs to apparently be in "link up"
> state but with no traffic flow possible in either direction. This is
> a particularly important point if using phylib - the temptation is to
> use phylib to pass the results of AN to the MAC for SGMII and disable
> AN on the MAC, but this is, in fact, wrong for the reason set out in
> this paragraph.
>
> There are bits present that allow AN bypass if it doesn't complete in
> a certain time, but that's an entirely separate issue - especially
> when there's SGMII PHYs that we have no access to!
>
> Sorting out these nuances over the life of phylink so far has been
> "interesting".
>
There's ton of quirks here and there, thanks for the efforts, which
help to sort them out.
Marcin
^ permalink raw reply
* [net-next: PATCH v2 5/5] net: mvpp2: enable ACPI support in the driver
From: Marcin Wojtas @ 2018-01-01 10:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171231192354.GB20455@lunn.ch>
HI Andrew,
2017-12-31 20:23 GMT+01:00 Andrew Lunn <andrew@lunn.ch>:
>> * Modify way of obtaining interrupts - with ACPI they are resources
>> bound to struct platform_device and it's not possible to obtain
>> them directly from the child node. Hence a formula is used, depending
>> on the port_id and number of possible CPUs.
>
> Hi Marcin
>
> I know nothing about ACPI. Is this limitation with respect to
> interrupts fundamental to ACPI, or just that nobody has implemented
> flexible interrupt support yet?
I think it's a limitation, however it would be great, if some real
ACPI expert was able to give an opinion here. I'd really prefer to
declare IRQ's in the child nodes, but it seems not possible.
>
>> * Until proper MDIO bus and PHY handling with ACPI is established in the
>> kernel, use only link interrupts feature in the driver.
>
> I think interrupts might be interesting with PHY devices, since they
> are child nodes of the MDIO device....
>
Apart from the phylink's SFP support that may require in-band
management, it's an alternative to the normal PHY handling. Once MDIO
bus + PHYs are supported for ACPI, phylib support will be used instead
of the IRQs, so there should be no problem here.
Best regards,
Marcin
^ permalink raw reply
* [net-next: PATCH v2 4/5] net: mvpp2: use device_*/fwnode_* APIs instead of of_*
From: Marcin Wojtas @ 2018-01-01 10:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171231191836.GA20455@lunn.ch>
Hi Andrew,
2017-12-31 20:18 GMT+01:00 Andrew Lunn <andrew@lunn.ch>:
> On Sun, Dec 31, 2017 at 12:58:39PM +0100, Marcin Wojtas wrote:
> Hi Marcin
>
>> Because there is no equivalent for for_each_available_child_of_node(),
>> use device_for_each_child_node() and check the port availability
>> inside the mvpp2_port_probe() routine.
>
> Could device_each_available_child_node() be added? I guess this will
> not be the last driver converted in this way, and having that macro
> will help with future ports.
>
Sure, I can add it in the next round.
Thanks,
Marcin
^ permalink raw reply
* [GIT PULL] Qualcomm Device Tree updates for 4.16
From: Andy Gross @ 2018-01-01 6:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514789609-4133-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-dts-for-4.16
for you to fetch changes up to 6e2797bd80001e7f6ffe6fa95efaa27338a43aae:
ARM: dts: msm8974-FP2: Add uSD slot nodes (2017-12-21 13:06:07 -0600)
----------------------------------------------------------------
Qualcomm Device Tree Changes for v4.16
* Add uSD slot nodes on msm8974-FP2 board
----------------------------------------------------------------
Luca Weiss (1):
ARM: dts: msm8974-FP2: Add uSD slot nodes
arch/arm/boot/dts/qcom-msm8974-fairphone-fp2.dts | 34 ++++++++++++++++++++++++
1 file changed, 34 insertions(+)
^ permalink raw reply
* [GIT PULL] Qualcomm Driver updates for 4.16
From: Andy Gross @ 2018-01-01 6:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514789609-4133-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-drivers-for-4.16
for you to fetch changes up to c01fc2275e01a91e2243d9202c04f3ed872f9de8:
soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe() (2018-01-01 00:29:09 -0600)
----------------------------------------------------------------
Qualcomm ARM Based Driver Updates for v4.16
* Fix error handling code in SMP2P probe
* Update SMP2P to use ACPS as mailbox client
* Add QMI support
* Fixups for Qualcomm SCM
* Fix licensing on rmtfs_mem
* Correct SMSM child node lookup
----------------------------------------------------------------
Bjorn Andersson (3):
soc: qcom: smp2p: Access APCS as mailbox client
soc: qcom: Introduce QMI encoder/decoder
soc: qcom: Introduce QMI helpers
Jesse Chan (1):
soc: qcom: rmtfs_mem: add missing MODULE_DESCRIPTION/AUTHOR/LICENSE
Johan Hovold (1):
soc: qcom: smsm: fix child-node lookup
Jordan Crouse (1):
firmware: qcom_scm: Add dependent headers to qcom_scm.h
Markus Elfring (1):
soc: qcom: smp2p: Use common error handling code in qcom_smp2p_probe()
Sudeep Holla (1):
firmware: qcom_scm: drop redandant of_platform_populate
.../devicetree/bindings/soc/qcom/qcom,smp2p.txt | 8 +-
drivers/firmware/qcom_scm.c | 24 -
drivers/soc/qcom/Kconfig | 10 +
drivers/soc/qcom/Makefile | 2 +
drivers/soc/qcom/qmi_encdec.c | 816 ++++++++++++++++++++
drivers/soc/qcom/qmi_interface.c | 848 +++++++++++++++++++++
drivers/soc/qcom/rmtfs_mem.c | 4 +
drivers/soc/qcom/smp2p.c | 55 +-
drivers/soc/qcom/smsm.c | 6 +-
include/linux/qcom_scm.h | 3 +
include/linux/soc/qcom/qmi.h | 271 +++++++
11 files changed, 2006 insertions(+), 41 deletions(-)
create mode 100644 drivers/soc/qcom/qmi_encdec.c
create mode 100644 drivers/soc/qcom/qmi_interface.c
create mode 100644 include/linux/soc/qcom/qmi.h
^ permalink raw reply
* [GIT PULL] Qualcomm Defconfig updates for 4.16
From: Andy Gross @ 2018-01-01 6:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514789609-4133-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-defconfig-for-4.16
for you to fetch changes up to b756f49a339aeca053ab71dd089a1868c3932f81:
ARM: qcom_defconfig: Enable Frambuffer console support (2017-12-21 13:28:31 -0600)
----------------------------------------------------------------
Qualcomm ARM Based defconfig Updates for v4.16
* Enable framebuffer, IOMMU, and DRM options
----------------------------------------------------------------
Srinivas Kandagatla (3):
ARM: qcom_defconfig: Enable DRM for 8064 display
ARM: qcom_defconfig: enable MSM IOMMU for display
ARM: qcom_defconfig: Enable Frambuffer console support
arch/arm/configs/qcom_defconfig | 3 +++
1 file changed, 3 insertions(+)
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 DT updates for 4.16
From: Andy Gross @ 2018-01-01 6:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514789609-4133-1-git-send-email-andy.gross@linaro.org>
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-for-4.16
for you to fetch changes up to 342a2922acb0f1be6b5e937427545f04c9d0a7ee:
arm64: dts: qcom: msm8916-pins: keep cdc_dmic pins in suspend mode (2017-12-31 23:50:14 -0600)
----------------------------------------------------------------
Qualcomm ARM64 Updates for v4.16
* Assorted cleanups for msm8916
* Fix IPC references for smsm
----------------------------------------------------------------
Bjorn Andersson (2):
arm64: dts: msm8916: Add missing #phy-cells
arm64: dts: msm8916: Correct ipc references for smsm
Damien Riegel (6):
arm64: dts: qcom: pm8916: fix wcd_codec indentation
arm64: dts: qcom: msm8916-pins: remove assignments to bias-disable
arm64: dts: qcom: msm8916: drop unused board-specific nodes
arm64: dts: qcom: msm8916: normalize I2C and SPI nodes
arm64: dts: qcom: msm8916-pins: move sdhc2 cd node with its siblings
arm64: dts: qcom: msm8916-pins: keep cdc_dmic pins in suspend mode
arch/arm64/boot/dts/qcom/msm8916-pins.dtsi | 88 ++++++++----------------------
arch/arm64/boot/dts/qcom/msm8916.dtsi | 29 +++++-----
arch/arm64/boot/dts/qcom/pm8916.dtsi | 82 ++++++++++++++--------------
3 files changed, 77 insertions(+), 122 deletions(-)
^ permalink raw reply
* [GIT PULL] Qualcomm ARM64 Defconfig updates for 4.16
From: Andy Gross @ 2018-01-01 6:53 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux.git tags/qcom-arm64-defconfig-for-4.16
for you to fetch changes up to d2fa1f37d21bf9729ae9ee79cb6bfc8de1f0a9a4:
arm64: defconfig: remove CONFIG_USB_QCOM_8X16_PHY (2017-12-21 13:28:11 -0600)
----------------------------------------------------------------
Qualcomm ARM64 Based defconfig Updates for v4.16
* Remove legacy QCOM config options
----------------------------------------------------------------
Alex Elder (3):
arm64: defconfig: remove CONFIG_USB_EHCI_MSM
arm64: defconfig: remove CONFIG_USB_MSM_OTG
arm64: defconfig: remove CONFIG_USB_QCOM_8X16_PHY
arch/arm64/configs/defconfig | 3 ---
1 file changed, 3 deletions(-)
^ permalink raw reply
* [PATCH v2 0/3] arm64: defconfig: remove some Qualcomm USB options
From: Andy Gross @ 2018-01-01 6:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <18cfab8f-e7c8-5881-19c7-5807ca090c8b@linaro.org>
On Thu, Nov 02, 2017 at 07:47:54AM -0500, Alex Elder wrote:
> On 11/02/2017 04:15 AM, Arnd Bergmann wrote:
> > On Tue, Oct 31, 2017 at 1:58 PM, Alex Elder <elder@linaro.org> wrote:
> >> This series deletes three config options related to USB on Qualcomm
> >> SoCs from the arm64 "defconfig". The code enabled by the options is
> >> no longer needed by any Qualcomm hardware. The driver code that
> >> corresponds to these config options is removed in a separate series.
> >>
> >> -Alex
> >>
> >> v2: Added Reviewed-by: Amit Kucheria <amit.kucheria@linaro.org>
> >
> > The patches look good. Should we apply them directly to arm-soc, or is
> > Andy going to forward them? Normally I'd wait for him to apply them,
> > but I see he has already given an Ack, so I don't know what to do here.
>
> Andy should answer, but my preference would be for you to apply them
> directly. As long as they have your attention right now you might as
> well. I suppose you could just do that and win the race with Andy...
I'll queue them up. I've been late in getting to these. Apologies for that.
Andy
^ permalink raw reply
* [PATCH v4 5/7] clk: Introduce davinci clocks
From: David Lechner @ 2018-01-01 0:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-6-git-send-email-david@lechnology.com>
On 12/31/2017 05:39 PM, David Lechner wrote:
> This introduces new drivers for arch/arm/mach-davinci. The code is based
> on the clock drivers from there and adapted to use the common clock
> framework.
>
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
...
> diff --git a/drivers/clk/davinci/da8xx-cfgchip-clk.c b/drivers/clk/davinci/da8xx-cfgchip-clk.c
> new file mode 100644
> index 0000000..780bb25
> --- /dev/null
> +++ b/drivers/clk/davinci/da8xx-cfgchip-clk.c
> @@ -0,0 +1,380 @@
...
> +static int da8xx_cfgchip_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct da8xx_cfgchip_clk_data *pdata = dev->platform_data;
> + struct da8xx_cfgchip_clk *phy_clk;
> + const char *parent_name;
> + struct clk *parent;
> + int ret;
> +
> + if (!pdata)
> + return -EINVAL;
> +
> + phy_clk = devm_kzalloc(dev, sizeof(*phy_clk), GFP_KERNEL);
> + if (!phy_clk)
> + return -ENOMEM;
> +
> + platform_set_drvdata(pdev, phy_clk);
> +
> + phy_clk->regmap = syscon_regmap_lookup_by_pdevname("syscon");
There is a mistake here. Device tree boards will fail to find "syscon".
It should be:
/* try device tree, then fall back to platform device */
phy_clk->regmap = syscon_regmap_lookup_by_compatible("ti,da830-cfgchip");
if (IS_ERR(phy_clk->regmap))
phy_clk->regmap = syscon_regmap_lookup_by_pdevname("syscon");
> + if (IS_ERR(phy_clk->regmap)) {
> + dev_err(dev, "Failed to get syscon\n");
> + return PTR_ERR(phy_clk->regmap);
> + }
^ permalink raw reply
* [PATCH v4 7/7] ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
This removes CONFIG_DAVINCI_RESET_CLOCKS. The option has been removed from
the kernel.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/configs/davinci_all_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 026154c..94d8946 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -31,7 +31,6 @@ CONFIG_MACH_MITYOMAPL138=y
CONFIG_MACH_OMAPL138_HAWKBOARD=y
CONFIG_DAVINCI_MUX_DEBUG=y
CONFIG_DAVINCI_MUX_WARNINGS=y
-CONFIG_DAVINCI_RESET_CLOCKS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
CONFIG_CMA=y
--
2.7.4
^ permalink raw reply related
* [PATCH v4 5/7] clk: Introduce davinci clocks
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
This introduces new drivers for arch/arm/mach-davinci. The code is based
on the clock drivers from there and adapted to use the common clock
framework.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/Makefile | 1 +
drivers/clk/davinci/Makefile | 3 +
drivers/clk/davinci/da8xx-cfgchip-clk.c | 380 ++++++++++++++++++++++++++++++
drivers/clk/davinci/pll.c | 333 ++++++++++++++++++++++++++
drivers/clk/davinci/psc.c | 217 +++++++++++++++++
include/linux/clk/davinci.h | 46 ++++
include/linux/platform_data/davinci_clk.h | 25 ++
7 files changed, 1005 insertions(+)
create mode 100644 drivers/clk/davinci/Makefile
create mode 100644 drivers/clk/davinci/da8xx-cfgchip-clk.c
create mode 100644 drivers/clk/davinci/pll.c
create mode 100644 drivers/clk/davinci/psc.c
create mode 100644 include/linux/clk/davinci.h
create mode 100644 include/linux/platform_data/davinci_clk.h
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f7f761b..c865fd0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
+obj-$(CONFIG_ARCH_DAVINCI) += davinci/
obj-$(CONFIG_H8300) += h8300/
obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-y += imgtec/
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
new file mode 100644
index 0000000..5efbdcd
--- /dev/null
+++ b/drivers/clk/davinci/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_PHY_DA8XX_USB) += da8xx-cfgchip-clk.o
+obj-y += pll.o
+obj-y += psc.o
\ No newline at end of file
diff --git a/drivers/clk/davinci/da8xx-cfgchip-clk.c b/drivers/clk/davinci/da8xx-cfgchip-clk.c
new file mode 100644
index 0000000..780bb25
--- /dev/null
+++ b/drivers/clk/davinci/da8xx-cfgchip-clk.c
@@ -0,0 +1,380 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * da8xx-cfgchip-clk - TI DaVinci DA8xx CFGCHIP clocks driver
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ *
+ * This driver exposes the USB PHY clocks on DA8xx/AM18xx/OMAP-L13x SoCs.
+ * The clocks consist of two muxes and a PLL. The USB 2.0 PHY mux and PLL are
+ * combined into a single clock in Linux. The USB 1.0 PHY clock just consists
+ * of a mux. These clocks are controlled through CFGCHIP2, which is accessed
+ * as a syscon regmap since it is shared with other devices.
+ */
+
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/mfd/da8xx-cfgchip.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_data/davinci_clk.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+/**
+ * da8xx_cfgchip_clk
+ * @usb0_hw: The USB 2.0 PHY clock (mux + PLL)
+ * @usb1_hw: The USB 1.1 PHY clock (mux)
+ * @usb0_clk: The USB 2.0 subsystem PSC clock
+ * @regmap: The CFGCHIP syscon regmap
+ */
+struct da8xx_cfgchip_clk {
+ struct clk_hw usb0_hw;
+ struct clk_hw usb1_hw;
+ struct clk *usb0_clk;
+ struct regmap *regmap;
+};
+
+/* The USB 2.0 PHY can use either USB_REFCLKIN or AUXCLK */
+enum usb0_phy_clk_parent {
+ USB20_PHY_CLK_PARENT_USB_REFCLKIN,
+ USB20_PHY_CLK_PARENT_PLL0_AUX,
+};
+
+/* The USB 1.1 PHY can use either the PLL output from the USB 2.0 PHY or
+ * USB_REFCLKIN
+ */
+enum usb1_phy_clk_parent {
+ USB1_PHY_CLK_PARENT_USB_REFCLKIN,
+ USB1_PHY_CLK_PARENT_USB0_PHY_PLL,
+};
+
+/* --- USB 2.0 PHY clock --- */
+
+static int usb0_phy_clk_prepare(struct clk_hw *hw)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb0_hw);
+
+ /* The USB 2.0 PSC clock is only needed temporarily during the USB 2.0
+ * PHY clock enable, but since clk_prepare() can't be called in an
+ * atomic context (i.e. in clk_enable()), we have to prepare it here.
+ */
+ return clk_prepare(clk->usb0_clk);
+}
+
+static void usb0_phy_clk_unprepare(struct clk_hw *hw)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb0_hw);
+
+ clk_unprepare(clk->usb0_clk);
+}
+
+static int usb0_phy_clk_enable(struct clk_hw *hw)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb0_hw);
+ unsigned int mask, val;
+ int ret;
+
+ /* Locking the USB 2.O PLL requires that the USB 2.O PSC is enabled
+ * temporaily. It can be turned back off once the PLL is locked.
+ */
+ clk_enable(clk->usb0_clk);
+
+ /* Turn on the USB 2.0 PHY, but just the PLL, and not OTG. The USB 1.1
+ * PHY may use the USB 2.0 PLL clock without USB 2.0 OTG being used.
+ */
+ mask = CFGCHIP2_RESET | CFGCHIP2_PHYPWRDN | CFGCHIP2_PHY_PLLON;
+ val = CFGCHIP2_PHY_PLLON;
+
+ regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val);
+ ret = regmap_read_poll_timeout(clk->regmap, CFGCHIP(2), val,
+ val & CFGCHIP2_PHYCLKGD, 0, 500000);
+
+ clk_disable(clk->usb0_clk);
+
+ return ret;
+}
+
+static void usb0_phy_clk_disable(struct clk_hw *hw)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb0_hw);
+ unsigned int val;
+
+ val = CFGCHIP2_PHYPWRDN;
+ regmap_write_bits(clk->regmap, CFGCHIP(2), val, val);
+}
+
+static unsigned long usb0_phy_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb0_hw);
+ unsigned int mask, val;
+
+ /* The parent clock rate must be one of the following */
+ mask = CFGCHIP2_REFFREQ_MASK;
+ switch (parent_rate) {
+ case 12000000:
+ val = CFGCHIP2_REFFREQ_12MHZ;
+ break;
+ case 13000000:
+ val = CFGCHIP2_REFFREQ_13MHZ;
+ break;
+ case 19200000:
+ val = CFGCHIP2_REFFREQ_19_2MHZ;
+ break;
+ case 20000000:
+ val = CFGCHIP2_REFFREQ_20MHZ;
+ break;
+ case 24000000:
+ val = CFGCHIP2_REFFREQ_24MHZ;
+ break;
+ case 26000000:
+ val = CFGCHIP2_REFFREQ_26MHZ;
+ break;
+ case 38400000:
+ val = CFGCHIP2_REFFREQ_38_4MHZ;
+ break;
+ case 40000000:
+ val = CFGCHIP2_REFFREQ_40MHZ;
+ break;
+ case 48000000:
+ val = CFGCHIP2_REFFREQ_48MHZ;
+ break;
+ default:
+ return 0;
+ }
+
+ regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val);
+
+ /* USB 2.0 PLL always supplies 48MHz */
+ return 48000000;
+}
+
+static long usb0_phy_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return 48000000;
+}
+
+static int usb0_phy_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb0_hw);
+ unsigned int mask, val;
+
+ /* Set the mux depending on the parent clock. */
+ mask = CFGCHIP2_USB2PHYCLKMUX;
+ switch (index) {
+ case USB20_PHY_CLK_PARENT_USB_REFCLKIN:
+ val = 0;
+ break;
+ case USB20_PHY_CLK_PARENT_PLL0_AUX:
+ val = CFGCHIP2_USB2PHYCLKMUX;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val);
+
+ return 0;
+}
+
+static u8 usb0_phy_clk_get_parent(struct clk_hw *hw)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb0_hw);
+ unsigned int val;
+
+ regmap_read(clk->regmap, CFGCHIP(2), &val);
+
+ if (val & CFGCHIP2_USB2PHYCLKMUX)
+ return USB20_PHY_CLK_PARENT_PLL0_AUX;
+
+ return USB20_PHY_CLK_PARENT_USB_REFCLKIN;
+}
+
+static const struct clk_ops usb0_phy_clk_ops = {
+ .prepare = usb0_phy_clk_prepare,
+ .unprepare = usb0_phy_clk_unprepare,
+ .enable = usb0_phy_clk_enable,
+ .disable = usb0_phy_clk_disable,
+ .recalc_rate = usb0_phy_clk_recalc_rate,
+ .round_rate = usb0_phy_clk_round_rate,
+ .set_parent = usb0_phy_clk_set_parent,
+ .get_parent = usb0_phy_clk_get_parent,
+};
+
+static const char * const usb0_phy_clk_parent_names[] = {
+ [USB20_PHY_CLK_PARENT_USB_REFCLKIN] = "usb_refclkin",
+ [USB20_PHY_CLK_PARENT_PLL0_AUX] = "pll0_aux_clk",
+};
+
+static const struct clk_init_data usb0_phy_clk_init_data = {
+ .name = "usb0_phy_clk",
+ .ops = &usb0_phy_clk_ops,
+ .parent_names = usb0_phy_clk_parent_names,
+ .num_parents = ARRAY_SIZE(usb0_phy_clk_parent_names),
+};
+
+/* --- USB 1.1 PHY clock --- */
+
+static int usb1_phy_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb1_hw);
+ unsigned int mask, val;
+
+ /* Set the USB 1.1 PHY clock mux based on the parent clock. */
+ mask = CFGCHIP2_USB1PHYCLKMUX;
+ switch (index) {
+ case USB1_PHY_CLK_PARENT_USB_REFCLKIN:
+ val = CFGCHIP2_USB1PHYCLKMUX;
+ break;
+ case USB1_PHY_CLK_PARENT_USB0_PHY_PLL:
+ val = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ regmap_write_bits(clk->regmap, CFGCHIP(2), mask, val);
+
+ return 0;
+}
+
+static u8 usb1_phy_clk_get_parent(struct clk_hw *hw)
+{
+ struct da8xx_cfgchip_clk *clk =
+ container_of(hw, struct da8xx_cfgchip_clk, usb1_hw);
+ unsigned int val;
+
+ regmap_read(clk->regmap, CFGCHIP(2), &val);
+
+ if (val & CFGCHIP2_USB1PHYCLKMUX)
+ return USB1_PHY_CLK_PARENT_USB_REFCLKIN;
+
+ return USB1_PHY_CLK_PARENT_USB0_PHY_PLL;
+}
+
+static const struct clk_ops usb1_phy_clk_ops = {
+ .set_parent = usb1_phy_clk_set_parent,
+ .get_parent = usb1_phy_clk_get_parent,
+};
+
+static const char * const usb1_phy_clk_parent_names[] = {
+ [USB1_PHY_CLK_PARENT_USB_REFCLKIN] = "usb_refclkin",
+ [USB1_PHY_CLK_PARENT_USB0_PHY_PLL] = "usb0_phy_clk",
+};
+
+static struct clk_init_data usb1_phy_clk_init_data = {
+ .name = "usb1_phy_clk",
+ .ops = &usb1_phy_clk_ops,
+ .parent_names = usb1_phy_clk_parent_names,
+ .num_parents = ARRAY_SIZE(usb1_phy_clk_parent_names),
+};
+
+/* --- platform driver --- */
+
+static int da8xx_cfgchip_clk_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct da8xx_cfgchip_clk_data *pdata = dev->platform_data;
+ struct da8xx_cfgchip_clk *phy_clk;
+ const char *parent_name;
+ struct clk *parent;
+ int ret;
+
+ if (!pdata)
+ return -EINVAL;
+
+ phy_clk = devm_kzalloc(dev, sizeof(*phy_clk), GFP_KERNEL);
+ if (!phy_clk)
+ return -ENOMEM;
+
+ platform_set_drvdata(pdev, phy_clk);
+
+ phy_clk->regmap = syscon_regmap_lookup_by_pdevname("syscon");
+ if (IS_ERR(phy_clk->regmap)) {
+ dev_err(dev, "Failed to get syscon\n");
+ return PTR_ERR(phy_clk->regmap);
+ }
+
+ /* USB 2.0 subsystem PSC clock - needed to lock PLL */
+ phy_clk->usb0_clk = clk_get(dev, "usb20");
+ if (IS_ERR(phy_clk->usb0_clk)) {
+ dev_err(dev, "Failed to get usb20 clock\n");
+ return PTR_ERR(phy_clk->usb0_clk);
+ }
+
+ phy_clk->usb0_hw.init = &usb0_phy_clk_init_data;
+ ret = devm_clk_hw_register(dev, &phy_clk->usb0_hw);
+ if (ret) {
+ dev_err(dev, "Failed to register usb0_phy_clk\n");
+ return ret;
+ }
+
+ phy_clk->usb1_hw.init = &usb1_phy_clk_init_data;
+ ret = devm_clk_hw_register(dev, &phy_clk->usb1_hw);
+ if (ret) {
+ dev_err(dev, "Failed to register usb1_phy_clk\n");
+ return ret;
+ }
+
+ parent_name = pdata->usb0_use_refclkin ? "usb_refclkin" : "pll0_aux";
+ parent = devm_clk_get(dev, parent_name);
+ if (IS_ERR(parent)) {
+ dev_err(dev, "Failed to get usb0 parent clock %s\n",
+ parent_name);
+ return PTR_ERR(parent);
+ }
+
+ ret = clk_set_parent(phy_clk->usb0_hw.clk, parent);
+ if (ret) {
+ dev_err(dev, "Failed to set usb0 parent clock to %s\n",
+ parent_name);
+ return ret;
+ }
+
+ clk_hw_register_clkdev(&phy_clk->usb0_hw, NULL, "da8xx-cfgchip-clk");
+
+ parent_name = pdata->usb1_use_refclkin ? "usb_refclkin" : "usb0_phy_clk";
+ parent = devm_clk_get(dev, parent_name);
+ if (IS_ERR(parent)) {
+ dev_err(dev, "Failed to get usb1 parent clock %s\n",
+ parent_name);
+ return PTR_ERR(parent);
+ }
+
+ ret = clk_set_parent(phy_clk->usb1_hw.clk, parent);
+ if (ret) {
+ dev_err(dev, "Failed to set usb1 parent clock to %s\n",
+ parent_name);
+ return ret;
+ }
+
+ clk_hw_register_clkdev(&phy_clk->usb0_hw, "usb20_phy", "da8xx-usb-phy");
+ clk_hw_register_clkdev(&phy_clk->usb1_hw, "usb11_phy", "da8xx-usb-phy");
+
+ return 0;
+}
+
+static struct platform_driver da8xx_cfgchip_clk_driver = {
+ .probe = da8xx_cfgchip_clk_probe,
+ .driver = {
+ .name = "da8xx-cfgchip-clk",
+ },
+};
+module_platform_driver(da8xx_cfgchip_clk_driver);
+
+MODULE_ALIAS("platform:da8xx-cfgchip-clk");
+MODULE_AUTHOR("David Lechner <david@lechnology.com>");
+MODULE_DESCRIPTION("TI DA8xx CFGCHIP clock driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
new file mode 100644
index 0000000..035cd91
--- /dev/null
+++ b/drivers/clk/davinci/pll.c
@@ -0,0 +1,333 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock driver for Davinci devices
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ *
+ * Based on drivers/clk/keystone/pll.c
+ * Copyright (C) 2013 Texas Instruments Inc.
+ * Murali Karicheri <m-karicheri2@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+#define REVID 0x000
+#define PLLCTL 0x100
+#define OCSEL 0x104
+#define PLLSECCTL 0x108
+#define PLLM 0x110
+#define PREDIV 0x114
+#define PLLDIV1 0x118
+#define PLLDIV2 0x11c
+#define PLLDIV3 0x120
+#define OSCDIV 0x124
+#define POSTDIV 0x128
+#define BPDIV 0x12c
+#define PLLCMD 0x138
+#define PLLSTAT 0x13c
+#define ALNCTL 0x140
+#define DCHANGE 0x144
+#define CKEN 0x148
+#define CKSTAT 0x14c
+#define SYSTAT 0x150
+#define PLLDIV4 0x160
+#define PLLDIV5 0x164
+#define PLLDIV6 0x168
+#define PLLDIV7 0x16c
+#define PLLDIV8 0x170
+#define PLLDIV9 0x174
+
+#define PLLM_MASK 0x1f
+#define PREDIV_RATIO_MASK 0x1f
+#define PLLDIV_RATIO_WIDTH 5
+#define PLLDIV_ENABLE_SHIFT 15
+#define OSCDIV_RATIO_WIDTH 5
+#define POSTDIV_RATIO_MASK 0x1f
+#define BPDIV_RATIO_SHIFT 0
+#define BPDIV_RATIO_WIDTH 5
+#define CKEN_OBSCLK_SHIFT 1
+#define CKEN_AUXEN_SHIFT 0
+
+/**
+ * struct davinci_pll_clk - Main PLL clock
+ * @hw: clk_hw for the pll
+ * @base: Base memory address
+ * @parent_rate: Saved parent rate used by some child clocks
+ */
+struct davinci_pll_clk {
+ struct clk_hw hw;
+ void __iomem *base;
+};
+
+#define to_davinci_pll_clk(_hw) container_of((_hw), struct davinci_pll_clk, hw)
+
+static unsigned long davinci_pll_clk_recalc(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
+ unsigned long rate = parent_rate;
+ u32 prediv, mult, postdiv;
+
+ prediv = readl(pll->base + PREDIV) & PREDIV_RATIO_MASK;
+ mult = readl(pll->base + PLLM) & PLLM_MASK;
+ postdiv = readl(pll->base + POSTDIV) & POSTDIV_RATIO_MASK;
+
+ rate /= prediv + 1;
+ rate *= mult + 1;
+ rate /= postdiv + 1;
+
+ return rate;
+}
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+
+#define DEBUG_REG(n) \
+{ \
+ .name = #n, \
+ .offset = n, \
+}
+
+static const struct debugfs_reg32 davinci_pll_regs[] = {
+ DEBUG_REG(REVID),
+ DEBUG_REG(PLLCTL),
+ DEBUG_REG(OCSEL),
+ DEBUG_REG(PLLSECCTL),
+ DEBUG_REG(PLLM),
+ DEBUG_REG(PREDIV),
+ DEBUG_REG(PLLDIV1),
+ DEBUG_REG(PLLDIV2),
+ DEBUG_REG(PLLDIV3),
+ DEBUG_REG(OSCDIV),
+ DEBUG_REG(POSTDIV),
+ DEBUG_REG(BPDIV),
+ DEBUG_REG(PLLCMD),
+ DEBUG_REG(PLLSTAT),
+ DEBUG_REG(ALNCTL),
+ DEBUG_REG(DCHANGE),
+ DEBUG_REG(CKEN),
+ DEBUG_REG(CKSTAT),
+ DEBUG_REG(SYSTAT),
+ DEBUG_REG(PLLDIV4),
+ DEBUG_REG(PLLDIV5),
+ DEBUG_REG(PLLDIV6),
+ DEBUG_REG(PLLDIV7),
+ DEBUG_REG(PLLDIV8),
+ DEBUG_REG(PLLDIV9),
+};
+
+static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
+ struct debugfs_regset32 *regset;
+ struct dentry *d;
+
+ regset = kzalloc(sizeof(regset), GFP_KERNEL);
+ if (!regset)
+ return -ENOMEM;
+
+ regset->regs = davinci_pll_regs;
+ regset->nregs = ARRAY_SIZE(davinci_pll_regs);
+ regset->base = pll->base;
+
+ d = debugfs_create_regset32("registers", 0400, dentry, regset);
+ if (IS_ERR(d)) {
+ kfree(regset);
+ return PTR_ERR(d);
+ }
+
+ return 0;
+}
+#else
+#define davinci_pll_debug_init NULL
+#endif
+
+static const struct clk_ops davinci_pll_clk_ops = {
+ .recalc_rate = davinci_pll_clk_recalc,
+ .debug_init = davinci_pll_debug_init,
+};
+
+/**
+ * davinci_pll_clk_register - Register a PLL clock
+ * @name: The clock name
+ * @parent_name: The parent clock name
+ * @base: The PLL's memory region
+ */
+struct clk *davinci_pll_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base)
+{
+ struct clk_init_data init;
+ struct davinci_pll_clk *pll;
+ struct clk *clk;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &davinci_pll_clk_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ pll->base = base;
+ pll->hw.init = &init;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+struct davinci_pll_aux_clk {
+ struct clk_hw hw;
+ struct davinci_pll_clk *pll;
+};
+
+/**
+ * davinci_pll_aux_clk_register - Register bypass clock (AUXCLK)
+ * @name: The clock name
+ * @parent_name: The parent clock name (usually "ref_clk" since this bypasses
+ * the PLL)
+ * @base: The PLL memory region
+ */
+struct clk *davinci_pll_aux_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base)
+{
+ return clk_register_gate(NULL, name, parent_name, 0, base + CKEN,
+ CKEN_AUXEN_SHIFT, 0, NULL);
+}
+
+/**
+ * davinci_pll_bpdiv_clk_register - Register bypass divider clock (SYSCLKBP)
+ * @name: The clock name
+ * @parent_name: The parent clock name (usually "ref_clk" since this bypasses
+ * the PLL)
+ * @base: The PLL memory region
+ */
+struct clk *davinci_pll_bpdiv_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base)
+{
+ return clk_register_divider(NULL, name, parent_name, 0, base + BPDIV,
+ BPDIV_RATIO_SHIFT, BPDIV_RATIO_WIDTH,
+ CLK_DIVIDER_READ_ONLY, NULL);
+}
+
+/**
+ * davinci_pll_obs_clk_register - Register oscillator divider clock (OBSCLK)
+ * @name: The clock name
+ * @parent_names: The parent clock names
+ * @num_parents: The number of paren clocks
+ * @base: The PLL memory region
+ * @table: A table of values cooresponding to the parent clocks (see OCSEL
+ * register in SRM for values)
+ */
+struct clk *davinci_pll_obs_clk_register(const char *name,
+ const char * const *parent_names,
+ u8 num_parents,
+ void __iomem *base,
+ u32 *table)
+{
+ struct clk_mux *mux;
+ struct clk_gate *gate;
+ struct clk_divider *divider;
+ struct clk *clk;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ mux->reg = base + OCSEL;
+ mux->table = table;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ gate->reg = base + CKEN;
+ gate->bit_idx = CKEN_OBSCLK_SHIFT;
+
+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+ if (!divider) {
+ kfree(gate);
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ divider->reg = base + OSCDIV;
+ divider->width = OSCDIV_RATIO_WIDTH;
+
+ clk = clk_register_composite(NULL, name, parent_names, num_parents,
+ &mux->hw, &clk_mux_ops,
+ ÷r->hw, &clk_divider_ops,
+ &gate->hw, &clk_gate_ops, 0);
+ if (IS_ERR(clk)) {
+ kfree(divider);
+ kfree(gate);
+ kfree(mux);
+ }
+
+ return clk;
+}
+
+/**
+ * davinci_pll_div_clk_register - Register a PLLDIV (SYSCLK) clock
+ * @name: The clock name
+ * @parent_name: The parent clock name
+ * @base: The PLL memory region
+ * @id: The id of the divider (n in PLLDIVn)
+ */
+struct clk *davinci_pll_div_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base,
+ u32 id)
+{
+ const char * const *parent_names = (parent_name ? &parent_name : NULL);
+ int num_parents = (parent_name ? 1 : 0);
+ struct clk_gate *gate;
+ struct clk_divider *divider;
+ struct clk *clk;
+ u32 reg;
+
+ /* PLLDIVn registers are not entirely consecutive */
+ if (id < 4)
+ reg = PLLDIV1 + 4 * (id - 1);
+ else
+ reg = PLLDIV4 + 4 * (id - 4);
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ gate->reg = base + reg;
+ gate->bit_idx = PLLDIV_ENABLE_SHIFT;
+
+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+ if (!divider) {
+ kfree(gate);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ divider->reg = base + reg;
+ divider->width = PLLDIV_RATIO_WIDTH;
+ divider->flags = CLK_DIVIDER_READ_ONLY;
+
+ clk = clk_register_composite(NULL, name, parent_names, num_parents,
+ NULL, NULL, ÷r->hw, &clk_divider_ops,
+ &gate->hw, &clk_gate_ops, 0);
+ if (IS_ERR(clk)) {
+ kfree(divider);
+ kfree(gate);
+ }
+
+ return clk;
+}
diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c
new file mode 100644
index 0000000..8ae85ee
--- /dev/null
+++ b/drivers/clk/davinci/psc.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock driver for DA8xx/AM17xx/AM18xx/OMAP-L13x PSC controllers
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ *
+ * Based on: drivers/clk/keystone/gate.c
+ * Copyright (C) 2013 Texas Instruments.
+ * Murali Karicheri <m-karicheri2@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * And: arch/arm/mach-davinci/psc.c
+ * Copyright (C) 2006 Texas Instruments.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+
+/* PSC register offsets */
+#define EPCPR 0x070
+#define PTCMD 0x120
+#define PTSTAT 0x128
+#define PDSTAT 0x200
+#define PDCTL 0x300
+#define MDSTAT 0x800
+#define MDCTL 0xa00
+
+/* PSC module states */
+enum davinci_psc_state {
+ PSC_STATE_SWRSTDISABLE = 0,
+ PSC_STATE_SYNCRST = 1,
+ PSC_STATE_DISABLE = 2,
+ PSC_STATE_ENABLE = 3,
+};
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_MCKOUT BIT(12)
+#define PDSTAT_STATE_MASK 0x1f
+#define MDCTL_FORCE BIT(31)
+#define MDCTL_LRESET BIT(8)
+#define PDCTL_EPCGOOD BIT(8)
+#define PDCTL_NEXT BIT(0)
+
+/**
+ * struct davinci_psc_clk - PSC clock structure
+ * @hw: clk_hw for the psc
+ * @psc_data: PSC driver specific data
+ * @lpsc: Local PSC number (module id)
+ * @pd: Power domain
+ */
+struct davinci_psc_clk {
+ struct clk_hw hw;
+ void __iomem *base;
+ u32 lpsc;
+ u32 pd;
+};
+
+#define to_davinci_psc_clk(_hw) container_of(_hw, struct davinci_psc_clk, hw)
+
+static void psc_config(struct davinci_psc_clk *psc,
+ enum davinci_psc_state next_state)
+{
+ u32 epcpr, ptcmd, pdstat, pdctl, mdstat, mdctl, ptstat;
+
+ mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc);
+ mdctl &= ~MDSTAT_STATE_MASK;
+ mdctl |= next_state;
+ /* TODO: old davinci clocks for da850 set MDCTL_FORCE bit for sata and
+ * dsp here. Is this really needed?
+ */
+ writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc);
+
+ pdstat = readl(psc->base + PDSTAT + 4 * psc->pd);
+ if ((pdstat & PDSTAT_STATE_MASK) == 0) {
+ pdctl = readl(psc->base + PDSTAT + 4 * psc->pd);
+ pdctl |= PDCTL_NEXT;
+ writel(pdctl, psc->base + PDSTAT + 4 * psc->pd);
+
+ ptcmd = BIT(psc->pd);
+ writel(ptcmd, psc->base + PTCMD);
+
+ do {
+ epcpr = __raw_readl(psc->base + EPCPR);
+ } while (!(epcpr & BIT(psc->pd)));
+
+ pdctl = __raw_readl(psc->base + PDCTL + 4 * psc->pd);
+ pdctl |= PDCTL_EPCGOOD;
+ __raw_writel(pdctl, psc->base + PDCTL + 4 * psc->pd);
+ } else {
+ ptcmd = BIT(psc->pd);
+ writel(ptcmd, psc->base + PTCMD);
+ }
+
+ do {
+ ptstat = readl(psc->base + PTSTAT);
+ } while (ptstat & BIT(psc->pd));
+
+ do {
+ mdstat = readl(psc->base + MDSTAT + 4 * psc->lpsc);
+ } while (!((mdstat & MDSTAT_STATE_MASK) == next_state));
+}
+
+static int davinci_psc_clk_enable(struct clk_hw *hw)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(hw);
+
+ psc_config(psc, PSC_STATE_ENABLE);
+
+ return 0;
+}
+
+static void davinci_psc_clk_disable(struct clk_hw *hw)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(hw);
+
+ psc_config(psc, PSC_STATE_DISABLE);
+}
+
+static int davinci_psc_clk_is_enabled(struct clk_hw *hw)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(hw);
+ u32 mdstat;
+
+ mdstat = readl(psc->base + MDSTAT + 4 * psc->lpsc);
+
+ return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
+}
+
+static const struct clk_ops davinci_psc_clk_ops = {
+ .enable = davinci_psc_clk_enable,
+ .disable = davinci_psc_clk_disable,
+ .is_enabled = davinci_psc_clk_is_enabled,
+};
+
+/**
+ * davinci_psc_clk_register - register psc clock
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @base: memory mapped register for the PSC
+ * @lpsc: local PSC number
+ * @pd: power domain
+ */
+struct clk *davinci_psc_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base,
+ u32 lpsc, u32 pd)
+{
+ struct clk_init_data init;
+ struct davinci_psc_clk *psc;
+ struct clk *clk;
+
+ psc = kzalloc(sizeof(*psc), GFP_KERNEL);
+ if (!psc)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &davinci_psc_clk_ops;
+ init.flags = 0;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+
+ psc->base = base;
+ psc->hw.init = &init;
+ psc->lpsc = lpsc;
+ psc->pd = pd;
+
+ clk = clk_register(NULL, &psc->hw);
+ if (IS_ERR(clk))
+ kfree(psc);
+
+ return clk;
+}
+
+/* FIXME: This needs to be converted to a reset controller. But, the reset
+ * framework is currently device tree only.
+ */
+
+DEFINE_SPINLOCK(davinci_psc_reset_lock);
+
+static int davinci_psc_clk_reset(struct davinci_psc_clk *psc, bool reset)
+{
+ unsigned long flags;
+ u32 mdctl;
+
+ if (IS_ERR_OR_NULL(psc))
+ return -EINVAL;
+
+ spin_lock_irqsave(&davinci_psc_reset_lock, flags);
+ mdctl = readl(psc->base + MDCTL + 4 * psc->lpsc);
+ if (reset)
+ mdctl &= ~MDCTL_LRESET;
+ else
+ mdctl |= MDCTL_LRESET;
+ writel(mdctl, psc->base + MDCTL + 4 * psc->lpsc);
+ spin_unlock_irqrestore(&davinci_psc_reset_lock, flags);
+
+ return 0;
+}
+
+int davinci_clk_reset_assert(struct clk *clk)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk));
+
+ return davinci_psc_clk_reset(psc, true);
+}
+EXPORT_SYMBOL(davinci_clk_reset_assert);
+
+int davinci_clk_reset_deassert(struct clk *clk)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk));
+
+ return davinci_psc_clk_reset(psc, false);
+}
+EXPORT_SYMBOL(davinci_clk_reset_deassert);
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
new file mode 100644
index 0000000..c5d2181
--- /dev/null
+++ b/include/linux/clk/davinci.h
@@ -0,0 +1,46 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI Davinci clocks
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+#ifndef __LINUX_CLK_DAVINCI_H__
+#define __LINUX_CLK_DAVINCI_H__
+
+#include <linux/clk-provider.h>
+#include <linux/types.h>
+
+struct clk *davinci_pll_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base);
+struct clk *davinci_pll_aux_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base);
+struct clk *davinci_pll_bpdiv_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base);
+struct clk *davinci_pll_obs_clk_register(const char *name,
+ const char * const *parent_names,
+ u8 num_parents,
+ void __iomem *base,
+ u32 *table);
+struct clk *davinci_pll_div_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base,
+ u32 id);
+struct clk *davinci_psc_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base,
+ u32 lpsc, u32 pd);
+
+/* convience macros for board declaration files */
+#define EXT_CLK(n, r) clk_register_fixed_rate(NULL, (n), NULL, 0, (r))
+#define FIX_CLK(n, p) clk_register_fixed_factor(NULL, (n), (p), 0, 1, 1)
+#define PLL_CLK davinci_pll_clk_register
+#define PLL_DIV_CLK davinci_pll_div_clk_register
+#define PLL_AUX_CLK davinci_pll_aux_clk_register
+#define PLL_BP_CLK davinci_pll_bpdiv_clk_register
+#define PLL_OBS_CLK davinci_pll_obs_clk_register
+#define PSC_CLK davinci_psc_clk_register
+
+#endif /* __LINUX_CLK_DAVINCI_H__ */
diff --git a/include/linux/platform_data/davinci_clk.h b/include/linux/platform_data/davinci_clk.h
new file mode 100644
index 0000000..7576ace
--- /dev/null
+++ b/include/linux/platform_data/davinci_clk.h
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI DaVinci Clock support
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#ifndef __PLATFORM_DATA_DAVINCI_CLK_H
+#define __PLATFORM_DATA_DAVINCI_CLK_H
+
+#include <linux/types.h>
+
+/**
+ * da8xx_cfgchip_clk_data - DA8xx CFGCHIP clock platform data
+ * @usb0_use_refclkin: when true, use USB_REFCLKIN, otherwise use AUXCLK for
+ * USB 2.0 PHY clock
+ * @usb1_use_refclkin: when true, use USB_REFCLKIN, otherwise use USB 2.0 PHY
+ * PLL for USB 1.1 PHY clock
+ */
+struct da8xx_cfgchip_clk_data {
+ bool usb0_use_refclkin;
+ bool usb1_use_refclkin;
+};
+
+#endif /* __PLATFORM_DATA_DAVINCI_CLK_H */
--
2.7.4
^ permalink raw reply related
* [PATCH v4 4/7] ARM: davinci: remove davinci_set_refclk_rate()
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
This removes the davinci_set_refclk_rate() function. This was used to set
the ref_clk rate after all clocks had been registered when clocks were
registered from a static table.
However, now it is possible to modify the rate before registering the
clocks in the first place by passing the rate as a function parameter.
The aux_clkin rate is also passed as a parameter since technically it is
also board-specific.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/mach-davinci/board-dm646x-evm.c | 12 +++++++-----
arch/arm/mach-davinci/clock.c | 32 --------------------------------
arch/arm/mach-davinci/clock.h | 1 -
arch/arm/mach-davinci/davinci.h | 2 +-
arch/arm/mach-davinci/dm646x.c | 18 +++++++-----------
5 files changed, 15 insertions(+), 50 deletions(-)
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index dafc852..c8f517b 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -716,17 +716,19 @@ static void __init evm_init_i2c(void)
}
#endif
-#define DM6467T_EVM_REF_FREQ 33000000
-
static void __init davinci_map_io(void)
{
dm646x_init();
}
+static void __init dm6467_evm_init_time(void)
+{
+ dm646x_init_time(27000000, 24000000);
+}
+
static void __init dm6467t_evm_init_time(void)
{
- dm646x_init_time();
- davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
+ dm646x_init_time(33000000, 24000000);
}
#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
@@ -800,7 +802,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
- .init_time = dm646x_init_time,
+ .init_time = dm6467_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index f82a90c..52b95e2 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -575,38 +575,6 @@ int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
}
EXPORT_SYMBOL(davinci_set_pllrate);
-/**
- * davinci_set_refclk_rate() - Set the reference clock rate
- * @rate: The new rate.
- *
- * Sets the reference clock rate to a given value. This will most likely
- * result in the entire clock tree getting updated.
- *
- * This is used to support boards which use a reference clock different
- * than that used by default in <soc>.c file. The reference clock rate
- * should be updated early in the boot process; ideally soon after the
- * clock tree has been initialized once with the default reference clock
- * rate (davinci_clk_init()).
- *
- * Returns 0 on success, error otherwise.
- */
-int davinci_set_refclk_rate(unsigned long rate)
-{
- struct clk *refclk;
-
- refclk = clk_get(NULL, "ref");
- if (IS_ERR(refclk)) {
- pr_err("%s: failed to get reference clock\n", __func__);
- return PTR_ERR(refclk);
- }
-
- clk_set_rate(refclk, rate);
-
- clk_put(refclk);
-
- return 0;
-}
-
struct clk * __init davinci_clk_init(struct clk *clk)
{
if (!clk->recalc) {
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index 66c40a2..61fcdaa 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -122,7 +122,6 @@ struct clk *davinci_clk_init(struct clk *clk);
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
unsigned int mult, unsigned int postdiv);
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
-int davinci_set_refclk_rate(unsigned long rate);
int davinci_simple_set_rate(struct clk *clk, unsigned long rate);
int davinci_clk_reset(struct clk *clk, bool reset);
void davinci_clk_enable(struct clk *clk);
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index d70f4d9..270cef8 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -111,7 +111,7 @@ int dm644x_gpio_register(void);
/* DM646x function declarations */
void dm646x_init(void);
-void dm646x_init_time(void);
+void dm646x_init_time(unsigned long ref_clk_rate, unsigned long aux_clkin_rate);
void dm646x_init_mcasp0(struct snd_platform_data *pdata);
void dm646x_init_mcasp1(struct snd_platform_data *pdata);
int dm646x_init_edma(struct edma_rsv_info *rsv);
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 0cd5d51..31dbe93 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -39,12 +39,6 @@
#define VSCLKDIS_MASK (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
BIT_MASK(8))
-/*
- * Device specific clocks
- */
-#define DM646X_REF_FREQ 27000000
-#define DM646X_AUX_FREQ 24000000
-
#define DM646X_EMAC_BASE 0x01c80000
#define DM646X_EMAC_MDIO_BASE (DM646X_EMAC_BASE + 0x4000)
#define DM646X_EMAC_CNTRL_OFFSET 0x0000
@@ -64,13 +58,11 @@ static struct pll_data pll2_data = {
static struct clk ref_clk = {
.name = "ref_clk",
- .rate = DM646X_REF_FREQ,
.set_rate = davinci_simple_set_rate,
};
static struct clk aux_clkin = {
.name = "aux_clkin",
- .rate = DM646X_AUX_FREQ,
};
static struct clk pll1_clk = {
@@ -320,10 +312,13 @@ static struct clk vpif1_clk = {
.flags = ALWAYS_ENABLED,
};
-static __init void dm646x_clk_init(void)
+static __init void dm646x_clk_init(unsigned long ref_clk_rate,
+ unsigned long aux_clkin_rate)
{
struct clk *clk;
+ ref_clk.rate = ref_clk_rate;
+ aux_clkin.rate = aux_clkin_rate;
clk = davinci_clk_init(&ref_clk);
clk_register_clkdev(clk, "ref", NULL);
clk = davinci_clk_init(&aux_clkin);
@@ -998,9 +993,10 @@ void __init dm646x_init(void)
davinci_map_sysmod();
}
-void __init dm646x_init_time(void)
+void __init dm646x_init_time(unsigned long ref_clk_rate,
+ unsigned long aux_clkin_rate)
{
- dm646x_clk_init();
+ dm646x_clk_init(ref_clk_rate, aux_clkin_rate);
davinci_timer_init();
}
--
2.7.4
^ permalink raw reply related
* [PATCH v4 3/7] ARM: davinci: fix duplicate clocks
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
There are a number of clocks that were duplicated because they are used by
more than one device. It is no longer necessary to do this since we are
explicitly calling clk_register_clkdev() for each clock. In da830.c, some
clocks were using the same LPSC, which would cause problems with reference
counting, so these are combinded into one clock each. In da850.c the
duplicate clocks had already been fixed by creating dummy child clocks, so
these clocks are removed.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/mach-davinci/da830.c | 65 ++++++--------------------------------
arch/arm/mach-davinci/da850.c | 72 ------------------------------------------
arch/arm/mach-davinci/dm365.c | 1 -
arch/arm/mach-davinci/dm644x.c | 3 --
arch/arm/mach-davinci/dm646x.c | 1 -
5 files changed, 9 insertions(+), 133 deletions(-)
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 73c48f5..b0e54a1 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -213,57 +213,22 @@ static struct clk spi1_clk = {
.gpsc = 1,
};
-static struct clk ecap0_clk = {
- .name = "ecap0",
+static struct clk ecap_clk = {
+ .name = "ecap",
.parent = &pll0_sysclk2,
.lpsc = DA8XX_LPSC1_ECAP,
.gpsc = 1,
};
-static struct clk ecap1_clk = {
- .name = "ecap1",
- .parent = &pll0_sysclk2,
- .lpsc = DA8XX_LPSC1_ECAP,
- .gpsc = 1,
-};
-
-static struct clk ecap2_clk = {
- .name = "ecap2",
- .parent = &pll0_sysclk2,
- .lpsc = DA8XX_LPSC1_ECAP,
- .gpsc = 1,
-};
-
-static struct clk pwm0_clk = {
- .name = "pwm0",
- .parent = &pll0_sysclk2,
- .lpsc = DA8XX_LPSC1_PWM,
- .gpsc = 1,
-};
-
-static struct clk pwm1_clk = {
- .name = "pwm1",
+static struct clk pwm_clk = {
+ .name = "pwm",
.parent = &pll0_sysclk2,
.lpsc = DA8XX_LPSC1_PWM,
.gpsc = 1,
};
-static struct clk pwm2_clk = {
- .name = "pwm2",
- .parent = &pll0_sysclk2,
- .lpsc = DA8XX_LPSC1_PWM,
- .gpsc = 1,
-};
-
-static struct clk eqep0_clk = {
- .name = "eqep0",
- .parent = &pll0_sysclk2,
- .lpsc = DA830_LPSC1_EQEP,
- .gpsc = 1,
-};
-
-static struct clk eqep1_clk = {
- .name = "eqep1",
+static struct clk eqep_clk = {
+ .name = "eqep",
.parent = &pll0_sysclk2,
.lpsc = DA830_LPSC1_EQEP,
.gpsc = 1,
@@ -304,11 +269,6 @@ static struct clk usb20_clk = {
.gpsc = 1,
};
-static struct clk cppi41_clk = {
- .name = "cppi41",
- .parent = &usb20_clk,
-};
-
static struct clk aemif_clk = {
.name = "aemif",
.parent = &pll0_sysclk3,
@@ -434,21 +394,16 @@ static __init void da830_clk_init(void)
clk_register_clkdev(clk, NULL, "spi_davinci.0");
clk = davinci_clk_init(&spi1_clk);
clk_register_clkdev(clk, NULL, "spi_davinci.1");
- clk = davinci_clk_init(&ecap0_clk);
+ clk = davinci_clk_init(&ecap_clk);
clk_register_clkdev(clk, "ecap0", NULL);
- clk = davinci_clk_init(&ecap1_clk);
clk_register_clkdev(clk, "ecap1", NULL);
- clk = davinci_clk_init(&ecap2_clk);
clk_register_clkdev(clk, "ecap2", NULL);
- clk = davinci_clk_init(&pwm0_clk);
+ clk = davinci_clk_init(&pwm_clk);
clk_register_clkdev(clk, "pwm0", NULL);
- clk = davinci_clk_init(&pwm1_clk);
clk_register_clkdev(clk, "pwm1", NULL);
- clk = davinci_clk_init(&pwm2_clk);
clk_register_clkdev(clk, "pwm2", NULL);
- clk = davinci_clk_init(&eqep0_clk);
+ clk = davinci_clk_init(&eqep_clk);
clk_register_clkdev(clk, NULL, "eqep.0");
- clk = davinci_clk_init(&eqep1_clk);
clk_register_clkdev(clk, NULL, "eqep.1");
clk = davinci_clk_init(&lcdc_clk);
clk_register_clkdev(clk, "fck", "da8xx_lcdc.0");
@@ -460,7 +415,6 @@ static __init void da830_clk_init(void)
clk_register_clkdev(clk, NULL, "davinci-mcasp.2");
clk = davinci_clk_init(&usb20_clk);
clk_register_clkdev(clk, "usb20", "musb-da8xx");
- clk = davinci_clk_init(&cppi41_clk);
clk_register_clkdev(clk, NULL, "cppi41-dmaengine");
clk = davinci_clk_init(&aemif_clk);
clk_register_clkdev(clk, "aemif", NULL);
@@ -470,7 +424,6 @@ static __init void da830_clk_init(void)
clk_register_clkdev(clk, "secu_mgr", NULL);
clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, NULL, "davinci_emac.1");
- clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, "fck", "davinci_mdio.0");
clk = davinci_clk_init(&gpio_clk);
clk_register_clkdev(clk, "gpio", NULL);
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index eaa05ac..0975edb 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -319,16 +319,6 @@ static struct clk emac_clk = {
.gpsc = 1,
};
-/*
- * In order to avoid adding the emac_clk to the clock lookup table twice (and
- * screwing up the linked list in the process) create a separate clock for
- * mdio inheriting the rate from emac_clk.
- */
-static struct clk mdio_clk = {
- .name = "mdio",
- .parent = &emac_clk,
-};
-
static struct clk mcasp_clk = {
.name = "mcasp",
.parent = &async3_clk,
@@ -377,16 +367,6 @@ static struct clk aemif_clk = {
.flags = ALWAYS_ENABLED,
};
-/*
- * In order to avoid adding the aemif_clk to the clock lookup table twice (and
- * screwing up the linked list in the process) create a separate clock for
- * nand inheriting the rate from aemif_clk.
- */
-static struct clk aemif_nand_clk = {
- .name = "nand",
- .parent = &aemif_clk,
-};
-
static struct clk usb11_clk = {
.name = "usb11",
.parent = &pll0_sysclk4,
@@ -401,11 +381,6 @@ static struct clk usb20_clk = {
.gpsc = 1,
};
-static struct clk cppi41_clk = {
- .name = "cppi41",
- .parent = &usb20_clk,
-};
-
static struct clk spi0_clk = {
.name = "spi0",
.parent = &pll0_sysclk2,
@@ -449,16 +424,6 @@ static struct clk ehrpwm_clk = {
.gpsc = 1,
};
-static struct clk ehrpwm0_clk = {
- .name = "ehrpwm0",
- .parent = &ehrpwm_clk,
-};
-
-static struct clk ehrpwm1_clk = {
- .name = "ehrpwm1",
- .parent = &ehrpwm_clk,
-};
-
#define DA8XX_EHRPWM_TBCLKSYNC BIT(12)
static void ehrpwm_tblck_enable(struct clk *clk)
@@ -486,15 +451,6 @@ static struct clk ehrpwm_tbclk = {
.clk_disable = ehrpwm_tblck_disable,
};
-static struct clk ehrpwm0_tbclk = {
- .name = "ehrpwm0_tbclk",
- .parent = &ehrpwm_tbclk,
-};
-
-static struct clk ehrpwm1_tbclk = {
- .name = "ehrpwm1_tbclk",
- .parent = &ehrpwm_tbclk,
-};
static struct clk ecap_clk = {
.name = "ecap",
@@ -503,21 +459,6 @@ static struct clk ecap_clk = {
.gpsc = 1,
};
-static struct clk ecap0_clk = {
- .name = "ecap0_clk",
- .parent = &ecap_clk,
-};
-
-static struct clk ecap1_clk = {
- .name = "ecap1_clk",
- .parent = &ecap_clk,
-};
-
-static struct clk ecap2_clk = {
- .name = "ecap2_clk",
- .parent = &ecap_clk,
-};
-
static __init void da850_clk_init(void)
{
struct clk *clk;
@@ -592,7 +533,6 @@ static __init void da850_clk_init(void)
clk_register_clkdev(clk, "rmii", NULL);
clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, NULL, "davinci_emac.1");
- clk = davinci_clk_init(&mdio_clk);
clk_register_clkdev(clk, "fck", "davinci_mdio.0");
clk = davinci_clk_init(&mcasp_clk);
clk_register_clkdev(clk, NULL, "davinci-mcasp.0");
@@ -608,13 +548,11 @@ static __init void da850_clk_init(void)
clk_register_clkdev(clk, NULL, "da830-mmc.1");
clk = davinci_clk_init(&aemif_clk);
clk_register_clkdev(clk, NULL, "ti-aemif");
- clk = davinci_clk_init(&aemif_nand_clk);
clk_register_clkdev(clk, "aemif", "davinci-nand.0");
clk = davinci_clk_init(&usb11_clk);
clk_register_clkdev(clk, "usb11", "ohci-da8xx");
clk = davinci_clk_init(&usb20_clk);
clk_register_clkdev(clk, "usb20", "musb-da8xx");
- clk = davinci_clk_init(&cppi41_clk);
clk_register_clkdev(clk, NULL, "cppi41-dmaengine");
clk = davinci_clk_init(&spi0_clk);
clk_register_clkdev(clk, NULL, "spi_davinci.0");
@@ -627,24 +565,14 @@ static __init void da850_clk_init(void)
clk = davinci_clk_init(&dsp_clk);
clk_register_clkdev(clk, NULL, "davinci-rproc.0");
clk = davinci_clk_init(&ehrpwm_clk);
- clk_register_clkdev(clk, NULL, NULL);
- clk = davinci_clk_init(&ehrpwm0_clk);
clk_register_clkdev(clk, "fck", "ehrpwm.0");
- clk = davinci_clk_init(&ehrpwm1_clk);
clk_register_clkdev(clk, "fck", "ehrpwm.1");
clk = davinci_clk_init(&ehrpwm_tbclk);
- clk_register_clkdev(clk, NULL, NULL);
- clk = davinci_clk_init(&ehrpwm0_tbclk);
clk_register_clkdev(clk, "tbclk", "ehrpwm.0");
- clk = davinci_clk_init(&ehrpwm1_tbclk);
clk_register_clkdev(clk, "tbclk", "ehrpwm.1");
clk = davinci_clk_init(&ecap_clk);
- clk_register_clkdev(clk, NULL, NULL);
- clk = davinci_clk_init(&ecap0_clk);
clk_register_clkdev(clk, "fck", "ecap.0");
- clk = davinci_clk_init(&ecap1_clk);
clk_register_clkdev(clk, "fck", "ecap.1");
- clk = davinci_clk_init(&ecap2_clk);
clk_register_clkdev(clk, "fck", "ecap.2");
}
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0cf4ab4..430fb1e 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -533,7 +533,6 @@ static __init void dm365_clk_init(void)
clk_register_clkdev(clk, "usb", NULL);
clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, NULL, "davinci_emac.1");
- clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, "fck", "davinci_mdio.0");
clk = davinci_clk_init(&voicecodec_clk);
clk_register_clkdev(clk, NULL, "davinci_voicecodec");
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 769ce29..58120f4 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -323,8 +323,6 @@ static __init void dm644x_clk_init(void)
clk_register_clkdev(clk, "master", "vpss");
clk = davinci_clk_init(&vpss_slave_clk);
clk_register_clkdev(clk, "slave", "vpss");
- clk = davinci_clk_init(&arm_clk);
- clk_register_clkdev(clk, "arm", NULL);
clk = davinci_clk_init(&uart0_clk);
clk_register_clkdev(clk, NULL, "serial8250.0");
clk = davinci_clk_init(&uart1_clk);
@@ -333,7 +331,6 @@ static __init void dm644x_clk_init(void)
clk_register_clkdev(clk, NULL, "serial8250.2");
clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, NULL, "davinci_emac.1");
- clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, "fck", "davinci_mdio.0");
clk = davinci_clk_init(&i2c_clk);
clk_register_clkdev(clk, NULL, "i2c_davinci.1");
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index d75b4bc09..0cd5d51 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -386,7 +386,6 @@ static __init void dm646x_clk_init(void)
clk_register_clkdev(clk, "aemif", NULL);
clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, NULL, "davinci_emac.1");
- clk = davinci_clk_init(&emac_clk);
clk_register_clkdev(clk, "fck", "davinci_mdio.0");
clk = davinci_clk_init(&pwm0_clk);
clk_register_clkdev(clk, "pwm0", NULL);
--
2.7.4
^ permalink raw reply related
* [PATCH v4 2/7] ARM: davinci: don't use static clk_lookup
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
In preparation of moving to the common clock framework, usage of static
struct clk_lookup is removed. The common clock framework uses an opaque
struct clk, so we won't be able to use static tables as was previously
done.
davinci_clk_init() is changed to init a single clock instead of a table
and an individual clk_register_clkdev() is added for each clock.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/mach-davinci/clock.c | 73 +++++------
arch/arm/mach-davinci/clock.h | 9 +-
arch/arm/mach-davinci/da830.c | 164 +++++++++++++++--------
arch/arm/mach-davinci/da850.c | 197 ++++++++++++++++++----------
arch/arm/mach-davinci/devices-da8xx.c | 5 +-
arch/arm/mach-davinci/dm355.c | 137 ++++++++++++-------
arch/arm/mach-davinci/dm365.c | 182 ++++++++++++++++---------
arch/arm/mach-davinci/dm644x.c | 125 ++++++++++++------
arch/arm/mach-davinci/dm646x.c | 131 +++++++++++-------
arch/arm/mach-davinci/include/mach/common.h | 1 -
arch/arm/mach-davinci/usb-da8xx.c | 15 +--
11 files changed, 652 insertions(+), 387 deletions(-)
diff --git a/arch/arm/mach-davinci/clock.c b/arch/arm/mach-davinci/clock.c
index f77a4f7..f82a90c 100644
--- a/arch/arm/mach-davinci/clock.c
+++ b/arch/arm/mach-davinci/clock.c
@@ -607,62 +607,51 @@ int davinci_set_refclk_rate(unsigned long rate)
return 0;
}
-int __init davinci_clk_init(struct clk_lookup *clocks)
+struct clk * __init davinci_clk_init(struct clk *clk)
{
- struct clk_lookup *c;
- struct clk *clk;
- size_t num_clocks = 0;
-
- for (c = clocks; c->clk; c++) {
- clk = c->clk;
+ if (!clk->recalc) {
- if (!clk->recalc) {
+ /* Check if clock is a PLL */
+ if (clk->pll_data)
+ clk->recalc = clk_pllclk_recalc;
- /* Check if clock is a PLL */
- if (clk->pll_data)
- clk->recalc = clk_pllclk_recalc;
+ /* Else, if it is a PLL-derived clock */
+ else if (clk->flags & CLK_PLL)
+ clk->recalc = clk_sysclk_recalc;
- /* Else, if it is a PLL-derived clock */
- else if (clk->flags & CLK_PLL)
- clk->recalc = clk_sysclk_recalc;
-
- /* Otherwise, it is a leaf clock (PSC clock) */
- else if (clk->parent)
- clk->recalc = clk_leafclk_recalc;
- }
+ /* Otherwise, it is a leaf clock (PSC clock) */
+ else if (clk->parent)
+ clk->recalc = clk_leafclk_recalc;
+ }
- if (clk->pll_data) {
- struct pll_data *pll = clk->pll_data;
+ if (clk->pll_data) {
+ struct pll_data *pll = clk->pll_data;
- if (!pll->div_ratio_mask)
- pll->div_ratio_mask = PLLDIV_RATIO_MASK;
+ if (!pll->div_ratio_mask)
+ pll->div_ratio_mask = PLLDIV_RATIO_MASK;
- if (pll->phys_base && !pll->base) {
- pll->base = ioremap(pll->phys_base, SZ_4K);
- WARN_ON(!pll->base);
- }
+ if (pll->phys_base && !pll->base) {
+ pll->base = ioremap(pll->phys_base, SZ_4K);
+ WARN_ON(!pll->base);
}
+ }
- if (clk->recalc)
- clk->rate = clk->recalc(clk);
-
- if (clk->lpsc)
- clk->flags |= CLK_PSC;
+ if (clk->recalc)
+ clk->rate = clk->recalc(clk);
- if (clk->flags & PSC_LRST)
- clk->reset = davinci_clk_reset;
+ if (clk->lpsc)
+ clk->flags |= CLK_PSC;
- clk_register(clk);
- num_clocks++;
+ if (clk->flags & PSC_LRST)
+ clk->reset = davinci_clk_reset;
- /* Turn on clocks that Linux doesn't otherwise manage */
- if (clk->flags & ALWAYS_ENABLED)
- clk_enable(clk);
- }
+ clk_register(clk);
- clkdev_add_table(clocks, num_clocks);
+ /* Turn on clocks that Linux doesn't otherwise manage */
+ if (clk->flags & ALWAYS_ENABLED)
+ clk_enable(clk);
- return 0;
+ return clk;
}
#ifdef CONFIG_DEBUG_FS
diff --git a/arch/arm/mach-davinci/clock.h b/arch/arm/mach-davinci/clock.h
index cf46781..66c40a2 100644
--- a/arch/arm/mach-davinci/clock.h
+++ b/arch/arm/mach-davinci/clock.h
@@ -118,14 +118,7 @@ struct clk {
#define PSC_FORCE BIT(6) /* Force module state transtition */
#define PSC_LRST BIT(8) /* Use local reset on enable/disable */
-#define CLK(dev, con, ck) \
- { \
- .dev_id = dev, \
- .con_id = con, \
- .clk = ck, \
- } \
-
-int davinci_clk_init(struct clk_lookup *clocks);
+struct clk *davinci_clk_init(struct clk *clk);
int davinci_set_pllrate(struct pll_data *pll, unsigned int prediv,
unsigned int mult, unsigned int postdiv);
int davinci_set_sysclk_rate(struct clk *clk, unsigned long rate);
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index 6a8b6ff..73c48f5 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -378,60 +378,113 @@ static struct clk rmii_clk = {
.parent = &pll0_sysclk7,
};
-static struct clk_lookup da830_clks[] = {
- CLK(NULL, "ref", &ref_clk),
- CLK(NULL, "pll0", &pll0_clk),
- CLK(NULL, "pll0_aux", &pll0_aux_clk),
- CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
- CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
- CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
- CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
- CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
- CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
- CLK("i2c_davinci.1", NULL, &i2c0_clk),
- CLK(NULL, "timer0", &timerp64_0_clk),
- CLK("davinci-wdt", NULL, &timerp64_1_clk),
- CLK(NULL, "arm_rom", &arm_rom_clk),
- CLK(NULL, "scr0_ss", &scr0_ss_clk),
- CLK(NULL, "scr1_ss", &scr1_ss_clk),
- CLK(NULL, "scr2_ss", &scr2_ss_clk),
- CLK(NULL, "dmax", &dmax_clk),
- CLK(NULL, "tpcc", &tpcc_clk),
- CLK(NULL, "tptc0", &tptc0_clk),
- CLK(NULL, "tptc1", &tptc1_clk),
- CLK("da830-mmc.0", NULL, &mmcsd_clk),
- CLK("serial8250.0", NULL, &uart0_clk),
- CLK("serial8250.1", NULL, &uart1_clk),
- CLK("serial8250.2", NULL, &uart2_clk),
- CLK("spi_davinci.0", NULL, &spi0_clk),
- CLK("spi_davinci.1", NULL, &spi1_clk),
- CLK(NULL, "ecap0", &ecap0_clk),
- CLK(NULL, "ecap1", &ecap1_clk),
- CLK(NULL, "ecap2", &ecap2_clk),
- CLK(NULL, "pwm0", &pwm0_clk),
- CLK(NULL, "pwm1", &pwm1_clk),
- CLK(NULL, "pwm2", &pwm2_clk),
- CLK("eqep.0", NULL, &eqep0_clk),
- CLK("eqep.1", NULL, &eqep1_clk),
- CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
- CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
- CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
- CLK("davinci-mcasp.2", NULL, &mcasp2_clk),
- CLK("musb-da8xx", "usb20", &usb20_clk),
- CLK("cppi41-dmaengine", NULL, &cppi41_clk),
- CLK(NULL, "aemif", &aemif_clk),
- CLK(NULL, "aintc", &aintc_clk),
- CLK(NULL, "secu_mgr", &secu_mgr_clk),
- CLK("davinci_emac.1", NULL, &emac_clk),
- CLK("davinci_mdio.0", "fck", &emac_clk),
- CLK(NULL, "gpio", &gpio_clk),
- CLK("i2c_davinci.2", NULL, &i2c1_clk),
- CLK("ohci-da8xx", "usb11", &usb11_clk),
- CLK(NULL, "emif3", &emif3_clk),
- CLK(NULL, "arm", &arm_clk),
- CLK(NULL, "rmii", &rmii_clk),
- CLK(NULL, NULL, NULL),
-};
+static __init void da830_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = davinci_clk_init(&ref_clk);
+ clk_register_clkdev(clk, "ref", NULL);
+ clk = davinci_clk_init(&pll0_clk);
+ clk_register_clkdev(clk, "pll0", NULL);
+ clk = davinci_clk_init(&pll0_aux_clk);
+ clk_register_clkdev(clk, "pll0_aux", NULL);
+ clk = davinci_clk_init(&pll0_sysclk2);
+ clk_register_clkdev(clk, "pll0_sysclk2", NULL);
+ clk = davinci_clk_init(&pll0_sysclk3);
+ clk_register_clkdev(clk, "pll0_sysclk3", NULL);
+ clk = davinci_clk_init(&pll0_sysclk4);
+ clk_register_clkdev(clk, "pll0_sysclk4", NULL);
+ clk = davinci_clk_init(&pll0_sysclk5);
+ clk_register_clkdev(clk, "pll0_sysclk5", NULL);
+ clk = davinci_clk_init(&pll0_sysclk6);
+ clk_register_clkdev(clk, "pll0_sysclk6", NULL);
+ clk = davinci_clk_init(&pll0_sysclk7);
+ clk_register_clkdev(clk, "pll0_sysclk7", NULL);
+ clk = davinci_clk_init(&i2c0_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.1");
+ clk = davinci_clk_init(&timerp64_0_clk);
+ clk_register_clkdev(clk, "timer0", NULL);
+ clk = davinci_clk_init(&timerp64_1_clk);
+ clk_register_clkdev(clk, NULL, "davinci-wdt");
+ clk = davinci_clk_init(&arm_rom_clk);
+ clk_register_clkdev(clk, "arm_rom", NULL);
+ clk = davinci_clk_init(&scr0_ss_clk);
+ clk_register_clkdev(clk, "scr0_ss", NULL);
+ clk = davinci_clk_init(&scr1_ss_clk);
+ clk_register_clkdev(clk, "scr1_ss", NULL);
+ clk = davinci_clk_init(&scr2_ss_clk);
+ clk_register_clkdev(clk, "scr2_ss", NULL);
+ clk = davinci_clk_init(&dmax_clk);
+ clk_register_clkdev(clk, "dmax", NULL);
+ clk = davinci_clk_init(&tpcc_clk);
+ clk_register_clkdev(clk, "tpcc", NULL);
+ clk = davinci_clk_init(&tptc0_clk);
+ clk_register_clkdev(clk, "tptc0", NULL);
+ clk = davinci_clk_init(&tptc1_clk);
+ clk_register_clkdev(clk, "tptc1", NULL);
+ clk = davinci_clk_init(&mmcsd_clk);
+ clk_register_clkdev(clk, NULL, "da830-mmc.0");
+ clk = davinci_clk_init(&uart0_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.0");
+ clk = davinci_clk_init(&uart1_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.1");
+ clk = davinci_clk_init(&uart2_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.2");
+ clk = davinci_clk_init(&spi0_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.0");
+ clk = davinci_clk_init(&spi1_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.1");
+ clk = davinci_clk_init(&ecap0_clk);
+ clk_register_clkdev(clk, "ecap0", NULL);
+ clk = davinci_clk_init(&ecap1_clk);
+ clk_register_clkdev(clk, "ecap1", NULL);
+ clk = davinci_clk_init(&ecap2_clk);
+ clk_register_clkdev(clk, "ecap2", NULL);
+ clk = davinci_clk_init(&pwm0_clk);
+ clk_register_clkdev(clk, "pwm0", NULL);
+ clk = davinci_clk_init(&pwm1_clk);
+ clk_register_clkdev(clk, "pwm1", NULL);
+ clk = davinci_clk_init(&pwm2_clk);
+ clk_register_clkdev(clk, "pwm2", NULL);
+ clk = davinci_clk_init(&eqep0_clk);
+ clk_register_clkdev(clk, NULL, "eqep.0");
+ clk = davinci_clk_init(&eqep1_clk);
+ clk_register_clkdev(clk, NULL, "eqep.1");
+ clk = davinci_clk_init(&lcdc_clk);
+ clk_register_clkdev(clk, "fck", "da8xx_lcdc.0");
+ clk = davinci_clk_init(&mcasp0_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcasp.0");
+ clk = davinci_clk_init(&mcasp1_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcasp.1");
+ clk = davinci_clk_init(&mcasp2_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcasp.2");
+ clk = davinci_clk_init(&usb20_clk);
+ clk_register_clkdev(clk, "usb20", "musb-da8xx");
+ clk = davinci_clk_init(&cppi41_clk);
+ clk_register_clkdev(clk, NULL, "cppi41-dmaengine");
+ clk = davinci_clk_init(&aemif_clk);
+ clk_register_clkdev(clk, "aemif", NULL);
+ clk = davinci_clk_init(&aintc_clk);
+ clk_register_clkdev(clk, "aintc", NULL);
+ clk = davinci_clk_init(&secu_mgr_clk);
+ clk_register_clkdev(clk, "secu_mgr", NULL);
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, NULL, "davinci_emac.1");
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, "fck", "davinci_mdio.0");
+ clk = davinci_clk_init(&gpio_clk);
+ clk_register_clkdev(clk, "gpio", NULL);
+ clk = davinci_clk_init(&i2c1_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.2");
+ clk = davinci_clk_init(&usb11_clk);
+ clk_register_clkdev(clk, "usb11", "ohci-da8xx");
+ clk = davinci_clk_init(&emif3_clk);
+ clk_register_clkdev(clk, "emif3", NULL);
+ clk = davinci_clk_init(&arm_clk);
+ clk_register_clkdev(clk, "arm", NULL);
+ clk = davinci_clk_init(&rmii_clk);
+ clk_register_clkdev(clk, "rmii", NULL);
+}
/*
* Device specific mux setup
@@ -1200,7 +1253,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = {
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da830_ids,
.ids_num = ARRAY_SIZE(da830_ids),
- .cpu_clks = da830_clks,
.psc_bases = da830_psc_bases,
.psc_bases_num = ARRAY_SIZE(da830_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
@@ -1224,6 +1276,6 @@ void __init da830_init(void)
void __init da830_init_time(void)
{
- davinci_clk_init(davinci_soc_info_da830.cpu_clks);
+ da830_clk_init();
davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 4da5b25..eaa05ac 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -518,71 +518,135 @@ static struct clk ecap2_clk = {
.parent = &ecap_clk,
};
-static struct clk_lookup da850_clks[] = {
- CLK(NULL, "ref", &ref_clk),
- CLK(NULL, "pll0", &pll0_clk),
- CLK(NULL, "pll0_aux", &pll0_aux_clk),
- CLK(NULL, "pll0_sysclk1", &pll0_sysclk1),
- CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
- CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
- CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
- CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
- CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
- CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
- CLK(NULL, "pll1", &pll1_clk),
- CLK(NULL, "pll1_aux", &pll1_aux_clk),
- CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
- CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
- CLK(NULL, "async3", &async3_clk),
- CLK("i2c_davinci.1", NULL, &i2c0_clk),
- CLK(NULL, "timer0", &timerp64_0_clk),
- CLK("davinci-wdt", NULL, &timerp64_1_clk),
- CLK(NULL, "arm_rom", &arm_rom_clk),
- CLK(NULL, "tpcc0", &tpcc0_clk),
- CLK(NULL, "tptc0", &tptc0_clk),
- CLK(NULL, "tptc1", &tptc1_clk),
- CLK(NULL, "tpcc1", &tpcc1_clk),
- CLK(NULL, "tptc2", &tptc2_clk),
- CLK("pruss_uio", "pruss", &pruss_clk),
- CLK("serial8250.0", NULL, &uart0_clk),
- CLK("serial8250.1", NULL, &uart1_clk),
- CLK("serial8250.2", NULL, &uart2_clk),
- CLK(NULL, "aintc", &aintc_clk),
- CLK(NULL, "gpio", &gpio_clk),
- CLK("i2c_davinci.2", NULL, &i2c1_clk),
- CLK(NULL, "emif3", &emif3_clk),
- CLK(NULL, "arm", &arm_clk),
- CLK(NULL, "rmii", &rmii_clk),
- CLK("davinci_emac.1", NULL, &emac_clk),
- CLK("davinci_mdio.0", "fck", &mdio_clk),
- CLK("davinci-mcasp.0", NULL, &mcasp_clk),
- CLK("davinci-mcbsp.0", NULL, &mcbsp0_clk),
- CLK("davinci-mcbsp.1", NULL, &mcbsp1_clk),
- CLK("da8xx_lcdc.0", "fck", &lcdc_clk),
- CLK("da830-mmc.0", NULL, &mmcsd0_clk),
- CLK("da830-mmc.1", NULL, &mmcsd1_clk),
- CLK("ti-aemif", NULL, &aemif_clk),
- CLK("davinci-nand.0", "aemif", &aemif_nand_clk),
- CLK("ohci-da8xx", "usb11", &usb11_clk),
- CLK("musb-da8xx", "usb20", &usb20_clk),
- CLK("cppi41-dmaengine", NULL, &cppi41_clk),
- CLK("spi_davinci.0", NULL, &spi0_clk),
- CLK("spi_davinci.1", NULL, &spi1_clk),
- CLK("vpif", NULL, &vpif_clk),
- CLK("ahci_da850", "fck", &sata_clk),
- CLK("davinci-rproc.0", NULL, &dsp_clk),
- CLK(NULL, NULL, &ehrpwm_clk),
- CLK("ehrpwm.0", "fck", &ehrpwm0_clk),
- CLK("ehrpwm.1", "fck", &ehrpwm1_clk),
- CLK(NULL, NULL, &ehrpwm_tbclk),
- CLK("ehrpwm.0", "tbclk", &ehrpwm0_tbclk),
- CLK("ehrpwm.1", "tbclk", &ehrpwm1_tbclk),
- CLK(NULL, NULL, &ecap_clk),
- CLK("ecap.0", "fck", &ecap0_clk),
- CLK("ecap.1", "fck", &ecap1_clk),
- CLK("ecap.2", "fck", &ecap2_clk),
- CLK(NULL, NULL, NULL),
-};
+static __init void da850_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = davinci_clk_init(&ref_clk);
+ clk_register_clkdev(clk, "ref", NULL);
+ clk = davinci_clk_init(&pll0_clk);
+ clk_register_clkdev(clk, "pll0", NULL);
+ clk = davinci_clk_init(&pll0_aux_clk);
+ clk_register_clkdev(clk, "pll0_aux", NULL);
+ clk = davinci_clk_init(&pll0_sysclk1);
+ clk_register_clkdev(clk, "pll0_sysclk1", NULL);
+ clk = davinci_clk_init(&pll0_sysclk2);
+ clk_register_clkdev(clk, "pll0_sysclk2", NULL);
+ clk = davinci_clk_init(&pll0_sysclk3);
+ clk_register_clkdev(clk, "pll0_sysclk3", NULL);
+ clk = davinci_clk_init(&pll0_sysclk4);
+ clk_register_clkdev(clk, "pll0_sysclk4", NULL);
+ clk = davinci_clk_init(&pll0_sysclk5);
+ clk_register_clkdev(clk, "pll0_sysclk5", NULL);
+ clk = davinci_clk_init(&pll0_sysclk6);
+ clk_register_clkdev(clk, "pll0_sysclk6", NULL);
+ clk = davinci_clk_init(&pll0_sysclk7);
+ clk_register_clkdev(clk, "pll0_sysclk7", NULL);
+ clk = davinci_clk_init(&pll1_clk);
+ clk_register_clkdev(clk, "pll1", NULL);
+ clk = davinci_clk_init(&pll1_aux_clk);
+ clk_register_clkdev(clk, "pll1_aux", NULL);
+ clk = davinci_clk_init(&pll1_sysclk2);
+ clk_register_clkdev(clk, "pll1_sysclk2", NULL);
+ clk = davinci_clk_init(&pll1_sysclk3);
+ clk_register_clkdev(clk, "pll1_sysclk3", NULL);
+ clk = davinci_clk_init(&async3_clk);
+ clk_register_clkdev(clk, "async3", NULL);
+ clk = davinci_clk_init(&i2c0_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.1");
+ clk = davinci_clk_init(&timerp64_0_clk);
+ clk_register_clkdev(clk, "timer0", NULL);
+ clk = davinci_clk_init(&timerp64_1_clk);
+ clk_register_clkdev(clk, NULL, "davinci-wdt");
+ clk = davinci_clk_init(&arm_rom_clk);
+ clk_register_clkdev(clk, "arm_rom", NULL);
+ clk = davinci_clk_init(&tpcc0_clk);
+ clk_register_clkdev(clk, "tpcc0", NULL);
+ clk = davinci_clk_init(&tptc0_clk);
+ clk_register_clkdev(clk, "tptc0", NULL);
+ clk = davinci_clk_init(&tptc1_clk);
+ clk_register_clkdev(clk, "tptc1", NULL);
+ clk = davinci_clk_init(&tpcc1_clk);
+ clk_register_clkdev(clk, "tpcc1", NULL);
+ clk = davinci_clk_init(&tptc2_clk);
+ clk_register_clkdev(clk, "tptc2", NULL);
+ clk = davinci_clk_init(&pruss_clk);
+ clk_register_clkdev(clk, "pruss", "pruss_uio");
+ clk = davinci_clk_init(&uart0_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.0");
+ clk = davinci_clk_init(&uart1_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.1");
+ clk = davinci_clk_init(&uart2_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.2");
+ clk = davinci_clk_init(&aintc_clk);
+ clk_register_clkdev(clk, "aintc", NULL);
+ clk = davinci_clk_init(&gpio_clk);
+ clk_register_clkdev(clk, "gpio", NULL);
+ clk = davinci_clk_init(&i2c1_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.2");
+ clk = davinci_clk_init(&emif3_clk);
+ clk_register_clkdev(clk, "emif3", NULL);
+ clk = davinci_clk_init(&arm_clk);
+ clk_register_clkdev(clk, "arm", NULL);
+ clk = davinci_clk_init(&rmii_clk);
+ clk_register_clkdev(clk, "rmii", NULL);
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, NULL, "davinci_emac.1");
+ clk = davinci_clk_init(&mdio_clk);
+ clk_register_clkdev(clk, "fck", "davinci_mdio.0");
+ clk = davinci_clk_init(&mcasp_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcasp.0");
+ clk = davinci_clk_init(&mcbsp0_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcbsp.0");
+ clk = davinci_clk_init(&mcbsp1_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcbsp.1");
+ clk = davinci_clk_init(&lcdc_clk);
+ clk_register_clkdev(clk, "fck", "da8xx_lcdc.0");
+ clk = davinci_clk_init(&mmcsd0_clk);
+ clk_register_clkdev(clk, NULL, "da830-mmc.0");
+ clk = davinci_clk_init(&mmcsd1_clk);
+ clk_register_clkdev(clk, NULL, "da830-mmc.1");
+ clk = davinci_clk_init(&aemif_clk);
+ clk_register_clkdev(clk, NULL, "ti-aemif");
+ clk = davinci_clk_init(&aemif_nand_clk);
+ clk_register_clkdev(clk, "aemif", "davinci-nand.0");
+ clk = davinci_clk_init(&usb11_clk);
+ clk_register_clkdev(clk, "usb11", "ohci-da8xx");
+ clk = davinci_clk_init(&usb20_clk);
+ clk_register_clkdev(clk, "usb20", "musb-da8xx");
+ clk = davinci_clk_init(&cppi41_clk);
+ clk_register_clkdev(clk, NULL, "cppi41-dmaengine");
+ clk = davinci_clk_init(&spi0_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.0");
+ clk = davinci_clk_init(&spi1_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.1");
+ clk = davinci_clk_init(&vpif_clk);
+ clk_register_clkdev(clk, NULL, "vpif");
+ clk = davinci_clk_init(&sata_clk);
+ clk_register_clkdev(clk, "fck", "ahci_da850");
+ clk = davinci_clk_init(&dsp_clk);
+ clk_register_clkdev(clk, NULL, "davinci-rproc.0");
+ clk = davinci_clk_init(&ehrpwm_clk);
+ clk_register_clkdev(clk, NULL, NULL);
+ clk = davinci_clk_init(&ehrpwm0_clk);
+ clk_register_clkdev(clk, "fck", "ehrpwm.0");
+ clk = davinci_clk_init(&ehrpwm1_clk);
+ clk_register_clkdev(clk, "fck", "ehrpwm.1");
+ clk = davinci_clk_init(&ehrpwm_tbclk);
+ clk_register_clkdev(clk, NULL, NULL);
+ clk = davinci_clk_init(&ehrpwm0_tbclk);
+ clk_register_clkdev(clk, "tbclk", "ehrpwm.0");
+ clk = davinci_clk_init(&ehrpwm1_tbclk);
+ clk_register_clkdev(clk, "tbclk", "ehrpwm.1");
+ clk = davinci_clk_init(&ecap_clk);
+ clk_register_clkdev(clk, NULL, NULL);
+ clk = davinci_clk_init(&ecap0_clk);
+ clk_register_clkdev(clk, "fck", "ecap.0");
+ clk = davinci_clk_init(&ecap1_clk);
+ clk_register_clkdev(clk, "fck", "ecap.1");
+ clk = davinci_clk_init(&ecap2_clk);
+ clk_register_clkdev(clk, "fck", "ecap.2");
+}
/*
* Device specific mux setup
@@ -1353,7 +1417,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = {
.jtag_id_reg = DA8XX_SYSCFG0_BASE + DA8XX_JTAG_ID_REG,
.ids = da850_ids,
.ids_num = ARRAY_SIZE(da850_ids),
- .cpu_clks = da850_clks,
.psc_bases = da850_psc_bases,
.psc_bases_num = ARRAY_SIZE(da850_psc_bases),
.pinmux_base = DA8XX_SYSCFG0_BASE + 0x120,
@@ -1396,6 +1459,6 @@ void __init da850_init(void)
void __init da850_init_time(void)
{
- davinci_clk_init(davinci_soc_info_da850.cpu_clks);
+ da850_clk_init();
davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/devices-da8xx.c b/arch/arm/mach-davinci/devices-da8xx.c
index fe5e15a..c9a79b2 100644
--- a/arch/arm/mach-davinci/devices-da8xx.c
+++ b/arch/arm/mach-davinci/devices-da8xx.c
@@ -1046,9 +1046,6 @@ static struct clk sata_refclk = {
.set_rate = davinci_simple_set_rate,
};
-static struct clk_lookup sata_refclk_lookup =
- CLK("ahci_da850", "refclk", &sata_refclk);
-
int __init da850_register_sata_refclk(int rate)
{
int ret;
@@ -1058,7 +1055,7 @@ int __init da850_register_sata_refclk(int rate)
if (ret)
return ret;
- clkdev_add(&sata_refclk_lookup);
+ clk_register_clkdev(&sata_refclk, "refclk", "ahci_da850");
return 0;
}
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 40641c0..9e5cfa9 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -337,51 +337,95 @@ static struct clk usb_clk = {
.lpsc = DAVINCI_LPSC_USB,
};
-static struct clk_lookup dm355_clks[] = {
- CLK(NULL, "ref", &ref_clk),
- CLK(NULL, "pll1", &pll1_clk),
- CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
- CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
- CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
- CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
- CLK(NULL, "pll1_aux", &pll1_aux_clk),
- CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
- CLK(NULL, "vpss_dac", &vpss_dac_clk),
- CLK("vpss", "master", &vpss_master_clk),
- CLK("vpss", "slave", &vpss_slave_clk),
- CLK(NULL, "clkout1", &clkout1_clk),
- CLK(NULL, "clkout2", &clkout2_clk),
- CLK(NULL, "pll2", &pll2_clk),
- CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
- CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
- CLK(NULL, "clkout3", &clkout3_clk),
- CLK(NULL, "arm", &arm_clk),
- CLK(NULL, "mjcp", &mjcp_clk),
- CLK("serial8250.0", NULL, &uart0_clk),
- CLK("serial8250.1", NULL, &uart1_clk),
- CLK("serial8250.2", NULL, &uart2_clk),
- CLK("i2c_davinci.1", NULL, &i2c_clk),
- CLK("davinci-mcbsp.0", NULL, &asp0_clk),
- CLK("davinci-mcbsp.1", NULL, &asp1_clk),
- CLK("dm6441-mmc.0", NULL, &mmcsd0_clk),
- CLK("dm6441-mmc.1", NULL, &mmcsd1_clk),
- CLK("spi_davinci.0", NULL, &spi0_clk),
- CLK("spi_davinci.1", NULL, &spi1_clk),
- CLK("spi_davinci.2", NULL, &spi2_clk),
- CLK(NULL, "gpio", &gpio_clk),
- CLK(NULL, "aemif", &aemif_clk),
- CLK(NULL, "pwm0", &pwm0_clk),
- CLK(NULL, "pwm1", &pwm1_clk),
- CLK(NULL, "pwm2", &pwm2_clk),
- CLK(NULL, "pwm3", &pwm3_clk),
- CLK(NULL, "timer0", &timer0_clk),
- CLK(NULL, "timer1", &timer1_clk),
- CLK("davinci-wdt", NULL, &timer2_clk),
- CLK(NULL, "timer3", &timer3_clk),
- CLK(NULL, "rto", &rto_clk),
- CLK(NULL, "usb", &usb_clk),
- CLK(NULL, NULL, NULL),
-};
+static __init void dm355_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = davinci_clk_init(&ref_clk);
+ clk_register_clkdev(clk, "ref", NULL);
+ clk = davinci_clk_init(&pll1_clk);
+ clk_register_clkdev(clk, "pll1", NULL);
+ clk = davinci_clk_init(&pll1_sysclk1);
+ clk_register_clkdev(clk, "pll1_sysclk1", NULL);
+ clk = davinci_clk_init(&pll1_sysclk2);
+ clk_register_clkdev(clk, "pll1_sysclk2", NULL);
+ clk = davinci_clk_init(&pll1_sysclk3);
+ clk_register_clkdev(clk, "pll1_sysclk3", NULL);
+ clk = davinci_clk_init(&pll1_sysclk4);
+ clk_register_clkdev(clk, "pll1_sysclk4", NULL);
+ clk = davinci_clk_init(&pll1_aux_clk);
+ clk_register_clkdev(clk, "pll1_aux", NULL);
+ clk = davinci_clk_init(&pll1_sysclkbp);
+ clk_register_clkdev(clk, "pll1_sysclkbp", NULL);
+ clk = davinci_clk_init(&vpss_dac_clk);
+ clk_register_clkdev(clk, "vpss_dac", NULL);
+ clk = davinci_clk_init(&vpss_master_clk);
+ clk_register_clkdev(clk, "master", "vpss");
+ clk = davinci_clk_init(&vpss_slave_clk);
+ clk_register_clkdev(clk, "slave", "vpss");
+ clk = davinci_clk_init(&clkout1_clk);
+ clk_register_clkdev(clk, "clkout1", NULL);
+ clk = davinci_clk_init(&clkout2_clk);
+ clk_register_clkdev(clk, "clkout2", NULL);
+ clk = davinci_clk_init(&pll2_clk);
+ clk_register_clkdev(clk, "pll2", NULL);
+ clk = davinci_clk_init(&pll2_sysclk1);
+ clk_register_clkdev(clk, "pll2_sysclk1", NULL);
+ clk = davinci_clk_init(&pll2_sysclkbp);
+ clk_register_clkdev(clk, "pll2_sysclkbp", NULL);
+ clk = davinci_clk_init(&clkout3_clk);
+ clk_register_clkdev(clk, "clkout3", NULL);
+ clk = davinci_clk_init(&arm_clk);
+ clk_register_clkdev(clk, "arm", NULL);
+ clk = davinci_clk_init(&mjcp_clk);
+ clk_register_clkdev(clk, "mjcp", NULL);
+ clk = davinci_clk_init(&uart0_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.0");
+ clk = davinci_clk_init(&uart1_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.1");
+ clk = davinci_clk_init(&uart2_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.2");
+ clk = davinci_clk_init(&i2c_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.1");
+ clk = davinci_clk_init(&asp0_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcbsp.0");
+ clk = davinci_clk_init(&asp1_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcbsp.1");
+ clk = davinci_clk_init(&mmcsd0_clk);
+ clk_register_clkdev(clk, NULL, "dm6441-mmc.0");
+ clk = davinci_clk_init(&mmcsd1_clk);
+ clk_register_clkdev(clk, NULL, "dm6441-mmc.1");
+ clk = davinci_clk_init(&spi0_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.0");
+ clk = davinci_clk_init(&spi1_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.1");
+ clk = davinci_clk_init(&spi2_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.2");
+ clk = davinci_clk_init(&gpio_clk);
+ clk_register_clkdev(clk, "gpio", NULL);
+ clk = davinci_clk_init(&aemif_clk);
+ clk_register_clkdev(clk, "aemif", NULL);
+ clk = davinci_clk_init(&pwm0_clk);
+ clk_register_clkdev(clk, "pwm0", NULL);
+ clk = davinci_clk_init(&pwm1_clk);
+ clk_register_clkdev(clk, "pwm1", NULL);
+ clk = davinci_clk_init(&pwm2_clk);
+ clk_register_clkdev(clk, "pwm2", NULL);
+ clk = davinci_clk_init(&pwm3_clk);
+ clk_register_clkdev(clk, "pwm3", NULL);
+ clk = davinci_clk_init(&timer0_clk);
+ clk_register_clkdev(clk, "timer0", NULL);
+ clk = davinci_clk_init(&timer1_clk);
+ clk_register_clkdev(clk, "timer1", NULL);
+ clk = davinci_clk_init(&timer2_clk);
+ clk_register_clkdev(clk, NULL, "davinci-wdt");
+ clk = davinci_clk_init(&timer3_clk);
+ clk_register_clkdev(clk, "timer3", NULL);
+ clk = davinci_clk_init(&rto_clk);
+ clk_register_clkdev(clk, "rto", NULL);
+ clk = davinci_clk_init(&usb_clk);
+ clk_register_clkdev(clk, "usb", NULL);
+}
/*----------------------------------------------------------------------*/
@@ -1012,7 +1056,6 @@ static const struct davinci_soc_info davinci_soc_info_dm355 = {
.jtag_id_reg = 0x01c40028,
.ids = dm355_ids,
.ids_num = ARRAY_SIZE(dm355_ids),
- .cpu_clks = dm355_clks,
.psc_bases = dm355_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm355_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -1047,7 +1090,7 @@ void __init dm355_init(void)
void __init dm355_init_time(void)
{
- davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
+ dm355_clk_init();
davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 0789ac6..0cf4ab4 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -425,66 +425,125 @@ static struct clk mjcp_clk = {
.lpsc = DM365_LPSC_MJCP,
};
-static struct clk_lookup dm365_clks[] = {
- CLK(NULL, "ref", &ref_clk),
- CLK(NULL, "pll1", &pll1_clk),
- CLK(NULL, "pll1_aux", &pll1_aux_clk),
- CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
- CLK(NULL, "clkout0", &clkout0_clk),
- CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
- CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
- CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
- CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
- CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
- CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
- CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
- CLK(NULL, "pll1_sysclk8", &pll1_sysclk8),
- CLK(NULL, "pll1_sysclk9", &pll1_sysclk9),
- CLK(NULL, "pll2", &pll2_clk),
- CLK(NULL, "pll2_aux", &pll2_aux_clk),
- CLK(NULL, "clkout1", &clkout1_clk),
- CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
- CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
- CLK(NULL, "pll2_sysclk3", &pll2_sysclk3),
- CLK(NULL, "pll2_sysclk4", &pll2_sysclk4),
- CLK(NULL, "pll2_sysclk5", &pll2_sysclk5),
- CLK(NULL, "pll2_sysclk6", &pll2_sysclk6),
- CLK(NULL, "pll2_sysclk7", &pll2_sysclk7),
- CLK(NULL, "pll2_sysclk8", &pll2_sysclk8),
- CLK(NULL, "pll2_sysclk9", &pll2_sysclk9),
- CLK(NULL, "vpss_dac", &vpss_dac_clk),
- CLK("vpss", "master", &vpss_master_clk),
- CLK("vpss", "slave", &vpss_slave_clk),
- CLK(NULL, "arm", &arm_clk),
- CLK("serial8250.0", NULL, &uart0_clk),
- CLK("serial8250.1", NULL, &uart1_clk),
- CLK("i2c_davinci.1", NULL, &i2c_clk),
- CLK("da830-mmc.0", NULL, &mmcsd0_clk),
- CLK("da830-mmc.1", NULL, &mmcsd1_clk),
- CLK("spi_davinci.0", NULL, &spi0_clk),
- CLK("spi_davinci.1", NULL, &spi1_clk),
- CLK("spi_davinci.2", NULL, &spi2_clk),
- CLK("spi_davinci.3", NULL, &spi3_clk),
- CLK("spi_davinci.4", NULL, &spi4_clk),
- CLK(NULL, "gpio", &gpio_clk),
- CLK(NULL, "aemif", &aemif_clk),
- CLK(NULL, "pwm0", &pwm0_clk),
- CLK(NULL, "pwm1", &pwm1_clk),
- CLK(NULL, "pwm2", &pwm2_clk),
- CLK(NULL, "pwm3", &pwm3_clk),
- CLK(NULL, "timer0", &timer0_clk),
- CLK(NULL, "timer1", &timer1_clk),
- CLK("davinci-wdt", NULL, &timer2_clk),
- CLK(NULL, "timer3", &timer3_clk),
- CLK(NULL, "usb", &usb_clk),
- CLK("davinci_emac.1", NULL, &emac_clk),
- CLK("davinci_mdio.0", "fck", &emac_clk),
- CLK("davinci_voicecodec", NULL, &voicecodec_clk),
- CLK("davinci-mcbsp", NULL, &asp0_clk),
- CLK(NULL, "rto", &rto_clk),
- CLK(NULL, "mjcp", &mjcp_clk),
- CLK(NULL, NULL, NULL),
-};
+static __init void dm365_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = davinci_clk_init(&ref_clk);
+ clk_register_clkdev(clk, "ref", NULL);
+ clk = davinci_clk_init(&pll1_clk);
+ clk_register_clkdev(clk, "pll1", NULL);
+ clk = davinci_clk_init(&pll1_aux_clk);
+ clk_register_clkdev(clk, "pll1_aux", NULL);
+ clk = davinci_clk_init(&pll1_sysclkbp);
+ clk_register_clkdev(clk, "pll1_sysclkbp", NULL);
+ clk = davinci_clk_init(&clkout0_clk);
+ clk_register_clkdev(clk, "clkout0", NULL);
+ clk = davinci_clk_init(&pll1_sysclk1);
+ clk_register_clkdev(clk, "pll1_sysclk1", NULL);
+ clk = davinci_clk_init(&pll1_sysclk2);
+ clk_register_clkdev(clk, "pll1_sysclk2", NULL);
+ clk = davinci_clk_init(&pll1_sysclk3);
+ clk_register_clkdev(clk, "pll1_sysclk3", NULL);
+ clk = davinci_clk_init(&pll1_sysclk4);
+ clk_register_clkdev(clk, "pll1_sysclk4", NULL);
+ clk = davinci_clk_init(&pll1_sysclk5);
+ clk_register_clkdev(clk, "pll1_sysclk5", NULL);
+ clk = davinci_clk_init(&pll1_sysclk6);
+ clk_register_clkdev(clk, "pll1_sysclk6", NULL);
+ clk = davinci_clk_init(&pll1_sysclk7);
+ clk_register_clkdev(clk, "pll1_sysclk7", NULL);
+ clk = davinci_clk_init(&pll1_sysclk8);
+ clk_register_clkdev(clk, "pll1_sysclk8", NULL);
+ clk = davinci_clk_init(&pll1_sysclk9);
+ clk_register_clkdev(clk, "pll1_sysclk9", NULL);
+ clk = davinci_clk_init(&pll2_clk);
+ clk_register_clkdev(clk, "pll2", NULL);
+ clk = davinci_clk_init(&pll2_aux_clk);
+ clk_register_clkdev(clk, "pll2_aux", NULL);
+ clk = davinci_clk_init(&clkout1_clk);
+ clk_register_clkdev(clk, "clkout1", NULL);
+ clk = davinci_clk_init(&pll2_sysclk1);
+ clk_register_clkdev(clk, "pll2_sysclk1", NULL);
+ clk = davinci_clk_init(&pll2_sysclk2);
+ clk_register_clkdev(clk, "pll2_sysclk2", NULL);
+ clk = davinci_clk_init(&pll2_sysclk3);
+ clk_register_clkdev(clk, "pll2_sysclk3", NULL);
+ clk = davinci_clk_init(&pll2_sysclk4);
+ clk_register_clkdev(clk, "pll2_sysclk4", NULL);
+ clk = davinci_clk_init(&pll2_sysclk5);
+ clk_register_clkdev(clk, "pll2_sysclk5", NULL);
+ clk = davinci_clk_init(&pll2_sysclk6);
+ clk_register_clkdev(clk, "pll2_sysclk6", NULL);
+ clk = davinci_clk_init(&pll2_sysclk7);
+ clk_register_clkdev(clk, "pll2_sysclk7", NULL);
+ clk = davinci_clk_init(&pll2_sysclk8);
+ clk_register_clkdev(clk, "pll2_sysclk8", NULL);
+ clk = davinci_clk_init(&pll2_sysclk9);
+ clk_register_clkdev(clk, "pll2_sysclk9", NULL);
+ clk = davinci_clk_init(&vpss_dac_clk);
+ clk_register_clkdev(clk, "vpss_dac", NULL);
+ clk = davinci_clk_init(&vpss_master_clk);
+ clk_register_clkdev(clk, "master", "vpss");
+ clk = davinci_clk_init(&vpss_slave_clk);
+ clk_register_clkdev(clk, "slave", "vpss");
+ clk = davinci_clk_init(&arm_clk);
+ clk_register_clkdev(clk, "arm", NULL);
+ clk = davinci_clk_init(&uart0_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.0");
+ clk = davinci_clk_init(&uart1_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.1");
+ clk = davinci_clk_init(&i2c_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.1");
+ clk = davinci_clk_init(&mmcsd0_clk);
+ clk_register_clkdev(clk, NULL, "da830-mmc.0");
+ clk = davinci_clk_init(&mmcsd1_clk);
+ clk_register_clkdev(clk, NULL, "da830-mmc.1");
+ clk = davinci_clk_init(&spi0_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.0");
+ clk = davinci_clk_init(&spi1_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.1");
+ clk = davinci_clk_init(&spi2_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.2");
+ clk = davinci_clk_init(&spi3_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.3");
+ clk = davinci_clk_init(&spi4_clk);
+ clk_register_clkdev(clk, NULL, "spi_davinci.4");
+ clk = davinci_clk_init(&gpio_clk);
+ clk_register_clkdev(clk, "gpio", NULL);
+ clk = davinci_clk_init(&aemif_clk);
+ clk_register_clkdev(clk, "aemif", NULL);
+ clk = davinci_clk_init(&pwm0_clk);
+ clk_register_clkdev(clk, "pwm0", NULL);
+ clk = davinci_clk_init(&pwm1_clk);
+ clk_register_clkdev(clk, "pwm1", NULL);
+ clk = davinci_clk_init(&pwm2_clk);
+ clk_register_clkdev(clk, "pwm2", NULL);
+ clk = davinci_clk_init(&pwm3_clk);
+ clk_register_clkdev(clk, "pwm3", NULL);
+ clk = davinci_clk_init(&timer0_clk);
+ clk_register_clkdev(clk, "timer0", NULL);
+ clk = davinci_clk_init(&timer1_clk);
+ clk_register_clkdev(clk, "timer1", NULL);
+ clk = davinci_clk_init(&timer2_clk);
+ clk_register_clkdev(clk, NULL, "davinci-wdt");
+ clk = davinci_clk_init(&timer3_clk);
+ clk_register_clkdev(clk, "timer3", NULL);
+ clk = davinci_clk_init(&usb_clk);
+ clk_register_clkdev(clk, "usb", NULL);
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, NULL, "davinci_emac.1");
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, "fck", "davinci_mdio.0");
+ clk = davinci_clk_init(&voicecodec_clk);
+ clk_register_clkdev(clk, NULL, "davinci_voicecodec");
+ clk = davinci_clk_init(&asp0_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcbsp");
+ clk = davinci_clk_init(&rto_clk);
+ clk_register_clkdev(clk, "rto", NULL);
+ clk = davinci_clk_init(&mjcp_clk);
+ clk_register_clkdev(clk, "mjcp", NULL);
+}
/*----------------------------------------------------------------------*/
@@ -1116,7 +1175,6 @@ static const struct davinci_soc_info davinci_soc_info_dm365 = {
.jtag_id_reg = 0x01c40028,
.ids = dm365_ids,
.ids_num = ARRAY_SIZE(dm365_ids),
- .cpu_clks = dm365_clks,
.psc_bases = dm365_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm365_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -1172,7 +1230,7 @@ void __init dm365_init(void)
void __init dm365_init_time(void)
{
- davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
+ dm365_clk_init();
davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index a1a2433..769ce29 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -285,47 +285,87 @@ static struct clk timer2_clk = {
.usecount = 1, /* REVISIT: why can't this be disabled? */
};
-static struct clk_lookup dm644x_clks[] = {
- CLK(NULL, "ref", &ref_clk),
- CLK(NULL, "pll1", &pll1_clk),
- CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
- CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
- CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
- CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
- CLK(NULL, "pll1_aux", &pll1_aux_clk),
- CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
- CLK(NULL, "pll2", &pll2_clk),
- CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
- CLK(NULL, "pll2_sysclk2", &pll2_sysclk2),
- CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
- CLK(NULL, "dsp", &dsp_clk),
- CLK(NULL, "arm", &arm_clk),
- CLK(NULL, "vicp", &vicp_clk),
- CLK("vpss", "master", &vpss_master_clk),
- CLK("vpss", "slave", &vpss_slave_clk),
- CLK(NULL, "arm", &arm_clk),
- CLK("serial8250.0", NULL, &uart0_clk),
- CLK("serial8250.1", NULL, &uart1_clk),
- CLK("serial8250.2", NULL, &uart2_clk),
- CLK("davinci_emac.1", NULL, &emac_clk),
- CLK("davinci_mdio.0", "fck", &emac_clk),
- CLK("i2c_davinci.1", NULL, &i2c_clk),
- CLK("palm_bk3710", NULL, &ide_clk),
- CLK("davinci-mcbsp", NULL, &asp_clk),
- CLK("dm6441-mmc.0", NULL, &mmcsd_clk),
- CLK(NULL, "spi", &spi_clk),
- CLK(NULL, "gpio", &gpio_clk),
- CLK(NULL, "usb", &usb_clk),
- CLK(NULL, "vlynq", &vlynq_clk),
- CLK(NULL, "aemif", &aemif_clk),
- CLK(NULL, "pwm0", &pwm0_clk),
- CLK(NULL, "pwm1", &pwm1_clk),
- CLK(NULL, "pwm2", &pwm2_clk),
- CLK(NULL, "timer0", &timer0_clk),
- CLK(NULL, "timer1", &timer1_clk),
- CLK("davinci-wdt", NULL, &timer2_clk),
- CLK(NULL, NULL, NULL),
-};
+static __init void dm644x_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = davinci_clk_init(&ref_clk);
+ clk_register_clkdev(clk, "ref", NULL);
+ clk = davinci_clk_init(&pll1_clk);
+ clk_register_clkdev(clk, "pll1", NULL);
+ clk = davinci_clk_init(&pll1_sysclk1);
+ clk_register_clkdev(clk, "pll1_sysclk1", NULL);
+ clk = davinci_clk_init(&pll1_sysclk2);
+ clk_register_clkdev(clk, "pll1_sysclk2", NULL);
+ clk = davinci_clk_init(&pll1_sysclk3);
+ clk_register_clkdev(clk, "pll1_sysclk3", NULL);
+ clk = davinci_clk_init(&pll1_sysclk5);
+ clk_register_clkdev(clk, "pll1_sysclk5", NULL);
+ clk = davinci_clk_init(&pll1_aux_clk);
+ clk_register_clkdev(clk, "pll1_aux", NULL);
+ clk = davinci_clk_init(&pll1_sysclkbp);
+ clk_register_clkdev(clk, "pll1_sysclkbp", NULL);
+ clk = davinci_clk_init(&pll2_clk);
+ clk_register_clkdev(clk, "pll2", NULL);
+ clk = davinci_clk_init(&pll2_sysclk1);
+ clk_register_clkdev(clk, "pll2_sysclk1", NULL);
+ clk = davinci_clk_init(&pll2_sysclk2);
+ clk_register_clkdev(clk, "pll2_sysclk2", NULL);
+ clk = davinci_clk_init(&pll2_sysclkbp);
+ clk_register_clkdev(clk, "pll2_sysclkbp", NULL);
+ clk = davinci_clk_init(&dsp_clk);
+ clk_register_clkdev(clk, "dsp", NULL);
+ clk = davinci_clk_init(&arm_clk);
+ clk_register_clkdev(clk, "arm", NULL);
+ clk = davinci_clk_init(&vicp_clk);
+ clk_register_clkdev(clk, "vicp", NULL);
+ clk = davinci_clk_init(&vpss_master_clk);
+ clk_register_clkdev(clk, "master", "vpss");
+ clk = davinci_clk_init(&vpss_slave_clk);
+ clk_register_clkdev(clk, "slave", "vpss");
+ clk = davinci_clk_init(&arm_clk);
+ clk_register_clkdev(clk, "arm", NULL);
+ clk = davinci_clk_init(&uart0_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.0");
+ clk = davinci_clk_init(&uart1_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.1");
+ clk = davinci_clk_init(&uart2_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.2");
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, NULL, "davinci_emac.1");
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, "fck", "davinci_mdio.0");
+ clk = davinci_clk_init(&i2c_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.1");
+ clk = davinci_clk_init(&ide_clk);
+ clk_register_clkdev(clk, NULL, "palm_bk3710");
+ clk = davinci_clk_init(&asp_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcbsp");
+ clk = davinci_clk_init(&mmcsd_clk);
+ clk_register_clkdev(clk, NULL, "dm6441-mmc.0");
+ clk = davinci_clk_init(&spi_clk);
+ clk_register_clkdev(clk, "spi", NULL);
+ clk = davinci_clk_init(&gpio_clk);
+ clk_register_clkdev(clk, "gpio", NULL);
+ clk = davinci_clk_init(&usb_clk);
+ clk_register_clkdev(clk, "usb", NULL);
+ clk = davinci_clk_init(&vlynq_clk);
+ clk_register_clkdev(clk, "vlynq", NULL);
+ clk = davinci_clk_init(&aemif_clk);
+ clk_register_clkdev(clk, "aemif", NULL);
+ clk = davinci_clk_init(&pwm0_clk);
+ clk_register_clkdev(clk, "pwm0", NULL);
+ clk = davinci_clk_init(&pwm1_clk);
+ clk_register_clkdev(clk, "pwm1", NULL);
+ clk = davinci_clk_init(&pwm2_clk);
+ clk_register_clkdev(clk, "pwm2", NULL);
+ clk = davinci_clk_init(&timer0_clk);
+ clk_register_clkdev(clk, "timer0", NULL);
+ clk = davinci_clk_init(&timer1_clk);
+ clk_register_clkdev(clk, "timer1", NULL);
+ clk = davinci_clk_init(&timer2_clk);
+ clk_register_clkdev(clk, NULL, "davinci-wdt");
+}
static struct emac_platform_data dm644x_emac_pdata = {
.ctrl_reg_offset = DM644X_EMAC_CNTRL_OFFSET,
@@ -905,7 +945,6 @@ static const struct davinci_soc_info davinci_soc_info_dm644x = {
.jtag_id_reg = 0x01c40028,
.ids = dm644x_ids,
.ids_num = ARRAY_SIZE(dm644x_ids),
- .cpu_clks = dm644x_clks,
.psc_bases = dm644x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm644x_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -935,7 +974,7 @@ void __init dm644x_init(void)
void __init dm644x_init_time(void)
{
- davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
+ dm644x_clk_init();
davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index c518403..d75b4bc09 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -320,49 +320,91 @@ static struct clk vpif1_clk = {
.flags = ALWAYS_ENABLED,
};
-static struct clk_lookup dm646x_clks[] = {
- CLK(NULL, "ref", &ref_clk),
- CLK(NULL, "aux", &aux_clkin),
- CLK(NULL, "pll1", &pll1_clk),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
- CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
- CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
- CLK(NULL, "pll1_aux", &pll1_aux_clk),
- CLK(NULL, "pll2", &pll2_clk),
- CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
- CLK(NULL, "dsp", &dsp_clk),
- CLK(NULL, "arm", &arm_clk),
- CLK(NULL, "edma_cc", &edma_cc_clk),
- CLK(NULL, "edma_tc0", &edma_tc0_clk),
- CLK(NULL, "edma_tc1", &edma_tc1_clk),
- CLK(NULL, "edma_tc2", &edma_tc2_clk),
- CLK(NULL, "edma_tc3", &edma_tc3_clk),
- CLK("serial8250.0", NULL, &uart0_clk),
- CLK("serial8250.1", NULL, &uart1_clk),
- CLK("serial8250.2", NULL, &uart2_clk),
- CLK("i2c_davinci.1", NULL, &i2c_clk),
- CLK(NULL, "gpio", &gpio_clk),
- CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
- CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
- CLK(NULL, "aemif", &aemif_clk),
- CLK("davinci_emac.1", NULL, &emac_clk),
- CLK("davinci_mdio.0", "fck", &emac_clk),
- CLK(NULL, "pwm0", &pwm0_clk),
- CLK(NULL, "pwm1", &pwm1_clk),
- CLK(NULL, "timer0", &timer0_clk),
- CLK(NULL, "timer1", &timer1_clk),
- CLK("davinci-wdt", NULL, &timer2_clk),
- CLK("palm_bk3710", NULL, &ide_clk),
- CLK(NULL, "vpif0", &vpif0_clk),
- CLK(NULL, "vpif1", &vpif1_clk),
- CLK(NULL, NULL, NULL),
-};
+static __init void dm646x_clk_init(void)
+{
+ struct clk *clk;
+
+ clk = davinci_clk_init(&ref_clk);
+ clk_register_clkdev(clk, "ref", NULL);
+ clk = davinci_clk_init(&aux_clkin);
+ clk_register_clkdev(clk, "aux", NULL);
+ clk = davinci_clk_init(&pll1_clk);
+ clk_register_clkdev(clk, "pll1", NULL);
+ clk = davinci_clk_init(&pll1_sysclk1);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclk2);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclk3);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclk4);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclk5);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclk6);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclk8);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclk9);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_sysclkbp);
+ clk_register_clkdev(clk, "pll1_sysclk", NULL);
+ clk = davinci_clk_init(&pll1_aux_clk);
+ clk_register_clkdev(clk, "pll1_aux", NULL);
+ clk = davinci_clk_init(&pll2_clk);
+ clk_register_clkdev(clk, "pll2", NULL);
+ clk = davinci_clk_init(&pll2_sysclk1);
+ clk_register_clkdev(clk, "pll2_sysclk1", NULL);
+ clk = davinci_clk_init(&dsp_clk);
+ clk_register_clkdev(clk, "dsp", NULL);
+ clk = davinci_clk_init(&arm_clk);
+ clk_register_clkdev(clk, "arm", NULL);
+ clk = davinci_clk_init(&edma_cc_clk);
+ clk_register_clkdev(clk, "edma_cc", NULL);
+ clk = davinci_clk_init(&edma_tc0_clk);
+ clk_register_clkdev(clk, "edma_tc0", NULL);
+ clk = davinci_clk_init(&edma_tc1_clk);
+ clk_register_clkdev(clk, "edma_tc1", NULL);
+ clk = davinci_clk_init(&edma_tc2_clk);
+ clk_register_clkdev(clk, "edma_tc2", NULL);
+ clk = davinci_clk_init(&edma_tc3_clk);
+ clk_register_clkdev(clk, "edma_tc3", NULL);
+ clk = davinci_clk_init(&uart0_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.0");
+ clk = davinci_clk_init(&uart1_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.1");
+ clk = davinci_clk_init(&uart2_clk);
+ clk_register_clkdev(clk, NULL, "serial8250.2");
+ clk = davinci_clk_init(&i2c_clk);
+ clk_register_clkdev(clk, NULL, "i2c_davinci.1");
+ clk = davinci_clk_init(&gpio_clk);
+ clk_register_clkdev(clk, "gpio", NULL);
+ clk = davinci_clk_init(&mcasp0_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcasp.0");
+ clk = davinci_clk_init(&mcasp1_clk);
+ clk_register_clkdev(clk, NULL, "davinci-mcasp.1");
+ clk = davinci_clk_init(&aemif_clk);
+ clk_register_clkdev(clk, "aemif", NULL);
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, NULL, "davinci_emac.1");
+ clk = davinci_clk_init(&emac_clk);
+ clk_register_clkdev(clk, "fck", "davinci_mdio.0");
+ clk = davinci_clk_init(&pwm0_clk);
+ clk_register_clkdev(clk, "pwm0", NULL);
+ clk = davinci_clk_init(&pwm1_clk);
+ clk_register_clkdev(clk, "pwm1", NULL);
+ clk = davinci_clk_init(&timer0_clk);
+ clk_register_clkdev(clk, "timer0", NULL);
+ clk = davinci_clk_init(&timer1_clk);
+ clk_register_clkdev(clk, "timer1", NULL);
+ clk = davinci_clk_init(&timer2_clk);
+ clk_register_clkdev(clk, NULL, "davinci-wdt");
+ clk = davinci_clk_init(&ide_clk);
+ clk_register_clkdev(clk, NULL, "palm_bk3710");
+ clk = davinci_clk_init(&vpif0_clk);
+ clk_register_clkdev(clk, "vpif0", NULL);
+ clk = davinci_clk_init(&vpif1_clk);
+ clk_register_clkdev(clk, "vpif1", NULL);
+}
static struct emac_platform_data dm646x_emac_pdata = {
.ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET,
@@ -888,7 +930,6 @@ static const struct davinci_soc_info davinci_soc_info_dm646x = {
.jtag_id_reg = 0x01c40028,
.ids = dm646x_ids,
.ids_num = ARRAY_SIZE(dm646x_ids),
- .cpu_clks = dm646x_clks,
.psc_bases = dm646x_psc_bases,
.psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
.pinmux_base = DAVINCI_SYSTEM_MODULE_BASE,
@@ -960,7 +1001,7 @@ void __init dm646x_init(void)
void __init dm646x_init_time(void)
{
- davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
+ dm646x_clk_init();
davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/include/mach/common.h b/arch/arm/mach-davinci/include/mach/common.h
index 19b9346..f0d5e858 100644
--- a/arch/arm/mach-davinci/include/mach/common.h
+++ b/arch/arm/mach-davinci/include/mach/common.h
@@ -53,7 +53,6 @@ struct davinci_soc_info {
u32 jtag_id_reg;
struct davinci_id *ids;
unsigned long ids_num;
- struct clk_lookup *cpu_clks;
u32 *psc_bases;
unsigned long psc_bases_num;
u32 pinmux_base;
diff --git a/arch/arm/mach-davinci/usb-da8xx.c b/arch/arm/mach-davinci/usb-da8xx.c
index d480a02..a2e575e 100644
--- a/arch/arm/mach-davinci/usb-da8xx.c
+++ b/arch/arm/mach-davinci/usb-da8xx.c
@@ -133,9 +133,6 @@ static struct clk usb_refclkin = {
.set_rate = davinci_simple_set_rate,
};
-static struct clk_lookup usb_refclkin_lookup =
- CLK(NULL, "usb_refclkin", &usb_refclkin);
-
/**
* da8xx_register_usb_refclkin - register USB_REFCLKIN clock
*
@@ -154,7 +151,7 @@ int __init da8xx_register_usb_refclkin(int rate)
if (ret)
return ret;
- clkdev_add(&usb_refclkin_lookup);
+ clk_register_clkdev(&usb_refclkin, "usb_refclkin", NULL);
return 0;
}
@@ -262,9 +259,6 @@ static struct clk usb20_phy_clk = {
.set_parent = usb20_phy_clk_set_parent,
};
-static struct clk_lookup usb20_phy_clk_lookup =
- CLK("da8xx-usb-phy", "usb20_phy", &usb20_phy_clk);
-
/**
* da8xx_register_usb20_phy_clk - register USB0PHYCLKMUX clock
*
@@ -291,7 +285,7 @@ int __init da8xx_register_usb20_phy_clk(bool use_usb_refclkin)
usb20_phy_clk.parent = parent;
ret = clk_register(&usb20_phy_clk);
if (!ret)
- clkdev_add(&usb20_phy_clk_lookup);
+ clk_register_clkdev(&usb20_phy_clk, "usb20_phy", "da8xx-usb-phy");
clk_put(parent);
@@ -324,9 +318,6 @@ static struct clk usb11_phy_clk = {
.set_parent = usb11_phy_clk_set_parent,
};
-static struct clk_lookup usb11_phy_clk_lookup =
- CLK("da8xx-usb-phy", "usb11_phy", &usb11_phy_clk);
-
/**
* da8xx_register_usb11_phy_clk - register USB1PHYCLKMUX clock
*
@@ -348,7 +339,7 @@ int __init da8xx_register_usb11_phy_clk(bool use_usb_refclkin)
usb11_phy_clk.parent = parent;
ret = clk_register(&usb11_phy_clk);
if (!ret)
- clkdev_add(&usb11_phy_clk_lookup);
+ clk_register_clkdev(&usb11_phy_clk, "usb11_phy", "da8xx-usb-phy");
clk_put(parent);
--
2.7.4
^ permalink raw reply related
* [PATCH v4 1/7] ARM: davinci: move davinci_clk_init() to init_time
From: David Lechner @ 2017-12-31 23:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
This moves the call of davinci_clk_init() from map_io to init_time for all
boards.
This is the proper place to init clocks. This is also done in preparation
for moving to the common clock framework.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/mach-davinci/board-da830-evm.c | 2 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 11 +++++++----
arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 2 +-
arch/arm/mach-davinci/board-sffsdr.c | 2 +-
arch/arm/mach-davinci/da830.c | 4 ++++
arch/arm/mach-davinci/da850.c | 4 ++++
arch/arm/mach-davinci/da8xx-dt.c | 2 +-
arch/arm/mach-davinci/davinci.h | 4 ++++
arch/arm/mach-davinci/dm355.c | 5 +++++
arch/arm/mach-davinci/dm365.c | 5 +++++
arch/arm/mach-davinci/dm644x.c | 5 +++++
arch/arm/mach-davinci/dm646x.c | 5 +++++
arch/arm/mach-davinci/include/mach/da8xx.h | 3 +++
20 files changed, 53 insertions(+), 15 deletions(-)
diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c
index a58bfca..7adf009 100644
--- a/arch/arm/mach-davinci/board-da830-evm.c
+++ b/arch/arm/mach-davinci/board-da830-evm.c
@@ -638,7 +638,7 @@ MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM")
.atag_offset = 0x100,
.map_io = da830_evm_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da830_init_time,
.init_machine = da830_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c
index 6039ec1..8602d0d 100644
--- a/arch/arm/mach-davinci/board-da850-evm.c
+++ b/arch/arm/mach-davinci/board-da850-evm.c
@@ -1481,7 +1481,7 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
.atag_offset = 0x100,
.map_io = da850_evm_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = da850_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c
index d60d998..3c15cb7 100644
--- a/arch/arm/mach-davinci/board-dm355-evm.c
+++ b/arch/arm/mach-davinci/board-dm355-evm.c
@@ -416,7 +416,7 @@ MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM")
.atag_offset = 0x100,
.map_io = dm355_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm355_init_time,
.init_machine = dm355_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c
index 1e7e9b8..3ebc89d 100644
--- a/arch/arm/mach-davinci/board-dm355-leopard.c
+++ b/arch/arm/mach-davinci/board-dm355-leopard.c
@@ -271,7 +271,7 @@ MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard")
.atag_offset = 0x100,
.map_io = dm355_leopard_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm355_init_time,
.init_machine = dm355_leopard_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c
index 17b2c29..3daeac7 100644
--- a/arch/arm/mach-davinci/board-dm365-evm.c
+++ b/arch/arm/mach-davinci/board-dm365-evm.c
@@ -774,7 +774,7 @@ MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM")
.atag_offset = 0x100,
.map_io = dm365_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm365_init_time,
.init_machine = dm365_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 5e1afc2..8d8c4ab 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -817,7 +817,7 @@ MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
.atag_offset = 0x100,
.map_io = davinci_evm_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-dm646x-evm.c b/arch/arm/mach-davinci/board-dm646x-evm.c
index 003bbe5..dafc852 100644
--- a/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -721,9 +721,12 @@ static void __init evm_init_i2c(void)
static void __init davinci_map_io(void)
{
dm646x_init();
+}
- if (machine_is_davinci_dm6467tevm())
- davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
+static void __init dm6467t_evm_init_time(void)
+{
+ dm646x_init_time();
+ davinci_set_refclk_rate(DM6467T_EVM_REF_FREQ);
}
#define DM646X_EVM_PHY_ID "davinci_mdio-0:01"
@@ -797,7 +800,7 @@ MACHINE_START(DAVINCI_DM6467_EVM, "DaVinci DM646x EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm646x_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
@@ -807,7 +810,7 @@ MACHINE_START(DAVINCI_DM6467TEVM, "DaVinci DM6467T EVM")
.atag_offset = 0x100,
.map_io = davinci_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm6467t_evm_init_time,
.init_machine = evm_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c
index 0b23cf3..f9a725a 100644
--- a/arch/arm/mach-davinci/board-mityomapl138.c
+++ b/arch/arm/mach-davinci/board-mityomapl138.c
@@ -570,7 +570,7 @@ MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808")
.atag_offset = 0x100,
.map_io = mityomapl138_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = mityomapl138_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-neuros-osd2.c b/arch/arm/mach-davinci/board-neuros-osd2.c
index 1e27baa..ff871a0 100644
--- a/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -227,7 +227,7 @@ MACHINE_START(NEUROS_OSD2, "Neuros OSD2")
.atag_offset = 0x100,
.map_io = davinci_ntosd2_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_ntosd2_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c
index 88ab45c..bc8a747 100644
--- a/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -334,7 +334,7 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
.atag_offset = 0x100,
.map_io = omapl138_hawk_map_io,
.init_irq = cp_intc_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = omapl138_hawk_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/board-sffsdr.c b/arch/arm/mach-davinci/board-sffsdr.c
index 1f02d4e..2922da9 100644
--- a/arch/arm/mach-davinci/board-sffsdr.c
+++ b/arch/arm/mach-davinci/board-sffsdr.c
@@ -150,7 +150,7 @@ MACHINE_START(SFFSDR, "Lyrtech SFFSDR")
.atag_offset = 0x100,
.map_io = davinci_sffsdr_map_io,
.init_irq = davinci_irq_init,
- .init_time = davinci_timer_init,
+ .init_time = dm644x_init_time,
.init_machine = davinci_sffsdr_init,
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c
index ed0b700..6a8b6ff 100644
--- a/arch/arm/mach-davinci/da830.c
+++ b/arch/arm/mach-davinci/da830.c
@@ -1220,6 +1220,10 @@ void __init da830_init(void)
da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K);
WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module");
+}
+void __init da830_init_time(void)
+{
davinci_clk_init(davinci_soc_info_da830.cpu_clks);
+ davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 04a58a3..4da5b25 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -1392,6 +1392,10 @@ void __init da850_init(void)
v = __raw_readl(DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
v &= ~CFGCHIP3_PLL1_MASTER_LOCK;
__raw_writel(v, DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG));
+}
+void __init da850_init_time(void)
+{
davinci_clk_init(davinci_soc_info_da850.cpu_clks);
+ davinci_timer_init();
}
diff --git a/arch/arm/mach-davinci/da8xx-dt.c b/arch/arm/mach-davinci/da8xx-dt.c
index 779e8ce..ab199f4 100644
--- a/arch/arm/mach-davinci/da8xx-dt.c
+++ b/arch/arm/mach-davinci/da8xx-dt.c
@@ -96,7 +96,7 @@ static const char *const da850_boards_compat[] __initconst = {
DT_MACHINE_START(DA850_DT, "Generic DA850/OMAP-L138/AM18x")
.map_io = da850_init,
- .init_time = davinci_timer_init,
+ .init_time = da850_init_time,
.init_machine = da850_init_machine,
.dt_compat = da850_boards_compat,
.init_late = davinci_init_late,
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index c62b90c..d70f4d9 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -83,6 +83,7 @@ int davinci_init_wdt(void);
/* DM355 function declarations */
void dm355_init(void);
+void dm355_init_time(void);
void dm355_init_spi0(unsigned chipselect_mask,
const struct spi_board_info *info, unsigned len);
void dm355_init_asp1(u32 evt_enable);
@@ -91,6 +92,7 @@ int dm355_gpio_register(void);
/* DM365 function declarations */
void dm365_init(void);
+void dm365_init_time(void);
void dm365_init_asp(void);
void dm365_init_vc(void);
void dm365_init_ks(struct davinci_ks_platform_data *pdata);
@@ -102,12 +104,14 @@ int dm365_gpio_register(void);
/* DM644x function declarations */
void dm644x_init(void);
+void dm644x_init_time(void);
void dm644x_init_asp(void);
int dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
int dm644x_gpio_register(void);
/* DM646x function declarations */
void dm646x_init(void);
+void dm646x_init_time(void);
void dm646x_init_mcasp0(struct snd_platform_data *pdata);
void dm646x_init_mcasp1(struct snd_platform_data *pdata);
int dm646x_init_edma(struct edma_rsv_info *rsv);
diff --git a/arch/arm/mach-davinci/dm355.c b/arch/arm/mach-davinci/dm355.c
index 938747f..40641c0 100644
--- a/arch/arm/mach-davinci/dm355.c
+++ b/arch/arm/mach-davinci/dm355.c
@@ -1043,7 +1043,12 @@ void __init dm355_init(void)
{
davinci_common_init(&davinci_soc_info_dm355);
davinci_map_sysmod();
+}
+
+void __init dm355_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm355.cpu_clks);
+ davinci_timer_init();
}
int __init dm355_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm365.c b/arch/arm/mach-davinci/dm365.c
index 5d9f96d..0789ac6 100644
--- a/arch/arm/mach-davinci/dm365.c
+++ b/arch/arm/mach-davinci/dm365.c
@@ -1168,7 +1168,12 @@ void __init dm365_init(void)
{
davinci_common_init(&davinci_soc_info_dm365);
davinci_map_sysmod();
+}
+
+void __init dm365_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm365.cpu_clks);
+ davinci_timer_init();
}
static struct resource dm365_vpss_resources[] = {
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 6b41e1c..a1a2433 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -931,7 +931,12 @@ void __init dm644x_init(void)
{
davinci_common_init(&davinci_soc_info_dm644x);
davinci_map_sysmod();
+}
+
+void __init dm644x_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm644x.cpu_clks);
+ davinci_timer_init();
}
int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
diff --git a/arch/arm/mach-davinci/dm646x.c b/arch/arm/mach-davinci/dm646x.c
index 6fc06a6..c518403 100644
--- a/arch/arm/mach-davinci/dm646x.c
+++ b/arch/arm/mach-davinci/dm646x.c
@@ -956,7 +956,12 @@ void __init dm646x_init(void)
{
davinci_common_init(&davinci_soc_info_dm646x);
davinci_map_sysmod();
+}
+
+void __init dm646x_init_time(void)
+{
davinci_clk_init(davinci_soc_info_dm646x.cpu_clks);
+ davinci_timer_init();
}
static int __init dm646x_init_devices(void)
diff --git a/arch/arm/mach-davinci/include/mach/da8xx.h b/arch/arm/mach-davinci/include/mach/da8xx.h
index 751d2ac..3481a0d 100644
--- a/arch/arm/mach-davinci/include/mach/da8xx.h
+++ b/arch/arm/mach-davinci/include/mach/da8xx.h
@@ -87,7 +87,10 @@ extern unsigned int da850_max_speed;
#define DA8XX_ARM_RAM_BASE 0xffff0000
void da830_init(void);
+void da830_init_time(void);
+
void da850_init(void);
+void da850_init_time(void);
int da830_register_edma(struct edma_rsv_info *rsv);
int da850_register_edma(struct edma_rsv_info *rsv[2]);
--
2.7.4
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