* [PATCH 05/12] pinctrl: armada-37xx: account for const type of of_device_id.data
From: Gregory CLEMENT @ 2018-01-02 15:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514899688-27844-6-git-send-email-Julia.Lawall@lip6.fr>
Hi Julia,
On mar., janv. 02 2018, Julia Lawall <Julia.Lawall@lip6.fr> wrote:
> The data field of an of_device_id structure has type const void *, so
> there is no need for a const-discarding cast when putting const values
> into such a structure.
>
> Done using Coccinelle.
>
> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Thanks,
Gregory
PS: actually the intent was not to do a const-discarding cast it was
just a useless cast! :)
>
> ---
> drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff -u -p a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> --- a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> +++ b/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
> @@ -1006,11 +1006,11 @@ static int armada_37xx_pinctrl_register(
> static const struct of_device_id armada_37xx_pinctrl_of_match[] = {
> {
> .compatible = "marvell,armada3710-sb-pinctrl",
> - .data = (void *)&armada_37xx_pin_sb,
> + .data = &armada_37xx_pin_sb,
> },
> {
> .compatible = "marvell,armada3710-nb-pinctrl",
> - .data = (void *)&armada_37xx_pin_nb,
> + .data = &armada_37xx_pin_nb,
> },
> { },
> };
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul
From: Fabio Estevam @ 2018-01-02 15:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <6FFDB281-8293-4D2C-891F-B376B52EFECF@nxp.com>
On Tue, Jan 2, 2018 at 1:17 PM, Anson Huang <anson.huang@nxp.com> wrote:
> This change is only valid for mx6ul and mx6ull, other SoCs like 6q/dl/qp are
> NOT impacted.
Thanks for the clarification:
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point
From: Fabio Estevam @ 2018-01-02 15:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E5B0DB53-D0E5-430B-BBCC-EF3899C70DAE@nxp.com>
On Tue, Jan 2, 2018 at 1:12 PM, Anson Huang <anson.huang@nxp.com> wrote:
> There is a comment in VDD_ARM, VDD_SOC must NOT lower than VDD_ARM.
>
> Output voltage must be set to the following rules:
> ? VDD_ARM_CAP <= VDD_SOC_CAP
> ? VDD_SOC_CAP - VDD_ARM_CAP < 330 mV
Thanks for the clarifcation.
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* [PATCH v2 0/8] Armada 7K/8K CP110 DT de-duplication
From: Gregory CLEMENT @ 2018-01-02 15:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180102145558.9773-1-thomas.petazzoni@free-electrons.com>
Hi Thomas,
On mar., janv. 02 2018, Thomas Petazzoni <thomas.petazzoni@free-electrons.com> wrote:
> Hello,
>
> This series aims at de-duplicating the Armada CP110 Device Tree
> description, which is currently duplicated between
> armada-cp110-master.dtsi and armada-cp110-slave.dtsi, even though they
> are almost identical. Indeed, one concept of Marvell SoCs is that they
> are made of HW blocks composed of a variety of IPs (network, PCIe,
> SATA, XOR, SPI, I2C, etc.), and those HW blocks can be duplicated
> several times within a given SoC. The Armada 7K SoC has a single CP110
> (so no duplication), while the Armada 8K SoC has two CP110. In the
> future, SoCs with more than 2 CP110s will be introduced.
>
> This duplication issue has been discussed at the DT workshop [1] in
> Prague last October, and I presented on this topic [2]. The solution
> of using the C pre-processor to avoid this duplication has been
> validated by the people present in this DT workshop, and this patch
> series simply submits what has been presented.
>
> - The first four patches are fixes for existing
> issues/inconsistencies in the Device Tree files. Since they don't
> fix any visible problems, they are not marked for -stable.
>
> - The fifth patch is a minor improvement.
>
> - The sixth patch making use of aliases for SPI busses simply aims at
> reducing the number of changes between the CP110 master and CP110
> slave description, by avoiding the need for the cell-index property
> in the SPI controller DT nodes.
>
> - The seventh patch implements the de-duplication itself, by
> introducing an armada-cp110.dtsi file included twice on Armada 8K
> platforms, once for the master CP110 and once for the slave CP110.
>
> - The last patch renames cpm to cp0 and cps to cp1, as the concept of
> master/slave CPs does not apply to future SoCs that have more than
> 2 CPs.
>
> Changes since v1:
>
> - Rebase on top of mvebu/dt64, since the NAND controller changes will
> only be submitted for 4.17.
>
> - Add patches fixing NAND related typos/inconsistencies:
> arm64: dts: marvell: fix typos in comment describing the NAND controller
> arm64: dts: marvell: fix compatible string list for Armada CP110 slave NAND
>
> - Improve the de-duplication patch by removing
> armada-cp110-master.dtsi and armada-cp110-slave.dtsi, since the
> concept of master/slave will no longer exist when we will have more
> than 2 CPs.
>
> - Add a patch renaming cpm -> cp0, cps -> cp1.
>
> Best regards,
>
> Thomas
>
I applied all the series on mvebu/dt64. The only change I made was
adding a commit log to the patch 3:
"Fix the same typo duplicated in both master and slave version of
armada-cp110-*.dtsi file: s/limiation/limitation/."
Thanks,
Gregory
> [1] https://elinux.org/Device_tree_kernel_summit_2017_etherpad
> [2] https://elinux.org/images/1/14/DTWorkshop2017-duplicate-data.pdf
>
> Thomas Petazzoni (8):
> arm64: dts: marvell: fix watchdog unit address in Armada AP806
> arm64: dts: marvell: use lower case for unit address and reg property
> arm64: dts: marvell: fix typos in comment describing the NAND
> controller
> arm64: dts: marvell: fix compatible string list for Armada CP110 slave
> NAND
> arm64: dts: marvell: use mvebu-icu.h where possible
> arm64: dts: marvell: use aliases for SPI busses on Armada 7K/8K
> arm64: dts: marvell: de-duplicate CP110 description
> arm64: dts: marvell: replace cpm by cp0, cps by cp1
>
> arch/arm64/boot/dts/marvell/armada-7040-db.dts | 46 +--
> arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 37 +-
> arch/arm64/boot/dts/marvell/armada-8020.dtsi | 2 +-
> arch/arm64/boot/dts/marvell/armada-8040-db.dts | 80 ++--
> arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 76 ++--
> arch/arm64/boot/dts/marvell/armada-8040.dtsi | 2 +-
> arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 80 +++-
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 +-
> arch/arm64/boot/dts/marvell/armada-common.dtsi | 10 +
> .../boot/dts/marvell/armada-cp110-master.dtsi | 449 ---------------------
> .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 448 --------------------
> arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 422 +++++++++++++++++++
> 12 files changed, 635 insertions(+), 1025 deletions(-)
> create mode 100644 arch/arm64/boot/dts/marvell/armada-common.dtsi
> delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> delete mode 100644 arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> create mode 100644 arch/arm64/boot/dts/marvell/armada-cp110.dtsi
>
> --
> 2.14.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: OMAP: clock: Fix debugfs_create_*() usage
From: Geert Uytterhoeven @ 2018-01-02 15:25 UTC (permalink / raw)
To: linux-arm-kernel
When exposing data access through debugfs, the correct
debugfs_create_*() functions must be used, depending on data type.
Remove all casts from data pointers passed to debugfs_create_*()
functions, as such casts prevent the compiler from flagging bugs.
Correct all wrong usage:
- clk.rate is unsigned long, not u32,
- clk.flags is u8, not u32, which exposed the successive
clk.rate_offset and clk.src_offset fields.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Compile-tested only.
---
arch/arm/mach-omap1/clock.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
index 43e3e188f5213418..fa512413a4717221 100644
--- a/arch/arm/mach-omap1/clock.c
+++ b/arch/arm/mach-omap1/clock.c
@@ -1011,17 +1011,17 @@ static int clk_debugfs_register_one(struct clk *c)
return -ENOMEM;
c->dent = d;
- d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
+ d = debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount);
if (!d) {
err = -ENOMEM;
goto err_out;
}
- d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
+ d = debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);
if (!d) {
err = -ENOMEM;
goto err_out;
}
- d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
+ d = debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags);
if (!d) {
err = -ENOMEM;
goto err_out;
--
2.7.4
^ permalink raw reply related
* [Cluster-devel] [PATCH 00/12] drop unneeded newline
From: Julia Lawall @ 2018-01-02 15:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905900.4242.4.camel@wdc.com>
On Tue, 2 Jan 2018, Bart Van Assche wrote:
> On Tue, 2018-01-02 at 15:00 +0100, Julia Lawall wrote:
> > On Tue, 2 Jan 2018, Bob Peterson wrote:
> > > ----- Original Message -----
> > > > ----- Original Message -----
> > > >
> > > Still, the GFS2 and DLM code has a plethora of broken-up printk messages,
> > > and I don't like the thought of re-combining them all.
> >
> > Actually, the point of the patch was to remove the unnecessary \n at the
> > end of the string, because log_print will add another one. If you prefer
> > to keep the string broken up, I can resend the patch in that form, but
> > without the unnecessary \n.
>
> Please combine any user-visible strings into a single line for which the
> unneeded newline is dropped since these strings are modified anyway by
> your patch.
That is what the submitted patch (2/12 specifically) did.
julia
^ permalink raw reply
* [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul
From: Fabio Estevam @ 2018-01-02 15:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <A2F3BA8B-361A-4809-83FE-4067CD868D5B@nxp.com>
Hi Anson,
On Tue, Jan 2, 2018 at 1:05 PM, Anson Huang <anson.huang@nxp.com> wrote:
> This change is to support 696MHz operating point, both the speed grading
> check and pll rate change are necessary for 696MHz support, do you think
> they should be in different patch?
I thought this could also change the behaviour for mx6q/dl/qp.
Are the others SoCs safe with this change?
^ permalink raw reply
* [PATCH V3 3/3] arm64: Extend early page table code to allow for larger kernels
From: Steve Capper @ 2018-01-02 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180102151254.4063-1-steve.capper@arm.com>
Currently the early assembler page table code assumes that precisely
1xpgd, 1xpud, 1xpmd are sufficient to represent the early kernel text
mappings.
Unfortunately this is rarely the case when running with a 16KB granule,
and we also run into limits with 4KB granule when building much larger
kernels.
This patch re-writes the early page table logic to compute indices of
mappings for each level of page table, and if multiple indices are
required, the next-level page table is scaled up accordingly.
Also the required size of the swapper_pg_dir is computed at link time
to cover the mapping [KIMAGE_ADDR + VOFFSET, _end]. When KASLR is
enabled, an extra page is set aside for each level that may require extra
entries at runtime.
Signed-off-by: Steve Capper <steve.capper@arm.com>
---
Changed in V3:
Corrected KASLR computation
Rebased against arm64/for-next/core, particularly Kristina's 52-bit
PA series.
---
arch/arm64/include/asm/kernel-pgtable.h | 47 ++++++++++-
arch/arm64/include/asm/pgtable.h | 1 +
arch/arm64/kernel/head.S | 145 +++++++++++++++++++++++---------
arch/arm64/kernel/vmlinux.lds.S | 1 +
arch/arm64/mm/mmu.c | 3 +-
5 files changed, 157 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/include/asm/kernel-pgtable.h b/arch/arm64/include/asm/kernel-pgtable.h
index 77a27af01371..82386e860dd2 100644
--- a/arch/arm64/include/asm/kernel-pgtable.h
+++ b/arch/arm64/include/asm/kernel-pgtable.h
@@ -52,7 +52,52 @@
#define IDMAP_PGTABLE_LEVELS (ARM64_HW_PGTABLE_LEVELS(PHYS_MASK_SHIFT))
#endif
-#define SWAPPER_DIR_SIZE (SWAPPER_PGTABLE_LEVELS * PAGE_SIZE)
+
+/*
+ * If KASLR is enabled, then an offset K is added to the kernel address
+ * space. The bottom 21 bits of this offset are zero to guarantee 2MB
+ * alignment for PA and VA.
+ *
+ * For each pagetable level of the swapper, we know that the shift will
+ * be larger than 21 (for the 4KB granule case we use section maps thus
+ * the smallest shift is actually 30) thus there is the possibility that
+ * KASLR can increase the number of pagetable entries by 1, so we make
+ * room for this extra entry.
+ *
+ * Note KASLR cannot increase the number of required entries for a level
+ * by more than one because it increments both the virtual start and end
+ * addresses equally (the extra entry comes from the case where the end
+ * address is just pushed over a boundary and the start address isn't).
+ */
+
+#ifdef CONFIG_RANDOMIZE_BASE
+#define EARLY_KASLR (1)
+#else
+#define EARLY_KASLR (0)
+#endif
+
+#define EARLY_ENTRIES(vstart, vend, shift) (((vend) >> (shift)) \
+ - ((vstart) >> (shift)) + 1 + EARLY_KASLR)
+
+#define EARLY_PGDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PGDIR_SHIFT))
+
+#if SWAPPER_PGTABLE_LEVELS > 3
+#define EARLY_PUDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, PUD_SHIFT))
+#else
+#define EARLY_PUDS(vstart, vend) (0)
+#endif
+
+#if SWAPPER_PGTABLE_LEVELS > 2
+#define EARLY_PMDS(vstart, vend) (EARLY_ENTRIES(vstart, vend, SWAPPER_TABLE_SHIFT))
+#else
+#define EARLY_PMDS(vstart, vend) (0)
+#endif
+
+#define EARLY_PAGES(vstart, vend) ( 1 /* PGDIR page */ \
+ + EARLY_PGDS((vstart), (vend)) /* each PGDIR needs a next level page table */ \
+ + EARLY_PUDS((vstart), (vend)) /* each PUD needs a next level page table */ \
+ + EARLY_PMDS((vstart), (vend))) /* each PMD needs a next level page table */
+#define SWAPPER_DIR_SIZE (PAGE_SIZE * EARLY_PAGES(KIMAGE_VADDR + TEXT_OFFSET, _end))
#define IDMAP_DIR_SIZE (IDMAP_PGTABLE_LEVELS * PAGE_SIZE)
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index bfa237e892f1..54b0a8398055 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -706,6 +706,7 @@ static inline void pmdp_set_wrprotect(struct mm_struct *mm,
#endif
extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+extern pgd_t swapper_pg_end[];
extern pgd_t idmap_pg_dir[PTRS_PER_PGD];
extern pgd_t tramp_pg_dir[PTRS_PER_PGD];
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 66f01869e97c..539e2642ed41 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -191,44 +191,110 @@ ENDPROC(preserve_boot_args)
.endm
/*
- * Macro to populate the PGD (and possibily PUD) for the corresponding
- * block entry in the next level (tbl) for the given virtual address.
+ * Macro to populate page table entries, these entries can be pointers to the next level
+ * or last level entries pointing to physical memory.
*
- * Preserves: tbl, next, virt
- * Corrupts: ptrs_per_pgd, tmp1, tmp2
+ * tbl: page table address
+ * rtbl: pointer to page table or physical memory
+ * index: start index to write
+ * eindex: end index to write - [index, eindex] written to
+ * flags: flags for pagetable entry to or in
+ * inc: increment to rtbl between each entry
+ * tmp1: temporary variable
+ *
+ * Preserves: tbl, eindex, flags, inc
+ * Corrupts: index, tmp1
+ * Returns: rtbl
*/
- .macro create_pgd_entry, tbl, virt, ptrs_per_pgd, tmp1, tmp2
- create_table_entry \tbl, \virt, PGDIR_SHIFT, \ptrs_per_pgd, \tmp1, \tmp2
-#if SWAPPER_PGTABLE_LEVELS > 3
- mov \ptrs_per_pgd, PTRS_PER_PUD
- create_table_entry \tbl, \virt, PUD_SHIFT, \ptrs_per_pgd, \tmp1, \tmp2
-#endif
-#if SWAPPER_PGTABLE_LEVELS > 2
- mov \ptrs_per_pgd, PTRS_PER_PTE
- create_table_entry \tbl, \virt, SWAPPER_TABLE_SHIFT, \ptrs_per_pgd, \tmp1, \tmp2
-#endif
+ .macro populate_entries, tbl, rtbl, index, eindex, flags, inc, tmp1
+9999: phys_to_pte \rtbl, \tmp1
+ orr \tmp1, \tmp1, \flags // tmp1 = table entry
+ str \tmp1, [\tbl, \index, lsl #3]
+ add \rtbl, \rtbl, \inc // rtbl = pa next level
+ add \index, \index, #1
+ cmp \index, \eindex
+ b.ls 9999b
.endm
/*
- * Macro to populate block entries in the page table for the start..end
- * virtual range (inclusive).
+ * Compute indices of table entries from virtual address range. If multiple entries
+ * were needed in the previous page table level then the next page table level is assumed
+ * to be composed of multiple pages. (This effectively scales the end index).
+ *
+ * vstart: virtual address of start of range
+ * vend: virtual address of end of range
+ * shift: shift used to transform virtual address into index
+ * ptrs: number of entries in page table
+ * istart: index in table corresponding to vstart
+ * iend: index in table corresponding to vend
+ * count: On entry: how many entries required in previous level, scales our end index
+ * On exit: returns how many entries required for next page table level
*
- * Preserves: tbl, flags
- * Corrupts: phys, start, end, tmp, pstate
+ * Preserves: vstart, vend, shift, ptrs
+ * Returns: istart, iend, count
*/
- .macro create_block_map, tbl, flags, phys, start, end, tmp
- lsr \start, \start, #SWAPPER_BLOCK_SHIFT
- and \start, \start, #PTRS_PER_PTE - 1 // table index
- bic \phys, \phys, #SWAPPER_BLOCK_SIZE - 1
- lsr \end, \end, #SWAPPER_BLOCK_SHIFT
- and \end, \end, #PTRS_PER_PTE - 1 // table end index
-9999: phys_to_pte \phys, \tmp
- orr \tmp, \tmp, \flags // table entry
- str \tmp, [\tbl, \start, lsl #3] // store the entry
- add \start, \start, #1 // next entry
- add \phys, \phys, #SWAPPER_BLOCK_SIZE // next block
- cmp \start, \end
- b.ls 9999b
+ .macro compute_indices, vstart, vend, shift, ptrs, istart, iend, count
+ lsr \iend, \vend, \shift
+ mov \istart, \ptrs
+ sub \istart, \istart, #1
+ and \iend, \iend, \istart // iend = (vend >> shift) & (ptrs - 1)
+ mov \istart, \ptrs
+ sub \count, \count, #1
+ mul \istart, \istart, \count
+ add \iend, \iend, \istart // iend += (count - 1) * ptrs
+ // our entries span multiple tables
+
+ lsr \istart, \vstart, \shift
+ mov \count, \ptrs
+ sub \count, \count, #1
+ and \istart, \istart, \count
+
+ sub \count, \iend, \istart
+ add \count, \count, #1
+ .endm
+
+/*
+ * Map memory for specified virtual address range. Each level of page table needed supports
+ * multiple entries. If a level requires n entries the next page table level is assumed to be
+ * formed from n pages.
+ *
+ * tbl: location of page table
+ * rtbl: address to be used for first level page table entry (typically tbl + PAGE_SIZE)
+ * vstart: start address to map
+ * vend: end address to map - we map [vstart, vend]
+ * flags: flags to use to map last level entries
+ * phys: physical address corresponding to vstart - physical memory is contiguous
+ * pgds: the number of pgd entries
+ *
+ * Temporaries: istart, iend, tmp, count, sv - these need to be different registers
+ * Preserves: vstart, vend, flags
+ * Corrupts: tbl, rtbl, istart, iend, tmp, count, sv
+ */
+ .macro map_memory, tbl, rtbl, vstart, vend, flags, phys, pgds, istart, iend, tmp, count, sv
+ add \rtbl, \tbl, #PAGE_SIZE
+ mov \sv, \rtbl
+ mov \count, #1
+ compute_indices \vstart, \vend, #PGDIR_SHIFT, \pgds, \istart, \iend, \count
+ populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
+ mov \tbl, \sv
+ mov \sv, \rtbl
+
+#if SWAPPER_PGTABLE_LEVELS > 3
+ compute_indices \vstart, \vend, #PUD_SHIFT, #PTRS_PER_PUD, \istart, \iend, \count
+ populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
+ mov \tbl, \sv
+ mov \sv, \rtbl
+#endif
+
+#if SWAPPER_PGTABLE_LEVELS > 2
+ compute_indices \vstart, \vend, #SWAPPER_TABLE_SHIFT, #PTRS_PER_PMD, \istart, \iend, \count
+ populate_entries \tbl, \rtbl, \istart, \iend, #PMD_TYPE_TABLE, #PAGE_SIZE, \tmp
+ mov \tbl, \sv
+#endif
+
+ compute_indices \vstart, \vend, #SWAPPER_BLOCK_SHIFT, #PTRS_PER_PTE, \istart, \iend, \count
+ bic \count, \phys, #SWAPPER_BLOCK_SIZE - 1
+ populate_entries \tbl, \count, \istart, \iend, \flags, #SWAPPER_BLOCK_SIZE, \tmp
.endm
/*
@@ -246,14 +312,16 @@ __create_page_tables:
* dirty cache lines being evicted.
*/
adrp x0, idmap_pg_dir
- ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ adrp x1, swapper_pg_end
+ sub x1, x1, x0
bl __inval_dcache_area
/*
* Clear the idmap and swapper page tables.
*/
adrp x0, idmap_pg_dir
- ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ adrp x1, swapper_pg_end
+ sub x1, x1, x0
1: stp xzr, xzr, [x0], #16
stp xzr, xzr, [x0], #16
stp xzr, xzr, [x0], #16
@@ -318,10 +386,10 @@ __create_page_tables:
#endif
1:
ldr_l x4, idmap_ptrs_per_pgd
- create_pgd_entry x0, x3, x4, x5, x6
mov x5, x3 // __pa(__idmap_text_start)
adr_l x6, __idmap_text_end // __pa(__idmap_text_end)
- create_block_map x0, x7, x3, x5, x6, x4
+
+ map_memory x0, x1, x3, x6, x7, x3, x4, x10, x11, x12, x13, x14
/*
* Map the kernel image (starting with PHYS_OFFSET).
@@ -330,12 +398,12 @@ __create_page_tables:
mov_q x5, KIMAGE_VADDR + TEXT_OFFSET // compile time __va(_text)
add x5, x5, x23 // add KASLR displacement
mov x4, PTRS_PER_PGD
- create_pgd_entry x0, x5, x4, x3, x6
adrp x6, _end // runtime __pa(_end)
adrp x3, _text // runtime __pa(_text)
sub x6, x6, x3 // _end - _text
add x6, x6, x5 // runtime __va(_end)
- create_block_map x0, x7, x3, x5, x6, x4
+
+ map_memory x0, x1, x5, x6, x7, x3, x4, x10, x11, x12, x13, x14
/*
* Since the page tables have been populated with non-cacheable
@@ -343,7 +411,8 @@ __create_page_tables:
* tables again to remove any speculatively loaded cache lines.
*/
adrp x0, idmap_pg_dir
- ldr x1, =(IDMAP_DIR_SIZE + SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ adrp x1, swapper_pg_end
+ sub x1, x1, x0
dmb sy
bl __inval_dcache_area
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 4c7112a47469..0221aca6493d 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -230,6 +230,7 @@ SECTIONS
#endif
swapper_pg_dir = .;
. += SWAPPER_DIR_SIZE;
+ swapper_pg_end = .;
__pecoff_data_size = ABSOLUTE(. - __initdata_begin);
_end = .;
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 4071602031ed..fdac11979bae 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -644,7 +644,8 @@ void __init paging_init(void)
* allocated with it.
*/
memblock_free(__pa_symbol(swapper_pg_dir) + PAGE_SIZE,
- SWAPPER_DIR_SIZE - PAGE_SIZE);
+ __pa_symbol(swapper_pg_end) - __pa_symbol(swapper_pg_dir)
+ - PAGE_SIZE);
}
/*
--
2.11.0
^ permalink raw reply related
* [PATCH V3 2/3] arm64: entry: Move the trampoline to be before PAN
From: Steve Capper @ 2018-01-02 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180102151254.4063-1-steve.capper@arm.com>
The trampline page tables are positioned after the early page tables in
the kernel linker script.
As we are about to change the early page table logic to resolve the
swapper size at link time as opposed to compile time, the
SWAPPER_DIR_SIZE variable (currently used to locate the trampline)
will be rendered unsuitable for low level assembler.
This patch solves this issue by moving the trampoline before the PAN
page tables. The offset to the trampoline from ttbr1 can then be
expressed by: PAGE_SIZE + RESERVED_TTBR0_SIZE, which is available to the
entry assembler.
Signed-off-by: Steve Capper <steve.capper@arm.com>
---
Patch added in V3 of the series to allow it to work with kpti.
---
arch/arm64/kernel/entry.S | 4 ++--
arch/arm64/kernel/vmlinux.lds.S | 11 ++++++-----
2 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 031392ee5f47..7902d8145b9a 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -987,7 +987,7 @@ __ni_sys_trace:
.macro tramp_map_kernel, tmp
mrs \tmp, ttbr1_el1
- sub \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ add \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
bic \tmp, \tmp, #USER_ASID_FLAG
msr ttbr1_el1, \tmp
#ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
@@ -1006,7 +1006,7 @@ alternative_else_nop_endif
.macro tramp_unmap_kernel, tmp
mrs \tmp, ttbr1_el1
- add \tmp, \tmp, #(SWAPPER_DIR_SIZE + RESERVED_TTBR0_SIZE)
+ sub \tmp, \tmp, #(PAGE_SIZE + RESERVED_TTBR0_SIZE)
orr \tmp, \tmp, #USER_ASID_FLAG
msr ttbr1_el1, \tmp
/*
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index 8e567de8f369..4c7112a47469 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -218,6 +218,12 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
idmap_pg_dir = .;
. += IDMAP_DIR_SIZE;
+
+#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
+ tramp_pg_dir = .;
+ . += PAGE_SIZE;
+#endif
+
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
reserved_ttbr0 = .;
. += RESERVED_TTBR0_SIZE;
@@ -225,11 +231,6 @@ SECTIONS
swapper_pg_dir = .;
. += SWAPPER_DIR_SIZE;
-#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
- tramp_pg_dir = .;
- . += PAGE_SIZE;
-#endif
-
__pecoff_data_size = ABSOLUTE(. - __initdata_begin);
_end = .;
--
2.11.0
^ permalink raw reply related
* [PATCH V3 1/3] arm64: Re-order reserved_ttbr0 in linker script
From: Steve Capper @ 2018-01-02 15:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180102151254.4063-1-steve.capper@arm.com>
Currently one resolves the location of the reserved_ttbr0 for PAN by
taking a positive offset from swapper_pg_dir. In a future patch we wish
to extend the swapper s.t. its size is determined at link time rather
than comile time, rendering SWAPPER_DIR_SIZE unsuitable for such a low
level calculation.
In this patch we re-arrange the order of the linker script s.t. instead
one computes reserved_ttbr0 by subtracting RESERVED_TTBR0_SIZE from
swapper_pg_dir.
Signed-off-by: Steve Capper <steve.capper@arm.com>
---
Changed in V3: corrected comment, added Ard's reviewed-by,
Rebased on top of kpti
Ard, Mark, I removed your tags because I had to add a change for
asm-uaccess.h. Please let me know if it's okay for me to put your tags
back?
Cheers,
--
Steve
---
arch/arm64/include/asm/asm-uaccess.h | 8 ++++----
arch/arm64/include/asm/uaccess.h | 4 ++--
arch/arm64/kernel/vmlinux.lds.S | 5 ++---
3 files changed, 8 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
index f4f234b6155e..8719ce122a38 100644
--- a/arch/arm64/include/asm/asm-uaccess.h
+++ b/arch/arm64/include/asm/asm-uaccess.h
@@ -13,11 +13,11 @@
*/
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
.macro __uaccess_ttbr0_disable, tmp1
- mrs \tmp1, ttbr1_el1 // swapper_pg_dir
- add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir
- msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
+ mrs \tmp1, ttbr1_el1 // swapper_pg_dir
+ sub \tmp1, \tmp1, #RESERVED_TTBR0_SIZE // reserved_ttbr0 just before swapper_pg_dir
+ msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
isb
- sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE
+ add \tmp1, \tmp1, #RESERVED_TTBR0_SIZE
bic \tmp1, \tmp1, #TTBR_ASID_MASK
msr ttbr1_el1, \tmp1 // set reserved ASID
isb
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 6eadf55ebaf0..e269d35372cf 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -108,8 +108,8 @@ static inline void __uaccess_ttbr0_disable(void)
unsigned long ttbr;
ttbr = read_sysreg(ttbr1_el1);
- /* reserved_ttbr0 placed at the end of swapper_pg_dir */
- write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1);
+ /* reserved_ttbr0 placed before swapper_pg_dir */
+ write_sysreg(ttbr - RESERVED_TTBR0_SIZE, ttbr0_el1);
isb();
/* Set reserved ASID */
ttbr &= ~TTBR_ASID_MASK;
diff --git a/arch/arm64/kernel/vmlinux.lds.S b/arch/arm64/kernel/vmlinux.lds.S
index ddfd3c0942f7..8e567de8f369 100644
--- a/arch/arm64/kernel/vmlinux.lds.S
+++ b/arch/arm64/kernel/vmlinux.lds.S
@@ -218,13 +218,12 @@ SECTIONS
. = ALIGN(PAGE_SIZE);
idmap_pg_dir = .;
. += IDMAP_DIR_SIZE;
- swapper_pg_dir = .;
- . += SWAPPER_DIR_SIZE;
-
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
reserved_ttbr0 = .;
. += RESERVED_TTBR0_SIZE;
#endif
+ swapper_pg_dir = .;
+ . += SWAPPER_DIR_SIZE;
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
tramp_pg_dir = .;
--
2.11.0
^ permalink raw reply related
* [PATCH V3 0/3] Map larger kernels at early init
From: Steve Capper @ 2018-01-02 15:12 UTC (permalink / raw)
To: linux-arm-kernel
The early pagetable creation code assumes that a single pgd, pud, pmd
and pte are sufficient to map the kernel text for MMU bringup. For 16KB
granules this is, unfortunately, rarely the case. Some kernels may be too
big even for a 64KB granule employing this scheme.
This patch series addresses the problem in three steps: 1) re-order the
reserved_ttbr0 to allow its address computation to be independent of
swapper_pg_dir size, 2) re-order the trampoline in a similar manner,
and 3) re-write the early pgtable code to allow for multiple page table
entries at each level.
Changes in v3: Series rebased on top of arm64/for-next/core branch. This
necessitated changes to accommodate kpti (mainly moving the trampiline page
table before the swapper, in patch #2); as well as 52-bit PA (some assembler
rebasing).
Changes in v2: Ack added to patch #1, KASLR space calculation redone
in patch #2.
Steve Capper (3):
arm64: Re-order reserved_ttbr0 in linker script
arm64: entry: Move the trampoline to be before PAN
arm64: Extend early page table code to allow for larger kernels
arch/arm64/include/asm/asm-uaccess.h | 8 +-
arch/arm64/include/asm/kernel-pgtable.h | 47 ++++++++++-
arch/arm64/include/asm/pgtable.h | 1 +
arch/arm64/include/asm/uaccess.h | 4 +-
arch/arm64/kernel/entry.S | 4 +-
arch/arm64/kernel/head.S | 145 +++++++++++++++++++++++---------
arch/arm64/kernel/vmlinux.lds.S | 15 ++--
arch/arm64/mm/mmu.c | 3 +-
8 files changed, 172 insertions(+), 55 deletions(-)
--
2.11.0
^ permalink raw reply
* [Cluster-devel] [PATCH 00/12] drop unneeded newline
From: Bart Van Assche @ 2018-01-02 15:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <alpine.DEB.2.20.1801021458360.24055@hadrien>
On Tue, 2018-01-02 at 15:00 +0100, Julia Lawall wrote:
> On Tue, 2 Jan 2018, Bob Peterson wrote:
> > ----- Original Message -----
> > > ----- Original Message -----
> > >
> > Still, the GFS2 and DLM code has a plethora of broken-up printk messages,
> > and I don't like the thought of re-combining them all.
>
> Actually, the point of the patch was to remove the unnecessary \n at the
> end of the string, because log_print will add another one. If you prefer
> to keep the string broken up, I can resend the patch in that form, but
> without the unnecessary \n.
Please combine any user-visible strings into a single line for which the
unneeded newline is dropped since these strings are modified anyway by
your patch.
Thanks,
Bart.
^ permalink raw reply
* [PATCH] arm64: dts: marvell: armada-37xx: add a crypto node
From: Gregory CLEMENT @ 2018-01-02 15:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226161653.4601-1-antoine.tenart@free-electrons.com>
Hi Antoine,
On mar., d?c. 26 2017, Antoine Tenart <antoine.tenart@free-electrons.com> wrote:
> This patch adds a crypto node describing the EIP97 engine found in
> Armada 37xx SoCs. The cryptographic engine is enabled by default.
>
> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Applied on mvebu/dt64
Thanks,
Gregory
> ---
> arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> index 90c26d616a54..4c4b7a2fb162 100644
> --- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
> @@ -309,6 +309,20 @@
> };
> };
>
> + crypto: crypto at 90000 {
> + compatible = "inside-secure,safexcel-eip97";
> + reg = <0x90000 0x20000>;
> + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "mem", "ring0", "ring1",
> + "ring2", "ring3", "eip";
> + clocks = <&nb_periph_clk 15>;
> + };
> +
> sdhci1: sdhci at d0000 {
> compatible = "marvell,armada-3700-sdhci",
> "marvell,sdhci-xenon";
> --
> 2.14.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v4 0/7] ARM: davinci: convert to common clock framework
From: Adam Ford @ 2018-01-02 15:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514763588-31560-1-git-send-email-david@lechnology.com>
On Sun, Dec 31, 2017 at 5:39 PM, David Lechner <david@lechnology.com> wrote:
> This series converts mach-davinci to use the common clock framework.
>
> Basically, this series does some cleanup and rearranging to get things
> ready for the conversion. Then there is a patch to add new driver in
> drivers/clk and finally a patch to make the conversion from the mach
> clock drivers to the new drivers.
>
> I have tested this on LEGO MINDSTORMS EV3 (TI AM1808), so I am confident
> that I haven't broken anything (too badly) in da850. But, I don't have
> other hardware to test.
I tested this on a DA850-EVM, but I was not able to successfully get it to boot.
It hangs during boot with no errors, oops's, or panics, but the
standard 4.15.0-rc5 from linux-stable booted just fine.
Maybe one of the TI guys will have some suggestions, but as-is, it
appears to break at least the DA850-evm.
>
> The one thing that I know I have broken is CPU frequency scaling on da850.
> I don't think it was working with device tree anyway, so I can't really test
> it with the hardware I have. I'm hoping that it will be OK to defer fixing
> it and add device tree support at the same time.
>
I agree with you that it's broken in the device tree, but I don't
think it ever worked.
> Dependencies:
> * This series applies on top of "ARM: davinici: move watchdog restart from
> mach to drivers" [1][2]
> * On da850, you will also need a patch to prevent problems with the USB PHY
> clocks [3]
> * Or get it all at once:
> git fetch https://github.com/dlech/ev3dev-kernel.git common-clk-v4
That is what I pulled to test.
adam
>
> [1]: https://patchwork.kernel.org/patch/10105623/
> [2]: https://patchwork.kernel.org/patch/10105613/
> [3]: https://patchwork.kernel.org/patch/10133193/
>
>
> v4 changes:
> * Basically, the whole series is new/reworked except for the first patch.
> * Instead of having an intermediate conversion of the clocks in mach-davinci,
> new clock drivers are introduced in drivers/clk.
> * There are a few more cleanup patches added before making the conversion.
>
> v3 changes:
> * Remove leftovers from rebasing in "ARM: davinci: don't use static clk_lookup"
> (fixes compile error)
>
> v2 changes:
> * Dropped "ARM: davinci: clean up map_io functions" - will resend as separate
> patch series
> * Reworked remaining patches so that there is less shuffling around
>
>
>
> David Lechner (7):
> ARM: davinci: move davinci_clk_init() to init_time
> ARM: davinci: don't use static clk_lookup
> ARM: davinci: fix duplicate clocks
> ARM: davinci: remove davinci_set_refclk_rate()
> clk: Introduce davinci clocks
> ARM: davinci: convert to common clock framework
> ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS
>
> arch/arm/Kconfig | 2 +-
> arch/arm/configs/davinci_all_defconfig | 1 -
> arch/arm/mach-davinci/Kconfig | 12 -
> arch/arm/mach-davinci/Makefile | 2 +-
> arch/arm/mach-davinci/board-da830-evm.c | 17 +-
> arch/arm/mach-davinci/board-da850-evm.c | 2 +-
> arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
> arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
> arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
> arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
> arch/arm/mach-davinci/board-dm646x-evm.c | 17 +-
> arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
> arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
> arch/arm/mach-davinci/board-omapl138-hawk.c | 17 +-
> arch/arm/mach-davinci/board-sffsdr.c | 2 +-
> arch/arm/mach-davinci/clock.c | 745 --------------------------
> arch/arm/mach-davinci/clock.h | 72 ---
> arch/arm/mach-davinci/common.c | 1 -
> arch/arm/mach-davinci/da830.c | 536 +++++--------------
> arch/arm/mach-davinci/da850.c | 785 ++++++----------------------
> arch/arm/mach-davinci/da8xx-dt.c | 17 +-
> arch/arm/mach-davinci/davinci.h | 4 +
> arch/arm/mach-davinci/devices-da8xx.c | 46 +-
> arch/arm/mach-davinci/dm355.c | 452 ++++------------
> arch/arm/mach-davinci/dm365.c | 594 ++++++---------------
> arch/arm/mach-davinci/dm644x.c | 401 ++++----------
> arch/arm/mach-davinci/dm646x.c | 451 +++++-----------
> arch/arm/mach-davinci/include/mach/clock.h | 3 -
> arch/arm/mach-davinci/include/mach/common.h | 9 -
> arch/arm/mach-davinci/include/mach/da8xx.h | 11 +-
> arch/arm/mach-davinci/psc.c | 137 -----
> arch/arm/mach-davinci/psc.h | 14 -
> arch/arm/mach-davinci/usb-da8xx.c | 225 +-------
> drivers/clk/Makefile | 1 +
> drivers/clk/davinci/Makefile | 3 +
> drivers/clk/davinci/da8xx-cfgchip-clk.c | 380 ++++++++++++++
> drivers/clk/davinci/pll.c | 333 ++++++++++++
> drivers/clk/davinci/psc.c | 217 ++++++++
> include/linux/clk/davinci.h | 46 ++
> include/linux/platform_data/davinci_clk.h | 25 +
> 40 files changed, 1875 insertions(+), 3717 deletions(-)
> delete mode 100644 arch/arm/mach-davinci/clock.c
> delete mode 100644 arch/arm/mach-davinci/psc.c
> create mode 100644 drivers/clk/davinci/Makefile
> create mode 100644 drivers/clk/davinci/da8xx-cfgchip-clk.c
> create mode 100644 drivers/clk/davinci/pll.c
> create mode 100644 drivers/clk/davinci/psc.c
> create mode 100644 include/linux/clk/davinci.h
> create mode 100644 include/linux/platform_data/davinci_clk.h
>
> --
> 2.7.4
>
^ permalink raw reply
* [net-next: PATCH v2 5/5] net: mvpp2: enable ACPI support in the driver
From: Marcin Wojtas @ 2018-01-02 15:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180102140852.GE15036@lunn.ch>
2018-01-02 15:08 GMT+01:00 Andrew Lunn <andrew@lunn.ch>:
>> Indeed in of_mdio_bus_register_phy, there is of_irq_get. This is more
>> a discussion for a MDIO bus / ACPI patchset, but we either find a way
>> to use IRQs with ACPI obtained from child nodes or for this world the
>> functionality will be limited (at least for the beginning).
>
> Hi Marcin
>
> What i want to avoid is adding something which partially works, and
> then have to throw it all away and start again in order to add full
> support.
>
> If ACPI really limits interrupts to devices, maybe we need a totally
> different representation of MDIO and PHYs in ACPI to what it used in
> device tree? The same may be true for the Ethernet ports of the mvpp2?
> They might have to be represented as real devices, not children of a
> device? Maybe trying to map DT to ACPI on a one-to-one basis is the
> wrong approach?
>
In terms of PP2 controller, I'd prefer to keep as much as possible to
describing how real hardware looks like, i.e. single common controller
with multiple ports as its children. Those considerations are
reflected in the DT description shape and how the driver enumerates,
which was part of the design of the initial support. Bending the
driver (huge amount of shared initialization and resources) to
multiple instances just for the sake of possible avoidance of IRQ
description in ACPI is IMO a huge and unnecessary overkill.
Anyway, I'll do a more research on the resources / ACPI representation
and will get back with some conclusions. I hope that someone from this
thread recipents will be able to give some advice too :)
Best regards,
Marcin
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6ul: add 696MHz operating point
From: Fabio Estevam @ 2018-01-02 15:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514912859-17691-1-git-send-email-Anson.Huang@nxp.com>
Hi Anson,
On Tue, Jan 2, 2018 at 3:07 PM, Anson Huang <Anson.Huang@nxp.com> wrote:
> Add 696MHz operating point according to datasheet
> (Rev. 0, 12/2015).
There is a newer version from 05/2017:
https://www.nxp.com/docs/en/data-sheet/IMX6ULAEC.pdf
>
> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> ---
> arch/arm/boot/dts/imx6ul.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
> index e0b4a46..86b3251 100644
> --- a/arch/arm/boot/dts/imx6ul.dtsi
> +++ b/arch/arm/boot/dts/imx6ul.dtsi
> @@ -68,12 +68,14 @@
> clock-latency = <61036>; /* two CLK32 periods */
> operating-points = <
> /* kHz uV */
> + 696000 1275000
> 528000 1175000
> 396000 1025000
> 198000 950000
> >;
> fsl,soc-operating-points = <
> /* KHz uV */
> + 696000 1275000
Why 1.275V?
According to the datasheet, the minimum value for VDD_SOC_CAP is 1.15V
for all frequencies.
Adding 25mV of margin leads to 1.175V.
^ permalink raw reply
* [PATCH v3 7/7] ARM: dts: stm32: add initial support of stm32mp157c eval board
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905311-12925-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
Add support of stm32mp157c evaluation board (part number: STM32MP157C-EV1)
split in 2 elements:
-Daughter board (part number: STM32MP157C-ED1)
which includes CPU, memory and power supply
-Mother board (part number: STM32MP157C-EM1)
which includes external peripherals (like display, camera,...)
and extension connectors.
The daughter board can run alone, this is why the device tree files
are split in two layers, for the complete evaluation board (ev1)
and for the daughter board alone (ed1).
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
---
arch/arm/boot/dts/Makefile | 6 ++++--
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 13 +++++++++++++
arch/arm/boot/dts/stm32mp157c-ed1.dts | 28 ++++++++++++++++++++++++++++
arch/arm/boot/dts/stm32mp157c-ev1.dts | 18 ++++++++++++++++++
4 files changed, 63 insertions(+), 2 deletions(-)
create mode 100644 arch/arm/boot/dts/stm32mp157c-ed1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d0381e9..d72c71c 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -839,7 +839,7 @@ dtb-$(CONFIG_ARCH_STI) += \
stih410-b2120.dtb \
stih410-b2260.dtb \
stih418-b2199.dtb
-dtb-$(CONFIG_ARCH_STM32)+= \
+dtb-$(CONFIG_ARCH_STM32) += \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
stm32f746-disco.dtb \
@@ -847,7 +847,9 @@ dtb-$(CONFIG_ARCH_STM32)+= \
stm32429i-eval.dtb \
stm32746g-eval.dtb \
stm32h743i-eval.dtb \
- stm32h743i-disco.dtb
+ stm32h743i-disco.dtb \
+ stm32mp157c-ed1.dtb \
+ stm32mp157c-ev1.dtb
dtb-$(CONFIG_MACH_SUN4I) += \
sun4i-a10-a1000.dtb \
sun4i-a10-ba10-tvbox.dtb \
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
index 440276a..7ac65f4 100644
--- a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -145,6 +145,19 @@
ngpios = <8>;
gpio-ranges = <&pinctrl 0 160 8>;
};
+
+ uart4_pins_a: uart4 at 0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('G', 11, AF6)>; /* UART4_TX */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <0>;
+ };
+ pins2 {
+ pinmux = <STM32_PINMUX('B', 2, AF8)>; /* UART4_RX */
+ bias-disable;
+ };
+ };
};
pinctrl_z: pin-controller-z {
diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts
new file mode 100644
index 0000000..78ccdd3
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157c.dtsi"
+#include "stm32mp157-pinctrl.dtsi"
+
+/ {
+ model = "STMicroelectronics STM32MP157C eval daughter";
+ compatible = "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+
+ memory {
+ reg = <0xC0000000 0x40000000>;
+ };
+};
+
+&uart4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart4_pins_a>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts
new file mode 100644
index 0000000..42e1769b
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+/dts-v1/;
+
+#include "stm32mp157c-ed1.dts"
+
+/ {
+ model = "STMicroelectronics STM32MP157C eval daughter on eval mother";
+ compatible = "st,stm32mp157c-ev1", "st,stm32mp157c-ed1", "st,stm32mp157";
+
+ chosen {
+ stdout-path = "serial3:115200n8";
+ };
+};
+
--
2.7.4
^ permalink raw reply related
* [PATCH v3 6/7] ARM: dts: stm32: add stm32mp157c initial support
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905311-12925-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
Add stm32mp157c initial support with:
-Dual Cortex-A7
-Arm psci, timer, gic
-Pinctrl
-Uart
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 172 ++++++++++++++++++++++++++++++
arch/arm/boot/dts/stm32mp157c.dtsi | 139 ++++++++++++++++++++++++
2 files changed, 311 insertions(+)
create mode 100644 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp157c.dtsi
diff --git a/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
new file mode 100644
index 0000000..440276a
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
@@ -0,0 +1,172 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/pinctrl/stm32-pinfunc.h>
+
+/ {
+ soc {
+ pinctrl: pin-controller {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-pinctrl";
+ ranges = <0 0x50002000 0xa400>;
+ pins-are-numbered;
+
+ gpioa: gpio at 50002000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x0 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOA";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 0 16>;
+ };
+
+ gpiob: gpio at 50003000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x1000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOB";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 16 16>;
+ };
+
+ gpioc: gpio at 50004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x2000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOC";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 32 16>;
+ };
+
+ gpiod: gpio at 50005000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x3000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOD";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 48 16>;
+ };
+
+ gpioe: gpio at 50006000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x4000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOE";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 64 16>;
+ };
+
+ gpiof: gpio at 50007000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x5000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOF";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 80 16>;
+ };
+
+ gpiog: gpio at 50008000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x6000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOG";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 96 16>;
+ };
+
+ gpioh: gpio at 50009000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x7000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOH";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 112 16>;
+ };
+
+ gpioi: gpio at 5000a000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x8000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOI";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 128 16>;
+ };
+
+ gpioj: gpio at 5000b000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x9000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOJ";
+ ngpios = <16>;
+ gpio-ranges = <&pinctrl 0 144 16>;
+ };
+
+ gpiok: gpio at 5000c000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0xa000 0x400>;
+ clocks = <&clk_pll3_p>;
+ st,bank-name = "GPIOK";
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl 0 160 8>;
+ };
+ };
+
+ pinctrl_z: pin-controller-z {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stm32mp157-z-pinctrl";
+ ranges = <0 0x54004000 0x400>;
+ pins-are-numbered;
+ status = "disabled";
+
+ gpioz: gpio at 54004000 {
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0 0x400>;
+ clocks = <&clk_pll2_p>;
+ st,bank-name = "GPIOZ";
+ st,bank-ioport = <11>;
+ ngpios = <8>;
+ gpio-ranges = <&pinctrl_z 0 400 8>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
new file mode 100644
index 0000000..93dbcac
--- /dev/null
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
+/*
+ * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
+ * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
+ */
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <0>;
+ };
+
+ cpu1: cpu at 1 {
+ compatible = "arm,cortex-a7";
+ device_type = "cpu";
+ reg = <1>;
+ };
+ };
+
+ psci {
+ compatible = "arm,psci";
+ method = "smc";
+ cpu_off = <0x84000002>;
+ cpu_on = <0x84000003>;
+ };
+
+ aliases {
+ gpio0 = &gpioa;
+ gpio1 = &gpiob;
+ gpio2 = &gpioc;
+ gpio3 = &gpiod;
+ gpio4 = &gpioe;
+ gpio5 = &gpiof;
+ gpio6 = &gpiog;
+ gpio7 = &gpioh;
+ gpio8 = &gpioi;
+ gpio9 = &gpioj;
+ gpio10 = &gpiok;
+ serial3 = &uart4;
+ };
+
+ intc: interrupt-controller at a0021000 {
+ compatible = "arm,cortex-a7-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xa0021000 0x1000>,
+ <0xa0022000 0x2000>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ interrupt-parent = <&intc>;
+ };
+
+ clocks {
+ clk_hse: clk-hse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+
+ clk_pll_per: clk-pll-per {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_hsi: clk-hsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <64000000>;
+ };
+
+ clk_lse: clk-lse {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ clk_lsi: clk-lsi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32000>;
+ };
+
+ clk_csi: clk-csi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <4000000>;
+ };
+
+ clk_pclk1: clk-pclk1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <86000000>;
+ };
+
+ clk_pll3_p: clk-pll3_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <172000000>;
+ };
+
+ clk_pll2_p: clk-pll2_p {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <264000000>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+
+ uart4: serial at 40010000 {
+ compatible = "st,stm32h7-uart";
+ reg = <0x40010000 0x400>;
+ interrupts = <GIC_SPI 52 IRQ_TYPE_NONE>;
+ clocks = <&clk_pclk1>;
+ status = "disabled";
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 5/7] ARM: configs: multi_v7: add stm32 support
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905311-12925-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch adds stm32 support to multi_v7_defconfig
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
arch/arm/configs/multi_v7_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 11e648a..a0163e7 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -77,6 +77,7 @@ CONFIG_ARCH_SPEAR13XX=y
CONFIG_MACH_SPEAR1310=y
CONFIG_MACH_SPEAR1340=y
CONFIG_ARCH_STI=y
+CONFIG_ARCH_STM32=y
CONFIG_ARCH_EXYNOS=y
CONFIG_EXYNOS5420_MCPM=y
CONFIG_ARCH_RENESAS=y
@@ -324,6 +325,8 @@ CONFIG_SERIAL_CONEXANT_DIGICOLOR=y
CONFIG_SERIAL_CONEXANT_DIGICOLOR_CONSOLE=y
CONFIG_SERIAL_ST_ASC=y
CONFIG_SERIAL_ST_ASC_CONSOLE=y
+CONFIG_SERIAL_STM32=y
+CONFIG_SERIAL_STM32_CONSOLE=y
CONFIG_VIRTIO_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_HW_RANDOM_ST=y
--
2.7.4
^ permalink raw reply related
* [PATCH v3 4/7] ARM: stm32: add initial support for STM32MP157
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905311-12925-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch adds initial support of STM32MP157 microprocessor (MPU)
based on Arm Cortex-A7. New Cortex-A infrastructure (gic, timer,...)
are selected if ARCH_MULTI_V7 is defined.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
Documentation/arm/stm32/stm32mp157-overview.rst | 19 +++++++++++++++++++
arch/arm/mach-stm32/Kconfig | 11 +++++++++++
arch/arm/mach-stm32/board-dt.c | 1 +
3 files changed, 31 insertions(+)
create mode 100644 Documentation/arm/stm32/stm32mp157-overview.rst
diff --git a/Documentation/arm/stm32/stm32mp157-overview.rst b/Documentation/arm/stm32/stm32mp157-overview.rst
new file mode 100644
index 0000000..62e176d
--- /dev/null
+++ b/Documentation/arm/stm32/stm32mp157-overview.rst
@@ -0,0 +1,19 @@
+STM32MP157 Overview
+===================
+
+Introduction
+------------
+
+The STM32MP157 is a Cortex-A MPU aimed at various applications.
+It features:
+
+- Dual core Cortex-A7 application core
+- 2D/3D image composition with GPU
+- Standard memories interface support
+- Standard connectivity, widely inherited from the STM32 MCU family
+- Comprehensive security support
+
+:Authors:
+
+- Ludovic Barre <ludovic.barre@st.com>
+- Gerald Baeza <gerald.baeza@st.com>
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index fb4b8b8..6b65df1 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -1,6 +1,9 @@
menuconfig ARCH_STM32
bool "STMicroelectronics STM32 family" if ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
+ select HAVE_ARM_ARCH_TIMER if ARCH_MULTI_V7
+ select ARM_GIC if ARCH_MULTI_V7
+ select ARM_PSCI if ARCH_MULTI_V7
select ARCH_HAS_RESET_CONTROLLER
select CLKSRC_STM32
select PINCTRL
@@ -31,4 +34,12 @@ config MACH_STM32H743
endif # ARMv7-M
+if ARCH_MULTI_V7
+
+config MACH_STM32MP157
+ bool "STMicroelectronics STM32MP157"
+ default y
+
+endif # ARMv7-A
+
endif
diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
index 4a258eb..d4e58ea 100644
--- a/arch/arm/mach-stm32/board-dt.c
+++ b/arch/arm/mach-stm32/board-dt.c
@@ -12,6 +12,7 @@ static const char *const stm32_compat[] __initconst = {
"st,stm32f469",
"st,stm32f746",
"st,stm32h743",
+ "st,stm32mp157",
NULL
};
--
2.7.4
^ permalink raw reply related
* [PATCH v3 3/7] dt-bindings: stm32: add support of STM32MP157
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905311-12925-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch adds STM32MP157 SoC bindings.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/arm/stm32.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32.txt
index 05762b0..6808ed9 100644
--- a/Documentation/devicetree/bindings/arm/stm32.txt
+++ b/Documentation/devicetree/bindings/arm/stm32.txt
@@ -7,3 +7,4 @@ using one of the following compatible strings:
st,stm32f469
st,stm32f746
st,stm32h743
+ st,stm32mp157
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/7] ARM: stm32: prepare stm32 family to welcome armv7 architecture
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905311-12925-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch prepares the STM32 machine for the integration of Cortex-A
based microprocessor (MPU), on top of the existing Cortex-M
microcontroller family (MCU). Since both MCUs and MPUs are sharing
common hardware blocks we can keep using ARCH_STM32 flag for most of
them. If a hardware block is specific to one family we can use either
ARM_SINGLE_ARMV7M or ARCH_MULTI_V7 flag.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
Documentation/arm/stm32/overview.rst | 15 +++++++++------
arch/arm/mach-stm32/Kconfig | 27 +++++++++++++++------------
arch/arm/mach-stm32/board-dt.c | 4 +---
3 files changed, 25 insertions(+), 21 deletions(-)
diff --git a/Documentation/arm/stm32/overview.rst b/Documentation/arm/stm32/overview.rst
index 6be6059..85cfc84 100644
--- a/Documentation/arm/stm32/overview.rst
+++ b/Documentation/arm/stm32/overview.rst
@@ -5,16 +5,17 @@ STM32 ARM Linux Overview
Introduction
------------
-The STMicroelectronics family of Cortex-M based MCUs are supported by the
-'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
-and STM32F746 (Cortex-M7) are supported.
+The STMicroelectronics STM32 family of Cortex-A microprocessors (MPUs) and
+Cortex-M microcontrollers (MCUs) are supported by the 'STM32' platform of
+ARM Linux.
Configuration
-------------
-A generic configuration is provided for STM32 family, and can be used as the
-default by
+For MCUs, use the provided default configuration:
make stm32_defconfig
+For MPUs, use multi_v7 configuration:
+ make multi_v7_defconfig
Layout
------
@@ -28,4 +29,6 @@ Device Trees.
:Authors:
-Maxime Coquelin <mcoquelin.stm32@gmail.com>
+- Maxime Coquelin <mcoquelin.stm32@gmail.com>
+- Ludovic Barre <ludovic.barre@st.com>
+- Gerald Baeza <gerald.baeza@st.com>
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 0d1889b..fb4b8b8 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -1,8 +1,7 @@
-config ARCH_STM32
- bool "STMicrolectronics STM32"
- depends on ARM_SINGLE_ARMV7M
+menuconfig ARCH_STM32
+ bool "STMicroelectronics STM32 family" if ARM_SINGLE_ARMV7M || ARCH_MULTI_V7
+ select ARMV7M_SYSTICK if ARM_SINGLE_ARMV7M
select ARCH_HAS_RESET_CONTROLLER
- select ARMV7M_SYSTICK
select CLKSRC_STM32
select PINCTRL
select RESET_CONTROLLER
@@ -10,22 +9,26 @@ config ARCH_STM32
help
Support for STMicroelectronics STM32 processors.
+if ARCH_STM32
+
+if ARM_SINGLE_ARMV7M
+
config MACH_STM32F429
- bool "STMicrolectronics STM32F429"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32F429"
default y
config MACH_STM32F469
- bool "STMicrolectronics STM32F469"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32F469"
default y
config MACH_STM32F746
- bool "STMicrolectronics STM32F746"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32F746"
default y
config MACH_STM32H743
- bool "STMicrolectronics STM32H743"
- depends on ARCH_STM32
+ bool "STMicroelectronics STM32H743"
default y
+
+endif # ARMv7-M
+
+endif
diff --git a/arch/arm/mach-stm32/board-dt.c b/arch/arm/mach-stm32/board-dt.c
index e918686..4a258eb 100644
--- a/arch/arm/mach-stm32/board-dt.c
+++ b/arch/arm/mach-stm32/board-dt.c
@@ -1,11 +1,10 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) Maxime Coquelin 2015
* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
- * License terms: GNU General Public License (GPL), version 2
*/
#include <linux/kernel.h>
-#include <asm/v7m.h>
#include <asm/mach/arch.h>
static const char *const stm32_compat[] __initconst = {
@@ -18,5 +17,4 @@ static const char *const stm32_compat[] __initconst = {
DT_MACHINE_START(STM32DT, "STM32 (Device Tree Support)")
.dt_compat = stm32_compat,
- .restart = armv7m_restart,
MACHINE_END
--
2.7.4
^ permalink raw reply related
* [PATCH v3 1/7] Documentation: arm: stm32: move to rst format
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514905311-12925-1-git-send-email-ludovic.Barre@st.com>
From: Ludovic Barre <ludovic.barre@st.com>
This patch rewrites stm32 documentation to rst
(ReStructuredText) format.
Signed-off-by: Ludovic Barre <ludovic.barre@st.com>
---
Documentation/arm/stm32/overview.rst | 31 +++++++++++++++++++++++
Documentation/arm/stm32/overview.txt | 33 -------------------------
Documentation/arm/stm32/stm32f429-overview.rst | 26 ++++++++++++++++++++
Documentation/arm/stm32/stm32f429-overview.txt | 22 -----------------
Documentation/arm/stm32/stm32f746-overview.rst | 33 +++++++++++++++++++++++++
Documentation/arm/stm32/stm32f746-overview.txt | 34 --------------------------
Documentation/arm/stm32/stm32h743-overview.rst | 34 ++++++++++++++++++++++++++
Documentation/arm/stm32/stm32h743-overview.txt | 30 -----------------------
8 files changed, 124 insertions(+), 119 deletions(-)
create mode 100644 Documentation/arm/stm32/overview.rst
delete mode 100644 Documentation/arm/stm32/overview.txt
create mode 100644 Documentation/arm/stm32/stm32f429-overview.rst
delete mode 100644 Documentation/arm/stm32/stm32f429-overview.txt
create mode 100644 Documentation/arm/stm32/stm32f746-overview.rst
delete mode 100644 Documentation/arm/stm32/stm32f746-overview.txt
create mode 100644 Documentation/arm/stm32/stm32h743-overview.rst
delete mode 100644 Documentation/arm/stm32/stm32h743-overview.txt
diff --git a/Documentation/arm/stm32/overview.rst b/Documentation/arm/stm32/overview.rst
new file mode 100644
index 0000000..6be6059
--- /dev/null
+++ b/Documentation/arm/stm32/overview.rst
@@ -0,0 +1,31 @@
+========================
+STM32 ARM Linux Overview
+========================
+
+Introduction
+------------
+
+The STMicroelectronics family of Cortex-M based MCUs are supported by the
+'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
+and STM32F746 (Cortex-M7) are supported.
+
+Configuration
+-------------
+
+A generic configuration is provided for STM32 family, and can be used as the
+default by
+ make stm32_defconfig
+
+Layout
+------
+
+All the files for multiple machine families are located in the platform code
+contained in arch/arm/mach-stm32
+
+There is a generic board board-dt.c in the mach folder which support
+Flattened Device Tree, which means, it works with any compatible board with
+Device Trees.
+
+:Authors:
+
+Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arm/stm32/overview.txt b/Documentation/arm/stm32/overview.txt
deleted file mode 100644
index a03b035..0000000
--- a/Documentation/arm/stm32/overview.txt
+++ /dev/null
@@ -1,33 +0,0 @@
- STM32 ARM Linux Overview
- ========================
-
-Introduction
-------------
-
- The STMicroelectronics family of Cortex-M based MCUs are supported by the
- 'STM32' platform of ARM Linux. Currently only the STM32F429 (Cortex-M4)
- and STM32F746 (Cortex-M7) are supported.
-
-
-Configuration
--------------
-
- A generic configuration is provided for STM32 family, and can be used as the
- default by
- make stm32_defconfig
-
-Layout
-------
-
- All the files for multiple machine families are located in the platform code
- contained in arch/arm/mach-stm32
-
- There is a generic board board-dt.c in the mach folder which support
- Flattened Device Tree, which means, it works with any compatible board with
- Device Trees.
-
-
-Document Author
----------------
-
- Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arm/stm32/stm32f429-overview.rst b/Documentation/arm/stm32/stm32f429-overview.rst
new file mode 100644
index 0000000..18feda9
--- /dev/null
+++ b/Documentation/arm/stm32/stm32f429-overview.rst
@@ -0,0 +1,26 @@
+STM32F429 Overview
+==================
+
+Introduction
+------------
+
+The STM32F429 is a Cortex-M4 MCU aimed at various applications.
+It features:
+
+- ARM Cortex-M4 up to 180MHz with FPU
+- 2MB internal Flash Memory
+- External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
+- I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
+- LCD controller & Camera interface
+- Cryptographic processor
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32F429_).
+
+.. _STM32F429: http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
+
+:Authors:
+
+Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arm/stm32/stm32f429-overview.txt b/Documentation/arm/stm32/stm32f429-overview.txt
deleted file mode 100644
index 5206822..0000000
--- a/Documentation/arm/stm32/stm32f429-overview.txt
+++ /dev/null
@@ -1,22 +0,0 @@
- STM32F429 Overview
- ==================
-
- Introduction
- ------------
- The STM32F429 is a Cortex-M4 MCU aimed at various applications.
- It features:
- - ARM Cortex-M4 up to 180MHz with FPU
- - 2MB internal Flash Memory
- - External memory support through FMC controller (PSRAM, SDRAM, NOR, NAND)
- - I2C, SPI, SAI, CAN, USB OTG, Ethernet controllers
- - LCD controller & Camera interface
- - Cryptographic processor
-
- Resources
- ---------
- Datasheet and reference manual are publicly available on ST website:
- - http://www.st.com/web/en/catalog/mmc/FM141/SC1169/SS1577/LN1806?ecmp=stm32f429-439_pron_pr-ces2014_nov2013
-
- Document Author
- ---------------
- Maxime Coquelin <mcoquelin.stm32@gmail.com>
diff --git a/Documentation/arm/stm32/stm32f746-overview.rst b/Documentation/arm/stm32/stm32f746-overview.rst
new file mode 100644
index 0000000..b5f4b6c
--- /dev/null
+++ b/Documentation/arm/stm32/stm32f746-overview.rst
@@ -0,0 +1,33 @@
+STM32F746 Overview
+==================
+
+Introduction
+------------
+
+The STM32F746 is a Cortex-M7 MCU aimed at various applications.
+It features:
+
+- Cortex-M7 core running up to @216MHz
+- 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
+- FMC controller to connect SDRAM, NOR and NAND memories
+- Dual mode QSPI
+- SD/MMC/SDIO support
+- Ethernet controller
+- USB OTFG FS & HS controllers
+- I2C, SPI, CAN busses support
+- Several 16 & 32 bits general purpose timers
+- Serial Audio interface
+- LCD controller
+- HDMI-CEC
+- SPDIFRX
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32F746_).
+
+.. _STM32F746: http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
+
+:Authors:
+
+Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arm/stm32/stm32f746-overview.txt b/Documentation/arm/stm32/stm32f746-overview.txt
deleted file mode 100644
index cffd2b1c..0000000
--- a/Documentation/arm/stm32/stm32f746-overview.txt
+++ /dev/null
@@ -1,34 +0,0 @@
- STM32F746 Overview
- ==================
-
- Introduction
- ------------
- The STM32F746 is a Cortex-M7 MCU aimed at various applications.
- It features:
- - Cortex-M7 core running up to @216MHz
- - 1MB internal flash, 320KBytes internal RAM (+4KB of backup SRAM)
- - FMC controller to connect SDRAM, NOR and NAND memories
- - Dual mode QSPI
- - SD/MMC/SDIO support
- - Ethernet controller
- - USB OTFG FS & HS controllers
- - I2C, SPI, CAN busses support
- - Several 16 & 32 bits general purpose timers
- - Serial Audio interface
- - LCD controller
- - HDMI-CEC
- - SPDIFRX
-
- Resources
- ---------
- Datasheet and reference manual are publicly available on ST website:
- - http://www.st.com/content/st_com/en/products/microcontrollers/stm32-32-bit-arm-cortex-mcus/stm32f7-series/stm32f7x6/stm32f746ng.html
-
- Document Author
- ---------------
- Alexandre Torgue <alexandre.torgue@st.com>
-
-
-
-
-
diff --git a/Documentation/arm/stm32/stm32h743-overview.rst b/Documentation/arm/stm32/stm32h743-overview.rst
new file mode 100644
index 0000000..3458dc0
--- /dev/null
+++ b/Documentation/arm/stm32/stm32h743-overview.rst
@@ -0,0 +1,34 @@
+STM32H743 Overview
+==================
+
+Introduction
+------------
+
+The STM32H743 is a Cortex-M7 MCU aimed at various applications.
+It features:
+
+- Cortex-M7 core running up to @400MHz
+- 2MB internal flash, 1MBytes internal RAM
+- FMC controller to connect SDRAM, NOR and NAND memories
+- Dual mode QSPI
+- SD/MMC/SDIO support
+- Ethernet controller
+- USB OTFG FS & HS controllers
+- I2C, SPI, CAN busses support
+- Several 16 & 32 bits general purpose timers
+- Serial Audio interface
+- LCD controller
+- HDMI-CEC
+- SPDIFRX
+- DFSDM
+
+Resources
+---------
+
+Datasheet and reference manual are publicly available on ST website (STM32H743_).
+
+.. _STM32H743: http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
+
+:Authors:
+
+Alexandre Torgue <alexandre.torgue@st.com>
diff --git a/Documentation/arm/stm32/stm32h743-overview.txt b/Documentation/arm/stm32/stm32h743-overview.txt
deleted file mode 100644
index 3031cba..0000000
--- a/Documentation/arm/stm32/stm32h743-overview.txt
+++ /dev/null
@@ -1,30 +0,0 @@
- STM32H743 Overview
- ==================
-
- Introduction
- ------------
- The STM32H743 is a Cortex-M7 MCU aimed at various applications.
- It features:
- - Cortex-M7 core running up to @400MHz
- - 2MB internal flash, 1MBytes internal RAM
- - FMC controller to connect SDRAM, NOR and NAND memories
- - Dual mode QSPI
- - SD/MMC/SDIO support
- - Ethernet controller
- - USB OTFG FS & HS controllers
- - I2C, SPI, CAN busses support
- - Several 16 & 32 bits general purpose timers
- - Serial Audio interface
- - LCD controller
- - HDMI-CEC
- - SPDIFRX
- - DFSDM
-
- Resources
- ---------
- Datasheet and reference manual are publicly available on ST website:
- - http://www.st.com/en/microcontrollers/stm32h7x3.html?querycriteria=productId=LN2033
-
- Document Author
- ---------------
- Alexandre Torgue <alexandre.torgue@st.com>
--
2.7.4
^ permalink raw reply related
* [PATCH v3 0/7] ARM: stm32: add initial STM32MPU support
From: Ludovic Barre @ 2018-01-02 15:01 UTC (permalink / raw)
To: linux-arm-kernel
From: Ludovic Barre <ludovic.barre@st.com>
This patch series extends the existing STM32 microcontrollers (MCUs)
family to microprocessors (MPUs). The MPU platform (based on
Arm Cortex-A) is a continuation of the MCU one (based on Arm
Cortex-M) in that it shares a wide number of hardware blocks.
change v3:
-Remove bootargs
-Remove armv7m_restart and Share stm32_compat for mcu/mpu
-Modify stm32 kconfig with Arnd template
-Remove patch below (Linus W: Patch applied)
devicetree: bindings: Document supported STM32 SoC family
pinctrl: stm32: Add STM32MP157 MPU support
change V2:
-Add stm32 documentation in this serie to avoid merge conflict
thread: "https://patchwork.kernel.org/patch/10102573/"
-Split bindings (stm32.txt) to separate patches.
-Remove ARCH_STM32_MCU/MPU flags
-Adopt rst format for Documentation/arm/stm32 files
-s/STMicrolectronics/STMicroelectronics/g
Ludovic Barre (7):
Documentation: arm: stm32: move to rst format
ARM: stm32: prepare stm32 family to welcome armv7 architecture
dt-bindings: stm32: add support of STM32MP157
ARM: stm32: add initial support for STM32MP157
ARM: configs: multi_v7: add stm32 support
ARM: dts: stm32: add stm32mp157c initial support
ARM: dts: stm32: add initial support of stm32mp157c eval board
Documentation/arm/stm32/overview.rst | 34 +++++
Documentation/arm/stm32/overview.txt | 33 -----
Documentation/arm/stm32/stm32f429-overview.rst | 26 ++++
Documentation/arm/stm32/stm32f429-overview.txt | 22 ---
Documentation/arm/stm32/stm32f746-overview.rst | 33 +++++
Documentation/arm/stm32/stm32f746-overview.txt | 34 -----
Documentation/arm/stm32/stm32h743-overview.rst | 34 +++++
Documentation/arm/stm32/stm32h743-overview.txt | 30 ----
Documentation/arm/stm32/stm32mp157-overview.rst | 19 +++
Documentation/devicetree/bindings/arm/stm32.txt | 1 +
arch/arm/boot/dts/Makefile | 6 +-
arch/arm/boot/dts/stm32mp157-pinctrl.dtsi | 185 ++++++++++++++++++++++++
arch/arm/boot/dts/stm32mp157c-ed1.dts | 28 ++++
arch/arm/boot/dts/stm32mp157c-ev1.dts | 18 +++
arch/arm/boot/dts/stm32mp157c.dtsi | 139 ++++++++++++++++++
arch/arm/configs/multi_v7_defconfig | 3 +
arch/arm/mach-stm32/Kconfig | 38 +++--
arch/arm/mach-stm32/board-dt.c | 5 +-
18 files changed, 552 insertions(+), 136 deletions(-)
create mode 100644 Documentation/arm/stm32/overview.rst
delete mode 100644 Documentation/arm/stm32/overview.txt
create mode 100644 Documentation/arm/stm32/stm32f429-overview.rst
delete mode 100644 Documentation/arm/stm32/stm32f429-overview.txt
create mode 100644 Documentation/arm/stm32/stm32f746-overview.rst
delete mode 100644 Documentation/arm/stm32/stm32f746-overview.txt
create mode 100644 Documentation/arm/stm32/stm32h743-overview.rst
delete mode 100644 Documentation/arm/stm32/stm32h743-overview.txt
create mode 100644 Documentation/arm/stm32/stm32mp157-overview.rst
create mode 100644 arch/arm/boot/dts/stm32mp157-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stm32mp157c-ed1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c-ev1.dts
create mode 100644 arch/arm/boot/dts/stm32mp157c.dtsi
--
2.7.4
^ permalink raw reply
* [PATCH v2 8/8] arm64: dts: marvell: replace cpm by cp0, cps by cp1
From: Thomas Petazzoni @ 2018-01-02 14:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180102145558.9773-1-thomas.petazzoni@free-electrons.com>
In preparation for the introduction of more than 2 CPs in upcoming
SoCs, it makes sense to move away from the "CP master" (cpm) and "CP
slave" (cps) naming, and use instead cp0/cp1.
This commit is the result of:
sed 's%cpm%cp0g%' arch/arm64/boot/dts/marvell/*
sed 's%cps%cp1g%' arch/arm64/boot/dts/marvell/*
So it is a purely mechaninal change.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Suggested-by: Hanna Hawa <hannah@marvell.com>
---
arch/arm64/boot/dts/marvell/armada-7040-db.dts | 46 ++++++-------
arch/arm64/boot/dts/marvell/armada-70x0.dtsi | 18 ++---
arch/arm64/boot/dts/marvell/armada-8020.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-8040-db.dts | 80 +++++++++++------------
arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts | 76 ++++++++++-----------
arch/arm64/boot/dts/marvell/armada-8040.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-80x0.dtsi | 34 +++++-----
7 files changed, 129 insertions(+), 129 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-7040-db.dts b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
index 52b5341cb270..44c95b97a422 100644
--- a/arch/arm64/boot/dts/marvell/armada-7040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-7040-db.dts
@@ -61,7 +61,7 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
- cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
+ cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h0-vbus";
regulator-min-microvolt = <5000000>;
@@ -70,7 +70,7 @@
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
- cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
+ cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
regulator-name = "usb3h1-vbus";
regulator-min-microvolt = <5000000>;
@@ -79,14 +79,14 @@
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
- cpm_usb3_0_phy: cpm-usb3-0-phy {
+ cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_0_vbus>;
+ vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
- cpm_usb3_1_phy: cpm-usb3-1-phy {
+ cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_1_vbus>;
+ vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
};
@@ -129,11 +129,11 @@
};
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
@@ -156,7 +156,7 @@
};
};
-&cpm_nand {
+&cp0_nand {
/*
* SPI on CPM and NAND have common pins on this board. We can
* use only one at a time. To enable the NAND (whihch will
@@ -186,7 +186,7 @@
};
-&cpm_spi1 {
+&cp0_spi1 {
status = "okay";
spi-flash at 0 {
@@ -214,17 +214,17 @@
};
};
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
-&cpm_usb3_0 {
- usb-phy = <&cpm_usb3_0_phy>;
+&cp0_usb3_0 {
+ usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
-&cpm_usb3_1 {
- usb-phy = <&cpm_usb3_1_phy>;
+&cp0_usb3_1 {
+ usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
@@ -235,14 +235,14 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <4>;
no-1-8-v;
cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};
-&cpm_mdio {
+&cp0_mdio {
status = "okay";
phy0: ethernet-phy at 0 {
@@ -253,28 +253,28 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
/* Network PHY */
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
- phys = <&cpm_comphy2 0>;
+ phys = <&cp0_comphy2 0>;
};
-&cpm_eth1 {
+&cp0_eth1 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
- phys = <&cpm_comphy0 1>;
+ phys = <&cp0_comphy0 1>;
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
diff --git a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
index 9917cff3dae6..f63b4fbd642b 100644
--- a/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-70x0.dtsi
@@ -46,17 +46,17 @@
/ {
aliases {
- gpio1 = &cpm_gpio1;
- gpio2 = &cpm_gpio2;
- spi1 = &cpm_spi0;
- spi2 = &cpm_spi1;
+ gpio1 = &cp0_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
};
};
/*
* Instantiate the CP110
*/
-#define CP110_NAME cpm
+#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
@@ -74,16 +74,16 @@
#undef CP110_PCIE1_BASE
#undef CP110_PCIE2_BASE
-&cpm_gpio1 {
+&cp0_gpio1 {
status = "okay";
};
-&cpm_gpio2 {
+&cp0_gpio2 {
status = "okay";
};
-&cpm_syscon0 {
- cpm_pinctrl: pinctrl {
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
compatible = "marvell,armada-7k-pinctrl";
nand_pins: nand-pins {
diff --git a/arch/arm64/boot/dts/marvell/armada-8020.dtsi b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
index 0ba0bc942598..3318d6b0214b 100644
--- a/arch/arm64/boot/dts/marvell/armada-8020.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8020.dtsi
@@ -60,6 +60,6 @@
* oscillator so this one is let enabled.
*/
-&cpm_rtc {
+&cp0_rtc {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-db.dts b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
index b1f6cccc5081..13e3209d554a 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-db.dts
@@ -61,46 +61,46 @@
reg = <0x0 0x0 0x0 0x80000000>;
};
- cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus {
+ cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
compatible = "regulator-fixed";
- regulator-name = "cpm-usb3h0-vbus";
+ regulator-name = "cp0-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
};
- cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus {
+ cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
compatible = "regulator-fixed";
- regulator-name = "cpm-usb3h1-vbus";
+ regulator-name = "cp0-usb3h1-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
};
- cpm_usb3_0_phy: cpm-usb3-0-phy {
+ cp0_usb3_0_phy: cp0-usb3-0-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_0_vbus>;
+ vcc-supply = <&cp0_reg_usb3_0_vbus>;
};
- cpm_usb3_1_phy: cpm-usb3-1-phy {
+ cp0_usb3_1_phy: cp0-usb3-1-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cpm_reg_usb3_1_vbus>;
+ vcc-supply = <&cp0_reg_usb3_1_vbus>;
};
- cps_reg_usb3_0_vbus: cps-usb3-0-vbus {
+ cp1_reg_usb3_0_vbus: cp1-usb3-0-vbus {
compatible = "regulator-fixed";
- regulator-name = "cps-usb3h0-vbus";
+ regulator-name = "cp1-usb3h0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&expander1 0 GPIO_ACTIVE_HIGH>;
};
- cps_usb3_0_phy: cps-usb3-0-phy {
+ cp1_usb3_0_phy: cp1-usb3-0-phy {
compatible = "usb-nop-xceiv";
- vcc-supply = <&cps_reg_usb3_0_vbus>;
+ vcc-supply = <&cp1_reg_usb3_0_vbus>;
};
};
@@ -144,16 +144,16 @@
};
/* CON6 on CP0 expansion */
-&cpm_pcie0 {
+&cp0_pcie0 {
status = "okay";
};
/* CON5 on CP0 expansion */
-&cpm_pcie2 {
+&cp0_pcie2 {
status = "okay";
};
-&cpm_i2c0 {
+&cp0_i2c0 {
status = "okay";
clock-frequency = <100000>;
@@ -178,23 +178,23 @@
};
/* CON4 on CP0 expansion */
-&cpm_sata0 {
+&cp0_sata0 {
status = "okay";
};
/* CON9 on CP0 expansion */
-&cpm_usb3_0 {
- usb-phy = <&cpm_usb3_0_phy>;
+&cp0_usb3_0 {
+ usb-phy = <&cp0_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP0 expansion */
-&cpm_usb3_1 {
- usb-phy = <&cpm_usb3_1_phy>;
+&cp0_usb3_1 {
+ usb-phy = <&cp0_usb3_1_phy>;
status = "okay";
};
-&cpm_mdio {
+&cp0_mdio {
status = "okay";
phy1: ethernet-phy at 1 {
@@ -202,42 +202,42 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
-&cpm_eth2 {
+&cp0_eth2 {
status = "okay";
phy = <&phy1>;
phy-mode = "rgmii-id";
};
/* CON6 on CP1 expansion */
-&cps_pcie0 {
+&cp1_pcie0 {
status = "okay";
};
/* CON7 on CP1 expansion */
-&cps_pcie1 {
+&cp1_pcie1 {
status = "okay";
};
/* CON5 on CP1 expansion */
-&cps_pcie2 {
+&cp1_pcie2 {
status = "okay";
};
-&cps_i2c0 {
+&cp1_i2c0 {
status = "okay";
clock-frequency = <100000>;
};
-&cps_spi1 {
+&cp1_spi1 {
status = "okay";
spi-flash at 0 {
@@ -272,14 +272,14 @@
* Proper NAND usage will require DPR-76 to be in position 1-2, which disables
* MDIO signal of CP1.
*/
-&cps_nand {
+&cp1_nand {
num-cs = <1>;
pinctrl-0 = <&nand_pins>, <&nand_rb>;
pinctrl-names = "default";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
marvell,nand-enable-arbiter;
- marvell,system-controller = <&cps_syscon0>;
+ marvell,system-controller = <&cp1_syscon0>;
nand-on-flash-bbt;
partition at 0 {
@@ -297,22 +297,22 @@
};
/* CON4 on CP1 expansion */
-&cps_sata0 {
+&cp1_sata0 {
status = "okay";
};
/* CON9 on CP1 expansion */
-&cps_usb3_0 {
- usb-phy = <&cps_usb3_0_phy>;
+&cp1_usb3_0 {
+ usb-phy = <&cp1_usb3_0_phy>;
status = "okay";
};
/* CON10 on CP1 expansion */
-&cps_usb3_1 {
+&cp1_usb3_1 {
status = "okay";
};
-&cps_mdio {
+&cp1_mdio {
status = "okay";
phy0: ethernet-phy at 0 {
@@ -320,16 +320,16 @@
};
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth0 {
+&cp1_eth0 {
status = "okay";
phy-mode = "10gbase-kr";
};
-&cps_eth1 {
+&cp1_eth1 {
status = "okay";
phy = <&phy0>;
phy-mode = "rgmii-id";
@@ -341,7 +341,7 @@
non-removable;
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
status = "okay";
bus-width = <8>;
non-removable;
diff --git a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
index b3350827ee55..c7aca67bd244 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
+++ b/arch/arm64/boot/dts/marvell/armada-8040-mcbin.dts
@@ -84,9 +84,9 @@
v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 {
compatible = "regulator-fixed";
enable-active-high;
- gpio = <&cpm_gpio2 15 GPIO_ACTIVE_HIGH>;
+ gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_xhci_vbus_pins>;
+ pinctrl-0 = <&cp0_xhci_vbus_pins>;
regulator-name = "v_5v0_usb3_hst_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
@@ -120,17 +120,17 @@
vqmmc-supply = <&v_vddo_h>;
};
-&cpm_i2c0 {
+&cp0_i2c0 {
clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c0_pins>;
+ pinctrl-0 = <&cp0_i2c0_pins>;
status = "okay";
};
-&cpm_i2c1 {
+&cp0_i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_i2c1_pins>;
+ pinctrl-0 = <&cp0_i2c1_pins>;
status = "okay";
i2c-switch at 70 {
@@ -157,9 +157,9 @@
};
};
-&cpm_mdio {
+&cp0_mdio {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_ge_mdio_pins>;
+ pinctrl-0 = <&cp0_ge_mdio_pins>;
status = "okay";
ge_phy: ethernet-phy at 0 {
@@ -167,44 +167,44 @@
};
};
-&cpm_pcie0 {
+&cp0_pcie0 {
pinctrl-names = "default";
- pinctrl-0 = <&cpm_pcie_pins>;
+ pinctrl-0 = <&cp0_pcie_pins>;
num-lanes = <4>;
num-viewport = <8>;
- reset-gpio = <&cpm_gpio1 20 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&cp0_gpio1 20 GPIO_ACTIVE_LOW>;
status = "okay";
};
-&cpm_pinctrl {
- cpm_ge_mdio_pins: ge-mdio-pins {
+&cp0_pinctrl {
+ cp0_ge_mdio_pins: ge-mdio-pins {
marvell,pins = "mpp32", "mpp34";
marvell,function = "ge";
};
- cpm_i2c1_pins: i2c1-pins {
+ cp0_i2c1_pins: i2c1-pins {
marvell,pins = "mpp35", "mpp36";
marvell,function = "i2c1";
};
- cpm_i2c0_pins: i2c0-pins {
+ cp0_i2c0_pins: i2c0-pins {
marvell,pins = "mpp37", "mpp38";
marvell,function = "i2c0";
};
- cpm_xhci_vbus_pins: xhci0-vbus-pins {
+ cp0_xhci_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp47";
marvell,function = "gpio";
};
- cpm_pcie_pins: pcie-pins {
+ cp0_pcie_pins: pcie-pins {
marvell,pins = "mpp52";
marvell,function = "gpio";
};
- cpm_sdhci_pins: sdhci-pins {
+ cp0_sdhci_pins: sdhci-pins {
marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59",
"mpp60", "mpp61";
marvell,function = "sdio";
};
};
-&cpm_xmdio {
+&cp0_xmdio {
status = "okay";
phy0: ethernet-phy at 0 {
@@ -218,83 +218,83 @@
};
};
-&cpm_ethernet {
+&cp0_ethernet {
status = "okay";
};
-&cpm_eth0 {
+&cp0_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy0>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
- phys = <&cpm_comphy4 0>;
+ phys = <&cp0_comphy4 0>;
};
-&cpm_sata0 {
+&cp0_sata0 {
/* CPM Lane 0 - U29 */
status = "okay";
};
-&cpm_sdhci0 {
+&cp0_sdhci0 {
/* U6 */
broken-cd;
bus-width = <4>;
pinctrl-names = "default";
- pinctrl-0 = <&cpm_sdhci_pins>;
+ pinctrl-0 = <&cp0_sdhci_pins>;
status = "okay";
vqmmc-supply = <&v_3_3>;
};
-&cpm_usb3_0 {
+&cp0_usb3_0 {
/* J38? - USB2.0 only */
status = "okay";
};
-&cpm_usb3_1 {
+&cp0_usb3_1 {
/* J38? - USB2.0 only */
status = "okay";
};
-&cps_ethernet {
+&cp1_ethernet {
status = "okay";
};
-&cps_eth0 {
+&cp1_eth0 {
status = "okay";
/* Network PHY */
phy = <&phy8>;
phy-mode = "10gbase-kr";
/* Generic PHY, providing serdes lanes */
- phys = <&cps_comphy4 0>;
+ phys = <&cp1_comphy4 0>;
};
-&cps_eth1 {
+&cp1_eth1 {
/* CPS Lane 0 - J5 (Gigabit RJ45) */
status = "okay";
/* Network PHY */
phy = <&ge_phy>;
phy-mode = "sgmii";
/* Generic PHY, providing serdes lanes */
- phys = <&cps_comphy0 1>;
+ phys = <&cp1_comphy0 1>;
};
-&cps_pinctrl {
- cps_spi1_pins: spi1-pins {
+&cp1_pinctrl {
+ cp1_spi1_pins: spi1-pins {
marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16";
marvell,function = "spi1";
};
};
-&cps_sata0 {
+&cp1_sata0 {
/* CPS Lane 1 - U32 */
/* CPS Lane 3 - U31 */
status = "okay";
};
-&cps_spi1 {
+&cp1_spi1 {
pinctrl-names = "default";
- pinctrl-0 = <&cps_spi1_pins>;
+ pinctrl-0 = <&cp1_spi1_pins>;
status = "okay";
spi-flash at 0 {
@@ -304,7 +304,7 @@
};
};
-&cps_usb3_0 {
+&cp1_usb3_0 {
/* CPS Lane 2 - CON7 */
usb-phy = <&usb3h0_phy>;
status = "okay";
diff --git a/arch/arm64/boot/dts/marvell/armada-8040.dtsi b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
index 60fe84f5cbcc..83d2b40e5981 100644
--- a/arch/arm64/boot/dts/marvell/armada-8040.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-8040.dtsi
@@ -59,6 +59,6 @@
* disable it. However, the RTC clock in CP slave is connected to the
* oscillator so this one is let enabled.
*/
-&cpm_rtc {
+&cp0_rtc {
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
index 5e038e7b7b30..0d36b0fa7153 100644
--- a/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-80x0.dtsi
@@ -46,19 +46,19 @@
/ {
aliases {
- gpio1 = &cps_gpio1;
- gpio2 = &cpm_gpio2;
- spi1 = &cpm_spi0;
- spi2 = &cpm_spi1;
- spi3 = &cps_spi0;
- spi4 = &cps_spi1;
+ gpio1 = &cp1_gpio1;
+ gpio2 = &cp0_gpio2;
+ spi1 = &cp0_spi0;
+ spi2 = &cp0_spi1;
+ spi3 = &cp1_spi0;
+ spi4 = &cp1_spi1;
};
};
/*
* Instantiate the master CP110
*/
-#define CP110_NAME cpm
+#define CP110_NAME cp0
#define CP110_BASE f2000000
#define CP110_PCIE_IO_BASE 0xf9000000
#define CP110_PCIE_MEM_BASE 0xf6000000
@@ -79,7 +79,7 @@
/*
* Instantiate the slave CP110
*/
-#define CP110_NAME cps
+#define CP110_NAME cp1
#define CP110_BASE f4000000
#define CP110_PCIE_IO_BASE 0xfd000000
#define CP110_PCIE_MEM_BASE 0xfa000000
@@ -98,23 +98,23 @@
#undef CP110_PCIE2_BASE
/* The 80x0 has two CP blocks, but uses only one block from each. */
-&cps_gpio1 {
+&cp1_gpio1 {
status = "okay";
};
-&cpm_gpio2 {
+&cp0_gpio2 {
status = "okay";
};
-&cpm_syscon0 {
- cpm_pinctrl: pinctrl {
- compatible = "marvell,armada-8k-cpm-pinctrl";
+&cp0_syscon0 {
+ cp0_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cp0-pinctrl";
};
};
-&cps_syscon0 {
- cps_pinctrl: pinctrl {
- compatible = "marvell,armada-8k-cps-pinctrl";
+&cp1_syscon0 {
+ cp1_pinctrl: pinctrl {
+ compatible = "marvell,armada-8k-cp1-pinctrl";
nand_pins: nand-pins {
marvell,pins =
@@ -135,7 +135,7 @@
};
};
-&cps_crypto {
+&cp1_crypto {
/*
* The cryptographic engine found on the cp110
* master is enabled by default at the SoC
--
2.14.3
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