* [PATCH v4 15/19] arm64; insn: Add encoder for the EXTR instruction
From: Marc Zyngier @ 2018-01-04 18:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104184334.16571-1-marc.zyngier@arm.com>
Add an encoder for the EXTR instruction, which also implements the ROR
variant (where Rn == Rm).
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/include/asm/insn.h | 6 ++++++
arch/arm64/kernel/insn.c | 32 ++++++++++++++++++++++++++++++++
2 files changed, 38 insertions(+)
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index 815b35bc53ed..f62c56b1793f 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -319,6 +319,7 @@ __AARCH64_INSN_FUNCS(and_imm, 0x7F800000, 0x12000000)
__AARCH64_INSN_FUNCS(orr_imm, 0x7F800000, 0x32000000)
__AARCH64_INSN_FUNCS(eor_imm, 0x7F800000, 0x52000000)
__AARCH64_INSN_FUNCS(ands_imm, 0x7F800000, 0x72000000)
+__AARCH64_INSN_FUNCS(extr, 0x7FA00000, 0x13800000)
__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
@@ -433,6 +434,11 @@ u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
enum aarch64_insn_register Rn,
enum aarch64_insn_register Rd,
u64 imm);
+u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
+ enum aarch64_insn_register Rm,
+ enum aarch64_insn_register Rn,
+ enum aarch64_insn_register Rd,
+ u8 lsb);
u32 aarch64_insn_gen_prefetch(enum aarch64_insn_register base,
enum aarch64_insn_prfm_type type,
enum aarch64_insn_prfm_target target,
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 72cb1721c63f..59669d7d4383 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -1621,3 +1621,35 @@ u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
return aarch64_encode_immediate(imm, variant, insn);
}
+
+u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
+ enum aarch64_insn_register Rm,
+ enum aarch64_insn_register Rn,
+ enum aarch64_insn_register Rd,
+ u8 lsb)
+{
+ u32 insn;
+
+ insn = aarch64_insn_get_extr_value();
+
+ switch (variant) {
+ case AARCH64_INSN_VARIANT_32BIT:
+ if (lsb > 31)
+ return AARCH64_BREAK_FAULT;
+ break;
+ case AARCH64_INSN_VARIANT_64BIT:
+ if (lsb > 63)
+ return AARCH64_BREAK_FAULT;
+ insn |= AARCH64_INSN_SF_BIT;
+ insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_N, insn, 1);
+ break;
+ default:
+ pr_err("%s: unknown variant encoding %d\n", __func__, variant);
+ return AARCH64_BREAK_FAULT;
+ }
+
+ insn = aarch64_insn_encode_immediate(AARCH64_INSN_IMM_S, insn, lsb);
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd);
+ insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, Rn);
+ return aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RM, insn, Rm);
+}
--
2.14.2
^ permalink raw reply related
* [PATCH v4 16/19] arm64: insn: Allow ADD/SUB (immediate) with LSL #12
From: Marc Zyngier @ 2018-01-04 18:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104184334.16571-1-marc.zyngier@arm.com>
The encoder for ADD/SUB (immediate) can only cope with 12bit
immediates, while there is an encoding for a 12bit immediate shifted
by 12 bits to the left.
Let's fix this small oversight by allowing the LSL_12 bit to be set.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/kernel/insn.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 59669d7d4383..20655537cdd1 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -35,6 +35,7 @@
#define AARCH64_INSN_SF_BIT BIT(31)
#define AARCH64_INSN_N_BIT BIT(22)
+#define AARCH64_INSN_LSL_12 BIT(22)
static int aarch64_insn_encoding_class[] = {
AARCH64_INSN_CLS_UNKNOWN,
@@ -903,9 +904,18 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
return AARCH64_BREAK_FAULT;
}
+ /* We can't encode more than a 24bit value (12bit + 12bit shift) */
+ if (imm & ~(BIT(24) - 1))
+ goto out;
+
+ /* If we have something in the top 12 bits... */
if (imm & ~(SZ_4K - 1)) {
- pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
- return AARCH64_BREAK_FAULT;
+ /* ... and in the low 12 bits -> error */
+ if (imm & (SZ_4K - 1))
+ goto out;
+
+ imm >>= 12;
+ insn |= AARCH64_INSN_LSL_12;
}
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, dst);
@@ -913,6 +923,10 @@ u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RN, insn, src);
return aarch64_insn_encode_immediate(AARCH64_INSN_IMM_12, insn, imm);
+
+out:
+ pr_err("%s: invalid immediate encoding %d\n", __func__, imm);
+ return AARCH64_BREAK_FAULT;
}
u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
--
2.14.2
^ permalink raw reply related
* [PATCH v4 17/19] arm64: KVM: Dynamically compute the HYP VA mask
From: Marc Zyngier @ 2018-01-04 18:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104184334.16571-1-marc.zyngier@arm.com>
As we're moving towards a much more dynamic way to compute our
HYP VA, let's express the mask in a slightly different way.
Instead of comparing the idmap position to the "low" VA mask,
we directly compute the mask by taking into account the idmap's
(VA_BIT-1) bit.
No functionnal change.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/kvm/va_layout.c | 17 ++++++-----------
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/kvm/va_layout.c b/arch/arm64/kvm/va_layout.c
index aee758574e61..75bb1c6772b0 100644
--- a/arch/arm64/kvm/va_layout.c
+++ b/arch/arm64/kvm/va_layout.c
@@ -21,24 +21,19 @@
#include <asm/insn.h>
#include <asm/kvm_mmu.h>
-#define HYP_PAGE_OFFSET_HIGH_MASK ((UL(1) << VA_BITS) - 1)
-#define HYP_PAGE_OFFSET_LOW_MASK ((UL(1) << (VA_BITS - 1)) - 1)
-
static u64 va_mask;
static void compute_layout(void)
{
phys_addr_t idmap_addr = __pa_symbol(__hyp_idmap_text_start);
- unsigned long mask = HYP_PAGE_OFFSET_HIGH_MASK;
+ u64 region;
- /*
- * Activate the lower HYP offset only if the idmap doesn't
- * clash with it,
- */
- if (idmap_addr > HYP_PAGE_OFFSET_LOW_MASK)
- mask = HYP_PAGE_OFFSET_HIGH_MASK;
+ /* Where is my RAM region? */
+ region = idmap_addr & BIT(VA_BITS - 1);
+ region ^= BIT(VA_BITS - 1);
- va_mask = mask;
+ va_mask = BIT(VA_BITS - 1) - 1;
+ va_mask |= region;
}
static u32 compute_instruction(int n, u32 rd, u32 rn)
--
2.14.2
^ permalink raw reply related
* [PATCH v4 18/19] arm64: KVM: Introduce EL2 VA randomisation
From: Marc Zyngier @ 2018-01-04 18:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104184334.16571-1-marc.zyngier@arm.com>
The main idea behind randomising the EL2 VA is that we usually have
a few spare bits between the most significant bit of the VA mask
and the most significant bit of the linear mapping.
Those bits could be a bunch of zeroes, and could be useful
to move things around a bit. Of course, the more memory you have,
the less randomisation you get...
Alternatively, these bits could be the result of KASLR, in which
case they are already random. But it would be nice to have a
*different* randomization, just to make the job of a potential
attacker a bit more difficult.
Inserting these random bits is a bit involved. We don't have a spare
register (short of rewriting all the kern_hyp_va call sites), and
the immediate we want to insert is too random to be used with the
ORR instruction. The best option I could come up with is the following
sequence:
and x0, x0, #va_mask
ror x0, x0, #first_random_bit
add x0, x0, #(random & 0xfff)
add x0, x0, #(random >> 12), lsl #12
ror x0, x0, #(63 - first_random_bit)
making it a fairly long sequence, but one that a decent CPU should
be able to execute without breaking a sweat. It is of course NOPed
out on VHE. The last 4 instructions can also be turned into NOPs
if it appears that there is no free bits to use.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm64/include/asm/kvm_mmu.h | 10 +++++-
arch/arm64/kvm/va_layout.c | 68 +++++++++++++++++++++++++++++++++++++---
virt/kvm/arm/mmu.c | 2 +-
3 files changed, 73 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
index cc882e890bb1..4fca6ddadccc 100644
--- a/arch/arm64/include/asm/kvm_mmu.h
+++ b/arch/arm64/include/asm/kvm_mmu.h
@@ -85,6 +85,10 @@
.macro kern_hyp_va reg
alternative_cb kvm_update_va_mask
and \reg, \reg, #1
+ ror \reg, \reg, #1
+ add \reg, \reg, #0
+ add \reg, \reg, #0
+ ror \reg, \reg, #63
alternative_cb_end
.endm
@@ -101,7 +105,11 @@ void kvm_update_va_mask(struct alt_instr *alt,
static inline unsigned long __kern_hyp_va(unsigned long v)
{
- asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n",
+ asm volatile(ALTERNATIVE_CB("and %0, %0, #1\n"
+ "ror %0, %0, #1\n"
+ "add %0, %0, #0\n"
+ "add %0, %0, #0\n"
+ "ror %0, %0, #63\n",
kvm_update_va_mask)
: "+r" (v));
return v;
diff --git a/arch/arm64/kvm/va_layout.c b/arch/arm64/kvm/va_layout.c
index 75bb1c6772b0..bf0d6bdf5f14 100644
--- a/arch/arm64/kvm/va_layout.c
+++ b/arch/arm64/kvm/va_layout.c
@@ -16,11 +16,15 @@
*/
#include <linux/kvm_host.h>
+#include <linux/random.h>
+#include <linux/memblock.h>
#include <asm/alternative.h>
#include <asm/debug-monitors.h>
#include <asm/insn.h>
#include <asm/kvm_mmu.h>
+static u8 tag_lsb;
+static u64 tag_val;
static u64 va_mask;
static void compute_layout(void)
@@ -32,8 +36,31 @@ static void compute_layout(void)
region = idmap_addr & BIT(VA_BITS - 1);
region ^= BIT(VA_BITS - 1);
- va_mask = BIT(VA_BITS - 1) - 1;
- va_mask |= region;
+ tag_lsb = fls64((u64)phys_to_virt(memblock_start_of_DRAM()) ^
+ (u64)(high_memory - 1));
+
+ if (tag_lsb == (VA_BITS - 1)) {
+ /*
+ * No space in the address, let's compute the mask so
+ * that it covers (VA_BITS - 1) bits, and the region
+ * bit. The tag is set to zero.
+ */
+ tag_lsb = tag_val = 0;
+ va_mask = BIT(VA_BITS - 1) - 1;
+ va_mask |= region;
+ } else {
+ /*
+ * We do have some free bits. Let's have the mask to
+ * cover the low bits of the VA, and the tag to
+ * contain the random stuff plus the region bit.
+ */
+ u64 mask = GENMASK_ULL(VA_BITS - 2, tag_lsb);
+
+ va_mask = BIT(tag_lsb) - 1;
+ tag_val = get_random_long() & mask;
+ tag_val |= region;
+ tag_val >>= tag_lsb;
+ }
}
static u32 compute_instruction(int n, u32 rd, u32 rn)
@@ -46,6 +73,33 @@ static u32 compute_instruction(int n, u32 rd, u32 rn)
AARCH64_INSN_VARIANT_64BIT,
rn, rd, va_mask);
break;
+
+ case 1:
+ /* ROR is a variant of EXTR with Rm = Rn */
+ insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
+ rn, rn, rd,
+ tag_lsb);
+ break;
+
+ case 2:
+ insn = aarch64_insn_gen_add_sub_imm(rd, rn,
+ tag_val & (SZ_4K - 1),
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_ADSB_ADD);
+ break;
+
+ case 3:
+ insn = aarch64_insn_gen_add_sub_imm(rd, rn,
+ tag_val & GENMASK(23, 12),
+ AARCH64_INSN_VARIANT_64BIT,
+ AARCH64_INSN_ADSB_ADD);
+ break;
+
+ case 4:
+ /* ROR is a variant of EXTR with Rm = Rn */
+ insn = aarch64_insn_gen_extr(AARCH64_INSN_VARIANT_64BIT,
+ rn, rn, rd, 64 - tag_lsb);
+ break;
}
return insn;
@@ -56,8 +110,8 @@ void __init kvm_update_va_mask(struct alt_instr *alt,
{
int i;
- /* We only expect a 1 instruction sequence */
- BUG_ON(nr_inst != 1);
+ /* We only expect a 5 instruction sequence */
+ BUG_ON(nr_inst != 5);
if (!has_vhe() && !va_mask)
compute_layout();
@@ -68,8 +122,12 @@ void __init kvm_update_va_mask(struct alt_instr *alt,
/*
* VHE doesn't need any address translation, let's NOP
* everything.
+ *
+ * Alternatively, if we don't have any spare bits in
+ * the address, NOP everything after masking tha
+ * kernel VA.
*/
- if (has_vhe()) {
+ if (has_vhe() || (!tag_lsb && i > 1)) {
updptr[i] = aarch64_insn_gen_nop();
continue;
}
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 14c5e5534f2f..d01c7111b1f7 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -1811,7 +1811,7 @@ int kvm_mmu_init(void)
kern_hyp_va((unsigned long)high_memory - 1));
if (hyp_idmap_start >= kern_hyp_va(PAGE_OFFSET) &&
- hyp_idmap_start < kern_hyp_va(~0UL) &&
+ hyp_idmap_start < kern_hyp_va((unsigned long)high_memory - 1) &&
hyp_idmap_start != (unsigned long)__hyp_idmap_text_start) {
/*
* The idmap page is intersecting with the VA space,
--
2.14.2
^ permalink raw reply related
* [PATCH v4 19/19] arm64: Update the KVM memory map documentation
From: Marc Zyngier @ 2018-01-04 18:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104184334.16571-1-marc.zyngier@arm.com>
Update the documentation to reflect the new tricks we play on the
EL2 mappings...
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
Documentation/arm64/memory.txt | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/Documentation/arm64/memory.txt b/Documentation/arm64/memory.txt
index 671bc0639262..ea64e20037f6 100644
--- a/Documentation/arm64/memory.txt
+++ b/Documentation/arm64/memory.txt
@@ -86,9 +86,11 @@ Translation table lookup with 64KB pages:
+-------------------------------------------------> [63] TTBR0/1
-When using KVM without the Virtualization Host Extensions, the hypervisor
-maps kernel pages in EL2 at a fixed offset from the kernel VA. See the
-kern_hyp_va macro for more details.
+When using KVM without the Virtualization Host Extensions, the
+hypervisor maps kernel pages in EL2 at a fixed offset (modulo a random
+offset) from the linear mapping. See the kern_hyp_va macro and
+kvm_update_va_mask function for more details. MMIO devices such as
+GICv2 gets mapped next to the HYP idmap page.
When using KVM with the Virtualization Host Extensions, no additional
mappings are created, since the host kernel runs directly in EL2.
--
2.14.2
^ permalink raw reply related
* [kernel-hardening] [PATCH] arm: Always use REFCOUNT_FULL
From: Russell King - ARM Linux @ 2018-01-04 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGXu5jKkw7aCN7N8P-UkoFH2xF8Szy-UsL5tJBYUQKaW2a38yA@mail.gmail.com>
On Thu, Jan 04, 2018 at 10:42:21AM -0800, Kees Cook wrote:
> On Thu, Jan 4, 2018 at 10:35 AM, Russell King - ARM Linux
> <linux@armlinux.org.uk> wrote:
> > On Thu, Jan 04, 2018 at 10:32:46AM -0800, Kees Cook wrote:
> >> On Thu, Jan 4, 2018 at 4:28 AM, Jinbum Park <jinb.park7@gmail.com> wrote:
> >> > arm prefers to use REFCOUNT_FULL by default.
> >> > This enables it for arm.
> >> >
> >> > Signed-off-by: Jinbum Park <jinb.park7@gmail.com>
> >>
> >> Acked-by: Kees Cook <keescook@chromium.org>
> >
> > I'd help if there was some kind of explanation about this. Not
> > everyone knows what REFCOUNT_FULL is.
> >
> > Also, why does "arm" "prefer" to use this? Where does the preference
> > come from - and why is it a preference but being enforced by the
> > Kconfig ?
>
> This came from discussions with Will Deacon (and others) during the
> Linux Security Summit. The arm64 side of this is in commit
> 4adcec1164de ("arm64: Always use REFCOUNT_FULL"). AIUI, Will said he
> didn't want the specialized "fast but technically incomplete"
> refcounting as seen with x86's fast refcount infrastructure, but
> rather to keep refcounts always fully protected by default because no
> one could point to real-world performance impacts with REFCOUNT_FULL
> vs unprotected atomic_t infrastructure.
>
> I'm fine leaving this choice up to the end user, but I think it makes
> sense to be always-on. If that's no okay, maybe make it default-y for
> arm32, and still let people turn it off if they want?
I'm not really asking for changes.
I'm basically asking for the commit message to do a better job of
explaining this - in years to come, the currently proposed commit
message contains very little information about why this commit exists.
Commit messages need to say what they're doing and why, and not assume
that someone's been to some conference and knows all the inside details
that were discussed there. It's also best to avoid referencing papers -
conferences and their websites come and go, and links break, at which
point information gets lost. If it's all properly explained in the
commit message, then it's there forever.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Maxime Ripard @ 2018-01-04 18:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1645801.yZU0HLsLbk@jernej-laptop>
On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej ?krabec wrote:
> Hi Rob,
>
> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
> > > This commit adds all necessary compatibles and descriptions needed to
> > > implement A83T HDMI pipeline.
> > >
> > > Mixer is already properly described, so only compatible is added.
> > >
> > > However, A83T TCON1, which is connected to HDMI, doesn't have channel 0,
> > > contrary to all TCONs currently described. Because of that, TCON
> > > documentation is extended.
> > >
> > > A83T features Synopsys DW HDMI controller with a custom PHY which looks
> > > like Synopsys Gen2 PHY with few additions. Since there is no
> > > documentation, needed properties were found out through experimentation
> > > and reading BSP code.
> > >
> > > At the end, example is added for newer SoCs, which features DE2 and DW
> > > HDMI.
> > >
> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > > ---
> > >
> > > .../bindings/display/sunxi/sun4i-drm.txt | 188
> > > ++++++++++++++++++++- 1 file changed, 181 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> > > 9f073af4c711..3eca258096a5 100644
> > > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > >
> > > @@ -64,6 +64,40 @@ Required properties:
> > > first port should be the input endpoint. The second should be the
> > > output, usually to an HDMI connector.
> > >
> > > +DWC HDMI TX Encoder
> > > +-----------------------------
> > > +
> > > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX controller IP
> > > +with Allwinner's own PHY IP. It supports audio and video outputs and CEC.
> > > +
> > > +These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
> > > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with the
> > > +following device-specific properties.
> > > +
> > > +Required properties:
> > > +
> > > + - compatible: value must be one of:
> > > + * "allwinner,sun8i-a83t-dw-hdmi"
> > > + - reg: two pairs of base address and size of memory-mapped region,
> > > first
> > > + for controller and second for PHY
> > > + registers.
> >
> > Seems like the phy should be a separate node and use the phy binding.
> > You can use the phy binding even if you don't use the kernel phy
> > framework...
>
> Unfortunately, it's not so straighforward. Phy is actually accessed through
> I2C implemented in HDMI controller. Second memory region in this case has
> small influence on phy. However, it has big influence on controller. For
> example, magic number has to be written in one register in second memory
> region in order to unlock read access to any register from first memory region
> (controller). However, they shouldn't be merged to one region, because first
> memory region requires byte access while second memory region can be accessed
> per byte or word.
>
> To complicate things more, later I want to add support for another SoC which
> has same glue layer (unlocking read access, etc.) and uses memory mapped phy
> registers in second memory region.
>
> I think current binding is the least complicated way to represent this.
I agree with Rob here. I did a similar thing for the DSI patches I've
sent a few monthes ago and it turned out to not be that difficult, so
I'm sure you can come up with something :)
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH v5 03/12] dt-bindings: display: sun4i-drm: Add LVDS properties
From: Maxime Ripard @ 2018-01-04 19:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1927811.df6406f6u0@jernej-laptop>
Hi,
On Sat, Dec 30, 2017 at 12:45:19PM +0100, Jernej ?krabec wrote:
> Hi Maxime,
>
> Dne ?etrtek, 21. december 2017 ob 12:02:29 CET je Maxime Ripard napisal(a):
> > Some clocks and resets supposed to drive the LVDS logic in the display
> > engine have been overlooked when the driver was first introduced.
> >
> > Add those additional resources to the binding, and we'll deal with the ABI
> > stability in the code.
> >
> > Reviewed-by: Chen-Yu Tsai <wens@csie.org>
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 9 +++++++-
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt index
> > 50cc72ee1168..1e21cfaac9e2 100644
> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> > @@ -121,6 +121,15 @@ Required properties:
> > On SoCs other than the A33 and V3s, there is one more clock required:
> > - 'tcon-ch1': The clock driving the TCON channel 1
> >
> > +On SoCs that support LVDS (all SoCs but the A13, H3, H5 and V3s), you
> > +need one more reset line:
> > + - 'lvds': The reset line driving the LVDS logic
> > +
> > +And on the SoCs newer than the A31 (sun6i and sun8i families), you
> > +need one more clock line:
> > + - 'lvds-alt': An alternative clock source, separate from the TCON
> > channel 0 + clock, that can be used to drive the LVDS clock
>
> I think this wording is imprecise, since A83T is part of the sun8i family, but
> from the code (patch 7) and DT changes (patch 9) you do, it doesn't need this
> property.
>
> Maybe it would be just easier to enumerate all compatibles which needs this
> property?
You're right, but the rest of the document uses the SoC name
instead. In order to remain consistent, I listed the (currently
supported) SoCs that need that property and applied that patch.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* [PATCH v5 1/2] PCI: mediatek: Clear IRQ status after IRQ dispatched to avoid reentry
From: Marc Zyngier @ 2018-01-04 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104184040.GE12239@red-moon>
On 04/01/18 18:40, Lorenzo Pieralisi wrote:
> [+Marc]
>
> On Wed, Dec 27, 2017 at 08:59:53AM +0800, honghui.zhang at mediatek.com wrote:
>> From: Honghui Zhang <honghui.zhang@mediatek.com>
>>
>> There maybe a same IRQ reentry scenario after IRQ received in current
>> IRQ handle flow:
>> EP device PCIe host driver EP driver
>> 1. issue an IRQ
>> 2. received IRQ
>> 3. clear IRQ status
>> 4. dispatch IRQ
>> 5. clear IRQ source
>> The IRQ status was not successfully cleared at step 2 since the IRQ
>> source was not cleared yet. So the PCIe host driver may receive the
>> same IRQ after step 5. Then there's an IRQ reentry occurred.
>> Even worse, if the reentry IRQ was not an IRQ that EP driver expected,
>> it may not handle the IRQ. Then we may run into the infinite loop from
>> step 2 to step 4.
>> Clear the IRQ status after IRQ have been dispatched to avoid the IRQ
>> reentry.
>> This patch also fix another INTx IRQ issue by initialize the iterate
>> before the loop. If an INTx IRQ re-occurred while we are dispatching
>> the INTx IRQ, then iterate may start from PCI_NUM_INTX + INTX_SHIFT
>> instead of INTX_SHIFT for the second time entering the
>> for_each_set_bit_from() loop.
>
> This looks like two different issues that should be fixed with two
> patches.
>
>> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com>
>> Acked-by: Ryder Lee <ryder.lee@mediatek.com>
>> ---
>> drivers/pci/host/pcie-mediatek.c | 11 ++++++-----
>> 1 file changed, 6 insertions(+), 5 deletions(-)
>
> For the sake of uniformity, I first want to understand why this
> driver does not call:
>
> chained_irq_enter/exit()
>
> in the primary handler (mtk_pcie_intr_handler()).
>
> With the GIC as a primary interrupt controller we have not
> even figured out how current code can actually work without
> calling the chained_* API.
>
> I want to come up with a consistent handling of IRQ domains for
> all host bridges and any discrepancy should be explained.
That's because this driver is a huge hack, see below:
>
>> diff --git a/drivers/pci/host/pcie-mediatek.c b/drivers/pci/host/pcie-mediatek.c
>> index db93efd..fc29a9a 100644
>> --- a/drivers/pci/host/pcie-mediatek.c
>> +++ b/drivers/pci/host/pcie-mediatek.c
>> @@ -601,15 +601,16 @@ static irqreturn_t mtk_pcie_intr_handler(int irq, void *data)
This function is not a chained irqchip, but an interrupt handler...
>> struct mtk_pcie_port *port = (struct mtk_pcie_port *)data;
>> unsigned long status;
>> u32 virq;
>> - u32 bit = INTX_SHIFT;
>> + u32 bit;
>>
>> while ((status = readl(port->base + PCIE_INT_STATUS)) & INTX_MASK) {
>> + bit = INTX_SHIFT;
>> for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
>> - /* Clear the INTx */
>> - writel(1 << bit, port->base + PCIE_INT_STATUS);
>> virq = irq_find_mapping(port->irq_domain,
>> bit - INTX_SHIFT);
>> generic_handle_irq(virq);
and nonetheless, this calls into generic_handle_irq(). That's a complete
violation of the interrupt layering. Maybe there is a good reason for
it, but I'd like to know which one.
Which means that all of the ack/mask has to be done outside of the
irqchip framework too... Disgusting.
>> + /* Clear the INTx */
>> + writel(1 << bit, port->base + PCIE_INT_STATUS);
>
> I think that these masking/acking should actually be done through
> the irq_chip hooks (see for instance pci-ftpci100.c) - that would
> make this kind of bugs much easier to prevent (because the IRQ
> layer does the sequencing for you).
+1.
> Marc (CC'ed) has a more comprehensive view on this than me - I would
> like to get to a point where all host bridges uses a consistent
> approach for chained IRQ handling and I hope this bug fix can be
> a starting point.
+1 again. We definitely need to come up with some form of common
approach for all these host drivers, and maybe turn that into a library...
Thanks,
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH 0/8] ARM: dts: keystone*: Continued warnings cleanups
From: Santosh Shilimkar @ 2018-01-04 19:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180102170202.15045-1-afd@ti.com>
On 1/2/2018 9:01 AM, Andrew F. Davis wrote:
> Hello all,
>
> Just a couple cleanups for DT warnings when compiling with W=1.
>
> This clears up 51 more warnings when building keystone_defconfig.
>
> Based on Santosh's "for_4.16/keystone-dts" branch.
>
Will see if this can be queued up post merge window as 'non-critical'
fixes o.w it waits for 4.17. Please repost it after addressing
Suman's comments.
Regards,
Santosh
^ permalink raw reply
* [PATCH v5 03/20] firmware: arm_scmi: add basic driver infrastructure for SCMI
From: Alexey Klimov @ 2018-01-04 19:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514904162-11201-4-git-send-email-sudeep.holla@arm.com>
Hi Sudeep,
thank you for working on this.
On Tue, Jan 2, 2018 at 2:42 PM, Sudeep Holla <sudeep.holla@arm.com> wrote:
[...]
> diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
> new file mode 100644
> index 000000000000..58d8f88893e6
> --- /dev/null
> +++ b/drivers/firmware/arm_scmi/driver.c
[..]
> + * Return: 0 is successfully released
> + * if null was passed, it returns -EINVAL;
> + */
> +int scmi_handle_put(const struct scmi_handle *handle)
> +{
> + struct scmi_info *info;
> +
> + if (!handle)
> + return -EINVAL;
> +
> + info = handle_to_scmi_info(handle);
> + mutex_lock(&scmi_list_mutex);
> + if (!WARN_ON(!info->users))
> + info->users--;
> + mutex_unlock(&scmi_list_mutex);
> +
> + return 0;
> +}
> +
> +static const struct scmi_desc scmi_generic_desc = {
> + .max_rx_timeout_ms = 30, /* we may increase this if required */
What are your thoughts about making it a module parameter?
IIRC, this may required to be increased when someone uses debugging
version of firmware, for example.
In such case someone might need to recompile the kernel in order to
boot with enabled and initialized scmi.
Also, there can be a chance that another transport will be used that
will require larger than 5 * 30 ms delay (such kind of transport can
be kinda useless, I know, but can help with development).
With module parameter you can still boot passing the larger timeout
parameter to the module from cmdline.
> + .max_msg = 20, /* Limited by MBOX_TX_QUEUE_LEN */
> + .max_msg_size = 128,
> +};
Best regards,
Alexey
^ permalink raw reply
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework
From: Adam Ford @ 2018-01-04 19:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f09641b7-a9e9-24d1-ce13-1b627d077ce5@lechnology.com>
On Thu, Jan 4, 2018 at 11:50 AM, David Lechner <david@lechnology.com> wrote:
>
>
> On 1/4/18 6:39 AM, Sekhar Nori wrote:
>>
>> On Monday 01 January 2018 05:09 AM, David Lechner wrote:
>>>
>>> This converts all of arch/arm/mach-davinci to the common clock framework.
>>> The clock drivers from clock.c and psc.c have been moved to drivers/clk,
>>> so these files are removed.
>>>
>>> There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV
>>> clocks now have "ref_clk" as a parent instead of the PLL clock. These
>>> clocks are part of the PLL's MMIO block, but they bypass the PLL and
>>> therefore it makes more sense to have "ref_clk" as their parent since
>>> "ref_clk" is the input clock of the PLL.
>>>
>>> CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks
>>> takes care of disabling unused clocks.
>>>
>>> Known issue: This breaks CPU frequency scaling on da850.
>>
>>
>> This functionality needs to be restored as part of this series since we
>> cannot commit anything with regressions.
>>
>
> Do you have a suggestion on how to accomplish this? I don't have a board for
> testing, so I don't have a way of knowing if my changes will work or not.
I work for Logic PD who makes the original da850-evm. I can help if
you want to send me patches. It would be better if you had a git repo
setup where I could just clone the repo and tests.
Having a larger collection of smaller the patches would also give me
the ability to bisect down to help determine what actually breaks the
da850-evm vs a few large patches.
Do you still need me to run the board with some of the extra debugging
enabled, or should I wait for the next round of patches?
adam
>
>>>
>>> Also, the order of #includes are cleaned up in files while we are
>>> touching
>>> this code.
>>>
>>> Signed-off-by: David Lechner <david@lechnology.com>
>>
>>
>> This is a pretty huge patch again and I hope it can be broken down.
>> Ideally one per SoC converted and then the unused code removal.
>>
>
> Will do.
^ permalink raw reply
* [PATCH 01/11] clk: sunxi-ng: Don't set k if width is 0 for nkmp plls
From: Jernej Škrabec @ 2018-01-04 19:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v67B23yUdACijKxosfFG_os5WndiBKX02DGA4PFUkxDx9g@mail.gmail.com>
Hi,
Dne ?etrtek, 04. januar 2018 ob 15:45:18 CET je Chen-Yu Tsai napisal(a):
> On Sun, Dec 31, 2017 at 5:01 AM, Jernej Skrabec <jernej.skrabec@siol.net>
wrote:
> > For example, A83T have nmp plls which are modelled as nkmp plls. Since k
> > is not specified, it has offset 0, shift 0 and lowest value 1. This
> > means that LSB bit is always set to 1, which may change clock rate.
> >
> > Fix that by applying k factor only if k width is greater than 0.
> >
> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > ---
> >
> > drivers/clk/sunxi-ng/ccu_nkmp.c | 21 +++++++++++++--------
> > 1 file changed, 13 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu_nkmp.c
> > b/drivers/clk/sunxi-ng/ccu_nkmp.c index e58c95787f94..709f528af2b3 100644
> > --- a/drivers/clk/sunxi-ng/ccu_nkmp.c
> > +++ b/drivers/clk/sunxi-ng/ccu_nkmp.c
> > @@ -81,7 +81,7 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw
> > *hw,>
> > unsigned long parent_rate)
> >
> > {
> >
> > struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
> >
> > - unsigned long n, m, k, p;
> > + unsigned long n, m, k = 1, p;
> >
> > u32 reg;
> >
> > reg = readl(nkmp->common.base + nkmp->common.reg);
> >
> > @@ -92,11 +92,13 @@ static unsigned long ccu_nkmp_recalc_rate(struct
> > clk_hw *hw,>
> > if (!n)
> >
> > n++;
> >
> > - k = reg >> nkmp->k.shift;
> > - k &= (1 << nkmp->k.width) - 1;
> > - k += nkmp->k.offset;
> > - if (!k)
> > - k++;
> > + if (nkmp->k.width) {
> > + k = reg >> nkmp->k.shift;
> > + k &= (1 << nkmp->k.width) - 1;
> > + k += nkmp->k.offset;
> > + if (!k)
> > + k++;
> > + }
>
> The conditional shouldn't be necessary. With nkmp->k.width = 0,
> you'd simply get k & 0, which is 0, which then gets bumped up to 1,
> unless k.offset > 1, which would be a bug.
>
> > m = reg >> nkmp->m.shift;
> > m &= (1 << nkmp->m.width) - 1;
> >
> > @@ -153,12 +155,15 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw,
> > unsigned long rate,>
> > reg = readl(nkmp->common.base + nkmp->common.reg);
> > reg &= ~GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift);
> >
> > - reg &= ~GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift);
> > + if (nkmp->k.width)
> > + reg &= ~GENMASK(nkmp->k.width + nkmp->k.shift - 1,
> > + nkmp->k.shift);
> >
> > reg &= ~GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift);
> > reg &= ~GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift);
> >
> > reg |= (_nkmp.n - nkmp->n.offset) << nkmp->n.shift;
> >
> > - reg |= (_nkmp.k - nkmp->k.offset) << nkmp->k.shift;
> > + if (nkmp->k.width)
> > + reg |= (_nkmp.k - nkmp->k.offset) << nkmp->k.shift;
>
> I think a better way would be
>
> reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) &
> GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift);
>
> And do this for all the factors, not just k. This pattern is what
> regmap_update_bits does, which seems much safer. I wonder what
> GENMASK() with a negative value would do though...
You're right, GENMASK(-1, 0) equals 0 (calculated by hand, not tested). This
seems much more elegant solution.
Semi-related question: All nmp PLLs have much wider N range than real nkmp
PLLs. This causes integer overflow when using nkmp formula from datasheet.
Usually, N is 1-256 for nmp PLLs, which means that for very high N factors, it
overflows. This also causes issue that M factor is never higher than 1.
I was wondering, if patch would be acceptable which would change this formula:
RATE = (24MHz * N * K) / (M * P)
to this:
RATE ((24MHz / M) * N * K) / P
I checked all M factors and are all in 1-4 or 1-2 range, which means it
wouldn't have any impact for real nkmp PLLs when parent is 24 MHz clock which
is probably always.
What do you think?
I discovered that when I tried to set A83T PLL_VIDEO to 346.5 MHz which is
possible only when above formula is changed.
Best regards,
Jernej
>
> ChenYu
>
> > reg |= (_nkmp.m - nkmp->m.offset) << nkmp->m.shift;
> > reg |= ilog2(_nkmp.p) << nkmp->p.shift;
> >
> > --
> > 2.15.1
^ permalink raw reply
* [PATCH 1/8] ARM: dts: keystone: Move keystone_irq to under device-state-control
From: Andrew F. Davis @ 2018-01-04 19:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cce1676d-8e91-c3d4-be79-7896011a8f26@ti.com>
On 01/02/2018 05:30 PM, Suman Anna wrote:
> Hi Andrew,
>
> On 01/02/2018 11:01 AM, Andrew F. Davis wrote:
>> The keystone_irq node describes a device that is a component of the device
>> state control module.
>
> I would prefer 'address space' to be added to this statement as this
> module is really not a single IP but really a collection of different
> register sets providing different functionalities. Some of these
> comments apply to the following patches as well.
>
Works for me, will re-word.
> As such, it should not be a member of soc0 bus
>> but instead a sub-node of device-state-control.
>>
>> This move also fixes a warning about not having a reg property. Now
>> that this is a sub-node of device-state-control, a syscon type node,
>> we add this reg property but relative to the syscon base, this way
>> when the dt-binding/driver are updated we can drop the non-standard
>> ti,syscon-dev property completely and simply use get_resource() in
>> the driver.
>
> Please add an appropriate 'ranges' property in the parent node following
> the parent-child node convention, it's upto individual drivers to use
> the appropriate API for whether they want to deal with the offset or the
> actual bus addresses. You should not tie this into forcing to use a
> get_resource() without ranges to get the offset.
>
Will add.
>>
>> Signed-off-by: Andrew F. Davis <afd@ti.com>
>> Acked-by: Nishanth Menon <nm@ti.com>
>> ---
>> arch/arm/boot/dts/keystone.dtsi | 21 ++++++++++++---------
>> 1 file changed, 12 insertions(+), 9 deletions(-)
>>
>> diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
>> index 93ea5c69ea77..158e0a903f7e 100644
>> --- a/arch/arm/boot/dts/keystone.dtsi
>> +++ b/arch/arm/boot/dts/keystone.dtsi
>> @@ -87,8 +87,19 @@
>> };
>>
>> devctrl: device-state-control at 2620000 {
>> - compatible = "ti,keystone-devctrl", "syscon";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "ti,keystone-devctrl", "syscon", "simple-mfd";
>
> nit, can you please maintain the current order of compatible and reg,
> and add the new properties after them.
>
#address/size-cells are the first properties in many other nodes,
including the top level soc0, I have no real preference, so I'll change
it around if you prefer.
> regards
> Suman
>
>> reg = <0x02620000 0x1000>;
>> +
>> + kirq0: keystone_irq at 2a0 {
>> + compatible = "ti,keystone-irq";
>> + reg = <0x2a0 0x4>;
>> + interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + ti,syscon-dev = <&devctrl 0x2a0>;
>> + };
>> };
>>
>> rstctrl: reset-controller {
>> @@ -282,14 +293,6 @@
>> 1 0 0x21000A00 0x00000100>;
>> };
>>
>> - kirq0: keystone_irq at 26202a0 {
>> - compatible = "ti,keystone-irq";
>> - interrupts = <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>;
>> - interrupt-controller;
>> - #interrupt-cells = <1>;
>> - ti,syscon-dev = <&devctrl 0x2a0>;
>> - };
>> -
>> pcie0: pcie at 21800000 {
>> compatible = "ti,keystone-pcie", "snps,dw-pcie";
>> clocks = <&clkpcie>;
>>
>
^ permalink raw reply
* [PATCH 2/4] dt-bindings: gpio: add raspberry pi GPIO expander binding
From: Baruch Siach @ 2018-01-04 19:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <860502005.181510.1514917560724@email.1und1.de>
Hi Stefan,
On Tue, Jan 02, 2018 at 07:26:00PM +0100, Stefan Wahren wrote:
> > Baruch Siach <baruch@tkos.co.il> hat am 2. Januar 2018 um 14:19 geschrieben:
> >
> >
> > The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware over
> > I2C. The firmware mailbox interface allows the ARM core to control the
> > GPIO lines.
> >
> > Signed-off-by: Baruch Siach <baruch@tkos.co.il>
> > ---
> > .../bindings/gpio/brcm,bcm2835-expgpio.txt | 24 ++++++++++++++++++++++
> > 1 file changed, 24 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/gpio/brcm,bcm2835-expgpio.txt
> >
> > diff --git a/Documentation/devicetree/bindings/gpio/brcm,bcm2835-expgpio.txt b/Documentation/devicetree/bindings/gpio/brcm,bcm2835-expgpio.txt
> > new file mode 100644
> > index 000000000000..55257f31a9be
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/gpio/brcm,bcm2835-expgpio.txt
> > @@ -0,0 +1,24 @@
> > +Raspberry Pi GPIO expander
> > +
> > +The Raspberry Pi 3 GPIO expander is controlled by the VC4 firmware. The
> > +firmware exposes a mailbox interface that allows the ARM core to control the
> > +GPIO lines on the expander.
> > +
> > +Required properties:
> > +
> > +- compatible : Should be "brcm,bcm2835-expgpio"
>
> from my understand this driver is specific to the Raspberry Pi and it's
> vendor is the Raspberry Pi Foundation. So i prefer Eric's suggestion of
> "raspberrypi,firmware-gpio", which also applies to the filename.
That was my inclination as well. But I thought that keeping DT compatibility
with downstream is desirable.
I'll change compatible/file/driver names to raspberry something.
baruch
> > +- gpio-controller : Marks the device node as a gpio controller
> > +- #gpio-cells : Should be two. The first cell is the pin number, and
> > + the second cell is used to specify the gpio polarity:
> > + 0 = active high
> > + 1 = active low
> > +- firmware : Reference to the RPi firmware device node
> > +
> > +Example:
> > +
> > +expgpio: expgpio {
> > + compatible = "brcm,bcm2835-expgpio";
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + firmware = <&firmware>;
> > +};
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch at tkos.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
^ permalink raw reply
* [PATCH v5 01/12] dt-bindings: panel: lvds: Document power-supply property
From: Maxime Ripard @ 2018-01-04 19:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2493504.1OPucrC18r@avalon>
Hi Laurent,
On Fri, Dec 22, 2017 at 02:08:20PM +0200, Laurent Pinchart wrote:
> Hi Maxime,
>
> Thank you for the patch.
>
> On Thursday, 21 December 2017 13:02:27 EET Maxime Ripard wrote:
> > The power-supply property is used by a vast majority of panels, including
> > panel-simple. Let's document it as a common property
> >
> > Reviewed-by: Rob Herring <robh@kernel.org>
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > Documentation/devicetree/bindings/display/panel/panel-common.txt | 6 ++++++
> > Documentation/devicetree/bindings/display/panel/panel-lvds.txt | 1 +
> > Documentation/devicetree/bindings/display/panel/simple-panel.txt | 2 +- 3
> > files changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git
> > a/Documentation/devicetree/bindings/display/panel/panel-common.txt
> > b/Documentation/devicetree/bindings/display/panel/panel-common.txt index
> > ec52c472c845..125ea68052af 100644
> > --- a/Documentation/devicetree/bindings/display/panel/panel-common.txt
> > +++ b/Documentation/devicetree/bindings/display/panel/panel-common.txt
> > @@ -78,6 +78,12 @@ used for panels that implement compatible control
> > signals. while active. Active high reset signals can be supported by
> > inverting the GPIO specifier polarity flag.
> >
> > +Power
> > +-----
> > +
> > +- power-supply: many display panels need an additional power supply in
> > + order to be fully powered-up. For such panels, power-supply contains
> > + a phandle to the regulator powering the panel.
>
> I think we should give more details here about the limitations of this
> property. How about the following explanation ?
>
> - power-supply: display panels require power to be supplied. While several
> panels need more than one power supply with panel-specific constraints
> governing the order and timings of the power supplies, in many cases a single
> power supply is sufficient, either because the panel has a single power rail,
> or because all its power rails can be driven by the same supply. In that case
> the power-supply property specifies the supply powering the panel as a phandle
> to a regulator.
That works for me. Do you want me to resend it with that text, or
should I merge it (and if so, with your Reviewed-by or Acked-by?)?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [arm-soc:next/dt 26/27] arch/arm64/boot/dts/sprd/sc9860.dtsi:10:10: fatal error: dt-bindings/clock/sprd,sc9860-clk.h: No such file or directory
From: kbuild test robot @ 2018-01-04 19:46 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git next/dt
head: b304c1c57f372c68a7a143b3b300c1a4666c8f7d
commit: 22f37a242925d28f7055639db64ea429afb50e54 [26/27] arm64: dts: add clocks for SC9860
config: arm64-defconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 22f37a242925d28f7055639db64ea429afb50e54
# save the attached .config to linux build tree
make.cross ARCH=arm64
All errors (new ones prefixed by >>):
In file included from arch/arm64/boot/dts/sprd/sp9860g-1h10.dts:11:0:
>> arch/arm64/boot/dts/sprd/sc9860.dtsi:10:10: fatal error: dt-bindings/clock/sprd,sc9860-clk.h: No such file or directory
#include <dt-bindings/clock/sprd,sc9860-clk.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
vim +10 arch/arm64/boot/dts/sprd/sc9860.dtsi
> 10 #include <dt-bindings/clock/sprd,sc9860-clk.h>
11 #include "whale2.dtsi"
12
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH V3] ARM: imx_v6_v7_defconfig: select the CONFIG_CPUFREQ_DT
From: Anson Huang @ 2018-01-04 19:48 UTC (permalink / raw)
To: linux-arm-kernel
Select CONFIG_CPUFREQ_DT by default to enable
cpu-freq driver for i.MX7D.
The rest changes are generated by "make savedefconfig".
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
changes since V2:
remove unexpected changes caused by savedefconfig.
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 29cd1ac..1c9c15f 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -58,6 +58,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
CONFIG_ARM_IMX6Q_CPUFREQ=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
--
1.9.1
^ permalink raw reply related
* [PATCH V4] ARM: imx_v6_v7_defconfig: select the CONFIG_CPUFREQ_DT
From: Anson Huang @ 2018-01-04 19:51 UTC (permalink / raw)
To: linux-arm-kernel
Select CONFIG_CPUFREQ_DT by default to enable
cpu-freq driver for i.MX7D.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
changes since V3:
correct commit message.
arch/arm/configs/imx_v6_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig
index 29cd1ac..1c9c15f 100644
--- a/arch/arm/configs/imx_v6_v7_defconfig
+++ b/arch/arm/configs/imx_v6_v7_defconfig
@@ -58,6 +58,7 @@ CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND=y
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPUFREQ_DT=y
CONFIG_ARM_IMX6Q_CPUFREQ=y
CONFIG_CPU_IDLE=y
CONFIG_VFP=y
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] mmc: sunxi: Add runtime_pm support
From: Maxime Ripard @ 2018-01-04 19:54 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAPDyKFomRYaL=gCwY2Kq0PXRJ9WtsQVCi-3KfkfSNU3+mnJpow@mail.gmail.com>
Hi Ulf,
On Thu, Dec 21, 2017 at 01:21:51PM +0100, Ulf Hansson wrote:
> On 20 December 2017 at 11:50, Maxime Ripard
> <maxime.ripard@free-electrons.com> wrote:
> > So far, even if our card was not in use, we didn't shut down our main
> > clock, which meant that it was still output on the MMC bus.
> >
> > While this obviously means that we could save some power there, it also
> > created issues when it comes with EMC control since we'll have a perfect
> > peak at the card clock rate.
> >
> > Let's implement runtime_pm with autosuspend so that we will shut down the
> > clock when it's not been in use for quite some time.
> >
> > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> > ---
> > drivers/mmc/host/sunxi-mmc.c | 90 ++++++++++++++++++++++++-------------
> > 1 file changed, 60 insertions(+), 30 deletions(-)
> >
> > diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
> > index 3ce46ebd3488..c6a0bd0e0476 100644
> > --- a/drivers/mmc/host/sunxi-mmc.c
> > +++ b/drivers/mmc/host/sunxi-mmc.c
> > @@ -35,6 +35,7 @@
> > #include <linux/of_gpio.h>
> > #include <linux/of_platform.h>
> > #include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > #include <linux/regulator/consumer.h>
> > #include <linux/reset.h>
> > #include <linux/scatterlist.h>
> > @@ -1217,29 +1218,11 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
> > return ret;
> > }
> >
> > - ret = clk_prepare_enable(host->clk_mmc);
> > - if (ret) {
> > - dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret);
> > - goto error_disable_clk_ahb;
> > - }
> > -
> > - ret = clk_prepare_enable(host->clk_output);
> > - if (ret) {
> > - dev_err(&pdev->dev, "Enable output clk err %d\n", ret);
> > - goto error_disable_clk_mmc;
> > - }
> > -
> > - ret = clk_prepare_enable(host->clk_sample);
> > - if (ret) {
> > - dev_err(&pdev->dev, "Enable sample clk err %d\n", ret);
> > - goto error_disable_clk_output;
> > - }
> > -
>
> Actually, I think you should keep all the above. Perhaps you may want
> to move it to a separate helper function though, which the
> ->runtime_resume() callbacks can invoke as well.
>
> More reasons to why, see the comment in the ->probe() function.
>
> > if (!IS_ERR(host->reset)) {
> > ret = reset_control_reset(host->reset);
> > if (ret) {
> > dev_err(&pdev->dev, "reset err %d\n", ret);
> > - goto error_disable_clk_sample;
> > + goto error_disable_clk_ahb;
> > }
> > }
> >
> > @@ -1258,12 +1241,6 @@ static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
> > error_assert_reset:
> > if (!IS_ERR(host->reset))
> > reset_control_assert(host->reset);
> > -error_disable_clk_sample:
> > - clk_disable_unprepare(host->clk_sample);
> > -error_disable_clk_output:
> > - clk_disable_unprepare(host->clk_output);
> > -error_disable_clk_mmc:
> > - clk_disable_unprepare(host->clk_mmc);
> > error_disable_clk_ahb:
> > clk_disable_unprepare(host->clk_ahb);
> > return ret;
> > @@ -1280,6 +1257,7 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
> > dev_err(&pdev->dev, "mmc alloc host failed\n");
> > return -ENOMEM;
> > }
> > + platform_set_drvdata(pdev, mmc);
> >
> > host = mmc_priv(mmc);
> > host->mmc = mmc;
> > @@ -1340,12 +1318,16 @@ static int sunxi_mmc_probe(struct platform_device *pdev)
> > if (ret)
> > goto error_free_dma;
> >
> > + pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
> > + pm_runtime_use_autosuspend(&pdev->dev);
> > + pm_runtime_enable(&pdev->dev);
> > +
>
> This means in case you don't have CONFIG_PM set when compiling this
> driver, the clocks will never be enabled using runtime PM.
>
> I think it's good practice to deal with this, therefore I think you
> should enable the clocks as before, and instead indicate that the
> device is already runtime resumed.
>
> In other words, before you call pm_runtime_enable(), invoke
> pm_runtime_set_active().
That's a very good point, I'll do that in the next iteration.
> > ret = mmc_add_host(mmc);
> > if (ret)
> > goto error_free_dma;
> >
> > dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
> > - platform_set_drvdata(pdev, mmc);
> > +
> > return 0;
> >
> > error_free_dma:
> > @@ -1361,27 +1343,75 @@ static int sunxi_mmc_remove(struct platform_device *pdev)
> > struct sunxi_mmc_host *host = mmc_priv(mmc);
> >
> > mmc_remove_host(mmc);
> > + pm_runtime_force_suspend(&pdev->dev);
>
> Do you need the clocks to be enabled, while calling disable_irq() and
> sunxi_mmc_reset_host()?
>
> In such case you need to call pm_runtime_get_sync() here. Then move
> pm_runtime_force_suspend() a few lines below, and later call
> pm_runtime_put_noidle().
We don't for disable_irq, but we need it for
sunxi_mmc_reset_host. I'll do what you suggest.
> > disable_irq(host->irq);
> > sunxi_mmc_reset_host(host);
> >
> > if (!IS_ERR(host->reset))
> > reset_control_assert(host->reset);
> >
> > - clk_disable_unprepare(host->clk_sample);
> > + dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
> > + mmc_free_host(mmc);
> > +
> > + return 0;
> > +}
> > +
> > +static int sunxi_mmc_runtime_resume(struct device *dev)
> > +{
> > + struct mmc_host *mmc = dev_get_drvdata(dev);
> > + struct sunxi_mmc_host *host = mmc_priv(mmc);
> > + int ret;
> > +
> > + ret = clk_prepare_enable(host->clk_mmc);
> > + if (ret) {
> > + dev_err(dev, "Enable mmc clk err %d\n", ret);
> > + return ret;
> > + }
> > +
> > + ret = clk_prepare_enable(host->clk_output);
> > + if (ret) {
> > + dev_err(dev, "Enable output clk err %d\n", ret);
> > + goto error_disable_clk_mmc;
> > + }
> > +
> > + ret = clk_prepare_enable(host->clk_sample);
> > + if (ret) {
> > + dev_err(dev, "Enable sample clk err %d\n", ret);
> > + goto error_disable_clk_output;
> > + }
> > +
> > + return 0;
> > +
> > +error_disable_clk_output:
> > clk_disable_unprepare(host->clk_output);
> > +error_disable_clk_mmc:
> > clk_disable_unprepare(host->clk_mmc);
> > - clk_disable_unprepare(host->clk_ahb);
> > + return ret;
> > +}
> >
> > - dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
> > - mmc_free_host(mmc);
> > +static int sunxi_mmc_runtime_suspend(struct device *dev)
> > +{
> > + struct mmc_host *mmc = dev_get_drvdata(dev);
> > + struct sunxi_mmc_host *host = mmc_priv(mmc);
> > +
> > + clk_disable_unprepare(host->clk_sample);
> > + clk_disable_unprepare(host->clk_output);
> > + clk_disable_unprepare(host->clk_mmc);
> >
> > return 0;
> > }
> >
> > +static const struct dev_pm_ops sunxi_mmc_pm_ops = {
> > + SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend,
> > + sunxi_mmc_runtime_resume,
> > + NULL)
> > +};
> > +
> > static struct platform_driver sunxi_mmc_driver = {
> > .driver = {
> > .name = "sunxi-mmc",
> > .of_match_table = of_match_ptr(sunxi_mmc_of_match),
> > + .pm = &sunxi_mmc_pm_ops,
> > },
> > .probe = sunxi_mmc_probe,
> > .remove = sunxi_mmc_remove,
> > --
> > git-series 0.9.1
>
> Otherwise this looks good to me!
>
> BTW, isn't system wide suspend/resume() also important to save power
> for? That's rather simple to implement, after you have enabled runtime
> PM support.
We don't have (unfortunately) any kind of suspend support at the
moment, so I guess that'll come as a single step when we'll have it :)
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [GIT PULL] Qualcomm Driver updates for 4.16
From: Andy Gross @ 2018-01-04 19:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <003c9462-aea5-f4b5-c5ca-fa0d0504a92b@arm.com>
On Tue, Jan 02, 2018 at 11:38:35AM +0000, Sudeep Holla wrote:
> H Andy,
>
> As Bjorn mention on the actual thread, you also need
>
> "[PATCH 1/4] of: platform: populate /firmware/ node from
> of_platform_default_populate_init()"
>
> which Rob has acked and I am fine if you pick it along with the above patch.
Yeah I saw that. I'm spinning a v2 of the pull request. Thanks
Andy
^ permalink raw reply
* [PATCH v2 1/3] drm/sun4i: hdmi: Check for unset best_parent in sun4i_tmds_determine_rate
From: Maxime Ripard @ 2018-01-04 19:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171226111227.4526-2-net147@gmail.com>
Hi,
On Tue, Dec 26, 2017 at 10:12:25PM +1100, Jonathan Liu wrote:
> We should check if the best match has been set before comparing it.
>
> Fixes: 9c5681011a0c ("drm/sun4i: Add HDMI support")
> Signed-off-by: Jonathan Liu <net147@gmail.com>
> ---
> drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
> index dc332ea56f6c..4d235e5ea31c 100644
> --- a/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
> +++ b/drivers/gpu/drm/sun4i/sun4i_hdmi_tmds_clk.c
> @@ -102,7 +102,7 @@ static int sun4i_tmds_determine_rate(struct clk_hw *hw,
> goto out;
> }
>
> - if (abs(rate - rounded / i) <
> + if (!best_parent || abs(rate - rounded / i) <
Why is that causing any issue?
If best_parent is set to 0...
> abs(rate - best_parent / best_div)) {
... the value returned here is going to be rate, which is going to be
higher than the first part of the comparison meaning ...
> best_parent = rounded;
... that best_parent is going to be set there.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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* [GIT PULL] Qualcomm Driver updates for 4.16
From: Andy Gross @ 2018-01-04 20:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514789609-4133-4-git-send-email-andy.gross@linaro.org>
Arnd/Olof/Kevin,
Please do not merge this pull request. I will be sending a v2
Andy
^ permalink raw reply
* [PATCH v5 01/12] dt-bindings: panel: lvds: Document power-supply property
From: Laurent Pinchart @ 2018-01-04 20:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104194436.reka6nw5hf32o4p3@flea.lan>
Hi Maxime,
On Thursday, 4 January 2018 21:44:36 EET Maxime Ripard wrote:
> On Fri, Dec 22, 2017 at 02:08:20PM +0200, Laurent Pinchart wrote:
> > On Thursday, 21 December 2017 13:02:27 EET Maxime Ripard wrote:
> >> The power-supply property is used by a vast majority of panels,
> >> including panel-simple. Let's document it as a common property
> >>
> >> Reviewed-by: Rob Herring <robh@kernel.org>
> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
> >> ---
> >>
> >> Documentation/devicetree/bindings/display/panel/panel-common.txt | 6 ++++
> >> Documentation/devicetree/bindings/display/panel/panel-lvds.txt | 1 +
> >> Documentation/devicetree/bindings/display/panel/simple-panel.txt | 2 +-
> >> 3 files changed, 8 insertions(+), 1 deletion(-)
> >>
> >> diff --git
> >> a/Documentation/devicetree/bindings/display/panel/panel-common.txt
> >> b/Documentation/devicetree/bindings/display/panel/panel-common.txt index
> >> ec52c472c845..125ea68052af 100644
> >> --- a/Documentation/devicetree/bindings/display/panel/panel-common.txt
> >> +++ b/Documentation/devicetree/bindings/display/panel/panel-common.txt
> >> @@ -78,6 +78,12 @@ used for panels that implement compatible control
> >> signals. while active. Active high reset signals can be supported by
> >> inverting the GPIO specifier polarity flag.
> >>
> >> +Power
> >> +-----
> >> +
> >> +- power-supply: many display panels need an additional power supply in
> >> + order to be fully powered-up. For such panels, power-supply contains
> >> + a phandle to the regulator powering the panel.
> >
> > I think we should give more details here about the limitations of this
> > property. How about the following explanation ?
> >
> > - power-supply: display panels require power to be supplied. While several
> > panels need more than one power supply with panel-specific constraints
> > governing the order and timings of the power supplies, in many cases a
> > single power supply is sufficient, either because the panel has a single
> > power rail, or because all its power rails can be driven by the same
> > supply. In that case the power-supply property specifies the supply
> > powering the panel as a phandle to a regulator.
>
> That works for me. Do you want me to resend it with that text, or
> should I merge it (and if so, with your Reviewed-by or Acked-by?)?
No need to resend if it's just for me. With the above text,
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
(on a side note, I wonder if it's more efficient to ask whether to resend
instead of just resending :-))
--
Regards,
Laurent Pinchart
^ permalink raw reply
* [PATCH] imx6: fix pcie enumeration
From: Bjorn Helgaas @ 2018-01-04 20:24 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515080883-30066-1-git-send-email-koen.vandeputte@ncentric.com>
[+cc Richard, Lucas, Lorenzo, linux-arm-kernel]
Hi Koen,
Thanks a lot for the fix!
Please run "git log --oneline drivers/pci/dwc/pci-imx6.c" and follow
the style convention, including "PCIe" capitalization.
"fix pcie enumeration" is not very descriptive. It should say something
about the specific problem, e.g., setting the root port's subordinate
bus number.
On Thu, Jan 04, 2018 at 04:48:03PM +0100, Koen Vandeputte wrote:
> By default, when the imx6 PCIe RC boots up, the subordinate is set
Not sure what "RC boots up" means. Maybe you're talking about a
hardware-defined default value at power-up, or maybe a value
programmed by a boot-loader? Please clarify and update the similar
comment in the code.
> equally to the secondary bus (1), and does not alter afterwards.
>
> This means that theoretically, the highest bus reachable downstream is
> bus 1.
Not just theoretically. If the bridge is operating correctly, it
should not forward any config transaction for a bus number greater
than the subordinate bus number.
> Before commit a20c7f36bd3d ("PCI: Do not allocate more buses than
> available in parent"), the driver ignored the subord value and just
> allowed up to 0xff on each device downstream.
>
> This caused a lot of errors to be printed, as this is not logical
> according to spec. (but it worked ..)
Including a sample error in the changelog might help somebody
suffering from the problem find this solution.
> After this commit, the driver stopped scanning deeper when the last
> allocated busnr equals the subordinate of it's master, causing devices
> to be undiscovered (especially behind bridges), uncovering the impact of
> this bug.
>
> Before:
>
> 00:00.0 PCI bridge: Synopsys, Inc. Device abcd (rev 01) (prog-if 00 ...
> Bus: primary=00, secondary=01, subordinate=01, sec-latency=0
>
> 00:00.0 0604: 16c3:abcd (rev 01)
> 01:00.0 0604: 10b5:8604 (rev ba)
> ... stops after bus 1 ...
>
> After:
>
> 00:00.0 PCI bridge: Synopsys, Inc. Device abcd (rev 01) (prog-if 00
> ...
> Bus: primary=00, secondary=01, subordinate=ff, sec-latency=0
>
> 00:00.0 0604: 16c3:abcd (rev 01)
> 01:00.0 0604: 10b5:8604 (rev ba)
> 02:01.0 0604: 10b5:8604 (rev ba)
> 02:04.0 0604: 10b5:8604 (rev ba)
> 02:05.0 0604: 10b5:8604 (rev ba)
> 03:00.0 0280: 168c:0033 (rev 01)
> 05:00.0 0280: 168c:0033 (rev 01)
>
Should have a "Fixes: a20c7f36bd3d ..." tag if that's really the
correct commit.
> Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
> ---
>
> Needs backports to 4.14 & 4.9 stables
Add a "CC: stable at vger.kernel.org" after your signed-off-by to handle
this. But something's wrong because a20c7f36bd3d only appeared in
v4.15-rc1, so either that's the wrong commit or stable kernels don't
need the fix.
> drivers/pci/dwc/pci-imx6.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/pci/dwc/pci-imx6.c b/drivers/pci/dwc/pci-imx6.c
> index b73483534a5b..3d13fa8c2eb1 100644
> --- a/drivers/pci/dwc/pci-imx6.c
> +++ b/drivers/pci/dwc/pci-imx6.c
> @@ -76,6 +76,9 @@ struct imx6_pcie {
>
> #define PCIE_RC_LCSR 0x80
>
> +#define PCIE_RC_BNR 0x18
> +#define PCIE_RC_BNR_MAX_SUBORDINATE (0xff << 16)
> +
> /* PCIe Port Logic registers (memory-mapped) */
> #define PL_OFFSET 0x700
> #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
> @@ -562,6 +565,17 @@ static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
> int ret;
>
> /*
> + * By default, the subordinate is set equally to the secondary
> + * bus (0x01) when the RC boots.
> + * This means that theoretically, only bus 1 is reachable from the RC.
> + * Force the PCIe RC subordinate to 0xff, otherwise no downstream
> + * devices will be detected behind bus 1.
> + */
> + tmp = dw_pcie_readl_rc(pp, PCIE_RC_BNR);
> + tmp |= PCIE_RC_BNR_MAX_SUBORDINATE;
> + dw_pcie_writel_rc(pp, PCIE_RC_BNR, tmp);
This functionality is not related to establishing the link, so I think
it should be put elsewhere, maybe either directly in imx6_pcie_probe()
or in imx6_pcie_host_init().
The DT really should contain a "bus-range" property and
dw_pcie_host_init() will already pay attention to that if it's
present, and I think it defaults to 0-0xff if it's not present.
So I think you should be using pp->busn instead of hard-coding
PCIE_RC_BNR_MAX_SUBORDINATE.
> + /*
> * Force Gen1 operation when starting the link. In case the link is
> * started in Gen2 mode, there is a possibility the devices on the
> * bus will not be detected at all. This happens with PCIe switches.
> --
> 2.7.4
>
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