* [PATCH v3 0/2] Xilinx ZynqMP IPI Mailbox Controller Driver
From: Wendy Liang @ 2018-01-04 23:51 UTC (permalink / raw)
To: linux-arm-kernel
Introduce mailbox controller driver for ZynqMP IPI(Inter-processor
interrupt) IP core.
There is previous discussion on the DT bindings:
https://patchwork.kernel.org/patch/10012755/
v3:
- add NULL entry to of_device_id of IPI controller
v2:
- change SPDX-License-Identifier license text style in .c file
- replace xlnx-ipi-ids with xlnx,ipi-ids
Wendy Liang (2):
mailbox: ZynqMP IPI mailbox controller
dt-bindings: mailbox: Add Xilinx IPI Mailbox
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 104 ++++
drivers/mailbox/Kconfig | 8 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 635 +++++++++++++++++++++
include/linux/mailbox/zynqmp-ipi-message.h | 24 +
5 files changed, 773 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
--
2.7.4
^ permalink raw reply
* [PATCH v3 1/2] mailbox: ZynqMP IPI mailbox controller
From: Wendy Liang @ 2018-01-04 23:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515109891-17133-1-git-send-email-jliang@xilinx.com>
This patch is to introduce ZynqMP IPI mailbox controller driver
to use the ZynqMP IPI block as mailboxes.
Signed-off-by: Wendy Liang <jliang@xilinx.com>
---
drivers/mailbox/Kconfig | 8 +
drivers/mailbox/Makefile | 2 +
drivers/mailbox/zynqmp-ipi-mailbox.c | 635 +++++++++++++++++++++++++++++
include/linux/mailbox/zynqmp-ipi-message.h | 24 ++
4 files changed, 669 insertions(+)
create mode 100644 drivers/mailbox/zynqmp-ipi-mailbox.c
create mode 100644 include/linux/mailbox/zynqmp-ipi-message.h
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index ba2f152..876614a 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -171,4 +171,12 @@ config BCM_FLEXRM_MBOX
Mailbox implementation of the Broadcom FlexRM ring manager,
which provides access to various offload engines on Broadcom
SoCs. Say Y here if you want to use the Broadcom FlexRM.
+
+config ZYNQMP_IPI_MBOX
+ tristate "Xilinx ZynqMP IPI Mailbox"
+ depends on ARCH_ZYNQMP && OF
+ help
+ Mailbox implementation for Xilinx ZynqMP IPI. It is used to send
+ notification or short message between processors with Xilinx
+ ZynqMP IPI.
endif
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 4896f8d..155f72f 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -36,3 +36,5 @@ obj-$(CONFIG_BCM_FLEXRM_MBOX) += bcm-flexrm-mailbox.o
obj-$(CONFIG_QCOM_APCS_IPC) += qcom-apcs-ipc-mailbox.o
obj-$(CONFIG_TEGRA_HSP_MBOX) += tegra-hsp.o
+
+obj-$(CONFIG_ZYNQMP_IPI_MBOX) += zynqmp-ipi-mailbox.o
diff --git a/drivers/mailbox/zynqmp-ipi-mailbox.c b/drivers/mailbox/zynqmp-ipi-mailbox.c
new file mode 100644
index 0000000..4258360d
--- /dev/null
+++ b/drivers/mailbox/zynqmp-ipi-mailbox.c
@@ -0,0 +1,635 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Xilinx Inter Processor Interrupt(IPI) Mailbox Driver
+ *
+ * Copyright (C) 2017 Xilinx Inc.
+ *
+ */
+
+#define pr_fmt(fmt) "%s: " fmt, __func__
+
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/mailbox_controller.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/arm-smccc.h>
+#include <linux/delay.h>
+#include <linux/mailbox/zynqmp-ipi-message.h>
+
+/* IPI agent ID any */
+#define IPI_ID_ANY 0xFFUL
+
+/* indicate if ZynqMP IPI mailbox driver uses SMC calls or HVC calls */
+#define USE_SMC 0
+#define USE_HVC 1
+
+/* Default IPI SMC function IDs */
+#define SMC_IPI_MAILBOX_OPEN 0x82001000U
+#define SMC_IPI_MAILBOX_RELEASE 0x82001001U
+#define SMC_IPI_MAILBOX_STATUS_ENQUIRY 0x82001002U
+#define SMC_IPI_MAILBOX_NOTIFY 0x82001003U
+#define SMC_IPI_MAILBOX_ACK 0x82001004U
+#define SMC_IPI_MAILBOX_ENABLE_IRQ 0x82001005U
+#define SMC_IPI_MAILBOX_DISABLE_IRQ 0x82001006U
+
+/* IPI SMC Macros */
+#define IPI_SMC_OPEN_IRQ_MASK 0x00000001UL /* IRQ enable bit in IPI
+ * open SMC call
+ */
+#define IPI_SMC_NOTIFY_BLOCK_MASK 0x00000001UL /* Flag to indicate if
+ * IPI notification needs
+ * to be blocking.
+ */
+#define IPI_SMC_ENQUIRY_DIRQ_MASK 0x00000001UL /* Flag to indicate if
+ * notification interrupt
+ * to be disabled.
+ */
+#define IPI_SMC_ACK_EIRQ_MASK 0x00000001UL /* Flag to indicate if
+ * notification interrupt
+ * to be enabled.
+ */
+
+/* IPI mailbox status */
+#define IPI_MB_STATUS_IDLE 0
+#define IPI_MB_STATUS_SEND_PENDING 1
+#define IPI_MB_STATUS_RECV_PENDING 2
+
+#define IPI_MB_CHNL_TX 0 /* IPI mailbox TX channel */
+#define IPI_MB_CHNL_RX 1 /* IPI mailbox RX channel */
+
+/**
+ * struct zynqmp_ipi_mchan - Description of a Xilinx ZynqMP IPI mailbox channel
+ * @is_opened: indicate if the IPI channel is opened
+ * @req_buf: local to remote request buffer start address
+ * @resp_buf: local to remote response buffer start address
+ * @req_buf_size: request buffer size
+ * @resp_buf_size: response buffer size
+ * @chan_type: channel type
+ */
+struct zynqmp_ipi_mchan {
+ int is_opened;
+ void __iomem *req_buf;
+ void __iomem *resp_buf;
+ size_t req_buf_size;
+ size_t resp_buf_size;
+ unsigned int chan_type;
+};
+
+/**
+ * struct zynqmp_ipi_mbox_pdata - Description of a ZynqMP IPI mailbox
+ * platform data.
+ * @dev: device pointer corresponding to the Xilinx ZynqMP
+ * IPI mailbox
+ * @local_id: local IPI agent ID
+ * @remote_id: remote IPI agent ID
+ * @method: IPI SMC or HVC is going to be used
+ * @mbox: mailbox Controller
+ * @mchans: array for channels, tx channel and rx channel.
+ * @irq: IPI agent interrupt ID
+ * @lock: IPI mailbox platform data lock
+ */
+struct zynqmp_ipi_mbox_pdata {
+ struct device *dev;
+ u32 local_id;
+ u32 remote_id;
+ unsigned int method;
+ struct mbox_controller mbox;
+ struct zynqmp_ipi_mchan mchans[2];
+ int irq;
+ spinlock_t lock; /* spin lock for local data */
+};
+
+static void zynqmp_ipi_fw_call(struct zynqmp_ipi_mbox_pdata *pdata,
+ unsigned long a0, unsigned long a3,
+ unsigned long a4, unsigned long a5,
+ unsigned long a6, unsigned long a7,
+ struct arm_smccc_res *res)
+{
+ unsigned long a1, a2;
+
+ a1 = pdata->local_id;
+ a2 = pdata->remote_id;
+ if (pdata->method == USE_SMC)
+ arm_smccc_smc(a0, a1, a2, a3, a4, a5, a6, a7, res);
+ else
+ arm_smccc_hvc(a0, a1, a2, a3, a4, a5, a6, a7, res);
+}
+
+/**
+ * zynqmp_ipi_interrupt - Interrupt handler for IPI notification
+ *
+ * @irq: Interrupt number
+ * @data: ZynqMP IPI mailbox platform data.
+ *
+ * Return: -EINVAL if there is no instance
+ * IRQ_NONE if the interrupt is not ours.
+ * IRQ_HANDLED if the rx interrupt was successfully handled.
+ */
+static irqreturn_t zynqmp_ipi_interrupt(int irq, void *data)
+{
+ struct zynqmp_ipi_mbox_pdata *pdata = data;
+ struct mbox_chan *chan;
+ struct zynqmp_ipi_mchan *mchan;
+ struct zynqmp_ipi_message msg;
+ u64 arg0, arg3;
+ struct arm_smccc_res res;
+ int ret;
+
+ arg0 = SMC_IPI_MAILBOX_STATUS_ENQUIRY;
+ arg3 = IPI_SMC_ENQUIRY_DIRQ_MASK;
+ zynqmp_ipi_fw_call(pdata, arg0, arg3, 0, 0, 0, 0, &res);
+ ret = (int)(res.a0 & 0xFFFFFFFF);
+ if (ret > 0 && ret & IPI_MB_STATUS_RECV_PENDING) {
+ chan = &pdata->mbox.chans[IPI_MB_CHNL_RX];
+ mchan = chan->con_priv;
+ if (mchan->is_opened) {
+ msg.len = mchan->req_buf_size;
+ msg.data = mchan->req_buf;
+ /* Client will direclty copy data from
+ * IPI buffer to client data memory
+ */
+ mbox_chan_received_data(chan, (void *)&msg);
+ return IRQ_HANDLED;
+ }
+ }
+ return IRQ_NONE;
+}
+
+/**
+ * zynqmp_ipi_peek_data - Peek to see if there are any rx messages.
+ *
+ * @chan: Channel Pointer
+ *
+ * Return: 'true' if there is pending rx data, 'false' if there is none.
+ */
+static bool zynqmp_ipi_peek_data(struct mbox_chan *chan)
+{
+ struct device *dev = chan->mbox->dev;
+ struct zynqmp_ipi_mbox_pdata *pdata = dev_get_drvdata(dev);
+ struct zynqmp_ipi_mchan *mchan = chan->con_priv;
+ int ret;
+ u64 arg0;
+ struct arm_smccc_res res;
+
+ if (WARN_ON(!pdata)) {
+ dev_err(dev, "no platform drv data??\n");
+ return false;
+ }
+
+ arg0 = SMC_IPI_MAILBOX_STATUS_ENQUIRY;
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ ret = (int)(res.a0 & 0xFFFFFFFF);
+
+ if (mchan->chan_type == IPI_MB_CHNL_TX) {
+ /* TX channel, check if the message has been acked
+ * by the remote, if yes, response is available.
+ */
+ if (ret < 0 || ret & IPI_MB_STATUS_SEND_PENDING)
+ return false;
+ else
+ return true;
+ } else if (ret > 0 && ret & IPI_MB_STATUS_RECV_PENDING) {
+ /* RX channel, check if there is message arrived. */
+ return true;
+ }
+ return false;
+}
+
+/**
+ * zynqmp_ipi_last_tx_done - See if the last tx message is sent
+ *
+ * @chan: Channel pointer
+ *
+ * Return: 'true' is no pending tx data, 'false' if there are any.
+ */
+static bool zynqmp_ipi_last_tx_done(struct mbox_chan *chan)
+{
+ struct device *dev = chan->mbox->dev;
+ struct zynqmp_ipi_mbox_pdata *pdata = dev_get_drvdata(dev);
+ struct zynqmp_ipi_mchan *mchan = chan->con_priv;
+ int ret;
+ u64 arg0;
+ struct arm_smccc_res res;
+ struct zynqmp_ipi_message msg;
+
+ if (WARN_ON(!pdata)) {
+ dev_err(dev, "no platform drv data??\n");
+ return false;
+ }
+
+ if (mchan->chan_type == IPI_MB_CHNL_TX) {
+ /* We only need to check if the message been taken
+ * by the remote in the TX channel
+ */
+ arg0 = SMC_IPI_MAILBOX_STATUS_ENQUIRY;
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ /* Check the SMC call status, a0 of the result */
+ ret = (int)(res.a0 & 0xFFFFFFFF);
+ if (ret < 0 || ret & IPI_MB_STATUS_SEND_PENDING)
+ return false;
+
+ msg.len = mchan->resp_buf_size;
+ msg.data = mchan->resp_buf;
+ /* Client will direclty copy data from
+ * IPI buffer to client data memory
+ */
+ mbox_chan_received_data(chan, (void *)&msg);
+ return true;
+ }
+ /* Always true for the response message in RX channel */
+ return true;
+}
+
+/**
+ * zynqmp_ipi_send_data - Send data
+ *
+ * @chan: Channel Pointer
+ * @data: Message Pointer
+ *
+ * Return: 0 if all goes good, else appropriate error messages.
+ */
+static int zynqmp_ipi_send_data(struct mbox_chan *chan, void *data)
+{
+ struct device *dev = chan->mbox->dev;
+ struct zynqmp_ipi_mbox_pdata *pdata = dev_get_drvdata(dev);
+ struct zynqmp_ipi_mchan *mchan = chan->con_priv;
+ struct zynqmp_ipi_message *msg = data;
+ u64 arg0;
+ struct arm_smccc_res res;
+ u32 timeout;
+ int ret;
+
+ if (WARN_ON(!pdata)) {
+ dev_err(dev, "no platform drv data??\n");
+ return -EINVAL;
+ }
+
+ if (mchan->chan_type == IPI_MB_CHNL_TX) {
+ /* Send request message */
+ if (msg && msg->len > mchan->resp_buf_size) {
+ dev_err(dev, "channel %d message length %u > max %lu\n",
+ mchan->chan_type, (unsigned int)msg->len,
+ mchan->resp_buf_size);
+ return -EINVAL;
+ }
+ /* Enquire if the mailbox is free to send message */
+ arg0 = SMC_IPI_MAILBOX_STATUS_ENQUIRY;
+ timeout = 10;
+ do {
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ ret = res.a0 & 0xFFFFFFFF;
+ if (ret >= 0 && !(ret & IPI_MB_STATUS_SEND_PENDING))
+ break;
+ usleep_range(1, 2);
+ timeout--;
+ } while (timeout);
+ if (!timeout) {
+ dev_warn(dev, "channel %d sending msg timesout.\n",
+ pdata->remote_id);
+ return -ETIME;
+ }
+ /* Copy message to the request buffer */
+ if (msg && msg->len)
+ memcpy_toio(mchan->req_buf, msg->data, msg->len);
+ /* Kick IPI mailbox to send message */
+ arg0 = SMC_IPI_MAILBOX_NOTIFY;
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ } else {
+ /* Send response message */
+ if (msg && msg->len > mchan->resp_buf_size) {
+ dev_err(dev, "channel %d message length %u > max %lu\n",
+ mchan->chan_type, (unsigned int)msg->len,
+ mchan->resp_buf_size);
+ return -EINVAL;
+ }
+ if (msg && msg->len)
+ memcpy(mchan->resp_buf, msg->data, msg->len);
+ arg0 = SMC_IPI_MAILBOX_NOTIFY;
+ arg0 = SMC_IPI_MAILBOX_ACK;
+ zynqmp_ipi_fw_call(pdata, arg0, IPI_SMC_ACK_EIRQ_MASK,
+ 0, 0, 0, 0, &res);
+ }
+ return 0;
+}
+
+/**
+ * zynqmp_ipi_startup - Startup the IPI channel
+ *
+ * @chan: Channel pointer
+ *
+ * Return: 0 if all goes good, else return corresponding error message
+ */
+static int zynqmp_ipi_startup(struct mbox_chan *chan)
+{
+ struct device *dev = chan->mbox->dev;
+ struct zynqmp_ipi_mbox_pdata *pdata = dev_get_drvdata(dev);
+ struct zynqmp_ipi_mchan *mchan = chan->con_priv;
+ u64 arg0;
+ struct arm_smccc_res res;
+ int ret = 0;
+ unsigned long flags;
+ unsigned int nchan_type;
+
+ spin_lock_irqsave(&pdata->lock, flags);
+ if (mchan->is_opened) {
+ /* IPI mailbox has been opened */
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return -EBUSY;
+ }
+
+ /* If no channel has been opened, open the IPI mailbox */
+ nchan_type = (mchan->chan_type + 1) % 2;
+ if (!pdata->mchans[nchan_type].is_opened) {
+ arg0 = SMC_IPI_MAILBOX_OPEN;
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ /* Check the SMC call status, a0 of the result */
+ ret = (int)(res.a0 | 0xFFFFFFFF);
+ if (res.a0 < 0) {
+ dev_err(dev, "SMC to open the IPI channel failed.\n");
+ ret = res.a0;
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return ret;
+ }
+ ret = 0;
+ }
+
+ /* If it is RX channel, enable the IPI notification interrupt */
+ if (mchan->chan_type == IPI_MB_CHNL_RX) {
+ arg0 = SMC_IPI_MAILBOX_ENABLE_IRQ;
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ }
+ mchan->is_opened = 1;
+ spin_unlock_irqrestore(&pdata->lock, flags);
+
+ return ret;
+}
+
+/**
+ * zynqmp_ipi_shutdown - Shutdown the IPI channel
+ *
+ * @chan: Channel pointer
+ */
+static void zynqmp_ipi_shutdown(struct mbox_chan *chan)
+{
+ struct device *dev = chan->mbox->dev;
+ struct zynqmp_ipi_mbox_pdata *pdata = dev_get_drvdata(dev);
+ struct zynqmp_ipi_mchan *mchan = chan->con_priv;
+ u64 arg0;
+ struct arm_smccc_res res;
+ unsigned long flags;
+ unsigned int chan_type;
+
+ spin_lock_irqsave(&pdata->lock, flags);
+ if (!mchan->is_opened) {
+ spin_unlock_irqrestore(&pdata->lock, flags);
+ return;
+ }
+
+ /* If it is RX channel, disable notification interrupt */
+ chan_type = mchan->chan_type;
+ if (chan_type == IPI_MB_CHNL_RX) {
+ arg0 = SMC_IPI_MAILBOX_DISABLE_IRQ;
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ }
+ /* Release IPI mailbox if no other channel is opened */
+ chan_type = (chan_type + 1) % 2;
+ if (!pdata->mchans[chan_type].is_opened) {
+ arg0 = SMC_IPI_MAILBOX_RELEASE;
+ zynqmp_ipi_fw_call(pdata, arg0, 0, 0, 0, 0, 0, &res);
+ }
+
+ mchan->is_opened = 0;
+ spin_unlock_irqrestore(&pdata->lock, flags);
+}
+
+/* ZynqMP IPI mailbox operations */
+static const struct mbox_chan_ops zynqmp_ipi_chan_ops = {
+ .startup = zynqmp_ipi_startup,
+ .shutdown = zynqmp_ipi_shutdown,
+ .peek_data = zynqmp_ipi_peek_data,
+ .last_tx_done = zynqmp_ipi_last_tx_done,
+ .send_data = zynqmp_ipi_send_data,
+};
+
+/**
+ * zynqmp_ipi_of_xlate - Translate of phandle to IPI mailbox channel
+ *
+ * @mbox: mailbox controller pointer
+ * @p: phandle pointer
+ *
+ * Return: Mailbox channel, else return error pointer.
+ */
+static struct mbox_chan *zynqmp_ipi_of_xlate(struct mbox_controller *mbox,
+ const struct of_phandle_args *p)
+{
+ struct zynqmp_ipi_mbox_pdata *pdata;
+ struct mbox_chan *chan;
+ struct device *dev = mbox->dev;
+ unsigned int chan_type;
+
+ pdata = container_of(mbox, struct zynqmp_ipi_mbox_pdata, mbox);
+
+ /* Only supports TX and RX channels */
+ chan_type = p->args[0];
+ if (chan_type != IPI_MB_CHNL_TX && chan_type != IPI_MB_CHNL_RX) {
+ dev_err(dev, "req chnl failure: invalid chnl type %u.\n",
+ chan_type);
+ return ERR_PTR(-EINVAL);
+ }
+ chan = &mbox->chans[chan_type];
+ return chan;
+}
+
+static const struct of_device_id zynqmp_ipi_of_match[] = {
+ {.compatible = "xlnx,zynqmp-ipi-mailbox"},
+ {},
+};
+MODULE_DEVICE_TABLE(of, zynqmp_ipi_of_match);
+
+static int zynqmp_ipi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = pdev->dev.of_node;
+ struct zynqmp_ipi_mbox_pdata *pdata;
+ struct zynqmp_ipi_mchan *mchan;
+ struct mbox_chan *chans;
+ struct mbox_controller *mbox;
+ const unsigned char *prop;
+ struct resource *res;
+ int ret = -EINVAL;
+
+ pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
+ if (!pdata)
+ return -ENOMEM;
+
+ pdata->dev = dev;
+
+ mchan = &pdata->mchans[IPI_MB_CHNL_TX];
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "local_request_region");
+ if (res) {
+ mchan->req_buf_size = resource_size(res);
+ mchan->req_buf = devm_ioremap(&pdev->dev, res->start,
+ mchan->req_buf_size);
+ if (IS_ERR(mchan->req_buf)) {
+ dev_err(dev, "Unable to map IPI buffer I/O memory\n");
+ ret = PTR_ERR(mchan->req_buf);
+ return ret;
+ }
+ }
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "remote_response_region");
+ if (res) {
+ mchan->resp_buf_size = resource_size(res);
+ mchan->resp_buf = devm_ioremap(&pdev->dev, res->start,
+ mchan->resp_buf_size);
+ if (IS_ERR(mchan->resp_buf)) {
+ dev_err(dev, "Unable to map IPI buffer I/O memory\n");
+ ret = PTR_ERR(mchan->resp_buf);
+ return ret;
+ }
+ }
+
+ mchan = &pdata->mchans[IPI_MB_CHNL_RX];
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "remote_request_region");
+ if (res) {
+ mchan->req_buf_size = resource_size(res);
+ mchan->req_buf = devm_ioremap(&pdev->dev, res->start,
+ mchan->req_buf_size);
+ if (IS_ERR(mchan->req_buf)) {
+ dev_err(dev, "Unable to map IPI buffer I/O memory\n");
+ ret = PTR_ERR(mchan->req_buf);
+ return ret;
+ }
+ }
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
+ "local_response_region");
+ if (res) {
+ mchan->resp_buf_size = resource_size(res);
+ mchan->resp_buf = devm_ioremap(&pdev->dev, res->start,
+ mchan->resp_buf_size);
+ if (IS_ERR(mchan->resp_buf)) {
+ dev_err(dev, "Unable to map IPI buffer I/O memory\n");
+ ret = PTR_ERR(mchan->resp_buf);
+ return ret;
+ }
+ }
+
+ /* Get the IPI local and remote agents IDs */
+ ret = of_property_read_u32_index(np, "xlnx,ipi-ids", 0,
+ &pdata->local_id);
+ if (ret < 0) {
+ dev_err(dev, "No IPI local ID is specified.\n");
+ return ret;
+ }
+ ret = of_property_read_u32_index(np, "xlnx,ipi-ids", 1,
+ &pdata->remote_id);
+ if (ret < 0) {
+ dev_err(dev, "No IPI remote ID is specified.\n");
+ return ret;
+ }
+
+ /* Get how to access IPI agent method */
+ prop = of_get_property(np, "method", NULL);
+ if (!prop) {
+ pdata->method = USE_SMC;
+ } else if (!strcmp(prop, "smc")) {
+ pdata->method = USE_SMC;
+ } else if (!strcmp(prop, "hvc")) {
+ pdata->method = USE_HVC;
+ } else {
+ dev_err(dev, "Invalid \"method\" %s.\n", prop);
+ return ret;
+ }
+
+ /* IPI IRQ */
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "unable to find IPI IRQ.\n");
+ return ret;
+ }
+ pdata->irq = ret;
+ ret = devm_request_irq(dev, pdata->irq, zynqmp_ipi_interrupt,
+ IRQF_SHARED, dev_name(dev), pdata);
+ if (ret) {
+ dev_err(dev, "IRQ %d is not requested successfully.\n",
+ pdata->irq);
+ return ret;
+ }
+
+ mbox = &pdata->mbox;
+ mbox->dev = dev;
+ mbox->ops = &zynqmp_ipi_chan_ops;
+ mbox->num_chans = 2;
+ mbox->txdone_irq = false;
+ mbox->txdone_poll = true;
+ mbox->txpoll_period = 5;
+ mbox->of_xlate = zynqmp_ipi_of_xlate;
+ chans = devm_kzalloc(dev, 2 * sizeof(*chans), GFP_KERNEL);
+ if (!chans)
+ return -ENOMEM;
+ mbox->chans = chans;
+ mbox->chans[IPI_MB_CHNL_TX].con_priv = &pdata->mchans[IPI_MB_CHNL_TX];
+ mbox->chans[IPI_MB_CHNL_RX].con_priv = &pdata->mchans[IPI_MB_CHNL_RX];
+ pdata->mchans[IPI_MB_CHNL_TX].chan_type = IPI_MB_CHNL_TX;
+ pdata->mchans[IPI_MB_CHNL_RX].chan_type = IPI_MB_CHNL_RX;
+ spin_lock_init(&pdata->lock);
+ platform_set_drvdata(pdev, pdata);
+ ret = mbox_controller_register(mbox);
+ if (ret)
+ dev_err(dev, "Failed to register mbox_controller(%d)\n", ret);
+ else
+ dev_info(dev, "Probed ZynqMP IPI Mailbox driver.\n");
+ return ret;
+}
+
+static int zynqmp_ipi_remove(struct platform_device *pdev)
+{
+ struct zynqmp_ipi_mbox_pdata *pdata;
+
+ pdata = platform_get_drvdata(pdev);
+ mbox_controller_unregister(&pdata->mbox);
+
+ return 0;
+}
+
+static struct platform_driver zynqmp_ipi_driver = {
+ .probe = zynqmp_ipi_probe,
+ .remove = zynqmp_ipi_remove,
+ .driver = {
+ .name = "zynqmp-ipi",
+ .of_match_table = of_match_ptr(zynqmp_ipi_of_match),
+ },
+};
+
+static struct class zynqmp_ipi_class = { .name = "zynqmp_ipi_mbox", };
+
+static int __init zynqmp_ipi_init(void)
+{
+ int err;
+
+ err = class_register(&zynqmp_ipi_class);
+ if (err)
+ return err;
+
+ return platform_driver_register(&zynqmp_ipi_driver);
+}
+subsys_initcall(zynqmp_ipi_init);
+
+static void __exit zynqmp_ipi_exit(void)
+{
+ platform_driver_unregister(&zynqmp_ipi_driver);
+ class_unregister(&zynqmp_ipi_class);
+}
+module_exit(zynqmp_ipi_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Xilinx ZynqMP IPI Mailbox driver");
+MODULE_AUTHOR("Xilinx Inc.");
diff --git a/include/linux/mailbox/zynqmp-ipi-message.h b/include/linux/mailbox/zynqmp-ipi-message.h
new file mode 100644
index 0000000..173c41d
--- /dev/null
+++ b/include/linux/mailbox/zynqmp-ipi-message.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2017 Xilinx Inc.
+ *
+ */
+
+#ifndef _LINUX_ZYNQMP_IPI_MESSAGE_H_
+#define _LINUX_ZYNQMP_IPI_MESSAGE_H_
+
+/**
+ * struct zynqmp_ipi_message - ZynqMP IPI message structure
+ * @len: Length of the request message
+ * @data: Request message pointer
+ *
+ * This is the structure for data used in mbox_send_message
+ * the maximum length of data buffer is fixed to 12 bytes.
+ * Client is supposed to be aware of this.
+ */
+struct zynqmp_ipi_message {
+ size_t len;
+ u8 *data;
+};
+
+#endif /* _LINUX_ZYNQMP_IPI_MESSAGE_H_ */
--
2.7.4
^ permalink raw reply related
* [PATCH v3 2/2] dt-bindings: mailbox: Add Xilinx IPI Mailbox
From: Wendy Liang @ 2018-01-04 23:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515109891-17133-1-git-send-email-jliang@xilinx.com>
Xilinx ZynqMP IPI(Inter Processor Interrupt) is a hardware block
in ZynqMP SoC used for the communication between various processor
systems.
Signed-off-by: Wendy Liang <jliang@xilinx.com>
---
.../bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt | 104 +++++++++++++++++++++
1 file changed, 104 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
diff --git a/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
new file mode 100644
index 0000000..5e270a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.txt
@@ -0,0 +1,104 @@
+Xilinx IPI Mailbox Controller
+========================================
+
+The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
+messaging between two Xilinx Zynq UltraScale+ MPSoC IPI agents. Each IPI
+agent owns registers used for notification and buffers for message.
+
+ +-------------------------------------+
+ | Xilinx ZynqMP IPI Controller |
+ +-------------------------------------+
+ +--------------------------------------------------+
+ATF | |
+ | |
+ | |
+ +--------------------------+ |
+ | |
+ | |
+ +--------------------------------------------------+
+ +------------------------------------------+
+ | +----------------+ +----------------+ |
+Hardware | | IPI Agent | | IPI Buffers | |
+ | | Registers | | | |
+ | | | | | |
+ | +----------------+ +----------------+ |
+ | |
+ | Xilinx IPI Agent Block |
+ +------------------------------------------+
+
+
+Controller Device Node:
+===========================
+Required properties:
+--------------------
+- compatible: Shall be: "xlnx,zynqmp-ipi-mailbox"
+- reg: IPI buffers address ranges
+- reg-names: Names of the reg resources. It should have:
+ * local_request_region
+ - IPI request msg buffer written by local and read
+ by remote
+ * local_response_region
+ - IPI response msg buffer written by local and read
+ by remote
+ * remote_request_region
+ - IPI request msg buffer written by remote and read
+ by local
+ * remote_response_region
+ - IPI response msg buffer written by remote and read
+ by local
+- #mbox-cells: Shall be 1. It contains:
+ * tx(0) or rx(1) channel
+- xlnx,ipi-ids: Xilinx IPI agent IDs of the two peers of the
+ Xilinx IPI communication channel.
+- interrupt-parent: Phandle for the interrupt controller
+- interrupts: Interrupt information corresponding to the
+ interrupt-names property.
+
+Optional properties:
+--------------------
+- method: The method of accessing the IPI agent registers.
+ Permitted values are: "smc" and "hvc". Default is
+ "smc".
+
+Example:
+===========================
+ /* APU<->RPU0 IPI mailbox controller */
+ ipi_mailbox_rpu0: mailbox at ff90400 {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ reg = <0x0 0xff990400 0x0 0x20>,
+ <0x0 0xff990420 0x0 0x20>,
+ <0x0 0xff990080 0x0 0x20>,
+ <0x0 0xff9900a0 0x0 0x20>;
+ reg-names = "local_request_region", "local_response_region",
+ "remote_request_region", "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx-ipi-ids = <0 1>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 29 4>;
+ };
+ /* APU<->RPU1 IPI mailbox controller */
+ ipi_mailbox_rpu1: mailbox at ff990440 {
+ compatible = "xlnx,zynqmp-ipi-mailbox";
+ reg = <0x0 0xff990440 0x0 0x20>,
+ <0x0 0xff990460 0x0 0x20>,
+ <0x0 0xff990280 0x0 0x20>,
+ <0x0 0xff9902a0 0x0 0x20>;
+ reg-names = "local_request_region", "local_response_region",
+ "remote_request_region", "remote_response_region";
+ #mbox-cells = <1>;
+ xlnx-ipi-ids = <0 2>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 29 4>;
+ };
+ rpu0 {
+ ...
+ mboxes = <&ipi_mailbox_rpu0 0>,
+ <&ipi_mailbox_rpu0 1>;
+ mbox-names = "tx", "rx";
+ };
+ rpu1 {
+ ...
+ mboxes = <&ipi_mailbox_rpu1 0>,
+ <&ipi_mailbox_rpu1 1>;
+ mbox-names = "tx", "rx";
+ };
--
2.7.4
^ permalink raw reply related
* [PATCH 0/7] clk: add helper functions for managing clk_onecell_data
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
I am writing some clock drivers that use struct clk_onecell_data a few
times, so I decided to write a helper function to allocate the memory
since it is a two step process and can be tedious. Then I noticed that
mediatek already had such a helper function, so I have moved that to the
clk core and made use of it in other drivers where possible.
David Lechner (7):
clk: add helper function for allocating clk_onecell_data
clk: mediatek: make use of clk_alloc_onecell_data()
clk: qoriq: make use of clk_alloc_onecell_data()
clk: hisilicon: make use of clk_alloc_onecell_data()
clk: rockchip: make use of clk_alloc_onecell_data()
clk: st: make use of clk_alloc_onecell_data()
clk: sunxi: make use of clk_alloc_onecell_data()
drivers/clk/clk-qoriq.c | 13 +++------
drivers/clk/clk.c | 49 ++++++++++++++++++++++++++++++++
drivers/clk/hisilicon/clk-hi3620.c | 7 +----
drivers/clk/mediatek/clk-mt2701-bdp.c | 2 +-
drivers/clk/mediatek/clk-mt2701-eth.c | 2 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 2 +-
drivers/clk/mediatek/clk-mt2701-img.c | 2 +-
drivers/clk/mediatek/clk-mt2701-mm.c | 2 +-
drivers/clk/mediatek/clk-mt2701-vdec.c | 2 +-
drivers/clk/mediatek/clk-mt2701.c | 10 +++----
drivers/clk/mediatek/clk-mt2712-bdp.c | 2 +-
drivers/clk/mediatek/clk-mt2712-img.c | 2 +-
drivers/clk/mediatek/clk-mt2712-jpgdec.c | 2 +-
drivers/clk/mediatek/clk-mt2712-mfg.c | 2 +-
drivers/clk/mediatek/clk-mt2712-mm.c | 2 +-
drivers/clk/mediatek/clk-mt2712-vdec.c | 2 +-
drivers/clk/mediatek/clk-mt2712-venc.c | 2 +-
drivers/clk/mediatek/clk-mt2712.c | 12 ++++----
drivers/clk/mediatek/clk-mt6797-img.c | 2 +-
drivers/clk/mediatek/clk-mt6797-mm.c | 2 +-
drivers/clk/mediatek/clk-mt6797-vdec.c | 2 +-
drivers/clk/mediatek/clk-mt6797-venc.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 8 +++---
drivers/clk/mediatek/clk-mt7622-aud.c | 2 +-
drivers/clk/mediatek/clk-mt7622-eth.c | 4 +--
drivers/clk/mediatek/clk-mt7622-hif.c | 4 +--
drivers/clk/mediatek/clk-mt7622.c | 8 +++---
drivers/clk/mediatek/clk-mt8135.c | 8 +++---
drivers/clk/mediatek/clk-mt8173.c | 18 ++++++------
drivers/clk/mediatek/clk-mtk.c | 25 ----------------
drivers/clk/mediatek/clk-mtk.h | 2 --
drivers/clk/rockchip/clk-rockchip.c | 11 +------
drivers/clk/st/clk-flexgen.c | 17 ++++-------
drivers/clk/st/clkgen-fsyn.c | 11 +------
drivers/clk/st/clkgen-pll.c | 12 ++------
drivers/clk/sunxi/clk-a10-pll2.c | 14 +++------
drivers/clk/sunxi/clk-mod0.c | 13 ++-------
drivers/clk/sunxi/clk-simple-gates.c | 13 ++-------
drivers/clk/sunxi/clk-sun8i-bus-gates.c | 13 ++-------
drivers/clk/sunxi/clk-sunxi.c | 14 +++------
drivers/clk/sunxi/clk-usb.c | 8 +-----
include/linux/clk-provider.h | 3 ++
42 files changed, 138 insertions(+), 195 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH 1/7] clk: add helper functions for managing clk_onecell_data
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
This adds helper functions for allocating and freeing struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/clk.c | 49 ++++++++++++++++++++++++++++++++++++++++++++
include/linux/clk-provider.h | 3 +++
2 files changed, 52 insertions(+)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index e24968f..83c8df7 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -3551,6 +3551,55 @@ struct clk_hw *of_clk_hw_simple_get(struct of_phandle_args *clkspec, void *data)
}
EXPORT_SYMBOL_GPL(of_clk_hw_simple_get);
+/**
+ * clk_alloc_onecell_data - allocate new struct clk_onecell_data
+ * @num_clks: Number of clock pointers to allocate
+ *
+ * An array of clock pointers is allocated and each clock pointer is
+ * initialized to ERR_PTR(-ENOENT).
+ *
+ * Returns: Pointer to struct clk_onecell_data or NULL on failure.
+ */
+struct clk_onecell_data *clk_alloc_onecell_data(size_t num_clks)
+{
+ struct clk_onecell_data *clk_data;
+ int i;
+
+ clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ if (!clk_data)
+ return NULL;
+
+ clk_data->clks = kcalloc(num_clks, sizeof(*clk_data->clks), GFP_KERNEL);
+ if (!clk_data->clks) {
+ kfree(clk_data);
+ return NULL;
+ }
+
+ for (i = 0; i < num_clks; i++)
+ clk_data->clks[i] = ERR_PTR(-ENOENT);
+
+ clk_data->clk_num = num_clks;
+
+ return clk_data;
+}
+EXPORT_SYMBOL_GPL(clk_alloc_onecell_data);
+
+/**
+ * clk_free_onecell_data - frees @clk_data and associated resources
+ * @clk_data: Pointer to struct clk_onecelldata that was allocated with
+ * clk_alloc_onecell_data()
+ *
+ * It is safe to call this function even if @clk_data is NULL or an error value.
+ */
+void clk_free_onecell_data(struct clk_onecell_data *clk_data)
+{
+ if (IS_ERR_OR_NULL(clk_data))
+ return;
+
+ kfree(clk_data->clks);
+ kfree(clk_data);
+}
+
struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data)
{
struct clk_onecell_data *clk_data = data;
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 175a62a..b1f51f7 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -786,6 +786,9 @@ struct clk_onecell_data {
unsigned int clk_num;
};
+struct clk_onecell_data *clk_alloc_onecell_data(size_t num_clks);
+void clk_free_onecell_data(struct clk_onecell_data *clk_data);
+
struct clk_hw_onecell_data {
unsigned int num;
struct clk_hw *hws[];
--
2.7.4
^ permalink raw reply related
* [PATCH 2/7] clk: mediatek: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
A new function clk_alloc_onecell_data() has been added to the clk core
that performs the same function as mtk_alloc_clk_data(), so we can replace
all instances with the new function.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/mediatek/clk-mt2701-bdp.c | 2 +-
drivers/clk/mediatek/clk-mt2701-eth.c | 2 +-
drivers/clk/mediatek/clk-mt2701-hif.c | 2 +-
drivers/clk/mediatek/clk-mt2701-img.c | 2 +-
drivers/clk/mediatek/clk-mt2701-mm.c | 2 +-
drivers/clk/mediatek/clk-mt2701-vdec.c | 2 +-
drivers/clk/mediatek/clk-mt2701.c | 10 +++++-----
drivers/clk/mediatek/clk-mt2712-bdp.c | 2 +-
drivers/clk/mediatek/clk-mt2712-img.c | 2 +-
drivers/clk/mediatek/clk-mt2712-jpgdec.c | 2 +-
drivers/clk/mediatek/clk-mt2712-mfg.c | 2 +-
drivers/clk/mediatek/clk-mt2712-mm.c | 2 +-
drivers/clk/mediatek/clk-mt2712-vdec.c | 2 +-
drivers/clk/mediatek/clk-mt2712-venc.c | 2 +-
drivers/clk/mediatek/clk-mt2712.c | 12 ++++++------
drivers/clk/mediatek/clk-mt6797-img.c | 2 +-
drivers/clk/mediatek/clk-mt6797-mm.c | 2 +-
drivers/clk/mediatek/clk-mt6797-vdec.c | 2 +-
drivers/clk/mediatek/clk-mt6797-venc.c | 2 +-
drivers/clk/mediatek/clk-mt6797.c | 8 ++++----
drivers/clk/mediatek/clk-mt7622-aud.c | 2 +-
drivers/clk/mediatek/clk-mt7622-eth.c | 4 ++--
drivers/clk/mediatek/clk-mt7622-hif.c | 4 ++--
drivers/clk/mediatek/clk-mt7622.c | 8 ++++----
drivers/clk/mediatek/clk-mt8135.c | 8 ++++----
drivers/clk/mediatek/clk-mt8173.c | 18 +++++++++---------
drivers/clk/mediatek/clk-mtk.c | 25 -------------------------
drivers/clk/mediatek/clk-mtk.h | 2 --
28 files changed, 54 insertions(+), 81 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/clk-mt2701-bdp.c
index fe4964d..b055a92 100644
--- a/drivers/clk/mediatek/clk-mt2701-bdp.c
+++ b/drivers/clk/mediatek/clk-mt2701-bdp.c
@@ -113,7 +113,7 @@ static int clk_mt2701_bdp_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
+ clk_data = clk_alloc_onecell_data(CLK_BDP_NR);
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
index 9251a65..4b7570e 100644
--- a/drivers/clk/mediatek/clk-mt2701-eth.c
+++ b/drivers/clk/mediatek/clk-mt2701-eth.c
@@ -55,7 +55,7 @@ static int clk_mt2701_eth_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
+ clk_data = clk_alloc_onecell_data(CLK_ETHSYS_NR);
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
index 18f3723..0f0c785 100644
--- a/drivers/clk/mediatek/clk-mt2701-hif.c
+++ b/drivers/clk/mediatek/clk-mt2701-hif.c
@@ -52,7 +52,7 @@ static int clk_mt2701_hif_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
+ clk_data = clk_alloc_onecell_data(CLK_HIFSYS_NR);
mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2701-img.c b/drivers/clk/mediatek/clk-mt2701-img.c
index b7441c9..d66c3e4 100644
--- a/drivers/clk/mediatek/clk-mt2701-img.c
+++ b/drivers/clk/mediatek/clk-mt2701-img.c
@@ -55,7 +55,7 @@ static int clk_mt2701_img_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
+ clk_data = clk_alloc_onecell_data(CLK_IMG_NR);
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2701-mm.c b/drivers/clk/mediatek/clk-mt2701-mm.c
index fe1f850..02e4736 100644
--- a/drivers/clk/mediatek/clk-mt2701-mm.c
+++ b/drivers/clk/mediatek/clk-mt2701-mm.c
@@ -98,7 +98,7 @@ static int clk_mt2701_mm_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_MM_NR);
+ clk_data = clk_alloc_onecell_data(CLK_MM_NR);
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2701-vdec.c b/drivers/clk/mediatek/clk-mt2701-vdec.c
index d3c0fc9..f29414e 100644
--- a/drivers/clk/mediatek/clk-mt2701-vdec.c
+++ b/drivers/clk/mediatek/clk-mt2701-vdec.c
@@ -66,7 +66,7 @@ static int clk_mt2701_vdec_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
+ clk_data = clk_alloc_onecell_data(CLK_VDEC_NR);
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
index 8e7f16f..df861a5 100644
--- a/drivers/clk/mediatek/clk-mt2701.c
+++ b/drivers/clk/mediatek/clk-mt2701.c
@@ -688,7 +688,7 @@ static int mtk_topckgen_init(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
+ clk_data = clk_alloc_onecell_data(CLK_TOP_NR);
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
@@ -755,7 +755,7 @@ static void __init mtk_infrasys_init_early(struct device_node *node)
int r, i;
if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+ infra_clk_data = clk_alloc_onecell_data(CLK_INFRA_NR);
for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
@@ -781,7 +781,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+ infra_clk_data = clk_alloc_onecell_data(CLK_INFRA_NR);
} else {
for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
@@ -909,7 +909,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
+ clk_data = clk_alloc_onecell_data(CLK_PERI_NR);
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
clk_data);
@@ -981,7 +981,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
+ clk_data = clk_alloc_onecell_data(CLK_APMIXED_NR);
if (!clk_data)
return -ENOMEM;
diff --git a/drivers/clk/mediatek/clk-mt2712-bdp.c b/drivers/clk/mediatek/clk-mt2712-bdp.c
index 5fe4728..b8b46e5 100644
--- a/drivers/clk/mediatek/clk-mt2712-bdp.c
+++ b/drivers/clk/mediatek/clk-mt2712-bdp.c
@@ -72,7 +72,7 @@ static int clk_mt2712_bdp_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_BDP_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_BDP_NR_CLK);
mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712-img.c b/drivers/clk/mediatek/clk-mt2712-img.c
index 139ff55..e9fbf20 100644
--- a/drivers/clk/mediatek/clk-mt2712-img.c
+++ b/drivers/clk/mediatek/clk-mt2712-img.c
@@ -50,7 +50,7 @@ static int clk_mt2712_img_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_IMG_NR_CLK);
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712-jpgdec.c b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
index c7d4aad..86e7de4 100644
--- a/drivers/clk/mediatek/clk-mt2712-jpgdec.c
+++ b/drivers/clk/mediatek/clk-mt2712-jpgdec.c
@@ -46,7 +46,7 @@ static int clk_mt2712_jpgdec_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_JPGDEC_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_JPGDEC_NR_CLK);
mtk_clk_register_gates(node, jpgdec_clks, ARRAY_SIZE(jpgdec_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712-mfg.c b/drivers/clk/mediatek/clk-mt2712-mfg.c
index 570f72d..2d63776 100644
--- a/drivers/clk/mediatek/clk-mt2712-mfg.c
+++ b/drivers/clk/mediatek/clk-mt2712-mfg.c
@@ -45,7 +45,7 @@ static int clk_mt2712_mfg_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_MFG_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_MFG_NR_CLK);
mtk_clk_register_gates(node, mfg_clks, ARRAY_SIZE(mfg_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712-mm.c b/drivers/clk/mediatek/clk-mt2712-mm.c
index a8b4b6d..6685425 100644
--- a/drivers/clk/mediatek/clk-mt2712-mm.c
+++ b/drivers/clk/mediatek/clk-mt2712-mm.c
@@ -140,7 +140,7 @@ static int clk_mt2712_mm_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_MM_NR_CLK);
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712-vdec.c b/drivers/clk/mediatek/clk-mt2712-vdec.c
index 55c64ee..c2de3ea 100644
--- a/drivers/clk/mediatek/clk-mt2712-vdec.c
+++ b/drivers/clk/mediatek/clk-mt2712-vdec.c
@@ -64,7 +64,7 @@ static int clk_mt2712_vdec_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_VDEC_NR_CLK);
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712-venc.c b/drivers/clk/mediatek/clk-mt2712-venc.c
index ccbfe98..4b1a146 100644
--- a/drivers/clk/mediatek/clk-mt2712-venc.c
+++ b/drivers/clk/mediatek/clk-mt2712-venc.c
@@ -47,7 +47,7 @@ static int clk_mt2712_venc_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_VENC_NR_CLK);
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt2712.c b/drivers/clk/mediatek/clk-mt2712.c
index 498d137..b3e19d3 100644
--- a/drivers/clk/mediatek/clk-mt2712.c
+++ b/drivers/clk/mediatek/clk-mt2712.c
@@ -1226,7 +1226,7 @@ static int clk_mt2712_apmixed_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_APMIXED_NR_CLK);
mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
@@ -1246,7 +1246,7 @@ static void clk_mt2712_top_init_early(struct device_node *node)
int r, i;
if (!top_clk_data) {
- top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ top_clk_data = clk_alloc_onecell_data(CLK_TOP_NR_CLK);
for (i = 0; i < CLK_TOP_NR_CLK; i++)
top_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
@@ -1278,7 +1278,7 @@ static int clk_mt2712_top_probe(struct platform_device *pdev)
}
if (!top_clk_data) {
- top_clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ top_clk_data = clk_alloc_onecell_data(CLK_TOP_NR_CLK);
} else {
for (i = 0; i < CLK_TOP_NR_CLK; i++) {
if (top_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
@@ -1313,7 +1313,7 @@ static int clk_mt2712_infra_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
@@ -1335,7 +1335,7 @@ static int clk_mt2712_peri_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_PERI_NR_CLK);
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
clk_data);
@@ -1365,7 +1365,7 @@ static int clk_mt2712_mcu_probe(struct platform_device *pdev)
return PTR_ERR(base);
}
- clk_data = mtk_alloc_clk_data(CLK_MCU_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_MCU_NR_CLK);
mtk_clk_register_composites(mcu_muxes, ARRAY_SIZE(mcu_muxes), base,
&mt2712_clk_lock, clk_data);
diff --git a/drivers/clk/mediatek/clk-mt6797-img.c b/drivers/clk/mediatek/clk-mt6797-img.c
index 94cc480..6debc6d 100644
--- a/drivers/clk/mediatek/clk-mt6797-img.c
+++ b/drivers/clk/mediatek/clk-mt6797-img.c
@@ -51,7 +51,7 @@ static int clk_mt6797_img_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_IMG_NR);
+ clk_data = clk_alloc_onecell_data(CLK_IMG_NR);
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt6797-mm.c b/drivers/clk/mediatek/clk-mt6797-mm.c
index c57d3ee..c32c274 100644
--- a/drivers/clk/mediatek/clk-mt6797-mm.c
+++ b/drivers/clk/mediatek/clk-mt6797-mm.c
@@ -111,7 +111,7 @@ static int clk_mt6797_mm_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_MM_NR);
+ clk_data = clk_alloc_onecell_data(CLK_MM_NR);
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt6797-vdec.c b/drivers/clk/mediatek/clk-mt6797-vdec.c
index 7c402ca..66c0fe3 100644
--- a/drivers/clk/mediatek/clk-mt6797-vdec.c
+++ b/drivers/clk/mediatek/clk-mt6797-vdec.c
@@ -68,7 +68,7 @@ static int clk_mt6797_vdec_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);
+ clk_data = clk_alloc_onecell_data(CLK_VDEC_NR);
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt6797-venc.c b/drivers/clk/mediatek/clk-mt6797-venc.c
index e73d517..1669b43 100644
--- a/drivers/clk/mediatek/clk-mt6797-venc.c
+++ b/drivers/clk/mediatek/clk-mt6797-venc.c
@@ -53,7 +53,7 @@ static int clk_mt6797_venc_probe(struct platform_device *pdev)
int r;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_VENC_NR);
+ clk_data = clk_alloc_onecell_data(CLK_VENC_NR);
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt6797.c b/drivers/clk/mediatek/clk-mt6797.c
index 5702bc9..8441633 100644
--- a/drivers/clk/mediatek/clk-mt6797.c
+++ b/drivers/clk/mediatek/clk-mt6797.c
@@ -395,7 +395,7 @@ static int mtk_topckgen_init(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
+ clk_data = clk_alloc_onecell_data(CLK_TOP_NR);
mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
clk_data);
@@ -553,7 +553,7 @@ static void mtk_infrasys_init_early(struct device_node *node)
int r, i;
if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+ infra_clk_data = clk_alloc_onecell_data(CLK_INFRA_NR);
for (i = 0; i < CLK_INFRA_NR; i++)
infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
@@ -577,7 +577,7 @@ static int mtk_infrasys_init(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
if (!infra_clk_data) {
- infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
+ infra_clk_data = clk_alloc_onecell_data(CLK_INFRA_NR);
} else {
for (i = 0; i < CLK_INFRA_NR; i++) {
if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
@@ -656,7 +656,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR);
+ clk_data = clk_alloc_onecell_data(CLK_APMIXED_NR);
if (!clk_data)
return -ENOMEM;
diff --git a/drivers/clk/mediatek/clk-mt7622-aud.c b/drivers/clk/mediatek/clk-mt7622-aud.c
index fad7d9f..9b1170f 100644
--- a/drivers/clk/mediatek/clk-mt7622-aud.c
+++ b/drivers/clk/mediatek/clk-mt7622-aud.c
@@ -143,7 +143,7 @@ static int clk_mt7622_audiosys_init(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
int r;
- clk_data = mtk_alloc_clk_data(CLK_AUDIO_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_AUDIO_NR_CLK);
mtk_clk_register_gates(node, audio_clks, ARRAY_SIZE(audio_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt7622-eth.c b/drivers/clk/mediatek/clk-mt7622-eth.c
index 6328127..881845c 100644
--- a/drivers/clk/mediatek/clk-mt7622-eth.c
+++ b/drivers/clk/mediatek/clk-mt7622-eth.c
@@ -79,7 +79,7 @@ static int clk_mt7622_ethsys_init(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
int r;
- clk_data = mtk_alloc_clk_data(CLK_ETH_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_ETH_NR_CLK);
mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
clk_data);
@@ -101,7 +101,7 @@ static int clk_mt7622_sgmiisys_init(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
int r;
- clk_data = mtk_alloc_clk_data(CLK_SGMII_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_SGMII_NR_CLK);
mtk_clk_register_gates(node, sgmii_clks, ARRAY_SIZE(sgmii_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt7622-hif.c b/drivers/clk/mediatek/clk-mt7622-hif.c
index a6e8534..5b0738b 100644
--- a/drivers/clk/mediatek/clk-mt7622-hif.c
+++ b/drivers/clk/mediatek/clk-mt7622-hif.c
@@ -90,7 +90,7 @@ static int clk_mt7622_ssusbsys_init(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
int r;
- clk_data = mtk_alloc_clk_data(CLK_SSUSB_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_SSUSB_NR_CLK);
mtk_clk_register_gates(node, ssusb_clks, ARRAY_SIZE(ssusb_clks),
clk_data);
@@ -112,7 +112,7 @@ static int clk_mt7622_pciesys_init(struct platform_device *pdev)
struct device_node *node = pdev->dev.of_node;
int r;
- clk_data = mtk_alloc_clk_data(CLK_PCIE_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_PCIE_NR_CLK);
mtk_clk_register_gates(node, pcie_clks, ARRAY_SIZE(pcie_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 92f7e32..ba6290f 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -628,7 +628,7 @@ static int mtk_topckgen_init(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_TOP_NR_CLK);
mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
clk_data);
@@ -658,7 +658,7 @@ static int __init mtk_infrasys_init(struct platform_device *pdev)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
@@ -681,7 +681,7 @@ static int mtk_apmixedsys_init(struct platform_device *pdev)
struct clk_onecell_data *clk_data;
struct device_node *node = pdev->dev.of_node;
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return -ENOMEM;
@@ -709,7 +709,7 @@ static int mtk_pericfg_init(struct platform_device *pdev)
if (IS_ERR(base))
return PTR_ERR(base);
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_PERI_NR_CLK);
mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mt8135.c b/drivers/clk/mediatek/clk-mt8135.c
index 07c21e4..9ce6e1d 100644
--- a/drivers/clk/mediatek/clk-mt8135.c
+++ b/drivers/clk/mediatek/clk-mt8135.c
@@ -533,7 +533,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
return;
}
- clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_TOP_NR_CLK);
mtk_clk_register_factors(root_clk_alias, ARRAY_SIZE(root_clk_alias), clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
@@ -554,7 +554,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
@@ -582,7 +582,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
return;
}
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_PERI_NR_CLK);
mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
clk_data);
@@ -635,7 +635,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
{
struct clk_onecell_data *clk_data;
- clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_APMIXED_NR_CLK);
if (!clk_data)
return;
diff --git a/drivers/clk/mediatek/clk-mt8173.c b/drivers/clk/mediatek/clk-mt8173.c
index 96c292c..1d1d09c 100644
--- a/drivers/clk/mediatek/clk-mt8173.c
+++ b/drivers/clk/mediatek/clk-mt8173.c
@@ -941,7 +941,7 @@ static void __init mtk_topckgen_init(struct device_node *node)
return;
}
- mt8173_top_clk_data = clk_data = mtk_alloc_clk_data(CLK_TOP_NR_CLK);
+ mt8173_top_clk_data = clk_data = clk_alloc_onecell_data(CLK_TOP_NR_CLK);
mtk_clk_register_fixed_clks(fixed_clks, ARRAY_SIZE(fixed_clks), clk_data);
mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), clk_data);
@@ -962,7 +962,7 @@ static void __init mtk_infrasys_init(struct device_node *node)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_INFRA_NR_CLK);
mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
clk_data);
@@ -992,7 +992,7 @@ static void __init mtk_pericfg_init(struct device_node *node)
return;
}
- clk_data = mtk_alloc_clk_data(CLK_PERI_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_PERI_NR_CLK);
mtk_clk_register_gates(node, peri_gates, ARRAY_SIZE(peri_gates),
clk_data);
@@ -1096,7 +1096,7 @@ static void __init mtk_apmixedsys_init(struct device_node *node)
return;
}
- mt8173_pll_clk_data = clk_data = mtk_alloc_clk_data(CLK_APMIXED_NR_CLK);
+ mt8173_pll_clk_data = clk_data = clk_alloc_onecell_data(CLK_APMIXED_NR_CLK);
if (!clk_data) {
iounmap(base);
return;
@@ -1139,7 +1139,7 @@ static void __init mtk_imgsys_init(struct device_node *node)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_IMG_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_IMG_NR_CLK);
mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),
clk_data);
@@ -1157,7 +1157,7 @@ static void __init mtk_mmsys_init(struct device_node *node)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_MM_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_MM_NR_CLK);
mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),
clk_data);
@@ -1174,7 +1174,7 @@ static void __init mtk_vdecsys_init(struct device_node *node)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_VDEC_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_VDEC_NR_CLK);
mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),
clk_data);
@@ -1191,7 +1191,7 @@ static void __init mtk_vencsys_init(struct device_node *node)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_VENC_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_VENC_NR_CLK);
mtk_clk_register_gates(node, venc_clks, ARRAY_SIZE(venc_clks),
clk_data);
@@ -1208,7 +1208,7 @@ static void __init mtk_vencltsys_init(struct device_node *node)
struct clk_onecell_data *clk_data;
int r;
- clk_data = mtk_alloc_clk_data(CLK_VENCLT_NR_CLK);
+ clk_data = clk_alloc_onecell_data(CLK_VENCLT_NR_CLK);
mtk_clk_register_gates(node, venclt_clks, ARRAY_SIZE(venclt_clks),
clk_data);
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 9c0ae42..64cf1ef 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -24,31 +24,6 @@
#include "clk-mtk.h"
#include "clk-gate.h"
-struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num)
-{
- int i;
- struct clk_onecell_data *clk_data;
-
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
- if (!clk_data)
- return NULL;
-
- clk_data->clks = kcalloc(clk_num, sizeof(*clk_data->clks), GFP_KERNEL);
- if (!clk_data->clks)
- goto err_out;
-
- clk_data->clk_num = clk_num;
-
- for (i = 0; i < clk_num; i++)
- clk_data->clks[i] = ERR_PTR(-ENOENT);
-
- return clk_data;
-err_out:
- kfree(clk_data);
-
- return NULL;
-}
-
void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
int num, struct clk_onecell_data *clk_data)
{
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index bf8006d..651a9e9 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -190,8 +190,6 @@ void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
int num, void __iomem *base, spinlock_t *lock,
struct clk_onecell_data *clk_data);
-struct clk_onecell_data *mtk_alloc_clk_data(unsigned int clk_num);
-
#define HAVE_RST_BAR BIT(0)
#define PLL_AO BIT(1)
--
2.7.4
^ permalink raw reply related
* [PATCH 3/7] clk: qoriq: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
Use helper function clk_alloc_onecell_data() to allocate struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/clk-qoriq.c | 13 ++++---------
1 file changed, 4 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c
index 3a1812f..5278cc7 100644
--- a/drivers/clk/clk-qoriq.c
+++ b/drivers/clk/clk-qoriq.c
@@ -1175,13 +1175,11 @@ static void __init legacy_pll_init(struct device_node *np, int idx)
count = of_property_count_strings(np, "clock-output-names");
BUILD_BUG_ON(ARRAY_SIZE(pll->div) < 4);
- subclks = kcalloc(4, sizeof(struct clk *), GFP_KERNEL);
- if (!subclks)
+ onecell_data = clk_alloc_onecell_data(4);
+ if (!onecell_data)
return;
- onecell_data = kmalloc(sizeof(*onecell_data), GFP_KERNEL);
- if (!onecell_data)
- goto err_clks;
+ subclks = onecell_data->clks;
if (count <= 3) {
subclks[0] = pll->div[0].clk;
@@ -1194,7 +1192,6 @@ static void __init legacy_pll_init(struct device_node *np, int idx)
subclks[3] = pll->div[3].clk;
}
- onecell_data->clks = subclks;
onecell_data->clk_num = count;
rc = of_clk_add_provider(np, of_clk_src_onecell_get, onecell_data);
@@ -1206,9 +1203,7 @@ static void __init legacy_pll_init(struct device_node *np, int idx)
return;
err_cell:
- kfree(onecell_data);
-err_clks:
- kfree(subclks);
+ clk_free_onecell_data(onecell_data);
}
/* Legacy node */
--
2.7.4
^ permalink raw reply related
* [PATCH 4/7] clk: hisilicon: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
Use helper function clk_alloc_onecell_data() to allocate struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/hisilicon/clk-hi3620.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/clk/hisilicon/clk-hi3620.c b/drivers/clk/hisilicon/clk-hi3620.c
index 77072c7..15f8d50 100644
--- a/drivers/clk/hisilicon/clk-hi3620.c
+++ b/drivers/clk/hisilicon/clk-hi3620.c
@@ -476,21 +476,16 @@ static void __init hi3620_mmc_clk_init(struct device_node *node)
return;
}
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(num);
if (WARN_ON(!clk_data))
return;
- clk_data->clks = kcalloc(num, sizeof(*clk_data->clks), GFP_KERNEL);
- if (!clk_data->clks)
- return;
-
for (i = 0; i < num; i++) {
struct hisi_mmc_clock *mmc_clk = &hi3620_mmc_clks[i];
clk_data->clks[mmc_clk->id] =
hisi_register_clk_mmc(mmc_clk, base, node);
}
- clk_data->clk_num = num;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
}
--
2.7.4
^ permalink raw reply related
* [PATCH 5/7] clk: rockchip: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
Use helper function clk_alloc_onecell_data() to allocate struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/rockchip/clk-rockchip.c | 11 +----------
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/clk/rockchip/clk-rockchip.c b/drivers/clk/rockchip/clk-rockchip.c
index 2c9bb81..499af3a 100644
--- a/drivers/clk/rockchip/clk-rockchip.c
+++ b/drivers/clk/rockchip/clk-rockchip.c
@@ -52,19 +52,12 @@ static void __init rk2928_gate_clk_init(struct device_node *node)
if (!reg)
return;
- clk_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(qty);
if (!clk_data) {
iounmap(reg);
return;
}
- clk_data->clks = kzalloc(qty * sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks) {
- kfree(clk_data);
- iounmap(reg);
- return;
- }
-
flags = CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE;
for (i = 0; i < qty; i++) {
@@ -91,8 +84,6 @@ static void __init rk2928_gate_clk_init(struct device_node *node)
WARN_ON(IS_ERR(clk_data->clks[i]));
}
- clk_data->clk_num = qty;
-
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
}
CLK_OF_DECLARE(rk2928_gate, "rockchip,rk2928-gate-clk", rk2928_gate_clk_init);
--
2.7.4
^ permalink raw reply related
* [PATCH 6/7] clk: st: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
Use helper function clk_alloc_onecell_data() to allocate struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/st/clk-flexgen.c | 17 +++++------------
drivers/clk/st/clkgen-fsyn.c | 11 +----------
drivers/clk/st/clkgen-pll.c | 12 ++----------
3 files changed, 8 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 918ba31..29ff00d 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -310,7 +310,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
{
struct device_node *pnode;
void __iomem *reg;
- struct clk_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data = NULL;
const char **parents;
int num_parents, i;
spinlock_t *rlock = NULL;
@@ -341,21 +341,15 @@ static void __init st_of_flexgen_setup(struct device_node *np)
clk_mode = data->mode;
}
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
- if (!clk_data)
- goto err;
-
ret = of_property_count_strings(np, "clock-output-names");
if (ret <= 0) {
pr_err("%s: Failed to get number of output clocks (%d)",
- __func__, clk_data->clk_num);
+ __func__, ret);
goto err;
}
- clk_data->clk_num = ret;
- clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
- GFP_KERNEL);
- if (!clk_data->clks)
+ clk_data = clk_alloc_onecell_data(ret);
+ if (!clk_data)
goto err;
rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
@@ -397,8 +391,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
err:
iounmap(reg);
- if (clk_data)
- kfree(clk_data->clks);
+ clk_free_onecell_data(clk_data);
kfree(clk_data);
kfree(parents);
kfree(rlock);
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 14819d9..48e6bff 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -869,19 +869,10 @@ static void __init st_of_create_quadfs_fsynths(
struct clk_onecell_data *clk_data;
int fschan;
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(QUADFS_MAX_CHAN);
if (!clk_data)
return;
- clk_data->clk_num = QUADFS_MAX_CHAN;
- clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *),
- GFP_KERNEL);
-
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) {
struct clk *clk;
const char *clk_name;
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 25bda48..07795ee 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -733,17 +733,10 @@ static void __init clkgen_c32_pll_setup(struct device_node *np,
num_odfs = data->num_odfs;
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(num_odfs);
if (!clk_data)
return;
- clk_data->clk_num = num_odfs;
- clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
- GFP_KERNEL);
-
- if (!clk_data->clks)
- goto err;
-
for (odf = 0; odf < num_odfs; odf++) {
struct clk *clk;
const char *clk_name;
@@ -768,8 +761,7 @@ static void __init clkgen_c32_pll_setup(struct device_node *np,
err:
kfree(pll_name);
- kfree(clk_data->clks);
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
}
static void __init clkgen_c32_pll0_setup(struct device_node *np)
{
--
2.7.4
^ permalink raw reply related
* [PATCH 7/7] clk: sunxi: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
Use helper function clk_alloc_onecell_data() to allocate struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/sunxi/clk-a10-pll2.c | 14 ++++----------
drivers/clk/sunxi/clk-mod0.c | 13 +++----------
drivers/clk/sunxi/clk-simple-gates.c | 13 +++----------
drivers/clk/sunxi/clk-sun8i-bus-gates.c | 13 +++----------
drivers/clk/sunxi/clk-sunxi.c | 14 ++++----------
drivers/clk/sunxi/clk-usb.c | 8 +-------
6 files changed, 18 insertions(+), 57 deletions(-)
diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c
index d8eab90..54b8386 100644
--- a/drivers/clk/sunxi/clk-a10-pll2.c
+++ b/drivers/clk/sunxi/clk-a10-pll2.c
@@ -58,13 +58,11 @@ static void __init sun4i_pll2_setup(struct device_node *node,
if (IS_ERR(reg))
return;
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(SUN4I_PLL2_OUTPUTS);
if (!clk_data)
goto err_unmap;
- clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
- if (!clks)
- goto err_free_data;
+ clks = clk_data->clks;
parent = of_clk_get_parent_name(node, 0);
prediv_clk = clk_register_divider(NULL, "pll2-prediv",
@@ -75,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
&sun4i_a10_pll2_lock);
if (IS_ERR(prediv_clk)) {
pr_err("Couldn't register the prediv clock\n");
- goto err_free_array;
+ goto err_free_data;
}
/* Setup the gate part of the PLL2 */
@@ -166,8 +164,6 @@ static void __init sun4i_pll2_setup(struct device_node *node,
2, 1);
WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
- clk_data->clks = clks;
- clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return;
@@ -178,10 +174,8 @@ static void __init sun4i_pll2_setup(struct device_node *node,
kfree(gate);
err_unregister_prediv:
clk_unregister_divider(prediv_clk);
-err_free_array:
- kfree(clks);
err_free_data:
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
err_unmap:
iounmap(reg);
}
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 4417ae1..d14c3f1 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -315,18 +315,13 @@ static void __init sunxi_mmc_setup(struct device_node *node,
return;
}
- clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(3);
if (!clk_data)
return;
- clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
- if (!clk_data->clks)
- goto err_free_data;
-
- clk_data->clk_num = 3;
clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
if (!clk_data->clks[0])
- goto err_free_clks;
+ goto err_free_data;
parent = __clk_get_name(clk_data->clks[0]);
@@ -366,10 +361,8 @@ static void __init sunxi_mmc_setup(struct device_node *node,
return;
-err_free_clks:
- kfree(clk_data->clks);
err_free_data:
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
}
static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index a085c3b..4685358 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -44,16 +44,12 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
clk_parent = of_clk_get_parent_name(node, 0);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- goto err_unmap;
-
number = of_property_count_u32_elems(node, "clock-indices");
of_property_read_u32_index(node, "clock-indices", number - 1, &number);
- clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks)
- goto err_free_data;
+ clk_data = clk_alloc_onecell_data(number + 1);
+ if (!clk_data)
+ goto err_unmap;
of_property_for_each_u32(node, "clock-indices", prop, p, index) {
of_property_read_string_index(node, "clock-output-names",
@@ -80,13 +76,10 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
}
- clk_data->clk_num = number + 1;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return;
-err_free_data:
- kfree(clk_data);
err_unmap:
iounmap(reg);
of_address_to_resource(node, 0, &res);
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index bee305b..f3a3e05 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -54,16 +54,12 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
parents[i] = of_clk_get_parent_name(node, idx);
}
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- goto err_unmap;
-
number = of_property_count_u32_elems(node, "clock-indices");
of_property_read_u32_index(node, "clock-indices", number - 1, &number);
- clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks)
- goto err_free_data;
+ clk_data = clk_alloc_onecell_data(number + 1);
+ if (!clk_data)
+ goto err_unmap;
i = 0;
of_property_for_each_u32(node, "clock-indices", prop, p, index) {
@@ -98,13 +94,10 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
}
}
- clk_data->clk_num = number + 1;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return;
-err_free_data:
- kfree(clk_data);
err_unmap:
iounmap(reg);
of_address_to_resource(node, 0, &res);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index aa4add5..5a09d35 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1012,15 +1012,11 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
return NULL;
}
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(ndivs);
if (!clk_data)
goto out_unmap;
- clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
- if (!clks)
- goto free_clkdata;
-
- clk_data->clks = clks;
+ clks = clk_data->clks;
/* It's not a good idea to have automatic reparenting changing
* our RAM clock! */
@@ -1045,7 +1041,7 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
if (data->div[i].gate) {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
- goto free_clks;
+ goto free_clkdata;
gate->reg = reg;
gate->bit_idx = data->div[i].gate;
@@ -1106,10 +1102,8 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
return clks;
free_gate:
kfree(gate);
-free_clks:
- kfree(clks);
free_clkdata:
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
out_unmap:
iounmap(reg);
return NULL;
diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
index fe0c3d16..4358d33 100644
--- a/drivers/clk/sunxi/clk-usb.c
+++ b/drivers/clk/sunxi/clk-usb.c
@@ -118,16 +118,10 @@ static void __init sunxi_usb_clk_setup(struct device_node *node,
qty = find_last_bit((unsigned long *)&data->clk_mask,
SUNXI_USB_MAX_SIZE);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(qty + 1);
if (!clk_data)
return;
- clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
for_each_set_bit(i, (unsigned long *)&data->clk_mask,
SUNXI_USB_MAX_SIZE) {
of_property_read_string_index(node, "clock-output-names",
--
2.7.4
^ permalink raw reply related
* [PATCH v3] arm64: v8.4: Support for new floating point multiplication instructions
From: gengdongjiu @ 2018-01-05 1:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <73019dea-3e2c-8d03-fe1a-6c54527fa401@arm.com>
Hi will/catalin
On 2017/12/13 18:09, Suzuki K Poulose wrote:
> On 13/12/17 10:13, Dongjiu Geng wrote:
>> ARM v8.4 extensions add new neon instructions for performing a
>> multiplication of each FP16 element of one vector with the corresponding
>> FP16 element of a second vector, and to add or subtract this without an
>> intermediate rounding to the corresponding FP32 element in a third vector.
>>
>> This patch detects this feature and let the userspace know about it via a
>> HWCAP bit and MRS emulation.
>>
>> Cc: Dave Martin <Dave.Martin@arm.com>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Reviewed-by: Dave Martin <Dave.Martin@arm.com>
>
> Looks good to me.
>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
sorry to disturb you. Reminder, hope this patch can be applied to Linux 4.15-rc7.
Thanks a lot in advance.
>
>
> .
>
^ permalink raw reply
* [PATCH -next] clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()
From: Wei Yongjun @ 2018-01-05 1:50 UTC (permalink / raw)
To: linux-arm-kernel
platform_get_resource() may return NULL, add proper
check to avoid potential NULL dereferencing.
This is detected by Coccinelle semantic patch.
@@
expression pdev, res, n, t, e, e1, e2;
@@
res = platform_get_resource(pdev, t, n);
+ if (!res)
+ return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/clk/meson/axg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index d883bef..1294f3a 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -879,6 +879,8 @@ static int axg_clkc_probe(struct platform_device *pdev)
/* Generic clocks and PLLs */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
clk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!clk_base) {
dev_err(&pdev->dev, "Unable to map clk base\n");
^ permalink raw reply related
* [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Icenowy Zheng @ 2018-01-05 2:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104185210.afsvsofq7q35psa6@flea.lan>
? 2018?1?5? GMT+08:00 ??2:52:10, Maxime Ripard <maxime.ripard@free-electrons.com> ??:
>On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej ?krabec wrote:
>> Hi Rob,
>>
>> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > > This commit adds all necessary compatibles and descriptions
>needed to
>> > > implement A83T HDMI pipeline.
>> > >
>> > > Mixer is already properly described, so only compatible is added.
>> > >
>> > > However, A83T TCON1, which is connected to HDMI, doesn't have
>channel 0,
>> > > contrary to all TCONs currently described. Because of that, TCON
>> > > documentation is extended.
>> > >
>> > > A83T features Synopsys DW HDMI controller with a custom PHY which
>looks
>> > > like Synopsys Gen2 PHY with few additions. Since there is no
>> > > documentation, needed properties were found out through
>experimentation
>> > > and reading BSP code.
>> > >
>> > > At the end, example is added for newer SoCs, which features DE2
>and DW
>> > > HDMI.
>> > >
>> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> > > ---
>> > >
>> > > .../bindings/display/sunxi/sun4i-drm.txt | 188
>> > > ++++++++++++++++++++- 1 file changed, 181 insertions(+), 7
>deletions(-)
>> > >
>> > > diff --git
>a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>index
>> > > 9f073af4c711..3eca258096a5 100644
>> > > ---
>a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > > +++
>b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > >
>> > > @@ -64,6 +64,40 @@ Required properties:
>> > > first port should be the input endpoint. The second should
>be the
>> > > output, usually to an HDMI connector.
>> > >
>> > > +DWC HDMI TX Encoder
>> > > +-----------------------------
>> > > +
>> > > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX
>controller IP
>> > > +with Allwinner's own PHY IP. It supports audio and video outputs
>and CEC.
>> > > +
>> > > +These DT bindings follow the Synopsys DWC HDMI TX bindings
>defined in
>> > > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
>with the
>> > > +following device-specific properties.
>> > > +
>> > > +Required properties:
>> > > +
>> > > + - compatible: value must be one of:
>> > > + * "allwinner,sun8i-a83t-dw-hdmi"
>> > > + - reg: two pairs of base address and size of memory-mapped
>region,
>> > > first
>> > > + for controller and second for PHY
>> > > + registers.
>> >
>> > Seems like the phy should be a separate node and use the phy
>binding.
>> > You can use the phy binding even if you don't use the kernel phy
>> > framework...
>>
>> Unfortunately, it's not so straighforward. Phy is actually accessed
>through
>> I2C implemented in HDMI controller. Second memory region in this case
>has
>> small influence on phy. However, it has big influence on controller.
>For
>> example, magic number has to be written in one register in second
>memory
>> region in order to unlock read access to any register from first
>memory region
>> (controller). However, they shouldn't be merged to one region,
>because first
>> memory region requires byte access while second memory region can be
>accessed
>> per byte or word.
>>
>> To complicate things more, later I want to add support for another
>SoC which
>> has same glue layer (unlocking read access, etc.) and uses memory
>mapped phy
>> registers in second memory region.
>>
>> I think current binding is the least complicated way to represent
>this.
>
>I agree with Rob here. I did a similar thing for the DSI patches I've
>sent a few monthes ago and it turned out to not be that difficult, so
>I'm sure you can come up with something :)
In A83T/H3/A64/H5/R40 this part is not purely a PHY.
It controls the access of main controller's register (e.g. read/write
lock and register obfuscation). So it should be called a "glue"
with PHY part (and on A83T seems a pure glue) but not a simple
PHY.
>
>Maxime
>
>--
>Maxime Ripard, Free Electrons
>Embedded Linux and Kernel engineering
>http://free-electrons.com
>
>_______________________________________________
>linux-arm-kernel mailing list
>linux-arm-kernel at lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Icenowy Zheng @ 2018-01-05 2:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1645801.yZU0HLsLbk@jernej-laptop>
? 2018?1?4? GMT+08:00 ??5:32:26, "Jernej ?krabec" <jernej.skrabec@siol.net> ??:
>Hi Rob,
>
>Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > This commit adds all necessary compatibles and descriptions needed
>to
>> > implement A83T HDMI pipeline.
>> >
>> > Mixer is already properly described, so only compatible is added.
>> >
>> > However, A83T TCON1, which is connected to HDMI, doesn't have
>channel 0,
>> > contrary to all TCONs currently described. Because of that, TCON
>> > documentation is extended.
>> >
>> > A83T features Synopsys DW HDMI controller with a custom PHY which
>looks
>> > like Synopsys Gen2 PHY with few additions. Since there is no
>> > documentation, needed properties were found out through
>experimentation
>> > and reading BSP code.
>> >
>> > At the end, example is added for newer SoCs, which features DE2 and
>DW
>> > HDMI.
>> >
>> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> > ---
>> >
>> > .../bindings/display/sunxi/sun4i-drm.txt | 188
>> > ++++++++++++++++++++- 1 file changed, 181 insertions(+), 7
>deletions(-)
>> >
>> > diff --git
>a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>index
>> > 9f073af4c711..3eca258096a5 100644
>> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> >
>> > @@ -64,6 +64,40 @@ Required properties:
>> > first port should be the input endpoint. The second should be
>the
>> > output, usually to an HDMI connector.
>> >
>> > +DWC HDMI TX Encoder
>> > +-----------------------------
>> > +
>> > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX
>controller IP
>> > +with Allwinner's own PHY IP. It supports audio and video outputs
>and CEC.
>> > +
>> > +These DT bindings follow the Synopsys DWC HDMI TX bindings defined
>in
>> > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
>the
>> > +following device-specific properties.
>> > +
>> > +Required properties:
>> > +
>> > + - compatible: value must be one of:
>> > + * "allwinner,sun8i-a83t-dw-hdmi"
>> > + - reg: two pairs of base address and size of memory-mapped
>region,
>> > first
>> > + for controller and second for PHY
>> > + registers.
>>
>> Seems like the phy should be a separate node and use the phy binding.
>> You can use the phy binding even if you don't use the kernel phy
>> framework...
>
>Unfortunately, it's not so straighforward. Phy is actually accessed
>through
>I2C implemented in HDMI controller. Second memory region in this case
>has
>small influence on phy. However, it has big influence on controller.
To be honest you used inaccurate word. Use "glue" directly
here may be more accurate.
>For
>example, magic number has to be written in one register in second
>memory
>region in order to unlock read access to any register from first memory
>region
>(controller). However, they shouldn't be merged to one region, because
>first
>memory region requires byte access while second memory region can be
>accessed
>per byte or word.
>
>To complicate things more, later I want to add support for another SoC
>which
>has same glue layer (unlocking read access, etc.) and uses memory
>mapped phy
>registers in second memory region.
>
>I think current binding is the least complicated way to represent this.
>
>>
>> > + - reg-io-width: See dw_hdmi.txt. Shall be 1.
>> > + - interrupts: HDMI interrupt number
>> > + - clocks: phandles to the clocks feeding the HDMI encoder
>> > + * iahb: the HDMI bus clock
>> > + * isfr: the HDMI register clock
>> > + * tmds: the HDMI tmds clock
>> > + - clock-names: the clock names mentioned above
>> > + - resets: phandles to the reset controllers driving the encoder
>> > + * ctrl: the reset line for the controller
>> > + * phy: the reset line for the PHY
>> > + - reset-names: the reset names mentioned above
>> > +
>> > + - ports: A ports node with endpoint definitions as defined in
>> > + Documentation/devicetree/bindings/media/video-interfaces.txt.
>The
>> > + first port should be the input endpoint. The second should be
>the
>> > + output, usually to an HDMI connector.
>> > +
>> >
>> > TV Encoder
>> > ----------
>> >
>> > @@ -94,18 +128,17 @@ Required properties:
>> > * allwinner,sun7i-a20-tcon
>> > * allwinner,sun8i-a33-tcon
>> > * allwinner,sun8i-a83t-tcon-lcd
>> >
>> > + * allwinner,sun8i-a83t-tcon-tv
>> >
>> > * allwinner,sun8i-v3s-tcon
>> >
>> > - reg: base address and size of memory-mapped region
>> > - interrupts: interrupt associated to this IP
>> >
>> > - - clocks: phandles to the clocks feeding the TCON. Three are
>needed:
>> >
>> > + - clocks: phandles to the clocks feeding the TCON. One is needed:
>> > - 'ahb': the interface clocks
>> >
>> > - - 'tcon-ch0': The clock driving the TCON channel 0
>> >
>> > - resets: phandles to the reset controllers driving the encoder
>> >
>> > - "lcd": the reset line for the TCON channel 0
>> >
>> > - clock-names: the clock names mentioned above
>> > - reset-names: the reset names mentioned above
>> >
>> > - - clock-output-names: Name of the pixel clock created
>> >
>> > - ports: A ports node with endpoint definitions as defined in
>> >
>> > Documentation/devicetree/bindings/media/video-interfaces.txt.
>The
>> >
>> > @@ -119,11 +152,31 @@ Required properties:
>> > channel the endpoint is associated to. If that property is not
>> > present, the endpoint number will be used as the channel number.
>> >
>> > -On SoCs other than the A33 and V3s, there is one more clock
>required:
>> > +Following compatibles:
>> > + * allwinner,sun4i-a10-tcon
>> > + * allwinner,sun5i-a13-tcon
>> > + * allwinner,sun6i-a31-tcon
>> > + * allwinner,sun6i-a31s-tcon
>> > + * allwinner,sun7i-a20-tcon
>> > + * allwinner,sun8i-a33-tcon
>> > + * allwinner,sun8i-a83t-tcon-lcd
>> > + * allwinner,sun8i-v3s-tcon
>> > +have additional required properties:
>> > + - 'tcon-ch0': The clock driving the TCON channel 0
>>
>> tcon-ch0 is a clock name, not a property.
>
>right.
>
>Best regards,
>Jernej
>
>
>
>_______________________________________________
>linux-arm-kernel mailing list
>linux-arm-kernel at lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework
From: David Lechner @ 2018-01-05 2:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f09641b7-a9e9-24d1-ce13-1b627d077ce5@lechnology.com>
On 01/04/2018 11:50 AM, David Lechner wrote:
>
>
> On 1/4/18 6:39 AM, Sekhar Nori wrote:
>> On Monday 01 January 2018 05:09 AM, David Lechner wrote:
>>> This converts all of arch/arm/mach-davinci to the common clock framework.
>>> The clock drivers from clock.c and psc.c have been moved to drivers/clk,
>>> so these files are removed.
>>>
>>> There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV
>>> clocks now have "ref_clk" as a parent instead of the PLL clock. These
>>> clocks are part of the PLL's MMIO block, but they bypass the PLL and
>>> therefore it makes more sense to have "ref_clk" as their parent since
>>> "ref_clk" is the input clock of the PLL.
>>>
>>> CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks
>>> takes care of disabling unused clocks.
>>>
>>> Known issue: This breaks CPU frequency scaling on da850.
>>
>> This functionality needs to be restored as part of this series since we
>> cannot commit anything with regressions.
>>
>
> Do you have a suggestion on how to accomplish this? I don't have a board for testing, so I don't have a way of knowing if my changes will work or not.
>
>>>
>>> Also, the order of #includes are cleaned up in files while we are touching
>>> this code.
>>>
>>> Signed-off-by: David Lechner <david@lechnology.com>
>>
>> This is a pretty huge patch again and I hope it can be broken down.
>> Ideally one per SoC converted and then the unused code removal.
>>
>
> Will do.
Well, I can do this, but I don't think it will compile or run. We can't
have the common clock framework and the legacy davinci clocks enabled at
the same time.
^ permalink raw reply
* [PATCH 05/12] arm64: dts: mt7622: add PMIC MT6380 related nodes
From: Sean Wang @ 2018-01-05 3:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOFm3uF0WHO6_Y6dKu3DnAd759tA2hNQs=0-P86s1A0e==27Ow@mail.gmail.com>
On Thu, 2018-01-04 at 11:27 +0100, Philippe Ombredanne wrote:
> Sean,
>
> On Thu, Jan 4, 2018 at 10:40 AM, <sean.wang@mediatek.com> wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> >
> > Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
> > regulator nodes in an alone file to allow similar boards using MT6380
> > able to resue the configuration.
> >
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > Cc: Mark Brown <broonie@kernel.org>
> > Cc: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
> > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
> > 3 files changed, 111 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> > new file mode 100644
> > index 0000000..7eb7dc2
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> > @@ -0,0 +1,91 @@
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Chenglin Xu <chenglin.xu@mediatek.com>
> > + * Sean Wang <sean.wang@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
>
> Would you mind using SPDX tags instead of this fine but long legalese?
> This is documented in Thomas patches [1].
> Also if you could spread the word in your team, this would earn you
> good karma points.
> Thank you!
>
> [1] https://lkml.org/lkml/2017/12/28/323
Hi, Philippe
thanks for your suggestion
Certainly, this can be replaced with
SPDX-License-Identifier: GPL-2.0
most drivers from MediaTek use the similar disclaimer, it should be fine
to use SPDX tags instead.
Sean
^ permalink raw reply
* [PATCH] arm: dts: mediatek: add audsys node for both MT2701 and MT7623
From: Ryder Lee @ 2018-01-05 3:57 UTC (permalink / raw)
To: linux-arm-kernel
Add audsys support for both MT2701/MT7623. Then modify afe node to adapt it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
This patch is dependent on https://www.spinics.net/lists/arm-kernel/msg626503.html
---
arch/arm/boot/dts/mt2701.dtsi | 188 ++++++++++++++++++++---------------------
arch/arm/boot/dts/mt7623.dtsi | 190 ++++++++++++++++++++----------------------
2 files changed, 182 insertions(+), 196 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 965ddfb..52b4622 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -426,104 +426,96 @@
status = "disabled";
};
- afe: audio-controller at 11220000 {
- compatible = "mediatek,mt2701-audio";
- reg = <0 0x11220000 0 0x2000>,
- <0 0x112a0000 0 0x20000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-
- clocks = <&infracfg CLK_INFRA_AUDIO>,
- <&topckgen CLK_TOP_AUD_MUX1_SEL>,
- <&topckgen CLK_TOP_AUD_MUX2_SEL>,
- <&topckgen CLK_TOP_AUD_MUX1_DIV>,
- <&topckgen CLK_TOP_AUD_MUX2_DIV>,
- <&topckgen CLK_TOP_AUD_48K_TIMING>,
- <&topckgen CLK_TOP_AUD_44K_TIMING>,
- <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
- <&topckgen CLK_TOP_APLL_SEL>,
- <&topckgen CLK_TOP_AUD1PLL_98M>,
- <&topckgen CLK_TOP_AUD2PLL_90M>,
- <&topckgen CLK_TOP_HADDS2PLL_98M>,
- <&topckgen CLK_TOP_HADDS2PLL_294M>,
- <&topckgen CLK_TOP_AUDPLL>,
- <&topckgen CLK_TOP_AUDPLL_D4>,
- <&topckgen CLK_TOP_AUDPLL_D8>,
- <&topckgen CLK_TOP_AUDPLL_D16>,
- <&topckgen CLK_TOP_AUDPLL_D24>,
- <&topckgen CLK_TOP_AUDINTBUS_SEL>,
- <&clk26m>,
- <&topckgen CLK_TOP_SYSPLL1_D4>,
- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
- <&topckgen CLK_TOP_ASM_M_SEL>,
- <&topckgen CLK_TOP_ASM_H_SEL>,
- <&topckgen CLK_TOP_UNIVPLL2_D4>,
- <&topckgen CLK_TOP_UNIVPLL2_D2>,
- <&topckgen CLK_TOP_SYSPLL_D5>;
-
- clock-names = "infra_sys_audio_clk",
- "top_audio_mux1_sel",
- "top_audio_mux2_sel",
- "top_audio_mux1_div",
- "top_audio_mux2_div",
- "top_audio_48k_timing",
- "top_audio_44k_timing",
- "top_audpll_mux_sel",
- "top_apll_sel",
- "top_aud1_pll_98M",
- "top_aud2_pll_90M",
- "top_hadds2_pll_98M",
- "top_hadds2_pll_294M",
- "top_audpll",
- "top_audpll_d4",
- "top_audpll_d8",
- "top_audpll_d16",
- "top_audpll_d24",
- "top_audintbus_sel",
- "clk_26m",
- "top_syspll1_d4",
- "top_aud_k1_src_sel",
- "top_aud_k2_src_sel",
- "top_aud_k3_src_sel",
- "top_aud_k4_src_sel",
- "top_aud_k5_src_sel",
- "top_aud_k6_src_sel",
- "top_aud_k1_src_div",
- "top_aud_k2_src_div",
- "top_aud_k3_src_div",
- "top_aud_k4_src_div",
- "top_aud_k5_src_div",
- "top_aud_k6_src_div",
- "top_aud_i2s1_mclk",
- "top_aud_i2s2_mclk",
- "top_aud_i2s3_mclk",
- "top_aud_i2s4_mclk",
- "top_aud_i2s5_mclk",
- "top_aud_i2s6_mclk",
- "top_asm_m_sel",
- "top_asm_h_sel",
- "top_univpll2_d4",
- "top_univpll2_d2",
- "top_syspll_d5";
+ audsys: audio-subsystem at 11220000 {
+ compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: audio-controller {
+ compatible = "mediatek,mt2701-audio";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "afe", "asys";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&audsys CLK_AUD_I2SO1>,
+ <&audsys CLK_AUD_I2SO2>,
+ <&audsys CLK_AUD_I2SO3>,
+ <&audsys CLK_AUD_I2SO4>,
+ <&audsys CLK_AUD_I2SIN1>,
+ <&audsys CLK_AUD_I2SIN2>,
+ <&audsys CLK_AUD_I2SIN3>,
+ <&audsys CLK_AUD_I2SIN4>,
+ <&audsys CLK_AUD_ASRCO1>,
+ <&audsys CLK_AUD_ASRCO2>,
+ <&audsys CLK_AUD_ASRCO3>,
+ <&audsys CLK_AUD_ASRCO4>,
+ <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_AFE_CONN>,
+ <&audsys CLK_AUD_A1SYS>,
+ <&audsys CLK_AUD_A2SYS>,
+ <&audsys CLK_AUD_AFE_MRGIF>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_a1sys_hp",
+ "top_audio_a2sys_hp",
+ "i2s0_src_sel",
+ "i2s1_src_sel",
+ "i2s2_src_sel",
+ "i2s3_src_sel",
+ "i2s0_src_div",
+ "i2s1_src_div",
+ "i2s2_src_div",
+ "i2s3_src_div",
+ "i2s0_mclk_en",
+ "i2s1_mclk_en",
+ "i2s2_mclk_en",
+ "i2s3_mclk_en",
+ "i2so0_hop_ck",
+ "i2so1_hop_ck",
+ "i2so2_hop_ck",
+ "i2so3_hop_ck",
+ "i2si0_hop_ck",
+ "i2si1_hop_ck",
+ "i2si2_hop_ck",
+ "i2si3_hop_ck",
+ "asrc0_out_ck",
+ "asrc1_out_ck",
+ "asrc2_out_ck",
+ "asrc3_out_ck",
+ "audio_afe_pd",
+ "audio_afe_conn_pd",
+ "audio_a1sys_pd",
+ "audio_a2sys_pd",
+ "audio_mrgif_pd";
+
+ assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+ assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>;
+ assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+ };
};
mmsys: syscon at 14000000 {
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 0640fb7..b0e39d0 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -538,105 +538,99 @@
status = "disabled";
};
- afe: audio-controller at 11220000 {
- compatible = "mediatek,mt7623-audio",
- "mediatek,mt2701-audio";
- reg = <0 0x11220000 0 0x2000>,
- <0 0x112a0000 0 0x20000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ audsys: audio-subsystem at 11220000 {
+ compatible = "mediatek,mt7623-audsys",
+ "mediatek,mt2701-audsys",
+ "syscon", "simple-mfd";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
- clocks = <&infracfg CLK_INFRA_AUDIO>,
- <&topckgen CLK_TOP_AUD_MUX1_SEL>,
- <&topckgen CLK_TOP_AUD_MUX2_SEL>,
- <&topckgen CLK_TOP_AUD_MUX1_DIV>,
- <&topckgen CLK_TOP_AUD_MUX2_DIV>,
- <&topckgen CLK_TOP_AUD_48K_TIMING>,
- <&topckgen CLK_TOP_AUD_44K_TIMING>,
- <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
- <&topckgen CLK_TOP_APLL_SEL>,
- <&topckgen CLK_TOP_AUD1PLL_98M>,
- <&topckgen CLK_TOP_AUD2PLL_90M>,
- <&topckgen CLK_TOP_HADDS2PLL_98M>,
- <&topckgen CLK_TOP_HADDS2PLL_294M>,
- <&topckgen CLK_TOP_AUDPLL>,
- <&topckgen CLK_TOP_AUDPLL_D4>,
- <&topckgen CLK_TOP_AUDPLL_D8>,
- <&topckgen CLK_TOP_AUDPLL_D16>,
- <&topckgen CLK_TOP_AUDPLL_D24>,
- <&topckgen CLK_TOP_AUDINTBUS_SEL>,
- <&clk26m>,
- <&topckgen CLK_TOP_SYSPLL1_D4>,
- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
- <&topckgen CLK_TOP_ASM_M_SEL>,
- <&topckgen CLK_TOP_ASM_H_SEL>,
- <&topckgen CLK_TOP_UNIVPLL2_D4>,
- <&topckgen CLK_TOP_UNIVPLL2_D2>,
- <&topckgen CLK_TOP_SYSPLL_D5>;
-
- clock-names = "infra_sys_audio_clk",
- "top_audio_mux1_sel",
- "top_audio_mux2_sel",
- "top_audio_mux1_div",
- "top_audio_mux2_div",
- "top_audio_48k_timing",
- "top_audio_44k_timing",
- "top_audpll_mux_sel",
- "top_apll_sel",
- "top_aud1_pll_98M",
- "top_aud2_pll_90M",
- "top_hadds2_pll_98M",
- "top_hadds2_pll_294M",
- "top_audpll",
- "top_audpll_d4",
- "top_audpll_d8",
- "top_audpll_d16",
- "top_audpll_d24",
- "top_audintbus_sel",
- "clk_26m",
- "top_syspll1_d4",
- "top_aud_k1_src_sel",
- "top_aud_k2_src_sel",
- "top_aud_k3_src_sel",
- "top_aud_k4_src_sel",
- "top_aud_k5_src_sel",
- "top_aud_k6_src_sel",
- "top_aud_k1_src_div",
- "top_aud_k2_src_div",
- "top_aud_k3_src_div",
- "top_aud_k4_src_div",
- "top_aud_k5_src_div",
- "top_aud_k6_src_div",
- "top_aud_i2s1_mclk",
- "top_aud_i2s2_mclk",
- "top_aud_i2s3_mclk",
- "top_aud_i2s4_mclk",
- "top_aud_i2s5_mclk",
- "top_aud_i2s6_mclk",
- "top_asm_m_sel",
- "top_asm_h_sel",
- "top_univpll2_d4",
- "top_univpll2_d2",
- "top_syspll_d5";
+ afe: audio-controller {
+ compatible = "mediatek,mt7623-audio",
+ "mediatek,mt2701-audio";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "afe", "asys";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&audsys CLK_AUD_I2SO1>,
+ <&audsys CLK_AUD_I2SO2>,
+ <&audsys CLK_AUD_I2SO3>,
+ <&audsys CLK_AUD_I2SO4>,
+ <&audsys CLK_AUD_I2SIN1>,
+ <&audsys CLK_AUD_I2SIN2>,
+ <&audsys CLK_AUD_I2SIN3>,
+ <&audsys CLK_AUD_I2SIN4>,
+ <&audsys CLK_AUD_ASRCO1>,
+ <&audsys CLK_AUD_ASRCO2>,
+ <&audsys CLK_AUD_ASRCO3>,
+ <&audsys CLK_AUD_ASRCO4>,
+ <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_AFE_CONN>,
+ <&audsys CLK_AUD_A1SYS>,
+ <&audsys CLK_AUD_A2SYS>,
+ <&audsys CLK_AUD_AFE_MRGIF>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_a1sys_hp",
+ "top_audio_a2sys_hp",
+ "i2s0_src_sel",
+ "i2s1_src_sel",
+ "i2s2_src_sel",
+ "i2s3_src_sel",
+ "i2s0_src_div",
+ "i2s1_src_div",
+ "i2s2_src_div",
+ "i2s3_src_div",
+ "i2s0_mclk_en",
+ "i2s1_mclk_en",
+ "i2s2_mclk_en",
+ "i2s3_mclk_en",
+ "i2so0_hop_ck",
+ "i2so1_hop_ck",
+ "i2so2_hop_ck",
+ "i2so3_hop_ck",
+ "i2si0_hop_ck",
+ "i2si1_hop_ck",
+ "i2si2_hop_ck",
+ "i2si3_hop_ck",
+ "asrc0_out_ck",
+ "asrc1_out_ck",
+ "asrc2_out_ck",
+ "asrc3_out_ck",
+ "audio_afe_pd",
+ "audio_afe_conn_pd",
+ "audio_a1sys_pd",
+ "audio_a2sys_pd",
+ "audio_mrgif_pd";
+
+ assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+ assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>;
+ assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+ };
};
mmc0: mmc at 11230000 {
--
1.9.1
^ permalink raw reply related
* [PATCH v4 2/3] mailbox: Add support for Hi3660 mailbox
From: Jassi Brar @ 2018-01-05 4:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513682145-19892-3-git-send-email-zhongkaihua@huawei.com>
On Tue, Dec 19, 2017 at 4:45 PM, Kaihua Zhong <zhongkaihua@huawei.com> wrote:
.....
> diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c
> new file mode 100644
> index 0000000..3ceca40
> --- /dev/null
> +++ b/drivers/mailbox/hi3660-mailbox.c
> @@ -0,0 +1,319 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2017 Hisilicon Limited.
> +// Copyright (c) 2017 Linaro Limited.
A blank here please.
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
.....
> +
> +static inline struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox)
>
inline in .c is out of fasion these days
> +{
> + return container_of(mbox, struct hi3660_mbox, controller);
> +}
> +
....
> +
> +static int hi3660_mbox_startup(struct mbox_chan *chan)
> +{
> + int ret;
> +
> + ret = hi3660_mbox_check_state(chan);
> + if (ret)
> + return ret;
> +
> + ret = hi3660_mbox_unlock(chan);
> + if (ret)
> + return ret;
> +
> + ret = hi3660_mbox_acquire_channel(chan);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
Do you not need to do "release channel" for shutdown() ?
.....
> +
> +static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg)
> +{
> + return hi3660_mbox_send(chan, msg);
>
Please directly have hi3660_mbox_send as .send_data
Cheers!
^ permalink raw reply
* [PATCH V7 12/12] arm64: dts: add clocks for SC9860
From: Chunyan Zhang @ 2018-01-05 5:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a2Qpbr6EB+qWMQqCLkbnVddL+MHx1sFNs-+97ZQ=QaHeg@mail.gmail.com>
On 5 January 2018 at 07:01, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thu, Jan 4, 2018 at 10:34 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Thu, Dec 7, 2017 at 1:57 PM, Chunyan Zhang
>> <chunyan.zhang@spreadtrum.com> wrote:
>>> Some clocks on SC9860 are in the same address area with syscon devices,
>>> those are what have a property of 'sprd,syscon' which would refer to
>>> syscon devices, others would have a reg property indicated their address
>>> ranges.
>>>
>>> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
>>> ---
>>> arch/arm64/boot/dts/sprd/sc9860.dtsi | 115 +++++++++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/sprd/whale2.dtsi | 18 +++++-
>>> 2 files changed, 131 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> index 7b7d8ce..bf03da4 100644
>>> --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> @@ -7,6 +7,7 @@
>>> */
>>>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/clock/sprd,sc9860-clk.h>
>>> #include "whale2.dtsi"
>>
>> This caused a build error since the sprd,sc9860-clk.h file does not
>> exist, I'll revert or undo the patch tomorrow.
>
> I've taken another look, and fixing it by removing the broken #include
> was easier than undoing the patches, so I did that now, see
> https://patchwork.kernel.org/patch/10145773/
Ok, thanks Arnd!
Chunyan
>
> Arnd
^ permalink raw reply
* [linux-sunxi] Re: [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Jernej Škrabec @ 2018-01-05 6:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4B652FB5-08B2-416B-ABA9-08E12112087D@aosc.io>
Hi,
Dne petek, 05. januar 2018 ob 03:49:09 CET je Icenowy Zheng napisal(a):
> ? 2018?1?5? GMT+08:00 ??2:52:10, Maxime Ripard <maxime.ripard@free-
electrons.com> ??:
> >On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej ?krabec wrote:
> >> Hi Rob,
> >>
> >> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
> >> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
> >> > > This commit adds all necessary compatibles and descriptions
> >
> >needed to
> >
> >> > > implement A83T HDMI pipeline.
> >> > >
> >> > > Mixer is already properly described, so only compatible is added.
> >> > >
> >> > > However, A83T TCON1, which is connected to HDMI, doesn't have
> >
> >channel 0,
> >
> >> > > contrary to all TCONs currently described. Because of that, TCON
> >> > > documentation is extended.
> >> > >
> >> > > A83T features Synopsys DW HDMI controller with a custom PHY which
> >
> >looks
> >
> >> > > like Synopsys Gen2 PHY with few additions. Since there is no
> >> > > documentation, needed properties were found out through
> >
> >experimentation
> >
> >> > > and reading BSP code.
> >> > >
> >> > > At the end, example is added for newer SoCs, which features DE2
> >
> >and DW
> >
> >> > > HDMI.
> >> > >
> >> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> >> > > ---
> >> > >
> >> > > .../bindings/display/sunxi/sun4i-drm.txt | 188
> >> > > ++++++++++++++++++++- 1 file changed, 181 insertions(+), 7
> >
> >deletions(-)
> >
> >> > > diff --git
> >
> >a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >> > > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >index
> >
> >> > > 9f073af4c711..3eca258096a5 100644
> >> > > ---
> >
> >a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >> > > +++
> >
> >b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >> > > @@ -64,6 +64,40 @@ Required properties:
> >> > > first port should be the input endpoint. The second should
> >
> >be the
> >
> >> > > output, usually to an HDMI connector.
> >> > >
> >> > > +DWC HDMI TX Encoder
> >> > > +-----------------------------
> >> > > +
> >> > > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX
> >
> >controller IP
> >
> >> > > +with Allwinner's own PHY IP. It supports audio and video outputs
> >
> >and CEC.
> >
> >> > > +
> >> > > +These DT bindings follow the Synopsys DWC HDMI TX bindings
> >
> >defined in
> >
> >> > > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
> >
> >with the
> >
> >> > > +following device-specific properties.
> >> > > +
> >> > > +Required properties:
> >> > > +
> >> > > + - compatible: value must be one of:
> >> > > + * "allwinner,sun8i-a83t-dw-hdmi"
> >> > > + - reg: two pairs of base address and size of memory-mapped
> >
> >region,
> >
> >> > > first
> >> > > + for controller and second for PHY
> >> > > + registers.
> >> >
> >> > Seems like the phy should be a separate node and use the phy
> >
> >binding.
> >
> >> > You can use the phy binding even if you don't use the kernel phy
> >> > framework...
> >>
> >> Unfortunately, it's not so straighforward. Phy is actually accessed
> >
> >through
> >
> >> I2C implemented in HDMI controller. Second memory region in this case
> >
> >has
> >
> >> small influence on phy. However, it has big influence on controller.
> >
> >For
> >
> >> example, magic number has to be written in one register in second
> >
> >memory
> >
> >> region in order to unlock read access to any register from first
> >
> >memory region
> >
> >> (controller). However, they shouldn't be merged to one region,
> >
> >because first
> >
> >> memory region requires byte access while second memory region can be
> >
> >accessed
> >
> >> per byte or word.
> >>
> >> To complicate things more, later I want to add support for another
> >
> >SoC which
> >
> >> has same glue layer (unlocking read access, etc.) and uses memory
> >
> >mapped phy
> >
> >> registers in second memory region.
> >>
> >> I think current binding is the least complicated way to represent
> >
> >this.
> >
> >I agree with Rob here. I did a similar thing for the DSI patches I've
> >sent a few monthes ago and it turned out to not be that difficult, so
> >I'm sure you can come up with something :)
>
> In A83T/H3/A64/H5/R40 this part is not purely a PHY.
> It controls the access of main controller's register (e.g. read/write
> lock and register obfuscation). So it should be called a "glue"
> with PHY part (and on A83T seems a pure glue) but not a simple
> PHY.
It's not so simple. Actually it has PHY settings also on A83T. For example,
value at 0x01EF0001 depends on polarity. Value at 0x01EF0002 sets PHY I2C
address. Bit 7 at 0x01EF0007 enables/disables external resistor. That is info
I discovered/received after I sent patches, so it's not cleary marked.
Proper memory map (starts at 0x01EE0000):
0x00000 - 0x10000 -> DW HDMI controller
0x10000 - 0x10010 -> (almost?) Common PHY settings
0x10010 - 0x10020 -> Allwinner proprietary glue layer
0x10020 - 0x10040 -> Allwinner proprietary PHY (not present on A83T)
In preliminary PHY doc AW released, there are additional regs at 0x01EF0FF8
and 0x01EF0FFC for controller ID and phy ID, but it was always 0 at A83T and
H3.
So splitting memory in so many regions just to satisfy clean division it
doesn't seem sane to me. Now that I checked how Maxime did it with MIPI DSI
driver, I'm good with dividing it into two parts.
Best regards,
Jernej
>
> >Maxime
> >
> >--
> >Maxime Ripard, Free Electrons
> >Embedded Linux and Kernel engineering
> >http://free-electrons.com
> >
> >_______________________________________________
> >linux-arm-kernel mailing list
> >linux-arm-kernel at lists.infradead.org
> >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
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^ permalink raw reply
* [GIT PULL 1/2] Broadcom devicetree changes for 4.16
From: Olof Johansson @ 2018-01-05 6:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222001227.30625-1-f.fainelli@gmail.com>
On Thu, Dec 21, 2017 at 04:12:26PM -0800, Florian Fainelli wrote:
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.16/devicetree
>
> for you to fetch changes up to ececb5639c33a6a0444bd8e1cda8bf2ef20c6a6b:
>
> Merge tag 'bcm2835-dt-next-2017-12-19' into devicetree/next (2017-12-20 17:32:58 -0800)
>
> ----------------------------------------------------------------
> This pull request contains Broadcom ARM-based SoCs Device Tree changes for
> 4.16, please pull the following:
>
> - Stefan updates the BCM283x DTS to make consistent use of the existing GPIO
> defines for the polarity specifier
>
> ----------------------------------------------------------------
> Florian Fainelli (1):
> Merge tag 'bcm2835-dt-next-2017-12-19' into devicetree/next
>
> Stefan Wahren (1):
> ARM: dts: bcm283x: Use GPIO polarity defines consistently
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 2/2] Broadcom drivers changes for 4.16
From: Olof Johansson @ 2018-01-05 6:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222001227.30625-2-f.fainelli@gmail.com>
On Thu, Dec 21, 2017 at 04:12:27PM -0800, Florian Fainelli wrote:
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.16/drivers
>
> for you to fetch changes up to f780429adfbc222a4d8a227a2a550ba627c7338b:
>
> soc: brcmstb: biuctrl: Move to early_initcall (2017-12-20 17:37:44 -0800)
>
> ----------------------------------------------------------------
> This pull request contains Broadcom ARM/ARM64 based SoCs drivers changes for
> 4.16, please pull the following:
>
> - Arnd provides an update to the Raspberry Pi firmware interface and uses time64_t to
> print the time to make it more future proof
>
> - Florian provides a set of updates to make the Broadcom STB Bus Interface Unit code
> work on newer ARM64-based chips, as well as perform the correct interface tuning
> for these chips to reach the expected performance
>
> ----------------------------------------------------------------
> Arnd Bergmann (1):
> firmware: raspberrypi: print time using time64_t
>
> Florian Fainelli (10):
> Merge tag 'bcm2835-drivers-next-2017-12-19' into drivers/next
> dt-bindings: arm: Add entry for Broadcom Brahma-B53
> dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation
> soc: brcmstb: Make CPU credit offset more parameterized
> soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs
> soc: brcmstb: biuctrl: Prepare for saving/restoring other registers
> soc: brcmstb: biuctrl: Wire-up new registers
> soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings
> soc: brcmstb: Split initialization
> soc: brcmstb: biuctrl: Move to early_initcall
Merged, thanks.
Btw, you're sort of bare on signatures for your pgp key. You should try
to get at least me or Arnd to sign it at some point, hopefully we'll
overlap at conferences sometime. I've probably already offered once,
but seems I didn't actually upload my signature when I did it.
-Olof
^ permalink raw reply
* [GIT PULL v2] arm64: dts: hisilicon dts updates for v4.16
From: Olof Johansson @ 2018-01-05 6:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5A45604E.4050801@hisilicon.com>
On Thu, Dec 28, 2017 at 09:21:18PM +0000, Wei Xu wrote:
> Hi Arnd, Hi Olof, Hi Kevin,
>
> Please help to pull the following changes.
> Thanks!
>
> Best Regards,
> Wei
>
> ---
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> git://github.com/hisilicon/linux-hisi.git tags/hisi-arm64-dt-for-4.16-v2
>
> for you to fetch changes up to 9a9760dede5c71e04b17b2ede594ee7148fd36e2:
>
> arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information (2017-12-22 09:11:42 +0000)
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] arm: actions: dt for v4.16 #1
From: Olof Johansson @ 2018-01-05 6:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222102107.5661-1-afaerber@suse.de>
On Fri, Dec 22, 2017 at 11:21:05AM +0100, Andreas F?rber wrote:
> Hi Olof and Arnd,
>
> Here's my dt pull for Actions Semi.
> This adds one new S500 based board, which I already updated to new SPDX style.
> A second pull will follow after I've converted the existing boards.
>
> Regards,
> Andreas
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions.git tags/actions-arm-dt-for-4.16
>
> for you to fetch changes up to 271a70da383cf69f32742d9e2d01a7b16d04d60c:
>
> arm: dts: owl-s500: Add Sparky (2017-12-22 10:53:52 +0100)
>
> ----------------------------------------------------------------
> Actions Semi arm based SoC DT for v4.16
>
> This adds a DT for the Allo.com Sparky SBC.
>
> ----------------------------------------------------------------
> Andreas F?rber (3):
> dt-bindings: Add vendor prefix for Allo.com
> dt-bindings: arm: actions: Add Sparky
> arm: dts: owl-s500: Add Sparky
Merged.
Tiny nit: For 32-bit, we use ARM: as prefix (and arm64: for 64-bit).
Yes, it's confusing. :)
-Olof
^ permalink raw reply
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