* [PATCH 6/7] clk: st: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
Use helper function clk_alloc_onecell_data() to allocate struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/st/clk-flexgen.c | 17 +++++------------
drivers/clk/st/clkgen-fsyn.c | 11 +----------
drivers/clk/st/clkgen-pll.c | 12 ++----------
3 files changed, 8 insertions(+), 32 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 918ba31..29ff00d 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -310,7 +310,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
{
struct device_node *pnode;
void __iomem *reg;
- struct clk_onecell_data *clk_data;
+ struct clk_onecell_data *clk_data = NULL;
const char **parents;
int num_parents, i;
spinlock_t *rlock = NULL;
@@ -341,21 +341,15 @@ static void __init st_of_flexgen_setup(struct device_node *np)
clk_mode = data->mode;
}
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
- if (!clk_data)
- goto err;
-
ret = of_property_count_strings(np, "clock-output-names");
if (ret <= 0) {
pr_err("%s: Failed to get number of output clocks (%d)",
- __func__, clk_data->clk_num);
+ __func__, ret);
goto err;
}
- clk_data->clk_num = ret;
- clk_data->clks = kcalloc(clk_data->clk_num, sizeof(struct clk *),
- GFP_KERNEL);
- if (!clk_data->clks)
+ clk_data = clk_alloc_onecell_data(ret);
+ if (!clk_data)
goto err;
rlock = kzalloc(sizeof(spinlock_t), GFP_KERNEL);
@@ -397,8 +391,7 @@ static void __init st_of_flexgen_setup(struct device_node *np)
err:
iounmap(reg);
- if (clk_data)
- kfree(clk_data->clks);
+ clk_free_onecell_data(clk_data);
kfree(clk_data);
kfree(parents);
kfree(rlock);
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index 14819d9..48e6bff 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -869,19 +869,10 @@ static void __init st_of_create_quadfs_fsynths(
struct clk_onecell_data *clk_data;
int fschan;
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(QUADFS_MAX_CHAN);
if (!clk_data)
return;
- clk_data->clk_num = QUADFS_MAX_CHAN;
- clk_data->clks = kzalloc(QUADFS_MAX_CHAN * sizeof(struct clk *),
- GFP_KERNEL);
-
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
for (fschan = 0; fschan < QUADFS_MAX_CHAN; fschan++) {
struct clk *clk;
const char *clk_name;
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 25bda48..07795ee 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -733,17 +733,10 @@ static void __init clkgen_c32_pll_setup(struct device_node *np,
num_odfs = data->num_odfs;
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(num_odfs);
if (!clk_data)
return;
- clk_data->clk_num = num_odfs;
- clk_data->clks = kzalloc(clk_data->clk_num * sizeof(struct clk *),
- GFP_KERNEL);
-
- if (!clk_data->clks)
- goto err;
-
for (odf = 0; odf < num_odfs; odf++) {
struct clk *clk;
const char *clk_name;
@@ -768,8 +761,7 @@ static void __init clkgen_c32_pll_setup(struct device_node *np,
err:
kfree(pll_name);
- kfree(clk_data->clks);
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
}
static void __init clkgen_c32_pll0_setup(struct device_node *np)
{
--
2.7.4
^ permalink raw reply related
* [PATCH 7/7] clk: sunxi: make use of clk_alloc_onecell_data()
From: David Lechner @ 2018-01-05 0:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515112695-3160-1-git-send-email-david@lechnology.com>
Use helper function clk_alloc_onecell_data() to allocate struct
clk_onecell_data.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/sunxi/clk-a10-pll2.c | 14 ++++----------
drivers/clk/sunxi/clk-mod0.c | 13 +++----------
drivers/clk/sunxi/clk-simple-gates.c | 13 +++----------
drivers/clk/sunxi/clk-sun8i-bus-gates.c | 13 +++----------
drivers/clk/sunxi/clk-sunxi.c | 14 ++++----------
drivers/clk/sunxi/clk-usb.c | 8 +-------
6 files changed, 18 insertions(+), 57 deletions(-)
diff --git a/drivers/clk/sunxi/clk-a10-pll2.c b/drivers/clk/sunxi/clk-a10-pll2.c
index d8eab90..54b8386 100644
--- a/drivers/clk/sunxi/clk-a10-pll2.c
+++ b/drivers/clk/sunxi/clk-a10-pll2.c
@@ -58,13 +58,11 @@ static void __init sun4i_pll2_setup(struct device_node *node,
if (IS_ERR(reg))
return;
- clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(SUN4I_PLL2_OUTPUTS);
if (!clk_data)
goto err_unmap;
- clks = kcalloc(SUN4I_PLL2_OUTPUTS, sizeof(struct clk *), GFP_KERNEL);
- if (!clks)
- goto err_free_data;
+ clks = clk_data->clks;
parent = of_clk_get_parent_name(node, 0);
prediv_clk = clk_register_divider(NULL, "pll2-prediv",
@@ -75,7 +73,7 @@ static void __init sun4i_pll2_setup(struct device_node *node,
&sun4i_a10_pll2_lock);
if (IS_ERR(prediv_clk)) {
pr_err("Couldn't register the prediv clock\n");
- goto err_free_array;
+ goto err_free_data;
}
/* Setup the gate part of the PLL2 */
@@ -166,8 +164,6 @@ static void __init sun4i_pll2_setup(struct device_node *node,
2, 1);
WARN_ON(IS_ERR(clks[SUN4I_A10_PLL2_8X]));
- clk_data->clks = clks;
- clk_data->clk_num = SUN4I_PLL2_OUTPUTS;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return;
@@ -178,10 +174,8 @@ static void __init sun4i_pll2_setup(struct device_node *node,
kfree(gate);
err_unregister_prediv:
clk_unregister_divider(prediv_clk);
-err_free_array:
- kfree(clks);
err_free_data:
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
err_unmap:
iounmap(reg);
}
diff --git a/drivers/clk/sunxi/clk-mod0.c b/drivers/clk/sunxi/clk-mod0.c
index 4417ae1..d14c3f1 100644
--- a/drivers/clk/sunxi/clk-mod0.c
+++ b/drivers/clk/sunxi/clk-mod0.c
@@ -315,18 +315,13 @@ static void __init sunxi_mmc_setup(struct device_node *node,
return;
}
- clk_data = kmalloc(sizeof(*clk_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(3);
if (!clk_data)
return;
- clk_data->clks = kcalloc(3, sizeof(*clk_data->clks), GFP_KERNEL);
- if (!clk_data->clks)
- goto err_free_data;
-
- clk_data->clk_num = 3;
clk_data->clks[0] = sunxi_factors_register(node, data, lock, reg);
if (!clk_data->clks[0])
- goto err_free_clks;
+ goto err_free_data;
parent = __clk_get_name(clk_data->clks[0]);
@@ -366,10 +361,8 @@ static void __init sunxi_mmc_setup(struct device_node *node,
return;
-err_free_clks:
- kfree(clk_data->clks);
err_free_data:
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
}
static DEFINE_SPINLOCK(sun4i_a10_mmc_lock);
diff --git a/drivers/clk/sunxi/clk-simple-gates.c b/drivers/clk/sunxi/clk-simple-gates.c
index a085c3b..4685358 100644
--- a/drivers/clk/sunxi/clk-simple-gates.c
+++ b/drivers/clk/sunxi/clk-simple-gates.c
@@ -44,16 +44,12 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
clk_parent = of_clk_get_parent_name(node, 0);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- goto err_unmap;
-
number = of_property_count_u32_elems(node, "clock-indices");
of_property_read_u32_index(node, "clock-indices", number - 1, &number);
- clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks)
- goto err_free_data;
+ clk_data = clk_alloc_onecell_data(number + 1);
+ if (!clk_data)
+ goto err_unmap;
of_property_for_each_u32(node, "clock-indices", prop, p, index) {
of_property_read_string_index(node, "clock-output-names",
@@ -80,13 +76,10 @@ static void __init sunxi_simple_gates_setup(struct device_node *node,
}
- clk_data->clk_num = number + 1;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return;
-err_free_data:
- kfree(clk_data);
err_unmap:
iounmap(reg);
of_address_to_resource(node, 0, &res);
diff --git a/drivers/clk/sunxi/clk-sun8i-bus-gates.c b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
index bee305b..f3a3e05 100644
--- a/drivers/clk/sunxi/clk-sun8i-bus-gates.c
+++ b/drivers/clk/sunxi/clk-sun8i-bus-gates.c
@@ -54,16 +54,12 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
parents[i] = of_clk_get_parent_name(node, idx);
}
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
- if (!clk_data)
- goto err_unmap;
-
number = of_property_count_u32_elems(node, "clock-indices");
of_property_read_u32_index(node, "clock-indices", number - 1, &number);
- clk_data->clks = kcalloc(number + 1, sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks)
- goto err_free_data;
+ clk_data = clk_alloc_onecell_data(number + 1);
+ if (!clk_data)
+ goto err_unmap;
i = 0;
of_property_for_each_u32(node, "clock-indices", prop, p, index) {
@@ -98,13 +94,10 @@ static void __init sun8i_h3_bus_gates_init(struct device_node *node)
}
}
- clk_data->clk_num = number + 1;
of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
return;
-err_free_data:
- kfree(clk_data);
err_unmap:
iounmap(reg);
of_address_to_resource(node, 0, &res);
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index aa4add5..5a09d35 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -1012,15 +1012,11 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
return NULL;
}
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(ndivs);
if (!clk_data)
goto out_unmap;
- clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
- if (!clks)
- goto free_clkdata;
-
- clk_data->clks = clks;
+ clks = clk_data->clks;
/* It's not a good idea to have automatic reparenting changing
* our RAM clock! */
@@ -1045,7 +1041,7 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
if (data->div[i].gate) {
gate = kzalloc(sizeof(*gate), GFP_KERNEL);
if (!gate)
- goto free_clks;
+ goto free_clkdata;
gate->reg = reg;
gate->bit_idx = data->div[i].gate;
@@ -1106,10 +1102,8 @@ static struct clk ** __init sunxi_divs_clk_setup(struct device_node *node,
return clks;
free_gate:
kfree(gate);
-free_clks:
- kfree(clks);
free_clkdata:
- kfree(clk_data);
+ clk_free_onecell_data(clk_data);
out_unmap:
iounmap(reg);
return NULL;
diff --git a/drivers/clk/sunxi/clk-usb.c b/drivers/clk/sunxi/clk-usb.c
index fe0c3d16..4358d33 100644
--- a/drivers/clk/sunxi/clk-usb.c
+++ b/drivers/clk/sunxi/clk-usb.c
@@ -118,16 +118,10 @@ static void __init sunxi_usb_clk_setup(struct device_node *node,
qty = find_last_bit((unsigned long *)&data->clk_mask,
SUNXI_USB_MAX_SIZE);
- clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
+ clk_data = clk_alloc_onecell_data(qty + 1);
if (!clk_data)
return;
- clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
- if (!clk_data->clks) {
- kfree(clk_data);
- return;
- }
-
for_each_set_bit(i, (unsigned long *)&data->clk_mask,
SUNXI_USB_MAX_SIZE) {
of_property_read_string_index(node, "clock-output-names",
--
2.7.4
^ permalink raw reply related
* [PATCH v3] arm64: v8.4: Support for new floating point multiplication instructions
From: gengdongjiu @ 2018-01-05 1:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <73019dea-3e2c-8d03-fe1a-6c54527fa401@arm.com>
Hi will/catalin
On 2017/12/13 18:09, Suzuki K Poulose wrote:
> On 13/12/17 10:13, Dongjiu Geng wrote:
>> ARM v8.4 extensions add new neon instructions for performing a
>> multiplication of each FP16 element of one vector with the corresponding
>> FP16 element of a second vector, and to add or subtract this without an
>> intermediate rounding to the corresponding FP32 element in a third vector.
>>
>> This patch detects this feature and let the userspace know about it via a
>> HWCAP bit and MRS emulation.
>>
>> Cc: Dave Martin <Dave.Martin@arm.com>
>> Cc: Suzuki K Poulose <suzuki.poulose@arm.com>
>> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com>
>> Reviewed-by: Dave Martin <Dave.Martin@arm.com>
>
> Looks good to me.
>
> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
sorry to disturb you. Reminder, hope this patch can be applied to Linux 4.15-rc7.
Thanks a lot in advance.
>
>
> .
>
^ permalink raw reply
* [PATCH -next] clk: meson-axg: fix potential NULL dereference in axg_clkc_probe()
From: Wei Yongjun @ 2018-01-05 1:50 UTC (permalink / raw)
To: linux-arm-kernel
platform_get_resource() may return NULL, add proper
check to avoid potential NULL dereferencing.
This is detected by Coccinelle semantic patch.
@@
expression pdev, res, n, t, e, e1, e2;
@@
res = platform_get_resource(pdev, t, n);
+ if (!res)
+ return -EINVAL;
... when != res == NULL
e = devm_ioremap(e1, res->start, e2);
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
drivers/clk/meson/axg.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index d883bef..1294f3a 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -879,6 +879,8 @@ static int axg_clkc_probe(struct platform_device *pdev)
/* Generic clocks and PLLs */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -EINVAL;
clk_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
if (!clk_base) {
dev_err(&pdev->dev, "Unable to map clk base\n");
^ permalink raw reply related
* [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Icenowy Zheng @ 2018-01-05 2:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104185210.afsvsofq7q35psa6@flea.lan>
? 2018?1?5? GMT+08:00 ??2:52:10, Maxime Ripard <maxime.ripard@free-electrons.com> ??:
>On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej ?krabec wrote:
>> Hi Rob,
>>
>> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > > This commit adds all necessary compatibles and descriptions
>needed to
>> > > implement A83T HDMI pipeline.
>> > >
>> > > Mixer is already properly described, so only compatible is added.
>> > >
>> > > However, A83T TCON1, which is connected to HDMI, doesn't have
>channel 0,
>> > > contrary to all TCONs currently described. Because of that, TCON
>> > > documentation is extended.
>> > >
>> > > A83T features Synopsys DW HDMI controller with a custom PHY which
>looks
>> > > like Synopsys Gen2 PHY with few additions. Since there is no
>> > > documentation, needed properties were found out through
>experimentation
>> > > and reading BSP code.
>> > >
>> > > At the end, example is added for newer SoCs, which features DE2
>and DW
>> > > HDMI.
>> > >
>> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> > > ---
>> > >
>> > > .../bindings/display/sunxi/sun4i-drm.txt | 188
>> > > ++++++++++++++++++++- 1 file changed, 181 insertions(+), 7
>deletions(-)
>> > >
>> > > diff --git
>a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>index
>> > > 9f073af4c711..3eca258096a5 100644
>> > > ---
>a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > > +++
>b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > >
>> > > @@ -64,6 +64,40 @@ Required properties:
>> > > first port should be the input endpoint. The second should
>be the
>> > > output, usually to an HDMI connector.
>> > >
>> > > +DWC HDMI TX Encoder
>> > > +-----------------------------
>> > > +
>> > > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX
>controller IP
>> > > +with Allwinner's own PHY IP. It supports audio and video outputs
>and CEC.
>> > > +
>> > > +These DT bindings follow the Synopsys DWC HDMI TX bindings
>defined in
>> > > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
>with the
>> > > +following device-specific properties.
>> > > +
>> > > +Required properties:
>> > > +
>> > > + - compatible: value must be one of:
>> > > + * "allwinner,sun8i-a83t-dw-hdmi"
>> > > + - reg: two pairs of base address and size of memory-mapped
>region,
>> > > first
>> > > + for controller and second for PHY
>> > > + registers.
>> >
>> > Seems like the phy should be a separate node and use the phy
>binding.
>> > You can use the phy binding even if you don't use the kernel phy
>> > framework...
>>
>> Unfortunately, it's not so straighforward. Phy is actually accessed
>through
>> I2C implemented in HDMI controller. Second memory region in this case
>has
>> small influence on phy. However, it has big influence on controller.
>For
>> example, magic number has to be written in one register in second
>memory
>> region in order to unlock read access to any register from first
>memory region
>> (controller). However, they shouldn't be merged to one region,
>because first
>> memory region requires byte access while second memory region can be
>accessed
>> per byte or word.
>>
>> To complicate things more, later I want to add support for another
>SoC which
>> has same glue layer (unlocking read access, etc.) and uses memory
>mapped phy
>> registers in second memory region.
>>
>> I think current binding is the least complicated way to represent
>this.
>
>I agree with Rob here. I did a similar thing for the DSI patches I've
>sent a few monthes ago and it turned out to not be that difficult, so
>I'm sure you can come up with something :)
In A83T/H3/A64/H5/R40 this part is not purely a PHY.
It controls the access of main controller's register (e.g. read/write
lock and register obfuscation). So it should be called a "glue"
with PHY part (and on A83T seems a pure glue) but not a simple
PHY.
>
>Maxime
>
>--
>Maxime Ripard, Free Electrons
>Embedded Linux and Kernel engineering
>http://free-electrons.com
>
>_______________________________________________
>linux-arm-kernel mailing list
>linux-arm-kernel at lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Icenowy Zheng @ 2018-01-05 2:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1645801.yZU0HLsLbk@jernej-laptop>
? 2018?1?4? GMT+08:00 ??5:32:26, "Jernej ?krabec" <jernej.skrabec@siol.net> ??:
>Hi Rob,
>
>Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > This commit adds all necessary compatibles and descriptions needed
>to
>> > implement A83T HDMI pipeline.
>> >
>> > Mixer is already properly described, so only compatible is added.
>> >
>> > However, A83T TCON1, which is connected to HDMI, doesn't have
>channel 0,
>> > contrary to all TCONs currently described. Because of that, TCON
>> > documentation is extended.
>> >
>> > A83T features Synopsys DW HDMI controller with a custom PHY which
>looks
>> > like Synopsys Gen2 PHY with few additions. Since there is no
>> > documentation, needed properties were found out through
>experimentation
>> > and reading BSP code.
>> >
>> > At the end, example is added for newer SoCs, which features DE2 and
>DW
>> > HDMI.
>> >
>> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
>> > ---
>> >
>> > .../bindings/display/sunxi/sun4i-drm.txt | 188
>> > ++++++++++++++++++++- 1 file changed, 181 insertions(+), 7
>deletions(-)
>> >
>> > diff --git
>a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>index
>> > 9f073af4c711..3eca258096a5 100644
>> > --- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> > +++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
>> >
>> > @@ -64,6 +64,40 @@ Required properties:
>> > first port should be the input endpoint. The second should be
>the
>> > output, usually to an HDMI connector.
>> >
>> > +DWC HDMI TX Encoder
>> > +-----------------------------
>> > +
>> > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX
>controller IP
>> > +with Allwinner's own PHY IP. It supports audio and video outputs
>and CEC.
>> > +
>> > +These DT bindings follow the Synopsys DWC HDMI TX bindings defined
>in
>> > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt with
>the
>> > +following device-specific properties.
>> > +
>> > +Required properties:
>> > +
>> > + - compatible: value must be one of:
>> > + * "allwinner,sun8i-a83t-dw-hdmi"
>> > + - reg: two pairs of base address and size of memory-mapped
>region,
>> > first
>> > + for controller and second for PHY
>> > + registers.
>>
>> Seems like the phy should be a separate node and use the phy binding.
>> You can use the phy binding even if you don't use the kernel phy
>> framework...
>
>Unfortunately, it's not so straighforward. Phy is actually accessed
>through
>I2C implemented in HDMI controller. Second memory region in this case
>has
>small influence on phy. However, it has big influence on controller.
To be honest you used inaccurate word. Use "glue" directly
here may be more accurate.
>For
>example, magic number has to be written in one register in second
>memory
>region in order to unlock read access to any register from first memory
>region
>(controller). However, they shouldn't be merged to one region, because
>first
>memory region requires byte access while second memory region can be
>accessed
>per byte or word.
>
>To complicate things more, later I want to add support for another SoC
>which
>has same glue layer (unlocking read access, etc.) and uses memory
>mapped phy
>registers in second memory region.
>
>I think current binding is the least complicated way to represent this.
>
>>
>> > + - reg-io-width: See dw_hdmi.txt. Shall be 1.
>> > + - interrupts: HDMI interrupt number
>> > + - clocks: phandles to the clocks feeding the HDMI encoder
>> > + * iahb: the HDMI bus clock
>> > + * isfr: the HDMI register clock
>> > + * tmds: the HDMI tmds clock
>> > + - clock-names: the clock names mentioned above
>> > + - resets: phandles to the reset controllers driving the encoder
>> > + * ctrl: the reset line for the controller
>> > + * phy: the reset line for the PHY
>> > + - reset-names: the reset names mentioned above
>> > +
>> > + - ports: A ports node with endpoint definitions as defined in
>> > + Documentation/devicetree/bindings/media/video-interfaces.txt.
>The
>> > + first port should be the input endpoint. The second should be
>the
>> > + output, usually to an HDMI connector.
>> > +
>> >
>> > TV Encoder
>> > ----------
>> >
>> > @@ -94,18 +128,17 @@ Required properties:
>> > * allwinner,sun7i-a20-tcon
>> > * allwinner,sun8i-a33-tcon
>> > * allwinner,sun8i-a83t-tcon-lcd
>> >
>> > + * allwinner,sun8i-a83t-tcon-tv
>> >
>> > * allwinner,sun8i-v3s-tcon
>> >
>> > - reg: base address and size of memory-mapped region
>> > - interrupts: interrupt associated to this IP
>> >
>> > - - clocks: phandles to the clocks feeding the TCON. Three are
>needed:
>> >
>> > + - clocks: phandles to the clocks feeding the TCON. One is needed:
>> > - 'ahb': the interface clocks
>> >
>> > - - 'tcon-ch0': The clock driving the TCON channel 0
>> >
>> > - resets: phandles to the reset controllers driving the encoder
>> >
>> > - "lcd": the reset line for the TCON channel 0
>> >
>> > - clock-names: the clock names mentioned above
>> > - reset-names: the reset names mentioned above
>> >
>> > - - clock-output-names: Name of the pixel clock created
>> >
>> > - ports: A ports node with endpoint definitions as defined in
>> >
>> > Documentation/devicetree/bindings/media/video-interfaces.txt.
>The
>> >
>> > @@ -119,11 +152,31 @@ Required properties:
>> > channel the endpoint is associated to. If that property is not
>> > present, the endpoint number will be used as the channel number.
>> >
>> > -On SoCs other than the A33 and V3s, there is one more clock
>required:
>> > +Following compatibles:
>> > + * allwinner,sun4i-a10-tcon
>> > + * allwinner,sun5i-a13-tcon
>> > + * allwinner,sun6i-a31-tcon
>> > + * allwinner,sun6i-a31s-tcon
>> > + * allwinner,sun7i-a20-tcon
>> > + * allwinner,sun8i-a33-tcon
>> > + * allwinner,sun8i-a83t-tcon-lcd
>> > + * allwinner,sun8i-v3s-tcon
>> > +have additional required properties:
>> > + - 'tcon-ch0': The clock driving the TCON channel 0
>>
>> tcon-ch0 is a clock name, not a property.
>
>right.
>
>Best regards,
>Jernej
>
>
>
>_______________________________________________
>linux-arm-kernel mailing list
>linux-arm-kernel at lists.infradead.org
>http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH v4 6/7] ARM: davinci: convert to common clock framework
From: David Lechner @ 2018-01-05 2:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f09641b7-a9e9-24d1-ce13-1b627d077ce5@lechnology.com>
On 01/04/2018 11:50 AM, David Lechner wrote:
>
>
> On 1/4/18 6:39 AM, Sekhar Nori wrote:
>> On Monday 01 January 2018 05:09 AM, David Lechner wrote:
>>> This converts all of arch/arm/mach-davinci to the common clock framework.
>>> The clock drivers from clock.c and psc.c have been moved to drivers/clk,
>>> so these files are removed.
>>>
>>> There is one subtle change in the clock trees. AUX, BPDIV and OSCDIV
>>> clocks now have "ref_clk" as a parent instead of the PLL clock. These
>>> clocks are part of the PLL's MMIO block, but they bypass the PLL and
>>> therefore it makes more sense to have "ref_clk" as their parent since
>>> "ref_clk" is the input clock of the PLL.
>>>
>>> CONFIG_DAVINCI_RESET_CLOCKS is removed since the common clock frameworks
>>> takes care of disabling unused clocks.
>>>
>>> Known issue: This breaks CPU frequency scaling on da850.
>>
>> This functionality needs to be restored as part of this series since we
>> cannot commit anything with regressions.
>>
>
> Do you have a suggestion on how to accomplish this? I don't have a board for testing, so I don't have a way of knowing if my changes will work or not.
>
>>>
>>> Also, the order of #includes are cleaned up in files while we are touching
>>> this code.
>>>
>>> Signed-off-by: David Lechner <david@lechnology.com>
>>
>> This is a pretty huge patch again and I hope it can be broken down.
>> Ideally one per SoC converted and then the unused code removal.
>>
>
> Will do.
Well, I can do this, but I don't think it will compile or run. We can't
have the common clock framework and the legacy davinci clocks enabled at
the same time.
^ permalink raw reply
* [PATCH 05/12] arm64: dts: mt7622: add PMIC MT6380 related nodes
From: Sean Wang @ 2018-01-05 3:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAOFm3uF0WHO6_Y6dKu3DnAd759tA2hNQs=0-P86s1A0e==27Ow@mail.gmail.com>
On Thu, 2018-01-04 at 11:27 +0100, Philippe Ombredanne wrote:
> Sean,
>
> On Thu, Jan 4, 2018 at 10:40 AM, <sean.wang@mediatek.com> wrote:
> > From: Sean Wang <sean.wang@mediatek.com>
> >
> > Enable pwrap and MT6380 on mt7622-rfb1 board. Also add all mt6380
> > regulator nodes in an alone file to allow similar boards using MT6380
> > able to resue the configuration.
> >
> > Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> > Cc: Mark Brown <broonie@kernel.org>
> > Cc: Matthias Brugger <matthias.bgg@gmail.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt6380.dtsi | 91 ++++++++++++++++++++++++++++
> > arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts | 8 +++
> > arch/arm64/boot/dts/mediatek/mt7622.dtsi | 12 ++++
> > 3 files changed, 111 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/mediatek/mt6380.dtsi
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt6380.dtsi b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> > new file mode 100644
> > index 0000000..7eb7dc2
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/mediatek/mt6380.dtsi
> > @@ -0,0 +1,91 @@
> > +/*
> > + * Copyright (c) 2018 MediaTek Inc.
> > + * Author: Chenglin Xu <chenglin.xu@mediatek.com>
> > + * Sean Wang <sean.wang@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
>
> Would you mind using SPDX tags instead of this fine but long legalese?
> This is documented in Thomas patches [1].
> Also if you could spread the word in your team, this would earn you
> good karma points.
> Thank you!
>
> [1] https://lkml.org/lkml/2017/12/28/323
Hi, Philippe
thanks for your suggestion
Certainly, this can be replaced with
SPDX-License-Identifier: GPL-2.0
most drivers from MediaTek use the similar disclaimer, it should be fine
to use SPDX tags instead.
Sean
^ permalink raw reply
* [PATCH] arm: dts: mediatek: add audsys node for both MT2701 and MT7623
From: Ryder Lee @ 2018-01-05 3:57 UTC (permalink / raw)
To: linux-arm-kernel
Add audsys support for both MT2701/MT7623. Then modify afe node to adapt it.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
---
This patch is dependent on https://www.spinics.net/lists/arm-kernel/msg626503.html
---
arch/arm/boot/dts/mt2701.dtsi | 188 ++++++++++++++++++++---------------------
arch/arm/boot/dts/mt7623.dtsi | 190 ++++++++++++++++++++----------------------
2 files changed, 182 insertions(+), 196 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 965ddfb..52b4622 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -426,104 +426,96 @@
status = "disabled";
};
- afe: audio-controller at 11220000 {
- compatible = "mediatek,mt2701-audio";
- reg = <0 0x11220000 0 0x2000>,
- <0 0x112a0000 0 0x20000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
-
- clocks = <&infracfg CLK_INFRA_AUDIO>,
- <&topckgen CLK_TOP_AUD_MUX1_SEL>,
- <&topckgen CLK_TOP_AUD_MUX2_SEL>,
- <&topckgen CLK_TOP_AUD_MUX1_DIV>,
- <&topckgen CLK_TOP_AUD_MUX2_DIV>,
- <&topckgen CLK_TOP_AUD_48K_TIMING>,
- <&topckgen CLK_TOP_AUD_44K_TIMING>,
- <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
- <&topckgen CLK_TOP_APLL_SEL>,
- <&topckgen CLK_TOP_AUD1PLL_98M>,
- <&topckgen CLK_TOP_AUD2PLL_90M>,
- <&topckgen CLK_TOP_HADDS2PLL_98M>,
- <&topckgen CLK_TOP_HADDS2PLL_294M>,
- <&topckgen CLK_TOP_AUDPLL>,
- <&topckgen CLK_TOP_AUDPLL_D4>,
- <&topckgen CLK_TOP_AUDPLL_D8>,
- <&topckgen CLK_TOP_AUDPLL_D16>,
- <&topckgen CLK_TOP_AUDPLL_D24>,
- <&topckgen CLK_TOP_AUDINTBUS_SEL>,
- <&clk26m>,
- <&topckgen CLK_TOP_SYSPLL1_D4>,
- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
- <&topckgen CLK_TOP_ASM_M_SEL>,
- <&topckgen CLK_TOP_ASM_H_SEL>,
- <&topckgen CLK_TOP_UNIVPLL2_D4>,
- <&topckgen CLK_TOP_UNIVPLL2_D2>,
- <&topckgen CLK_TOP_SYSPLL_D5>;
-
- clock-names = "infra_sys_audio_clk",
- "top_audio_mux1_sel",
- "top_audio_mux2_sel",
- "top_audio_mux1_div",
- "top_audio_mux2_div",
- "top_audio_48k_timing",
- "top_audio_44k_timing",
- "top_audpll_mux_sel",
- "top_apll_sel",
- "top_aud1_pll_98M",
- "top_aud2_pll_90M",
- "top_hadds2_pll_98M",
- "top_hadds2_pll_294M",
- "top_audpll",
- "top_audpll_d4",
- "top_audpll_d8",
- "top_audpll_d16",
- "top_audpll_d24",
- "top_audintbus_sel",
- "clk_26m",
- "top_syspll1_d4",
- "top_aud_k1_src_sel",
- "top_aud_k2_src_sel",
- "top_aud_k3_src_sel",
- "top_aud_k4_src_sel",
- "top_aud_k5_src_sel",
- "top_aud_k6_src_sel",
- "top_aud_k1_src_div",
- "top_aud_k2_src_div",
- "top_aud_k3_src_div",
- "top_aud_k4_src_div",
- "top_aud_k5_src_div",
- "top_aud_k6_src_div",
- "top_aud_i2s1_mclk",
- "top_aud_i2s2_mclk",
- "top_aud_i2s3_mclk",
- "top_aud_i2s4_mclk",
- "top_aud_i2s5_mclk",
- "top_aud_i2s6_mclk",
- "top_asm_m_sel",
- "top_asm_h_sel",
- "top_univpll2_d4",
- "top_univpll2_d2",
- "top_syspll_d5";
+ audsys: audio-subsystem at 11220000 {
+ compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
+
+ afe: audio-controller {
+ compatible = "mediatek,mt2701-audio";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "afe", "asys";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&audsys CLK_AUD_I2SO1>,
+ <&audsys CLK_AUD_I2SO2>,
+ <&audsys CLK_AUD_I2SO3>,
+ <&audsys CLK_AUD_I2SO4>,
+ <&audsys CLK_AUD_I2SIN1>,
+ <&audsys CLK_AUD_I2SIN2>,
+ <&audsys CLK_AUD_I2SIN3>,
+ <&audsys CLK_AUD_I2SIN4>,
+ <&audsys CLK_AUD_ASRCO1>,
+ <&audsys CLK_AUD_ASRCO2>,
+ <&audsys CLK_AUD_ASRCO3>,
+ <&audsys CLK_AUD_ASRCO4>,
+ <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_AFE_CONN>,
+ <&audsys CLK_AUD_A1SYS>,
+ <&audsys CLK_AUD_A2SYS>,
+ <&audsys CLK_AUD_AFE_MRGIF>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_a1sys_hp",
+ "top_audio_a2sys_hp",
+ "i2s0_src_sel",
+ "i2s1_src_sel",
+ "i2s2_src_sel",
+ "i2s3_src_sel",
+ "i2s0_src_div",
+ "i2s1_src_div",
+ "i2s2_src_div",
+ "i2s3_src_div",
+ "i2s0_mclk_en",
+ "i2s1_mclk_en",
+ "i2s2_mclk_en",
+ "i2s3_mclk_en",
+ "i2so0_hop_ck",
+ "i2so1_hop_ck",
+ "i2so2_hop_ck",
+ "i2so3_hop_ck",
+ "i2si0_hop_ck",
+ "i2si1_hop_ck",
+ "i2si2_hop_ck",
+ "i2si3_hop_ck",
+ "asrc0_out_ck",
+ "asrc1_out_ck",
+ "asrc2_out_ck",
+ "asrc3_out_ck",
+ "audio_afe_pd",
+ "audio_afe_conn_pd",
+ "audio_a1sys_pd",
+ "audio_a2sys_pd",
+ "audio_mrgif_pd";
+
+ assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+ assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>;
+ assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+ };
};
mmsys: syscon at 14000000 {
diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi
index 0640fb7..b0e39d0 100644
--- a/arch/arm/boot/dts/mt7623.dtsi
+++ b/arch/arm/boot/dts/mt7623.dtsi
@@ -538,105 +538,99 @@
status = "disabled";
};
- afe: audio-controller at 11220000 {
- compatible = "mediatek,mt7623-audio",
- "mediatek,mt2701-audio";
- reg = <0 0x11220000 0 0x2000>,
- <0 0x112a0000 0 0x20000>;
- interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
- power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+ audsys: audio-subsystem at 11220000 {
+ compatible = "mediatek,mt7623-audsys",
+ "mediatek,mt2701-audsys",
+ "syscon", "simple-mfd";
+ reg = <0 0x11220000 0 0x2000>;
+ #clock-cells = <1>;
- clocks = <&infracfg CLK_INFRA_AUDIO>,
- <&topckgen CLK_TOP_AUD_MUX1_SEL>,
- <&topckgen CLK_TOP_AUD_MUX2_SEL>,
- <&topckgen CLK_TOP_AUD_MUX1_DIV>,
- <&topckgen CLK_TOP_AUD_MUX2_DIV>,
- <&topckgen CLK_TOP_AUD_48K_TIMING>,
- <&topckgen CLK_TOP_AUD_44K_TIMING>,
- <&topckgen CLK_TOP_AUDPLL_MUX_SEL>,
- <&topckgen CLK_TOP_APLL_SEL>,
- <&topckgen CLK_TOP_AUD1PLL_98M>,
- <&topckgen CLK_TOP_AUD2PLL_90M>,
- <&topckgen CLK_TOP_HADDS2PLL_98M>,
- <&topckgen CLK_TOP_HADDS2PLL_294M>,
- <&topckgen CLK_TOP_AUDPLL>,
- <&topckgen CLK_TOP_AUDPLL_D4>,
- <&topckgen CLK_TOP_AUDPLL_D8>,
- <&topckgen CLK_TOP_AUDPLL_D16>,
- <&topckgen CLK_TOP_AUDPLL_D24>,
- <&topckgen CLK_TOP_AUDINTBUS_SEL>,
- <&clk26m>,
- <&topckgen CLK_TOP_SYSPLL1_D4>,
- <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K5_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K6_SRC_SEL>,
- <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K5_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_K6_SRC_DIV>,
- <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S5_MCLK>,
- <&topckgen CLK_TOP_AUD_I2S6_MCLK>,
- <&topckgen CLK_TOP_ASM_M_SEL>,
- <&topckgen CLK_TOP_ASM_H_SEL>,
- <&topckgen CLK_TOP_UNIVPLL2_D4>,
- <&topckgen CLK_TOP_UNIVPLL2_D2>,
- <&topckgen CLK_TOP_SYSPLL_D5>;
-
- clock-names = "infra_sys_audio_clk",
- "top_audio_mux1_sel",
- "top_audio_mux2_sel",
- "top_audio_mux1_div",
- "top_audio_mux2_div",
- "top_audio_48k_timing",
- "top_audio_44k_timing",
- "top_audpll_mux_sel",
- "top_apll_sel",
- "top_aud1_pll_98M",
- "top_aud2_pll_90M",
- "top_hadds2_pll_98M",
- "top_hadds2_pll_294M",
- "top_audpll",
- "top_audpll_d4",
- "top_audpll_d8",
- "top_audpll_d16",
- "top_audpll_d24",
- "top_audintbus_sel",
- "clk_26m",
- "top_syspll1_d4",
- "top_aud_k1_src_sel",
- "top_aud_k2_src_sel",
- "top_aud_k3_src_sel",
- "top_aud_k4_src_sel",
- "top_aud_k5_src_sel",
- "top_aud_k6_src_sel",
- "top_aud_k1_src_div",
- "top_aud_k2_src_div",
- "top_aud_k3_src_div",
- "top_aud_k4_src_div",
- "top_aud_k5_src_div",
- "top_aud_k6_src_div",
- "top_aud_i2s1_mclk",
- "top_aud_i2s2_mclk",
- "top_aud_i2s3_mclk",
- "top_aud_i2s4_mclk",
- "top_aud_i2s5_mclk",
- "top_aud_i2s6_mclk",
- "top_asm_m_sel",
- "top_asm_h_sel",
- "top_univpll2_d4",
- "top_univpll2_d2",
- "top_syspll_d5";
+ afe: audio-controller {
+ compatible = "mediatek,mt7623-audio",
+ "mediatek,mt2701-audio";
+ interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "afe", "asys";
+ power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
+
+ clocks = <&infracfg CLK_INFRA_AUDIO>,
+ <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_48K_TIMING>,
+ <&topckgen CLK_TOP_AUD_44K_TIMING>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
+ <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
+ <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
+ <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
+ <&audsys CLK_AUD_I2SO1>,
+ <&audsys CLK_AUD_I2SO2>,
+ <&audsys CLK_AUD_I2SO3>,
+ <&audsys CLK_AUD_I2SO4>,
+ <&audsys CLK_AUD_I2SIN1>,
+ <&audsys CLK_AUD_I2SIN2>,
+ <&audsys CLK_AUD_I2SIN3>,
+ <&audsys CLK_AUD_I2SIN4>,
+ <&audsys CLK_AUD_ASRCO1>,
+ <&audsys CLK_AUD_ASRCO2>,
+ <&audsys CLK_AUD_ASRCO3>,
+ <&audsys CLK_AUD_ASRCO4>,
+ <&audsys CLK_AUD_AFE>,
+ <&audsys CLK_AUD_AFE_CONN>,
+ <&audsys CLK_AUD_A1SYS>,
+ <&audsys CLK_AUD_A2SYS>,
+ <&audsys CLK_AUD_AFE_MRGIF>;
+
+ clock-names = "infra_sys_audio_clk",
+ "top_audio_mux1_sel",
+ "top_audio_mux2_sel",
+ "top_audio_a1sys_hp",
+ "top_audio_a2sys_hp",
+ "i2s0_src_sel",
+ "i2s1_src_sel",
+ "i2s2_src_sel",
+ "i2s3_src_sel",
+ "i2s0_src_div",
+ "i2s1_src_div",
+ "i2s2_src_div",
+ "i2s3_src_div",
+ "i2s0_mclk_en",
+ "i2s1_mclk_en",
+ "i2s2_mclk_en",
+ "i2s3_mclk_en",
+ "i2so0_hop_ck",
+ "i2so1_hop_ck",
+ "i2so2_hop_ck",
+ "i2so3_hop_ck",
+ "i2si0_hop_ck",
+ "i2si1_hop_ck",
+ "i2si2_hop_ck",
+ "i2si3_hop_ck",
+ "asrc0_out_ck",
+ "asrc1_out_ck",
+ "asrc2_out_ck",
+ "asrc3_out_ck",
+ "audio_afe_pd",
+ "audio_afe_conn_pd",
+ "audio_a1sys_pd",
+ "audio_a2sys_pd",
+ "audio_mrgif_pd";
+
+ assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX2_SEL>,
+ <&topckgen CLK_TOP_AUD_MUX1_DIV>,
+ <&topckgen CLK_TOP_AUD_MUX2_DIV>;
+ assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
+ <&topckgen CLK_TOP_AUD2PLL_90M>;
+ assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
+ };
};
mmc0: mmc at 11230000 {
--
1.9.1
^ permalink raw reply related
* [PATCH v4 2/3] mailbox: Add support for Hi3660 mailbox
From: Jassi Brar @ 2018-01-05 4:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513682145-19892-3-git-send-email-zhongkaihua@huawei.com>
On Tue, Dec 19, 2017 at 4:45 PM, Kaihua Zhong <zhongkaihua@huawei.com> wrote:
.....
> diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c
> new file mode 100644
> index 0000000..3ceca40
> --- /dev/null
> +++ b/drivers/mailbox/hi3660-mailbox.c
> @@ -0,0 +1,319 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2017 Hisilicon Limited.
> +// Copyright (c) 2017 Linaro Limited.
A blank here please.
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <linux/device.h>
> +#include <linux/err.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/iopoll.h>
.....
> +
> +static inline struct hi3660_mbox *to_hi3660_mbox(struct mbox_controller *mbox)
>
inline in .c is out of fasion these days
> +{
> + return container_of(mbox, struct hi3660_mbox, controller);
> +}
> +
....
> +
> +static int hi3660_mbox_startup(struct mbox_chan *chan)
> +{
> + int ret;
> +
> + ret = hi3660_mbox_check_state(chan);
> + if (ret)
> + return ret;
> +
> + ret = hi3660_mbox_unlock(chan);
> + if (ret)
> + return ret;
> +
> + ret = hi3660_mbox_acquire_channel(chan);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
Do you not need to do "release channel" for shutdown() ?
.....
> +
> +static int hi3660_mbox_send_data(struct mbox_chan *chan, void *msg)
> +{
> + return hi3660_mbox_send(chan, msg);
>
Please directly have hi3660_mbox_send as .send_data
Cheers!
^ permalink raw reply
* [PATCH V7 12/12] arm64: dts: add clocks for SC9860
From: Chunyan Zhang @ 2018-01-05 5:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a2Qpbr6EB+qWMQqCLkbnVddL+MHx1sFNs-+97ZQ=QaHeg@mail.gmail.com>
On 5 January 2018 at 07:01, Arnd Bergmann <arnd@arndb.de> wrote:
> On Thu, Jan 4, 2018 at 10:34 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Thu, Dec 7, 2017 at 1:57 PM, Chunyan Zhang
>> <chunyan.zhang@spreadtrum.com> wrote:
>>> Some clocks on SC9860 are in the same address area with syscon devices,
>>> those are what have a property of 'sprd,syscon' which would refer to
>>> syscon devices, others would have a reg property indicated their address
>>> ranges.
>>>
>>> Signed-off-by: Chunyan Zhang <chunyan.zhang@spreadtrum.com>
>>> ---
>>> arch/arm64/boot/dts/sprd/sc9860.dtsi | 115 +++++++++++++++++++++++++++++++++++
>>> arch/arm64/boot/dts/sprd/whale2.dtsi | 18 +++++-
>>> 2 files changed, 131 insertions(+), 2 deletions(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/sprd/sc9860.dtsi b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> index 7b7d8ce..bf03da4 100644
>>> --- a/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> +++ b/arch/arm64/boot/dts/sprd/sc9860.dtsi
>>> @@ -7,6 +7,7 @@
>>> */
>>>
>>> #include <dt-bindings/interrupt-controller/arm-gic.h>
>>> +#include <dt-bindings/clock/sprd,sc9860-clk.h>
>>> #include "whale2.dtsi"
>>
>> This caused a build error since the sprd,sc9860-clk.h file does not
>> exist, I'll revert or undo the patch tomorrow.
>
> I've taken another look, and fixing it by removing the broken #include
> was easier than undoing the patches, so I did that now, see
> https://patchwork.kernel.org/patch/10145773/
Ok, thanks Arnd!
Chunyan
>
> Arnd
^ permalink raw reply
* [linux-sunxi] Re: [PATCH 06/11] dt-bindings: display: sun4i-drm: Add A83T HDMI pipeline
From: Jernej Škrabec @ 2018-01-05 6:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4B652FB5-08B2-416B-ABA9-08E12112087D@aosc.io>
Hi,
Dne petek, 05. januar 2018 ob 03:49:09 CET je Icenowy Zheng napisal(a):
> ? 2018?1?5? GMT+08:00 ??2:52:10, Maxime Ripard <maxime.ripard@free-
electrons.com> ??:
> >On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej ?krabec wrote:
> >> Hi Rob,
> >>
> >> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
> >> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
> >> > > This commit adds all necessary compatibles and descriptions
> >
> >needed to
> >
> >> > > implement A83T HDMI pipeline.
> >> > >
> >> > > Mixer is already properly described, so only compatible is added.
> >> > >
> >> > > However, A83T TCON1, which is connected to HDMI, doesn't have
> >
> >channel 0,
> >
> >> > > contrary to all TCONs currently described. Because of that, TCON
> >> > > documentation is extended.
> >> > >
> >> > > A83T features Synopsys DW HDMI controller with a custom PHY which
> >
> >looks
> >
> >> > > like Synopsys Gen2 PHY with few additions. Since there is no
> >> > > documentation, needed properties were found out through
> >
> >experimentation
> >
> >> > > and reading BSP code.
> >> > >
> >> > > At the end, example is added for newer SoCs, which features DE2
> >
> >and DW
> >
> >> > > HDMI.
> >> > >
> >> > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> >> > > ---
> >> > >
> >> > > .../bindings/display/sunxi/sun4i-drm.txt | 188
> >> > > ++++++++++++++++++++- 1 file changed, 181 insertions(+), 7
> >
> >deletions(-)
> >
> >> > > diff --git
> >
> >a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >> > > b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >index
> >
> >> > > 9f073af4c711..3eca258096a5 100644
> >> > > ---
> >
> >a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >> > > +++
> >
> >b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
> >
> >> > > @@ -64,6 +64,40 @@ Required properties:
> >> > > first port should be the input endpoint. The second should
> >
> >be the
> >
> >> > > output, usually to an HDMI connector.
> >> > >
> >> > > +DWC HDMI TX Encoder
> >> > > +-----------------------------
> >> > > +
> >> > > +The HDMI transmitter is a Synopsys DesignWare HDMI 1.4 TX
> >
> >controller IP
> >
> >> > > +with Allwinner's own PHY IP. It supports audio and video outputs
> >
> >and CEC.
> >
> >> > > +
> >> > > +These DT bindings follow the Synopsys DWC HDMI TX bindings
> >
> >defined in
> >
> >> > > +Documentation/devicetree/bindings/display/bridge/dw_hdmi.txt
> >
> >with the
> >
> >> > > +following device-specific properties.
> >> > > +
> >> > > +Required properties:
> >> > > +
> >> > > + - compatible: value must be one of:
> >> > > + * "allwinner,sun8i-a83t-dw-hdmi"
> >> > > + - reg: two pairs of base address and size of memory-mapped
> >
> >region,
> >
> >> > > first
> >> > > + for controller and second for PHY
> >> > > + registers.
> >> >
> >> > Seems like the phy should be a separate node and use the phy
> >
> >binding.
> >
> >> > You can use the phy binding even if you don't use the kernel phy
> >> > framework...
> >>
> >> Unfortunately, it's not so straighforward. Phy is actually accessed
> >
> >through
> >
> >> I2C implemented in HDMI controller. Second memory region in this case
> >
> >has
> >
> >> small influence on phy. However, it has big influence on controller.
> >
> >For
> >
> >> example, magic number has to be written in one register in second
> >
> >memory
> >
> >> region in order to unlock read access to any register from first
> >
> >memory region
> >
> >> (controller). However, they shouldn't be merged to one region,
> >
> >because first
> >
> >> memory region requires byte access while second memory region can be
> >
> >accessed
> >
> >> per byte or word.
> >>
> >> To complicate things more, later I want to add support for another
> >
> >SoC which
> >
> >> has same glue layer (unlocking read access, etc.) and uses memory
> >
> >mapped phy
> >
> >> registers in second memory region.
> >>
> >> I think current binding is the least complicated way to represent
> >
> >this.
> >
> >I agree with Rob here. I did a similar thing for the DSI patches I've
> >sent a few monthes ago and it turned out to not be that difficult, so
> >I'm sure you can come up with something :)
>
> In A83T/H3/A64/H5/R40 this part is not purely a PHY.
> It controls the access of main controller's register (e.g. read/write
> lock and register obfuscation). So it should be called a "glue"
> with PHY part (and on A83T seems a pure glue) but not a simple
> PHY.
It's not so simple. Actually it has PHY settings also on A83T. For example,
value at 0x01EF0001 depends on polarity. Value at 0x01EF0002 sets PHY I2C
address. Bit 7 at 0x01EF0007 enables/disables external resistor. That is info
I discovered/received after I sent patches, so it's not cleary marked.
Proper memory map (starts at 0x01EE0000):
0x00000 - 0x10000 -> DW HDMI controller
0x10000 - 0x10010 -> (almost?) Common PHY settings
0x10010 - 0x10020 -> Allwinner proprietary glue layer
0x10020 - 0x10040 -> Allwinner proprietary PHY (not present on A83T)
In preliminary PHY doc AW released, there are additional regs at 0x01EF0FF8
and 0x01EF0FFC for controller ID and phy ID, but it was always 0 at A83T and
H3.
So splitting memory in so many regions just to satisfy clean division it
doesn't seem sane to me. Now that I checked how Maxime did it with MIPI DSI
driver, I'm good with dividing it into two parts.
Best regards,
Jernej
>
> >Maxime
> >
> >--
> >Maxime Ripard, Free Electrons
> >Embedded Linux and Kernel engineering
> >http://free-electrons.com
> >
> >_______________________________________________
> >linux-arm-kernel mailing list
> >linux-arm-kernel at lists.infradead.org
> >http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
> --
> You received this message because you are subscribed to the Google Groups
> "linux-sunxi" group. To unsubscribe from this group and stop receiving
> emails from it, send an email to linux-sunxi+unsubscribe at googlegroups.com.
> For more options, visit https://groups.google.com/d/optout.
^ permalink raw reply
* [GIT PULL 1/2] Broadcom devicetree changes for 4.16
From: Olof Johansson @ 2018-01-05 6:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222001227.30625-1-f.fainelli@gmail.com>
On Thu, Dec 21, 2017 at 04:12:26PM -0800, Florian Fainelli wrote:
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.16/devicetree
>
> for you to fetch changes up to ececb5639c33a6a0444bd8e1cda8bf2ef20c6a6b:
>
> Merge tag 'bcm2835-dt-next-2017-12-19' into devicetree/next (2017-12-20 17:32:58 -0800)
>
> ----------------------------------------------------------------
> This pull request contains Broadcom ARM-based SoCs Device Tree changes for
> 4.16, please pull the following:
>
> - Stefan updates the BCM283x DTS to make consistent use of the existing GPIO
> defines for the polarity specifier
>
> ----------------------------------------------------------------
> Florian Fainelli (1):
> Merge tag 'bcm2835-dt-next-2017-12-19' into devicetree/next
>
> Stefan Wahren (1):
> ARM: dts: bcm283x: Use GPIO polarity defines consistently
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL 2/2] Broadcom drivers changes for 4.16
From: Olof Johansson @ 2018-01-05 6:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222001227.30625-2-f.fainelli@gmail.com>
On Thu, Dec 21, 2017 at 04:12:27PM -0800, Florian Fainelli wrote:
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> http://github.com/Broadcom/stblinux.git tags/arm-soc/for-4.16/drivers
>
> for you to fetch changes up to f780429adfbc222a4d8a227a2a550ba627c7338b:
>
> soc: brcmstb: biuctrl: Move to early_initcall (2017-12-20 17:37:44 -0800)
>
> ----------------------------------------------------------------
> This pull request contains Broadcom ARM/ARM64 based SoCs drivers changes for
> 4.16, please pull the following:
>
> - Arnd provides an update to the Raspberry Pi firmware interface and uses time64_t to
> print the time to make it more future proof
>
> - Florian provides a set of updates to make the Broadcom STB Bus Interface Unit code
> work on newer ARM64-based chips, as well as perform the correct interface tuning
> for these chips to reach the expected performance
>
> ----------------------------------------------------------------
> Arnd Bergmann (1):
> firmware: raspberrypi: print time using time64_t
>
> Florian Fainelli (10):
> Merge tag 'bcm2835-drivers-next-2017-12-19' into drivers/next
> dt-bindings: arm: Add entry for Broadcom Brahma-B53
> dt-bindings: arm: brcmstb: Correct BIUCTRL node documentation
> soc: brcmstb: Make CPU credit offset more parameterized
> soc: brcmstb: Correct CPU_CREDIT_REG offset for Brahma-B53 CPUs
> soc: brcmstb: biuctrl: Prepare for saving/restoring other registers
> soc: brcmstb: biuctrl: Wire-up new registers
> soc: brcmstb: biuctrl: Fine tune B53 MCP interface settings
> soc: brcmstb: Split initialization
> soc: brcmstb: biuctrl: Move to early_initcall
Merged, thanks.
Btw, you're sort of bare on signatures for your pgp key. You should try
to get at least me or Arnd to sign it at some point, hopefully we'll
overlap at conferences sometime. I've probably already offered once,
but seems I didn't actually upload my signature when I did it.
-Olof
^ permalink raw reply
* [GIT PULL v2] arm64: dts: hisilicon dts updates for v4.16
From: Olof Johansson @ 2018-01-05 6:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5A45604E.4050801@hisilicon.com>
On Thu, Dec 28, 2017 at 09:21:18PM +0000, Wei Xu wrote:
> Hi Arnd, Hi Olof, Hi Kevin,
>
> Please help to pull the following changes.
> Thanks!
>
> Best Regards,
> Wei
>
> ---
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> git://github.com/hisilicon/linux-hisi.git tags/hisi-arm64-dt-for-4.16-v2
>
> for you to fetch changes up to 9a9760dede5c71e04b17b2ede594ee7148fd36e2:
>
> arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information (2017-12-22 09:11:42 +0000)
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] arm: actions: dt for v4.16 #1
From: Olof Johansson @ 2018-01-05 6:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222102107.5661-1-afaerber@suse.de>
On Fri, Dec 22, 2017 at 11:21:05AM +0100, Andreas F?rber wrote:
> Hi Olof and Arnd,
>
> Here's my dt pull for Actions Semi.
> This adds one new S500 based board, which I already updated to new SPDX style.
> A second pull will follow after I've converted the existing boards.
>
> Regards,
> Andreas
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions.git tags/actions-arm-dt-for-4.16
>
> for you to fetch changes up to 271a70da383cf69f32742d9e2d01a7b16d04d60c:
>
> arm: dts: owl-s500: Add Sparky (2017-12-22 10:53:52 +0100)
>
> ----------------------------------------------------------------
> Actions Semi arm based SoC DT for v4.16
>
> This adds a DT for the Allo.com Sparky SBC.
>
> ----------------------------------------------------------------
> Andreas F?rber (3):
> dt-bindings: Add vendor prefix for Allo.com
> dt-bindings: arm: actions: Add Sparky
> arm: dts: owl-s500: Add Sparky
Merged.
Tiny nit: For 32-bit, we use ARM: as prefix (and arm64: for 64-bit).
Yes, it's confusing. :)
-Olof
^ permalink raw reply
* [GIT PULL] arm: actions: dt64 for v4.16 #1
From: Olof Johansson @ 2018-01-05 6:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222102107.5661-2-afaerber@suse.de>
On Fri, Dec 22, 2017 at 11:21:06AM +0100, Andreas F?rber wrote:
> Hi Olof and Arnd,
>
> Here's my dt64 pull for Actions Semi.
> This adds S700 and the CubieBoard7. Timer binding will go via timer tree.
> A second pull will follow after I've converted S900 to new SPDX style.
>
> Regards,
> Andreas
>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions.git tags/actions-arm64-dt-for-4.16
>
> for you to fetch changes up to 0bea2a65387961efcb59794a9fb7f9a63c6eb722:
>
> arm64: dts: actions: Add S700 and CubieBoard7 (2017-12-22 10:52:54 +0100)
>
> ----------------------------------------------------------------
> Actions Semi arm64 based SoC DT for v4.16
>
> This adds S700 SoC and CubieBoard7.
>
> ----------------------------------------------------------------
> Andreas F?rber (3):
> dt-bindings: arm: actions: Add S700 and CubieBoard7
> dt-bindings: power: Add Actions Semi S700 SPS
> arm64: dts: actions: Add S700 and CubieBoard7
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] arm: actions: drivers for v4.16
From: Olof Johansson @ 2018-01-05 6:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222102107.5661-3-afaerber@suse.de>
On Fri, Dec 22, 2017 at 11:21:07AM +0100, Andreas F?rber wrote:
> Hi Olof and Arnd,
>
> Here's my drivers pull for Actions Semi.
> Timer changes are supposed to go via timer tree this time.
>
> Regards,
> Andreas
>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions.git tags/actions-drivers-for-4.16
>
> for you to fetch changes up to 3ad85b08f7789d51e6aad0f535296d1c31e319b9:
>
> soc: actions: sps: Add S700 (2017-11-27 23:11:01 +0100)
>
> ----------------------------------------------------------------
> Actions Semi SoC drivers for v4.16
>
> The SPS power domain driver is extended for S700 SoC.
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] Second Round of Renesas ARM64 Based SoC DT Updates for v4.16
From: Olof Johansson @ 2018-01-05 6:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513936760.git.horms+renesas@verge.net.au>
On Fri, Dec 22, 2017 at 11:29:20AM +0100, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these second round of Renesas ARM64 based SoC DT updates
> for v4.16.
>
> This pull request is based on the previous round of
> such requests, tagged as renesas-arm64-dt-for-v4.16,
> which you have already pulled.
>
>
> The following changes since commit 8aba250d7800702bbd2f6a91174e01b9a84ed2dd:
>
> arm64: dts: renesas: r8a77970: use SYSC power domain macros (2017-12-05 09:30:48 +0100)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-arm64-dt2-for-v4.16
>
> for you to fetch changes up to 68b2c029e6200933fa3f6c06c8e6de33e8c78c51:
>
> arm64: dts: renesas: salvator-common: enable usb3_peri0 (2017-12-21 10:22:12 +0100)
>
> ----------------------------------------------------------------
> Second Round of Renesas ARM64 Based SoC DT Updates for v4.16
>
> * Add usb3_phy node to r8a7795 (R-Car H3) and r8a7796 (R-Car M3-W) SoCs, and
> enable usb3_peri0 on salvator boards
>
> * Allow DTBs of boards of r8a7795 (R-Car H3) and r8a7796 SoCs to build
> without any warnings when compiled with W=1 using gcc-linaro-5.4.1-2017.05
> - Move nodes which have no reg property out of bus, they don't belong there
> - Add reg properties to dummy pciec[01] nodes
> - Also sort sub-nodes of root node to allow for easier maintenance
>
> * Add Add EthernetAVB PHY reset to r8a7795 (R-Car H3) and r8a7796 SoCs boards.
>
> Geert Uytterhoeven says "... add properties to describe the EthernetAVB
> PHY reset topology to the common Salvator-X/XS and ULCB DTS files, which
> solves two issues:
> 1. On Salvator-XS, the enable pin of the regulator providing PHY power
> is connected to PRESETn, and PSCI powers down the SoC during system
> suspend. Hence a PHY reset is needed to restore network
> functionality after system resume.
> 2. Linux should not rely on the boot loader having reset the PHY, but
> should reset the PHY during driver probe."
>
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] Renesas ARM Based SoC Defconfig Updates for v4.16
From: Olof Johansson @ 2018-01-05 6:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513935930.git.horms+renesas@verge.net.au>
On Fri, Dec 22, 2017 at 11:29:33AM +0100, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these Renesas ARM based SoC defconfig updates for v4.16.
>
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-defconfig-for-v4.16
>
> for you to fetch changes up to 1943cbd3b39ee3310494d5b531a906e836bb9f7f:
>
> ARM: shmobile: defconfig: Enable PWM (2017-12-20 09:29:49 +0100)
>
> ----------------------------------------------------------------
> Renesas ARM Based SoC Defconfig Updates for v4.16
>
> shmobile_defconfig:
> * Enable PWM timers, which are present on R-Car and RZ/G1 platforms,
> as a built-in
> * Enable SGTL5000 audio codec, which is present on the he iWave RZ/G1M Q7
> carrier board, as a built-in
>
> multi_v7_defconfig:
> * Enable PWM timers, which are present on R-Car and RZ/G1 platforms,
> as a module
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] Second Round of Renesas ARM Based SoC DT Updates for v4.16
From: Olof Johansson @ 2018-01-05 6:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513938145.git.horms+renesas@verge.net.au>
On Fri, Dec 22, 2017 at 11:30:10AM +0100, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these second round of Renesas ARM based SoC DT updates for
> v4.16.
>
> This pull request is based on the previous round of
> such requests, tagged as renesas-dt-for-v4.16,
> which you have already pulled.
>
>
> The following changes since commit 7f32eddb81ecc06131a643babe2d0f961fbd7f08:
>
> ARM: dts: alt: Convert to named i2c-gpio bindings (2017-12-04 09:34:53 +0100)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-dt2-for-v4.16
>
> for you to fetch changes up to 5b062010675b3d74c9a6c6896e2becf932a4ca74:
>
> ARM: dts: r8a7745: Add missing clock for secondary CA7 CPU core (2017-12-22 09:24:00 +0100)
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] Second Round of Renesas ARM Based SoC Updates for v4.16
From: Olof Johansson @ 2018-01-05 6:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513936182.git.horms+renesas@verge.net.au>
On Fri, Dec 22, 2017 at 11:30:37AM +0100, Simon Horman wrote:
> Hi Olof, Hi Kevin, Hi Arnd,
>
> Please consider these second round of Renesas ARM based SoC updates for v4.16.
>
> This pull request is based on the previous round of
> such requests, tagged as renesas-soc-for-v4.16,
> which I have already sent a pull-request for.
>
>
> The following changes since commit 90f0d2b344313a8a4c366ef60d0df33008d2be84:
>
> soc: renesas: Identify R-Car M3-W ES1.1 (2017-11-27 11:40:57 +0100)
>
> are available in the git repository at:
>
> https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git tags/renesas-soc2-for-v4.16
>
> for you to fetch changes up to 91c719f5ec6671f7b63762d78897af5583dd7693:
>
> soc: renesas: rcar-sysc: Keep wakeup sources active during system suspend (2017-12-20 11:16:05 +0100)
>
> ----------------------------------------------------------------
> Second Round of Renesas ARM Based SoC Updates for v4.16
>
> * rcar-sysc: Keep wakeup sources active during system suspend
>
> Geert Uytterhoeven says "If an R-Car SYSC slave device is part of the
> CPG/MSTP or CPG/MSSR Clock Domain and to be used as a wakeup source, it
> must be kept active during system suspend.
>
> Currently this is handled in device-specific drivers by explicitly
> increasing the use count of the module clock when the device is
> configured as a wakeup source. However, the proper way to prevent the
> device from being stopped is to inform this requirement to the genpd
> core, by setting the GENPD_FLAG_ACTIVE_WAKEUP flag.
>
> Note that this will only affect devices configured as wakeup sources."
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] arm: actions: dt for v4.16 #1
From: Andreas Färber @ 2018-01-05 6:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180105063729.ttkwbct2smxx5x3z@localhost>
Am 05.01.2018 um 07:37 schrieb Olof Johansson:
> On Fri, Dec 22, 2017 at 11:21:05AM +0100, Andreas F?rber wrote:
>> Hi Olof and Arnd,
>>
>> Here's my dt pull for Actions Semi.
>> This adds one new S500 based board, which I already updated to new SPDX style.
>> A second pull will follow after I've converted the existing boards.
>>
>> Regards,
>> Andreas
>>
>> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>>
>> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>>
>> are available in the git repository at:
>>
>> git://git.kernel.org/pub/scm/linux/kernel/git/afaerber/linux-actions.git tags/actions-arm-dt-for-4.16
>>
>> for you to fetch changes up to 271a70da383cf69f32742d9e2d01a7b16d04d60c:
>>
>> arm: dts: owl-s500: Add Sparky (2017-12-22 10:53:52 +0100)
>>
>> ----------------------------------------------------------------
>> Actions Semi arm based SoC DT for v4.16
>>
>> This adds a DT for the Allo.com Sparky SBC.
>>
>> ----------------------------------------------------------------
>> Andreas F?rber (3):
>> dt-bindings: Add vendor prefix for Allo.com
>> dt-bindings: arm: actions: Add Sparky
>> arm: dts: owl-s500: Add Sparky
>
> Merged.
Thanks!
> Tiny nit: For 32-bit, we use ARM: as prefix (and arm64: for 64-bit).
> Yes, it's confusing. :)
It's not confusing, it's just that Arm switched from ARM to arm/Arm, so
I started adjusting my scripts. I can revert that of course.
Cheers,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 N?rnberg, Germany
GF: Felix Imend?rffer, Jane Smithard, Graham Norton
HRB 21284 (AG N?rnberg)
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt for v4.16 (#1)
From: Olof Johansson @ 2018-01-05 6:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87r2rndoip.fsf@free-electrons.com>
On Fri, Dec 22, 2017 at 11:51:10AM +0100, Gregory CLEMENT wrote:
> Hi,
>
> Here is the first pull request for dt for mvebu for v4.16.
>
> Gregory
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the Git repository at:
>
> git://git.infradead.org/linux-mvebu.git tags/mvebu-dt-4.16-1
>
> for you to fetch changes up to cea96bf1836f22d2586f650a0299bd37abf2d42e:
>
> arm: kirkwood: dts: Use lower case for bindings notation (2017-12-18 17:44:48 +0100)
>
> ----------------------------------------------------------------
> mvebu dt for 4.16 (part 1)
>
> Fix potential dtc warnings on kirkwoods files
> Declare a new pin (RB) usbale for NAND controller on Armada 38x
Merged, thanks.
-Olof
^ permalink raw reply
* [GIT PULL] ARM: mvebu: dt64 for v4.16 (#1)
From: Olof Johansson @ 2018-01-05 6:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <87po77doi0.fsf@free-electrons.com>
On Fri, Dec 22, 2017 at 11:51:35AM +0100, Gregory CLEMENT wrote:
> Hi,
>
> Here is the first pull request for dt64 for mvebu for v4.16.
>
> Gregory
>
> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>
> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>
> are available in the Git repository at:
>
> git://git.infradead.org/linux-mvebu.git tags/mvebu-dt64-4.16-1
>
> for you to fetch changes up to 4cada03801992d09ccceaf5f462e9dadb75a9613:
>
> ARM64: dts: marvell: Add thermal support for A7K/A8K (2017-12-18 17:13:17 +0100)
>
> ----------------------------------------------------------------
> mvebu dt64 for 4.16 (part 1)
>
> Add the NAND support on the Marvell 8040-DB board
> Add the thermal support for Martvell A7K/A8K Socs
> Add nodes allowing cpufreq support on Aramda 3700 SoCs
Merged, thanks.
-Olof
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox