* [PATCH v7 3/5] arm64: dts: add ufs dts node
From: Li Wei @ 2018-01-06 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106095117.67907-1-liwei213@huawei.com>
arm64: dts: add ufs node for Hisilicon.
Signed-off-by: Li Wei <liwei213@huawei.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index ab0b95ba5ae5..3c57346366ad 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -904,6 +904,26 @@
reset-gpios = <&gpio11 1 0 >;
};
+ /* UFS */
+ ufs: ufs at ff3b0000 {
+ compatible = "hisilicon,hi3660-ufs", "jedec,ufs-1.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3b0000 0x0 0x1000>,
+ <0x0 0xff3b1000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ /* offset: 0x84; bit: 7 */
+ resets = <&crg_rst 0x84 12>,
+ <&crg_rst 0x84 7>;
+ reset-names = "rst", "assert";
+ };
+
/* SD */
dwmmc1: dwmmc1 at ff37f000 {
#address-cells = <1>;
--
2.15.0
^ permalink raw reply related
* [PATCH v7 4/5] arm64: defconfig: enable configs for Hisilicon ufs
From: Li Wei @ 2018-01-06 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106095117.67907-1-liwei213@huawei.com>
This enable configs for Hisilicon Hixxxx UFS driver.
Signed-off-by: Li Wei <liwei213@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/configs/defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 6356c6da34ea..fa6f921eed86 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -174,6 +174,9 @@ CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_SAS_ATA=y
CONFIG_SCSI_HISI_SAS=y
CONFIG_SCSI_HISI_SAS_PCI=y
+CONFIG_SCSI_UFSHCD=y
+CONFIG_SCSI_UFSHCD_PLATFORM=y
+CONFIG_SCSI_UFS_HISI=y
CONFIG_ATA=y
CONFIG_SATA_AHCI=y
CONFIG_SATA_AHCI_PLATFORM=y
--
2.15.0
^ permalink raw reply related
* [PATCH v7 5/5] arm64: defconfig: enable f2fs and squashfs
From: Li Wei @ 2018-01-06 9:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106095117.67907-1-liwei213@huawei.com>
Partitions in HiKey960 are formatted as f2fs and squashfs.
f2fs is for userdata; squashfs is for system. Both partitions are required
by Android.
Signed-off-by: Li Wei <liwei213@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
---
arch/arm64/configs/defconfig | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index fa6f921eed86..7be4ee2ac680 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -572,6 +572,7 @@ CONFIG_ACPI_APEI_GHES=y
CONFIG_ACPI_APEI_PCIEAER=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
+CONFIG_F2FS_FS=y
CONFIG_EXT4_FS_POSIX_ACL=y
CONFIG_BTRFS_FS=m
CONFIG_BTRFS_FS_POSIX_ACL=y
@@ -587,6 +588,13 @@ CONFIG_HUGETLBFS=y
CONFIG_CONFIGFS_FS=y
CONFIG_EFIVAR_FS=y
CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_FILE_DIRECT=y
+CONFIG_SQUASHFS_DECOMP_MULTI_PERCPU=y
+CONFIG_SQUASHFS_XATTR=y
+CONFIG_SQUASHFS_LZ4=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_SQUASHFS_4K_DEVBLK_SIZE=y
CONFIG_NFS_FS=y
CONFIG_NFS_V4=y
CONFIG_NFS_V4_1=y
--
2.15.0
^ permalink raw reply related
* [PATCH V2 1/2] ARM: dts: imx6ul: add 696MHz operating point
From: Anson Huang @ 2018-01-06 10:42 UTC (permalink / raw)
To: linux-arm-kernel
Add 696MHz operating point according to datasheet
(Rev. 0, 12/2015).
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index d5181f8..963e169 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -68,12 +68,14 @@
clock-latency = <61036>; /* two CLK32 periods */
operating-points = <
/* kHz uV */
+ 696000 1275000
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
/* KHz uV */
+ 696000 1275000
528000 1175000
396000 1175000
198000 1175000
--
1.9.1
^ permalink raw reply related
* [PATCH V2 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul
From: Anson Huang @ 2018-01-06 10:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515235360-1628-1-git-send-email-Anson.Huang@nxp.com>
Add 696MHz operating point for i.MX6UL, only for those
parts with speed grading fuse set to 2b'10 supports
696MHz operating point, so, speed grading check is also
added for i.MX6UL in this patch, the clock tree for each
operating point are as below:
696MHz:
pll1 696000000
pll1_bypass 696000000
pll1_sys 696000000
pll1_sw 696000000
arm 696000000
528MHz:
pll2 528000000
pll2_bypass 528000000
pll2_bus 528000000
ca7_secondary_sel 528000000
step 528000000
pll1_sw 528000000
arm 528000000
396MHz:
pll2_pfd2_396m 396000000
ca7_secondary_sel 396000000
step 396000000
pll1_sw 396000000
arm 396000000
198MHz:
pll2_pfd2_396m 396000000
ca7_secondary_sel 396000000
step 396000000
pll1_sw 396000000
arm 198000000
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
---
changes since v1:
redo the patch based on linux-next-pm.
drivers/cpufreq/imx6q-cpufreq.c | 46 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 8bfb077..741f22e 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -136,6 +136,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
clks[PLL2_PFD2_396M].clk);
clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
+ if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
+ clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
+ clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
+ }
} else {
clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
@@ -260,6 +264,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
of_node_put(np);
}
+#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
+
+static void imx6ul_opp_check_speed_grading(struct device *dev)
+{
+ struct device_node *np;
+ void __iomem *base;
+ u32 val;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+ if (!np)
+ return;
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ dev_err(dev, "failed to map ocotp\n");
+ goto put_node;
+ }
+
+ /*
+ * Speed GRADING[1:0] defines the max speed of ARM:
+ * 2b'00: Reserved;
+ * 2b'01: 528000000Hz;
+ * 2b'10: 696000000Hz;
+ * 2b'11: Reserved;
+ * We need to set the max speed of ARM according to fuse map.
+ */
+ val = readl_relaxed(base + OCOTP_CFG3);
+ val >>= OCOTP_CFG3_SPEED_SHIFT;
+ val &= 0x3;
+ if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
+ if (dev_pm_opp_disable(dev, 696000000))
+ dev_warn(dev, "failed to disable 696MHz OPP\n");
+ iounmap(base);
+put_node:
+ of_node_put(np);
+}
+
static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
struct device_node *np;
@@ -314,7 +355,10 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
goto put_reg;
}
- imx6q_opp_check_speed_grading(cpu_dev);
+ if (of_machine_is_compatible("fsl,imx6ul"))
+ imx6ul_opp_check_speed_grading(cpu_dev);
+ else
+ imx6q_opp_check_speed_grading(cpu_dev);
/* Because we have added the OPPs here, we must free them */
free_opp = true;
--
1.9.1
^ permalink raw reply related
* [PATCH 2/7] ARM: dts: imx6ul: update i.MX 6UltraLite iomux headers
From: Stefan Agner @ 2018-01-06 10:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180105164505.uzv7nu3r6awuyxzu@rob-hp-laptop>
On 2018-01-05 17:45, Rob Herring wrote:
> On Tue, Jan 02, 2018 at 05:42:18PM +0100, Stefan Agner wrote:
>> From: Fugang Duan <fugang.duan@nxp.com>
>>
>> Update i.MX 6UltraLite IOMUXC pin defines.
>
> That's obvious reading the diff. The commit message should tell me why.
> They were wrong?
I guess pretty much :-)
What I can tell from the change itself it seems that daisy chain
configurations were missing. And some additional pinmux options. Will
update the commit message accordingly.
--
Stefan
>
>>
>> Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
^ permalink raw reply
* [PATCH] pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
From: Stefan Agner @ 2018-01-06 11:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdYKiLeRZdBCWie+UGK=96FicXXmWvGUvwNFD2ZWOUx7Rw@mail.gmail.com>
On 2018-01-03 09:09, Linus Walleij wrote:
> On Tue, Jan 2, 2018 at 5:40 PM, Stefan Agner <stefan@agner.ch> wrote:
>
>> From: Bai Ping <ping.bai@nxp.com>
>>
>> On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
>> are available in a separate IOMUXC_SNVS module. Add support for the
>> IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
>>
>> Signed-off-by: Bai Ping <ping.bai@nxp.com>
>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>
> So 6 unsigned long 32 bit is succeeded by 6 unsigned long long, 64 bit?
>
> Someone is having fun naming these platforms I see.
Hehe, yeah definitely. At least they use proper type suffixes ;-)
>
>> Required properties:
>> -- compatible: "fsl,imx6ul-iomuxc"
>> +- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
>> + "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
>
> Pretty uncontroversial change but still nice to give the DT people a chance
> to ACK it.
>
>> static int imx6ul_pinctrl_probe(struct platform_device *pdev)
>> {
>> - return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info);
>> + const struct of_device_id *match;
>> + struct imx_pinctrl_soc_info *pinctrl_info;
>> +
>> + match = of_match_device(imx6ul_pinctrl_of_match, &pdev->dev);
>> +
>> + if (!match)
>> + return -ENODEV;
>> +
>> + pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;
>
> 1. Do not use a cast on void * pointers.
>
> 2. Use this function:
> extern const void *of_device_get_match_data(const struct device *dev);
>
> From <linux/of_device.h>
Ok. We use the same code in pinmux-imx7d.c, will send a patch to
simplify that too.
--
Stefan
^ permalink raw reply
* [PATCH 7/7] arm64: allwinner: h6: add support for Pine H64 board
From: Icenowy Zheng @ 2018-01-06 11:53 UTC (permalink / raw)
To: linux-arm-kernel
Pine H64 is an Allwinner H6-based SBC from Pine64, with the following
features:
- 1GiB/2GiB/4GiB LPDDR3 DRAM (in 4GiB situation only 3GiB is
accessible)
- AXP805 PMIC
- Raspberry-Pi-compatible GPIO header, "Euler" GPIO header (not
compatible with the "Euler" on Pine A64) and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
arch/arm64/boot/dts/allwinner/Makefile | 1 +
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 66 ++++++++++++++++++++++
2 files changed, 67 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
index f505227b0250..addf245226f6 100644
--- a/arch/arm64/boot/dts/allwinner/Makefile
+++ b/arch/arm64/boot/dts/allwinner/Makefile
@@ -10,3 +10,4 @@ dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-prime.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-zero-plus2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo2.dtb
dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-nanopi-neo-plus2.dtb
+dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h6-pine-h64.dtb
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
new file mode 100644
index 000000000000..0d7b294c8aa9
--- /dev/null
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2017 Icenowy Zheng <icenowy@aosc.io>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "sun50i-h6.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Pine H64";
+ compatible = "pine64,pine-h64", "allwinner,sun50i-h6";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_ph_pins>;
+ status = "okay";
+};
--
2.14.2
^ permalink raw reply related
* [PATCH 0/3] ARM branch predictor hardening
From: Marc Zyngier @ 2018-01-06 12:09 UTC (permalink / raw)
To: linux-arm-kernel
This small series implements some basic BP hardening by invalidating
the BTB on CPUs that are known to be susceptible to aliasing attacks.
These patches are closely modelled against what we do on arm64,
although simpler as we can rely on an architected instruction to
perform the invalidation.
The first patch reuses the Cortex-A8 BTB invalidation in switch_mm and
generalises it to be used on all affected CPUs. The second perform the
same invalidation on fatal signal delivery. The last one nukes it on
guest exit, and results in some major surgery (kudos to Dimitris
Papastamos who came up with the magic vector decoding sequence).
Note that that M-class CPUs are not affected and for R-class cores,
the mitigation doesn't make much sense since we do not enforce
user/kernel isolation.
Marc Zyngier (3):
arm: Add BTB invalidation on switch_mm for Cortex-A9, A12, A15 and A17
arm: Invalidate BTB on fatal signal for Cortex A8, A9, A12, A15 and
A17
arm: KVM: Invalidate BTB on guest exit
arch/arm/include/asm/cp15.h | 2 ++
arch/arm/kvm/hyp/hyp-entry.S | 74 +++++++++++++++++++++++++++++++++++++-------
arch/arm/mm/fault.c | 11 +++++++
arch/arm/mm/proc-v7-2level.S | 4 +--
arch/arm/mm/proc-v7-3level.S | 6 ++++
arch/arm/mm/proc-v7.S | 32 +++++++++----------
6 files changed, 100 insertions(+), 29 deletions(-)
--
2.14.2
^ permalink raw reply
* [PATCH 1/3] arm: Add BTB invalidation on switch_mm for Cortex-A9, A12, A15 and A17
From: Marc Zyngier @ 2018-01-06 12:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106120907.26701-1-marc.zyngier@arm.com>
In order to avoid aliasing attacks against the branch predictor,
some implementations require to invalidate the BTB when switching
from one user context to another.
For this, we reuse the existing implementation for Cortex-A8, and
apply it to A9, A12, A15, and A17.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm/mm/proc-v7-2level.S | 4 ++--
arch/arm/mm/proc-v7-3level.S | 6 ++++++
arch/arm/mm/proc-v7.S | 32 ++++++++++++++++----------------
3 files changed, 24 insertions(+), 18 deletions(-)
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index c6141a5435c3..0422e58b74e8 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -41,7 +41,7 @@
* even on Cortex-A8 revisions not affected by 430973.
* If IBE is not set, the flush BTAC/BTB won't do anything.
*/
-ENTRY(cpu_ca8_switch_mm)
+ENTRY(cpu_v7_btbinv_switch_mm)
#ifdef CONFIG_MMU
mov r2, #0
mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
@@ -66,7 +66,7 @@ ENTRY(cpu_v7_switch_mm)
#endif
bx lr
ENDPROC(cpu_v7_switch_mm)
-ENDPROC(cpu_ca8_switch_mm)
+ENDPROC(cpu_v7_btbinv_switch_mm)
/*
* cpu_v7_set_pte_ext(ptep, pte)
diff --git a/arch/arm/mm/proc-v7-3level.S b/arch/arm/mm/proc-v7-3level.S
index 7d16bbc4102b..934272e1fa08 100644
--- a/arch/arm/mm/proc-v7-3level.S
+++ b/arch/arm/mm/proc-v7-3level.S
@@ -54,6 +54,11 @@
* Set the translation table base pointer to be pgd_phys (physical address of
* the new TTB).
*/
+ENTRY(cpu_v7_btbinv_switch_mm)
+#ifdef CONFIG_MMU
+ mov r2, #0
+ mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB
+#endif
ENTRY(cpu_v7_switch_mm)
#ifdef CONFIG_MMU
mmid r2, r2
@@ -64,6 +69,7 @@ ENTRY(cpu_v7_switch_mm)
#endif
ret lr
ENDPROC(cpu_v7_switch_mm)
+ENDPROC(cpu_v7_btbinv_switch_mm)
#ifdef __ARMEB__
#define rl r3
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 01d64c0b2563..23fa537101ab 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -159,18 +159,18 @@ ENDPROC(cpu_v7_do_resume)
#endif
/*
- * Cortex-A8
+ * Cortex-A8/A12/A15/A17 that require a BTB invalidation on switch_mm
*/
- globl_equ cpu_ca8_proc_init, cpu_v7_proc_init
- globl_equ cpu_ca8_proc_fin, cpu_v7_proc_fin
- globl_equ cpu_ca8_reset, cpu_v7_reset
- globl_equ cpu_ca8_do_idle, cpu_v7_do_idle
- globl_equ cpu_ca8_dcache_clean_area, cpu_v7_dcache_clean_area
- globl_equ cpu_ca8_set_pte_ext, cpu_v7_set_pte_ext
- globl_equ cpu_ca8_suspend_size, cpu_v7_suspend_size
+ globl_equ cpu_v7_btbinv_proc_init, cpu_v7_proc_init
+ globl_equ cpu_v7_btbinv_proc_fin, cpu_v7_proc_fin
+ globl_equ cpu_v7_btbinv_reset, cpu_v7_reset
+ globl_equ cpu_v7_btbinv_do_idle, cpu_v7_do_idle
+ globl_equ cpu_v7_btbinv_dcache_clean_area, cpu_v7_dcache_clean_area
+ globl_equ cpu_v7_btbinv_set_pte_ext, cpu_v7_set_pte_ext
+ globl_equ cpu_v7_btbinv_suspend_size, cpu_v7_suspend_size
#ifdef CONFIG_ARM_CPU_SUSPEND
- globl_equ cpu_ca8_do_suspend, cpu_v7_do_suspend
- globl_equ cpu_ca8_do_resume, cpu_v7_do_resume
+ globl_equ cpu_v7_btbinv_do_suspend, cpu_v7_do_suspend
+ globl_equ cpu_v7_btbinv_do_resume, cpu_v7_do_resume
#endif
/*
@@ -181,7 +181,7 @@ ENDPROC(cpu_v7_do_resume)
globl_equ cpu_ca9mp_reset, cpu_v7_reset
globl_equ cpu_ca9mp_do_idle, cpu_v7_do_idle
globl_equ cpu_ca9mp_dcache_clean_area, cpu_v7_dcache_clean_area
- globl_equ cpu_ca9mp_switch_mm, cpu_v7_switch_mm
+ globl_equ cpu_ca9mp_switch_mm, cpu_v7_btbinv_switch_mm
globl_equ cpu_ca9mp_set_pte_ext, cpu_v7_set_pte_ext
.globl cpu_ca9mp_suspend_size
.equ cpu_ca9mp_suspend_size, cpu_v7_suspend_size + 4 * 2
@@ -548,8 +548,8 @@ __v7_setup_stack:
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
+ define_processor_functions v7_btbinv, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#ifndef CONFIG_ARM_LPAE
- define_processor_functions ca8, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
define_processor_functions ca9mp, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
#endif
#ifdef CONFIG_CPU_PJ4B
@@ -614,7 +614,7 @@ __v7_ca9mp_proc_info:
__v7_ca8_proc_info:
.long 0x410fc080
.long 0xff0ffff0
- __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = ca8_processor_functions
+ __v7_proc __v7_ca8_proc_info, __v7_setup, proc_fns = v7_btbinv_processor_functions
.size __v7_ca8_proc_info, . - __v7_ca8_proc_info
#endif /* CONFIG_ARM_LPAE */
@@ -658,7 +658,7 @@ __v7_ca7mp_proc_info:
__v7_ca12mp_proc_info:
.long 0x410fc0d0
.long 0xff0ffff0
- __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup
+ __v7_proc __v7_ca12mp_proc_info, __v7_ca12mp_setup, proc_fns = v7_btbinv_processor_functions
.size __v7_ca12mp_proc_info, . - __v7_ca12mp_proc_info
/*
@@ -668,7 +668,7 @@ __v7_ca12mp_proc_info:
__v7_ca15mp_proc_info:
.long 0x410fc0f0
.long 0xff0ffff0
- __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup
+ __v7_proc __v7_ca15mp_proc_info, __v7_ca15mp_setup, proc_fns = v7_btbinv_processor_functions
.size __v7_ca15mp_proc_info, . - __v7_ca15mp_proc_info
/*
@@ -688,7 +688,7 @@ __v7_b15mp_proc_info:
__v7_ca17mp_proc_info:
.long 0x410fc0e0
.long 0xff0ffff0
- __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup
+ __v7_proc __v7_ca17mp_proc_info, __v7_ca17mp_setup, proc_fns = v7_btbinv_processor_functions
.size __v7_ca17mp_proc_info, . - __v7_ca17mp_proc_info
/*
--
2.14.2
^ permalink raw reply related
* [PATCH 2/3] arm: Invalidate BTB on fatal signal for Cortex A8, A9, A12, A15 and A17
From: Marc Zyngier @ 2018-01-06 12:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106120907.26701-1-marc.zyngier@arm.com>
In order to prevent aliasing attacks on the branch predictor,
invalidate the BTB on CPUs that are known to be affected.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm/include/asm/cp15.h | 2 ++
arch/arm/mm/fault.c | 11 +++++++++++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/include/asm/cp15.h b/arch/arm/include/asm/cp15.h
index 4c9fa72b59f5..9e900ae855aa 100644
--- a/arch/arm/include/asm/cp15.h
+++ b/arch/arm/include/asm/cp15.h
@@ -65,6 +65,8 @@
#define __write_sysreg(v, r, w, c, t) asm volatile(w " " c : : "r" ((t)(v)))
#define write_sysreg(v, ...) __write_sysreg(v, __VA_ARGS__)
+#define BPIALL __ACCESS_CP15(c7, 0, c5, 6)
+
extern unsigned long cr_alignment; /* defined in entry-armv.S */
static inline unsigned long get_cr(void)
diff --git a/arch/arm/mm/fault.c b/arch/arm/mm/fault.c
index 42f585379e19..62da5f99eda0 100644
--- a/arch/arm/mm/fault.c
+++ b/arch/arm/mm/fault.c
@@ -21,6 +21,7 @@
#include <linux/highmem.h>
#include <linux/perf_event.h>
+#include <asm/cp15.h>
#include <asm/exception.h>
#include <asm/pgtable.h>
#include <asm/system_misc.h>
@@ -181,6 +182,16 @@ __do_user_fault(struct task_struct *tsk, unsigned long addr,
si.si_errno = 0;
si.si_code = code;
si.si_addr = (void __user *)addr;
+
+ switch(read_cpuid_part()) {
+ case ARM_CPU_PART_CORTEX_A8:
+ case ARM_CPU_PART_CORTEX_A9:
+ case ARM_CPU_PART_CORTEX_A12:
+ case ARM_CPU_PART_CORTEX_A15:
+ case ARM_CPU_PART_CORTEX_A17:
+ write_sysreg(0, BPIALL);
+ break;
+ }
force_sig_info(sig, &si, tsk);
}
--
2.14.2
^ permalink raw reply related
* [PATCH 3/3] arm: KVM: Invalidate BTB on guest exit
From: Marc Zyngier @ 2018-01-06 12:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106120907.26701-1-marc.zyngier@arm.com>
In order to avoid aliasing attacks against the branch predictor,
let's invalidate the BTB on guest exit. This is made complicated
by the fact that we cannot take a branch before invalidating the
BTB.
Another thing is that we perform the invalidation on all
implementations, no matter if they are affected or not.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
arch/arm/kvm/hyp/hyp-entry.S | 74 +++++++++++++++++++++++++++++++++++++-------
1 file changed, 63 insertions(+), 11 deletions(-)
diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S
index 95a2faefc070..aa8adfa64ec9 100644
--- a/arch/arm/kvm/hyp/hyp-entry.S
+++ b/arch/arm/kvm/hyp/hyp-entry.S
@@ -61,15 +61,60 @@
__kvm_hyp_vector:
.global __kvm_hyp_vector
- @ Hyp-mode exception vector
- W(b) hyp_reset
- W(b) hyp_undef
- W(b) hyp_svc
- W(b) hyp_pabt
- W(b) hyp_dabt
- W(b) hyp_hvc
- W(b) hyp_irq
- W(b) hyp_fiq
+ /*
+ * We encode the exception entry in the bottom 3 bits of
+ * SP, and we have to guarantee to be 8 bytes aligned.
+ */
+ add sp, sp, #1 /* Reset 7 */
+ add sp, sp, #1 /* Undef 6 */
+ add sp, sp, #1 /* Syscall 5 */
+ add sp, sp, #1 /* Prefetch abort 4 */
+ add sp, sp, #1 /* Data abort 3 */
+ add sp, sp, #1 /* HVC 2 */
+ add sp, sp, #1 /* IRQ 1 */
+ add sp, sp, #1 /* FIQ 0 */
+
+ sub sp, sp, #1
+
+ mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
+ isb
+
+ /*
+ * As we cannot use any temporary registers and cannot
+ * clobber SP, we can decode the exception entry using
+ * an unrolled binary search.
+ */
+ tst sp, #4
+ bne 1f
+
+ tst sp, #2
+ bne 3f
+
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne hyp_irq
+ b hyp_irq
+
+1:
+ tst sp, #2
+ bne 2f
+
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne hyp_svc
+ b hyp_pabt
+
+2:
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne hyp_reset
+ b hyp_undef
+
+3:
+ tst sp, #1
+ bic sp, sp, #0x7
+ bne hyp_dabt
+ b hyp_hvc
.macro invalid_vector label, cause
.align
@@ -149,7 +194,14 @@ hyp_hvc:
bx ip
1:
- push {lr}
+ /*
+ * Pushing r2 here is just a way of keeping the stack aligned to
+ * 8 bytes on any path that can trigger a HYP exception. Here,
+ * we may well be about to jump into the guest, and the guest
+ * exit would otherwise be badly decoded by our fancy
+ * "decode-exception-without-a-branch" code...
+ */
+ push {r2, lr}
mov lr, r0
mov r0, r1
@@ -159,7 +211,7 @@ hyp_hvc:
THUMB( orr lr, #1)
blx lr @ Call the HYP function
- pop {lr}
+ pop {r2, lr}
eret
guest_trap:
--
2.14.2
^ permalink raw reply related
* [PATCH] pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
From: Stefan Agner @ 2018-01-06 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <b6d157d12f87caa1ad2ab7c500aa17b2@agner.ch>
On 2018-01-06 12:14, Stefan Agner wrote:
> On 2018-01-03 09:09, Linus Walleij wrote:
>> On Tue, Jan 2, 2018 at 5:40 PM, Stefan Agner <stefan@agner.ch> wrote:
>>
>>> From: Bai Ping <ping.bai@nxp.com>
>>>
>>> On i.MX 6ULL, the BOOT_MODEx and TAMPERx pin MUX and CTRL registers
>>> are available in a separate IOMUXC_SNVS module. Add support for the
>>> IOMUXC_SNVS module to the i.MX 6UL pinctrl driver.
>>>
>>> Signed-off-by: Bai Ping <ping.bai@nxp.com>
>>> Signed-off-by: Stefan Agner <stefan@agner.ch>
>>
>> So 6 unsigned long 32 bit is succeeded by 6 unsigned long long, 64 bit?
>>
>> Someone is having fun naming these platforms I see.
>
> Hehe, yeah definitely. At least they use proper type suffixes ;-)
>
>>
>>> Required properties:
>>> -- compatible: "fsl,imx6ul-iomuxc"
>>> +- compatible: "fsl,imx6ul-iomuxc" for main IOMUX controller or
>>> + "fsl,imx6ull-iomuxc-snvs" for i.MX 6ULL's SNVS IOMUX controller.
>>
>> Pretty uncontroversial change but still nice to give the DT people a chance
>> to ACK it.
>>
>>> static int imx6ul_pinctrl_probe(struct platform_device *pdev)
>>> {
>>> - return imx_pinctrl_probe(pdev, &imx6ul_pinctrl_info);
>>> + const struct of_device_id *match;
>>> + struct imx_pinctrl_soc_info *pinctrl_info;
>>> +
>>> + match = of_match_device(imx6ul_pinctrl_of_match, &pdev->dev);
>>> +
>>> + if (!match)
>>> + return -ENODEV;
>>> +
>>> + pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;
>>
>> 1. Do not use a cast on void * pointers.
>>
>> 2. Use this function:
>> extern const void *of_device_get_match_data(const struct device *dev);
Just realized that imx_pinctrl_probe needs a non-const struct
imx_pinctrl_soc_info *...
Afaik, while casting to non-const struct pointers in imxXX_pinctrl_probe
is not nice but should be technically ok since it is a non-const
declaration. However, in pinmux-imx7d.c the struct imx_pinctrl_soc_info
declarations have even been constified with b3060044e495 ("pinctrl:
freescale: imx7d: make of_device_ids const"). That seems not ok!
I wonder how that even works under the light of
CONFIG_STRICT_KERNEL_RWX. In a quick test it seems to boot fine though,
as far as I can tell rodata are set to ro once boot completed... It
seems at that point the pinmux driver has been initialized completely
and does not write to the struct anymore.
How can we fix this properly? IMHO we should at least unconstify the
struct imx7d_pinctrl_info/imx7d_lpsr_pinctrl_info declarations in
pinctrl-imx7d.c...
--
Stefan
>>
>> From <linux/of_device.h>
>
> Ok. We use the same code in pinmux-imx7d.c, will send a patch to
> simplify that too.
>
> --
> Stefan
^ permalink raw reply
* [PATCH] iio: adc: stm32: fix scan of multiple channels with DMA
From: Jonathan Cameron @ 2018-01-06 12:50 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515162894-11637-1-git-send-email-fabrice.gasnier@st.com>
On Fri, 5 Jan 2018 15:34:54 +0100
Fabrice Gasnier <fabrice.gasnier@st.com> wrote:
> By default, watermark is set to '1'. Watermark is used to fine tune
> cyclic dma buffer period. In case watermark is left untouched (e.g. 1)
> and several channels are being scanned, buffer period is wrongly set
> (e.g. to 1 sample). As a consequence, data is never pushed to upper layer.
> Fix buffer period size, by taking scan channels number into account.
>
> Fixes: 2763ea0585c9 ("iio: adc: stm32: add optional dma support")
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Given where we are in the cycle I've applied this to the togreg
branch for the next merge window and marked it for stable.
This is probably the quickest way to get it in at this stage.
Thanks,
Jonathan
> ---
> drivers/iio/adc/stm32-adc.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
> index c9d96f9..cecf1e5 100644
> --- a/drivers/iio/adc/stm32-adc.c
> +++ b/drivers/iio/adc/stm32-adc.c
> @@ -1315,6 +1315,7 @@ static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
> {
> struct stm32_adc *adc = iio_priv(indio_dev);
> unsigned int watermark = STM32_DMA_BUFFER_SIZE / 2;
> + unsigned int rx_buf_sz = STM32_DMA_BUFFER_SIZE;
>
> /*
> * dma cyclic transfers are used, buffer is split into two periods.
> @@ -1323,7 +1324,7 @@ static int stm32_adc_set_watermark(struct iio_dev *indio_dev, unsigned int val)
> * - one buffer (period) driver can push with iio_trigger_poll().
> */
> watermark = min(watermark, val * (unsigned)(sizeof(u16)));
> - adc->rx_buf_sz = watermark * 2;
> + adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv);
>
> return 0;
> }
^ permalink raw reply
* [PATCH v2 01/11] arm64: use RET instruction for exiting the trampoline
From: Ard Biesheuvel @ 2018-01-06 13:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515157961-20963-2-git-send-email-will.deacon@arm.com>
On 5 January 2018 at 13:12, Will Deacon <will.deacon@arm.com> wrote:
> Speculation attacks against the entry trampoline can potentially resteer
> the speculative instruction stream through the indirect branch and into
> arbitrary gadgets within the kernel.
>
> This patch defends against these attacks by forcing a misprediction
> through the return stack: a dummy BL instruction loads an entry into
> the stack, so that the predicted program flow of the subsequent RET
> instruction is to a branch-to-self instruction which is finally resolved
> as a branch to the kernel vectors with speculation suppressed.
>
How safe is it to assume that every microarchitecture will behave as
expected here? Wouldn't it be safer in general not to rely on a memory
load for x30 in the first place? (see below) Or may the speculative
execution still branch anywhere even if the branch target is
guaranteed to be known by that time?
> Signed-off-by: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm64/kernel/entry.S | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
> index 031392ee5f47..71092ee09b6b 100644
> --- a/arch/arm64/kernel/entry.S
> +++ b/arch/arm64/kernel/entry.S
> @@ -1029,6 +1029,14 @@ alternative_else_nop_endif
> .if \regsize == 64
> msr tpidrro_el0, x30 // Restored in kernel_ventry
> .endif
> + /*
> + * Defend against branch aliasing attacks by pushing a dummy
> + * entry onto the return stack and using a RET instruction to
> + * entr the full-fat kernel vectors.
> + */
> + bl 2f
> + b .
> +2:
> tramp_map_kernel x30
> #ifdef CONFIG_RANDOMIZE_BASE
> adr x30, tramp_vectors + PAGE_SIZE
> @@ -1041,7 +1049,7 @@ alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
> msr vbar_el1, x30
> add x30, x30, #(1b - tramp_vectors)
> isb
> - br x30
> + ret
> .endm
>
> .macro tramp_exit, regsize = 64
> --
> 2.1.4
>
This uses Marc's callback alternative patching for the KASLR case, the
non-KASLR case just uses a plain movz/movk sequence to load the
address of vectors rather than a literal.
(apologies for the patch soup)
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 55d05dacd02e..e8a846335e8e 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -1031,17 +1031,19 @@ alternative_else_nop_endif
.endif
tramp_map_kernel x30
#ifdef CONFIG_RANDOMIZE_BASE
- adr x30, tramp_vectors + PAGE_SIZE
alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
- ldr x30, [x30]
+ b tramp_vectors + PAGE_SIZE + .Ltramp_stage2_size * (1b
- tramp_vectors - 0x400) / 0x80
#else
- ldr x30, =vectors
-#endif
+ movz x30, :abs_g3:vectors
+ movk x30, :abs_g2_nc:vectors
+ movk x30, :abs_g1_nc:vectors
+ movk x30, :abs_g0_nc:vectors
prfm plil1strm, [x30, #(1b - tramp_vectors)]
msr vbar_el1, x30
add x30, x30, #(1b - tramp_vectors)
isb
br x30
+#endif
.endm
.macro tramp_exit, regsize = 64
@@ -1080,12 +1082,25 @@ END(tramp_exit_compat)
.ltorg
.popsection // .entry.tramp.text
#ifdef CONFIG_RANDOMIZE_BASE
- .pushsection ".rodata", "a"
+ .pushsection ".text", "ax"
.align PAGE_SHIFT
.globl __entry_tramp_data_start
__entry_tramp_data_start:
- .quad vectors
- .popsection // .rodata
+ .irpc i, 01234567
+alternative_cb tramp_patch_vectors_address
+ movz x30, :abs_g3:0
+ movk x30, :abs_g2_nc:0
+ movk x30, :abs_g1_nc:0
+ movk x30, :abs_g0_nc:0
+alternative_cb_end
+ prfm plil1strm, [x30, #(0x400 + \i * 0x80)]
+ msr vbar_el1, x30
+ add x30, x30, 0x400 + \i * 0x80
+ isb
+ br x30
+ .endr
+ .set .Ltramp_stage2_size, (. - __entry_tramp_data_start) / 8
+ .popsection // .text
#endif /* CONFIG_RANDOMIZE_BASE */
#endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 916d9ced1c3f..4a9788e76489 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -547,13 +547,38 @@ static int __init map_entry_trampoline(void)
extern char __entry_tramp_data_start[];
__set_fixmap(FIX_ENTRY_TRAMP_DATA,
- __pa_symbol(__entry_tramp_data_start),
- PAGE_KERNEL_RO);
+ __pa_symbol(__entry_tramp_data_start), prot);
}
return 0;
}
core_initcall(map_entry_trampoline);
+
+#ifdef CONFIG_RANDOMIZE_BASE
+void __init tramp_patch_vectors_address(struct alt_instr *alt,
+ __le32 *origptr, __le32 *updptr,
+ int nr_inst)
+{
+ enum aarch64_insn_movewide_type type;
+ int s;
+
+ /* We only expect a 4 instruction sequence */
+ BUG_ON(nr_inst != 4);
+
+ type = AARCH64_INSN_MOVEWIDE_ZERO;
+ for (s = 0; nr_inst--; s += 16) {
+ extern const char vectors[];
+
+ u32 insn = aarch64_insn_gen_movewide(AARCH64_INSN_REG_30,
+ (u16)((u64)vectors >> s),
+ s,
+ AARCH64_INSN_VARIANT_64BIT,
+ type);
+ *updptr++ = cpu_to_le32(insn);
+ type = AARCH64_INSN_MOVEWIDE_KEEP;
+ }
+}
+#endif
#endif
/*
^ permalink raw reply related
* [PATCH 3/3] arm: KVM: Invalidate BTB on guest exit
From: Ard Biesheuvel @ 2018-01-06 13:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106120907.26701-4-marc.zyngier@arm.com>
On 6 January 2018 at 12:09, Marc Zyngier <marc.zyngier@arm.com> wrote:
> In order to avoid aliasing attacks against the branch predictor,
> let's invalidate the BTB on guest exit. This is made complicated
> by the fact that we cannot take a branch before invalidating the
> BTB.
>
> Another thing is that we perform the invalidation on all
> implementations, no matter if they are affected or not.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm/kvm/hyp/hyp-entry.S | 74 +++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 63 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S
> index 95a2faefc070..aa8adfa64ec9 100644
> --- a/arch/arm/kvm/hyp/hyp-entry.S
> +++ b/arch/arm/kvm/hyp/hyp-entry.S
> @@ -61,15 +61,60 @@
> __kvm_hyp_vector:
> .global __kvm_hyp_vector
>
> - @ Hyp-mode exception vector
> - W(b) hyp_reset
> - W(b) hyp_undef
> - W(b) hyp_svc
> - W(b) hyp_pabt
> - W(b) hyp_dabt
> - W(b) hyp_hvc
> - W(b) hyp_irq
> - W(b) hyp_fiq
> + /*
> + * We encode the exception entry in the bottom 3 bits of
> + * SP, and we have to guarantee to be 8 bytes aligned.
> + */
> + add sp, sp, #1 /* Reset 7 */
> + add sp, sp, #1 /* Undef 6 */
> + add sp, sp, #1 /* Syscall 5 */
> + add sp, sp, #1 /* Prefetch abort 4 */
> + add sp, sp, #1 /* Data abort 3 */
> + add sp, sp, #1 /* HVC 2 */
> + add sp, sp, #1 /* IRQ 1 */
> + add sp, sp, #1 /* FIQ 0 */
> +
> + sub sp, sp, #1
> +
> + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
> + isb
> +
> + /*
> + * As we cannot use any temporary registers and cannot
> + * clobber SP, we can decode the exception entry using
> + * an unrolled binary search.
> + */
> + tst sp, #4
> + bne 1f
> +
> + tst sp, #2
> + bne 3f
> +
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_irq
> + b hyp_irq
hyp_fiq ?
> +
> +1:
> + tst sp, #2
> + bne 2f
> +
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_svc
> + b hyp_pabt
> +
> +2:
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_reset
> + b hyp_undef
> +
> +3:
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_dabt
> + b hyp_hvc
>
> .macro invalid_vector label, cause
> .align
> @@ -149,7 +194,14 @@ hyp_hvc:
> bx ip
>
> 1:
> - push {lr}
> + /*
> + * Pushing r2 here is just a way of keeping the stack aligned to
> + * 8 bytes on any path that can trigger a HYP exception. Here,
> + * we may well be about to jump into the guest, and the guest
> + * exit would otherwise be badly decoded by our fancy
> + * "decode-exception-without-a-branch" code...
> + */
> + push {r2, lr}
>
> mov lr, r0
> mov r0, r1
> @@ -159,7 +211,7 @@ hyp_hvc:
> THUMB( orr lr, #1)
> blx lr @ Call the HYP function
>
> - pop {lr}
> + pop {r2, lr}
> eret
>
> guest_trap:
> --
> 2.14.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 3/3] arm: KVM: Invalidate BTB on guest exit
From: Ard Biesheuvel @ 2018-01-06 13:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106120907.26701-4-marc.zyngier@arm.com>
On 6 January 2018 at 12:09, Marc Zyngier <marc.zyngier@arm.com> wrote:
> In order to avoid aliasing attacks against the branch predictor,
> let's invalidate the BTB on guest exit. This is made complicated
> by the fact that we cannot take a branch before invalidating the
> BTB.
>
You can't even take an unconditional branch?
> Another thing is that we perform the invalidation on all
> implementations, no matter if they are affected or not.
>
> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> ---
> arch/arm/kvm/hyp/hyp-entry.S | 74 +++++++++++++++++++++++++++++++++++++-------
> 1 file changed, 63 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S
> index 95a2faefc070..aa8adfa64ec9 100644
> --- a/arch/arm/kvm/hyp/hyp-entry.S
> +++ b/arch/arm/kvm/hyp/hyp-entry.S
> @@ -61,15 +61,60 @@
> __kvm_hyp_vector:
> .global __kvm_hyp_vector
>
> - @ Hyp-mode exception vector
> - W(b) hyp_reset
> - W(b) hyp_undef
> - W(b) hyp_svc
> - W(b) hyp_pabt
> - W(b) hyp_dabt
> - W(b) hyp_hvc
> - W(b) hyp_irq
> - W(b) hyp_fiq
> + /*
> + * We encode the exception entry in the bottom 3 bits of
> + * SP, and we have to guarantee to be 8 bytes aligned.
> + */
> + add sp, sp, #1 /* Reset 7 */
> + add sp, sp, #1 /* Undef 6 */
> + add sp, sp, #1 /* Syscall 5 */
> + add sp, sp, #1 /* Prefetch abort 4 */
> + add sp, sp, #1 /* Data abort 3 */
> + add sp, sp, #1 /* HVC 2 */
> + add sp, sp, #1 /* IRQ 1 */
> + add sp, sp, #1 /* FIQ 0 */
> +
> + sub sp, sp, #1
> +
> + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
> + isb
> +
> + /*
> + * As we cannot use any temporary registers and cannot
> + * clobber SP, we can decode the exception entry using
> + * an unrolled binary search.
> + */
> + tst sp, #4
> + bne 1f
> +
> + tst sp, #2
> + bne 3f
> +
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_irq
> + b hyp_irq
> +
> +1:
> + tst sp, #2
> + bne 2f
> +
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_svc
> + b hyp_pabt
> +
> +2:
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_reset
> + b hyp_undef
> +
> +3:
> + tst sp, #1
> + bic sp, sp, #0x7
> + bne hyp_dabt
> + b hyp_hvc
>
> .macro invalid_vector label, cause
> .align
> @@ -149,7 +194,14 @@ hyp_hvc:
> bx ip
>
> 1:
> - push {lr}
> + /*
> + * Pushing r2 here is just a way of keeping the stack aligned to
> + * 8 bytes on any path that can trigger a HYP exception. Here,
> + * we may well be about to jump into the guest, and the guest
> + * exit would otherwise be badly decoded by our fancy
> + * "decode-exception-without-a-branch" code...
> + */
> + push {r2, lr}
>
> mov lr, r0
> mov r0, r1
> @@ -159,7 +211,7 @@ hyp_hvc:
> THUMB( orr lr, #1)
> blx lr @ Call the HYP function
>
> - pop {lr}
> + pop {r2, lr}
> eret
>
> guest_trap:
> --
> 2.14.2
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH 3/3] arm: KVM: Invalidate BTB on guest exit
From: Marc Zyngier @ 2018-01-06 13:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu-1JRts29L29CyMJ2Mba0aaVTS2W1yGRKqOyT1XTEmdUQ@mail.gmail.com>
On Sat, 6 Jan 2018 13:27:13 +0000
Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 6 January 2018 at 12:09, Marc Zyngier <marc.zyngier@arm.com> wrote:
> > In order to avoid aliasing attacks against the branch predictor,
> > let's invalidate the BTB on guest exit. This is made complicated
> > by the fact that we cannot take a branch before invalidating the
> > BTB.
> >
> > Another thing is that we perform the invalidation on all
> > implementations, no matter if they are affected or not.
> >
> > Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
> > ---
> > arch/arm/kvm/hyp/hyp-entry.S | 74 +++++++++++++++++++++++++++++++++++++-------
> > 1 file changed, 63 insertions(+), 11 deletions(-)
> >
> > diff --git a/arch/arm/kvm/hyp/hyp-entry.S b/arch/arm/kvm/hyp/hyp-entry.S
> > index 95a2faefc070..aa8adfa64ec9 100644
> > --- a/arch/arm/kvm/hyp/hyp-entry.S
> > +++ b/arch/arm/kvm/hyp/hyp-entry.S
> > @@ -61,15 +61,60 @@
> > __kvm_hyp_vector:
> > .global __kvm_hyp_vector
> >
> > - @ Hyp-mode exception vector
> > - W(b) hyp_reset
> > - W(b) hyp_undef
> > - W(b) hyp_svc
> > - W(b) hyp_pabt
> > - W(b) hyp_dabt
> > - W(b) hyp_hvc
> > - W(b) hyp_irq
> > - W(b) hyp_fiq
> > + /*
> > + * We encode the exception entry in the bottom 3 bits of
> > + * SP, and we have to guarantee to be 8 bytes aligned.
> > + */
> > + add sp, sp, #1 /* Reset 7 */
> > + add sp, sp, #1 /* Undef 6 */
> > + add sp, sp, #1 /* Syscall 5 */
> > + add sp, sp, #1 /* Prefetch abort 4 */
> > + add sp, sp, #1 /* Data abort 3 */
> > + add sp, sp, #1 /* HVC 2 */
> > + add sp, sp, #1 /* IRQ 1 */
> > + add sp, sp, #1 /* FIQ 0 */
> > +
> > + sub sp, sp, #1
> > +
> > + mcr p15, 0, r0, c7, c5, 6 /* BPIALL */
> > + isb
> > +
> > + /*
> > + * As we cannot use any temporary registers and cannot
> > + * clobber SP, we can decode the exception entry using
> > + * an unrolled binary search.
> > + */
> > + tst sp, #4
> > + bne 1f
> > +
> > + tst sp, #2
> > + bne 3f
> > +
> > + tst sp, #1
> > + bic sp, sp, #0x7
> > + bne hyp_irq
> > + b hyp_irq
>
> hyp_fiq ?
Indeed. Thanks for spotting that one!
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* [PATCH 3/3] arm: KVM: Invalidate BTB on guest exit
From: Marc Zyngier @ 2018-01-06 13:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAKv+Gu8JjwtoWUiY9zyhukarAfXB-LQHb10gb7tSE0iJ308b7w@mail.gmail.com>
On Sat, 6 Jan 2018 13:35:46 +0000
Ard Biesheuvel <ard.biesheuvel@linaro.org> wrote:
> On 6 January 2018 at 12:09, Marc Zyngier <marc.zyngier@arm.com> wrote:
> > In order to avoid aliasing attacks against the branch predictor,
> > let's invalidate the BTB on guest exit. This is made complicated
> > by the fact that we cannot take a branch before invalidating the
> > BTB.
> >
>
> You can't even take an unconditional branch?
Yup. We certainly have that restriction on arm64, and I assume it is
the same on 32bit.
M.
--
Without deviation from the norm, progress is not possible.
^ permalink raw reply
* [PATCH 2/5] clk: lpc32xx: read-only divider can propagate rate change
From: Vladimir Zapolskiy @ 2018-01-06 14:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515181225.5048.52.camel@baylibre.com>
Hi Jerome,
On 01/05/2018 09:40 PM, Jerome Brunet wrote:
> On Fri, 2018-01-05 at 20:12 +0200, Vladimir Zapolskiy wrote:
>> Hi Jerome,
>>
>> On 01/05/2018 07:09 PM, Jerome Brunet wrote:
>>> When a divider clock has CLK_DIVIDER_READ_ONLY set, it means that the
>>> register shall be left un-touched, but it does not mean the clock
>>> should stop rate propagation if CLK_SET_RATE_PARENT is set
>>>
>>
>> okay, the statement sounds correct, but there is no such clocks on LPC32xx,
>> thus I hardly can confirm that adding dead/inapplicable code is a fix.
>>
>>> This properly handled in qcom clk-regmap-divider but it was not in the
>>> lpc32xx divider
>>>
>>> Fixes: f7c82a60ba26 ("clk: lpc32xx: add common clock framework driver")
>>> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
>>
>> I would suggest to drop two LPC32xx clock driver changes from the series.
>
> Hi Vladimir,
>
> This is fine by me. Whether LPC32xx supports CLK_DIVIDER_READ_ONLY is up to you,
> but you should be consistent about it.
>
> I added the fix to LPC32xx because it looks like the generic divider (a lot) and
right, the relevant divider operations were copied, however the difference
is important, unfortunately there is no simple option to get rid of regmap,
because System Control Block registers are shared with a number of other
device drivers.
> appears to support CLK_DIVIDER_READ_ONLY. If it does not, could you please kill
> the related code ?
The driver supports CLK_DIVIDER_READ_ONLY clocks, and it should not be
changed, but all such clocks don't have children with CLK_SET_RATE_PARENT
property, which invalidates your fix for LPC32xx. Please let me know,
if I missed something.
--
With best wishes,
Vladimir
^ permalink raw reply
* [PATCH v2 0/5] constify struct imx_pinctrl_soc_info
From: Stefan Agner @ 2018-01-06 14:25 UTC (permalink / raw)
To: linux-arm-kernel
This patchset grew out of the discussion around the first version
of "pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL".
This is necessary for pinctrls of SoCs with multiple compatible
strings (currently only imx7d) since the struct uses the .data
pointer in struct of_device_id. It is also helpful for all other
SoCs since it decreases the .data section for all drivers by 1276
bytes.
Bai Ping (1):
pinctrl: imx6ul: add IOMUXC SNVS pinctrl driver for i.MX 6ULL
Stefan Agner (4):
pinctrl: imx: use struct imx_pinctrl_soc_info as a const
pinctrl: imx7d: simplify imx7d_pinctrl_probe
pinctrl: imx: constify struct imx_pinctrl_soc_info
pinctrl: imx7ulp: constify struct imx_cfg_params_decode
.../bindings/pinctrl/fsl,imx6ul-pinctrl.txt | 3 +-
drivers/pinctrl/freescale/pinctrl-imx.c | 81 ++++++++++------------
drivers/pinctrl/freescale/pinctrl-imx.h | 13 ++--
drivers/pinctrl/freescale/pinctrl-imx25.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx35.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx50.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx51.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx53.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6dl.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6q.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6sl.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6sx.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6ul.c | 52 ++++++++++++--
drivers/pinctrl/freescale/pinctrl-imx7d.c | 10 +--
drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 7 +-
drivers/pinctrl/freescale/pinctrl-vf610.c | 5 +-
16 files changed, 111 insertions(+), 78 deletions(-)
--
2.15.1
^ permalink raw reply
* [PATCH v2 1/5] pinctrl: imx: use struct imx_pinctrl_soc_info as a const
From: Stefan Agner @ 2018-01-06 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106142553.15322-1-stefan@agner.ch>
For some SoCs the struct imx_pinctrl_soc_info is passed through
of_device_id.data which is const. Most variables are already const
or otherwise not written. However, some fields are modified at
runtime. Move those fields to the dynamically allocated struct
imx_pinctrl.
Fixes: b3060044e495 ("pinctrl: freescale: imx7d: make of_device_ids const")
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 79 ++++++++++++++---------------
drivers/pinctrl/freescale/pinctrl-imx.h | 11 ++--
drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 3 +-
drivers/pinctrl/freescale/pinctrl-vf610.c | 3 +-
4 files changed, 44 insertions(+), 52 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 6e472691d8ee..86256d25c4a3 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -62,7 +62,6 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
struct pinctrl_map **map, unsigned *num_maps)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct imx_pinctrl_soc_info *info = ipctl->info;
const struct group_desc *grp;
struct pinctrl_map *new_map;
struct device_node *parent;
@@ -75,7 +74,7 @@ static int imx_dt_node_to_map(struct pinctrl_dev *pctldev,
*/
grp = imx_pinctrl_find_group_by_name(pctldev, np->name);
if (!grp) {
- dev_err(info->dev, "unable to find group for node %s\n",
+ dev_err(ipctl->dev, "unable to find group for node %s\n",
np->name);
return -EINVAL;
}
@@ -146,7 +145,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
unsigned group)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
unsigned int npins, pin_id;
int i;
@@ -174,7 +173,7 @@ static int imx_pmx_set(struct pinctrl_dev *pctldev, unsigned selector,
struct imx_pin *pin = &((struct imx_pin *)(grp->data))[i];
pin_id = pin->pin;
- pin_reg = &info->pin_regs[pin_id];
+ pin_reg = &ipctl->pin_regs[pin_id];
if (pin_reg->mux_reg == -1) {
dev_dbg(ipctl->dev, "Pin(%s) does not support mux function\n",
@@ -255,7 +254,7 @@ static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
unsigned long *configs,
unsigned int num_configs)
{
- struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
struct imx_cfg_params_decode *decode;
enum pin_config_param param;
u32 raw_config = 0;
@@ -289,7 +288,7 @@ static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
static u32 imx_pinconf_parse_generic_config(struct device_node *np,
struct imx_pinctrl *ipctl)
{
- struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
struct pinctrl_dev *pctl = ipctl->pctl;
unsigned int num_configs;
unsigned long *configs;
@@ -310,11 +309,11 @@ static int imx_pinconf_get(struct pinctrl_dev *pctldev,
unsigned pin_id, unsigned long *config)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
if (pin_reg->conf_reg == -1) {
- dev_err(info->dev, "Pin(%s) does not support config function\n",
+ dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
}
@@ -332,12 +331,12 @@ static int imx_pinconf_set(struct pinctrl_dev *pctldev,
unsigned num_configs)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
int i;
if (pin_reg->conf_reg == -1) {
- dev_err(info->dev, "Pin(%s) does not support config function\n",
+ dev_err(ipctl->dev, "Pin(%s) does not support config function\n",
info->pins[pin_id].name);
return -EINVAL;
}
@@ -368,8 +367,7 @@ static void imx_pinconf_dbg_show(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned pin_id)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct imx_pinctrl_soc_info *info = ipctl->info;
- const struct imx_pin_reg *pin_reg = &info->pin_regs[pin_id];
+ const struct imx_pin_reg *pin_reg = &ipctl->pin_regs[pin_id];
unsigned long config;
if (!pin_reg || pin_reg->conf_reg == -1) {
@@ -427,13 +425,13 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
struct imx_pinctrl *ipctl,
u32 index)
{
- struct imx_pinctrl_soc_info *info = ipctl->info;
+ const struct imx_pinctrl_soc_info *info = ipctl->info;
int size, pin_size;
const __be32 *list;
int i;
u32 config;
- dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
+ dev_dbg(ipctl->dev, "group(%d): %s\n", index, np->name);
if (info->flags & SHARE_MUX_CONF_REG)
pin_size = SHARE_FSL_PIN_SIZE;
@@ -460,7 +458,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
if (!list) {
list = of_get_property(np, "pinmux", &size);
if (!list) {
- dev_err(info->dev,
+ dev_err(ipctl->dev,
"no fsl,pins and pins property in node %pOF\n", np);
return -EINVAL;
}
@@ -468,7 +466,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
/* we do not check return since it's safe node passed down */
if (!size || size % pin_size) {
- dev_err(info->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
+ dev_err(ipctl->dev, "Invalid fsl,pins or pins property in node %pOF\n", np);
return -EINVAL;
}
@@ -476,9 +474,9 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
config = imx_pinconf_parse_generic_config(np, ipctl);
grp->num_pins = size / pin_size;
- grp->data = devm_kzalloc(info->dev, grp->num_pins *
+ grp->data = devm_kzalloc(ipctl->dev, grp->num_pins *
sizeof(struct imx_pin), GFP_KERNEL);
- grp->pins = devm_kzalloc(info->dev, grp->num_pins *
+ grp->pins = devm_kzalloc(ipctl->dev, grp->num_pins *
sizeof(unsigned int), GFP_KERNEL);
if (!grp->pins || !grp->data)
return -ENOMEM;
@@ -502,7 +500,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
}
pin_id = (mux_reg != -1) ? mux_reg / 4 : conf_reg / 4;
- pin_reg = &info->pin_regs[pin_id];
+ pin_reg = &ipctl->pin_regs[pin_id];
pin->pin = pin_id;
grp->pins[i] = pin_id;
pin_reg->mux_reg = mux_reg;
@@ -524,7 +522,7 @@ static int imx_pinctrl_parse_groups(struct device_node *np,
pin->config = config & ~IMX_PAD_SION;
}
- dev_dbg(info->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
+ dev_dbg(ipctl->dev, "%s: 0x%x 0x%08lx", info->pins[pin_id].name,
pin->mux_mode, pin->config);
}
@@ -536,13 +534,12 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
u32 index)
{
struct pinctrl_dev *pctl = ipctl->pctl;
- struct imx_pinctrl_soc_info *info = ipctl->info;
struct device_node *child;
struct function_desc *func;
struct group_desc *grp;
u32 i = 0;
- dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
+ dev_dbg(pctl->dev, "parse function(%d): %s\n", index, np->name);
func = pinmux_generic_get_function(pctl, index);
if (!func)
@@ -552,10 +549,10 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
func->name = np->name;
func->num_group_names = of_get_child_count(np);
if (func->num_group_names == 0) {
- dev_err(info->dev, "no groups defined in %pOF\n", np);
+ dev_err(ipctl->dev, "no groups defined in %pOF\n", np);
return -EINVAL;
}
- func->group_names = devm_kcalloc(info->dev, func->num_group_names,
+ func->group_names = devm_kcalloc(ipctl->dev, func->num_group_names,
sizeof(char *), GFP_KERNEL);
if (!func->group_names)
return -ENOMEM;
@@ -563,15 +560,15 @@ static int imx_pinctrl_parse_functions(struct device_node *np,
for_each_child_of_node(np, child) {
func->group_names[i] = child->name;
- grp = devm_kzalloc(info->dev, sizeof(struct group_desc),
+ grp = devm_kzalloc(ipctl->dev, sizeof(struct group_desc),
GFP_KERNEL);
if (!grp)
return -ENOMEM;
- mutex_lock(&info->mutex);
+ mutex_lock(&ipctl->mutex);
radix_tree_insert(&pctl->pin_group_tree,
- info->group_index++, grp);
- mutex_unlock(&info->mutex);
+ ipctl->group_index++, grp);
+ mutex_unlock(&ipctl->mutex);
imx_pinctrl_parse_groups(child, grp, ipctl, i++);
}
@@ -608,7 +605,6 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
struct device_node *np = pdev->dev.of_node;
struct device_node *child;
struct pinctrl_dev *pctl = ipctl->pctl;
- struct imx_pinctrl_soc_info *info = ipctl->info;
u32 nfuncs = 0;
u32 i = 0;
bool flat_funcs;
@@ -635,13 +631,13 @@ static int imx_pinctrl_probe_dt(struct platform_device *pdev,
if (!function)
return -ENOMEM;
- mutex_lock(&info->mutex);
+ mutex_lock(&ipctl->mutex);
radix_tree_insert(&pctl->pin_function_tree, i, function);
- mutex_unlock(&info->mutex);
+ mutex_unlock(&ipctl->mutex);
}
pctl->num_functions = nfuncs;
- info->group_index = 0;
+ ipctl->group_index = 0;
if (flat_funcs) {
pctl->num_groups = of_get_child_count(np);
} else {
@@ -672,7 +668,7 @@ static void imx_free_resources(struct imx_pinctrl *ipctl)
}
int imx_pinctrl_probe(struct platform_device *pdev,
- struct imx_pinctrl_soc_info *info)
+ const struct imx_pinctrl_soc_info *info)
{
struct regmap_config config = { .name = "gpr" };
struct device_node *dev_np = pdev->dev.of_node;
@@ -687,7 +683,6 @@ int imx_pinctrl_probe(struct platform_device *pdev,
dev_err(&pdev->dev, "wrong pinctrl info\n");
return -EINVAL;
}
- info->dev = &pdev->dev;
if (info->gpr_compatible) {
gpr = syscon_regmap_lookup_by_compatible(info->gpr_compatible);
@@ -700,14 +695,14 @@ int imx_pinctrl_probe(struct platform_device *pdev,
if (!ipctl)
return -ENOMEM;
- info->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*info->pin_regs) *
+ ipctl->pin_regs = devm_kmalloc(&pdev->dev, sizeof(*ipctl->pin_regs) *
info->npins, GFP_KERNEL);
- if (!info->pin_regs)
+ if (!ipctl->pin_regs)
return -ENOMEM;
for (i = 0; i < info->npins; i++) {
- info->pin_regs[i].mux_reg = -1;
- info->pin_regs[i].conf_reg = -1;
+ ipctl->pin_regs[i].mux_reg = -1;
+ ipctl->pin_regs[i].conf_reg = -1;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -751,10 +746,10 @@ int imx_pinctrl_probe(struct platform_device *pdev,
/* platform specific callback */
imx_pmx_ops.gpio_set_direction = info->gpio_set_direction;
- mutex_init(&info->mutex);
+ mutex_init(&ipctl->mutex);
ipctl->info = info;
- ipctl->dev = info->dev;
+ ipctl->dev = &pdev->dev;
platform_set_drvdata(pdev, ipctl);
ret = devm_pinctrl_register_and_init(&pdev->dev,
imx_pinctrl_desc, ipctl,
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 5aa22b52c1d4..41ee75537da4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -58,14 +58,10 @@ struct imx_cfg_params_decode {
};
struct imx_pinctrl_soc_info {
- struct device *dev;
const struct pinctrl_pin_desc *pins;
unsigned int npins;
- struct imx_pin_reg *pin_regs;
- unsigned int group_index;
unsigned int flags;
const char *gpr_compatible;
- struct mutex mutex;
/* MUX_MODE shift and mask in case SHARE_MUX_CONF_REG */
unsigned int mux_mask;
@@ -95,7 +91,10 @@ struct imx_pinctrl {
struct pinctrl_dev *pctl;
void __iomem *base;
void __iomem *input_sel_base;
- struct imx_pinctrl_soc_info *info;
+ const struct imx_pinctrl_soc_info *info;
+ struct imx_pin_reg *pin_regs;
+ unsigned int group_index;
+ struct mutex mutex;
};
#define IMX_CFG_PARAMS_DECODE(p, m, o) \
@@ -117,5 +116,5 @@ struct imx_pinctrl {
#define IOMUXC_CONFIG_SION (0x1 << 4)
int imx_pinctrl_probe(struct platform_device *pdev,
- struct imx_pinctrl_soc_info *info);
+ const struct imx_pinctrl_soc_info *info);
#endif /* __DRIVERS_PINCTRL_IMX_H */
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
index b7bebb292f37..9161c984f57b 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
@@ -307,11 +307,10 @@ static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
- pin_reg = &info->pin_regs[offset];
+ pin_reg = &ipctl->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index ac18bb6d6d5e..42745c690be3 100644
--- a/drivers/pinctrl/freescale/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -300,11 +300,10 @@ static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
unsigned offset, bool input)
{
struct imx_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
- struct imx_pinctrl_soc_info *info = ipctl->info;
const struct imx_pin_reg *pin_reg;
u32 reg;
- pin_reg = &info->pin_regs[offset];
+ pin_reg = &ipctl->pin_regs[offset];
if (pin_reg->mux_reg == -1)
return -EINVAL;
--
2.15.1
^ permalink raw reply related
* [PATCH v2 2/5] pinctrl: imx7d: simplify imx7d_pinctrl_probe
From: Stefan Agner @ 2018-01-06 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106142553.15322-1-stefan@agner.ch>
Using of_device_get_match_data in imx7d_pinctrl_probe simplifies
the function. Also get rid of the void pointer cast since
imx_pinctrl_probe now accepts const struct imx_pinctrl_soc_info.
Cc: Arvind Yadav <arvind.yadav.cs@gmail.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/pinctrl/freescale/pinctrl-imx7d.c | 10 +++-------
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7d.c b/drivers/pinctrl/freescale/pinctrl-imx7d.c
index 754159ee7b1e..0b0a2f33b06a 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7d.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7d.c
@@ -378,16 +378,12 @@ static const struct of_device_id imx7d_pinctrl_of_match[] = {
static int imx7d_pinctrl_probe(struct platform_device *pdev)
{
- const struct of_device_id *match;
- struct imx_pinctrl_soc_info *pinctrl_info;
+ const struct imx_pinctrl_soc_info *pinctrl_info;
- match = of_match_device(imx7d_pinctrl_of_match, &pdev->dev);
-
- if (!match)
+ pinctrl_info = of_device_get_match_data(&pdev->dev);
+ if (!pinctrl_info)
return -ENODEV;
- pinctrl_info = (struct imx_pinctrl_soc_info *) match->data;
-
return imx_pinctrl_probe(pdev, pinctrl_info);
}
--
2.15.1
^ permalink raw reply related
* [PATCH v2 3/5] pinctrl: imx: constify struct imx_pinctrl_soc_info
From: Stefan Agner @ 2018-01-06 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106142553.15322-1-stefan@agner.ch>
Now that imx_pinctrl_probe accepts const struct imx_pinctrl_soc_info
we can constify all declarations of struct imx_pinctrl_soc_info.
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/pinctrl/freescale/pinctrl-imx25.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx35.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx50.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx51.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx53.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6dl.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6q.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6sl.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx6sx.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 2 +-
drivers/pinctrl/freescale/pinctrl-vf610.c | 2 +-
11 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx25.c b/drivers/pinctrl/freescale/pinctrl-imx25.c
index d7367fabe712..db6d9d1382f9 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx25.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx25.c
@@ -309,7 +309,7 @@ static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
};
-static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx25_pinctrl_info = {
.pins = imx25_pinctrl_pads,
.npins = ARRAY_SIZE(imx25_pinctrl_pads),
};
diff --git a/drivers/pinctrl/freescale/pinctrl-imx35.c b/drivers/pinctrl/freescale/pinctrl-imx35.c
index 6315ba6af431..6927946ae4b5 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx35.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx35.c
@@ -999,7 +999,7 @@ static const struct pinctrl_pin_desc imx35_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
};
-static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx35_pinctrl_info = {
.pins = imx35_pinctrl_pads,
.npins = ARRAY_SIZE(imx35_pinctrl_pads),
};
diff --git a/drivers/pinctrl/freescale/pinctrl-imx50.c b/drivers/pinctrl/freescale/pinctrl-imx50.c
index 8e3a17df5c5d..eb349b97290f 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx50.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx50.c
@@ -385,7 +385,7 @@ static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
};
-static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx50_pinctrl_info = {
.pins = imx50_pinctrl_pads,
.npins = ARRAY_SIZE(imx50_pinctrl_pads),
.gpr_compatible = "fsl,imx50-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx51.c b/drivers/pinctrl/freescale/pinctrl-imx51.c
index eeac64ba2709..49acd991b5fb 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx51.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx51.c
@@ -762,7 +762,7 @@ static const struct pinctrl_pin_desc imx51_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
};
-static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx51_pinctrl_info = {
.pins = imx51_pinctrl_pads,
.npins = ARRAY_SIZE(imx51_pinctrl_pads),
};
diff --git a/drivers/pinctrl/freescale/pinctrl-imx53.c b/drivers/pinctrl/freescale/pinctrl-imx53.c
index 46a9572f3473..6dd0c60eaea4 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx53.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx53.c
@@ -448,7 +448,7 @@ static const struct pinctrl_pin_desc imx53_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
};
-static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx53_pinctrl_info = {
.pins = imx53_pinctrl_pads,
.npins = ARRAY_SIZE(imx53_pinctrl_pads),
.gpr_compatible = "fsl,imx53-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6dl.c b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
index 3f25ca5867cc..91b85fc01de8 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6dl.c
@@ -457,7 +457,7 @@ static const struct pinctrl_pin_desc imx6dl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
};
-static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
.pins = imx6dl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
.gpr_compatible = "fsl,imx6q-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6q.c b/drivers/pinctrl/freescale/pinctrl-imx6q.c
index d61651c40458..5f653d69d0f5 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6q.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6q.c
@@ -460,7 +460,7 @@ static const struct pinctrl_pin_desc imx6q_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
};
-static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
.pins = imx6q_pinctrl_pads,
.npins = ARRAY_SIZE(imx6q_pinctrl_pads),
.gpr_compatible = "fsl,imx6q-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sl.c b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
index d023f6b00623..1167dc273c04 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sl.c
@@ -363,7 +363,7 @@ static const struct pinctrl_pin_desc imx6sl_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
};
-static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
.pins = imx6sl_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
.gpr_compatible = "fsl,imx6sl-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx6sx.c b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
index 898b781701e6..15ea56c75f68 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx6sx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx6sx.c
@@ -367,7 +367,7 @@ static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
};
-static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
.pins = imx6sx_pinctrl_pads,
.npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
.gpr_compatible = "fsl,imx6sx-iomuxc-gpr",
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
index 9161c984f57b..0406d8b39e6a 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
@@ -324,7 +324,7 @@ static int imx7ulp_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
return 0;
}
-static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
.pins = imx7ulp_pinctrl_pads,
.npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
.flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
diff --git a/drivers/pinctrl/freescale/pinctrl-vf610.c b/drivers/pinctrl/freescale/pinctrl-vf610.c
index 42745c690be3..c078f859ae15 100644
--- a/drivers/pinctrl/freescale/pinctrl-vf610.c
+++ b/drivers/pinctrl/freescale/pinctrl-vf610.c
@@ -318,7 +318,7 @@ static int vf610_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
return 0;
}
-static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
+static const struct imx_pinctrl_soc_info vf610_pinctrl_info = {
.pins = vf610_pinctrl_pads,
.npins = ARRAY_SIZE(vf610_pinctrl_pads),
.flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,
--
2.15.1
^ permalink raw reply related
* [PATCH v2 4/5] pinctrl: imx7ulp: constify struct imx_cfg_params_decode
From: Stefan Agner @ 2018-01-06 14:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106142553.15322-1-stefan@agner.ch>
The decode parameters are constant mark them const.
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/pinctrl/freescale/pinctrl-imx.c | 2 +-
drivers/pinctrl/freescale/pinctrl-imx.h | 2 +-
drivers/pinctrl/freescale/pinctrl-imx7ulp.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.c b/drivers/pinctrl/freescale/pinctrl-imx.c
index 86256d25c4a3..24aaddd760a0 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx.c
@@ -255,7 +255,7 @@ static u32 imx_pinconf_decode_generic_config(struct imx_pinctrl *ipctl,
unsigned int num_configs)
{
const struct imx_pinctrl_soc_info *info = ipctl->info;
- struct imx_cfg_params_decode *decode;
+ const struct imx_cfg_params_decode *decode;
enum pin_config_param param;
u32 raw_config = 0;
u32 param_val;
diff --git a/drivers/pinctrl/freescale/pinctrl-imx.h b/drivers/pinctrl/freescale/pinctrl-imx.h
index 41ee75537da4..038e8c0e5b96 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx.h
+++ b/drivers/pinctrl/freescale/pinctrl-imx.h
@@ -71,7 +71,7 @@ struct imx_pinctrl_soc_info {
bool generic_pinconf;
const struct pinconf_generic_params *custom_params;
unsigned int num_custom_params;
- struct imx_cfg_params_decode *decodes;
+ const struct imx_cfg_params_decode *decodes;
unsigned int num_decodes;
void (*fixup)(unsigned long *configs, unsigned int num_configs,
u32 *raw_config);
diff --git a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
index 0406d8b39e6a..f363e45fd246 100644
--- a/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
+++ b/drivers/pinctrl/freescale/pinctrl-imx7ulp.c
@@ -266,7 +266,7 @@ static const struct pinctrl_pin_desc imx7ulp_pinctrl_pads[] = {
#define BP_MUX_MODE 8
#define BM_PULL_ENABLED BIT(1)
-struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
+static const struct imx_cfg_params_decode imx7ulp_cfg_decodes[] = {
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_STRENGTH, BIT(6), 6),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_DRIVE_PUSH_PULL, BIT(5), 5),
IMX_CFG_PARAMS_DECODE(PIN_CONFIG_SLEW_RATE, BIT(2), 2),
--
2.15.1
^ permalink raw reply related
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