* [PATCH] Revert "ARM: dts: exynos: Add missing interrupt-controller properties to Exynos5410 PMU"
From: Krzysztof Kozlowski @ 2018-01-07 10:17 UTC (permalink / raw)
To: linux-arm-kernel
This reverts commit 6737b081409a4373e9d02c75aea7b916481e31b5.
Unlike on Exynos5420-family, on Exynos5410 the PMU is not an interrupt
controller so it should not handle interrupts of RTC. The DTC warning
(addressed by mentioned commit) should be fixed by not routing RTC
interrupts to PMU.
Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5410.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 375b73015ee4..83641ad0d8f2 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -72,9 +72,6 @@
clock-names = "clkout16";
clocks = <&fin_pll>;
#clock-cells = <1>;
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
};
clock: clock-controller at 10010000 {
--
2.11.0
^ permalink raw reply related
* soc: imx: gpcv2: removing and probing fails
From: Stefan Agner @ 2018-01-07 10:48 UTC (permalink / raw)
To: linux-arm-kernel
Hi Andrew,
I noticed that the driver fails when removing and probing again. As far
as I can see due to duplicate add of the platform devices.
As far as I can tell the driver should register the remove callback and
do a platform_device_unregister on the newly created platform devices.
However, as far as I can tell we don't hold on to a reference to them...
I guess we could keep references in imx_gpcv2_probe, but maybe there is
an easier way?
This can be reproduced by using:
CONFIG_DEBUG_TEST_DRIVER_REMOVE=y
The full stack trace:
[ 0.673113] ------------[ cut here ]------------
[ 0.676786] WARNING: CPU: 0 PID: 1 at fs/sysfs/dir.c:31
sysfs_warn_dup+0x64/0x74
[ 0.686186] sysfs: cannot create duplicate filename
'/devices/platform/soc/30000000.aips-bus/303a0000.gpc/imx7-pgc-domain.1'
[ 0.698594] Modules linked in:
[ 0.700783] CPU: 0 PID: 1 Comm: swapper/0 Not tainted
4.15.0-rc3-00027-g3b196a7dd3bd-dirty #220
[ 0.711659] Hardware name: Freescale i.MX7 Dual (Device Tree)
[ 0.716746] [<8010f55c>] (unwind_backtrace) from [<8010b8e4>]
(show_stack+0x10/0x14)
[ 0.726785] [<8010b8e4>] (show_stack) from [<80830124>]
(dump_stack+0x88/0x9c)
[ 0.735813] [<80830124>] (dump_stack) from [<8011e58c>]
(__warn+0xdc/0xf4)
[ 0.742232] [<8011e58c>] (__warn) from [<8011e5dc>]
(warn_slowpath_fmt+0x38/0x48)
[ 0.752034] [<8011e5dc>] (warn_slowpath_fmt) from [<80276600>]
(sysfs_warn_dup+0x64/0x74)
[ 0.762167] [<80276600>] (sysfs_warn_dup) from [<802766d8>]
(sysfs_create_dir_ns+0x84/0x90)
[ 0.772513] [<802766d8>] (sysfs_create_dir_ns) from [<80834660>]
(kobject_add_internal+0xb4/0x30c)
[ 0.783562] [<80834660>] (kobject_add_internal) from [<80834904>]
(kobject_add+0x4c/0x9c)
[ 0.793846] [<80834904>] (kobject_add) from [<8050bdd0>]
(device_add+0xe0/0x594)
[ 0.803418] [<8050bdd0>] (device_add) from [<80510178>]
(platform_device_add+0x110/0x224)
[ 0.813805] [<80510178>] (platform_device_add) from [<8049bfa0>]
(imx_gpcv2_probe+0xdc/0x1f8)
[ 0.824592] [<8049bfa0>] (imx_gpcv2_probe) from [<80510364>]
(platform_drv_probe+0x50/0xac)
[ 0.835264] [<80510364>] (platform_drv_probe) from [<8050e9ac>]
(driver_probe_device+0x1b4/0x3c8)
[ 0.846525] [<8050e9ac>] (driver_probe_device) from [<8050ec64>]
(__driver_attach+0xa4/0xa8)
[ 0.857356] [<8050ec64>] (__driver_attach) from [<8050cd88>]
(bus_for_each_dev+0x4c/0x9c)
[ 0.867935] [<8050cd88>] (bus_for_each_dev) from [<8050df40>]
(bus_add_driver+0x188/0x20c)
[ 0.878650] [<8050df40>] (bus_add_driver) from [<8050f554>]
(driver_register+0x78/0xf4)
[ 0.889101] [<8050f554>] (driver_register) from [<80101a5c>]
(do_one_initcall+0x44/0x168)
[ 0.899733] [<80101a5c>] (do_one_initcall) from [<80c00db8>]
(kernel_init_freeable+0x14c/0x1d8)
[ 0.910899] [<80c00db8>] (kernel_init_freeable) from [<80842638>]
(kernel_init+0x8/0x10c)
[ 0.921529] [<80842638>] (kernel_init) from [<80107988>]
(ret_from_fork+0x14/0x2c)
[ 0.931569] ---[ end trace 27014f64d1c1710e ]---
[ 0.935967] ------------[ cut here ]------------
[ 0.940537] WARNING: CPU: 0 PID: 1 at lib/kobject.c:240
kobject_add_internal+0x278/0x30c
[ 0.951181] kobject_add_internal failed for imx7-pgc-domain.1 with
-EEXIST, don't try to register things with the same name in the same
directory.
[ 0.966666] Modules linked in:
[ 0.969363] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W
4.15.0-rc3-00027-g3b196a7dd3bd-dirty #220
[ 0.981886] Hardware name: Freescale i.MX7 Dual (Device Tree)
[ 0.987266] [<8010f55c>] (unwind_backtrace) from [<8010b8e4>]
(show_stack+0x10/0x14)
[ 0.997423] [<8010b8e4>] (show_stack) from [<80830124>]
(dump_stack+0x88/0x9c)
[ 1.006649] [<80830124>] (dump_stack) from [<8011e58c>]
(__warn+0xdc/0xf4)
[ 1.013159] [<8011e58c>] (__warn) from [<8011e5dc>]
(warn_slowpath_fmt+0x38/0x48)
[ 1.022994] [<8011e5dc>] (warn_slowpath_fmt) from [<80834824>]
(kobject_add_internal+0x278/0x30c)
[ 1.033847] [<80834824>] (kobject_add_internal) from [<80834904>]
(kobject_add+0x4c/0x9c)
[ 1.043990] [<80834904>] (kobject_add) from [<8050bdd0>]
(device_add+0xe0/0x594)
[ 1.053333] [<8050bdd0>] (device_add) from [<80510178>]
(platform_device_add+0x110/0x224)
[ 1.063508] [<80510178>] (platform_device_add) from [<8049bfa0>]
(imx_gpcv2_probe+0xdc/0x1f8)
[ 1.074202] [<8049bfa0>] (imx_gpcv2_probe) from [<80510364>]
(platform_drv_probe+0x50/0xac)
[ 1.084735] [<80510364>] (platform_drv_probe) from [<8050e9ac>]
(driver_probe_device+0x1b4/0x3c8)
[ 1.095818] [<8050e9ac>] (driver_probe_device) from [<8050ec64>]
(__driver_attach+0xa4/0xa8)
[ 1.106556] [<8050ec64>] (__driver_attach) from [<8050cd88>]
(bus_for_each_dev+0x4c/0x9c)
[ 1.117104] [<8050cd88>] (bus_for_each_dev) from [<8050df40>]
(bus_add_driver+0x188/0x20c)
[ 1.127752] [<8050df40>] (bus_add_driver) from [<8050f554>]
(driver_register+0x78/0xf4)
[ 1.138150] [<8050f554>] (driver_register) from [<80101a5c>]
(do_one_initcall+0x44/0x168)
[ 1.148780] [<80101a5c>] (do_one_initcall) from [<80c00db8>]
(kernel_init_freeable+0x14c/0x1d8)
[ 1.159946] [<80c00db8>] (kernel_init_freeable) from [<80842638>]
(kernel_init+0x8/0x10c)
[ 1.170577] [<80842638>] (kernel_init) from [<80107988>]
(ret_from_fork+0x14/0x2c)
[ 1.180607] ---[ end trace 27014f64d1c1710f ]---
[ 1.185014] ------------[ cut here ]------------
[ 1.189571] Kernel BUG at 5168736d [verbose debug info unavailable]
[ 1.195868] Internal error: Oops - BUG: 0 [#1] SMP ARM
[ 1.200985] Modules linked in:
[ 1.203978] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W
4.15.0-rc3-00027-g3b196a7dd3bd-dirty #220
[ 1.216449] Hardware name: Freescale i.MX7 Dual (Device Tree)
[ 1.221768] PC is at kfree+0xfc/0x140
[ 1.225376] LR is at platform_device_release+0x10/0x34
[ 1.230510] pc : [<801fd494>] lr : [<8050ff50>] psr: 40000013
[ 1.236804] sp : ac079df0 ip : 00000000 fp : ffffffef
[ 1.242008] r10: ac225400 r9 : ac225000 r8 : 80d23fa0
[ 1.247201] r7 : af770d04 r6 : 00000000 r5 : ac225410 r4 :
ac225410
[ 1.253741] r3 : af794494 r2 : af794480 r1 : a0000013 r0 :
80d241a0
[ 1.260252] Flags: nZcv IRQs on FIQs on Mode SVC_32 ISA ARM
Segment none
[ 1.267425] Control: 10c5387d Table: 8000406a DAC: 00000051
[ 1.273163] Process swapper/0 (pid: 1, stack limit = 0x7ec51c00)
[ 1.279174] Stack: (0xac079df0 to 0xac07a000)
[ 1.283497] 9de0: ac225410
ac225418 ac225410 ac225410
[ 1.293629] 9e00: ac225410 00000000 af770d04 8050ff50 ac225418
80509c4c ac225418 80d2a744
[ 1.302856] 9e20: ac2a68c0 80834038 80aa8500 af770d04 af770de8
ac11fa10 80aa8500 8049c078
[ 1.312114] 9e40: 00000000 00000000 ac32d180 00000001 80b40a88
ac11fa10 fffffffe 80d24010
[ 1.321543] 9e60: fffffdfb 80d24010 80daef28 00000000 00000000
80510364 ac11fa10 00000000
[ 1.331081] 9e80: 80daef24 00000000 80d24010 8050e9ac af770b0c
00000000 000000d7 ac11fa10
[ 1.340735] 9ea0: 80d24010 ac11fa44 00000000 000000d7 80c5b83c
80c6c578 00000000 8050ec64
[ 1.350475] 9ec0: 00000000 80d24010 8050ebc0 8050cd88 ac041758
ac114ab4 80d24010 ac2a3400
[ 1.360365] 9ee0: 80d2ab20 8050df40 80afeb04 80c35e1c 80d24010
80d24010 00000000 80c35e4c
[ 1.370388] 9f00: 80d58600 8050f554 ffffe000 00000000 80c35e4c
80101a5c 80b949dc 000000d7
[ 1.380600] 9f20: 00000000 8013a238 00000000 80b1d70c 00000006
00000006 80aada0c 00000000
[ 1.390896] 9f40: 80ab6b90 80aada80 affffc8a affffc92 00000000
00000007 80d58600 80c5b830
[ 1.401286] 9f60: 00000007 80d58600 80c5b834 80d58600 000000d7
80c00db8 00000006 00000006
[ 1.411792] 9f80: 00000000 80c005b0 00000000 80842630 00000000
00000000 00000000 00000000
[ 1.422343] 9fa0: 00000000 80842638 00000000 80107988 00000000
00000000 00000000 00000000
[ 1.432895] 9fc0: 00000000 00000000 00000000 00000000 00000000
00000000 00000000 00000000
[ 1.443458] 9fe0: 00000000 00000000 00000000 00000000 00000013
00000000 bf73ffff 4c5eafe0
[ 1.454043] [<801fd494>] (kfree) from [<8050ff50>]
(platform_device_release+0x10/0x34)
[ 1.464336] [<8050ff50>] (platform_device_release) from [<80509c4c>]
(device_release+0x2c/0x90)
[ 1.475435] [<80509c4c>] (device_release) from [<80834038>]
(kobject_put+0x94/0xe4)
[ 1.485474] [<80834038>] (kobject_put) from [<8049c078>]
(imx_gpcv2_probe+0x1b4/0x1f8)
[ 1.495784] [<8049c078>] (imx_gpcv2_probe) from [<80510364>]
(platform_drv_probe+0x50/0xac)
[ 1.506544] [<80510364>] (platform_drv_probe) from [<8050e9ac>]
(driver_probe_device+0x1b4/0x3c8)
[ 1.517844] [<8050e9ac>] (driver_probe_device) from [<8050ec64>]
(__driver_attach+0xa4/0xa8)
[ 1.528708] [<8050ec64>] (__driver_attach) from [<8050cd88>]
(bus_for_each_dev+0x4c/0x9c)
[ 1.539313] [<8050cd88>] (bus_for_each_dev) from [<8050df40>]
(bus_add_driver+0x188/0x20c)
[ 1.550011] [<8050df40>] (bus_add_driver) from [<8050f554>]
(driver_register+0x78/0xf4)
[ 1.560449] [<8050f554>] (driver_register) from [<80101a5c>]
(do_one_initcall+0x44/0x168)
[ 1.571073] [<80101a5c>] (do_one_initcall) from [<80c00db8>]
(kernel_init_freeable+0x14c/0x1d8)
[ 1.582239] [<80c00db8>] (kernel_init_freeable) from [<80842638>]
(kernel_init+0x8/0x10c)
[ 1.592874] [<80842638>] (kernel_init) from [<80107988>]
(ret_from_fork+0x14/0x2c)
[ 1.602885] Code: 1a000003 e5923014 e3130001 1a000000 (e7f001f2)
[ 1.608796] ---[ end trace 27014f64d1c17110 ]---
[ 1.613635] Kernel panic - not syncing: Attempted to kill init!
exitcode=0x0000000b
[ 1.613635]
[ 1.627569] ---[ end Kernel panic - not syncing: Attempted to kill
init! exitcode=0x0000000b
[ 1.627569]
--
Stefan
^ permalink raw reply
* [GIT PULL 0/4] ARM: exynos: Second pull for v4.16
From: Krzysztof Kozlowski @ 2018-01-07 11:36 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
Last round of updates for v4.16. Two tags based on previous.
Best regards,
Krzysztof
^ permalink raw reply
* [GIT PULL 3/4] soc: samsung: Stuff for v4.16
From: Krzysztof Kozlowski @ 2018-01-07 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180107113625.15488-1-krzk@kernel.org>
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-drivers-4.16-2
for you to fetch changes up to 06512c539ff1d6d008d5e8ab9d6f5f6405972f53:
soc: samsung: Add SPDX license identifiers (2018-01-03 18:45:15 +0100)
----------------------------------------------------------------
Samsung soc drivers changes for v4.16
Add SPDX license identifiers.
----------------------------------------------------------------
Krzysztof Kozlowski (1):
soc: samsung: Add SPDX license identifiers
drivers/soc/samsung/Kconfig | 1 +
drivers/soc/samsung/Makefile | 1 +
drivers/soc/samsung/exynos-pmu.c | 16 ++++++----------
drivers/soc/samsung/exynos-pmu.h | 5 +----
drivers/soc/samsung/exynos3250-pmu.c | 16 ++++++----------
drivers/soc/samsung/exynos4-pmu.c | 16 ++++++----------
drivers/soc/samsung/exynos5250-pmu.c | 16 ++++++----------
drivers/soc/samsung/exynos5420-pmu.c | 16 ++++++----------
drivers/soc/samsung/pm_domains.c | 24 ++++++++++--------------
9 files changed, 43 insertions(+), 68 deletions(-)
^ permalink raw reply
* [GIT PULL 1/4] ARM: dts: exynos: Stuff for v4.16, 2nd round
From: Krzysztof Kozlowski @ 2018-01-07 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180107113625.15488-1-krzk@kernel.org>
Hi,
On top of previous pull request.
Best regards,
Krzysztof
The following changes since commit 3be1ecf291df8191f5ea395d363acc8fa029b5fd:
ARM: dts: exynos: Use lower case hex addresses in node unit addresses (2017-12-18 18:15:51 +0100)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt-4.16-2
for you to fetch changes up to 5628a8ca14149ba4226e3bdce3a04c3b688435ad:
ARM: dts: exynos: fix RTC interrupt for exynos5410 (2018-01-07 11:15:59 +0100)
----------------------------------------------------------------
Samsung DTS ARM changes for 4.16, part 2
1. Add SPDX license identifiers.
2. Properly fix DTC warning for PMU/RTC interrupts on Exynos5410.
----------------------------------------------------------------
Arnd Bergmann (1):
ARM: dts: exynos: fix RTC interrupt for exynos5410
Krzysztof Kozlowski (5):
ARM: dts: exynos: Add SPDX license identifiers
ARM: dts: s3c24xx: Add SPDX license identifiers
ARM: dts: s3c64xx: Add SPDX license identifiers
ARM: dts: s5pv210: Add SPDX license identifiers
Revert "ARM: dts: exynos: Add missing interrupt-controller properties to Exynos5410 PMU"
arch/arm/boot/dts/exynos3250-artik5-eval.dts | 5 +----
arch/arm/boot/dts/exynos3250-artik5.dtsi | 5 +----
arch/arm/boot/dts/exynos3250-monk.dts | 5 +----
arch/arm/boot/dts/exynos3250-pinctrl.dtsi | 7 ++-----
arch/arm/boot/dts/exynos3250-rinato.dts | 5 +----
arch/arm/boot/dts/exynos3250.dtsi | 5 +----
arch/arm/boot/dts/exynos4-cpu-thermal.dtsi | 6 +-----
arch/arm/boot/dts/exynos4.dtsi | 5 +----
arch/arm/boot/dts/exynos4210-origen.dts | 7 ++-----
arch/arm/boot/dts/exynos4210-pinctrl.dtsi | 7 ++-----
arch/arm/boot/dts/exynos4210-smdkv310.dts | 7 ++-----
arch/arm/boot/dts/exynos4210-trats.dts | 7 ++-----
arch/arm/boot/dts/exynos4210-universal_c210.dts | 7 ++-----
arch/arm/boot/dts/exynos4210.dtsi | 7 ++-----
arch/arm/boot/dts/exynos4412-itop-elite.dts | 5 +----
arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi | 5 +----
arch/arm/boot/dts/exynos4412-odroid-common.dtsi | 5 +----
arch/arm/boot/dts/exynos4412-odroidu3.dts | 7 ++-----
arch/arm/boot/dts/exynos4412-odroidx.dts | 7 ++-----
arch/arm/boot/dts/exynos4412-odroidx2.dts | 7 ++-----
arch/arm/boot/dts/exynos4412-origen.dts | 7 ++-----
arch/arm/boot/dts/exynos4412-pinctrl.dtsi | 7 ++-----
arch/arm/boot/dts/exynos4412-ppmu-common.dtsi | 5 +----
arch/arm/boot/dts/exynos4412-prime.dtsi | 5 +----
arch/arm/boot/dts/exynos4412-smdk4412.dts | 7 ++-----
arch/arm/boot/dts/exynos4412.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5.dtsi | 5 +----
arch/arm/boot/dts/exynos5250-arndale.dts | 5 +----
arch/arm/boot/dts/exynos5250-pinctrl.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5250-smdk5250.dts | 5 +----
arch/arm/boot/dts/exynos5250-snow-common.dtsi | 5 +----
arch/arm/boot/dts/exynos5250-snow-rev5.dts | 5 +----
arch/arm/boot/dts/exynos5250-snow.dts | 5 +----
arch/arm/boot/dts/exynos5250-spring.dts | 5 +----
arch/arm/boot/dts/exynos5250.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5260-pinctrl.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5260-xyref5260.dts | 7 ++-----
arch/arm/boot/dts/exynos5260.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5410-odroidxu.dts | 5 +----
arch/arm/boot/dts/exynos5410-pinctrl.dtsi | 5 +----
arch/arm/boot/dts/exynos5410-smdk5410.dts | 7 ++-----
arch/arm/boot/dts/exynos5410.dtsi | 9 +--------
arch/arm/boot/dts/exynos5420-arndale-octa.dts | 7 ++-----
arch/arm/boot/dts/exynos5420-cpus.dtsi | 5 +----
arch/arm/boot/dts/exynos5420-peach-pit.dts | 5 +----
arch/arm/boot/dts/exynos5420-pinctrl.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5420-smdk5420.dts | 7 ++-----
arch/arm/boot/dts/exynos5420-tmu-sensor-conf.dtsi | 6 +-----
arch/arm/boot/dts/exynos5420-trip-points.dtsi | 6 +-----
arch/arm/boot/dts/exynos5420.dtsi | 5 +----
arch/arm/boot/dts/exynos5422-cpus.dtsi | 5 +----
arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5422-odroidhc1.dts | 7 ++-----
arch/arm/boot/dts/exynos5422-odroidxu3-audio.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 7 ++-----
arch/arm/boot/dts/exynos5422-odroidxu3-lite.dts | 7 ++-----
arch/arm/boot/dts/exynos5422-odroidxu3.dts | 7 ++-----
arch/arm/boot/dts/exynos5422-odroidxu4.dts | 7 ++-----
arch/arm/boot/dts/exynos5440-sd5v1.dts | 7 ++-----
arch/arm/boot/dts/exynos5440-ssdk5440.dts | 7 ++-----
arch/arm/boot/dts/exynos5440-tmu-sensor-conf.dtsi | 6 +-----
arch/arm/boot/dts/exynos5440-trip-points.dtsi | 6 +-----
arch/arm/boot/dts/exynos5440.dtsi | 7 ++-----
arch/arm/boot/dts/exynos54xx-odroidxu-leds.dtsi | 7 ++-----
arch/arm/boot/dts/exynos54xx.dtsi | 5 +----
arch/arm/boot/dts/s3c2416-pinctrl.dtsi | 5 +----
arch/arm/boot/dts/s3c2416-smdk2416.dts | 5 +----
arch/arm/boot/dts/s3c2416.dtsi | 5 +----
arch/arm/boot/dts/s3c24xx.dtsi | 5 +----
arch/arm/boot/dts/s3c6400.dtsi | 7 ++-----
arch/arm/boot/dts/s3c6410-mini6410.dts | 7 ++-----
arch/arm/boot/dts/s3c6410-smdk6410.dts | 7 ++-----
arch/arm/boot/dts/s3c6410.dtsi | 7 ++-----
arch/arm/boot/dts/s3c64xx-pinctrl.dtsi | 5 +----
arch/arm/boot/dts/s3c64xx.dtsi | 5 +----
arch/arm/boot/dts/s5pv210-aquila.dts | 5 +----
arch/arm/boot/dts/s5pv210-goni.dts | 5 +----
arch/arm/boot/dts/s5pv210-pinctrl.dtsi | 5 +----
arch/arm/boot/dts/s5pv210-smdkc110.dts | 5 +----
arch/arm/boot/dts/s5pv210-smdkv210.dts | 5 +----
arch/arm/boot/dts/s5pv210-torbreck.dts | 5 +----
arch/arm/boot/dts/s5pv210.dtsi | 7 ++-----
82 files changed, 121 insertions(+), 376 deletions(-)
^ permalink raw reply
* [GIT PULL 2/4] arm64: dts: exynos: Stuff for v4.16, 2nd round
From: Krzysztof Kozlowski @ 2018-01-07 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180107113625.15488-1-krzk@kernel.org>
Hi,
On top of previous pull request.
Best regards,
Krzysztof
The following changes since commit 3808354701090723b53c73afaccfcafdeb8a5bfe:
arm64: dts: exynos: Increase bus frequency for MHL chip (2017-12-04 17:51:10 +0100)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-dt64-4.16-2
for you to fetch changes up to 45fef752126603d591754befa63d0a800492eb6c:
arm64: dts: exynos: Add SPDX license identifiers (2018-01-03 18:16:35 +0100)
----------------------------------------------------------------
Samsung DTS ARM64 changes for v4.16, part 2
1. Fix DTC warnings around unit addresses.
2. Add SPDX license identifiers.
----------------------------------------------------------------
Krzysztof Kozlowski (3):
arm64: dts: exynos: Use lower case hex addresses in node unit addresses
arm64: dts: exynos: Fix typo in MSCL clock controller unit address of Exynos5433
arm64: dts: exynos: Add SPDX license identifiers
arch/arm64/boot/dts/exynos/exynos5433-bus.dtsi | 5 +----
arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 5 +----
arch/arm64/boot/dts/exynos/exynos5433-tm2-common.dtsi | 5 +----
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 5 +----
arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 5 +----
.../boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi | 5 +----
.../arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi | 5 +----
arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 5 +----
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 15 ++++++---------
arch/arm64/boot/dts/exynos/exynos7-espresso.dts | 7 ++-----
arch/arm64/boot/dts/exynos/exynos7-pinctrl.dtsi | 7 ++-----
arch/arm64/boot/dts/exynos/exynos7-tmu-sensor-conf.dtsi | 6 +-----
arch/arm64/boot/dts/exynos/exynos7-trip-points.dtsi | 6 +-----
arch/arm64/boot/dts/exynos/exynos7.dtsi | 9 +++------
14 files changed, 23 insertions(+), 67 deletions(-)
^ permalink raw reply
* [GIT PULL 4/4] ARM: exynos/samsung: Stuff for v4.16
From: Krzysztof Kozlowski @ 2018-01-07 11:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180107113625.15488-1-krzk@kernel.org>
The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git tags/samsung-soc-4.16-2
for you to fetch changes up to 4490e3c688d9e409a98189a6ea08bc2823d452e2:
ARM: SAMSUNG: Add SPDX license identifiers (2018-01-03 18:43:13 +0100)
----------------------------------------------------------------
Samsung mach/soc changes for v4.16
Add SPDX license identifiers.
----------------------------------------------------------------
Krzysztof Kozlowski (5):
ARM: EXYNOS: Add SPDX license identifiers
ARM: S3C24XX: Add SPDX license identifiers
ARM: S3C64XX: Add SPDX license identifiers
ARM: S5PV210: Add SPDX license identifiers
ARM: SAMSUNG: Add SPDX license identifiers
arch/arm/mach-exynos/Kconfig | 4 +--
arch/arm/mach-exynos/Makefile | 4 +--
arch/arm/mach-exynos/common.h | 5 +--
arch/arm/mach-exynos/exynos-smc.S | 5 +--
arch/arm/mach-exynos/exynos.c | 16 ++++-----
arch/arm/mach-exynos/firmware.c | 14 +++-----
arch/arm/mach-exynos/headsmp.S | 6 +---
arch/arm/mach-exynos/include/mach/map.h | 7 ++--
arch/arm/mach-exynos/mcpm-exynos.c | 17 +++-------
arch/arm/mach-exynos/platsmp.c | 21 +++++-------
arch/arm/mach-exynos/pm.c | 24 ++++++-------
arch/arm/mach-exynos/sleep.S | 11 +-----
arch/arm/mach-exynos/smc.h | 5 +--
arch/arm/mach-exynos/suspend.c | 24 ++++++-------
arch/arm/mach-s3c24xx/Kconfig | 4 +--
arch/arm/mach-s3c24xx/Makefile | 4 +--
arch/arm/mach-s3c24xx/Makefile.boot | 2 ++
arch/arm/mach-s3c24xx/anubis.h | 7 ++--
arch/arm/mach-s3c24xx/bast-ide.c | 17 ++++------
arch/arm/mach-s3c24xx/bast-irq.c | 28 ++++------------
arch/arm/mach-s3c24xx/bast.h | 7 ++--
arch/arm/mach-s3c24xx/common-smdk.c | 21 +++++-------
arch/arm/mach-s3c24xx/common-smdk.h | 7 ++--
arch/arm/mach-s3c24xx/common.c | 29 ++++------------
arch/arm/mach-s3c24xx/common.h | 5 +--
arch/arm/mach-s3c24xx/cpufreq-utils.c | 18 ++++------
arch/arm/mach-s3c24xx/fb-core.h | 5 +--
arch/arm/mach-s3c24xx/gta02.h | 7 ++--
arch/arm/mach-s3c24xx/h1940-bluetooth.c | 16 +++------
arch/arm/mach-s3c24xx/h1940.h | 7 ++--
arch/arm/mach-s3c24xx/include/mach/dma.h | 10 ++----
arch/arm/mach-s3c24xx/include/mach/fb.h | 1 +
arch/arm/mach-s3c24xx/include/mach/gpio-samsung.h | 7 ++--
arch/arm/mach-s3c24xx/include/mach/hardware.h | 7 ++--
arch/arm/mach-s3c24xx/include/mach/irqs.h | 10 ++----
arch/arm/mach-s3c24xx/include/mach/map.h | 10 ++----
arch/arm/mach-s3c24xx/include/mach/pm-core.h | 9 ++---
arch/arm/mach-s3c24xx/include/mach/regs-clock.h | 10 ++----
arch/arm/mach-s3c24xx/include/mach/regs-gpio.h | 10 ++----
arch/arm/mach-s3c24xx/include/mach/regs-irq.h | 10 ++----
arch/arm/mach-s3c24xx/include/mach/regs-lcd.h | 11 ++----
.../mach-s3c24xx/include/mach/regs-s3c2443-clock.h | 10 ++----
arch/arm/mach-s3c24xx/include/mach/rtc-core.h | 7 ++--
arch/arm/mach-s3c24xx/include/mach/s3c2412.h | 5 +--
arch/arm/mach-s3c24xx/iotiming-s3c2410.c | 18 ++++------
arch/arm/mach-s3c24xx/iotiming-s3c2412.c | 18 ++++------
arch/arm/mach-s3c24xx/irq-pm.c | 19 ++++-------
arch/arm/mach-s3c24xx/mach-amlm5900.c | 35 +++++--------------
arch/arm/mach-s3c24xx/mach-anubis.c | 15 +++------
arch/arm/mach-s3c24xx/mach-at2440evb.c | 21 +++++-------
arch/arm/mach-s3c24xx/mach-bast.c | 17 ++++------
arch/arm/mach-s3c24xx/mach-gta02.c | 33 +++++-------------
arch/arm/mach-s3c24xx/mach-h1940.c | 17 ++++------
arch/arm/mach-s3c24xx/mach-jive.c | 17 ++++------
arch/arm/mach-s3c24xx/mach-mini2440.c | 23 +++++--------
arch/arm/mach-s3c24xx/mach-n30.c | 27 +++++++--------
arch/arm/mach-s3c24xx/mach-nexcoder.c | 22 +++++-------
arch/arm/mach-s3c24xx/mach-osiris-dvs.c | 19 ++++-------
arch/arm/mach-s3c24xx/mach-osiris.c | 14 +++-----
arch/arm/mach-s3c24xx/mach-otom.c | 13 +++-----
arch/arm/mach-s3c24xx/mach-qt2410.c | 27 +++------------
arch/arm/mach-s3c24xx/mach-rx1950.c | 17 ++++------
arch/arm/mach-s3c24xx/mach-rx3715.c | 18 ++++------
arch/arm/mach-s3c24xx/mach-s3c2416-dt.c | 28 +++++++---------
arch/arm/mach-s3c24xx/mach-smdk2410.c | 39 ++++++----------------
arch/arm/mach-s3c24xx/mach-smdk2413.c | 19 ++++-------
arch/arm/mach-s3c24xx/mach-smdk2416.c | 18 ++++------
arch/arm/mach-s3c24xx/mach-smdk2440.c | 23 +++++--------
arch/arm/mach-s3c24xx/mach-smdk2443.c | 22 +++++-------
arch/arm/mach-s3c24xx/mach-tct_hammer.c | 33 +++++-------------
arch/arm/mach-s3c24xx/mach-vr1000.c | 19 ++++-------
arch/arm/mach-s3c24xx/mach-vstms.c | 15 +++------
arch/arm/mach-s3c24xx/nand-core.h | 7 ++--
arch/arm/mach-s3c24xx/osiris.h | 7 ++--
arch/arm/mach-s3c24xx/otom.h | 7 ++--
arch/arm/mach-s3c24xx/pll-s3c2410.c | 30 +++++------------
arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c | 20 +++++------
arch/arm/mach-s3c24xx/pll-s3c2440-16934400.c | 20 +++++------
arch/arm/mach-s3c24xx/pm-h1940.S | 19 ++---------
arch/arm/mach-s3c24xx/pm-s3c2410.c | 27 ++++-----------
arch/arm/mach-s3c24xx/pm-s3c2412.c | 17 ++++------
arch/arm/mach-s3c24xx/pm-s3c2416.c | 17 ++++------
arch/arm/mach-s3c24xx/pm.c | 39 +++++++---------------
arch/arm/mach-s3c24xx/regs-dsc.h | 7 ++--
arch/arm/mach-s3c24xx/regs-mem.h | 5 +--
arch/arm/mach-s3c24xx/s3c2410.c | 17 ++++------
arch/arm/mach-s3c24xx/s3c2412-power.h | 5 +--
arch/arm/mach-s3c24xx/s3c2412.c | 16 ++++-----
arch/arm/mach-s3c24xx/s3c2416.c | 31 +++++------------
arch/arm/mach-s3c24xx/s3c2440.c | 17 ++++------
arch/arm/mach-s3c24xx/s3c2442.c | 29 ++++------------
arch/arm/mach-s3c24xx/s3c2443.c | 17 ++++------
arch/arm/mach-s3c24xx/s3c244x.c | 17 ++++------
arch/arm/mach-s3c24xx/setup-camif.c | 14 +++-----
arch/arm/mach-s3c24xx/setup-i2c.c | 17 ++++------
arch/arm/mach-s3c24xx/setup-sdhci-gpio.c | 21 +++++-------
arch/arm/mach-s3c24xx/setup-spi.c | 16 ++++-----
arch/arm/mach-s3c24xx/setup-ts.c | 17 ++++------
arch/arm/mach-s3c24xx/simtec-audio.c | 19 ++++-------
arch/arm/mach-s3c24xx/simtec-nor.c | 19 ++++-------
arch/arm/mach-s3c24xx/simtec-pm.c | 21 +++++-------
arch/arm/mach-s3c24xx/simtec-usb.c | 21 +++++-------
arch/arm/mach-s3c24xx/simtec.h | 10 ++----
arch/arm/mach-s3c24xx/sleep-s3c2410.S | 20 ++---------
arch/arm/mach-s3c24xx/sleep-s3c2412.S | 20 ++---------
arch/arm/mach-s3c24xx/sleep.S | 20 ++---------
arch/arm/mach-s3c24xx/spi-core.h | 5 +--
arch/arm/mach-s3c24xx/vr1000.h | 11 ++----
arch/arm/mach-s3c64xx/Kconfig | 5 +--
arch/arm/mach-s3c64xx/Makefile | 4 +--
arch/arm/mach-s3c64xx/ata-core.h | 7 ++--
arch/arm/mach-s3c64xx/backlight.h | 5 +--
arch/arm/mach-s3c64xx/common.c | 26 ++++++---------
arch/arm/mach-s3c64xx/common.h | 5 +--
arch/arm/mach-s3c64xx/cpuidle.c | 15 +++------
arch/arm/mach-s3c64xx/crag6410.h | 5 +--
arch/arm/mach-s3c64xx/dev-audio.c | 13 +++-----
arch/arm/mach-s3c64xx/dev-backlight.c | 16 ++++-----
arch/arm/mach-s3c64xx/dev-uart.c | 22 +++++-------
arch/arm/mach-s3c64xx/include/mach/gpio-samsung.h | 7 ++--
arch/arm/mach-s3c64xx/include/mach/hardware.h | 1 +
arch/arm/mach-s3c64xx/include/mach/map.h | 10 ++----
arch/arm/mach-s3c64xx/include/mach/pm-core.h | 8 ++---
arch/arm/mach-s3c64xx/include/mach/regs-clock.h | 10 ++----
arch/arm/mach-s3c64xx/include/mach/regs-irq.h | 10 ++----
arch/arm/mach-s3c64xx/irq-pm.c | 21 +++++-------
arch/arm/mach-s3c64xx/irq-uart.h | 7 ++--
arch/arm/mach-s3c64xx/mach-anw6410.c | 22 +++++-------
arch/arm/mach-s3c64xx/mach-crag6410-module.c | 15 ++++-----
arch/arm/mach-s3c64xx/mach-crag6410.c | 19 ++++-------
arch/arm/mach-s3c64xx/mach-hmt.c | 14 +++-----
arch/arm/mach-s3c64xx/mach-mini6410.c | 20 ++++-------
arch/arm/mach-s3c64xx/mach-ncp.c | 13 ++------
arch/arm/mach-s3c64xx/mach-real6410.c | 20 ++++-------
arch/arm/mach-s3c64xx/mach-s3c64xx-dt.c | 14 +++-----
arch/arm/mach-s3c64xx/mach-smartq.c | 13 ++------
arch/arm/mach-s3c64xx/mach-smartq.h | 6 +---
arch/arm/mach-s3c64xx/mach-smartq5.c | 13 ++------
arch/arm/mach-s3c64xx/mach-smartq7.c | 13 ++------
arch/arm/mach-s3c64xx/mach-smdk6400.c | 15 +++------
arch/arm/mach-s3c64xx/mach-smdk6410.c | 18 ++++------
arch/arm/mach-s3c64xx/onenand-core.h | 7 ++--
arch/arm/mach-s3c64xx/pl080.c | 14 +++-----
arch/arm/mach-s3c64xx/pm.c | 21 +++++-------
arch/arm/mach-s3c64xx/regs-modem.h | 7 ++--
arch/arm/mach-s3c64xx/regs-srom.h | 7 ++--
arch/arm/mach-s3c64xx/s3c6400.c | 15 +++------
arch/arm/mach-s3c64xx/s3c6410.c | 17 ++++------
arch/arm/mach-s3c64xx/setup-fb-24bpp.c | 21 +++++-------
arch/arm/mach-s3c64xx/setup-i2c0.c | 21 +++++-------
arch/arm/mach-s3c64xx/setup-i2c1.c | 21 +++++-------
arch/arm/mach-s3c64xx/setup-ide.c | 17 ++++------
arch/arm/mach-s3c64xx/setup-keypad.c | 17 ++++------
arch/arm/mach-s3c64xx/setup-sdhci-gpio.c | 19 ++++-------
arch/arm/mach-s3c64xx/setup-spi.c | 13 +++-----
arch/arm/mach-s3c64xx/setup-usb-phy.c | 14 +++-----
arch/arm/mach-s3c64xx/sleep.S | 7 ++--
arch/arm/mach-s3c64xx/watchdog-reset.h | 7 ++--
arch/arm/mach-s5pv210/Kconfig | 4 +--
arch/arm/mach-s5pv210/Makefile | 4 +--
arch/arm/mach-s5pv210/common.h | 5 +--
arch/arm/mach-s5pv210/pm.c | 25 ++++++--------
arch/arm/mach-s5pv210/regs-clock.h | 7 ++--
arch/arm/mach-s5pv210/s5pv210.c | 18 ++++------
arch/arm/mach-s5pv210/sleep.S | 6 +---
arch/arm/plat-samsung/Kconfig | 4 +--
arch/arm/plat-samsung/Makefile | 4 +--
arch/arm/plat-samsung/adc.c | 19 ++++-------
arch/arm/plat-samsung/cpu.c | 17 ++++------
arch/arm/plat-samsung/dev-uart.c | 21 +++++-------
arch/arm/plat-samsung/devs.c | 17 ++++------
arch/arm/plat-samsung/gpio-samsung.c | 26 ++++++---------
arch/arm/plat-samsung/include/plat/adc-core.h | 10 ++----
arch/arm/plat-samsung/include/plat/adc.h | 10 ++----
arch/arm/plat-samsung/include/plat/cpu-freq-core.h | 10 ++----
arch/arm/plat-samsung/include/plat/cpu-freq.h | 10 ++----
arch/arm/plat-samsung/include/plat/cpu.h | 10 ++----
arch/arm/plat-samsung/include/plat/devs.h | 10 ++----
arch/arm/plat-samsung/include/plat/fb-s3c2410.h | 8 ++---
arch/arm/plat-samsung/include/plat/fb.h | 10 ++----
.../plat-samsung/include/plat/gpio-cfg-helpers.h | 10 ++----
arch/arm/plat-samsung/include/plat/gpio-cfg.h | 10 ++----
arch/arm/plat-samsung/include/plat/gpio-core.h | 10 ++----
arch/arm/plat-samsung/include/plat/iic-core.h | 10 ++----
arch/arm/plat-samsung/include/plat/keypad.h | 6 +---
arch/arm/plat-samsung/include/plat/map-base.h | 10 ++----
arch/arm/plat-samsung/include/plat/map-s3c.h | 10 ++----
arch/arm/plat-samsung/include/plat/map-s5p.h | 10 ++----
arch/arm/plat-samsung/include/plat/pm-common.h | 7 ++--
arch/arm/plat-samsung/include/plat/pm.h | 10 ++----
arch/arm/plat-samsung/include/plat/pwm-core.h | 5 +--
arch/arm/plat-samsung/include/plat/regs-adc.h | 10 ++----
arch/arm/plat-samsung/include/plat/regs-irqtype.h | 8 ++---
arch/arm/plat-samsung/include/plat/regs-spi.h | 10 ++----
arch/arm/plat-samsung/include/plat/regs-udc.h | 11 ++----
arch/arm/plat-samsung/include/plat/samsung-time.h | 10 ++----
arch/arm/plat-samsung/include/plat/sdhci.h | 10 ++----
arch/arm/plat-samsung/include/plat/usb-phy.h | 6 +---
arch/arm/plat-samsung/include/plat/wakeup-mask.h | 11 ++----
arch/arm/plat-samsung/init.c | 19 ++++-------
arch/arm/plat-samsung/platformdata.c | 15 +++------
arch/arm/plat-samsung/pm-check.c | 22 +++++-------
arch/arm/plat-samsung/pm-common.c | 24 ++++++-------
arch/arm/plat-samsung/pm-debug.c | 24 ++++++-------
arch/arm/plat-samsung/pm-gpio.c | 22 +++++-------
arch/arm/plat-samsung/pm.c | 21 +++++-------
arch/arm/plat-samsung/wakeup-mask.c | 15 +++------
arch/arm/plat-samsung/watchdog-reset.c | 21 +++++-------
208 files changed, 962 insertions(+), 1999 deletions(-)
^ permalink raw reply
* [PATCH v2 1/6] ARM: at91: add TCB registers definitions
From: Philippe Ombredanne @ 2018-01-07 11:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180105143006.5369-2-alexandre.belloni@free-electrons.com>
On Fri, Jan 5, 2018 at 3:30 PM, Alexandre Belloni
<alexandre.belloni@free-electrons.com> wrote:
> Add registers and bits definitions for the timer counter blocks found on
> Atmel ARM SoCs.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> include/soc/at91/atmel_tcb.h | 229 +++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 229 insertions(+)
> create mode 100644 include/soc/at91/atmel_tcb.h
>
> diff --git a/include/soc/at91/atmel_tcb.h b/include/soc/at91/atmel_tcb.h
> new file mode 100644
> index 000000000000..f48e60f8ab92
> --- /dev/null
> +++ b/include/soc/at91/atmel_tcb.h
> @@ -0,0 +1,229 @@
> +/*
> + * Copyright (C) 2016 Atmel
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License version 2 as published by
> + * the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + *
> + * You should have received a copy of the GNU General Public License along with
> + * this program. If not, see <http://www.gnu.org/licenses/>.
> + */
Alexandre,
Would you mind using SPDx tags here like you did in
/drivers/clocksource/timer-atmel-tcb.c ?
Thanks!
--
Cordially
Philippe Ombredanne
^ permalink raw reply
* [PATCH] Revert "ARM: dts: bcm283x: Fix DTC warnings about missing phy-cells"
From: Stefan Wahren @ 2018-01-07 13:36 UTC (permalink / raw)
To: linux-arm-kernel
This reverts commit 014d6da6cb2525d7f48fb08c705cb130cc7b5f4a.
The DT clean up could trigger an endless deferred probe of DWC2 USB driver
on the Raspberry Pi 2/3. So revert the change until we fixed the probing
issue.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
Hi Arnd,
hi Olof,
i hope this has a chance to get into 4.15.
arch/arm/boot/dts/bcm283x.dtsi | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index dcde93c..013431e 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -639,6 +639,5 @@
usbphy: phy {
compatible = "usb-nop-xceiv";
- #phy-cells = <0>;
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH] soc: imx: gpc: de-register power domains only if initialized
From: Stefan Agner @ 2018-01-07 13:49 UTC (permalink / raw)
To: linux-arm-kernel
If power domain information are missing in the device tree, no
power domains get initialized. However, imx_gpc_remove tries to
remove power domains always in the old DT binding case. Only
remove power domains when imx_gpc_probe initialized them in
first place.
Fixes: 721cabf6c660 ("soc: imx: move PGC handling to a new GPC driver")
Cc: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Stefan Agner <stefan@agner.ch>
---
drivers/soc/imx/gpc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/gpc.c b/drivers/soc/imx/gpc.c
index 53f7275d6cbd..62bb724726d9 100644
--- a/drivers/soc/imx/gpc.c
+++ b/drivers/soc/imx/gpc.c
@@ -470,13 +470,21 @@ static int imx_gpc_probe(struct platform_device *pdev)
static int imx_gpc_remove(struct platform_device *pdev)
{
+ struct device_node *pgc_node;
int ret;
+ pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
+
+ /* bail out if DT too old and doesn't provide the necessary info */
+ if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
+ !pgc_node)
+ return 0;
+
/*
* If the old DT binding is used the toplevel driver needs to
* de-register the power domains
*/
- if (!of_get_child_by_name(pdev->dev.of_node, "pgc")) {
+ if (!pgc_node) {
of_genpd_del_provider(pdev->dev.of_node);
ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
--
2.15.1
^ permalink raw reply related
* [PATCH v6 10/10] clocksource: timer-dm: Check prescaler value
From: Keerthy @ 2018-01-07 15:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180104224713.GA11557@lenoch>
On 1/5/2018 4:17 AM, Ladislav Michl wrote:
> On Tue, Jan 02, 2018 at 03:39:59PM +0530, Keerthy wrote:
>> From: Ladislav Michl <ladis@linux-mips.org>
>>
>> Invalid prescaler value is silently ignored. Fix that
>> by returning -EINVAL in such case. As invalid value
>> disabled use of the prescaler, use -1 explicitely for
>> that purpose.
>>
>> Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
>> ---
>> drivers/clocksource/timer-dm.c | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/clocksource/timer-dm.c b/drivers/clocksource/timer-dm.c
>> index 60db173..01a9cb0 100644
>> --- a/drivers/clocksource/timer-dm.c
>> +++ b/drivers/clocksource/timer-dm.c
>> @@ -672,6 +672,9 @@ int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
>> if (prescaler >= 0x00 && prescaler <= 0x07) {
>> l |= OMAP_TIMER_CTRL_PRE;
>> l |= prescaler << 2;
>> + } else {
>> + if (prescaler != -1)
>> + return -EINVAL;
>
> Argh... This is actually wrong, as it leaves timer enabled.
> I suggest simply dropping this patch and I'll rethink whole
> approach a bit later (and better).
Okay. I hope the rest 9 patches work well for you.
>
>> }
>> omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
>>
>
> Sorry for the noise,
> ladis
>
^ permalink raw reply
* [PATCH v6 00/10] omap: dmtimer: Move driver out of plat-omap
From: Keerthy @ 2018-01-07 15:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514887799-24605-1-git-send-email-j-keerthy@ti.com>
On 1/2/2018 3:39 PM, Keerthy wrote:
> The series moves dmtimer out of plat-omap to drivers/clocksource.
> The series also does a bunch of changes to pwm-omap-dmtimer code
> to adapt to the driver migration and clean up plat specific
> pdata-quirks and use the dmtimer platform data.
>
> Boot tested on DRA7-EVM and AM437X-GP-EVM.
> Compile tested omap1_defconfig.
>
> This is based on top of linux-next branch.
>
> This is tested on on IGEPv2 (OMAP3430 based) by Ladis.
Daniel/Theirry,
Let me know if you have any comments on this migration series.
Patch 10/10 from Ladis can be dropped as he plans to rework on that.
Regards,
Keerthy
>
> Changes from V5:
>
> * Added couple of fixes from Ladis for pwm-dmtimer.
>
> Changes from v4:
>
> * Made OMAP_DM_TIMER config option silent.
> * Changed the driver name to timer-dm.c
>
> Changes from v3:
>
> * Reverted to v2 approach of using dev_get_platdata to fetch dmtimer ops.
>
> Changes from V2:
>
> * Wrapped the inline functions in header file under OMAP2PLUS
> * Added a new of helper function to fetch plat_data from of node.
>
> Keerthy (8):
> clocksource: dmtimer: Remove all the exports
> arm: omap: timer: Wrap the inline functions under OMAP2PLUS define
> arm: omap: Move dmtimer.h out of plat-omap
> arm: OMAP: Move dmtimer driver out of plat-omap to drivers under
> clocksource
> dmtimer: Add timer ops to the platform data structure
> clocksource: dmtimer: Populate the timer ops to the pdata
> pwm: pwm-omap-dmtimer: Adapt driver to utilize dmtimer pdata ops
> arm: omap: pdata-quirks: Remove unused timer pdata
>
> Ladislav Michl (2):
> clocksource: timer-dm: Hook device platform data if not already
> assigned
> clocksource: timer-dm: Check prescaler value
>
> arch/arm/mach-omap1/pm.c | 2 +-
> arch/arm/mach-omap1/timer.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_2420_data.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_2430_data.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_3xxx_data.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_44xx_data.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_54xx_data.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 2 +-
> arch/arm/mach-omap2/omap_hwmod_81xx_data.c | 2 +-
> arch/arm/mach-omap2/pdata-quirks.c | 32 -----------
> arch/arm/mach-omap2/timer.c | 2 +-
> arch/arm/plat-omap/Kconfig | 6 --
> arch/arm/plat-omap/Makefile | 1 -
> drivers/clocksource/Kconfig | 3 +
> drivers/clocksource/Makefile | 1 +
> .../dmtimer.c => drivers/clocksource/timer-dm.c | 67 +++++++++++-----------
> drivers/pwm/pwm-omap-dmtimer.c | 39 +++++++------
> .../include/plat => include/clocksource}/dmtimer.h | 8 ++-
> include/linux/platform_data/dmtimer-omap.h | 38 ++++++++++++
> 20 files changed, 117 insertions(+), 100 deletions(-)
> rename arch/arm/plat-omap/dmtimer.c => drivers/clocksource/timer-dm.c (94%)
> rename {arch/arm/plat-omap/include/plat => include/clocksource}/dmtimer.h (97%)
>
^ permalink raw reply
* [PATCH 6/7] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file
From: Philippe Ombredanne @ 2018-01-07 16:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106050910.48070-1-icenowy@aosc.io>
On Sat, Jan 6, 2018 at 6:09 AM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
> memory map fully reworked and some high-speed peripherals (PCIe, USB
> 3.0) introduced.
>
> This commit adds the basical DTSI file of it, including the clock
> support and UART support.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 214 +++++++++++++++++++++++++++
> 1 file changed, 214 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> new file mode 100644
> index 000000000000..482f5cb64d07
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -0,0 +1,214 @@
> +/*
> + * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
Icenowy,
This is a very long legalese indeed!
Do you mind using the new concise SPDX tags instead here and in the
rest of your patch?
See Thomas doc [1]
Thanks!
[1] https://lkml.org/lkml/2017/12/28/323
--
Cordially
Philippe Ombredanne
^ permalink raw reply
* [PATCH v2 1/2] mtd: spi-nor: cadence-quadspi: Refactor indirect read/write sequence.
From: Cyrille Pitchen @ 2018-01-07 18:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171229091103.14436-2-vigneshr@ti.com>
Le 29/12/2017 ? 10:11, Vignesh R a ?crit?:
> Move configuring of indirect read/write start address to
> cqspi_indirect_*_execute() function and rename cqspi_indirect_*_setup()
> function. This will help to reuse cqspi_indirect_*_setup() function for
> supporting direct access mode.
>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
Applied to the spi-nor/next branch of linux-mtd after removing the one
too many empty line in cqspi_read_setup() (see below).
Thanks!
> ---
>
> v2: No changes.
>
> drivers/mtd/spi-nor/cadence-quadspi.c | 27 ++++++++++++---------------
> 1 file changed, 12 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index 75a2bc447a99..becc7d714ab8 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -450,8 +450,7 @@ static int cqspi_command_write_addr(struct spi_nor *nor,
> return cqspi_exec_flash_cmd(cqspi, reg);
> }
>
> -static int cqspi_indirect_read_setup(struct spi_nor *nor,
> - const unsigned int from_addr)
> +static int cqspi_read_setup(struct spi_nor *nor)
> {
> struct cqspi_flash_pdata *f_pdata = nor->priv;
> struct cqspi_st *cqspi = f_pdata->cqspi;
> @@ -459,7 +458,6 @@ static int cqspi_indirect_read_setup(struct spi_nor *nor,
> unsigned int dummy_clk = 0;
> unsigned int reg;
>
> - writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
>
removed the above empty line ;)
> reg = nor->read_opcode << CQSPI_REG_RD_INSTR_OPCODE_LSB;
> reg |= cqspi_calc_rdreg(nor, nor->read_opcode);
> @@ -493,8 +491,8 @@ static int cqspi_indirect_read_setup(struct spi_nor *nor,
> return 0;
> }
>
> -static int cqspi_indirect_read_execute(struct spi_nor *nor,
> - u8 *rxbuf, const unsigned n_rx)
> +static int cqspi_indirect_read_execute(struct spi_nor *nor, u8 *rxbuf,
> + loff_t from_addr, const size_t n_rx)
> {
> struct cqspi_flash_pdata *f_pdata = nor->priv;
> struct cqspi_st *cqspi = f_pdata->cqspi;
> @@ -504,6 +502,7 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor,
> unsigned int bytes_to_read = 0;
> int ret = 0;
>
> + writel(from_addr, reg_base + CQSPI_REG_INDIRECTRDSTARTADDR);
> writel(remaining, reg_base + CQSPI_REG_INDIRECTRDBYTES);
>
> /* Clear all interrupts. */
> @@ -570,8 +569,7 @@ static int cqspi_indirect_read_execute(struct spi_nor *nor,
> return ret;
> }
>
> -static int cqspi_indirect_write_setup(struct spi_nor *nor,
> - const unsigned int to_addr)
> +static int cqspi_write_setup(struct spi_nor *nor)
> {
> unsigned int reg;
> struct cqspi_flash_pdata *f_pdata = nor->priv;
> @@ -584,8 +582,6 @@ static int cqspi_indirect_write_setup(struct spi_nor *nor,
> reg = cqspi_calc_rdreg(nor, nor->program_opcode);
> writel(reg, reg_base + CQSPI_REG_RD_INSTR);
>
> - writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
> -
> reg = readl(reg_base + CQSPI_REG_SIZE);
> reg &= ~CQSPI_REG_SIZE_ADDRESS_MASK;
> reg |= (nor->addr_width - 1);
> @@ -593,8 +589,8 @@ static int cqspi_indirect_write_setup(struct spi_nor *nor,
> return 0;
> }
>
> -static int cqspi_indirect_write_execute(struct spi_nor *nor,
> - const u8 *txbuf, const unsigned n_tx)
> +static int cqspi_indirect_write_execute(struct spi_nor *nor, loff_t to_addr,
> + const u8 *txbuf, const size_t n_tx)
> {
> const unsigned int page_size = nor->page_size;
> struct cqspi_flash_pdata *f_pdata = nor->priv;
> @@ -604,6 +600,7 @@ static int cqspi_indirect_write_execute(struct spi_nor *nor,
> unsigned int write_bytes;
> int ret;
>
> + writel(to_addr, reg_base + CQSPI_REG_INDIRECTWRSTARTADDR);
> writel(remaining, reg_base + CQSPI_REG_INDIRECTWRBYTES);
>
> /* Clear all interrupts. */
> @@ -900,11 +897,11 @@ static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
> if (ret)
> return ret;
>
> - ret = cqspi_indirect_write_setup(nor, to);
> + ret = cqspi_write_setup(nor);
> if (ret)
> return ret;
>
> - ret = cqspi_indirect_write_execute(nor, buf, len);
> + ret = cqspi_indirect_write_execute(nor, to, buf, len);
> if (ret)
> return ret;
>
> @@ -920,11 +917,11 @@ static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
> if (ret)
> return ret;
>
> - ret = cqspi_indirect_read_setup(nor, from);
> + ret = cqspi_read_setup(nor);
> if (ret)
> return ret;
>
> - ret = cqspi_indirect_read_execute(nor, buf, len);
> + ret = cqspi_indirect_read_execute(nor, buf, from, len);
> if (ret)
> return ret;
>
>
^ permalink raw reply
* [PATCH v2 2/2] mtd: spi-nor: cadence-quadspi: Add support for direct access mode
From: Cyrille Pitchen @ 2018-01-07 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171229091103.14436-3-vigneshr@ti.com>
Le 29/12/2017 ? 10:11, Vignesh R a ?crit?:
> Cadence QSPI controller provides direct access mode through which flash
> can be accessed in a memory-mapped IO mode. This enables read/write to
> flash using memcpy*() functions. This mode provides higher throughput
> for both read/write operations when compared to current indirect mode of
> operation.
>
> This patch therefore adds support to use QSPI in direct mode. If the
> window reserved in SoC's memory map for MMIO access is less that of
> flash size(like on most SoCFPGA variants), then the driver falls back
> to indirect mode of operation.
>
> On TI's 66AK2G SoC, with ARM running at 600MHz and QSPI at 96MHz
> switching to direct mode improves read throughput from 3MB/s to 8MB/s.
>
> Signed-off-by: Vignesh R <vigneshr@ti.com>
Applied to the spi-nor/next branch of linux-mtd
Thanks!
> ---
>
> v2: enable direct access controller during controller init.
>
> drivers/mtd/spi-nor/cadence-quadspi.c | 31 +++++++++++++++++++++++++++++--
> 1 file changed, 29 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
> index becc7d714ab8..f693a57ebbd6 100644
> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
> @@ -58,6 +58,7 @@ struct cqspi_flash_pdata {
> u8 data_width;
> u8 cs;
> bool registered;
> + bool use_direct_mode;
> };
>
> struct cqspi_st {
> @@ -68,6 +69,7 @@ struct cqspi_st {
>
> void __iomem *iobase;
> void __iomem *ahb_base;
> + resource_size_t ahb_size;
> struct completion transfer_complete;
> struct mutex bus_mutex;
>
> @@ -103,6 +105,7 @@ struct cqspi_st {
> /* Register map */
> #define CQSPI_REG_CONFIG 0x00
> #define CQSPI_REG_CONFIG_ENABLE_MASK BIT(0)
> +#define CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL BIT(7)
> #define CQSPI_REG_CONFIG_DECODE_MASK BIT(9)
> #define CQSPI_REG_CONFIG_CHIPSELECT_LSB 10
> #define CQSPI_REG_CONFIG_DMA_MASK BIT(15)
> @@ -891,6 +894,8 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
> static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
> size_t len, const u_char *buf)
> {
> + struct cqspi_flash_pdata *f_pdata = nor->priv;
> + struct cqspi_st *cqspi = f_pdata->cqspi;
> int ret;
>
> ret = cqspi_set_protocol(nor, 0);
> @@ -901,7 +906,10 @@ static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
> if (ret)
> return ret;
>
> - ret = cqspi_indirect_write_execute(nor, to, buf, len);
> + if (f_pdata->use_direct_mode)
> + memcpy_toio(cqspi->ahb_base + to, buf, len);
> + else
> + ret = cqspi_indirect_write_execute(nor, to, buf, len);
> if (ret)
> return ret;
>
> @@ -911,6 +919,8 @@ static ssize_t cqspi_write(struct spi_nor *nor, loff_t to,
> static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
> size_t len, u_char *buf)
> {
> + struct cqspi_flash_pdata *f_pdata = nor->priv;
> + struct cqspi_st *cqspi = f_pdata->cqspi;
> int ret;
>
> ret = cqspi_set_protocol(nor, 1);
> @@ -921,7 +931,10 @@ static ssize_t cqspi_read(struct spi_nor *nor, loff_t from,
> if (ret)
> return ret;
>
> - ret = cqspi_indirect_read_execute(nor, buf, from, len);
> + if (f_pdata->use_direct_mode)
> + memcpy_fromio(buf, cqspi->ahb_base + from, len);
> + else
> + ret = cqspi_indirect_read_execute(nor, buf, from, len);
> if (ret)
> return ret;
>
> @@ -1056,6 +1069,8 @@ static int cqspi_of_get_pdata(struct platform_device *pdev)
>
> static void cqspi_controller_init(struct cqspi_st *cqspi)
> {
> + u32 reg;
> +
> cqspi_controller_enable(cqspi, 0);
>
> /* Configure the remap address register, no remap */
> @@ -1078,6 +1093,11 @@ static void cqspi_controller_init(struct cqspi_st *cqspi)
> writel(cqspi->fifo_depth * cqspi->fifo_width / 8,
> cqspi->iobase + CQSPI_REG_INDIRECTWRWATERMARK);
>
> + /* Enable Direct Access Controller */
> + reg = readl(cqspi->iobase + CQSPI_REG_CONFIG);
> + reg |= CQSPI_REG_CONFIG_ENB_DIR_ACC_CTRL;
> + writel(reg, cqspi->iobase + CQSPI_REG_CONFIG);
> +
> cqspi_controller_enable(cqspi, 1);
> }
>
> @@ -1153,6 +1173,12 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
> goto err;
>
> f_pdata->registered = true;
> +
> + if (mtd->size <= cqspi->ahb_size) {
> + f_pdata->use_direct_mode = true;
> + dev_dbg(nor->dev, "using direct mode for %s\n",
> + mtd->name);
> + }
> }
>
> return 0;
> @@ -1212,6 +1238,7 @@ static int cqspi_probe(struct platform_device *pdev)
> dev_err(dev, "Cannot remap AHB address.\n");
> return PTR_ERR(cqspi->ahb_base);
> }
> + cqspi->ahb_size = resource_size(res_ahb);
>
> init_completion(&cqspi->transfer_complete);
>
>
^ permalink raw reply
* [PATCH v2 3/6] clocksource/drivers: atmel-pit: allow unselecting ATMEL_PIT
From: Daniel Lezcano @ 2018-01-07 18:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180105143006.5369-4-alexandre.belloni@free-electrons.com>
On 05/01/2018 15:30, Alexandre Belloni wrote:
> With the new TCB clocksource driver, atmel platforms are now able to boot
> without the PIT driver. Allow unselecting it.
>
> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> ---
> drivers/clocksource/Kconfig | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 5609572e0236..55ccfa0ba63b 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -381,7 +381,14 @@ config ARMV7M_SYSTICK
>
> config ATMEL_PIT
> select TIMER_OF if OF
> - def_bool SOC_AT91SAM9 || SOC_SAMA5
> + bool "Atmel Periodic Interval Timer (PIT)"
> + depends on SOC_AT91SAM9 || SOC_SAMA5
> + default SOC_AT91SAM9 || SOC_SAMA5
> + help
> + Select this to get a clocksource based on the Atmel Periodic Interval
> + Timer. It has a relatively low resolution and the TC Block clocksource
> + should be preferred.
> + It also provides a clock event device.
Please conform to the format:
config ATMEL_PIT
bool "Atmel Periodic Interval Timer (PIT)" if COMPILE_TEST
select ...
help
bla bla
and select ATMEL_PIT from the platform's Kconfig.
> config ATMEL_ST
> bool "Atmel ST timer support" if COMPILE_TEST
>
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH v2 3/6] clocksource/drivers: atmel-pit: allow unselecting ATMEL_PIT
From: Alexandre Belloni @ 2018-01-07 18:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <64398ab7-fbc6-0313-ccc6-51ff02d087e6@linaro.org>
On 07/01/2018 at 19:07:13 +0100, Daniel Lezcano wrote:
> On 05/01/2018 15:30, Alexandre Belloni wrote:
> > With the new TCB clocksource driver, atmel platforms are now able to boot
> > without the PIT driver. Allow unselecting it.
> >
> > Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> > ---
> > drivers/clocksource/Kconfig | 9 ++++++++-
> > 1 file changed, 8 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> > index 5609572e0236..55ccfa0ba63b 100644
> > --- a/drivers/clocksource/Kconfig
> > +++ b/drivers/clocksource/Kconfig
> > @@ -381,7 +381,14 @@ config ARMV7M_SYSTICK
> >
> > config ATMEL_PIT
> > select TIMER_OF if OF
> > - def_bool SOC_AT91SAM9 || SOC_SAMA5
> > + bool "Atmel Periodic Interval Timer (PIT)"
> > + depends on SOC_AT91SAM9 || SOC_SAMA5
> > + default SOC_AT91SAM9 || SOC_SAMA5
> > + help
> > + Select this to get a clocksource based on the Atmel Periodic Interval
> > + Timer. It has a relatively low resolution and the TC Block clocksource
> > + should be preferred.
> > + It also provides a clock event device.
>
> Please conform to the format:
>
> config ATMEL_PIT
> bool "Atmel Periodic Interval Timer (PIT)" if COMPILE_TEST
> select ...
> help
> bla bla
>
> and select ATMEL_PIT from the platform's Kconfig.
>
Well, the goal is actually to allow people to unselect it so we don't
want the platform to select it.
--
Alexandre Belloni, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [arm-platforms:kvm-arm64/haslr 17/22] arch/arm/kvm/../../../virt/kvm/arm/mmu.c:754:33: error: 'VA_BITS' undeclared; did you mean 'NMI_BITS'?
From: kbuild test robot @ 2018-01-07 19:03 UTC (permalink / raw)
To: linux-arm-kernel
tree: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git kvm-arm64/haslr
head: b6f07d796000cff9e69657e2369c1adbad6a72a2
commit: 326f33852915935d41ade2e8f55fbed2cdfaabe3 [17/22] KVM: arm/arm64: Move HYP IO VAs to the "idmap" range
config: arm-axm55xx_defconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
git checkout 326f33852915935d41ade2e8f55fbed2cdfaabe3
# save the attached .config to linux build tree
make.cross ARCH=arm
All errors (new ones prefixed by >>):
In file included from include/linux/kernel.h:11:0,
from include/asm-generic/bug.h:18,
from arch/arm/include/asm/bug.h:60,
from include/linux/bug.h:5,
from include/linux/mmdebug.h:5,
from include/linux/mm.h:9,
from include/linux/mman.h:5,
from arch/arm/kvm/../../../virt/kvm/arm/mmu.c:19:
arch/arm/kvm/../../../virt/kvm/arm/mmu.c: In function 'create_hyp_io_mappings':
>> arch/arm/kvm/../../../virt/kvm/arm/mmu.c:754:33: error: 'VA_BITS' undeclared (first use in this function); did you mean 'NMI_BITS'?
if ((base ^ io_map_base) & BIT(VA_BITS - 1)) {
^
include/linux/bitops.h:7:28: note: in definition of macro 'BIT'
#define BIT(nr) (1UL << (nr))
^~
arch/arm/kvm/../../../virt/kvm/arm/mmu.c:754:33: note: each undeclared identifier is reported only once for each function it appears in
if ((base ^ io_map_base) & BIT(VA_BITS - 1)) {
^
include/linux/bitops.h:7:28: note: in definition of macro 'BIT'
#define BIT(nr) (1UL << (nr))
^~
vim +754 arch/arm/kvm/../../../virt/kvm/arm/mmu.c
717
718 /**
719 * create_hyp_io_mappings - Map IO into both kernel and HYP
720 * @phys_addr: The physical start address which gets mapped
721 * @size: Size of the region being mapped
722 * @kaddr: Kernel VA for this mapping
723 * @haddr: HYP VA for this mapping
724 *
725 * The resulting HYP VA is completely unrelated to the kernel VA.
726 */
727 int create_hyp_io_mappings(phys_addr_t phys_addr, size_t size,
728 void __iomem **kaddr,
729 void __iomem **haddr)
730 {
731 pgd_t *pgd = hyp_pgd;
732 unsigned long base;
733 int ret;
734
735 *kaddr = ioremap(phys_addr, size);
736 if (!*kaddr)
737 return -ENOMEM;
738
739 if (is_kernel_in_hyp_mode()) {
740 *haddr = *kaddr;
741 return 0;
742 }
743
744 mutex_lock(&io_map_lock);
745
746 base = io_map_base - size;
747 base &= ~(size - 1);
748
749 /*
750 * Verify that BIT(VA_BITS - 1) hasn't been flipped by
751 * allocating the new area, as it would indicate we've
752 * overflowed the idmap/IO address range.
753 */
> 754 if ((base ^ io_map_base) & BIT(VA_BITS - 1)) {
755 ret = -ENOMEM;
756 goto out;
757 }
758
759 if (__kvm_cpu_uses_extended_idmap())
760 pgd = boot_hyp_pgd;
761
762 ret = __create_hyp_mappings(pgd, base, base + size,
763 __phys_to_pfn(phys_addr), PAGE_HYP_DEVICE);
764
765 if (!ret) {
766 *haddr = (void __iomem *)base;
767 io_map_base = base;
768 }
769
770 out:
771 mutex_unlock(&io_map_lock);
772
773 if (ret) {
774 iounmap(*kaddr);
775 *kaddr = NULL;
776 }
777
778 return ret;
779 }
780
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v6 10/10] clocksource: timer-dm: Check prescaler value
From: Ladislav Michl @ 2018-01-07 19:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <f743a25e-d29e-8693-f2c6-87d2f648d613@ti.com>
On Sun, Jan 07, 2018 at 09:26:44PM +0530, Keerthy wrote:
> On 1/5/2018 4:17 AM, Ladislav Michl wrote:
> > On Tue, Jan 02, 2018 at 03:39:59PM +0530, Keerthy wrote:
> > > From: Ladislav Michl <ladis@linux-mips.org>
> > >
> > > Invalid prescaler value is silently ignored. Fix that
> > > by returning -EINVAL in such case. As invalid value
> > > disabled use of the prescaler, use -1 explicitely for
> > > that purpose.
> > >
> > > Signed-off-by: Ladislav Michl <ladis@linux-mips.org>
> > > ---
> > > drivers/clocksource/timer-dm.c | 3 +++
> > > 1 file changed, 3 insertions(+)
> > >
> > > diff --git a/drivers/clocksource/timer-dm.c b/drivers/clocksource/timer-dm.c
> > > index 60db173..01a9cb0 100644
> > > --- a/drivers/clocksource/timer-dm.c
> > > +++ b/drivers/clocksource/timer-dm.c
> > > @@ -672,6 +672,9 @@ int omap_dm_timer_set_prescaler(struct omap_dm_timer *timer, int prescaler)
> > > if (prescaler >= 0x00 && prescaler <= 0x07) {
> > > l |= OMAP_TIMER_CTRL_PRE;
> > > l |= prescaler << 2;
> > > + } else {
> > > + if (prescaler != -1)
> > > + return -EINVAL;
> >
> > Argh... This is actually wrong, as it leaves timer enabled.
> > I suggest simply dropping this patch and I'll rethink whole
> > approach a bit later (and better).
>
> Okay. I hope the rest 9 patches work well for you.
Yes. I rebased event capture patches on top of this serie (based on
linux-next) and will post them during next week for review. Fixed
patch will be included (note, it is not really needed for your serie
as noone is calling this function).
> >
> > > }
> > > omap_dm_timer_write_reg(timer, OMAP_TIMER_CTRL_REG, l);
> >
> > Sorry for the noise,
> > ladis
> >
^ permalink raw reply
* [PATCH v2 3/5] ARM64: dts: meson-axg: uart: Add the pinctrl info description
From: Martin Blumenstingl @ 2018-01-07 20:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106001044.108163-4-yixun.lan@amlogic.com>
Hi Yixun,
On Sat, Jan 6, 2018 at 1:10 AM, Yixun Lan <yixun.lan@amlogic.com> wrote:
> Describe the pinctrl info for the UART controller which is found
> in the Meson-AXG SoCs.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 97 ++++++++++++++++++++++++++++++
> 1 file changed, 97 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> index 644d0f9eaf8c..1eb45781c850 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
> @@ -448,6 +448,70 @@
> function = "spi1";
> };
> };
> +
> + uart_a_pins: uart_a {
> + mux {
> + groups = "uart_tx_a",
> + "uart_rx_a";
> + function = "uart_a";
> + };
> + };
> +
> + uart_a_cts_rts_pins: uart_a_cts_rts {
> + mux {
> + groups = "uart_cts_a",
> + "uart_rts_a";
> + function = "uart_a";
> + };
> + };
> +
> + uart_b_x_pins: uart_b_x {
> + mux {
> + groups = "uart_tx_b_x",
> + "uart_rx_b_x";
> + function = "uart_b";
> + };
> + };
> +
> + uart_b_x_cts_rts_pins: uart_b_x_cts_rts {
> + mux {
> + groups = "uart_cts_b_x",
> + "uart_rts_b_x";
> + function = "uart_b";
> + };
> + };
> +
> + uart_b_z_pins: uart_b_z {
> + mux {
> + groups = "uart_tx_b_z",
> + "uart_rx_b_z";
> + function = "uart_b";
> + };
> + };
> +
> + uart_b_z_cts_rts_pins: uart_b_z_cts_rts {
> + mux {
> + groups = "uart_cts_b_z",
> + "uart_rts_b_z";
> + function = "uart_b";
> + };
> + };
> +
> + uart_ao_b_z_pins: uart_ao_b_z {
> + mux {
> + groups = "uart_ao_tx_b_z",
> + "uart_ao_rx_b_z";
> + function = "uart_ao_b_gpioz";
(the following question just came up while I was looking at this
patch, but I guess it's more a question towards the pinctrl driver)
the name of the function looks a bit "weird" since below you are also
using "uart_ao_b"
did you choose "uart_ao_b_gpioz" here because we cannot have the same
function name for the periphs and AO pinctrl or is there some other
reason?
I am asking because I would have expected it to look like this:
groups = "uart_ao_tx_b_z", "uart_ao_rx_b_z";
function = "uart_ao_b";
(same for the cts/rts pins below)
> + };
> + };
> +
> + uart_ao_b_z_cts_rts_pins: uart_ao_b_z_cts_rts {
> + mux {
> + groups = "uart_ao_cts_b_z",
> + "uart_ao_rts_b_z";
> + function = "uart_ao_b_gpioz";
> + };
> + };
> };
> };
>
> @@ -492,12 +556,45 @@
> gpio-ranges = <&pinctrl_aobus 0 0 15>;
> };
>
> +
did you add this additional newline on purpose?
> remote_input_ao_pins: remote_input_ao {
> mux {
> groups = "remote_input_ao";
> function = "remote_input_ao";
> };
> };
> +
> + uart_ao_a_pins: uart_ao_a {
> + mux {
> + groups = "uart_ao_tx_a",
> + "uart_ao_rx_a";
> + function = "uart_ao_a";
> + };
> + };
> +
> + uart_ao_a_cts_rts_pins: uart_ao_a_cts_rts {
> + mux {
> + groups = "uart_ao_cts_a",
> + "uart_ao_rts_a";
> + function = "uart_ao_a";
> + };
> + };
> +
> + uart_ao_b_pins: uart_ao_b {
> + mux {
> + groups = "uart_ao_tx_b",
> + "uart_ao_rx_b";
> + function = "uart_ao_b";
> + };
> + };
> +
> + uart_ao_b_cts_rts_pins: uart_ao_b_cts_rts {
> + mux {
> + groups = "uart_ao_cts_b",
> + "uart_ao_rts_b";
> + function = "uart_ao_b";
> + };
> + };
> };
>
> pwm_AO_ab: pwm at 7000 {
> --
> 2.15.1
>
>
> _______________________________________________
> linux-amlogic mailing list
> linux-amlogic at lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-amlogic
Regards
Martin
^ permalink raw reply
* [PATCH 00/12] Marvell NAND controller rework with ->exec_op()
From: Robert Jarzmik @ 2018-01-07 20:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180103215206.5d85b41b@bbrezillon>
Boris Brezillon <boris.brezillon@free-electrons.com> writes:
> On Wed, 3 Jan 2018 21:10:28 +0100
> Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
>> Hm, that's weird. Can you try with the old driver (pxa3xx)?
Ah you're right, my NAND was damaged ...
> Alternatively, you can type 'nand bad' from uboot to check if it
> detects the same bad blocks.
Mmmh no, the SPL is barebox in my case. Do you have a command in linux or
barebox to do the same thing ?
Cheers.
--
Robert
^ permalink raw reply
* [PATCH 00/12] Marvell NAND controller rework with ->exec_op()
From: Miquel RAYNAL @ 2018-01-07 21:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <874lnxcrsq.fsf@belgarion.home>
Hi Robert,
On Sun, 07 Jan 2018 21:55:33 +0100
Robert Jarzmik <robert.jarzmik@free.fr> wrote:
> Boris Brezillon <boris.brezillon@free-electrons.com> writes:
>
> > On Wed, 3 Jan 2018 21:10:28 +0100
> > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> >> Hm, that's weird. Can you try with the old driver (pxa3xx)?
> Ah you're right, my NAND was damaged ...
>
> > Alternatively, you can type 'nand bad' from uboot to check if it
> > detects the same bad blocks.
> Mmmh no, the SPL is barebox in my case. Do you have a command in
> linux or barebox to do the same thing ?
Not sure, but nand -i should do the trick.
https://www.barebox.org/doc/latest/commands/hwmanip/nand.html
But I am not sure this is still relevant now we know the NAND was
damaged by the previous experiments (sorry about that). Can you put the
NAND in a clean state and report us if it is still failing?
Thanks for your help,
Miqu?l
^ permalink raw reply
* [PATCH 00/12] Marvell NAND controller rework with ->exec_op()
From: Boris Brezillon @ 2018-01-07 21:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180107220911.31844b3a@xps13>
On Sun, 7 Jan 2018 22:09:11 +0100
Miquel RAYNAL <miquel.raynal@free-electrons.com> wrote:
> Hi Robert,
>
> On Sun, 07 Jan 2018 21:55:33 +0100
> Robert Jarzmik <robert.jarzmik@free.fr> wrote:
>
> > Boris Brezillon <boris.brezillon@free-electrons.com> writes:
> >
> > > On Wed, 3 Jan 2018 21:10:28 +0100
> > > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> > >> Hm, that's weird. Can you try with the old driver (pxa3xx)?
> > Ah you're right, my NAND was damaged ...
> >
> > > Alternatively, you can type 'nand bad' from uboot to check if it
> > > detects the same bad blocks.
> > Mmmh no, the SPL is barebox in my case. Do you have a command in
> > linux or barebox to do the same thing ?
>
> Not sure, but nand -i should do the trick.
> https://www.barebox.org/doc/latest/commands/hwmanip/nand.html
>
> But I am not sure this is still relevant now we know the NAND was
> damaged by the previous experiments (sorry about that). Can you put the
> NAND in a clean state and report us if it is still failing?
In order to do that you'll have to scrub the blocks storing the BBT, and
I'm not sure barebox supports that. Linux does not, for sure, so if you
want to forcibly erase bad blocks from linux, you'll have to comment
these lines [1].
[1]http://elixir.free-electrons.com/linux/v4.15-rc6/source/drivers/mtd/nand/nand_base.c#L3056
^ permalink raw reply
* [PATCH 00/12] Marvell NAND controller rework with ->exec_op()
From: Boris Brezillon @ 2018-01-07 21:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180107221911.51115566@bbrezillon>
On Sun, 7 Jan 2018 22:19:11 +0100
Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> On Sun, 7 Jan 2018 22:09:11 +0100
> Miquel RAYNAL <miquel.raynal@free-electrons.com> wrote:
>
> > Hi Robert,
> >
> > On Sun, 07 Jan 2018 21:55:33 +0100
> > Robert Jarzmik <robert.jarzmik@free.fr> wrote:
> >
> > > Boris Brezillon <boris.brezillon@free-electrons.com> writes:
> > >
> > > > On Wed, 3 Jan 2018 21:10:28 +0100
> > > > Boris Brezillon <boris.brezillon@free-electrons.com> wrote:
> > > >> Hm, that's weird. Can you try with the old driver (pxa3xx)?
> > > Ah you're right, my NAND was damaged ...
> > >
> > > > Alternatively, you can type 'nand bad' from uboot to check if it
> > > > detects the same bad blocks.
> > > Mmmh no, the SPL is barebox in my case. Do you have a command in
> > > linux or barebox to do the same thing ?
> >
> > Not sure, but nand -i should do the trick.
> > https://www.barebox.org/doc/latest/commands/hwmanip/nand.html
> >
> > But I am not sure this is still relevant now we know the NAND was
> > damaged by the previous experiments (sorry about that). Can you put the
> > NAND in a clean state and report us if it is still failing?
>
> In order to do that you'll have to scrub the blocks storing the BBT, and
> I'm not sure barebox supports that. Linux does not, for sure, so if you
> want to forcibly erase bad blocks from linux, you'll have to comment
> these lines [1].
Apparently there's a "nand -g <offs>" command to mark a block good in
barebox. After doing that you should be able to erase the blocks storing
the BBT (it should be placed in the last 2 blocks of the NAND).
>
> [1]http://elixir.free-electrons.com/linux/v4.15-rc6/source/drivers/mtd/nand/nand_base.c#L3056
^ permalink raw reply
* [PATCH v2 1/5] dt-bindings: mtd: add Marvell NAND controller documentation
From: Miquel RAYNAL @ 2018-01-07 21:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171220210511.ty2e7mkiktvn4een@rob-hp-laptop>
Hi Rob,
On Wed, 20 Dec 2017 15:05:11 -0600
Rob Herring <robh@kernel.org> wrote:
> On Tue, Dec 19, 2017 at 02:29:38PM +0100, Miquel Raynal wrote:
> > Document the legacy and the new bindings for Marvell NAND
> > controller.
> >
> > The pxa3xx_nand.c driver does only support legacy bindings, which
> > are incomplete and inaccurate. A rework of this controller (called
> > marvell_nand.c) does support both.
> >
> > Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
> > ---
> > .../devicetree/bindings/mtd/marvell-nand.txt | 123
> > +++++++++++++++++++++ 1 file changed, 123 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/mtd/marvell-nand.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mtd/marvell-nand.txt
> > b/Documentation/devicetree/bindings/mtd/marvell-nand.txt new file
> > mode 100644 index 000000000000..aa6a1ed045b2
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mtd/marvell-nand.txt
> > @@ -0,0 +1,123 @@
> > +Marvell NAND Flash Controller (NFC)
> > +
> > +Required properties:
> > +- compatible: can be one of the following:
> > + * "marvell,armada-8k-nand-controller"
> > + * "marvell,armada370-nand-controller"
> > + * "marvell,pxa3xx-nand-controller"
> > + * "marvell,armada-8k-nand" (deprecated)
> > + * "marvell,armada370-nand" (deprecated)
> > + * "marvell,pxa3xx-nand" (deprecated)
> > + Compatibles marked deprecated support only the old bindings
> > described
> > + at the bottom.
> > +- reg: NAND flash controller memory area.
> > +- #address-cells: shall be set to 1. Encode the NAND CS.
> > +- #size-cells: shall be set to 0.
> > +- interrupts: shall define the NAND controller interrupt.
> > +- clocks: shall reference the NAND controller clock.
> > +- marvell,system-controller: Set to retrieve the syscon node that
> > handles
> > + NAND controller related registers (only required with the
> > + "marvell,armada-8k-nand[-controller]" compatibles).
> > +
> > +Optional properties:
> > +- label: see partition.txt. New platforms shall omit this property.
> > +- dmas: shall reference DMA channel associated to the NAND
> > controller.
> > + This property is only used with
> > "marvell,pxa3xx-nand[-controller]"
> > + compatible strings.
> > +- dma-names: shall be "rxtx".
> > + This property is only used with
> > "marvell,pxa3xx-nand[-controller]"
> > + compatible strings.
> > +
> > +Optional children nodes:
> > +Children nodes represent the available NAND chips.
> > +
> > +Required properties:
> > +- reg: shall contain the native Chip Select ids (0-3)
> > +- marvell,rb: shall contain the native Ready/Busy ids (0-1)
>
> We already have at least 2 other <vendor>,rb properties. Let's not
> add a 3rd and make a common one instead.
I switched to "nand-rb", added this property in nand.txt (in another
commit) and updated all the DT accordingly.
>
> > +
> > +Optional properties:
> > +- marvell,nand-keep-config: orders the driver not to take the
> > timings
> > + from the core and leaving them completely untouched. Bootloader
> > + timings will then be used.
> > +- label: MTD name.
> > +- nand-on-flash-bbt: see nand.txt.
> > +- nand-ecc-mode: see nand.txt. Will use hardware ECC if not
> > specified. +- nand-ecc-algo: see nand.txt. This property may be
> > added when using
> > + hardware ECC for clarification but will be ignored by the driver
> > + because ECC mode is chosen depending on the page size and the
> > strength
> > + required by the NAND chip. This value may be overwritten with
> > + nand-ecc-strength property.
>
> If not used, then drop it.
Well, nand-ecc-algo will be useful when not using the ECC
engine, so it cannot be removed. I tried to explain better the
situation.
>
> > +- nand-ecc-strength: see nand.txt.
> > +- nand-ecc-step-size: see nand.txt. This has no effect and will be
> > + ignored by the driver when using hardware ECC because Marvell's
> > NAND
> > + flash controller does use fixed strength (1-bit for Hamming,
> > 16-bit
> > + for BCH), so the step size will shrink or grow in order to fit
> > the
> > + required strength. Step sizes are not completely random for all
> > and
> > + follow certain patterns described in AN-379, "Marvell SoC NFC
> > ECC".
>
> Same here.
The comment about being ignored was not accurate, I simply removed
that part.
Thanks,
Miqu?l
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