* [PATCH v5 17/44] dt-bindings: clock: Add bindings for DA8XX CFGCHIP gate clocks
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds a new binding for the gate clocks present in the CFGCHIP syscon
registers in TI DA8XX SoCs. There are actually other gate clocks in this
block that could be added in the future, but TBCLK is currently the only
one being used.
Signed-off-by: David Lechner <david@lechnology.com>
---
.../clock/ti/davinci/da8xx-cfgchip-gate.txt | 38 ++++++++++++++++++++++
1 file changed, 38 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt
new file mode 100644
index 0000000..55821b0
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt
@@ -0,0 +1,38 @@
+Binding for TI DA8XX/OMAP-L13X/AM17XX/AM18XX CFGCHIP gate clocks
+
+TI DA8XX/OMAP-L13X/AM17XX/AM18XX SoCs contain a general purpose set of
+registers call CFGCHIPn. Some of these registers function as clock
+gates. This document describes the bindings for those clocks.
+
+Required properties:
+- compatible: shall be "ti,da830-tbclk".
+- #clock-cells: from common clock binding; shall be set to 0.
+- clocks: phandle to the parent clock
+
+Optional properties:
+- clock-output-names: from common clock binding.
+
+Parent:
+This node must be a child of a "ti,da830-cfgchip" node.
+
+Assignment:
+The assigned-clocks and assigned-clock-parents from the common clock bindings
+can be used to indicate which parent clock should be used.
+
+Examples:
+
+ cfgchip: syscon at 1417c {
+ compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
+ reg = <0x1417c 0x14>;
+
+ ehrpwm_tbclk: tbclk {
+ compatible = "ti,da830-tbclk";
+ #clock-cells = <0>;
+ clocks = <&psc1 17>;
+ clock-output-names = "ehrpwm_tbclk";
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+
--
2.7.4
^ permalink raw reply related
* [PATCH v5 16/44] clk: davinci: Add platform information for TI DM646x PSC
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PSC clocks on TI
DaVinci 646x based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/psc-dm646x.c | 68 ++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 70 insertions(+)
create mode 100644 drivers/clk/davinci/psc-dm646x.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index a20e379..6c388d4 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -15,4 +15,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += psc-dm365.o
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += psc-dm644x.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x) += psc-dm646x.o
endif
diff --git a/drivers/clk/davinci/psc-dm646x.c b/drivers/clk/davinci/psc-dm646x.c
new file mode 100644
index 0000000..cbc3976
--- /dev/null
+++ b/drivers/clk/davinci/psc-dm646x.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PSC clock descriptions for TI DaVinci DM646x
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "psc.h"
+
+static const struct davinci_psc_clk_info dm646x_psc_info[] __initconst = {
+ LPSC(0, 0, arm, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ /* REVISIT how to disable? */
+ LPSC(1, 0, dsp, pll1_sysclk1, LPSC_ALWAYS_ENABLED),
+ LPSC(4, 0, edma_cc, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(5, 0, edma_tc0, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(6, 0, edma_tc1, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(7, 0, edma_tc2, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(8, 0, edma_tc3, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(10, 0, ide, pll1_sysclk4, 0),
+ LPSC(14, 0, emac, pll1_sysclk3, 0),
+ LPSC(16, 0, vpif0, ref_clk, LPSC_ALWAYS_ENABLED),
+ LPSC(17, 0, vpif1, ref_clk, LPSC_ALWAYS_ENABLED),
+ LPSC(21, 0, aemif, pll1_sysclk3, LPSC_ALWAYS_ENABLED),
+ LPSC(22, 0, mcasp0, pll1_sysclk3, 0),
+ LPSC(23, 0, mcasp1, pll1_sysclk3, 0),
+ LPSC(26, 0, uart0, aux_clkin, 0),
+ LPSC(27, 0, uart1, aux_clkin, 0),
+ LPSC(28, 0, uart2, aux_clkin, 0),
+ /* REVIST: disabling hangs system */
+ LPSC(29, 0, pwm0, pll1_sysclk3, LPSC_ALWAYS_ENABLED),
+ /* REVIST: disabling hangs system */
+ LPSC(30, 0, pwm1, pll1_sysclk3, LPSC_ALWAYS_ENABLED),
+ LPSC(31, 0, i2c, pll1_sysclk3, 0),
+ LPSC(33, 0, gpio, pll1_sysclk3, 0),
+ LPSC(34, 0, timer0, pll1_sysclk3, 0),
+ LPSC(35, 0, timer1, pll1_sysclk3, 0),
+ { }
+};
+
+void __init dm646x_psc_clk_init(void __iomem *psc)
+{
+ struct clk_onecell_data *clk_data;
+
+ clk_data = davinci_psc_register_clocks(psc, dm646x_psc_info, 41);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[0], "arm", NULL);
+ clk_register_clkdev(clk_data->clks[10], NULL, "palm_bk3710");
+ clk_register_clkdev(clk_data->clks[14], NULL, "davinci_emac.1");
+ clk_register_clkdev(clk_data->clks[14], "fck", "davinci_mdio.0");
+ clk_register_clkdev(clk_data->clks[21], "aemif", NULL);
+ clk_register_clkdev(clk_data->clks[22], NULL, "davinci-mcasp.0");
+ clk_register_clkdev(clk_data->clks[23], NULL, "davinci-mcasp.1");
+ clk_register_clkdev(clk_data->clks[26], NULL, "serial8250.0");
+ clk_register_clkdev(clk_data->clks[27], NULL, "serial8250.1");
+ clk_register_clkdev(clk_data->clks[28], NULL, "serial8250.2");
+ clk_register_clkdev(clk_data->clks[31], NULL, "i2c_davinci.1");
+ clk_register_clkdev(clk_data->clks[33], "gpio", NULL);
+ clk_register_clkdev(clk_data->clks[34], "timer0", NULL);
+
+ clk_free_onecell_data(clk_data);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 6d2896d..3810ea3 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -21,5 +21,6 @@ void da850_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
void dm355_psc_clk_init(void __iomem *psc);
void dm365_psc_clk_init(void __iomem *psc);
void dm644x_psc_clk_init(void __iomem *psc);
+void dm646x_psc_clk_init(void __iomem *psc);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 15/44] clk: davinci: Add platform information for TI DM644x PSC
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PSC clocks on TI
DaVinci 644x based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/psc-dm644x.c | 73 ++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 75 insertions(+)
create mode 100644 drivers/clk/davinci/psc-dm644x.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index 78dc1eb..a20e379 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -14,4 +14,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += psc-dm365.o
+obj-$(CONFIG_ARCH_DAVINCI_DM644x) += psc-dm644x.o
endif
diff --git a/drivers/clk/davinci/psc-dm644x.c b/drivers/clk/davinci/psc-dm644x.c
new file mode 100644
index 0000000..ef5ef14
--- /dev/null
+++ b/drivers/clk/davinci/psc-dm644x.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PSC clock descriptions for TI DaVinci DM644x
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "psc.h"
+
+static const struct davinci_psc_clk_info dm644x_psc_info[] __initconst = {
+ LPSC(0, 0, vpss_master, pll1_sysclk3, 0),
+ LPSC(1, 0, vpss_slave, pll1_sysclk3, 0),
+ LPSC(6, 0, emac, pll1_sysclk5, 0),
+ LPSC(9, 0, usb, pll1_sysclk5, 0),
+ LPSC(10, 0, ide, pll1_sysclk5, 0),
+ LPSC(11, 0, vlynq, pll1_sysclk5, 0),
+ LPSC(14, 0, aemif, pll1_sysclk5, 0),
+ LPSC(15, 0, mmcsd, pll1_sysclk5, 0),
+ LPSC(17, 0, asp0, pll1_sysclk5, 0),
+ LPSC(18, 0, i2c, pll1_aux_clk, 0),
+ LPSC(19, 0, uart0, pll1_aux_clk, 0),
+ LPSC(20, 0, uart1, pll1_aux_clk, 0),
+ LPSC(21, 0, uart2, pll1_aux_clk, 0),
+ LPSC(22, 0, spi, pll1_sysclk5, 0),
+ LPSC(23, 0, pwm0, pll1_aux_clk, 0),
+ LPSC(24, 0, pwm1, pll1_aux_clk, 0),
+ LPSC(25, 0, pwm2, pll1_aux_clk, 0),
+ LPSC(26, 0, gpio, pll1_sysclk5, 0),
+ LPSC(27, 0, timer0, pll1_aux_clk, 0),
+ LPSC(28, 0, timer1, pll1_aux_clk, 0),
+ /* REVISIT: why can't this be disabled? */
+ LPSC(29, 0, timer2, pll1_aux_clk, LPSC_ALWAYS_ENABLED),
+ LPSC(31, 0, arm, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ /* REVISIT how to disable? */
+ LPSC(39, 1, dsp, pll1_sysclk1, LPSC_ALWAYS_ENABLED),
+ /* REVISIT how to disable? */
+ LPSC(40, 1, vicp, pll1_sysclk2, LPSC_ALWAYS_ENABLED),
+ { }
+};
+
+void __init dm644x_psc_clk_init(void __iomem *psc)
+{
+ struct clk_onecell_data *clk_data;
+
+ clk_data = davinci_psc_register_clocks(psc, dm644x_psc_info, 41);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[0], "master", "vpss");
+ clk_register_clkdev(clk_data->clks[1], "slave", "vpss");
+ clk_register_clkdev(clk_data->clks[6], NULL, "davinci_emac.1");
+ clk_register_clkdev(clk_data->clks[6], "fck", "davinci_mdio.0");
+ clk_register_clkdev(clk_data->clks[9], "usb", NULL);
+ clk_register_clkdev(clk_data->clks[10], NULL, "palm_bk3710");
+ clk_register_clkdev(clk_data->clks[14], "aemif", NULL);
+ clk_register_clkdev(clk_data->clks[15], NULL, "dm6441-mmc.0");
+ clk_register_clkdev(clk_data->clks[17], NULL, "davinci-mcbsp");
+ clk_register_clkdev(clk_data->clks[18], NULL, "i2c_davinci.1");
+ clk_register_clkdev(clk_data->clks[19], NULL, "serial8250.0");
+ clk_register_clkdev(clk_data->clks[20], NULL, "serial8250.1");
+ clk_register_clkdev(clk_data->clks[21], NULL, "serial8250.2");
+ clk_register_clkdev(clk_data->clks[26], "gpio", NULL);
+ clk_register_clkdev(clk_data->clks[27], "timer0", NULL);
+ clk_register_clkdev(clk_data->clks[29], NULL, "davinci-wdt");
+ clk_register_clkdev(clk_data->clks[31], "arm", NULL);
+
+ clk_free_onecell_data(clk_data);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index c7d8c5f..6d2896d 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -20,5 +20,6 @@ void da830_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
void da850_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
void dm355_psc_clk_init(void __iomem *psc);
void dm365_psc_clk_init(void __iomem *psc);
+void dm644x_psc_clk_init(void __iomem *psc);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 14/44] clk: davinci: Add platform information for TI DM365 PSC
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PSC clocks on TI
DaVinci 365 based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/psc-dm365.c | 83 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 85 insertions(+)
create mode 100644 drivers/clk/davinci/psc-dm365.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index e0da5c3..78dc1eb 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -13,4 +13,5 @@ obj-y += psc.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o
+obj-$(CONFIG_ARCH_DAVINCI_DM365) += psc-dm365.o
endif
diff --git a/drivers/clk/davinci/psc-dm365.c b/drivers/clk/davinci/psc-dm365.c
new file mode 100644
index 0000000..0232832
--- /dev/null
+++ b/drivers/clk/davinci/psc-dm365.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PSC clock descriptions for TI DaVinci DM365
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "psc.h"
+
+static const struct davinci_psc_clk_info dm365_psc_info[] __initconst = {
+ LPSC(1, 0, vpss_slave, pll1_sysclk5, 0),
+ LPSC(5, 0, timer3, pll1_aux_clk, 0),
+ LPSC(6, 0, spi1, pll1_sysclk4, 0),
+ LPSC(7, 0, mmcsd1, pll1_sysclk4, 0),
+ LPSC(8, 0, asp0, pll1_sysclk4, 0),
+ LPSC(9, 0, usb, pll1_aux_clk, 0),
+ LPSC(10, 0, pwm3, ref_clk, 0),
+ LPSC(11, 0, spi2, pll1_sysclk4, 0),
+ LPSC(12, 0, rto, pll1_sysclk4, 0),
+ LPSC(14, 0, aemif, pll1_sysclk4, 0),
+ LPSC(15, 0, mmcsd0, pll1_sysclk8, 0),
+ LPSC(18, 0, i2c, pll1_aux_clk, 0),
+ LPSC(19, 0, uart0, pll1_aux_clk, 0),
+ LPSC(20, 0, uart1, pll1_sysclk4, 0),
+ LPSC(22, 0, spi0, pll1_sysclk4, 0),
+ LPSC(23, 0, pwm0, pll1_aux_clk, 0),
+ LPSC(24, 0, pwm1, pll1_aux_clk, 0),
+ LPSC(25, 0, pwm2, pll1_aux_clk, 0),
+ LPSC(26, 0, gpio, pll1_sysclk4, 0),
+ LPSC(27, 0, timer0, pll1_aux_clk, 0),
+ LPSC(28, 0, timer1, pll1_aux_clk, 0),
+ /* REVISIT: why can't this be disabled? */
+ LPSC(29, 0, timer2, pll1_aux_clk, LPSC_ALWAYS_ENABLED),
+ LPSC(31, 0, arm, pll2_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(38, 0, spi3, pll1_sysclk4, 0),
+ LPSC(39, 0, spi4, pll1_aux_clk, 0),
+ LPSC(40, 0, emac, pll2_sysclk4, 0),
+ LPSC(44, 1, voice_codec, pll1_sysclk3, 0),
+ LPSC(46, 1, vpss_dac, pll1_sysclk3, 0),
+ LPSC(47, 0, vpss_master, pll1_sysclk5, 0),
+ LPSC(50, 0, mjcp, pll1_sysclk3, 0),
+ { }
+};
+
+void __init dm365_psc_clk_init(void __iomem *psc)
+{
+ struct clk_onecell_data *clk_data;
+
+ clk_data = davinci_psc_register_clocks(psc, dm365_psc_info, 52);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[1], "slave", "vpss");
+ clk_register_clkdev(clk_data->clks[6], NULL, "spi_davinci.1");
+ clk_register_clkdev(clk_data->clks[7], NULL, "da830-mmc.1");
+ clk_register_clkdev(clk_data->clks[8], NULL, "davinci-mcbsp");
+ clk_register_clkdev(clk_data->clks[9], "usb", NULL);
+ clk_register_clkdev(clk_data->clks[11], NULL, "spi_davinci.2");
+ clk_register_clkdev(clk_data->clks[14], "aemif", NULL);
+ clk_register_clkdev(clk_data->clks[15], NULL, "da830-mmc.0");
+ clk_register_clkdev(clk_data->clks[18], NULL, "i2c_davinci.1");
+ clk_register_clkdev(clk_data->clks[19], NULL, "serial8250.0");
+ clk_register_clkdev(clk_data->clks[20], NULL, "serial8250.1");
+ clk_register_clkdev(clk_data->clks[22], NULL, "spi_davinci.0");
+ clk_register_clkdev(clk_data->clks[26], "gpio", NULL);
+ clk_register_clkdev(clk_data->clks[27], "timer0", NULL);
+ clk_register_clkdev(clk_data->clks[29], NULL, "davinci-wdt");
+ clk_register_clkdev(clk_data->clks[31], "arm", NULL);
+ clk_register_clkdev(clk_data->clks[38], NULL, "spi_davinci.3");
+ clk_register_clkdev(clk_data->clks[39], NULL, "spi_davinci.4");
+ clk_register_clkdev(clk_data->clks[40], NULL, "davinci_emac.1");
+ clk_register_clkdev(clk_data->clks[40], "fck", "davinci_mdio.0");
+ clk_register_clkdev(clk_data->clks[44], NULL, "davinci_voicecodec");
+ clk_register_clkdev(clk_data->clks[46], "vpss_dac", NULL);
+ clk_register_clkdev(clk_data->clks[47], "master", "vpss");
+
+ clk_free_onecell_data(clk_data);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index dc09177..c7d8c5f 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -19,5 +19,6 @@ void dm646x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void da830_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
void da850_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
void dm355_psc_clk_init(void __iomem *psc);
+void dm365_psc_clk_init(void __iomem *psc);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 13/44] clk: davinci: Add platform information for TI DM355 PSC
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PSC clocks on TI
DaVinci 355 based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/psc-dm355.c | 78 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 80 insertions(+)
create mode 100644 drivers/clk/davinci/psc-dm355.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index aef0390..e0da5c3 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -12,4 +12,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o
obj-y += psc.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355) += psc-dm355.o
endif
diff --git a/drivers/clk/davinci/psc-dm355.c b/drivers/clk/davinci/psc-dm355.c
new file mode 100644
index 0000000..09075ed
--- /dev/null
+++ b/drivers/clk/davinci/psc-dm355.c
@@ -0,0 +1,78 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PSC clock descriptions for TI DaVinci DM355
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "psc.h"
+
+static const struct davinci_psc_clk_info dm355_psc_info[] __initconst = {
+ LPSC(0, 0, vpss_master, pll1_sysclk4, 0),
+ LPSC(1, 0, vpss_slave, pll1_sysclk4, 0),
+ LPSC(5, 0, timer3, pll1_aux_clk, 0),
+ LPSC(6, 0, spi1, pll1_sysclk2, 0),
+ LPSC(7, 0, mmcsd1, pll1_sysclk2, 0),
+ LPSC(8, 0, asp1, pll1_sysclk2, 0),
+ LPSC(9, 0, usb, pll1_sysclk2, 0),
+ LPSC(10, 0, pwm3, pll1_aux_clk, 0),
+ LPSC(11, 0, spi2, pll1_sysclk2, 0),
+ LPSC(12, 0, rto, pll1_aux_clk, 0),
+ LPSC(14, 0, aemif, pll1_sysclk2, 0),
+ LPSC(15, 0, mmcsd0, pll1_sysclk2, 0),
+ LPSC(17, 0, asp0, pll1_sysclk2, 0),
+ LPSC(18, 0, i2c, pll1_aux_clk, 0),
+ LPSC(19, 0, uart0, pll1_aux_clk, 0),
+ LPSC(20, 0, uart1, pll1_aux_clk, 0),
+ LPSC(21, 0, uart2, pll1_sysclk2, 0),
+ LPSC(22, 0, spi0, pll1_sysclk2, 0),
+ LPSC(23, 0, pwm0, pll1_aux_clk, 0),
+ LPSC(24, 0, pwm1, pll1_aux_clk, 0),
+ LPSC(25, 0, pwm2, pll1_aux_clk, 0),
+ LPSC(26, 0, gpio, pll1_sysclk2, 0),
+ LPSC(27, 0, timer0, pll1_aux_clk, 0),
+ LPSC(28, 0, timer1, pll1_aux_clk, 0),
+ /* REVISIT: why can't this be disabled? */
+ LPSC(29, 0, timer2, pll1_aux_clk, LPSC_ALWAYS_ENABLED),
+ LPSC(31, 0, arm, pll1_sysclk1, LPSC_ALWAYS_ENABLED),
+ LPSC(40, 0, mjcp, pll1_sysclk1, 0),
+ LPSC(41, 0, vpss_dac, pll1_sysclk3, 0),
+ { }
+};
+
+void __init dm355_psc_clk_init(void __iomem *psc)
+{
+ struct clk_onecell_data *clk_data;
+
+ clk_data = davinci_psc_register_clocks(psc, dm355_psc_info, 42);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[0], "master", "vpss");
+ clk_register_clkdev(clk_data->clks[1], "slave", "vpss");
+ clk_register_clkdev(clk_data->clks[6], NULL, "spi_davinci.1");
+ clk_register_clkdev(clk_data->clks[7], NULL, "dm6441-mmc.1");
+ clk_register_clkdev(clk_data->clks[8], NULL, "davinci-mcbsp.1");
+ clk_register_clkdev(clk_data->clks[9], "usb", NULL);
+ clk_register_clkdev(clk_data->clks[11], NULL, "spi_davinci.2");
+ clk_register_clkdev(clk_data->clks[14], "aemif", NULL);
+ clk_register_clkdev(clk_data->clks[15], NULL, "dm6441-mmc.0");
+ clk_register_clkdev(clk_data->clks[17], NULL, "davinci-mcbsp.0");
+ clk_register_clkdev(clk_data->clks[18], NULL, "i2c_davinci.1");
+ clk_register_clkdev(clk_data->clks[19], NULL, "serial8250.0");
+ clk_register_clkdev(clk_data->clks[20], NULL, "serial8250.1");
+ clk_register_clkdev(clk_data->clks[21], NULL, "serial8250.2");
+ clk_register_clkdev(clk_data->clks[22], NULL, "spi_davinci.0");
+ clk_register_clkdev(clk_data->clks[26], "gpio", NULL);
+ clk_register_clkdev(clk_data->clks[27], "timer0", NULL);
+ clk_register_clkdev(clk_data->clks[29], NULL, "davinci-wdt");
+ clk_register_clkdev(clk_data->clks[31], "arm", NULL);
+ clk_register_clkdev(clk_data->clks[41], "vpss_dac", NULL);
+
+ clk_free_onecell_data(clk_data);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 3d8bdfa..dc09177 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -18,5 +18,6 @@ void dm646x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void da830_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
void da850_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
+void dm355_psc_clk_init(void __iomem *psc);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 12/44] clk: davinci: Add platform information for TI DA850 PSC
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PSC clocks on TI DA850/
OMAP-L138/AM18XX SoCs.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/psc-da850.c | 117 ++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 119 insertions(+)
create mode 100644 drivers/clk/davinci/psc-da850.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index fb14c8c..aef0390 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -11,4 +11,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o
obj-y += psc.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
+obj-$(CONFIG_ARCH_DAVINCI_DA850) += psc-da850.o
endif
diff --git a/drivers/clk/davinci/psc-da850.c b/drivers/clk/davinci/psc-da850.c
new file mode 100644
index 0000000..3b4583d
--- /dev/null
+++ b/drivers/clk/davinci/psc-da850.c
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PSC clock descriptions for TI DA850/OMAP-L138/AM18XX
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/types.h>
+
+#include "psc.h"
+
+static const struct davinci_psc_clk_info da850_psc0_info[] __initconst = {
+ LPSC(0, 0, tpcc0, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(1, 0, tptc0, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(2, 0, tptc1, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(3, 0, aemif, pll0_sysclk3, 0),
+ LPSC(4, 0, spi0, pll0_sysclk2, 0),
+ LPSC(5, 0, mmcsd0, pll0_sysclk2, 0),
+ LPSC(6, 0, aintc, pll0_sysclk4, LPSC_ALWAYS_ENABLED),
+ LPSC(7, 0, arm_rom, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(9, 0, uart0, pll0_sysclk2, 0),
+ LPSC(13, 0, pruss, pll0_sysclk2, 0),
+ LPSC(14, 0, arm, pll0_sysclk6, LPSC_ALWAYS_ENABLED),
+ LPSC(15, 1, dsp, pll0_sysclk1, LPSC_FORCE | LPSC_LOCAL_RESET),
+ { }
+};
+
+static const struct davinci_psc_clk_info da850_psc1_info[] __initconst = {
+ LPSC(0, 0, tpcc1, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(1, 0, usb0, pll0_sysclk2, 0),
+ LPSC(2, 0, usb1, pll0_sysclk4, 0),
+ LPSC(3, 0, gpio, pll0_sysclk4, 0),
+ LPSC(5, 0, emac, pll0_sysclk4, 0),
+ LPSC(6, 0, emif3, pll0_sysclk5, LPSC_ALWAYS_ENABLED),
+ LPSC(7, 0, mcasp0, async3, 0),
+ LPSC(8, 0, sata, pll0_sysclk2, LPSC_FORCE),
+ LPSC(9, 0, vpif, pll0_sysclk2, 0),
+ LPSC(10, 0, spi1, async3, 0),
+ LPSC(11, 0, i2c1, pll0_sysclk4, 0),
+ LPSC(12, 0, uart1, async3, 0),
+ LPSC(13, 0, uart2, async3, 0),
+ LPSC(14, 0, mcbsp0, async3, 0),
+ LPSC(15, 0, mcbsp1, async3, 0),
+ LPSC(16, 0, lcdc, pll0_sysclk2, 0),
+ LPSC(17, 0, ehrpwm, async3, 0),
+ LPSC(18, 0, mmcsd1, pll0_sysclk2, 0),
+ LPSC(20, 0, ecap, async3, 0),
+ LPSC(21, 0, tptc2, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ { }
+};
+
+void __init da850_psc_clk_init(void __iomem *psc0, void __iomem *psc1)
+{
+ struct clk_onecell_data *clk_data;
+
+ clk_data = davinci_psc_register_clocks(psc0, da850_psc0_info, 16);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[3], NULL, "ti-aemif");
+ clk_register_clkdev(clk_data->clks[3], "aemif", "davinci-nand.0");
+ clk_register_clkdev(clk_data->clks[4], NULL, "spi_davinci.0");
+ clk_register_clkdev(clk_data->clks[5], NULL, "da830-mmc.0");
+ clk_register_clkdev(clk_data->clks[9], NULL, "serial8250.0");
+ clk_register_clkdev(clk_data->clks[14], "arm", NULL);
+ clk_register_clkdev(clk_data->clks[15], NULL, "davinci-rproc.0");
+
+ clk_free_onecell_data(clk_data);
+
+ clk_data = davinci_psc_register_clocks(psc1, da850_psc1_info, 32);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[1], "usb20_psc_clk", NULL);
+ clk_register_clkdev(clk_data->clks[1], NULL, "musb-da8xx");
+ clk_register_clkdev(clk_data->clks[1], NULL, "cppi41-dmaengine");
+ clk_register_clkdev(clk_data->clks[2], NULL, "ohci-da8xx");
+ clk_register_clkdev(clk_data->clks[3], "gpio", NULL);
+ clk_register_clkdev(clk_data->clks[5], NULL, "davinci_emac.1");
+ clk_register_clkdev(clk_data->clks[5], "fck", "davinci_mdio.0");
+ clk_register_clkdev(clk_data->clks[7], NULL, "davinci-mcasp.0");
+ clk_register_clkdev(clk_data->clks[8], "fck", "ahci_da850");
+ clk_register_clkdev(clk_data->clks[9], NULL, "vpif");
+ clk_register_clkdev(clk_data->clks[10], NULL, "spi_davinci.1");
+ clk_register_clkdev(clk_data->clks[11], NULL, "i2c_davinci.2");
+ clk_register_clkdev(clk_data->clks[12], NULL, "serial8250.1");
+ clk_register_clkdev(clk_data->clks[13], NULL, "serial8250.2");
+ clk_register_clkdev(clk_data->clks[14], NULL, "davinci-mcbsp.0");
+ clk_register_clkdev(clk_data->clks[15], NULL, "davinci-mcbsp.1");
+ clk_register_clkdev(clk_data->clks[16], "fck", "da8xx_lcdc.0");
+ clk_register_clkdev(clk_data->clks[17], "fck", "ehrpwm.0");
+ clk_register_clkdev(clk_data->clks[17], "fck", "ehrpwm.1");
+ clk_register_clkdev(clk_data->clks[18], NULL, "da830-mmc.1");
+ clk_register_clkdev(clk_data->clks[20], "fck", "ecap.0");
+ clk_register_clkdev(clk_data->clks[20], "fck", "ecap.1");
+ clk_register_clkdev(clk_data->clks[20], "fck", "ecap.2");
+
+ clk_free_onecell_data(clk_data);
+}
+
+#ifdef CONFIG_OF
+static void __init of_da850_psc0_clk_init(struct device_node *node)
+{
+ of_davinci_psc_clk_init(node, da850_psc0_info, 16);
+}
+CLK_OF_DECLARE(da850_psc0_clk, "ti,da850-psc0", of_da850_psc0_clk_init);
+
+static void __init of_da850_psc1_clk_init(struct device_node *node)
+{
+ of_davinci_psc_clk_init(node, da850_psc1_info, 32);
+}
+CLK_OF_DECLARE(da850_psc1_clk, "ti,da850-psc1", of_da850_psc1_clk_init);
+#endif
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 3ec8100..3d8bdfa 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -17,5 +17,6 @@ void dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void dm646x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void da830_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
+void da850_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 11/44] clk: davinci: Add platform information for TI DA830 PSC
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PSC clocks on TI DA830/
OMAP-L137/AM17XX SoCs.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/psc-da830.c | 96 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 2 +
3 files changed, 99 insertions(+)
create mode 100644 drivers/clk/davinci/psc-da830.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index cd1bf2c..fb14c8c 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -10,4 +10,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o
obj-y += psc.o
+obj-$(CONFIG_ARCH_DAVINCI_DA830) += psc-da830.o
endif
diff --git a/drivers/clk/davinci/psc-da830.c b/drivers/clk/davinci/psc-da830.c
new file mode 100644
index 0000000..193b08f
--- /dev/null
+++ b/drivers/clk/davinci/psc-da830.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PSC clock descriptions for TI DA830/OMAP-L137/AM17XX
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "psc.h"
+
+static const struct davinci_psc_clk_info da830_psc0_info[] __initconst = {
+ LPSC(0, 0, tpcc, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(1, 0, tptc0, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(2, 0, tptc1, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(3, 0, aemif, pll0_sysclk3, LPSC_ALWAYS_ENABLED),
+ LPSC(4, 0, spi0, pll0_sysclk2, 0),
+ LPSC(5, 0, mmcsd, pll0_sysclk2, 0),
+ LPSC(6, 0, aintc, pll0_sysclk4, LPSC_ALWAYS_ENABLED),
+ LPSC(7, 0, arm_rom, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(8, 0, secu_mgr, pll0_sysclk4, LPSC_ALWAYS_ENABLED),
+ LPSC(9, 0, uart0, pll0_sysclk2, 0),
+ LPSC(10, 0, scr0_ss, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(11, 0, scr1_ss, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(12, 0, scr2_ss, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(13, 0, dmax, pll0_sysclk2, LPSC_ALWAYS_ENABLED),
+ LPSC(14, 0, arm, pll0_sysclk6, LPSC_ALWAYS_ENABLED),
+ { }
+};
+
+static const struct davinci_psc_clk_info da830_psc1_info[] __initconst = {
+ LPSC(1, 0, usb0, pll0_sysclk2, 0),
+ LPSC(2, 0, usb1, pll0_sysclk4, 0),
+ LPSC(3, 0, gpio, pll0_sysclk4, 0),
+ LPSC(5, 0, emac, pll0_sysclk4, 0),
+ LPSC(6, 0, emif3, pll0_sysclk5, LPSC_ALWAYS_ENABLED),
+ LPSC(7, 0, mcasp0, pll0_sysclk2, 0),
+ LPSC(8, 0, mcasp1, pll0_sysclk2, 0),
+ LPSC(9, 0, mcasp2, pll0_sysclk2, 0),
+ LPSC(10, 0, spi1, pll0_sysclk2, 0),
+ LPSC(11, 0, i2c1, pll0_sysclk4, 0),
+ LPSC(12, 0, uart1, pll0_sysclk2, 0),
+ LPSC(13, 0, uart2, pll0_sysclk2, 0),
+ LPSC(16, 0, lcdc, pll0_sysclk2, 0),
+ LPSC(17, 0, pwm, pll0_sysclk2, 0),
+ LPSC(20, 0, ecap, pll0_sysclk2, 0),
+ LPSC(21, 0, eqep, pll0_sysclk2, 0),
+ { }
+};
+
+void __init da830_psc_clk_init(void __iomem *psc0, void __iomem *psc1)
+{
+ struct clk_onecell_data *clk_data;
+
+ clk_data = davinci_psc_register_clocks(psc0, da830_psc0_info, 16);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[4], NULL, "spi_davinci.0");
+ clk_register_clkdev(clk_data->clks[5], NULL, "da830-mmc.0");
+ clk_register_clkdev(clk_data->clks[9], NULL, "serial8250.0");
+ clk_register_clkdev(clk_data->clks[14], "arm", NULL);
+
+ clk_free_onecell_data(clk_data);
+
+ clk_data = davinci_psc_register_clocks(psc1, da830_psc1_info, 32);
+ if (!clk_data)
+ return;
+
+ clk_register_clkdev(clk_data->clks[1], NULL, "musb-da8xx");
+ clk_register_clkdev(clk_data->clks[1], NULL, "cppi41-dmaengine");
+ clk_register_clkdev(clk_data->clks[2], NULL, "ohci-da8xx");
+ clk_register_clkdev(clk_data->clks[3], "gpio", NULL);
+ clk_register_clkdev(clk_data->clks[5], NULL, "davinci_emac.1");
+ clk_register_clkdev(clk_data->clks[5], "fck", "davinci_mdio.0");
+ clk_register_clkdev(clk_data->clks[7], NULL, "davinci-mcasp.0");
+ clk_register_clkdev(clk_data->clks[8], NULL, "davinci-mcasp.1");
+ clk_register_clkdev(clk_data->clks[9], NULL, "davinci-mcasp.2");
+ clk_register_clkdev(clk_data->clks[10], NULL, "spi_davinci.1");
+ clk_register_clkdev(clk_data->clks[11], NULL, "i2c_davinci.2");
+ clk_register_clkdev(clk_data->clks[12], NULL, "serial8250.1");
+ clk_register_clkdev(clk_data->clks[13], NULL, "serial8250.2");
+ clk_register_clkdev(clk_data->clks[16], "fck", "da8xx_lcdc.0");
+ clk_register_clkdev(clk_data->clks[17], "fck", "ehrpwm.0");
+ clk_register_clkdev(clk_data->clks[17], "fck", "ehrpwm.1");
+ clk_register_clkdev(clk_data->clks[20], "fck", "ecap.0");
+ clk_register_clkdev(clk_data->clks[20], "fck", "ecap.1");
+ clk_register_clkdev(clk_data->clks[20], "fck", "ecap.2");
+ clk_register_clkdev(clk_data->clks[21], NULL, "eqep.0");
+ clk_register_clkdev(clk_data->clks[21], NULL, "eqep.1");
+
+ clk_free_onecell_data(clk_data);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index d495de7..3ec8100 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -16,4 +16,6 @@ void dm365_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void dm646x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
+void da830_psc_clk_init(void __iomem *psc0, void __iomem *psc1);
+
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 10/44] clk: davinci: New driver for davinci PSC clocks
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds a new driver for mach-davinci PSC clocks. This is porting the
code from arch/arm/mach-davinci/psc.c to the common clock framework and
is converting it to use regmap to simplify the code. Additionally, it adds
device tree support for these clocks.
Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the keystone driver
makes the assumption that there is only one PSC per SoC and uses global
variables, but here we have two controllers per SoC.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 2 +
drivers/clk/davinci/psc.c | 282 +++++++++++++++++++++++++++++++++++++++++++
drivers/clk/davinci/psc.h | 49 ++++++++
3 files changed, 333 insertions(+)
create mode 100644 drivers/clk/davinci/psc.c
create mode 100644 drivers/clk/davinci/psc.h
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index d471386..cd1bf2c 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -8,4 +8,6 @@ obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o
obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o
+
+obj-y += psc.o
endif
diff --git a/drivers/clk/davinci/psc.c b/drivers/clk/davinci/psc.c
new file mode 100644
index 0000000..a8b5f57
--- /dev/null
+++ b/drivers/clk/davinci/psc.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock driver for TI Davinci PSC controllers
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ *
+ * Based on: drivers/clk/keystone/gate.c
+ * Copyright (C) 2013 Texas Instruments.
+ * Murali Karicheri <m-karicheri2@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * And: arch/arm/mach-davinci/psc.c
+ * Copyright (C) 2006 Texas Instruments.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clk/davinci.h>
+#include <linux/clkdev.h>
+#include <linux/err.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "psc.h"
+
+/* PSC register offsets */
+#define EPCPR 0x070
+#define PTCMD 0x120
+#define PTSTAT 0x128
+#define PDSTAT(n) (0x200 + 4 * (n))
+#define PDCTL(n) (0x300 + 4 * (n))
+#define MDSTAT(n) (0x800 + 4 * (n))
+#define MDCTL(n) (0xa00 + 4 * (n))
+
+/* PSC module states */
+enum davinci_psc_state {
+ PSC_STATE_SWRSTDISABLE = 0,
+ PSC_STATE_SYNCRST = 1,
+ PSC_STATE_DISABLE = 2,
+ PSC_STATE_ENABLE = 3,
+};
+
+#define MDSTAT_STATE_MASK 0x3f
+#define MDSTAT_MCKOUT BIT(12)
+#define PDSTAT_STATE_MASK 0x1f
+#define MDCTL_FORCE BIT(31)
+#define MDCTL_LRESET BIT(8)
+#define PDCTL_EPCGOOD BIT(8)
+#define PDCTL_NEXT BIT(0)
+
+/**
+ * struct davinci_psc_clk - PSC clock structure
+ * @hw: clk_hw for the psc
+ * @regmap: PSC MMIO region
+ * @lpsc: Local PSC number (module id)
+ * @pd: Power domain
+ * @flags: LPSC_* quirk flags
+ */
+struct davinci_psc_clk {
+ struct clk_hw hw;
+ struct regmap *regmap;
+ u32 lpsc;
+ u32 pd;
+ u32 flags;
+};
+
+#define to_davinci_psc_clk(_hw) container_of(_hw, struct davinci_psc_clk, hw)
+
+static void psc_config(struct davinci_psc_clk *psc,
+ enum davinci_psc_state next_state)
+{
+ u32 epcpr, pdstat, mdstat, mdctl, ptstat;
+
+ mdctl = next_state;
+ if (psc->flags & LPSC_FORCE)
+ mdctl |= MDCTL_FORCE;
+ regmap_write_bits(psc->regmap, MDCTL(psc->lpsc), MDSTAT_STATE_MASK,
+ mdctl);
+
+ regmap_read(psc->regmap, PDSTAT(psc->pd), &pdstat);
+ if ((pdstat & PDSTAT_STATE_MASK) == 0) {
+ regmap_write_bits(psc->regmap, PDSTAT(psc->pd),
+ PDSTAT_STATE_MASK, PDCTL_NEXT);
+
+ regmap_write(psc->regmap, PTCMD, BIT(psc->pd));
+
+ regmap_read_poll_timeout(psc->regmap, EPCPR, epcpr,
+ epcpr & BIT(psc->pd), 0, 0);
+
+ regmap_write_bits(psc->regmap, PDCTL(psc->pd), PDCTL_EPCGOOD,
+ PDCTL_EPCGOOD);
+ } else {
+ regmap_write(psc->regmap, PTCMD, BIT(psc->pd));
+ }
+
+ regmap_read_poll_timeout(psc->regmap, PTSTAT, ptstat,
+ !(ptstat & BIT(psc->pd)), 0, 0);
+
+ regmap_read_poll_timeout(psc->regmap, MDSTAT(psc->lpsc), mdstat,
+ (mdstat & MDSTAT_STATE_MASK) == next_state,
+ 0, 0);
+}
+
+static int davinci_psc_clk_enable(struct clk_hw *hw)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(hw);
+
+ psc_config(psc, PSC_STATE_ENABLE);
+
+ return 0;
+}
+
+static void davinci_psc_clk_disable(struct clk_hw *hw)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(hw);
+
+ psc_config(psc, PSC_STATE_DISABLE);
+}
+
+static int davinci_psc_clk_is_enabled(struct clk_hw *hw)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(hw);
+ u32 mdstat;
+
+ regmap_read(psc->regmap, MDSTAT(psc->lpsc), &mdstat);
+
+ return (mdstat & MDSTAT_MCKOUT) ? 1 : 0;
+}
+
+static const struct clk_ops davinci_psc_clk_ops = {
+ .enable = davinci_psc_clk_enable,
+ .disable = davinci_psc_clk_disable,
+ .is_enabled = davinci_psc_clk_is_enabled,
+};
+
+/**
+ * davinci_psc_clk_register - register psc clock
+ * @dev: device that is registering this clock
+ * @name: name of this clock
+ * @parent_name: name of clock's parent
+ * @regmap: PSC MMIO region
+ * @lpsc: local PSC number
+ * @pd: power domain
+ * @flags: LPSC_* flags
+ */
+static struct clk *davinci_psc_clk_register(const char *name,
+ const char *parent_name,
+ struct regmap *regmap,
+ u32 lpsc, u32 pd, u32 flags)
+{
+ struct clk_init_data init;
+ struct davinci_psc_clk *psc;
+ struct clk *clk;
+
+ psc = kzalloc(sizeof(*psc), GFP_KERNEL);
+ if (!psc)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &davinci_psc_clk_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = CLK_SET_RATE_PARENT;
+
+ if (flags & LPSC_ALWAYS_ENABLED)
+ init.flags |= CLK_IS_CRITICAL;
+
+ psc->regmap = regmap;
+ psc->hw.init = &init;
+ psc->lpsc = lpsc;
+ psc->pd = pd;
+ psc->flags = flags;
+
+ clk = clk_register(NULL, &psc->hw);
+ if (IS_ERR(clk))
+ kfree(psc);
+
+ return clk;
+}
+
+/*
+ * FIXME: This needs to be converted to a reset controller. But, the reset
+ * framework is currently device tree only.
+ */
+
+static int davinci_psc_clk_reset(struct davinci_psc_clk *psc, bool reset)
+{
+ u32 mdctl;
+
+ if (IS_ERR_OR_NULL(psc))
+ return -EINVAL;
+
+ mdctl = reset ? 0 : MDCTL_LRESET;
+ regmap_write_bits(psc->regmap, MDCTL(psc->lpsc), MDCTL_LRESET, mdctl);
+
+ return 0;
+}
+
+int davinci_clk_reset_assert(struct clk *clk)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk));
+
+ return davinci_psc_clk_reset(psc, true);
+}
+EXPORT_SYMBOL(davinci_clk_reset_assert);
+
+int davinci_clk_reset_deassert(struct clk *clk)
+{
+ struct davinci_psc_clk *psc = to_davinci_psc_clk(__clk_get_hw(clk));
+
+ return davinci_psc_clk_reset(psc, false);
+}
+EXPORT_SYMBOL(davinci_clk_reset_deassert);
+
+static const struct regmap_config davinci_psc_regmap_config = {
+ .reg_bits = 32,
+ .reg_stride = 4,
+ .val_bits = 32,
+};
+
+struct clk_onecell_data *
+davinci_psc_register_clocks(void __iomem *base,
+ const struct davinci_psc_clk_info *info,
+ u8 num_clks)
+{
+ struct clk_onecell_data *clk_data;
+ struct regmap *regmap;
+
+ clk_data = clk_alloc_onecell_data(num_clks);
+ if (!clk_data) {
+ pr_err("%s: Out of memory\n", __func__);
+ return NULL;
+ }
+
+ regmap = regmap_init_mmio(NULL, base, &davinci_psc_regmap_config);
+ if (IS_ERR(regmap)) {
+ pr_err("%s: regmap_init_mmio failed (%ld)\n", __func__,
+ PTR_ERR(regmap));
+ clk_free_onecell_data(clk_data);
+ return NULL;
+ }
+
+ for (; info->name; info++) {
+ struct clk *clk;
+
+ clk = davinci_psc_clk_register(info->name, info->parent, regmap,
+ info->lpsc, info->pd, info->flags);
+ if (IS_ERR(clk)) {
+ pr_warn("%s: Failed to register %s (%ld)\n", __func__,
+ info->name, PTR_ERR(clk));
+ continue;
+ }
+
+ clk_data->clks[info->lpsc] = clk;
+ }
+
+ return clk_data;
+}
+
+#ifdef CONFIG_OF
+void of_davinci_psc_clk_init(struct device_node *node,
+ const struct davinci_psc_clk_info *info,
+ u8 num_clks)
+{
+ struct clk_onecell_data *clk_data;
+ void __iomem *base;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: ioremap failed\n", __func__);
+ return;
+ }
+
+ clk_data = davinci_psc_register_clocks(base, info, num_clks);
+ if (!clk_data)
+ return;
+
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
+}
+#endif
diff --git a/drivers/clk/davinci/psc.h b/drivers/clk/davinci/psc.h
new file mode 100644
index 0000000..6022f6e
--- /dev/null
+++ b/drivers/clk/davinci/psc.h
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock driver for TI Davinci PSC controllers
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#ifndef __CLK_DAVINCI_PSC_H__
+#define __CLK_DAVINCI_PSC_H__
+
+#include <linux/types.h>
+
+/* PSC quirk flags */
+#define LPSC_ALWAYS_ENABLED BIT(1) /* never disable this clock */
+#define LPSC_FORCE BIT(2) /* requires MDCTL FORCE bit */
+#define LPSC_LOCAL_RESET BIT(3) /* acts as reset provider */
+
+struct clk_onecell_data;
+
+struct davinci_psc_clk_info {
+ const char *name;
+ const char *parent;
+ u32 lpsc;
+ u32 pd;
+ unsigned long flags;
+ bool has_reset;
+};
+
+#define LPSC(l, d, n, p, f) \
+{ \
+ .name = #n, \
+ .parent = #p, \
+ .lpsc = (l), \
+ .pd = (d), \
+ .flags = (f), \
+}
+
+struct clk_onecell_data *
+davinci_psc_register_clocks(void __iomem *base,
+ const struct davinci_psc_clk_info *info,
+ u8 num_clks);
+
+#ifdef CONFIG_OF
+void of_davinci_psc_clk_init(struct device_node *node,
+ const struct davinci_psc_clk_info *info,
+ u8 num_clks);
+#endif
+
+#endif /* __CLK_DAVINCI_PSC_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 09/44] dt-bindings: clock: New bindings for TI Davinci PSC
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds a new binding for the Power Sleep Controller (PSC) for the
mach-davinci family of processors.
Note: Although TI Keystone has a very similar PSC, we are not using the
existing bindings. Keystone is using a legacy one-node-per-clock binding
(actually two nodes if you count the separate reset binding for the same
IP block). Also, some davinci LPSCs have quirks that aren't handled by
the keystone bindings, so we would be adding one compatible string per
clock with quirks instead of just a new compatible string for each
controller.
Signed-off-by: David Lechner <david@lechnology.com>
---
.../devicetree/bindings/clock/ti/davinci/psc.txt | 47 ++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
new file mode 100644
index 0000000..83a9da5
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
@@ -0,0 +1,47 @@
+Binding for TI DaVinci Power Sleep Controller (PSC)
+
+The PSC provides power management, clock gating and reset functionality. It is
+primarily used for clocking.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-psc0" for PSC0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-psc1" for PSC1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area.
+- #clock-cells: from common clock binding; shall be set to 1.
+- #reset-cells: from reset binding; shall be set to 1.
+
+Consumers:
+
+ Clock and reset consumers shall use the local power domain module ID
+ (LPSC) as the index corresponding to the clock cell. Refer to the
+ device-specific datasheet to find these numbers. NB: Most local domains
+ only provide a clock and not a reset.
+
+Examples:
+
+ psc0: clock-controller at 10000 {
+ compatible = "ti,da850-psc0";
+ reg = <0x10000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ /* consumer */
+ dsp: dsp at 11800000 {
+ compatible = "ti,da850-dsp";
+ reg = <0x11800000 0x40000>,
+ <0x11e00000 0x8000>,
+ <0x11f00000 0x8000>,
+ <0x01c14044 0x4>,
+ <0x01c14174 0x8>;
+ reg-names = "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig";
+ interrupt-parent = <&intc>;
+ interrupts = <28>;
+ clocks = <&psc0 15>;
+ resets = <&psc0 15>;
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
+- Documentation/devicetree/bindings/reset/reset.txt
--
2.7.4
^ permalink raw reply related
* [PATCH v5 08/44] clk: davinci: Add platform information for TI DM646x PLL
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PLL clocks on TI
DaVinci 646x based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/pll-dm646x.c | 44 ++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 46 insertions(+)
create mode 100644 drivers/clk/davinci/pll-dm646x.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index 59d8ab6..d471386 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -7,4 +7,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o
obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o
+obj-$(CONFIG_ARCH_DAVINCI_DM646x) += pll-dm646x.o
endif
diff --git a/drivers/clk/davinci/pll-dm646x.c b/drivers/clk/davinci/pll-dm646x.c
new file mode 100644
index 0000000..9d5bdaf
--- /dev/null
+++ b/drivers/clk/davinci/pll-dm646x.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock descriptions for TI DM646X
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "pll.h"
+
+static const struct davinci_pll_divclk_info dm646x_pll1_divclk_info[] __initconst = {
+ DIVCLK(1, pll1_sysclk1, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(2, pll1_sysclk2, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(3, pll1_sysclk3, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(4, pll1_sysclk4, pll1, 0),
+ DIVCLK(5, pll1_sysclk5, pll1, 0),
+ DIVCLK(6, pll1_sysclk6, pll1, 0),
+ DIVCLK(7, pll1_sysclk7, pll1, 0),
+ DIVCLK(8, pll1_sysclk8, pll1, 0),
+ DIVCLK(9, pll1_sysclk9, pll1, 0),
+ { }
+};
+
+static const struct davinci_pll_divclk_info dm646x_pll2_divclk_info[] __initconst = {
+ DIVCLK(1, pll2_sysclk1, pll2, 0),
+ { }
+};
+
+void __init dm646x_pll_clk_init(void __iomem *pll1, void __iomem *pll2)
+{
+ const struct davinci_pll_divclk_info *info;
+
+ davinci_pll_clk_register("pll1", "ref_clk", pll1);
+ for (info = dm646x_pll1_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll1);
+ davinci_pll_bpdiv_clk_register("pll1_sysclkbp", "ref_clk", pll1);
+ davinci_pll_aux_clk_register("pll1_aux_clk", "ref_clk", pll1);
+
+ davinci_pll_clk_register("pll2_clk", "ref_clk", pll2);
+ for (info = dm646x_pll2_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll2);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 535990a..d495de7 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -14,5 +14,6 @@ void da850_pll_clk_init(void __iomem *pll0, void __iomem *pll1);
void dm355_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void dm365_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
+void dm646x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 07/44] clk: davinci: Add platform information for TI DM644x PLL
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PLL clocks on TI
DaVinci 644x based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/pll-dm644x.c | 41 ++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 43 insertions(+)
create mode 100644 drivers/clk/davinci/pll-dm644x.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index 353aa02..59d8ab6 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -6,4 +6,5 @@ obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o
+obj-$(CONFIG_ARCH_DAVINCI_DM644x) += pll-dm644x.o
endif
diff --git a/drivers/clk/davinci/pll-dm644x.c b/drivers/clk/davinci/pll-dm644x.c
new file mode 100644
index 0000000..b0d0373
--- /dev/null
+++ b/drivers/clk/davinci/pll-dm644x.c
@@ -0,0 +1,41 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock descriptions for TI DM644X
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "pll.h"
+
+static const struct davinci_pll_divclk_info dm644x_pll1_divclk_info[] __initconst = {
+ DIVCLK(1, pll1_sysclk1, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(2, pll1_sysclk2, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(3, pll1_sysclk3, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(5, pll1_sysclk5, pll1, DIVCLK_FIXED_DIV),
+ { }
+};
+
+static const struct davinci_pll_divclk_info dm644x_pll2_divclk_info[] __initconst = {
+ DIVCLK(1, pll2_sysclk1, pll2, 0),
+ DIVCLK(2, pll2_sysclk2, pll2, 0),
+ { }
+};
+
+void __init dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2)
+{
+ const struct davinci_pll_divclk_info *info;
+
+ davinci_pll_clk_register("pll1", "ref_clk", pll1);
+ for (info = dm644x_pll1_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll1);
+ davinci_pll_aux_clk_register("pll1_aux_clk", "ref_clk", pll1);
+ davinci_pll_bpdiv_clk_register("pll1_sysclkbp", "ref_clk", pll1);
+
+ davinci_pll_clk_register("pll2", "ref_clk", pll2);
+ for (info = dm644x_pll2_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll2);
+ davinci_pll_bpdiv_clk_register("pll2_sysclkbp", "ref_clk", pll2);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 5bf60a7..535990a 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -13,5 +13,6 @@ void da830_pll_clk_init(void __iomem *pll);
void da850_pll_clk_init(void __iomem *pll0, void __iomem *pll1);
void dm355_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
void dm365_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
+void dm644x_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 06/44] clk: davinci: Add platform information for TI DM365 PLL
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PLL clocks on TI
DaVinci 365 based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/pll-dm365.c | 64 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 66 insertions(+)
create mode 100644 drivers/clk/davinci/pll-dm365.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index 6720bd0..353aa02 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -5,4 +5,5 @@ obj-y += pll.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
+obj-$(CONFIG_ARCH_DAVINCI_DM365) += pll-dm365.o
endif
diff --git a/drivers/clk/davinci/pll-dm365.c b/drivers/clk/davinci/pll-dm365.c
new file mode 100644
index 0000000..9892b0b
--- /dev/null
+++ b/drivers/clk/davinci/pll-dm365.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock descriptions for TI DM365
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include "pll.h"
+
+static const char * const dm365_pll_obsclk_parent_names[] = {
+ "ref_clk",
+};
+
+static u32 dm365_pll_obsclk_table[] = {
+ 0x10,
+};
+
+static const struct davinci_pll_divclk_info dm365_pll1_divclk_info[] __initconst = {
+ DIVCLK(1, pll1_sysclk1, pll1, 0),
+ DIVCLK(2, pll1_sysclk2, pll1, 0),
+ DIVCLK(3, pll1_sysclk3, pll1, 0),
+ DIVCLK(4, pll1_sysclk4, pll1, 0),
+ DIVCLK(5, pll1_sysclk5, pll1, 0),
+ DIVCLK(6, pll1_sysclk6, pll1, 0),
+ DIVCLK(7, pll1_sysclk7, pll1, 0),
+ DIVCLK(8, pll1_sysclk8, pll1, 0),
+ DIVCLK(9, pll1_sysclk9, pll1, 0),
+ { }
+};
+
+static const struct davinci_pll_divclk_info dm365_pll2_divclk_info[] __initconst = {
+ DIVCLK(1, pll2_sysclk1, pll2, 0),
+ DIVCLK(2, pll2_sysclk2, pll2, 0),
+ DIVCLK(3, pll2_sysclk3, pll2, 0),
+ DIVCLK(4, pll2_sysclk4, pll2, 0),
+ DIVCLK(5, pll2_sysclk5, pll2, 0),
+ { }
+};
+
+void __init dm365_pll_clk_init(void __iomem *pll1, void __iomem *pll2)
+{
+ const struct davinci_pll_divclk_info *info;
+
+ davinci_pll_clk_register("pll1", "ref_clk", pll1);
+ davinci_pll_aux_clk_register("pll1_aux_clk", "ref_clk", pll1);
+ davinci_pll_bpdiv_clk_register("pll1_sysclkbp", "ref_clk", pll1);
+ davinci_pll_obs_clk_register("clkout0", dm365_pll_obsclk_parent_names,
+ ARRAY_SIZE(dm365_pll_obsclk_parent_names),
+ pll1, dm365_pll_obsclk_table);
+ for (info = dm365_pll1_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll1);
+
+ davinci_pll_clk_register("pll2", "ref_clk", pll2);
+ davinci_pll_aux_clk_register("clkout1", "ref_clk", pll2);
+ davinci_pll_obs_clk_register("clkout1", dm365_pll_obsclk_parent_names,
+ ARRAY_SIZE(dm365_pll_obsclk_parent_names),
+ pll2, dm365_pll_obsclk_table);
+ for (info = dm365_pll2_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll2);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 95333fe..5bf60a7 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -12,5 +12,6 @@
void da830_pll_clk_init(void __iomem *pll);
void da850_pll_clk_init(void __iomem *pll0, void __iomem *pll1);
void dm355_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
+void dm365_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 05/44] clk: davinci: Add platform information for TI DM355 PLL
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PLL clocks on TI
DaVinci 355 based systems.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/pll-dm355.c | 40 ++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 42 insertions(+)
create mode 100644 drivers/clk/davinci/pll-dm355.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index 13049d4..6720bd0 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -4,4 +4,5 @@ ifeq ($(CONFIG_COMMON_CLK), y)
obj-y += pll.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
+obj-$(CONFIG_ARCH_DAVINCI_DM355) += pll-dm355.o
endif
diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c
new file mode 100644
index 0000000..972fd2b
--- /dev/null
+++ b/drivers/clk/davinci/pll-dm355.c
@@ -0,0 +1,40 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock descriptions for TI DM355
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "pll.h"
+
+static const struct davinci_pll_divclk_info dm355_pll1_divclk_info[] __initconst = {
+ DIVCLK(1, pll1_sysclk1, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(2, pll1_sysclk2, pll1, DIVCLK_FIXED_DIV),
+ DIVCLK(3, pll1_sysclk3, pll1, 0),
+ DIVCLK(4, pll1_sysclk4, pll1, 0),
+ { }
+};
+
+static const struct davinci_pll_divclk_info dm355_pll2_divclk_info[] __initconst = {
+ DIVCLK(1, pll2_sysclk1, pll2, DIVCLK_FIXED_DIV),
+ { }
+};
+
+void __init dm355_pll_clk_init(void __iomem *pll1, void __iomem *pll2)
+{
+ const struct davinci_pll_divclk_info *info;
+
+ davinci_pll_clk_register("pll1", "ref_clk", pll1);
+ for (info = dm355_pll1_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll1);
+ davinci_pll_aux_clk_register("pll1_aux_clk", "ref_clk", pll1);
+ davinci_pll_bpdiv_clk_register("pll1_sysclkbp", "ref_clk", pll1);
+
+ davinci_pll_clk_register("pll2", "ref_clk", pll2);
+ for (info = dm355_pll2_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll2);
+ davinci_pll_bpdiv_clk_register("pll2_sysclkbp", "ref_clk", pll2);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 7b08fe0..95333fe 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -11,5 +11,6 @@
void da830_pll_clk_init(void __iomem *pll);
void da850_pll_clk_init(void __iomem *pll0, void __iomem *pll1);
+void dm355_pll_clk_init(void __iomem *pll1, void __iomem *pll2);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 04/44] clk: davinci: Add platform information for TI DA850 PLL
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PLL clocks on TI DA850/
OMAP-L138/AM18XX SoCs.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/pll-da850.c | 67 +++++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 1 +
3 files changed, 69 insertions(+)
create mode 100644 drivers/clk/davinci/pll-da850.c
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index 9061e19..13049d4 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -3,4 +3,5 @@
ifeq ($(CONFIG_COMMON_CLK), y)
obj-y += pll.o
obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
+obj-$(CONFIG_ARCH_DAVINCI_DA850) += pll-da850.o
endif
diff --git a/drivers/clk/davinci/pll-da850.c b/drivers/clk/davinci/pll-da850.c
new file mode 100644
index 0000000..2f00f3d
--- /dev/null
+++ b/drivers/clk/davinci/pll-da850.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock descriptions for TI DA850/OMAP-L138/AM18XX
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/clkdev.h>
+#include <linux/init.h>
+#include <linux/of.h>
+#include <linux/types.h>
+
+#include "pll.h"
+
+/*
+ * NB: Technically, the clocks flagged as DIVCLK_FIXED_DIV are "fixed ratio",
+ * meaning that we could change the divider as long as we keep the correct
+ * ratio between all of the clocks, but we don't support that because there is
+ * currently not a need for it.
+ */
+
+static const struct davinci_pll_divclk_info da850_pll0_divclk_info[] __initconst = {
+ DIVCLK(1, pll0_sysclk1, pll0, DIVCLK_FIXED_DIV),
+ DIVCLK(2, pll0_sysclk2, pll0, DIVCLK_FIXED_DIV),
+ DIVCLK(3, pll0_sysclk3, pll0, 0),
+ DIVCLK(4, pll0_sysclk4, pll0, DIVCLK_FIXED_DIV),
+ DIVCLK(5, pll0_sysclk5, pll0, 0),
+ DIVCLK(6, pll0_sysclk6, pll0, DIVCLK_ARM_RATE | DIVCLK_FIXED_DIV),
+ DIVCLK(7, pll0_sysclk7, pll0, 0),
+ { }
+};
+
+static const struct davinci_pll_divclk_info da850_pll1_divclk_info[] __initconst = {
+ DIVCLK(1, pll1_sysclk1, pll1, DIVCLK_ALWAYS_ENABLED),
+ DIVCLK(2, pll1_sysclk2, pll1, 0),
+ DIVCLK(3, pll1_sysclk3, pll1, 0),
+ { }
+};
+
+void __init da850_pll_clk_init(void __iomem *pll0, void __iomem *pll1)
+{
+ const struct davinci_pll_divclk_info *info;
+
+ davinci_pll_clk_register("pll0", "ref_clk", pll0);
+ davinci_pll_aux_clk_register("pll0_aux_clk", "ref_clk", pll0);
+ for (info = da850_pll0_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll0);
+
+ davinci_pll_clk_register("pll1", "ref_clk", pll1);
+ for (info = da850_pll1_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll1);
+}
+
+#ifdef CONFIG_OF
+static void __init of_da850_pll0_auxclk_init(struct device_node *node)
+{
+ of_davinci_pll_init(node, "pll0", da850_pll0_divclk_info, 7);
+}
+CLK_OF_DECLARE(da850_pll0_auxclk, "ti,da850-pll0", of_da850_pll0_auxclk_init);
+
+static void __init of_da850_pll1_auxclk_init(struct device_node *node)
+{
+ of_davinci_pll_init(node, "pll1", da850_pll1_divclk_info, 3);
+}
+CLK_OF_DECLARE(da850_pll1_auxclk, "ti,da850-pll1", of_da850_pll1_auxclk_init);
+#endif
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
index 4f4d60d..7b08fe0 100644
--- a/include/linux/clk/davinci.h
+++ b/include/linux/clk/davinci.h
@@ -10,5 +10,6 @@
#include <linux/types.h>
void da830_pll_clk_init(void __iomem *pll);
+void da850_pll_clk_init(void __iomem *pll0, void __iomem *pll1);
#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 03/44] clk: davinci: Add platform information for TI DA830 PLL
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds platform-specific declarations for the PLL clocks on TI DA830/
OMAP-L137/AM17XX SoCs.
Signed-off-by: David Lechner <david@lechnology.com>
---
drivers/clk/davinci/Makefile | 1 +
drivers/clk/davinci/pll-da830.c | 38 ++++++++++++++++++++++++++++++++++++++
include/linux/clk/davinci.h | 14 ++++++++++++++
3 files changed, 53 insertions(+)
create mode 100644 drivers/clk/davinci/pll-da830.c
create mode 100644 include/linux/clk/davinci.h
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
index d9673bd..9061e19 100644
--- a/drivers/clk/davinci/Makefile
+++ b/drivers/clk/davinci/Makefile
@@ -2,4 +2,5 @@
ifeq ($(CONFIG_COMMON_CLK), y)
obj-y += pll.o
+obj-$(CONFIG_ARCH_DAVINCI_DA830) += pll-da830.o
endif
diff --git a/drivers/clk/davinci/pll-da830.c b/drivers/clk/davinci/pll-da830.c
new file mode 100644
index 0000000..369db59
--- /dev/null
+++ b/drivers/clk/davinci/pll-da830.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock descriptions for TI DA830/OMAP-L137/AM17XX
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+
+#include "pll.h"
+
+/*
+ * NB: Technically, the clocks flagged as DIVCLK_FIXED_DIV are "fixed ratio",
+ * meaning that we could change the divider as long as we keep the correct
+ * ratio between all of the clocks, but we don't support that because there is
+ * currently not a need for it.
+ */
+
+static const struct davinci_pll_divclk_info da830_pll_divclk_info[] __initconst = {
+ DIVCLK(2, pll0_sysclk2, pll0, DIVCLK_FIXED_DIV),
+ DIVCLK(3, pll0_sysclk3, pll0, 0),
+ DIVCLK(4, pll0_sysclk4, pll0, DIVCLK_FIXED_DIV),
+ DIVCLK(5, pll0_sysclk5, pll0, 0),
+ DIVCLK(6, pll0_sysclk6, pll0, DIVCLK_FIXED_DIV),
+ DIVCLK(7, pll0_sysclk7, pll0, 0),
+ { }
+};
+
+void __init da830_pll_clk_init(void __iomem *pll)
+{
+ const struct davinci_pll_divclk_info *info;
+
+ davinci_pll_clk_register("pll0", "ref_clk", pll);
+ davinci_pll_aux_clk_register("pll0_aux_clk", "ref_clk", pll);
+ for (info = da830_pll_divclk_info; info->name; info++)
+ davinci_pll_divclk_register(info, pll);
+}
diff --git a/include/linux/clk/davinci.h b/include/linux/clk/davinci.h
new file mode 100644
index 0000000..4f4d60d
--- /dev/null
+++ b/include/linux/clk/davinci.h
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * TI Davinci clocks
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+#ifndef __LINUX_CLK_DAVINCI_H__
+#define __LINUX_CLK_DAVINCI_H__
+
+#include <linux/types.h>
+
+void da830_pll_clk_init(void __iomem *pll);
+
+#endif /* __LINUX_CLK_DAVINCI_H__ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 02/44] clk: davinci: New driver for davinci PLL clocks
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds a new driver for mach-davinci PLL clocks. This is porting the
code from arch/arm/mach-davinci/clock.c to the common clock framework.
Additionally, it adds device tree support for these clocks.
The ifeq ($(CONFIG_COMMON_CLK), y) in the Makefile is needed to prevent
compile errors until the clock code in arch/arm/mach-davinci is removed.
Note: although there are similar clocks for TI Keystone we are not able
to share the code for a few reasons. The keystone clocks are device tree
only and use legacy one-node-per-clock bindings. Also the register
layouts are a bit different, which would add even more if/else mess
to the keystone clocks. And the keystone PLL driver doesn't support
setting clock rates.
Signed-off-by: David Lechner <david@lechnology.com>
---
MAINTAINERS | 6 +
drivers/clk/Makefile | 1 +
drivers/clk/davinci/Makefile | 5 +
drivers/clk/davinci/pll.c | 564 +++++++++++++++++++++++++++++++++++++++++++
drivers/clk/davinci/pll.h | 61 +++++
5 files changed, 637 insertions(+)
create mode 100644 drivers/clk/davinci/Makefile
create mode 100644 drivers/clk/davinci/pll.c
create mode 100644 drivers/clk/davinci/pll.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a6e86e2..1db0cf0 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -13554,6 +13554,12 @@ F: arch/arm/mach-davinci/
F: drivers/i2c/busses/i2c-davinci.c
F: arch/arm/boot/dts/da850*
+TI DAVINCI SERIES CLOCK DRIVER
+M: David Lechner <david@lechnology.com>
+S: Maintained
+F: Documentation/devicetree/bindings/clock/ti/davinci/
+F: drivers/clk/davinci/
+
TI DAVINCI SERIES GPIO DRIVER
M: Keerthy <j-keerthy@ti.com>
L: linux-gpio at vger.kernel.org
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index f7f761b..c865fd0 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -60,6 +60,7 @@ obj-$(CONFIG_ARCH_ARTPEC) += axis/
obj-$(CONFIG_ARC_PLAT_AXS10X) += axs10x/
obj-y += bcm/
obj-$(CONFIG_ARCH_BERLIN) += berlin/
+obj-$(CONFIG_ARCH_DAVINCI) += davinci/
obj-$(CONFIG_H8300) += h8300/
obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-y += imgtec/
diff --git a/drivers/clk/davinci/Makefile b/drivers/clk/davinci/Makefile
new file mode 100644
index 0000000..d9673bd
--- /dev/null
+++ b/drivers/clk/davinci/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+
+ifeq ($(CONFIG_COMMON_CLK), y)
+obj-y += pll.o
+endif
diff --git a/drivers/clk/davinci/pll.c b/drivers/clk/davinci/pll.c
new file mode 100644
index 0000000..46f9c18
--- /dev/null
+++ b/drivers/clk/davinci/pll.c
@@ -0,0 +1,564 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PLL clock driver for TI Davinci SoCs
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ *
+ * Based on drivers/clk/keystone/pll.c
+ * Copyright (C) 2013 Texas Instruments Inc.
+ * Murali Karicheri <m-karicheri2@ti.com>
+ * Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
+ * And on arch/arm/mach-davinci/clock.c
+ * Copyright (C) 2006-2007 Texas Instruments.
+ * Copyright (C) 2008-2009 Deep Root Systems, LLC
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/of_address.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+
+#include "pll.h"
+
+#define REVID 0x000
+#define PLLCTL 0x100
+#define OCSEL 0x104
+#define PLLSECCTL 0x108
+#define PLLM 0x110
+#define PREDIV 0x114
+#define PLLDIV1 0x118
+#define PLLDIV2 0x11c
+#define PLLDIV3 0x120
+#define OSCDIV 0x124
+#define POSTDIV 0x128
+#define BPDIV 0x12c
+#define PLLCMD 0x138
+#define PLLSTAT 0x13c
+#define ALNCTL 0x140
+#define DCHANGE 0x144
+#define CKEN 0x148
+#define CKSTAT 0x14c
+#define SYSTAT 0x150
+#define PLLDIV4 0x160
+#define PLLDIV5 0x164
+#define PLLDIV6 0x168
+#define PLLDIV7 0x16c
+#define PLLDIV8 0x170
+#define PLLDIV9 0x174
+
+#define PLLCTL_PLLEN BIT(0)
+#define PLLCTL_PLLPWRDN BIT(1)
+#define PLLCTL_PLLRST BIT(3)
+#define PLLCTL_PLLDIS BIT(4)
+#define PLLCTL_PLLENSRC BIT(5)
+#define PLLCTL_CLKMODE BIT(8)
+
+#define PLLM_MASK 0x1f
+#define PREDIV_RATIO_MASK 0x1f
+#define PREDIV_PREDEN BIT(15)
+#define PLLDIV_RATIO_WIDTH 5
+#define PLLDIV_ENABLE_SHIFT 15
+#define OSCDIV_RATIO_WIDTH 5
+#define POSTDIV_RATIO_MASK 0x1f
+#define POSTDIV_POSTDEN BIT(15)
+#define BPDIV_RATIO_SHIFT 0
+#define BPDIV_RATIO_WIDTH 5
+#define CKEN_OBSCLK_SHIFT 1
+#define CKEN_AUXEN_SHIFT 0
+
+/*
+ * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN
+ * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us
+ * ensures we are good for all > 4MHz OSCIN/CLKIN inputs. Typically the input
+ * is ~25MHz. Units are micro seconds.
+ */
+#define PLL_BYPASS_TIME 1
+/* From OMAP-L138 datasheet table 6-4. Units are micro seconds */
+#define PLL_RESET_TIME 1
+/*
+ * From OMAP-L138 datasheet table 6-4; assuming prediv = 1, sqrt(pllm) = 4
+ * Units are micro seconds.
+ */
+#define PLL_LOCK_TIME 20
+
+/**
+ * struct davinci_pll_clk - Main PLL clock
+ * @hw: clk_hw for the pll
+ * @base: Base memory address
+ * @parent_rate: Saved parent rate used by some child clocks
+ */
+struct davinci_pll_clk {
+ struct clk_hw hw;
+ void __iomem *base;
+};
+
+#define to_davinci_pll_clk(_hw) container_of((_hw), struct davinci_pll_clk, hw)
+
+static unsigned long davinci_pll_clk_recalc(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
+ unsigned long rate = parent_rate;
+ u32 prediv, mult, postdiv;
+
+ prediv = readl(pll->base + PREDIV) & PREDIV_RATIO_MASK;
+ mult = readl(pll->base + PLLM) & PLLM_MASK;
+ postdiv = readl(pll->base + POSTDIV) & POSTDIV_RATIO_MASK;
+
+ rate /= prediv + 1;
+ rate *= mult + 1;
+ rate /= postdiv + 1;
+
+ return rate;
+}
+
+/**
+ * davinci_pll_get_best_rate - Calculate PLL output closest to a given rate
+ * @rate: The target rate
+ * @parent_rate: The PLL input clock rate
+ * @mult: Pointer to hold the multiplier value (optional)
+ * @postdiv: Pointer to hold the postdiv value (optional)
+ *
+ * Returns: The closest rate less than or equal to @rate that the PLL can
+ * generate. @mult and @postdiv will contain the values required to generate
+ * that rate.
+ */
+static long davinci_pll_get_best_rate(u32 rate, u32 parent_rate, u32 *mult,
+ u32 *postdiv)
+{
+ u32 r, m, d;
+ u32 best_rate = 0;
+ u32 best_mult = 0;
+ u32 best_postdiv = 0;
+
+ for (d = 1; d <= 4; d++) {
+ for (m = min(32U, rate * d / parent_rate); m > 0; m--) {
+ r = parent_rate * m / d;
+
+ if (r < best_rate)
+ break;
+
+ if (r > best_rate && r <= rate) {
+ best_rate = r;
+ best_mult = m;
+ best_postdiv = d;
+ }
+
+ if (best_rate == rate)
+ goto out;
+ }
+ }
+
+out:
+ if (mult)
+ *mult = best_mult;
+ if (postdiv)
+ *postdiv = best_postdiv;
+
+ return best_rate;
+}
+
+static long davinci_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ return davinci_pll_get_best_rate(rate, *parent_rate, NULL, NULL);
+}
+
+/**
+ * __davinci_pll_set_rate - set the output rate of a given PLL.
+ *
+ * Note: Currently tested to work with OMAP-L138 only.
+ *
+ * @pll: pll whose rate needs to be changed.
+ * @prediv: The pre divider value. Passing 0 disables the pre-divider.
+ * @pllm: The multiplier value. Passing 0 leads to multiply-by-one.
+ * @postdiv: The post divider value. Passing 0 disables the post-divider.
+ */
+static void __davinci_pll_set_rate(struct davinci_pll_clk *pll, u32 prediv,
+ u32 mult, u32 postdiv)
+{
+ u32 ctrl, locktime;
+
+ /*
+ * PLL lock time required per OMAP-L138 datasheet is
+ * (2000 * prediv)/sqrt(pllm) OSCIN cycles. We approximate sqrt(pllm)
+ * as 4 and OSCIN cycle as 25 MHz.
+ */
+ if (prediv) {
+ locktime = ((2000 * prediv) / 100);
+ prediv = (prediv - 1) | PREDIV_PREDEN;
+ } else {
+ locktime = PLL_LOCK_TIME;
+ }
+ if (postdiv)
+ postdiv = (postdiv - 1) | POSTDIV_POSTDEN;
+ if (mult)
+ mult = mult - 1;
+
+ ctrl = readl(pll->base + PLLCTL);
+
+ /* Switch the PLL to bypass mode */
+ ctrl &= ~(PLLCTL_PLLENSRC | PLLCTL_PLLEN);
+ writel(ctrl, pll->base + PLLCTL);
+
+ udelay(PLL_BYPASS_TIME);
+
+ /* Reset and enable PLL */
+ ctrl &= ~(PLLCTL_PLLRST | PLLCTL_PLLDIS);
+ writel(ctrl, pll->base + PLLCTL);
+
+ writel(prediv, pll->base + PREDIV);
+ writel(mult, pll->base + PLLM);
+ writel(postdiv, pll->base + POSTDIV);
+
+ udelay(PLL_RESET_TIME);
+
+ /* Bring PLL out of reset */
+ ctrl |= PLLCTL_PLLRST;
+ writel(ctrl, pll->base + PLLCTL);
+
+ udelay(locktime);
+
+ /* Remove PLL from bypass mode */
+ ctrl |= PLLCTL_PLLEN;
+ writel(ctrl, pll->base + PLLCTL);
+}
+
+static int davinci_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
+ u32 mult, postdiv;
+
+ davinci_pll_get_best_rate(rate, parent_rate, &mult, &postdiv);
+ __davinci_pll_set_rate(pll, 1, mult, postdiv);
+
+ return 0;
+}
+
+#ifdef CONFIG_DEBUG_FS
+#include <linux/debugfs.h>
+
+#define DEBUG_REG(n) \
+{ \
+ .name = #n, \
+ .offset = n, \
+}
+
+static const struct debugfs_reg32 davinci_pll_regs[] = {
+ DEBUG_REG(REVID),
+ DEBUG_REG(PLLCTL),
+ DEBUG_REG(OCSEL),
+ DEBUG_REG(PLLSECCTL),
+ DEBUG_REG(PLLM),
+ DEBUG_REG(PREDIV),
+ DEBUG_REG(PLLDIV1),
+ DEBUG_REG(PLLDIV2),
+ DEBUG_REG(PLLDIV3),
+ DEBUG_REG(OSCDIV),
+ DEBUG_REG(POSTDIV),
+ DEBUG_REG(BPDIV),
+ DEBUG_REG(PLLCMD),
+ DEBUG_REG(PLLSTAT),
+ DEBUG_REG(ALNCTL),
+ DEBUG_REG(DCHANGE),
+ DEBUG_REG(CKEN),
+ DEBUG_REG(CKSTAT),
+ DEBUG_REG(SYSTAT),
+ DEBUG_REG(PLLDIV4),
+ DEBUG_REG(PLLDIV5),
+ DEBUG_REG(PLLDIV6),
+ DEBUG_REG(PLLDIV7),
+ DEBUG_REG(PLLDIV8),
+ DEBUG_REG(PLLDIV9),
+};
+
+static int davinci_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+ struct davinci_pll_clk *pll = to_davinci_pll_clk(hw);
+ struct debugfs_regset32 *regset;
+ struct dentry *d;
+
+ regset = kzalloc(sizeof(regset), GFP_KERNEL);
+ if (!regset)
+ return -ENOMEM;
+
+ regset->regs = davinci_pll_regs;
+ regset->nregs = ARRAY_SIZE(davinci_pll_regs);
+ regset->base = pll->base;
+
+ d = debugfs_create_regset32("registers", 0400, dentry, regset);
+ if (IS_ERR(d)) {
+ kfree(regset);
+ return PTR_ERR(d);
+ }
+
+ return 0;
+}
+#else
+#define davinci_pll_debug_init NULL
+#endif
+
+static const struct clk_ops davinci_pll_clk_ops = {
+ .recalc_rate = davinci_pll_clk_recalc,
+ .round_rate = davinci_pll_round_rate,
+ .set_rate = davinci_pll_set_rate,
+ .debug_init = davinci_pll_debug_init,
+};
+
+/**
+ * davinci_pll_clk_register - Register a PLL clock
+ * @name: The clock name
+ * @parent_name: The parent clock name
+ * @base: The PLL's memory region
+ */
+struct clk *davinci_pll_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base)
+{
+ struct clk_init_data init;
+ struct davinci_pll_clk *pll;
+ struct clk *clk;
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = name;
+ init.ops = &davinci_pll_clk_ops;
+ init.parent_names = (parent_name ? &parent_name : NULL);
+ init.num_parents = (parent_name ? 1 : 0);
+ init.flags = 0;
+
+ pll->base = base;
+ pll->hw.init = &init;
+
+ clk = clk_register(NULL, &pll->hw);
+ if (IS_ERR(clk))
+ kfree(pll);
+
+ return clk;
+}
+
+struct davinci_pll_aux_clk {
+ struct clk_hw hw;
+ struct davinci_pll_clk *pll;
+};
+
+/**
+ * davinci_pll_aux_clk_register - Register bypass clock (AUXCLK)
+ * @name: The clock name
+ * @parent_name: The parent clock name (usually "ref_clk" since this bypasses
+ * the PLL)
+ * @base: The PLL memory region
+ */
+struct clk *davinci_pll_aux_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base)
+{
+ return clk_register_gate(NULL, name, parent_name, 0, base + CKEN,
+ CKEN_AUXEN_SHIFT, 0, NULL);
+}
+
+/**
+ * davinci_pll_bpdiv_clk_register - Register bypass divider clock (SYSCLKBP)
+ * @name: The clock name
+ * @parent_name: The parent clock name (usually "ref_clk" since this bypasses
+ * the PLL)
+ * @base: The PLL memory region
+ */
+struct clk *davinci_pll_bpdiv_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base)
+{
+ return clk_register_divider(NULL, name, parent_name, 0, base + BPDIV,
+ BPDIV_RATIO_SHIFT, BPDIV_RATIO_WIDTH,
+ CLK_DIVIDER_READ_ONLY, NULL);
+}
+
+/**
+ * davinci_pll_obs_clk_register - Register oscillator divider clock (OBSCLK)
+ * @name: The clock name
+ * @parent_names: The parent clock names
+ * @num_parents: The number of paren clocks
+ * @base: The PLL memory region
+ * @table: A table of values cooresponding to the parent clocks (see OCSEL
+ * register in SRM for values)
+ */
+struct clk *davinci_pll_obs_clk_register(const char *name,
+ const char * const *parent_names,
+ u8 num_parents,
+ void __iomem *base,
+ u32 *table)
+{
+ struct clk_mux *mux;
+ struct clk_gate *gate;
+ struct clk_divider *divider;
+ struct clk *clk;
+
+ mux = kzalloc(sizeof(*mux), GFP_KERNEL);
+ if (!mux)
+ return ERR_PTR(-ENOMEM);
+
+ mux->reg = base + OCSEL;
+ mux->table = table;
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate) {
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ gate->reg = base + CKEN;
+ gate->bit_idx = CKEN_OBSCLK_SHIFT;
+
+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+ if (!divider) {
+ kfree(gate);
+ kfree(mux);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ divider->reg = base + OSCDIV;
+ divider->width = OSCDIV_RATIO_WIDTH;
+
+ clk = clk_register_composite(NULL, name, parent_names, num_parents,
+ &mux->hw, &clk_mux_ops,
+ ÷r->hw, &clk_divider_ops,
+ &gate->hw, &clk_gate_ops, 0);
+ if (IS_ERR(clk)) {
+ kfree(divider);
+ kfree(gate);
+ kfree(mux);
+ }
+
+ return clk;
+}
+
+struct clk *
+davinci_pll_divclk_register(const struct davinci_pll_divclk_info *info,
+ void __iomem *base)
+{
+ const struct clk_ops *divider_ops = &clk_divider_ops;
+ struct clk_gate *gate;
+ struct clk_divider *divider;
+ struct clk *clk;
+ u32 reg;
+ u32 flags = 0;
+
+ /* PLLDIVn registers are not entirely consecutive */
+ if (info->id < 4)
+ reg = PLLDIV1 + 4 * (info->id - 1);
+ else
+ reg = PLLDIV4 + 4 * (info->id - 4);
+
+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
+ if (!gate)
+ return ERR_PTR(-ENOMEM);
+
+ gate->reg = base + reg;
+ gate->bit_idx = PLLDIV_ENABLE_SHIFT;
+
+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
+ if (!divider) {
+ kfree(gate);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ divider->reg = base + reg;
+ divider->width = PLLDIV_RATIO_WIDTH;
+ divider->flags = 0;
+
+ if (info->flags & DIVCLK_FIXED_DIV) {
+ flags |= CLK_DIVIDER_READ_ONLY;
+ divider_ops = &clk_divider_ro_ops;
+ }
+
+ /* Only the ARM clock can change the parent PLL rate */
+ if (info->flags & DIVCLK_ARM_RATE)
+ flags |= CLK_SET_RATE_PARENT;
+
+ if (info->flags & DIVCLK_ALWAYS_ENABLED)
+ flags |= CLK_IS_CRITICAL;
+
+ clk = clk_register_composite(NULL, info->name, &info->parent_name, 1,
+ NULL, NULL, ÷r->hw, divider_ops,
+ &gate->hw, &clk_gate_ops, flags);
+ if (IS_ERR(clk)) {
+ kfree(divider);
+ kfree(gate);
+ }
+
+ return clk;
+}
+
+#ifdef CONFIG_OF
+#define MAX_NAME_SIZE 20
+
+void of_davinci_pll_init(struct device_node *node, const char *name,
+ const struct davinci_pll_divclk_info *info,
+ u8 max_divclk_id)
+{
+ struct device_node *child;
+ const char *parent_name;
+ void __iomem *base;
+ struct clk *clk;
+
+ base = of_iomap(node, 0);
+ if (!base) {
+ pr_err("%s: ioremap failed\n", __func__);
+ return;
+ }
+
+ parent_name = of_clk_get_parent_name(node, 0);
+
+ clk = davinci_pll_clk_register(name, parent_name, base);
+ if (IS_ERR(clk)) {
+ pr_err("%s: failed to register %s (%ld)\n", __func__, name,
+ PTR_ERR(clk));
+ return;
+ }
+
+ child = of_get_child_by_name(node, "sysclk");
+ if (child && of_device_is_available(child)) {
+ struct clk_onecell_data *clk_data;
+
+ clk_data = clk_alloc_onecell_data(max_divclk_id + 1);
+ if (!clk_data) {
+ pr_err("%s: out of memory\n", __func__);
+ return;
+ }
+
+ for (; info->name; info++) {
+ clk = davinci_pll_divclk_register(info, base);
+ if (IS_ERR(clk))
+ pr_warn("%s: failed to register %s (%ld)\n",
+ __func__, info->name, PTR_ERR(clk));
+ else
+ clk_data->clks[info->id] = clk;
+ }
+ of_clk_add_provider(child, of_clk_src_onecell_get, clk_data);
+ }
+ of_node_put(child);
+
+ child = of_get_child_by_name(node, "auxclk");
+ if (child && of_device_is_available(child)) {
+ char child_name[MAX_NAME_SIZE];
+
+ snprintf(child_name, MAX_NAME_SIZE, "%s_aux_clk", name);
+
+ clk = davinci_pll_aux_clk_register(child_name, parent_name, base);
+ if (IS_ERR(clk))
+ pr_warn("%s: failed to register %s (%ld)\n", __func__,
+ child_name, PTR_ERR(clk));
+ else
+ of_clk_add_provider(child, of_clk_src_simple_get, clk);
+ }
+ of_node_put(child);
+}
+#endif
diff --git a/drivers/clk/davinci/pll.h b/drivers/clk/davinci/pll.h
new file mode 100644
index 0000000..259678b
--- /dev/null
+++ b/drivers/clk/davinci/pll.h
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Clock driver for TI Davinci PSC controllers
+ *
+ * Copyright (C) 2017 David Lechner <david@lechnology.com>
+ */
+
+#ifndef __CLK_DAVINCI_PLL_H___
+#define __CLK_DAVINCI_PLL_H___
+
+#include <linux/bitops.h>
+#include <linux/types.h>
+
+#define DIVCLK_ARM_RATE BIT(0) /* Controls ARM rate */
+#define DIVCLK_FIXED_DIV BIT(1) /* Fixed divider */
+#define DIVCLK_ALWAYS_ENABLED BIT(2) /* Or bad things happen */
+
+struct davinci_pll_divclk_info {
+ const char *name;
+ const char *parent_name;
+ u32 id;
+ u32 flags;
+};
+
+#define DIVCLK(i, n, p, f) \
+{ \
+ .name = #n, \
+ .parent_name = #p, \
+ .id = (i), \
+ .flags = (f), \
+}
+
+struct clk;
+
+struct clk *davinci_pll_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base);
+struct clk *davinci_pll_aux_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base);
+struct clk *davinci_pll_bpdiv_clk_register(const char *name,
+ const char *parent_name,
+ void __iomem *base);
+struct clk *davinci_pll_obs_clk_register(const char *name,
+ const char * const *parent_names,
+ u8 num_parents,
+ void __iomem *base,
+ u32 *table);
+struct clk *
+davinci_pll_divclk_register(const struct davinci_pll_divclk_info *info,
+ void __iomem *base);
+
+#ifdef CONFIG_OF
+struct device_node;
+
+void of_davinci_pll_init(struct device_node *node, const char *name,
+ const struct davinci_pll_divclk_info *info,
+ u8 max_divclk_id);
+#endif
+
+#endif /* __CLK_DAVINCI_PLL_H___ */
--
2.7.4
^ permalink raw reply related
* [PATCH v5 01/44] dt-bindings: clock: Add new bindings for TI Davinci PLL clocks
From: David Lechner @ 2018-01-08 2:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377863-20358-1-git-send-email-david@lechnology.com>
This adds a new binding for the PLL IP blocks in the mach-davinci family
of processors. Currently, only the SYSCLKn and AUXCLK outputs are needed,
but in the future additional child nodes could be added for OBSCLK and
BPDIV.
Note: Although these PLL controllers are very similar to the TI Keystone
SoCs, we are not re-using those bindings. The Keystone bindings use a
legacy one-node-per-clock binding. Furthermore, the mach-davinici SoCs
have a slightly different PLL register layout and a number of quirks that
can't be handled by the existing bindings, so the keystone bindings could
not be used as-is anyway.
Signed-off-by: David Lechner <david@lechnology.com>
---
.../devicetree/bindings/clock/ti/davinci/pll.txt | 47 ++++++++++++++++++++++
1 file changed, 47 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
diff --git a/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
new file mode 100644
index 0000000..99bf5da
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
@@ -0,0 +1,47 @@
+Binding for TI DaVinci PLL Controllers
+
+The PLL provides clocks to most of the components on the SoC. In addition
+to the PLL itself, this controller also contains bypasses, gates, dividers,
+an multiplexers for various clock signals.
+
+Required properties:
+- compatible: shall be one of:
+ - "ti,da850-pll0" for PLL0 on DA850/OMAP-L138/AM18XX
+ - "ti,da850-pll1" for PLL1 on DA850/OMAP-L138/AM18XX
+- reg: physical base address and size of the controller's register area.
+- clocks: phandle to the PLL input clock source
+
+Optional child nodes:
+
+sysclk
+ Describes the PLLDIVn divider clocks that provide the SYSCLKn clock
+ domains. The node name must be "sysclk". Consumers of this node should
+ use "n" in "SYSCLKn" as the parameter for the clock cell.
+
+ Required properties:
+ - #clock-cells: must be 1
+
+auxclk
+ Describes the AUXCLK output of the PLL. The node name must be "auxclk".
+
+ Required properties:
+ - #clock-cells: must be 0
+
+Examples:
+
+ pll0: clock-controller at 11000 {
+ compatible = "ti,da850-pll0";
+ reg = <0x11000 0x1000>;
+ clocks = <&ref_clk>;
+
+ pll0_sysclk: sysclk {
+ #clock-cells = <1>;
+ };
+
+ pll0_aux_clk: auxclk {
+ #clock-cells = <0>;
+ };
+ };
+
+Also see:
+- Documentation/devicetree/bindings/clock/clock-bindings.txt
--
2.7.4
^ permalink raw reply related
* [PATCH v5 00/44] ARM: davinci: convert to common clock framework
From: David Lechner @ 2018-01-08 2:16 UTC (permalink / raw)
To: linux-arm-kernel
This series converts mach-davinci to use the common clock framework.
The series works like this, the first 21 patches create new clock drivers
using the common clock framework. There are basically 3 groups of clocks -
PLL, PSC and CFGCHIP (syscon). There are six different SoCs that each have
unique init data, which is the reason for so many patches.
Then, starting with "ARM: davinci: move davinci_clk_init() to init_time",
we get the mach code ready for the switch by adding the code needed for
the new clock drivers and adding #ifndef CONFIG_COMMON_CLK around the
legacy clocks so that we can switch easily between the old and the new.
"ARM: davinci: switch to common clock framework" actually flips the switch
to start using the new clock drivers. Then the next 8 patches remove all
of the old clock code.
The final three patches add device tree support to the one SoC that
supports it.
v5 changes:
- Basically, this is an entirely new series
- Patches are broken up into bite-sized pieces
- Converted PSC clock driver to use regmap
- Restored "force" flag for certain DA850 clocks
- Added device tree bindings
- Moved more of the clock init to drivers/clk
- Fixed frequency scaling (maybe*)
* I have frequency scaling using cpufreq-dt, so I know the clocks are doing
what they need to do to make this work, but I haven't figured out how to
test davinci-cpufreq driver yet. (Patches to make cpufreq-dt work will be
sent separately after this series has landed.)
Dependencies:
This series applies on top of linux-davinci/master plus the following patches:
- [1] clk: fix reentrancy of clk_enable() on UP systems
- [2] clk: add helper functions for managing clk_onecell_data
- [3] clk: divider: fix clk_round_rate() when CLK_DIVIDER_READ_ONLY &&
CLK_RATE_SET_PARENT
- [4] watchdog: davinci_wdt: add restart function
- [5] ARM: davinci: remove watchdog reset
- [6] USB: musb: da8xx: remove clock con_id
- [7] USB: ohci: da8xx: remove clk con_id
- [8] ARM: da8xx: remove con_id from USB clocks
You can find a working branch with everything included in the "common-clk-v5"
branch of https://github.com/dlech/ev3dev-kernel.git.
[1]: https://patchwork.kernel.org/patch/10145933/
[2]: https://patchwork.kernel.org/patch/10145873/
[3]: https://patchwork.kernel.org/patch/10147983/
[4]: https://patchwork.kernel.org/patch/10148097/
[5]: https://patchwork.kernel.org/patch/10148099/
[6]: https://patchwork.kernel.org/patch/10148111/
[7]: https://patchwork.kernel.org/patch/10148107/
[8]: https://patchwork.kernel.org/patch/10148109/
Testing/debugging for the uninitiated:
I only have one device to test with, which is based on da850, so I will
have to rely on others to do some testing here. Since we are dealing with
clocks, if something isn't working, you most likely won't see output on
the serial port. To figure out what is going on, you need to enable...
CONFIG_DEBUG_LL=y
CONFIG_EARLY_PRINTK=y
and add "earlyprintk clk_ignore_unused" to the kernel command line options.
You may need to select a different UART for this depending on your board. I
think UART1 is the default in the kernel configuration.
On da850 devices comment out the lines:
else
clk_set_parent(clk, parent->clk);
in da850.c or, if using device tree, comment out the lines:
assigned-clocks = <&async3_clk>;
assigned-clock-parents = <&pll1_sysclk 2>;
in da850.dtsi when doing earlyprintk, otherwise the UART1 and UART2 clock
source will change during boot and cause garbled output after a point.
David Lechner (44):
dt-bindings: clock: Add new bindings for TI Davinci PLL clocks
clk: davinci: New driver for davinci PLL clocks
clk: davinci: Add platform information for TI DA830 PLL
clk: davinci: Add platform information for TI DA850 PLL
clk: davinci: Add platform information for TI DM355 PLL
clk: davinci: Add platform information for TI DM365 PLL
clk: davinci: Add platform information for TI DM644x PLL
clk: davinci: Add platform information for TI DM646x PLL
dt-bindings: clock: New bindings for TI Davinci PSC
clk: davinci: New driver for davinci PSC clocks
clk: davinci: Add platform information for TI DA830 PSC
clk: davinci: Add platform information for TI DA850 PSC
clk: davinci: Add platform information for TI DM355 PSC
clk: davinci: Add platform information for TI DM365 PSC
clk: davinci: Add platform information for TI DM644x PSC
clk: davinci: Add platform information for TI DM646x PSC
dt-bindings: clock: Add bindings for DA8XX CFGCHIP gate clocks
dt-bindings: clock: Add binding for TI DA8XX CFGCHIP mux clocks
clk: davinci: New driver for TI DA8XX CFGCHIP clocks
dt-bindings: clock: Add bindings for TI DA8XX USB PHY clocks
clk: davinci: New driver for TI DA8XX USB PHY clocks
ARM: davinci: move davinci_clk_init() to init_time
ARM: da830: add new clock init using common clock framework
ARM: da850: add new clock init using common clock framework
ARM: dm355: add new clock init using common clock framework
ARM: dm365: add new clock init using common clock framework
ARM: dm644x: add new clock init using common clock framework
ARM: dm646x: add new clock init using common clock framework
ARM: da8xx: add new USB PHY clock init using common clock framework
ARM: da8xx: add new sata_refclk init using common clock frmework
ARM: davinci: remove CONFIG_DAVINCI_RESET_CLOCKS
ARM: davinci_all_defconfig: remove CONFIG_DAVINCI_RESET_CLOCKS
ARM: davinci: switch to common clock framework
ARM: da830: Remove legacy clock init
ARM: da850: Remove legacy clock init
ARM: dm355: Remove legacy clock init
ARM: dm365: Remove legacy clock init
ARM: dm644x: Remove legacy clock init
ARM: dm646x: Remove legacy clock init
ARM: da8xx: Remove legacy clock init
ARM: davinci: remove legacy clocks
ARM: davinci: add device tree support to timer
ARM: da8xx-dt: switch to device tree clocks
ARM: dts: da850: Add clocks
.../clock/ti/davinci/da8xx-cfgchip-gate.txt | 38 ++
.../clock/ti/davinci/da8xx-cfgchip-mux.txt | 42 ++
.../clock/ti/davinci/da8xx-cfgchip-usb-phy.txt | 55 ++
.../devicetree/bindings/clock/ti/davinci/pll.txt | 47 ++
.../devicetree/bindings/clock/ti/davinci/psc.txt | 47 ++
MAINTAINERS | 6 +
arch/arm/Kconfig | 2 +-
arch/arm/boot/dts/da850.dtsi | 167 +++++
arch/arm/configs/davinci_all_defconfig | 1 -
arch/arm/mach-davinci/Kconfig | 13 +-
arch/arm/mach-davinci/Makefile | 2 +-
arch/arm/mach-davinci/board-da830-evm.c | 2 +-
arch/arm/mach-davinci/board-da850-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-evm.c | 2 +-
arch/arm/mach-davinci/board-dm355-leopard.c | 2 +-
arch/arm/mach-davinci/board-dm365-evm.c | 2 +-
arch/arm/mach-davinci/board-dm644x-evm.c | 2 +-
arch/arm/mach-davinci/board-dm646x-evm.c | 19 +-
arch/arm/mach-davinci/board-mityomapl138.c | 2 +-
arch/arm/mach-davinci/board-neuros-osd2.c | 2 +-
arch/arm/mach-davinci/board-omapl138-hawk.c | 2 +-
arch/arm/mach-davinci/board-sffsdr.c | 2 +-
arch/arm/mach-davinci/clock.c | 745 ---------------------
arch/arm/mach-davinci/clock.h | 76 ---
arch/arm/mach-davinci/common.c | 3 -
arch/arm/mach-davinci/da830.c | 438 +-----------
arch/arm/mach-davinci/da850.c | 689 ++-----------------
arch/arm/mach-davinci/da8xx-dt.c | 61 +-
arch/arm/mach-davinci/davinci.h | 8 +
arch/arm/mach-davinci/devices-da8xx.c | 43 +-
arch/arm/mach-davinci/devices.c | 1 -
arch/arm/mach-davinci/dm355.c | 390 +----------
arch/arm/mach-davinci/dm365.c | 476 +------------
arch/arm/mach-davinci/dm644x.c | 322 +--------
arch/arm/mach-davinci/dm646x.c | 362 +---------
arch/arm/mach-davinci/include/mach/clock.h | 3 -
arch/arm/mach-davinci/include/mach/common.h | 9 -
arch/arm/mach-davinci/include/mach/da8xx.h | 3 +
arch/arm/mach-davinci/psc.c | 137 ----
arch/arm/mach-davinci/psc.h | 12 -
arch/arm/mach-davinci/time.c | 19 +-
arch/arm/mach-davinci/usb-da8xx.c | 262 ++------
drivers/clk/Makefile | 1 +
drivers/clk/davinci/Makefile | 22 +
drivers/clk/davinci/da8xx-cfgchip.c | 203 ++++++
drivers/clk/davinci/da8xx-usb-phy-clk.c | 425 ++++++++++++
drivers/clk/davinci/pll-da830.c | 38 ++
drivers/clk/davinci/pll-da850.c | 67 ++
drivers/clk/davinci/pll-dm355.c | 40 ++
drivers/clk/davinci/pll-dm365.c | 64 ++
drivers/clk/davinci/pll-dm644x.c | 41 ++
drivers/clk/davinci/pll-dm646x.c | 44 ++
drivers/clk/davinci/pll.c | 564 ++++++++++++++++
drivers/clk/davinci/pll.h | 61 ++
drivers/clk/davinci/psc-da830.c | 96 +++
drivers/clk/davinci/psc-da850.c | 117 ++++
drivers/clk/davinci/psc-dm355.c | 78 +++
drivers/clk/davinci/psc-dm365.c | 83 +++
drivers/clk/davinci/psc-dm644x.c | 73 ++
drivers/clk/davinci/psc-dm646x.c | 68 ++
drivers/clk/davinci/psc.c | 282 ++++++++
drivers/clk/davinci/psc.h | 49 ++
include/linux/clk/davinci.h | 39 ++
63 files changed, 3172 insertions(+), 3801 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-gate.txt
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-mux.txt
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/da8xx-cfgchip-usb-phy.txt
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/pll.txt
create mode 100644 Documentation/devicetree/bindings/clock/ti/davinci/psc.txt
delete mode 100644 arch/arm/mach-davinci/clock.c
delete mode 100644 arch/arm/mach-davinci/psc.c
create mode 100644 drivers/clk/davinci/Makefile
create mode 100644 drivers/clk/davinci/da8xx-cfgchip.c
create mode 100644 drivers/clk/davinci/da8xx-usb-phy-clk.c
create mode 100644 drivers/clk/davinci/pll-da830.c
create mode 100644 drivers/clk/davinci/pll-da850.c
create mode 100644 drivers/clk/davinci/pll-dm355.c
create mode 100644 drivers/clk/davinci/pll-dm365.c
create mode 100644 drivers/clk/davinci/pll-dm644x.c
create mode 100644 drivers/clk/davinci/pll-dm646x.c
create mode 100644 drivers/clk/davinci/pll.c
create mode 100644 drivers/clk/davinci/pll.h
create mode 100644 drivers/clk/davinci/psc-da830.c
create mode 100644 drivers/clk/davinci/psc-da850.c
create mode 100644 drivers/clk/davinci/psc-dm355.c
create mode 100644 drivers/clk/davinci/psc-dm365.c
create mode 100644 drivers/clk/davinci/psc-dm644x.c
create mode 100644 drivers/clk/davinci/psc-dm646x.c
create mode 100644 drivers/clk/davinci/psc.c
create mode 100644 drivers/clk/davinci/psc.h
create mode 100644 include/linux/clk/davinci.h
--
2.7.4
^ permalink raw reply
* [PATCH -next] ASoC: mediatek: mt2701: fix return value check in mt2701_afe_pcm_dev_probe()
From: Wei Yongjun @ 2018-01-08 2:15 UTC (permalink / raw)
To: linux-arm-kernel
In case of error, the function syscon_node_to_regmap() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check should
be replaced with IS_ERR().
Fixes: dfa3cbb83e09 ("ASoC: mediatek: modify MT2701 AFE driver to adapt mfd device")
Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
---
sound/soc/mediatek/mt2701/mt2701-afe-pcm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
index f0cd08f..5bc4e00 100644
--- a/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
+++ b/sound/soc/mediatek/mt2701/mt2701-afe-pcm.c
@@ -1440,9 +1440,9 @@ static int mt2701_afe_pcm_dev_probe(struct platform_device *pdev)
}
afe->regmap = syscon_node_to_regmap(dev->parent->of_node);
- if (!afe->regmap) {
+ if (IS_ERR(afe->regmap)) {
dev_err(dev, "could not get regmap from parent\n");
- return -ENODEV;
+ return PTR_ERR(afe->regmap);
}
mutex_init(&afe->irq_alloc_lock);
^ permalink raw reply related
* [PATCH 00/13] replace print_symbol() with printk()-s
From: Sergey Senozhatsky @ 2018-01-08 2:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180105144239.i3pc6npgmoi4ddln@pathway.suse.cz>
On (01/05/18 15:42), Petr Mladek wrote:
>
> I am all for it. But I would postpone this removal to 4.17.
> The reason is rather ugly. 13th patch is already in arc tree.
> We would need to shuffle the patch or coordinate pull requests.
JFI, the patch is in Linus's tree as of now (d0729bc6bee797fb).
-ss
^ permalink raw reply
* [PATCH V3 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul
From: Anson Huang @ 2018-01-08 2:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515377091-10422-1-git-send-email-Anson.Huang@nxp.com>
Add 696MHz operating point for i.MX6UL, only for those
parts with speed grading fuse set to 2b'10 supports
696MHz operating point, so, speed grading check is also
added for i.MX6UL in this patch, the clock tree for each
operating point are as below:
696MHz:
pll1 696000000
pll1_bypass 696000000
pll1_sys 696000000
pll1_sw 696000000
arm 696000000
528MHz:
pll2 528000000
pll2_bypass 528000000
pll2_bus 528000000
ca7_secondary_sel 528000000
step 528000000
pll1_sw 528000000
arm 528000000
396MHz:
pll2_pfd2_396m 396000000
ca7_secondary_sel 396000000
step 396000000
pll1_sw 396000000
arm 396000000
198MHz:
pll2_pfd2_396m 396000000
ca7_secondary_sel 396000000
step 396000000
pll1_sw 396000000
arm 198000000
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
changes since v2:
add reviewed-by.
drivers/cpufreq/imx6q-cpufreq.c | 46 ++++++++++++++++++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 8bfb077..741f22e 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -136,6 +136,10 @@ static int imx6q_set_target(struct cpufreq_policy *policy, unsigned int index)
clks[PLL2_PFD2_396M].clk);
clk_set_parent(clks[STEP].clk, clks[SECONDARY_SEL].clk);
clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
+ if (freq_hz > clk_get_rate(clks[PLL2_BUS].clk)) {
+ clk_set_rate(clks[PLL1_SYS].clk, new_freq * 1000);
+ clk_set_parent(clks[PLL1_SW].clk, clks[PLL1_SYS].clk);
+ }
} else {
clk_set_parent(clks[STEP].clk, clks[PLL2_PFD2_396M].clk);
clk_set_parent(clks[PLL1_SW].clk, clks[STEP].clk);
@@ -260,6 +264,43 @@ static void imx6q_opp_check_speed_grading(struct device *dev)
of_node_put(np);
}
+#define OCOTP_CFG3_6UL_SPEED_696MHZ 0x2
+
+static void imx6ul_opp_check_speed_grading(struct device *dev)
+{
+ struct device_node *np;
+ void __iomem *base;
+ u32 val;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx6ul-ocotp");
+ if (!np)
+ return;
+
+ base = of_iomap(np, 0);
+ if (!base) {
+ dev_err(dev, "failed to map ocotp\n");
+ goto put_node;
+ }
+
+ /*
+ * Speed GRADING[1:0] defines the max speed of ARM:
+ * 2b'00: Reserved;
+ * 2b'01: 528000000Hz;
+ * 2b'10: 696000000Hz;
+ * 2b'11: Reserved;
+ * We need to set the max speed of ARM according to fuse map.
+ */
+ val = readl_relaxed(base + OCOTP_CFG3);
+ val >>= OCOTP_CFG3_SPEED_SHIFT;
+ val &= 0x3;
+ if (val != OCOTP_CFG3_6UL_SPEED_696MHZ)
+ if (dev_pm_opp_disable(dev, 696000000))
+ dev_warn(dev, "failed to disable 696MHz OPP\n");
+ iounmap(base);
+put_node:
+ of_node_put(np);
+}
+
static int imx6q_cpufreq_probe(struct platform_device *pdev)
{
struct device_node *np;
@@ -314,7 +355,10 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
goto put_reg;
}
- imx6q_opp_check_speed_grading(cpu_dev);
+ if (of_machine_is_compatible("fsl,imx6ul"))
+ imx6ul_opp_check_speed_grading(cpu_dev);
+ else
+ imx6q_opp_check_speed_grading(cpu_dev);
/* Because we have added the OPPs here, we must free them */
free_opp = true;
--
1.9.1
^ permalink raw reply related
* [PATCH V3 1/2] ARM: dts: imx6ul: add 696MHz operating point
From: Anson Huang @ 2018-01-08 2:04 UTC (permalink / raw)
To: linux-arm-kernel
Add 696MHz operating point according to datasheet
(Rev. 0, 12/2015).
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
---
changes since v2:
add reviewed-by.
arch/arm/boot/dts/imx6ul.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index d5181f8..963e169 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -68,12 +68,14 @@
clock-latency = <61036>; /* two CLK32 periods */
operating-points = <
/* kHz uV */
+ 696000 1275000
528000 1175000
396000 1025000
198000 950000
>;
fsl,soc-operating-points = <
/* KHz uV */
+ 696000 1275000
528000 1175000
396000 1175000
198000 1175000
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for i.mx6ul
From: Anson Huang @ 2018-01-08 1:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <2009633.KF2URkV5n1@aspire.rjw.lan>
Best Regards!
Anson Huang
> -----Original Message-----
> From: Rafael J. Wysocki [mailto:rjw at rjwysocki.net]
> Sent: 2018-01-08 7:34 AM
> To: Anson Huang <anson.huang@nxp.com>
> Cc: Rafael J. Wysocki <rafael@kernel.org>; linux-arm-
> kernel at lists.infradead.org; devicetree at vger.kernel.org; Linux PM <linux-
> pm at vger.kernel.org>; Linux Kernel Mailing List <linux-
> kernel at vger.kernel.org>; Shawn Guo <shawnguo@kernel.org>; Sascha Hauer
> <kernel@pengutronix.de>; Fabio Estevam <fabio.estevam@nxp.com>; Rob
> Herring <robh+dt@kernel.org>; Mark Rutland <mark.rutland@arm.com>;
> Russell King - ARM Linux <linux@armlinux.org.uk>; Viresh Kumar
> <viresh.kumar@linaro.org>; Jacky Bai <ping.bai@nxp.com>; A.s. Dong
> <aisheng.dong@nxp.com>
> Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point for
> i.mx6ul
>
> On Saturday, January 6, 2018 4:05:41 AM CET Anson Huang wrote:
> > Hi, Rafael
> >
> > Best Regards!
> > Anson Huang
> >
> >
> > > -----Original Message-----
> > > From: rjwysocki at gmail.com [mailto:rjwysocki at gmail.com] On Behalf Of
> > > Rafael J. Wysocki
> > > Sent: 2018-01-05 8:21 PM
> > > To: Anson Huang <anson.huang@nxp.com>
> > > Cc: linux-arm-kernel at lists.infradead.org;
> > > devicetree at vger.kernel.org; Linux PM <linux-pm@vger.kernel.org>;
> > > Linux Kernel Mailing List <linux- kernel@vger.kernel.org>; Shawn Guo
> > > <shawnguo@kernel.org>; Sascha Hauer <kernel@pengutronix.de>; Fabio
> > > Estevam <fabio.estevam@nxp.com>; Rob Herring <robh+dt@kernel.org>;
> > > Mark Rutland <mark.rutland@arm.com>; Russell King - ARM Linux
> > > <linux@armlinux.org.uk>; Rafael J. Wysocki <rjw@rjwysocki.net>;
> > > Viresh Kumar <viresh.kumar@linaro.org>; Jacky Bai
> > > <ping.bai@nxp.com>; A.s. Dong <aisheng.dong@nxp.com>
> > > Subject: Re: [PATCH 2/2] cpufreq: imx6q: add 696MHz operating point
> > > for i.mx6ul
> > >
> > > On Tue, Jan 2, 2018 at 6:07 PM, Anson Huang <Anson.Huang@nxp.com>
> wrote:
> > > > Add 696MHz operating point for i.MX6UL, only for those parts with
> > > > speed grading fuse set to 2b'10 supports 696MHz operating point,
> > > > so, speed grading check is also added for i.MX6UL in this patch,
> > > > the clock tree for each operating point are as below:
> > > >
> > > > 696MHz:
> > > > pll1 696000000
> > > > pll1_bypass 696000000
> > > > pll1_sys 696000000
> > > > pll1_sw 696000000
> > > > arm 696000000
> > > > 528MHz:
> > > > pll2 528000000
> > > > pll2_bypass 528000000
> > > > pll2_bus 528000000
> > > > ca7_secondary_sel 528000000
> > > > step 528000000
> > > > pll1_sw 528000000
> > > > arm 528000000
> > > > 396MHz:
> > > > pll2_pfd2_396m 396000000
> > > > ca7_secondary_sel 396000000
> > > > step 396000000
> > > > pll1_sw 396000000
> > > > arm 396000000
> > > > 198MHz:
> > > > pll2_pfd2_396m 396000000
> > > > ca7_secondary_sel 396000000
> > > > step 396000000
> > > > pll1_sw 396000000
> > > > arm 198000000
> > > >
> > > > Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
> > >
> > > This doesn't apply for me and in a nontrivial way.
> > >
> > > What kernel is it against?
> >
> > I did it based on linux-next, it should be on linux-next-pm branch, I
> > redo the patch set V2 based on linux-next-pm, also redo the test,
> > sorry for the inconvenience.
>
> But you didn't add the Reviewed-by: tags from Fabio to them.
>
> Was that on purpose or by mistake?
>
> Thanks,
> Rafael
It was my mistake, I thought it will be added by maintainer, I will add them and set a V3
patch set. Thanks.
Anson.
^ permalink raw reply
* 答复: [PATCH v7 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
From: liwei (CM) @ 2018-01-08 1:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <127f93dd-29c8-8cfc-9b02-5dc72609a272@linaro.org>
Hi. Zhangfei
Thank you, I will add it in the next patch.
-----????-----
???: zhangfei [mailto:zhangfei.gao at linaro.org]
????: 2018?1?8? 9:40
???: liwei (CM); robh+dt at kernel.org; mark.rutland at arm.com; xuwei (O); catalin.marinas at arm.com; will.deacon at arm.com; vinholikatti at gmail.com; jejb at linux.vnet.ibm.com; martin.petersen at oracle.com; khilman at baylibre.com; arnd at arndb.de; gregory.clement at free-electrons.com; thomas.petazzoni at free-electrons.com; yamada.masahiro at socionext.com; riku.voipio at linaro.org; treding at nvidia.com; krzk at kernel.org; eric at anholt.net; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux-scsi at vger.kernel.org
??: zangleigang; Gengjianfeng; guodong.xu at linaro.org; Fengbaopeng (kevin, Kirin Solution Dept)
??: Re: [PATCH v7 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
Hi, Wei
On 2018?01?06? 17:51, Li Wei wrote:
> This patchset adds driver support for UFS for Hi3660 SoC. It is verified on HiKey960 board.
Usually here should list the change compared with the last change set, to make it easier to reviewer, who may pay more attention to the differences.
For example
v7:xxx //change since v6
v6:xxx // change since v5
> Li Wei (5):
> scsi: ufs: add Hisilicon ufs driver code
> dt-bindings: scsi: ufs: add document for hisi-ufs
> arm64: dts: add ufs dts node
> arm64: defconfig: enable configs for Hisilicon ufs
> arm64: defconfig: enable f2fs and squashfs
>
> Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 43 ++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 +
> arch/arm64/configs/defconfig | 11 +
> drivers/scsi/ufs/Kconfig | 9 +
> drivers/scsi/ufs/Makefile | 1 +
> drivers/scsi/ufs/ufs-hisi.c | 621 +++++++++++++++++++++
> drivers/scsi/ufs/ufs-hisi.h | 116 ++++
> 7 files changed, 821 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
> create mode 100644 drivers/scsi/ufs/ufs-hisi.c
> create mode 100644 drivers/scsi/ufs/ufs-hisi.h
>
^ permalink raw reply
* [PATCH v7 0/5] scsi: ufs: add ufs driver code for Hisilicon Hi3660 SoC
From: zhangfei @ 2018-01-08 1:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180106095117.67907-1-liwei213@huawei.com>
Hi, Wei
On 2018?01?06? 17:51, Li Wei wrote:
> This patchset adds driver support for UFS for Hi3660 SoC. It is verified on HiKey960 board.
Usually here should list the change compared with the last change set,
to make it easier
to reviewer, who may pay more attention to the differences.
For example
v7:xxx //change since v6
v6:xxx // change since v5
> Li Wei (5):
> scsi: ufs: add Hisilicon ufs driver code
> dt-bindings: scsi: ufs: add document for hisi-ufs
> arm64: dts: add ufs dts node
> arm64: defconfig: enable configs for Hisilicon ufs
> arm64: defconfig: enable f2fs and squashfs
>
> Documentation/devicetree/bindings/ufs/ufs-hisi.txt | 43 ++
> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 20 +
> arch/arm64/configs/defconfig | 11 +
> drivers/scsi/ufs/Kconfig | 9 +
> drivers/scsi/ufs/Makefile | 1 +
> drivers/scsi/ufs/ufs-hisi.c | 621 +++++++++++++++++++++
> drivers/scsi/ufs/ufs-hisi.h | 116 ++++
> 7 files changed, 821 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ufs/ufs-hisi.txt
> create mode 100644 drivers/scsi/ufs/ufs-hisi.c
> create mode 100644 drivers/scsi/ufs/ufs-hisi.h
>
^ permalink raw reply
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