* [PATCH v1 06/16] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table
From: Suzuki K Poulose @ 2018-01-09 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109190414.4017-1-suzuki.poulose@arm.com>
So far we have only supported 3 level page table with fixed IPA of 40bits.
Fix stage2_flush_memslot() to accommodate for 4 level tables.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
virt/kvm/arm/mmu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 761787befd3b..e6548c85c495 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -375,7 +375,8 @@ static void stage2_flush_memslot(struct kvm *kvm,
pgd = kvm->arch.pgd + stage2_pgd_index(addr);
do {
next = stage2_pgd_addr_end(addr, end);
- stage2_flush_puds(kvm, pgd, addr, next);
+ if (!stage2_pgd_none(*pgd))
+ stage2_flush_puds(kvm, pgd, addr, next);
} while (pgd++, addr = next, addr != end);
}
--
2.13.6
^ permalink raw reply related
* [PATCH v1 05/16] arm64: Helper for parange to PASize
From: Suzuki K Poulose @ 2018-01-09 19:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109190414.4017-1-suzuki.poulose@arm.com>
Add a helper to convert ID_AA64MMFR0_EL1:PARange to they physical
size shift. Limit the size to the maximum supported by the kernel.
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/cpufeature.h | 16 ++++++++++++++++
arch/arm64/kvm/hyp/s2-setup.c | 28 +++++-----------------------
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index ac67cfc2585a..0564e14616eb 100644
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -304,6 +304,22 @@ static inline u64 read_zcr_features(void)
return zcr;
}
+static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
+{
+ switch (parange) {
+ case 0: return 32;
+ case 1: return 36;
+ case 2: return 40;
+ case 3: return 42;
+ case 4: return 44;
+
+ default:
+ case 5: return 48;
+#ifdef CONFIG_ARM64_PA_BITS_52
+ case 6: return 52;
+#endif
+ }
+}
#endif /* __ASSEMBLY__ */
#endif
diff --git a/arch/arm64/kvm/hyp/s2-setup.c b/arch/arm64/kvm/hyp/s2-setup.c
index 603e1ee83e89..b1129c83c531 100644
--- a/arch/arm64/kvm/hyp/s2-setup.c
+++ b/arch/arm64/kvm/hyp/s2-setup.c
@@ -19,11 +19,13 @@
#include <asm/kvm_arm.h>
#include <asm/kvm_asm.h>
#include <asm/kvm_hyp.h>
+#include <asm/cpufeature.h>
u32 __hyp_text __init_stage2_translation(void)
{
u64 val = VTCR_EL2_FLAGS;
u64 parange;
+ u32 phys_shift;
u64 tmp;
/*
@@ -37,27 +39,7 @@ u32 __hyp_text __init_stage2_translation(void)
val |= parange << 16;
/* Compute the actual PARange... */
- switch (parange) {
- case 0:
- parange = 32;
- break;
- case 1:
- parange = 36;
- break;
- case 2:
- parange = 40;
- break;
- case 3:
- parange = 42;
- break;
- case 4:
- parange = 44;
- break;
- case 5:
- default:
- parange = 48;
- break;
- }
+ phys_shift = id_aa64mmfr0_parange_to_phys_shift(parange);
/*
* ... and clamp it to 40 bits, unless we have some braindead
@@ -65,7 +47,7 @@ u32 __hyp_text __init_stage2_translation(void)
* return that value for the rest of the kernel to decide what
* to do.
*/
- val |= 64 - (parange > 40 ? 40 : parange);
+ val |= 64 - (phys_shift > 40 ? 40 : phys_shift);
/*
* Check the availability of Hardware Access Flag / Dirty Bit
@@ -86,5 +68,5 @@ u32 __hyp_text __init_stage2_translation(void)
write_sysreg(val, vtcr_el2);
- return parange;
+ return phys_shift;
}
--
2.13.6
^ permalink raw reply related
* [PATCH v1 04/16] arm64: Refactor pud_huge for reusability
From: Suzuki K Poulose @ 2018-01-09 19:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109190414.4017-1-suzuki.poulose@arm.com>
Make pud_huge reusable for stage2 tables, independent
of the stage1 levels.
Cc: Steve Capper <steve.capper@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/pgtable.h | 5 +++++
arch/arm64/mm/hugetlbpage.c | 2 +-
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index a5a5203b603d..a1c6e93a1a11 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -469,6 +469,11 @@ static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
#define __raw_pud_bad(pud) (!(pud_val((pud)) & PUD_TABLE_BIT))
#define __raw_pud_present(pud) pte_present(pud_pte((pud)))
+static inline int __raw_pud_huge(pud_t pud)
+{
+ return pud_val(pud) && !(pud_val(pud) & PUD_TABLE_BIT);
+}
+
static inline void __raw_set_pud(pud_t *pudp, pud_t pud)
{
*pudp = pud;
diff --git a/arch/arm64/mm/hugetlbpage.c b/arch/arm64/mm/hugetlbpage.c
index 6cb0fa92a651..a6bd5cc3d88b 100644
--- a/arch/arm64/mm/hugetlbpage.c
+++ b/arch/arm64/mm/hugetlbpage.c
@@ -35,7 +35,7 @@ int pmd_huge(pmd_t pmd)
int pud_huge(pud_t pud)
{
#ifndef __PAGETABLE_PMD_FOLDED
- return pud_val(pud) && !(pud_val(pud) & PUD_TABLE_BIT);
+ return __raw_pud_huge(pud);
#else
return 0;
#endif
--
2.13.6
^ permalink raw reply related
* [PATCH v1 03/16] arm64: Make page table helpers reusable
From: Suzuki K Poulose @ 2018-01-09 19:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109190414.4017-1-suzuki.poulose@arm.com>
This patch rearranges the page table level helpers so that it can
be reused for a page table with different number of levels
(e.g, stage2 page table for a VM) than the kernel page tables.
As such there is no functional change with this patch.
The page table helpers are defined to do the right thing for the
fixed page table levels set for the kernel. This patch tries to
refactor the code such that, we can have helpers for each level,
which should be used when the caller knows that the level exists
for the page table dealt with. Since the kernel defines helpers
p.d_action and __p.d_action, for consistency, we name the raw
page table action helpers __raw_p.d_action.
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Steve Capper <steve.capper@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
arch/arm64/include/asm/pgalloc.h | 32 +++++++++++++++++-----
arch/arm64/include/asm/pgtable.h | 58 +++++++++++++++++++++++++---------------
2 files changed, 63 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/include/asm/pgalloc.h b/arch/arm64/include/asm/pgalloc.h
index e9d9f1b006ef..e555b04045d0 100644
--- a/arch/arm64/include/asm/pgalloc.h
+++ b/arch/arm64/include/asm/pgalloc.h
@@ -29,6 +29,28 @@
#define PGALLOC_GFP (GFP_KERNEL | __GFP_ZERO)
#define PGD_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
+static inline void __raw_pmd_free(pmd_t *pmd)
+{
+ BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
+ free_page((unsigned long)pmd);
+}
+
+static inline void __raw_pud_free(pud_t *pud)
+{
+ BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
+ free_page((unsigned long)pud);
+}
+
+static inline void __raw_pgd_populate(pgd_t *pgdp, phys_addr_t pud, pgdval_t prot)
+{
+ __raw_set_pgd(pgdp, __pgd(__phys_to_pgd_val(pud) | prot));
+}
+
+static inline void __raw_pud_populate(pud_t *pud, phys_addr_t pmd, pudval_t prot)
+{
+ __raw_set_pud(pud, __pud(__phys_to_pud_val(pmd) | prot));
+}
+
#if CONFIG_PGTABLE_LEVELS > 2
static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
@@ -38,13 +60,12 @@ static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
{
- BUG_ON((unsigned long)pmd & (PAGE_SIZE-1));
- free_page((unsigned long)pmd);
+ __raw_pmd_free(pmd);
}
static inline void __pud_populate(pud_t *pud, phys_addr_t pmd, pudval_t prot)
{
- set_pud(pud, __pud(__phys_to_pud_val(pmd) | prot));
+ __raw_pud_populate(pud, pmd, prot);
}
static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
@@ -67,13 +88,12 @@ static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
static inline void pud_free(struct mm_struct *mm, pud_t *pud)
{
- BUG_ON((unsigned long)pud & (PAGE_SIZE-1));
- free_page((unsigned long)pud);
+ __raw_pud_free(pud);
}
static inline void __pgd_populate(pgd_t *pgdp, phys_addr_t pud, pgdval_t prot)
{
- set_pgd(pgdp, __pgd(__phys_to_pgd_val(pud) | prot));
+ __raw_pgd_populate(pgdp, pud, prot);
}
static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index bfa237e892f1..a5a5203b603d 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -464,31 +464,40 @@ static inline phys_addr_t pmd_page_paddr(pmd_t pmd)
*/
#define mk_pte(page,prot) pfn_pte(page_to_pfn(page),prot)
-#if CONFIG_PGTABLE_LEVELS > 2
-
-#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
-#define pud_none(pud) (!pud_val(pud))
-#define pud_bad(pud) (!(pud_val(pud) & PUD_TABLE_BIT))
-#define pud_present(pud) pte_present(pud_pte(pud))
+#define __raw_pud_none(pud) (!pud_val((pud)))
+#define __raw_pud_bad(pud) (!(pud_val((pud)) & PUD_TABLE_BIT))
+#define __raw_pud_present(pud) pte_present(pud_pte((pud)))
-static inline void set_pud(pud_t *pudp, pud_t pud)
+static inline void __raw_set_pud(pud_t *pudp, pud_t pud)
{
*pudp = pud;
dsb(ishst);
isb();
}
-static inline void pud_clear(pud_t *pudp)
+static inline void __raw_pud_clear(pud_t *pudp)
{
- set_pud(pudp, __pud(0));
+ __raw_set_pud(pudp, __pud(0));
}
-static inline phys_addr_t pud_page_paddr(pud_t pud)
+static inline phys_addr_t __raw_pud_page_paddr(pud_t pud)
{
return __pud_to_phys(pud);
}
+#if CONFIG_PGTABLE_LEVELS > 2
+
+#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd_val(pmd))
+
+#define pud_none(pud) __raw_pud_none((pud))
+#define pud_bad(pud) __raw_pud_bad((pud))
+#define pud_present(pud) __raw_pud_present((pud))
+
+#define set_pud(pudp, pud) __raw_set_pud((pudp), (pud))
+#define pud_clear(pudp) __raw_pud_clear((pudp))
+#define pud_page_paddr(pud) __raw_pud_page_paddr((pud))
+
/* Find an entry in the second-level page table. */
#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
@@ -517,30 +526,37 @@ static inline phys_addr_t pud_page_paddr(pud_t pud)
#endif /* CONFIG_PGTABLE_LEVELS > 2 */
-#if CONFIG_PGTABLE_LEVELS > 3
-
-#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
+#define __raw_pgd_none(pgd) (!pgd_val((pgd)))
+#define __raw_pgd_bad(pgd) (!(pgd_val((pgd)) & 2))
+#define __raw_pgd_present(pgd) (pgd_val((pgd)))
-#define pgd_none(pgd) (!pgd_val(pgd))
-#define pgd_bad(pgd) (!(pgd_val(pgd) & 2))
-#define pgd_present(pgd) (pgd_val(pgd))
-
-static inline void set_pgd(pgd_t *pgdp, pgd_t pgd)
+static inline void __raw_set_pgd(pgd_t *pgdp, pgd_t pgd)
{
*pgdp = pgd;
dsb(ishst);
}
-static inline void pgd_clear(pgd_t *pgdp)
+static inline void __raw_pgd_clear(pgd_t *pgdp)
{
- set_pgd(pgdp, __pgd(0));
+ __raw_set_pgd(pgdp, __pgd(0));
}
-static inline phys_addr_t pgd_page_paddr(pgd_t pgd)
+static inline phys_addr_t __raw_pgd_page_paddr(pgd_t pgd)
{
return __pgd_to_phys(pgd);
}
+#if CONFIG_PGTABLE_LEVELS > 3
+
+#define pud_ERROR(pud) __pud_error(__FILE__, __LINE__, pud_val(pud))
+
+#define pgd_none(pgd) __raw_pgd_none((pgd))
+#define pgd_bad(pgd) __raw_pgd_bad((pgd))
+#define pgd_present(pgd) __raw_pgd_present((pgd))
+#define set_pgd(pgdp, pgd) __raw_set_pgd((pgdp), (pgd))
+#define pgd_clear(pgdp) __raw_pgd_clear((pgdp))
+#define pgd_page_paddr(pgd) __raw_pgd_page_paddr((pgd))
+
/* Find an entry in the frst-level page table. */
#define pud_index(addr) (((addr) >> PUD_SHIFT) & (PTRS_PER_PUD - 1))
--
2.13.6
^ permalink raw reply related
* [PATCH v1 02/16] irqchip: gicv3-its: Add helpers for handling 52bit address
From: Suzuki K Poulose @ 2018-01-09 19:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109190414.4017-1-suzuki.poulose@arm.com>
Add helpers for encoding/decoding 52bit address in GICv3 ITS BASER
register. When ITS uses 64K page size, the 52bits of physical address
are encoded in BASER[47:12] as follows :
Bits[47:16] of the register => bits[47:16] of the physical address
Bits[15:12] of the register => bits[51:48] of the physical address
bits[15:0] of the physical address are 0.
Also adds a mask for CBASER address. This will be used for adding 52bit
support for VGIC ITS. More importantly ignore the upper bits if 52bit
support is not enabled.
Cc: Shanker Donthineni <shankerd@codeaurora.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/irqchip/irq-gic-v3-its.c | 2 +-
include/linux/irqchip/arm-gic-v3.h | 32 ++++++++++++++++++++++++++++++--
2 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
index 4039e64cd342..e6aa84f806f7 100644
--- a/drivers/irqchip/irq-gic-v3-its.c
+++ b/drivers/irqchip/irq-gic-v3-its.c
@@ -1615,7 +1615,7 @@ static int its_setup_baser(struct its_node *its, struct its_baser *baser,
}
/* Convert 52bit PA to 48bit field */
- baser_phys = GITS_BASER_PHYS_52_to_48(baser_phys);
+ baser_phys = GITS_BASER_ADDR64K_FROM_PHYS(baser_phys);
}
retry_baser:
diff --git a/include/linux/irqchip/arm-gic-v3.h b/include/linux/irqchip/arm-gic-v3.h
index c00c4c33e432..b880b6682fa6 100644
--- a/include/linux/irqchip/arm-gic-v3.h
+++ b/include/linux/irqchip/arm-gic-v3.h
@@ -320,6 +320,15 @@
#define GITS_IIDR_REV(r) (((r) >> GITS_IIDR_REV_SHIFT) & 0xf)
#define GITS_IIDR_PRODUCTID_SHIFT 24
+#ifdef CONFIG_ARM64_PA_BITS_52
+#define GITS_PA_HI_MASK (0xfULL)
+#define GITS_PA_SHIFT 52
+#else
+/* Do not use the bits [51-48] if we don't support 52bit */
+#define GITS_PA_HI_MASK 0
+#define GITS_PA_SHIFT 48
+#endif
+
#define GITS_CBASER_VALID (1ULL << 63)
#define GITS_CBASER_SHAREABILITY_SHIFT (10)
#define GITS_CBASER_INNER_CACHEABILITY_SHIFT (59)
@@ -343,6 +352,7 @@
#define GITS_CBASER_WaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, WaWb)
#define GITS_CBASER_RaWaWt GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWt)
#define GITS_CBASER_RaWaWb GIC_BASER_CACHEABILITY(GITS_CBASER, INNER, RaWaWb)
+#define GITS_CBASER_ADDRESS(x) ((x) & GENMASK_ULL(GITS_PA_SHIFT, 12))
#define GITS_BASER_NR_REGS 8
@@ -373,8 +383,26 @@
#define GITS_BASER_ENTRY_SIZE_SHIFT (48)
#define GITS_BASER_ENTRY_SIZE(r) ((((r) >> GITS_BASER_ENTRY_SIZE_SHIFT) & 0x1f) + 1)
#define GITS_BASER_ENTRY_SIZE_MASK GENMASK_ULL(52, 48)
-#define GITS_BASER_PHYS_52_to_48(phys) \
- (((phys) & GENMASK_ULL(47, 16)) | (((phys) >> 48) & 0xf) << 12)
+
+/*
+ * With 64K page size, the physical address can be upto 52bit and
+ * uses the following encoding in the GITS_BASER[47:12]:
+ *
+ * Bits[47:16] of the register => bits[47:16] of the base physical address.
+ * Bits[15:12] of the register => bits[51:48] of the base physical address.
+ * bits[15:0] of the base physical address are 0.
+ * Clear the upper bits if the kernel doesn't support 52bits.
+ */
+#define GITS_BASER_ADDR64K_LO_MASK GENMASK_ULL(47, 16)
+#define GITS_BASER_ADDR64K_HI_SHIFT 12
+#define GITS_BASER_ADDR64K_HI_MOVE (48 - GITS_BASER_ADDR64K_HI_SHIFT)
+#define GITS_BASER_ADDR64K_HI_MASK (GITS_PA_HI_MASK << GITS_BASER_ADDR64K_HI_SHIFT)
+#define GITS_BASER_ADDR64K_TO_PHYS(x) \
+ (((x) & GITS_BASER_ADDR64K_LO_MASK) | \
+ (((x) & GITS_BASER_ADDR64K_HI_MASK) << GITS_BASER_ADDR64K_HI_MOVE))
+#define GITS_BASER_ADDR64K_FROM_PHYS(p) \
+ (((p) & GITS_BASER_ADDR64K_LO_MASK) | \
+ (((p) >> GITS_BASER_ADDR64K_HI_MOVE) & GITS_BASER_ADDR64K_HI_MASK))
#define GITS_BASER_SHAREABILITY_SHIFT (10)
#define GITS_BASER_InnerShareable \
GIC_BASER_SHAREABILITY(GITS_BASER, InnerShareable)
--
2.13.6
^ permalink raw reply related
* [PATCH v1 01/16] virtio: Validate queue pfn for 32bit transports
From: Suzuki K Poulose @ 2018-01-09 19:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109190414.4017-1-suzuki.poulose@arm.com>
virtio-mmio using virtio-v1 and virtio legacy pci use a 32bit PFN
for the queue. If the queue pfn is too large to fit in 32bits, which
we could hit on arm64 systems with 52bit physical addresses (even with
64K page size), we simply miss out a proper link to the other side of
the queue.
Add a check to validate the PFN, rather than silently breaking
the devices.
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Jason Wang <jasowang@redhat.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
drivers/virtio/virtio_mmio.c | 19 ++++++++++++++++---
drivers/virtio/virtio_pci_legacy.c | 11 +++++++++--
2 files changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/virtio/virtio_mmio.c b/drivers/virtio/virtio_mmio.c
index a9192fe4f345..47109baf37f7 100644
--- a/drivers/virtio/virtio_mmio.c
+++ b/drivers/virtio/virtio_mmio.c
@@ -358,6 +358,7 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned index,
struct virtqueue *vq;
unsigned long flags;
unsigned int num;
+ u64 addr;
int err;
if (!name)
@@ -394,16 +395,26 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned index,
goto error_new_virtqueue;
}
+ addr = virtqueue_get_desc_addr(vq);
+ /*
+ * virtio-mmio v1 uses a 32bit QUEUE PFN. If we have something that
+ * doesn't fit in 32bit, fail the setup rather than pretending to
+ * be successful.
+ */
+ if (vm_dev->version == 1 && (addr >> (PAGE_SHIFT + 32))) {
+ dev_err(&vdev->dev, "virtio-mmio: queue address too large\n");
+ err = -ENOMEM;
+ goto error_bad_pfn;
+ }
+
/* Activate the queue */
writel(virtqueue_get_vring_size(vq), vm_dev->base + VIRTIO_MMIO_QUEUE_NUM);
if (vm_dev->version == 1) {
writel(PAGE_SIZE, vm_dev->base + VIRTIO_MMIO_QUEUE_ALIGN);
- writel(virtqueue_get_desc_addr(vq) >> PAGE_SHIFT,
+ writel(addr >> PAGE_SHIFT,
vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
} else {
- u64 addr;
- addr = virtqueue_get_desc_addr(vq);
writel((u32)addr, vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_LOW);
writel((u32)(addr >> 32),
vm_dev->base + VIRTIO_MMIO_QUEUE_DESC_HIGH);
@@ -430,6 +441,8 @@ static struct virtqueue *vm_setup_vq(struct virtio_device *vdev, unsigned index,
return vq;
+error_bad_pfn:
+ vring_del_virtqueue(vq);
error_new_virtqueue:
if (vm_dev->version == 1) {
writel(0, vm_dev->base + VIRTIO_MMIO_QUEUE_PFN);
diff --git a/drivers/virtio/virtio_pci_legacy.c b/drivers/virtio/virtio_pci_legacy.c
index 2780886e8ba3..099d2cfb47b3 100644
--- a/drivers/virtio/virtio_pci_legacy.c
+++ b/drivers/virtio/virtio_pci_legacy.c
@@ -122,6 +122,7 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev,
struct virtqueue *vq;
u16 num;
int err;
+ u64 q_pfn;
/* Select the queue we're interested in */
iowrite16(index, vp_dev->ioaddr + VIRTIO_PCI_QUEUE_SEL);
@@ -141,9 +142,15 @@ static struct virtqueue *setup_vq(struct virtio_pci_device *vp_dev,
if (!vq)
return ERR_PTR(-ENOMEM);
+ q_pfn = virtqueue_get_desc_addr(vq) >> VIRTIO_PCI_QUEUE_ADDR_SHIFT;
+ if (q_pfn >> 32) {
+ dev_err(&vp_dev->pci_dev->dev, "virtio-pci queue PFN too large\n");
+ err = -ENOMEM;
+ goto out_deactivate;
+ }
+
/* activate the queue */
- iowrite32(virtqueue_get_desc_addr(vq) >> VIRTIO_PCI_QUEUE_ADDR_SHIFT,
- vp_dev->ioaddr + VIRTIO_PCI_QUEUE_PFN);
+ iowrite32((u32)q_pfn, vp_dev->ioaddr + VIRTIO_PCI_QUEUE_PFN);
vq->priv = (void __force *)vp_dev->ioaddr + VIRTIO_PCI_QUEUE_NOTIFY;
--
2.13.6
^ permalink raw reply related
* [PATCH 00/16] kvm: arm64: Support for dynamic IPA size
From: Suzuki K Poulose @ 2018-01-09 19:03 UTC (permalink / raw)
To: linux-arm-kernel
On arm64 we have a static limit of 40bits of physical address space
for the VM with KVM. This series lifts the limitation and allows the
VM to configure the physical address space upto 52bit on systems
where it is supported. We retain the default and minimum size to 40bits
to avoid breaking backward compatibility.
The interface provided is an IOCTL on the VM fd. The guest can change
only increase the limit from what is already configured, to prevent
breaking the devices which may have already been configured with a
particular guest PA. The guest can issue the request until something
is actually mapped into the stage2 table (e.g, memory region or device).
This also implies that we now have per VM configuration of stage2
control registers (VTCR_EL2 bits).
The arm64 page table level helpers are defined based on the page
table levels used by the host VA. So, the accessors may not work
if the guest uses more number of levels in stage2 than the stage1
of the host. In order to provide an independent stage2 page table,
we refactor the arm64 page table helpers to give us raw accessors
for each level, which should only used when that level is present.
And then, based on the VM, we make the decision of the stage2
page table using the raw accessors.
The series also adds :
- Support for handling 52bit IPA for vgic ITS.
- Cleanup in virtio to handle errors when the PFN used in
the virtio transport doesn't fit in 32bit.
Tested with
- Modified kvmtool, which can only be used for (patches included in
the series for reference / testing):
* with virtio-pci upto 44bit PA (Due to 4K page size for virtio-pci
legacy implemented by kvmtool)
* Upto 48bit PA with virtio-mmio, due to 32bit PFN limitation.
- Hacked Qemu (boot loader support for highmem, phys-shift support)
* with virtio-pci GIC-v3 ITS & MSI upto 52bit on Foundation model.
The series applies on arm64 for-next/core tree with 52bit PA support patches.
One would need the fix for virtio_mmio cleanup [1] on top of the arm64
tree to remove the warnings from virtio.
[1] https://marc.info/?l=linux-virtualization&m=151308636322117&w=2
Kristina Martsenko (1):
vgic: its: Add support for 52bit guest physical address
Suzuki K Poulose (15):
virtio: Validate queue pfn for 32bit transports
irqchip: gicv3-its: Add helpers for handling 52bit address
arm64: Make page table helpers reusable
arm64: Refactor pud_huge for reusability
arm64: Helper for parange to PASize
kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table
kvm: arm/arm64: Remove spurious WARN_ON
kvm: arm/arm64: Clean up stage2 pgd life time
kvm: arm/arm64: Delay stage2 page table allocation
kvm: arm/arm64: Prepare for VM specific stage2 translations
kvm: arm64: Make stage2 page table layout dynamic
kvm: arm64: Dynamic configuration of VTCR and VTTBR mask
kvm: arm64: Configure VTCR per VM
kvm: arm64: Switch to per VM IPA
kvm: arm64: Allow configuring physical address space size
Documentation/virtual/kvm/api.txt | 27 +++
arch/arm/include/asm/kvm_arm.h | 2 -
arch/arm/include/asm/kvm_host.h | 7 +
arch/arm/include/asm/kvm_mmu.h | 13 +-
arch/arm/include/asm/stage2_pgtable.h | 46 +++---
arch/arm64/include/asm/cpufeature.h | 16 ++
arch/arm64/include/asm/kvm_arm.h | 112 +++++++++++--
arch/arm64/include/asm/kvm_asm.h | 2 +-
arch/arm64/include/asm/kvm_host.h | 21 ++-
arch/arm64/include/asm/kvm_mmu.h | 83 ++++++++--
arch/arm64/include/asm/pgalloc.h | 32 +++-
arch/arm64/include/asm/pgtable.h | 61 ++++---
arch/arm64/include/asm/stage2_pgtable-nopmd.h | 42 -----
arch/arm64/include/asm/stage2_pgtable-nopud.h | 39 -----
arch/arm64/include/asm/stage2_pgtable.h | 211 ++++++++++++++++--------
arch/arm64/kvm/hyp/s2-setup.c | 34 +---
arch/arm64/kvm/hyp/switch.c | 8 +
arch/arm64/kvm/reset.c | 28 ++++
arch/arm64/mm/hugetlbpage.c | 2 +-
drivers/irqchip/irq-gic-v3-its.c | 2 +-
drivers/virtio/virtio_mmio.c | 19 ++-
drivers/virtio/virtio_pci_legacy.c | 11 +-
include/linux/irqchip/arm-gic-v3.h | 32 +++-
include/uapi/linux/kvm.h | 4 +
virt/kvm/arm/arm.c | 25 ++-
virt/kvm/arm/mmu.c | 228 +++++++++++++++-----------
virt/kvm/arm/vgic/vgic-its.c | 36 ++--
virt/kvm/arm/vgic/vgic-kvm-device.c | 2 +-
virt/kvm/arm/vgic/vgic-mmio-v3.c | 1 -
29 files changed, 738 insertions(+), 408 deletions(-)
delete mode 100644 arch/arm64/include/asm/stage2_pgtable-nopmd.h
delete mode 100644 arch/arm64/include/asm/stage2_pgtable-nopud.h
--
2.13.6
^ permalink raw reply
* [PATCH] mfd: syscon: Remove unused Exynos PMU headers
From: Krzysztof Kozlowski @ 2018-01-09 18:59 UTC (permalink / raw)
To: linux-arm-kernel
Since commit 5812f0106c44 ("phy: exynos4: Remove duplicated defines of
PHY register defines") and commit 7a66647b25b6 ("phy: exynos: Use one
define for enable bit") all users of syscon Exynos PMU headers (for PHY
drivers) are converted to use different headers so these can be removed.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
Actually I removed these headers in mentioned commits:
- https://www.spinics.net/lists/arm-kernel/msg568612.html
- https://www.spinics.net/lists/arm-kernel/msg568608.html
however this part of patch disappeared when applying...
---
include/linux/mfd/syscon/exynos4-pmu.h | 21 ---------------------
include/linux/mfd/syscon/exynos5-pmu.h | 19 -------------------
2 files changed, 40 deletions(-)
delete mode 100644 include/linux/mfd/syscon/exynos4-pmu.h
delete mode 100644 include/linux/mfd/syscon/exynos5-pmu.h
diff --git a/include/linux/mfd/syscon/exynos4-pmu.h b/include/linux/mfd/syscon/exynos4-pmu.h
deleted file mode 100644
index 278b1b1549e9..000000000000
--- a/include/linux/mfd/syscon/exynos4-pmu.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * Copyright (C) 2015 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_
-#define _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_
-
-/* Exynos4 PMU register definitions */
-
-/* MIPI_PHYn_CONTROL register offset: n = 0..1 */
-#define EXYNOS4_MIPI_PHY_CONTROL(n) (0x710 + (n) * 4)
-#define EXYNOS4_MIPI_PHY_ENABLE (1 << 0)
-#define EXYNOS4_MIPI_PHY_SRESETN (1 << 1)
-#define EXYNOS4_MIPI_PHY_MRESETN (1 << 2)
-#define EXYNOS4_MIPI_PHY_RESET_MASK (3 << 1)
-
-#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS4_H_ */
diff --git a/include/linux/mfd/syscon/exynos5-pmu.h b/include/linux/mfd/syscon/exynos5-pmu.h
deleted file mode 100644
index b4942a32b81d..000000000000
--- a/include/linux/mfd/syscon/exynos5-pmu.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Exynos5 SoC series Power Management Unit (PMU) register offsets
- * and bit definitions.
- *
- * Copyright (C) 2014 Samsung Electronics Co., Ltd.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
-#define _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_
-
-#define EXYNOS5_PHY_ENABLE BIT(0)
-#define EXYNOS5_MIPI_PHY_S_RESETN BIT(1)
-#define EXYNOS5_MIPI_PHY_M_RESETN BIT(2)
-
-#endif /* _LINUX_MFD_SYSCON_PMU_EXYNOS5_H_ */
--
2.11.0
^ permalink raw reply related
* [PATCH V5 00/13] drivers: Boot Constraint core
From: Greg Kroah-Hartman @ 2018-01-09 18:47 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cover.1513264961.git.viresh.kumar@linaro.org>
On Thu, Dec 14, 2017 at 09:03:07PM +0530, Viresh Kumar wrote:
> Hi Greg,
>
> Here is V5 of the boot constraints core based on your feedback from V4.
> Hope this looks better now :)
>
> I have tested the Hisilicon patches (again) on hikey 9660 board, IMX
> stuff was earlier tested by Sascha (Pengutronix) on i.MX6 and Qualcomm
> stuff was earlier tested by Rajendra (Qualcomm) on Dragonboard 410C
> (This required some more patches related to display driver which
> Rajendra should be sending separately later on).
Can you resend this? As you can tell, I've been a bit busy for the past
month or so :(
And you had a few different versions of at least one of these patches,
which is messy. Also, why is there no signed-off-by on the OF core
patches?
thanks,
greg k-h
^ permalink raw reply
* [PATCH 04/11] drm/bridge/synopsys: dw-hdmi: Export some PHY related functions
From: Jernej Škrabec @ 2018-01-09 18:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1586880.7NXXgpct7p@avalon>
Hi Laurent,
Dne torek, 09. januar 2018 ob 17:08:55 CET je Laurent Pinchart napisal(a):
> Hello,
>
> On Tuesday, 9 January 2018 17:58:46 EET Jernej ?krabec wrote:
> > Dne torek, 09. januar 2018 ob 11:43:08 CET je Archit Taneja napisal(a):
> > > On 12/31/2017 02:31 AM, Jernej Skrabec wrote:
> > >> Parts of PHY code could be useful also for custom PHYs. For example,
> > >> Allwinner A83T has custom PHY which is probably Synopsys gen2 PHY
> > >> with few additional memory mapped registers, so most of the Synopsys
> > >> PHY
> > >> related code could be reused.
> > >>
> > >> It turns out that even completely custom HDMI PHYs, such as the one
> > >> found in Allwinner H3, can reuse some of those functions. This would
> > >> suggest that (some?) functions exported in this commit are actually
> > >> part
> > >> of generic PHY interface and not really specific to Synopsys PHYs.
> > >>
> > >> Export useful PHY functions.
> > >>
> > >> Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> > >> ---
> > >>
> > >> drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 45 +++++++++++++++++-------
> > >> drivers/gpu/drm/bridge/synopsys/dw-hdmi.h | 2 ++
> > >> include/drm/bridge/dw_hdmi.h | 10 +++++++
> > >> 3 files changed, 44 insertions(+), 13 deletions(-)
> > >>
> > >> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > >> b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c index
> > >> 7ca14d7325b5..67467d0b683a 100644
> > >> --- a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
> > >> +++ b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
>
> [snip]
>
> > >> @@ -1065,6 +1067,23 @@ static void
> > >> dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable)
> > >>
> > >> HDMI_PHY_CONF0_SELDIPIF_MASK);
> > >>
> > >> }
> > >>
> > >> +void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi, u8 enable)
> > >> +{
> > >> + hdmi_mask_writeb(hdmi, enable, HDMI_MC_PHYRSTZ,
> > >> + HDMI_MC_PHYRSTZ_PHYRSTZ_OFFSET,
> > >> + HDMI_MC_PHYRSTZ_PHYRSTZ_MASK);
> > >> +}
> > >> +EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset);
>
> I don't remember the details, is the reset signal Gen2-specific ?
According to this comment:
/* PHY reset. The reset signal is active high on Gen2 PHYs. */
I would guess that it is not specific to Gen2, otherwise the comment wouldn't
be needed. I will remove "gen2" from the name.
>
> How about asserting and deasserting the reset signal in the same call
> instead of having to call this function twice ?
It works on A83T if reset signal is asserted and deasserted immediately. I
will change function according to your proposal.
Best regards,
Jernej
>
> > >> +void dw_hdmi_phy_set_slave_addr(struct dw_hdmi *hdmi)
> > >> +{
> > >> + hdmi_phy_test_clear(hdmi, 1);
> > >> + hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2,
> > >> + HDMI_PHY_I2CM_SLAVE_ADDR);
> > >> + hdmi_phy_test_clear(hdmi, 0);
> > >> +}
> > >> +EXPORT_SYMBOL_GPL(dw_hdmi_phy_set_slave_addr);
> > >
> > > Should this be called dw_hdmi_phy_gen2_set_slave_addr?
> >
> > Probably. I will rename it in v2 to be consistent with other phy
> > functions.
>
> The I2C write function is called dw_hdmi_phy_i2c_write(). If we want to be
> conosistent we should either rename this one to dw_hdmi_phy_i2c_set_addr()
> or rename them both to dw_hdmi_phy_gen2_i2c_write() and
> dw_hdmi_phy_gen2_i2c_set_addr(). I think I'd prefer the former, and we could
> even drop gen2 from dw_hdmi_phy_gen2_pddq() and dw_hdmi_phy_gen2_txpwron()
> if desired.
>
> > > Looks good otherwise. Same for patches 3 and 4 in this series.
> > >
> > >> +
> > >>
> > >> static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi)
> > >> {
> > >>
> > >> const struct dw_hdmi_phy_data *phy = hdmi->phy.data;
>
> [snip]
>
> --
> Regards,
>
> Laurent Pinchart
^ permalink raw reply
* [PATCH 1/2] drivers: psci: remove cluster terminology and dependency on physical_package_id
From: Sudeep Holla @ 2018-01-09 18:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109173451.GB17222@red-moon>
Hi Lorenzo,
On 09/01/18 17:34, Lorenzo Pieralisi wrote:
> On Tue, Jan 09, 2018 at 04:49:27PM +0000, Sudeep Holla wrote:
>> Since the definition of the term "cluster" is not well defined in the
>> architecture, we should avoid using it. Also the physical package id
>> is currently mapped to so called "clusters" in ARM/ARM64 platforms which
>> is already argumentative.
>
> I think we should describe why the PSCI checker uses the physical
> package id (ie because it is likely that power domains map to "clusters"
> - so physical package id *current* boundaries, it is trying to test
> "cluster" idle states) but I can easily rework the log before sending it
> upstream.
>
I agree. If I need to resend 2/2 based on review I will update the log
accordingly with acked-by tag. Otherwise, you can pick it up and update
the log.
> I will send it upstream for the next cycle along with patch (2), or
> if you prefer to send it yourself:
>
> Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>
> Thanks for putting it together,
> Lorenzo
>
>> This patch removes the dependency on physical_package_id from the topology
>> in this PSCI checker. Also it replaces all the occurences of clusters to
>> cpu_groups which is derived from core_sibling_mask and may not directly
>> map to physical "cluster".
>>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
>> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
>> ---
>> drivers/firmware/psci_checker.c | 46 ++++++++++++++++++++---------------------
>> 1 file changed, 22 insertions(+), 24 deletions(-)
>>
>> diff --git a/drivers/firmware/psci_checker.c b/drivers/firmware/psci_checker.c
>> index f3f4f810e5df..bb1c068bff19 100644
>> --- a/drivers/firmware/psci_checker.c
>> +++ b/drivers/firmware/psci_checker.c
>> @@ -77,8 +77,8 @@ static int psci_ops_check(void)
>> return 0;
>> }
>>
>> -static int find_clusters(const struct cpumask *cpus,
>> - const struct cpumask **clusters)
>> +static int find_cpu_groups(const struct cpumask *cpus,
>> + const struct cpumask **cpu_groups)
>> {
>> unsigned int nb = 0;
>> cpumask_var_t tmp;
>> @@ -88,11 +88,11 @@ static int find_clusters(const struct cpumask *cpus,
>> cpumask_copy(tmp, cpus);
>>
>> while (!cpumask_empty(tmp)) {
>> - const struct cpumask *cluster =
>> + const struct cpumask *cpu_group =
>> topology_core_cpumask(cpumask_any(tmp));
>>
>> - clusters[nb++] = cluster;
>> - cpumask_andnot(tmp, tmp, cluster);
>> + cpu_groups[nb++] = cpu_group;
>> + cpumask_andnot(tmp, tmp, cpu_group);
>> }
>>
>> free_cpumask_var(tmp);
>> @@ -170,24 +170,24 @@ static int hotplug_tests(void)
>> {
>> int err;
>> cpumask_var_t offlined_cpus;
>> - int i, nb_cluster;
>> - const struct cpumask **clusters;
>> + int i, nb_cpu_group;
>> + const struct cpumask **cpu_groups;
>> char *page_buf;
>>
>> err = -ENOMEM;
>> if (!alloc_cpumask_var(&offlined_cpus, GFP_KERNEL))
>> return err;
>> - /* We may have up to nb_available_cpus clusters. */
>> - clusters = kmalloc_array(nb_available_cpus, sizeof(*clusters),
>> - GFP_KERNEL);
>> - if (!clusters)
>> + /* We may have up to nb_available_cpus cpu_groups. */
>> + cpu_groups = kmalloc_array(nb_available_cpus, sizeof(*cpu_groups),
>> + GFP_KERNEL);
>> + if (!cpu_groups)
>> goto out_free_cpus;
>> page_buf = (char *)__get_free_page(GFP_KERNEL);
>> if (!page_buf)
>> - goto out_free_clusters;
>> + goto out_free_cpu_groups;
>>
>> err = 0;
>> - nb_cluster = find_clusters(cpu_online_mask, clusters);
>> + nb_cpu_group = find_cpu_groups(cpu_online_mask, cpu_groups);
>>
>> /*
>> * Of course the last CPU cannot be powered down and cpu_down() should
>> @@ -197,24 +197,22 @@ static int hotplug_tests(void)
>> err += down_and_up_cpus(cpu_online_mask, offlined_cpus);
>>
>> /*
>> - * Take down CPUs by cluster this time. When the last CPU is turned
>> - * off, the cluster itself should shut down.
>> + * Take down CPUs by cpu group this time. When the last CPU is turned
>> + * off, the cpu group itself should shut down.
>> */
>> - for (i = 0; i < nb_cluster; ++i) {
>> - int cluster_id =
>> - topology_physical_package_id(cpumask_any(clusters[i]));
>> + for (i = 0; i < nb_cpu_group; ++i) {
>> ssize_t len = cpumap_print_to_pagebuf(true, page_buf,
>> - clusters[i]);
>> + cpu_groups[i]);
>> /* Remove trailing newline. */
>> page_buf[len - 1] = '\0';
>> - pr_info("Trying to turn off and on again cluster %d "
>> - "(CPUs %s)\n", cluster_id, page_buf);
>> - err += down_and_up_cpus(clusters[i], offlined_cpus);
>> + pr_info("Trying to turn off and on again group %d (CPUs %s)\n",
>> + i, page_buf);
>> + err += down_and_up_cpus(cpu_groups[i], offlined_cpus);
>> }
>>
>> free_page((unsigned long)page_buf);
>> -out_free_clusters:
>> - kfree(clusters);
>> +out_free_cpu_groups:
>> + kfree(cpu_groups);
>> out_free_cpus:
>> free_cpumask_var(offlined_cpus);
>> return err;
>> --
>> 2.7.4
>>
--
Regards,
Sudeep
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH v3 3/6] coresight: Support panic kdump functionality
From: Mathieu Poirier @ 2018-01-09 18:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1513844415-11427-4-git-send-email-leo.yan@linaro.org>
On Thu, Dec 21, 2017 at 04:20:12PM +0800, Leo Yan wrote:
> After kernel panic happens, coresight has many useful info can be used
> for analysis. For example, the trace info from ETB RAM can be used to
> check the CPU execution flows before crash. So we can save the tracing
> data from sink devices, and rely on kdump to save DDR content and uses
> "crash" tool to extract coresight dumping from vmcore file.
>
> This patch is to add a simple framework to support panic dump
> functionality; it registers panic notifier, and provide the general APIs
> {coresight_kdump_add|coresight_kdump_del} as helper functions so any
> coresight device can add itself into dump list or delete as needed.
>
> This driver provides helper function coresight_kdump_update() to update
> the dump buffer base address and buffer size. This function can be used
> by coresight driver, e.g. it can be used to save ETM meta data info at
> runtime and these info can be prepared pre panic happening.
>
> When kernel panic happens, the notifier iterates dump list and calls
> callback function to dump device specific info. The panic dump is
> mainly used to dump trace data so we can get to know the execution flow
> before the panic happens.
>
> Signed-off-by: Leo Yan <leo.yan@linaro.org>
> ---
> drivers/hwtracing/coresight/Kconfig | 9 ++
> drivers/hwtracing/coresight/Makefile | 1 +
> .../hwtracing/coresight/coresight-panic-kdump.c | 154 +++++++++++++++++++++
> drivers/hwtracing/coresight/coresight-priv.h | 13 ++
> include/linux/coresight.h | 7 +
> 5 files changed, 184 insertions(+)
> create mode 100644 drivers/hwtracing/coresight/coresight-panic-kdump.c
>
> diff --git a/drivers/hwtracing/coresight/Kconfig b/drivers/hwtracing/coresight/Kconfig
> index ef9cb3c..4812529 100644
> --- a/drivers/hwtracing/coresight/Kconfig
> +++ b/drivers/hwtracing/coresight/Kconfig
> @@ -103,4 +103,13 @@ config CORESIGHT_CPU_DEBUG
> properly, please refer Documentation/trace/coresight-cpu-debug.txt
> for detailed description and the example for usage.
>
> +config CORESIGHT_PANIC_KDUMP
> + bool "CoreSight Panic Kdump driver"
> + depends on ARM || ARM64
At this time only ETMv4 supports the feature, so it is only ARM64.
> + help
> + This driver provides panic kdump functionality for CoreSight
> + devices. When a kernel panic happen a device supplied callback function
> + is used to save trace data to memory. From there we rely on kdump to extract
> + the trace data from kernel dump file.
> +
> endif
> diff --git a/drivers/hwtracing/coresight/Makefile b/drivers/hwtracing/coresight/Makefile
> index 61db9dd..946fe19 100644
> --- a/drivers/hwtracing/coresight/Makefile
> +++ b/drivers/hwtracing/coresight/Makefile
> @@ -18,3 +18,4 @@ obj-$(CONFIG_CORESIGHT_SOURCE_ETM4X) += coresight-etm4x.o \
> obj-$(CONFIG_CORESIGHT_DYNAMIC_REPLICATOR) += coresight-dynamic-replicator.o
> obj-$(CONFIG_CORESIGHT_STM) += coresight-stm.o
> obj-$(CONFIG_CORESIGHT_CPU_DEBUG) += coresight-cpu-debug.o
> +obj-$(CONFIG_CORESIGHT_PANIC_KDUMP) += coresight-panic-kdump.o
> diff --git a/drivers/hwtracing/coresight/coresight-panic-kdump.c b/drivers/hwtracing/coresight/coresight-panic-kdump.c
> new file mode 100644
> index 0000000..c21d20b
> --- /dev/null
> +++ b/drivers/hwtracing/coresight/coresight-panic-kdump.c
> @@ -0,0 +1,154 @@
> +// SPDX-License-Identifier: GPL-2.0
> +// Copyright (c) 2017 Linaro Limited.
> +#include <linux/coresight.h>
> +#include <linux/coresight-pmu.h>
> +#include <linux/cpumask.h>
> +#include <linux/device.h>
> +#include <linux/init.h>
> +#include <linux/list.h>
> +#include <linux/mm.h>
> +#include <linux/perf_event.h>
> +#include <linux/slab.h>
> +#include <linux/types.h>
> +
> +#include "coresight-priv.h"
> +
> +typedef void (*coresight_cb_t)(void *data);
> +
> +/**
> + * struct coresight_kdump_node - Node information for dump
> + * @cpu: The cpu this node is affined to.
> + * @csdev: Handler for coresight device.
> + * @buf: Pointer for dump buffer.
> + * @buf_size: Length of dump buffer.
> + * @list: Hook to the list.
> + */
> +struct coresight_kdump_node {
> + int cpu;
> + struct coresight_device *csdev;
> + char *buf;
> + unsigned int buf_size;
> + struct list_head list;
> +};
> +
> +static DEFINE_SPINLOCK(coresight_kdump_lock);
> +static LIST_HEAD(coresight_kdump_list);
> +static struct notifier_block coresight_kdump_nb;
> +
> +int coresight_kdump_update(struct coresight_device *csdev, char *buf,
> + unsigned int buf_size)
> +{
> + struct coresight_kdump_node *node = csdev->dump_node;
> +
> + if (!node) {
> + dev_err(&csdev->dev, "Failed to update dump node.\n");
> + return -EINVAL;
> + }
> +
> + node->buf = buf;
> + node->buf_size = buf_size;
> + return 0;
> +}
> +
> +int coresight_kdump_add(struct coresight_device *csdev, int cpu)
> +{
> + struct coresight_kdump_node *node;
> + unsigned long flags;
> +
> + node = kzalloc(sizeof(*node), GFP_KERNEL);
> + if (!node)
> + return -ENOMEM;
> +
> + csdev->dump_node = (void *)node;
> + node->cpu = cpu;
> + node->csdev = csdev;
> +
> + spin_lock_irqsave(&coresight_kdump_lock, flags);
> + list_add_tail(&node->list, &coresight_kdump_list);
> + spin_unlock_irqrestore(&coresight_kdump_lock, flags);
> + return 0;
> +}
> +
> +void coresight_kdump_del(struct coresight_device *csdev)
> +{
> + struct coresight_kdump_node *node, *next;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&coresight_kdump_lock, flags);
> + list_for_each_entry_safe(node, next, &coresight_kdump_list, list) {
> + if (node->csdev == csdev) {
> + list_del(&node->list);
> + kfree(node);
> + break;
> + }
> + }
> + spin_unlock_irqrestore(&coresight_kdump_lock, flags);
> +}
> +
> +static coresight_cb_t
> +coresight_kdump_get_cb(struct coresight_device *csdev)
> +{
> + coresight_cb_t cb = NULL;
> +
> + switch (csdev->type) {
> + case CORESIGHT_DEV_TYPE_SINK:
> + case CORESIGHT_DEV_TYPE_LINKSINK:
> + cb = sink_ops(csdev)->panic_cb;
> + break;
> + case CORESIGHT_DEV_TYPE_SOURCE:
> + cb = source_ops(csdev)->panic_cb;
> + break;
> + case CORESIGHT_DEV_TYPE_LINK:
> + cb = link_ops(csdev)->panic_cb;
> + break;
I don't see why we need a callback for link devices - didn't I raised
that question before?
And I've been thinking further about this. The way we call the panic callbacks
won't work. When a panic is triggered there might be trace data in the CS network
that hasn't made it to the sink yet and calling the panic callbacks for sinks
will lead to a loss of data.
That is why, when accessing from both sysFS and perf, the current implementation
takes great care to stop the tracers first and then deal with the sink. To fix
this I suggest to call the panic callbacks only for sources. What happens there
will depend on what interface is used (sysFS or perf) - look at what is
currently done to get a better understanding.
> + default:
> + dev_info(&csdev->dev, "Unsupport panic dump\n");
I would not bother with the dev_info()...
> + break;
> + }
> +
> + return cb;
> +}
> +
> +/**
> + * coresight_kdump_notify - Invoke panic dump callbacks, this is
> + * the main function to fulfill the panic dump. It distinguishs
> + * to two types: one is pre panic dump which the callback function
> + * handler is NULL and coresight drivers can use function
> + * coresight_kdump_update() to directly update dump buffer base
> + * address and buffer size, for this case this function does nothing
> + * and directly bail out; another case is for post panic dump so
> + * invoke callback on alive CPU.
Now that pre and post processing are gone the description above doesn't match
what the function is doing.
> + *
> + * Returns: 0 on success.
> + */
> +static int coresight_kdump_notify(struct notifier_block *nb,
> + unsigned long mode, void *_unused)
> +{
> + struct coresight_kdump_node *node;
> + struct coresight_device *csdev;
> + coresight_cb_t cb;
> + unsigned long flags;
> +
> + spin_lock_irqsave(&coresight_kdump_lock, flags);
> +
> + list_for_each_entry(node, &coresight_kdump_list, list) {
> + csdev = node->csdev;
> + cb = coresight_kdump_get_cb(csdev);
> + if (cb)
> + cb(csdev);
> + }
> +
> + spin_unlock_irqrestore(&coresight_kdump_lock, flags);
> + return 0;
> +}
> +
> +static int __init coresight_kdump_init(void)
> +{
> + int ret;
> +
> + coresight_kdump_nb.notifier_call = coresight_kdump_notify;
> + ret = atomic_notifier_chain_register(&panic_notifier_list,
> + &coresight_kdump_nb);
> + return ret;
> +}
> +late_initcall(coresight_kdump_init);
> diff --git a/drivers/hwtracing/coresight/coresight-priv.h b/drivers/hwtracing/coresight/coresight-priv.h
> index f1d0e21d..937750e 100644
> --- a/drivers/hwtracing/coresight/coresight-priv.h
> +++ b/drivers/hwtracing/coresight/coresight-priv.h
> @@ -151,4 +151,17 @@ static inline int etm_readl_cp14(u32 off, unsigned int *val) { return 0; }
> static inline int etm_writel_cp14(u32 off, u32 val) { return 0; }
> #endif
>
> +#ifdef CONFIG_CORESIGHT_PANIC_KDUMP
> +extern int coresight_kdump_add(struct coresight_device *csdev, int cpu);
> +extern void coresight_kdump_del(struct coresight_device *csdev);
> +extern int coresight_kdump_update(struct coresight_device *csdev,
> + char *buf, unsigned int buf_size);
> +#else
> +static inline int
> +coresight_kdump_add(struct coresight_device *csdev, int cpu) { return 0; }
> +static inline void coresight_kdump_del(struct coresight_device *csdev) {}
> +static inline int coresight_kdump_update(struct coresight_device *csdev,
> + char *buf, unsigned int buf_size) { return 0; }
static inline int
coresight_kdump_update(struct coresight_device *csdev, char *buf,
unsigned int buf_size) { return 0; }
> +#endif
> +
> #endif
> diff --git a/include/linux/coresight.h b/include/linux/coresight.h
> index d950dad..43e40fa 100644
> --- a/include/linux/coresight.h
> +++ b/include/linux/coresight.h
> @@ -171,6 +171,7 @@ struct coresight_device {
> bool orphan;
> bool enable; /* true only if configured as part of a path */
> bool activated; /* true only if a sink is part of a path */
> + void *dump_node;
Please add a description for this entry.
> };
>
> #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
> @@ -189,6 +190,7 @@ struct coresight_device {
> * @set_buffer: initialises buffer mechanic before a trace session.
> * @reset_buffer: finalises buffer mechanic after a trace session.
> * @update_buffer: update buffer pointers after a trace session.
> + * @panic_cb: hook function for panic notifier.
> */
> struct coresight_ops_sink {
> int (*enable)(struct coresight_device *csdev, u32 mode);
> @@ -205,6 +207,7 @@ struct coresight_ops_sink {
> void (*update_buffer)(struct coresight_device *csdev,
> struct perf_output_handle *handle,
> void *sink_config);
> + void (*panic_cb)(void *data);
> };
>
> /**
> @@ -212,10 +215,12 @@ struct coresight_ops_sink {
> * Operations available for links.
> * @enable: enables flow between iport and oport.
> * @disable: disables flow between iport and oport.
> + * @panic_cb: hook function for panic notifier.
> */
> struct coresight_ops_link {
> int (*enable)(struct coresight_device *csdev, int iport, int oport);
> void (*disable)(struct coresight_device *csdev, int iport, int oport);
> + void (*panic_cb)(void *data);
> };
>
> /**
> @@ -227,6 +232,7 @@ struct coresight_ops_link {
> * to the HW.
> * @enable: enables tracing for a source.
> * @disable: disables tracing for a source.
> + * @panic_cb: hook function for panic notifier.
> */
> struct coresight_ops_source {
> int (*cpu_id)(struct coresight_device *csdev);
> @@ -235,6 +241,7 @@ struct coresight_ops_source {
> struct perf_event *event, u32 mode);
> void (*disable)(struct coresight_device *csdev,
> struct perf_event *event);
> + void (*panic_cb)(void *data);
> };
>
> struct coresight_ops {
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 3/3] soc: samsung: Add SPDX license identifiers to headers
From: Krzysztof Kozlowski @ 2018-01-09 18:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109182956.2456-1-krzk@kernel.org>
Replace GPL license statements with SPDX GPL-2.0 license identifiers.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
include/linux/soc/samsung/exynos-pmu.h | 5 +----
include/linux/soc/samsung/exynos-regs-pmu.h | 6 +-----
2 files changed, 2 insertions(+), 9 deletions(-)
diff --git a/include/linux/soc/samsung/exynos-pmu.h b/include/linux/soc/samsung/exynos-pmu.h
index e57eb4b6cc5a..fc0b445bb36b 100644
--- a/include/linux/soc/samsung/exynos-pmu.h
+++ b/include/linux/soc/samsung/exynos-pmu.h
@@ -1,12 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2014 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Header for EXYNOS PMU Driver support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
*/
#ifndef __LINUX_SOC_EXYNOS_PMU_H
diff --git a/include/linux/soc/samsung/exynos-regs-pmu.h b/include/linux/soc/samsung/exynos-regs-pmu.h
index bebdde5dccd6..66dcb9ec273a 100644
--- a/include/linux/soc/samsung/exynos-regs-pmu.h
+++ b/include/linux/soc/samsung/exynos-regs-pmu.h
@@ -1,14 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* EXYNOS - Power management unit definition
*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *
* Notice:
* This is not a list of all Exynos Power Management Unit SFRs.
* There are too many of them, not mentioning subtle differences
--
2.11.0
^ permalink raw reply related
* [PATCH 2/3] memory: samsung: Add SPDX license identifiers
From: Krzysztof Kozlowski @ 2018-01-09 18:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109182956.2456-1-krzk@kernel.org>
Replace GPL license statements with SPDX GPL-2.0 license identifiers.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/memory/samsung/Kconfig | 1 +
drivers/memory/samsung/Makefile | 1 +
drivers/memory/samsung/exynos-srom.c | 18 +++++++-----------
drivers/memory/samsung/exynos-srom.h | 7 ++-----
4 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/memory/samsung/Kconfig b/drivers/memory/samsung/Kconfig
index 9de12222061c..79ce7ea58903 100644
--- a/drivers/memory/samsung/Kconfig
+++ b/drivers/memory/samsung/Kconfig
@@ -1,3 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
config SAMSUNG_MC
bool "Samsung Exynos Memory Controller support" if COMPILE_TEST
help
diff --git a/drivers/memory/samsung/Makefile b/drivers/memory/samsung/Makefile
index 9c554d5522ad..00587be66211 100644
--- a/drivers/memory/samsung/Makefile
+++ b/drivers/memory/samsung/Makefile
@@ -1 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_EXYNOS_SROM) += exynos-srom.o
diff --git a/drivers/memory/samsung/exynos-srom.c b/drivers/memory/samsung/exynos-srom.c
index bf827a666694..7edd7fb540f2 100644
--- a/drivers/memory/samsung/exynos-srom.c
+++ b/drivers/memory/samsung/exynos-srom.c
@@ -1,14 +1,10 @@
-/*
- * Copyright (c) 2015 Samsung Electronics Co., Ltd.
- * http://www.samsung.com/
- *
- * EXYNOS - SROM Controller support
- * Author: Pankaj Dubey <pankaj.dubey@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright (c) 2015 Samsung Electronics Co., Ltd.
+// http://www.samsung.com/
+//
+// EXYNOS - SROM Controller support
+// Author: Pankaj Dubey <pankaj.dubey@samsung.com>
#include <linux/io.h>
#include <linux/init.h>
diff --git a/drivers/memory/samsung/exynos-srom.h b/drivers/memory/samsung/exynos-srom.h
index 34660c6a57a9..da612797f522 100644
--- a/drivers/memory/samsung/exynos-srom.h
+++ b/drivers/memory/samsung/exynos-srom.h
@@ -1,13 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2015 Samsung Electronics Co., Ltd.
* http://www.samsung.com
*
* Exynos SROMC register definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
#ifndef __EXYNOS_SROM_H
#define __EXYNOS_SROM_H __FILE__
--
2.11.0
^ permalink raw reply related
* [PATCH 1/3] ARM: EXYNOS: Add SPDX license identifiers
From: Krzysztof Kozlowski @ 2018-01-09 18:29 UTC (permalink / raw)
To: linux-arm-kernel
Replace GPL license statements with SPDX GPL-2.0 and GPL-2.0+ license
identifiers.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/include/debug/exynos.S | 7 ++-----
arch/arm/include/debug/samsung.S | 10 +++-------
include/linux/serial_s3c.h | 17 ++---------------
3 files changed, 7 insertions(+), 27 deletions(-)
diff --git a/arch/arm/include/debug/exynos.S b/arch/arm/include/debug/exynos.S
index 60bf3c23200d..74b56769f9cb 100644
--- a/arch/arm/include/debug/exynos.S
+++ b/arch/arm/include/debug/exynos.S
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0 */
/*
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
* http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
/* pull in the relevant register and map files. */
diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index f4eeed2a1981..69201d7fb48f 100644
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -1,13 +1,9 @@
-/* arch/arm/plat-samsung/include/plat/debug-macro.S
- *
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
* Copyright 2005, 2007 Simtec Electronics
* http://armlinux.simtec.co.uk/
* Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
+ */
#include <linux/serial_s3c.h>
diff --git a/include/linux/serial_s3c.h b/include/linux/serial_s3c.h
index a7f004a3c177..463ed28d2b27 100644
--- a/include/linux/serial_s3c.h
+++ b/include/linux/serial_s3c.h
@@ -1,3 +1,4 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Internal header file for Samsung S3C2410 serial ports (UART0-2)
*
@@ -10,21 +11,7 @@
* Internal header file for MX1ADS serial ports (UART1 & 2)
*
* Copyright (C) 2002 Shane Nay (shane at minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-*/
+ */
#ifndef __ASM_ARM_REGS_SERIAL_H
#define __ASM_ARM_REGS_SERIAL_H
--
2.11.0
^ permalink raw reply related
* [RFT PATCH] crypto: arm64 - implement SHA-512 using special instructions
From: Ard Biesheuvel @ 2018-01-09 18:23 UTC (permalink / raw)
To: linux-arm-kernel
Implement the SHA-512 using the new special instructions that have
been introduced as an optional extension in ARMv8.2.
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
---
arch/arm64/crypto/Kconfig | 6 ++
arch/arm64/crypto/Makefile | 3 +
arch/arm64/crypto/sha512-ce-core.S | 207 +++++++++++++++++++++++++++++++++++++
arch/arm64/crypto/sha512-ce-glue.c | 119 +++++++++++++++++++++
4 files changed, 335 insertions(+)
create mode 100644 arch/arm64/crypto/sha512-ce-core.S
create mode 100644 arch/arm64/crypto/sha512-ce-glue.c
diff --git a/arch/arm64/crypto/Kconfig b/arch/arm64/crypto/Kconfig
index 70c517aa4501..aad288f4b9de 100644
--- a/arch/arm64/crypto/Kconfig
+++ b/arch/arm64/crypto/Kconfig
@@ -29,6 +29,12 @@ config CRYPTO_SHA2_ARM64_CE
select CRYPTO_HASH
select CRYPTO_SHA256_ARM64
+config CRYPTO_SHA512_ARM64_CE
+ tristate "SHA-384/SHA-512 digest algorithm (ARMv8 Crypto Extensions)"
+ depends on KERNEL_MODE_NEON
+ select CRYPTO_HASH
+ select CRYPTO_SHA512_ARM64
+
config CRYPTO_GHASH_ARM64_CE
tristate "GHASH/AES-GCM using ARMv8 Crypto Extensions"
depends on KERNEL_MODE_NEON
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index b5edc5918c28..d7573d31d397 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -14,6 +14,9 @@ sha1-ce-y := sha1-ce-glue.o sha1-ce-core.o
obj-$(CONFIG_CRYPTO_SHA2_ARM64_CE) += sha2-ce.o
sha2-ce-y := sha2-ce-glue.o sha2-ce-core.o
+obj-$(CONFIG_CRYPTO_SHA512_ARM64_CE) += sha512-ce.o
+sha512-ce-y := sha512-ce-glue.o sha512-ce-core.o
+
obj-$(CONFIG_CRYPTO_GHASH_ARM64_CE) += ghash-ce.o
ghash-ce-y := ghash-ce-glue.o ghash-ce-core.o
diff --git a/arch/arm64/crypto/sha512-ce-core.S b/arch/arm64/crypto/sha512-ce-core.S
new file mode 100644
index 000000000000..6c562f8df0b0
--- /dev/null
+++ b/arch/arm64/crypto/sha512-ce-core.S
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
+ *
+ * Copyright (C) 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+ //
+ // Temporary - for testing only. binutils has no support for these yet
+ //
+ .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
+ .set .Lq\b, \b
+ .set .Lv\b\().2d, \b
+ .endr
+
+ .macro sha512h, rd, rn, rm
+ .inst 0xce608000 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
+ .endm
+
+ .macro sha512h2, rd, rn, rm
+ .inst 0xce608400 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
+ .endm
+
+ .macro sha512su0, rd, rn
+ .inst 0xcec08000 | .L\rd | (.L\rn << 5)
+ .endm
+
+ .macro sha512su1, rd, rn, rm
+ .inst 0xce608800 | .L\rd | (.L\rn << 5) | (.L\rm << 16)
+ .endm
+
+ .text
+ .arch armv8-a+crypto
+
+ /*
+ * The SHA-512 round constants
+ */
+ .align 4
+.Lsha512_rcon:
+ .quad 0x428a2f98d728ae22, 0x7137449123ef65cd
+ .quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
+ .quad 0x3956c25bf348b538, 0x59f111f1b605d019
+ .quad 0x923f82a4af194f9b, 0xab1c5ed5da6d8118
+ .quad 0xd807aa98a3030242, 0x12835b0145706fbe
+ .quad 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
+ .quad 0x72be5d74f27b896f, 0x80deb1fe3b1696b1
+ .quad 0x9bdc06a725c71235, 0xc19bf174cf692694
+ .quad 0xe49b69c19ef14ad2, 0xefbe4786384f25e3
+ .quad 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65
+ .quad 0x2de92c6f592b0275, 0x4a7484aa6ea6e483
+ .quad 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5
+ .quad 0x983e5152ee66dfab, 0xa831c66d2db43210
+ .quad 0xb00327c898fb213f, 0xbf597fc7beef0ee4
+ .quad 0xc6e00bf33da88fc2, 0xd5a79147930aa725
+ .quad 0x06ca6351e003826f, 0x142929670a0e6e70
+ .quad 0x27b70a8546d22ffc, 0x2e1b21385c26c926
+ .quad 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df
+ .quad 0x650a73548baf63de, 0x766a0abb3c77b2a8
+ .quad 0x81c2c92e47edaee6, 0x92722c851482353b
+ .quad 0xa2bfe8a14cf10364, 0xa81a664bbc423001
+ .quad 0xc24b8b70d0f89791, 0xc76c51a30654be30
+ .quad 0xd192e819d6ef5218, 0xd69906245565a910
+ .quad 0xf40e35855771202a, 0x106aa07032bbd1b8
+ .quad 0x19a4c116b8d2d0c8, 0x1e376c085141ab53
+ .quad 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8
+ .quad 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb
+ .quad 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3
+ .quad 0x748f82ee5defb2fc, 0x78a5636f43172f60
+ .quad 0x84c87814a1f0ab72, 0x8cc702081a6439ec
+ .quad 0x90befffa23631e28, 0xa4506cebde82bde9
+ .quad 0xbef9a3f7b2c67915, 0xc67178f2e372532b
+ .quad 0xca273eceea26619c, 0xd186b8c721c0c207
+ .quad 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178
+ .quad 0x06f067aa72176fba, 0x0a637dc5a2c898a6
+ .quad 0x113f9804bef90dae, 0x1b710b35131c471b
+ .quad 0x28db77f523047d84, 0x32caab7b40c72493
+ .quad 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c
+ .quad 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a
+ .quad 0x5fcb6fab3ad6faec, 0x6c44198c4a475817
+
+ .macro dround, i0, i1, i2, i3, i4, rc0, rc1, in0, in1, in2, in3, in4
+ .ifnb \rc1
+ ld1 {v\rc1\().2d}, [x3], #16
+ .endif
+ add v\rc0\().2d, v\rc0\().2d, v\in0\().2d
+ ext v6.16b, v\i2\().16b, v\i3\().16b, #8
+ ext v\rc0\().16b, v\rc0\().16b, v\rc0\().16b, #8
+ ext v7.16b, v\i1\().16b, v\i2\().16b, #8
+ add v\i3\().2d, v\i3\().2d, v\rc0\().2d
+ .ifnb \in1
+ ext v10.16b, v\in3\().16b, v\in4\().16b, #8
+ sha512su0 v\in0\().2d, v\in1\().2d
+ .endif
+ sha512h q\i3, q6, v7.2d
+ .ifnb \in1
+ sha512su1 v\in0\().2d, v\in2\().2d, v10.2d
+ .endif
+ add v\i4\().2d, v\i1\().2d, v\i3\().2d
+ sha512h2 q\i3, q\i1, v\i0\().2d
+ .endm
+
+ /*
+ * void sha512_ce_transform(struct sha512_state *sst, u8 const *src,
+ * int blocks)
+ */
+ENTRY(sha512_ce_transform)
+ /* load state */
+ ld1 {v20.2d-v23.2d}, [x0]
+
+ /* load input */
+0: ld1 {v12.2d-v15.2d}, [x1], #64
+ ld1 {v16.2d-v19.2d}, [x1], #64
+ sub w2, w2, #1
+
+ /* load round constants */
+ adr x3, .Lsha512_rcon
+
+CPU_LE( rev64 v12.16b, v12.16b )
+CPU_LE( rev64 v13.16b, v13.16b )
+CPU_LE( rev64 v14.16b, v14.16b )
+CPU_LE( rev64 v15.16b, v15.16b )
+CPU_LE( rev64 v16.16b, v16.16b )
+CPU_LE( rev64 v17.16b, v17.16b )
+CPU_LE( rev64 v18.16b, v18.16b )
+CPU_LE( rev64 v19.16b, v19.16b )
+
+ ld1 {v8.2d}, [x3], #16
+
+ mov v0.16b, v20.16b
+ mov v1.16b, v21.16b
+ mov v2.16b, v22.16b
+ mov v3.16b, v23.16b
+
+ // v0 ab cd -- ef gh ab
+ // v1 cd -- ef gh ab cd
+ // v2 ef gh ab cd -- ef
+ // v3 gh ab cd -- ef gh
+ // v4 -- ef gh ab cd --
+
+ dround 0, 1, 2, 3, 4, 8, 9, 12, 13, 19, 16, 17
+ dround 3, 0, 4, 2, 1, 9, 8, 13, 14, 12, 17, 18
+ dround 2, 3, 1, 4, 0, 8, 9, 14, 15, 13, 18, 19
+ dround 4, 2, 0, 1, 3, 9, 8, 15, 16, 14, 19, 12
+ dround 1, 4, 3, 0, 2, 8, 9, 16, 17, 15, 12, 13
+
+ dround 0, 1, 2, 3, 4, 9, 8, 17, 18, 16, 13, 14
+ dround 3, 0, 4, 2, 1, 8, 9, 18, 19, 17, 14, 15
+ dround 2, 3, 1, 4, 0, 9, 8, 19, 12, 18, 15, 16
+ dround 4, 2, 0, 1, 3, 8, 9, 12, 13, 19, 16, 17
+ dround 1, 4, 3, 0, 2, 9, 8, 13, 14, 12, 17, 18
+
+ dround 0, 1, 2, 3, 4, 8, 9, 14, 15, 13, 18, 19
+ dround 3, 0, 4, 2, 1, 9, 8, 15, 16, 14, 19, 12
+ dround 2, 3, 1, 4, 0, 8, 9, 16, 17, 15, 12, 13
+ dround 4, 2, 0, 1, 3, 9, 8, 17, 18, 16, 13, 14
+ dround 1, 4, 3, 0, 2, 8, 9, 18, 19, 17, 14, 15
+
+ dround 0, 1, 2, 3, 4, 9, 8, 19, 12, 18, 15, 16
+ dround 3, 0, 4, 2, 1, 8, 9, 12, 13, 19, 16, 17
+ dround 2, 3, 1, 4, 0, 9, 8, 13, 14, 12, 17, 18
+ dround 4, 2, 0, 1, 3, 8, 9, 14, 15, 13, 18, 19
+ dround 1, 4, 3, 0, 2, 9, 8, 15, 16, 14, 19, 12
+
+ dround 0, 1, 2, 3, 4, 8, 9, 16, 17, 15, 12, 13
+ dround 3, 0, 4, 2, 1, 9, 8, 17, 18, 16, 13, 14
+ dround 2, 3, 1, 4, 0, 8, 9, 18, 19, 17, 14, 15
+ dround 4, 2, 0, 1, 3, 9, 8, 19, 12, 18, 15, 16
+ dround 1, 4, 3, 0, 2, 8, 9, 12, 13, 19, 16, 17
+
+ dround 0, 1, 2, 3, 4, 9, 8, 13, 14, 12, 17, 18
+ dround 3, 0, 4, 2, 1, 8, 9, 14, 15, 13, 18, 19
+ dround 2, 3, 1, 4, 0, 9, 8, 15, 16, 14, 19, 12
+ dround 4, 2, 0, 1, 3, 8, 9, 16, 17, 15, 12, 13
+ dround 1, 4, 3, 0, 2, 9, 8, 17, 18, 16, 13, 14
+
+ dround 0, 1, 2, 3, 4, 8, 9, 18, 19, 17, 14, 15
+ dround 3, 0, 4, 2, 1, 9, 8, 19, 12, 18, 15, 16
+ dround 2, 3, 1, 4, 0, 8, 9, 12
+ dround 4, 2, 0, 1, 3, 9, 8, 13
+ dround 1, 4, 3, 0, 2, 8, 9, 14
+
+ dround 0, 1, 2, 3, 4, 9, 8, 15
+ dround 3, 0, 4, 2, 1, 8, 9, 16
+ dround 2, 3, 1, 4, 0, 9, 8, 17
+ dround 4, 2, 0, 1, 3, 8, 9, 18
+ dround 1, 4, 3, 0, 2, 9, , 19
+
+ /* update state */
+ add v20.2d, v20.2d, v0.2d
+ add v21.2d, v21.2d, v1.2d
+ add v22.2d, v22.2d, v2.2d
+ add v23.2d, v23.2d, v3.2d
+
+ /* handled all input blocks? */
+ cbnz w2, 0b
+
+ /* store new state */
+3: st1 {v20.2d-v23.2d}, [x0]
+ ret
+ENDPROC(sha512_ce_transform)
diff --git a/arch/arm64/crypto/sha512-ce-glue.c b/arch/arm64/crypto/sha512-ce-glue.c
new file mode 100644
index 000000000000..a77c8632a589
--- /dev/null
+++ b/arch/arm64/crypto/sha512-ce-glue.c
@@ -0,0 +1,119 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * sha512-ce-glue.c - SHA-384/SHA-512 using ARMv8 Crypto Extensions
+ *
+ * Copyright (C) 2018 Linaro Ltd <ard.biesheuvel@linaro.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <asm/neon.h>
+#include <asm/simd.h>
+#include <asm/unaligned.h>
+#include <crypto/internal/hash.h>
+#include <crypto/sha.h>
+#include <crypto/sha512_base.h>
+#include <linux/cpufeature.h>
+#include <linux/crypto.h>
+#include <linux/module.h>
+
+MODULE_DESCRIPTION("SHA-384/SHA-512 secure hash using ARMv8 Crypto Extensions");
+MODULE_AUTHOR("Ard Biesheuvel <ard.biesheuvel@linaro.org>");
+MODULE_LICENSE("GPL v2");
+
+asmlinkage void sha512_ce_transform(struct sha512_state *sst, u8 const *src,
+ int blocks);
+
+asmlinkage void sha512_block_data_order(u64 *digest, u8 const *src, int blocks);
+
+static int sha512_ce_update(struct shash_desc *desc, const u8 *data,
+ unsigned int len)
+{
+ if (!may_use_simd())
+ return sha512_base_do_update(desc, data, len,
+ (sha512_block_fn *)sha512_block_data_order);
+
+ kernel_neon_begin();
+ sha512_base_do_update(desc, data, len,
+ (sha512_block_fn *)sha512_ce_transform);
+ kernel_neon_end();
+
+ return 0;
+}
+
+static int sha512_ce_finup(struct shash_desc *desc, const u8 *data,
+ unsigned int len, u8 *out)
+{
+ if (!may_use_simd()) {
+ if (len)
+ sha512_base_do_update(desc, data, len,
+ (sha512_block_fn *)sha512_block_data_order);
+ sha512_base_do_finalize(desc,
+ (sha512_block_fn *)sha512_block_data_order);
+ return sha512_base_finish(desc, out);
+ }
+
+ kernel_neon_begin();
+ sha512_base_do_update(desc, data, len,
+ (sha512_block_fn *)sha512_ce_transform);
+ sha512_base_do_finalize(desc, (sha512_block_fn *)sha512_ce_transform);
+ kernel_neon_end();
+ return sha512_base_finish(desc, out);
+}
+
+static int sha512_ce_final(struct shash_desc *desc, u8 *out)
+{
+ if (!may_use_simd()) {
+ sha512_base_do_finalize(desc,
+ (sha512_block_fn *)sha512_block_data_order);
+ return sha512_base_finish(desc, out);
+ }
+
+ kernel_neon_begin();
+ sha512_base_do_finalize(desc, (sha512_block_fn *)sha512_ce_transform);
+ kernel_neon_end();
+ return sha512_base_finish(desc, out);
+}
+
+static struct shash_alg algs[] = { {
+ .init = sha384_base_init,
+ .update = sha512_ce_update,
+ .final = sha512_ce_final,
+ .finup = sha512_ce_finup,
+ .descsize = sizeof(struct sha512_state),
+ .digestsize = SHA384_DIGEST_SIZE,
+ .base.cra_name = "sha384",
+ .base.cra_driver_name = "sha384-ce",
+ .base.cra_priority = 200,
+ .base.cra_flags = CRYPTO_ALG_TYPE_SHASH,
+ .base.cra_blocksize = SHA512_BLOCK_SIZE,
+ .base.cra_module = THIS_MODULE,
+}, {
+ .init = sha512_base_init,
+ .update = sha512_ce_update,
+ .final = sha512_ce_final,
+ .finup = sha512_ce_finup,
+ .descsize = sizeof(struct sha512_state),
+ .digestsize = SHA512_DIGEST_SIZE,
+ .base.cra_name = "sha512",
+ .base.cra_driver_name = "sha512-ce",
+ .base.cra_priority = 200,
+ .base.cra_flags = CRYPTO_ALG_TYPE_SHASH,
+ .base.cra_blocksize = SHA512_BLOCK_SIZE,
+ .base.cra_module = THIS_MODULE,
+} };
+
+static int __init sha512_ce_mod_init(void)
+{
+ return crypto_register_shashes(algs, ARRAY_SIZE(algs));
+}
+
+static void __exit sha512_ce_mod_fini(void)
+{
+ crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
+}
+
+module_cpu_feature_match(SHA512, sha512_ce_mod_init);
+module_exit(sha512_ce_mod_fini);
--
2.11.0
^ permalink raw reply related
* [PATCH 2/2] crypto: s5p-sss - Add SPDX license identifier
From: Krzysztof Kozlowski @ 2018-01-09 17:57 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180109175736.6885-1-krzk@kernel.org>
Replace GPL license statement with SPDX GPL-2.0 license identifier.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/crypto/s5p-sss.c | 24 ++++++++++--------------
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/drivers/crypto/s5p-sss.c b/drivers/crypto/s5p-sss.c
index 62830a43d959..188f44b7eb27 100644
--- a/drivers/crypto/s5p-sss.c
+++ b/drivers/crypto/s5p-sss.c
@@ -1,17 +1,13 @@
-/*
- * Cryptographic API.
- *
- * Support for Samsung S5PV210 and Exynos HW acceleration.
- *
- * Copyright (C) 2011 NetUP Inc. All rights reserved.
- * Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as published
- * by the Free Software Foundation.
- *
- * Hash part based on omap-sham.c driver.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Cryptographic API.
+//
+// Support for Samsung S5PV210 and Exynos HW acceleration.
+//
+// Copyright (C) 2011 NetUP Inc. All rights reserved.
+// Copyright (c) 2017 Samsung Electronics Co., Ltd. All rights reserved.
+//
+// Hash part based on omap-sham.c driver.
#include <linux/clk.h>
#include <linux/crypto.h>
--
2.11.0
^ permalink raw reply related
* [PATCH 1/2] crypto: exynos-rng - Add SPDX license identifier and correct module license
From: Krzysztof Kozlowski @ 2018-01-09 17:57 UTC (permalink / raw)
To: linux-arm-kernel
Replace GPL license statement with SPDX GPL-2.0 license identifier and
correct the module license to GPLv2.
The license itself was a generic GPL because of copy-and-paste from old
drivers/char/hw_random/exynos-rng.c driver (on which this was based on).
However the module license indicated GPL-2.0 or later. GPL-2.0 was
intended by author so fix up this mess.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
drivers/crypto/exynos-rng.c | 12 ++----------
1 file changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/crypto/exynos-rng.c b/drivers/crypto/exynos-rng.c
index 451620b475a0..a2e91f94096f 100644
--- a/drivers/crypto/exynos-rng.c
+++ b/drivers/crypto/exynos-rng.c
@@ -1,3 +1,4 @@
+// SPDX-License-Identifier: GPL-2.0
/*
* exynos-rng.c - Random Number Generator driver for the Exynos
*
@@ -6,15 +7,6 @@
* Loosely based on old driver from drivers/char/hw_random/exynos-rng.c:
* Copyright (C) 2012 Samsung Electronics
* Jonghwa Lee <jonghwa3.lee@samsung.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation;
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
*/
#include <linux/clk.h>
@@ -386,4 +378,4 @@ module_platform_driver(exynos_rng_driver);
MODULE_DESCRIPTION("Exynos H/W Random Number Generator driver");
MODULE_AUTHOR("Krzysztof Kozlowski <krzk@kernel.org>");
-MODULE_LICENSE("GPL");
+MODULE_LICENSE("GPL v2");
--
2.11.0
^ permalink raw reply related
* [PATCH v2 0/6] ARM branch predictor hardening
From: Russell King - ARM Linux @ 2018-01-09 17:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <BE82ED38-B07B-47AE-8D9D-0320E25F6CCF@gmail.com>
On Tue, Jan 09, 2018 at 09:13:37AM -0800, Florian Fainelli wrote:
> On January 8, 2018 10:55:27 AM PST, Marc Zyngier <marc.zyngier@arm.com> wrote:
> >This small series implements some basic BP hardening by invalidating
> >the BTB on CPUs that are known to be susceptible to aliasing attacks.
> >
> >These patches are closely modelled against what we do on arm64,
> >although simpler as we can rely on an architected instruction to
> >perform the invalidation. The notable exception is Cortex-A15, where
> >BTB invalidation behaves like a NOP, and the only way to shoot the
> >predictor down is to invalidate the icache *and* to have ACTLR[0] set
> >to 1 (which is a secure-only operation).
>
> Is there a publicly available test case/exploit that we could use to
> regress test this against? I will follow up with the Brahma-B15
> patches after you send your v3.
While there are some x86 programs as part of the original information
release, this is something that I've been concerned about, and over
the days since I've been working hard at researching the bugs on the
various ARM CPUs.
The first thing I need to say is that the original x86 programs have
several issues that make them unreliable even on x86 hardware - for
example, running them on a Core 2 Duo after replacing "rdtscp" with
"lfence; rdtsc" results in failures - partly because they're a slower
processor, but also because the exploits are not particularly well
written.
The whole idea is that you speculatively drag a cache line in and
identify which cache line was dragged in - particularly in the
spectre case, where we are trying to identify one of 256 cache lines.
This really gets messed up if the cache line for the zero or 255
byte value always gets loaded due to the compiler laying the data
out such that (eg) "temp" shares the same cache line as "array2"!
Hence, I'm really not impressed by these exploits - a failure with
them does not mean there isn't an issue, it just means that they
didn't identify an issue which could be due to bugs within the
exploit programs themselves!
So, I've been putting together a set of better exploit programs
which work on x86-64, x86-32, ARM64, and various ARM32 machines.
This has lead me to some interesting observations that I'm not yet
ready to share all the details of publicly, some of them lead me
to question whether flushing the BTB can be deemed to really
mitigate the problem.
This is why I've been fairly quiet on public forums about this so
far.
Please bear in mind that the release of this problem has not been
managed particularly well (the fact that there aren't fixes already
prepared and lined up to go tells you that) and there's quite a
panic to (a) understand and (b) come up with proper fixes at the
moment.
It is quite understandable that people want answers and fixes as a
top priority, but I believe that rushing ahead without a full and
proper understanding of the issues here would be very foolhardy,
and /could/ end up making exploitation easier rather than harder.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line in suburbia: sync at 8.8Mbps down 630kbps up
According to speedtest.net: 8.21Mbps down 510kbps up
^ permalink raw reply
* [Letux-kernel] [PATCH v5 3/5] misc serdev: Add w2sg0004 (gps receiver) power control driver
From: Andreas Kemnade @ 2018-01-09 17:43 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20171222124427.GI3374@localhost>
On Fri, 22 Dec 2017 13:44:27 +0100
Johan Hovold <johan@kernel.org> wrote:
[...]
> I'd suggest reiterating the problem you're trying to solve and
> enumerating the previously discussed potential solutions in order to
> find a proper abstraction level for this (before getting lost in
> implementation details).
>
The main point here is in short words: Having a device powered on or off
when the uart it is attached to, is used or not used anymore,
so the already available userspace applications do not need to be changed.
I digged out a bit around:
alternative aproaches were:
adding hooks to the uart/tty layer:
https://marc.info/?l=linux-kernel&m=143333222014616&w=2
https://marc.info/?l=devicetree&m=143130955414580&w=2
I do not find it right now in my archive:
adding a virtual gpio for dtr to the omap_serial driver.
The driver behind the virtual io would then handle pm. One reason it was
rejected was that the devicetree should only contain real hardware and
not virtual stuff.
Regards,
Andreas
-------------- next part --------------
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^ permalink raw reply
* [PATCH] ARM: dts: samsung: Remove unused samsung_k3pe0e000b
From: Krzysztof Kozlowski @ 2018-01-09 17:42 UTC (permalink / raw)
To: linux-arm-kernel
The only user of DTSI for Samsung K3PE0E000B memory was removed in
commit fa63d037283a ("ARM: dts: omap5: Make uevm as the official board
and deprecate sevm support") so get rid of this DTSI as well.
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
MAINTAINERS | 1 -
arch/arm/boot/dts/samsung_k3pe0e000b.dtsi | 68 -------------------------------
2 files changed, 69 deletions(-)
delete mode 100644 arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
diff --git a/MAINTAINERS b/MAINTAINERS
index 2842ce504fe3..36a5a13a1af4 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1849,7 +1849,6 @@ Q: https://patchwork.kernel.org/project/linux-samsung-soc/list/
S: Maintained
F: arch/arm/boot/dts/s3c*
F: arch/arm/boot/dts/s5p*
-F: arch/arm/boot/dts/samsung*
F: arch/arm/boot/dts/exynos*
F: arch/arm64/boot/dts/exynos/
F: arch/arm/plat-samsung/
diff --git a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi b/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
deleted file mode 100644
index dbdda36179ee..000000000000
--- a/arch/arm/boot/dts/samsung_k3pe0e000b.dtsi
+++ /dev/null
@@ -1,68 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Timings and Geometry for Samsung K3PE0E000B memory part
- */
-
-/ {
- samsung_K3PE0E000B: lpddr2 {
- compatible = "Samsung,K3PE0E000B","jedec,lpddr2-s4";
- density = <4096>;
- io-width = <32>;
-
- tRPab-min-tck = <3>;
- tRCD-min-tck = <3>;
- tWR-min-tck = <3>;
- tRASmin-min-tck = <3>;
- tRRD-min-tck = <2>;
- tWTR-min-tck = <2>;
- tXP-min-tck = <2>;
- tRTP-min-tck = <2>;
- tCKE-min-tck = <3>;
- tCKESR-min-tck = <3>;
- tFAW-min-tck = <8>;
-
- timings_samsung_K3PE0E000B_533MHz: lpddr2-timings at 0 {
- compatible = "jedec,lpddr2-timings";
- min-freq = <10000000>;
- max-freq = <533333333>;
- tRPab = <21000>;
- tRCD = <18000>;
- tWR = <15000>;
- tRAS-min = <42000>;
- tRRD = <10000>;
- tWTR = <7500>;
- tXP = <7500>;
- tRTP = <7500>;
- tCKESR = <15000>;
- tDQSCK-max = <5500>;
- tFAW = <50000>;
- tZQCS = <90000>;
- tZQCL = <360000>;
- tZQinit = <1000000>;
- tRAS-max-ns = <70000>;
- tDQSCK-max-derated = <6000>;
- };
-
- timings_samsung_K3PE0E000B_266MHz: lpddr2-timings at 1 {
- compatible = "jedec,lpddr2-timings";
- min-freq = <10000000>;
- max-freq = <266666666>;
- tRPab = <21000>;
- tRCD = <18000>;
- tWR = <15000>;
- tRAS-min = <42000>;
- tRRD = <10000>;
- tWTR = <7500>;
- tXP = <7500>;
- tRTP = <7500>;
- tCKESR = <15000>;
- tDQSCK-max = <5500>;
- tFAW = <50000>;
- tZQCS = <90000>;
- tZQCL = <360000>;
- tZQinit = <1000000>;
- tRAS-max-ns = <70000>;
- tDQSCK-max-derated = <6000>;
- };
- };
-};
--
2.11.0
^ permalink raw reply related
* [PATCH] ARM: OMAP: clock: Fix debugfs_create_*() usage
From: Aaro Koskinen @ 2018-01-09 17:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1514906735-8977-1-git-send-email-geert+renesas@glider.be>
Hi,
On Tue, Jan 02, 2018 at 04:25:35PM +0100, Geert Uytterhoeven wrote:
> When exposing data access through debugfs, the correct
> debugfs_create_*() functions must be used, depending on data type.
>
> Remove all casts from data pointers passed to debugfs_create_*()
> functions, as such casts prevent the compiler from flagging bugs.
>
> Correct all wrong usage:
> - clk.rate is unsigned long, not u32,
> - clk.flags is u8, not u32, which exposed the successive
> clk.rate_offset and clk.src_offset fields.
>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi>
A.
> ---
> Compile-tested only.
> ---
> arch/arm/mach-omap1/clock.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/clock.c b/arch/arm/mach-omap1/clock.c
> index 43e3e188f5213418..fa512413a4717221 100644
> --- a/arch/arm/mach-omap1/clock.c
> +++ b/arch/arm/mach-omap1/clock.c
> @@ -1011,17 +1011,17 @@ static int clk_debugfs_register_one(struct clk *c)
> return -ENOMEM;
> c->dent = d;
>
> - d = debugfs_create_u8("usecount", S_IRUGO, c->dent, (u8 *)&c->usecount);
> + d = debugfs_create_u8("usecount", S_IRUGO, c->dent, &c->usecount);
> if (!d) {
> err = -ENOMEM;
> goto err_out;
> }
> - d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
> + d = debugfs_create_ulong("rate", S_IRUGO, c->dent, &c->rate);
> if (!d) {
> err = -ENOMEM;
> goto err_out;
> }
> - d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
> + d = debugfs_create_x8("flags", S_IRUGO, c->dent, &c->flags);
> if (!d) {
> err = -ENOMEM;
> goto err_out;
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 1/2] drivers: psci: remove cluster terminology and dependency on physical_package_id
From: Lorenzo Pieralisi @ 2018-01-09 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515516568-31359-2-git-send-email-sudeep.holla@arm.com>
On Tue, Jan 09, 2018 at 04:49:27PM +0000, Sudeep Holla wrote:
> Since the definition of the term "cluster" is not well defined in the
> architecture, we should avoid using it. Also the physical package id
> is currently mapped to so called "clusters" in ARM/ARM64 platforms which
> is already argumentative.
I think we should describe why the PSCI checker uses the physical
package id (ie because it is likely that power domains map to "clusters"
- so physical package id *current* boundaries, it is trying to test
"cluster" idle states) but I can easily rework the log before sending it
upstream.
I will send it upstream for the next cycle along with patch (2), or
if you prefer to send it yourself:
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Thanks for putting it together,
Lorenzo
> This patch removes the dependency on physical_package_id from the topology
> in this PSCI checker. Also it replaces all the occurences of clusters to
> cpu_groups which is derived from core_sibling_mask and may not directly
> map to physical "cluster".
>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
> ---
> drivers/firmware/psci_checker.c | 46 ++++++++++++++++++++---------------------
> 1 file changed, 22 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/firmware/psci_checker.c b/drivers/firmware/psci_checker.c
> index f3f4f810e5df..bb1c068bff19 100644
> --- a/drivers/firmware/psci_checker.c
> +++ b/drivers/firmware/psci_checker.c
> @@ -77,8 +77,8 @@ static int psci_ops_check(void)
> return 0;
> }
>
> -static int find_clusters(const struct cpumask *cpus,
> - const struct cpumask **clusters)
> +static int find_cpu_groups(const struct cpumask *cpus,
> + const struct cpumask **cpu_groups)
> {
> unsigned int nb = 0;
> cpumask_var_t tmp;
> @@ -88,11 +88,11 @@ static int find_clusters(const struct cpumask *cpus,
> cpumask_copy(tmp, cpus);
>
> while (!cpumask_empty(tmp)) {
> - const struct cpumask *cluster =
> + const struct cpumask *cpu_group =
> topology_core_cpumask(cpumask_any(tmp));
>
> - clusters[nb++] = cluster;
> - cpumask_andnot(tmp, tmp, cluster);
> + cpu_groups[nb++] = cpu_group;
> + cpumask_andnot(tmp, tmp, cpu_group);
> }
>
> free_cpumask_var(tmp);
> @@ -170,24 +170,24 @@ static int hotplug_tests(void)
> {
> int err;
> cpumask_var_t offlined_cpus;
> - int i, nb_cluster;
> - const struct cpumask **clusters;
> + int i, nb_cpu_group;
> + const struct cpumask **cpu_groups;
> char *page_buf;
>
> err = -ENOMEM;
> if (!alloc_cpumask_var(&offlined_cpus, GFP_KERNEL))
> return err;
> - /* We may have up to nb_available_cpus clusters. */
> - clusters = kmalloc_array(nb_available_cpus, sizeof(*clusters),
> - GFP_KERNEL);
> - if (!clusters)
> + /* We may have up to nb_available_cpus cpu_groups. */
> + cpu_groups = kmalloc_array(nb_available_cpus, sizeof(*cpu_groups),
> + GFP_KERNEL);
> + if (!cpu_groups)
> goto out_free_cpus;
> page_buf = (char *)__get_free_page(GFP_KERNEL);
> if (!page_buf)
> - goto out_free_clusters;
> + goto out_free_cpu_groups;
>
> err = 0;
> - nb_cluster = find_clusters(cpu_online_mask, clusters);
> + nb_cpu_group = find_cpu_groups(cpu_online_mask, cpu_groups);
>
> /*
> * Of course the last CPU cannot be powered down and cpu_down() should
> @@ -197,24 +197,22 @@ static int hotplug_tests(void)
> err += down_and_up_cpus(cpu_online_mask, offlined_cpus);
>
> /*
> - * Take down CPUs by cluster this time. When the last CPU is turned
> - * off, the cluster itself should shut down.
> + * Take down CPUs by cpu group this time. When the last CPU is turned
> + * off, the cpu group itself should shut down.
> */
> - for (i = 0; i < nb_cluster; ++i) {
> - int cluster_id =
> - topology_physical_package_id(cpumask_any(clusters[i]));
> + for (i = 0; i < nb_cpu_group; ++i) {
> ssize_t len = cpumap_print_to_pagebuf(true, page_buf,
> - clusters[i]);
> + cpu_groups[i]);
> /* Remove trailing newline. */
> page_buf[len - 1] = '\0';
> - pr_info("Trying to turn off and on again cluster %d "
> - "(CPUs %s)\n", cluster_id, page_buf);
> - err += down_and_up_cpus(clusters[i], offlined_cpus);
> + pr_info("Trying to turn off and on again group %d (CPUs %s)\n",
> + i, page_buf);
> + err += down_and_up_cpus(cpu_groups[i], offlined_cpus);
> }
>
> free_page((unsigned long)page_buf);
> -out_free_clusters:
> - kfree(clusters);
> +out_free_cpu_groups:
> + kfree(cpu_groups);
> out_free_cpus:
> free_cpumask_var(offlined_cpus);
> return err;
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH 05/19] drm/vc4: Use the alpha format helper
From: Eric Anholt @ 2018-01-09 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <78890e262e8394b2319f15c11de3282a2a2a2efd.1515494838.git-series.maxime.ripard@free-electrons.com>
Maxime Ripard <maxime.ripard@free-electrons.com> writes:
> Now that the core has a drm format helper to tell if a format embeds an
> alpha component in it, let's use it.
>
> Cc: Eric Anholt <eric@anholt.net>
> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
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^ permalink raw reply
* [PATCH 08/11 v2] ARM: OMAP1: constify gpio_led
From: Aaro Koskinen @ 2018-01-09 17:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <c00efa8371f63d6b888590ea66767c832088cd1a.1514267721.git.arvind.yadav.cs@gmail.com>
On Tue, Dec 26, 2017 at 12:07:11PM +0530, Arvind Yadav wrote:
> gpio_led are not supposed to change at runtime.
> struct gpio_led_platform_data working with const gpio_led
> provided by <linux/leds.h>. So mark the non-const structs
> as const.
>
> Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com>
Acked-by: Aaro Koskinen <aaro.koskinen@iki.fi>
A.
> ---
> changes in v2:
> The GPIO LED driver can be built as a module, it can
> be loaded after the init sections have gone away.
> So removed '__initconst'.
>
> arch/arm/mach-omap1/board-h2.c | 2 +-
> arch/arm/mach-omap1/board-h3.c | 2 +-
> arch/arm/mach-omap1/board-htcherald.c | 2 +-
> arch/arm/mach-omap1/board-osk.c | 4 ++--
> 4 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm/mach-omap1/board-h2.c b/arch/arm/mach-omap1/board-h2.c
> index ab51f85..9aeb8ad 100644
> --- a/arch/arm/mach-omap1/board-h2.c
> +++ b/arch/arm/mach-omap1/board-h2.c
> @@ -274,7 +274,7 @@ static struct platform_device h2_kp_device = {
> .resource = h2_kp_resources,
> };
>
> -static struct gpio_led h2_gpio_led_pins[] = {
> +static const struct gpio_led h2_gpio_led_pins[] = {
> {
> .name = "h2:red",
> .default_trigger = "heartbeat",
> diff --git a/arch/arm/mach-omap1/board-h3.c b/arch/arm/mach-omap1/board-h3.c
> index ad339f5..2edcd63 100644
> --- a/arch/arm/mach-omap1/board-h3.c
> +++ b/arch/arm/mach-omap1/board-h3.c
> @@ -326,7 +326,7 @@ static struct spi_board_info h3_spi_board_info[] __initdata = {
> },
> };
>
> -static struct gpio_led h3_gpio_led_pins[] = {
> +static const struct gpio_led h3_gpio_led_pins[] = {
> {
> .name = "h3:red",
> .default_trigger = "heartbeat",
> diff --git a/arch/arm/mach-omap1/board-htcherald.c b/arch/arm/mach-omap1/board-htcherald.c
> index 67d4669..e6a79fd 100644
> --- a/arch/arm/mach-omap1/board-htcherald.c
> +++ b/arch/arm/mach-omap1/board-htcherald.c
> @@ -292,7 +292,7 @@ static struct platform_device herald_gpiokeys_device = {
> };
>
> /* LEDs for the Herald. These connect to the HTCPLD GPIO device. */
> -static struct gpio_led gpio_leds[] = {
> +static const struct gpio_led gpio_leds[] = {
> {"dpad", NULL, HTCPLD_GPIO_LED_DPAD, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
> {"kbd", NULL, HTCPLD_GPIO_LED_KBD, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
> {"vibrate", NULL, HTCPLD_GPIO_LED_VIBRATE, 0, 0, LEDS_GPIO_DEFSTATE_OFF},
> diff --git a/arch/arm/mach-omap1/board-osk.c b/arch/arm/mach-omap1/board-osk.c
> index c66372e..e2277b5 100644
> --- a/arch/arm/mach-omap1/board-osk.c
> +++ b/arch/arm/mach-omap1/board-osk.c
> @@ -167,7 +167,7 @@ static struct platform_device *osk5912_devices[] __initdata = {
> &osk5912_cf_device,
> };
>
> -static struct gpio_led tps_leds[] = {
> +static const struct gpio_led tps_leds[] = {
> /* NOTE: D9 and D2 have hardware blink support.
> * Also, D9 requires non-battery power.
> */
> @@ -385,7 +385,7 @@ static struct platform_device osk5912_lcd_device = {
> .id = -1,
> };
>
> -static struct gpio_led mistral_gpio_led_pins[] = {
> +static const struct gpio_led mistral_gpio_led_pins[] = {
> {
> .name = "mistral:red",
> .default_trigger = "heartbeat",
> --
> 2.7.4
>
^ permalink raw reply
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