* [PATCH 1/2 v2] ARM: dts: Add Aspeed SoC USB controllers to device-tree
From: Benjamin Herrenschmidt @ 2018-01-12 6:21 UTC (permalink / raw)
To: linux-arm-kernel
This adds the USB controllers to the DT template of the
AST24xx and AST25xx SoCs.
This patch doesn't enable them by default on any board specific
.dts yet. This will be done when we have the necessary clock/reset
and pinmux support. In the meantime though, this will work if
u-boot configures things properly.
For the AST2400 I only added pinmux definition for port 1
which is dual USB1/USB2. There are additional USB1 only ports
that might require more work but I don't have HW to test at
hand so I'm leaving that to whoever cares.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2: Previous patch was missing actually adding the nodes
(which was an old patch in my tree I had forgotten to
merge).
arch/arm/boot/dts/aspeed-g4.dtsi | 27 +++++++++++++++++++++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 40 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 67 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index b0d8431a3700..e55f2ad5de59 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -103,6 +103,23 @@
status = "disabled";
};
+ ehci0: usb at 1e6a1000 {
+ compatible = "aspeed,ast2400-ehci", "generic-ehci";
+ reg = <0x1e6a1000 0x100>;
+ interrupts = <5>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ status = "disabled";
+ };
+
+ uhci: usb at 1e6b0000 {
+ compatible = "aspeed,ast2400-uhci", "generic-uhci";
+ reg = <0x1e6b0000 0x100>;
+ interrupts = <14>;
+ #ports = <3>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -1227,6 +1244,16 @@
groups = "USBCKI";
};
+ pinctrl_usb2h_default: usb2h_default {
+ function = "USB2H1";
+ groups = "USB2H1";
+ };
+
+ pinctrl_usb2d_default: usb2d_default {
+ function = "USB2D1";
+ groups = "USB2D1";
+ };
+
pinctrl_vgabios_rom_default: vgabios_rom_default {
function = "VGABIOS_ROM";
groups = "VGABIOS_ROM";
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 40de3b66c33f..655258edee24 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -138,6 +138,31 @@
status = "disabled";
};
+ ehci0: usb at 1e6a1000 {
+ compatible = "aspeed,ast2500-ehci", "generic-ehci";
+ reg = <0x1e6a1000 0x100>;
+ interrupts = <5>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ status = "disabled";
+ };
+
+ ehci1: usb at 1e6a3000 {
+ compatible = "aspeed,ast2500-ehci", "generic-ehci";
+ reg = <0x1e6a3000 0x100>;
+ interrupts = <13>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
+ status = "disabled";
+ };
+
+ uhci: usb at 1e6b0000 {
+ compatible = "aspeed,ast2500-uhci", "generic-uhci";
+ reg = <0x1e6b0000 0x100>;
+ interrupts = <14>;
+ #ports = <2>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -1358,6 +1383,21 @@
groups = "USBCKI";
};
+ pinctrl_usb2ah_default: usb2ah_default {
+ function = "USB2AH";
+ groups = "USB2AH";
+ };
+
+ pinctrl_usb11bhid_default: usb11bhid_default {
+ function = "USB11BHID";
+ groups = "USB11BHID";
+ };
+
+ pinctrl_usb2bh_default: usb2bh_default {
+ function = "USB2BH";
+ groups = "USB2BH";
+ };
+
pinctrl_vgabiosrom_default: vgabiosrom_default {
function = "VGABIOSROM";
groups = "VGABIOSROM";
^ permalink raw reply related
* [PATCH 2/2] dts: ARM: Aspeed: Enable USB ports on ast2500 eval board
From: Benjamin Herrenschmidt @ 2018-01-12 6:21 UTC (permalink / raw)
To: linux-arm-kernel
This enables both USB ports as host with EHCI and UHCI
attached to them.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
v2: Unchanged (except subject)
arch/arm/boot/dts/aspeed-ast2500-evb.dts | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-ast2500-evb.dts b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
index 6946c8610c4c..0c3f14d05046 100644
--- a/arch/arm/boot/dts/aspeed-ast2500-evb.dts
+++ b/arch/arm/boot/dts/aspeed-ast2500-evb.dts
@@ -80,3 +80,21 @@
reg = <0x4d>;
};
};
+
+&ehci0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2ah_default>;
+};
+
+&ehci1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2bh_default>;
+};
+
+&uhci {
+ status = "okay";
+
+ /* No pinctrl, this follows the above EHCI settings */
+};
^ permalink raw reply related
* [PATCH v4 1/3] regulator: axp20x: add drivevbus support for axp803
From: Jagan Teki @ 2018-01-12 6:30 UTC (permalink / raw)
To: linux-arm-kernel
Like axp221, axp223, axp813 the axp803 is also supporting external
regulator to drive the OTG VBus through N_VBUSEN PMIC pin.
Add support for it.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v4:
- rebase on master
Changes for v3:
- Update drivevbus in table of regulators
Documentation/devicetree/bindings/mfd/axp20x.txt | 3 ++-
drivers/regulator/axp20x-regulator.c | 2 ++
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mfd/axp20x.txt b/Documentation/devicetree/bindings/mfd/axp20x.txt
index 9455503..d1762f3 100644
--- a/Documentation/devicetree/bindings/mfd/axp20x.txt
+++ b/Documentation/devicetree/bindings/mfd/axp20x.txt
@@ -43,7 +43,7 @@ Optional properties:
regulator to drive the OTG VBus, rather then
as an input pin which signals whether the
board is driving OTG VBus or not.
- (axp221 / axp223 / axp813 only)
+ (axp221 / axp223 / axp803/ axp813 only)
- x-powers,master-mode: Boolean (axp806 only). Set this when the PMIC is
wired for master mode. The default is slave mode.
@@ -132,6 +132,7 @@ FLDO2 : LDO : fldoin-supply : shared supply
LDO_IO0 : LDO : ips-supply : GPIO 0
LDO_IO1 : LDO : ips-supply : GPIO 1
RTC_LDO : LDO : ips-supply : always on
+DRIVEVBUS : Enable output : drivevbus-supply : external regulator
AXP806 regulators, type, and corresponding input supply names:
diff --git a/drivers/regulator/axp20x-regulator.c b/drivers/regulator/axp20x-regulator.c
index 181622b..91b8ff8 100644
--- a/drivers/regulator/axp20x-regulator.c
+++ b/drivers/regulator/axp20x-regulator.c
@@ -721,6 +721,8 @@ static int axp20x_regulator_probe(struct platform_device *pdev)
case AXP803_ID:
regulators = axp803_regulators;
nregulators = AXP803_REG_ID_MAX;
+ drivevbus = of_property_read_bool(pdev->dev.parent->of_node,
+ "x-powers,drive-vbus-en");
break;
case AXP806_ID:
regulators = axp806_regulators;
--
2.7.4
^ permalink raw reply related
* [PATCH v4 2/3] arm64: allwinner: axp803: Add drivevbus regulator
From: Jagan Teki @ 2018-01-12 6:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515738618-3617-1-git-send-email-jagan@amarulasolutions.com>
Add reg_drivevbus regualtor for boards which are using
external regulator to drive the OTG VBus through N_VBUSEN
PMIC pin.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v4:
- rebase on master
Changes for v3:
- none
arch/arm64/boot/dts/allwinner/axp803.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/axp803.dtsi b/arch/arm64/boot/dts/allwinner/axp803.dtsi
index ff8af52..e5eae8b 100644
--- a/arch/arm64/boot/dts/allwinner/axp803.dtsi
+++ b/arch/arm64/boot/dts/allwinner/axp803.dtsi
@@ -146,5 +146,10 @@
regulator-max-microvolt = <3000000>;
regulator-name = "rtc-ldo";
};
+
+ reg_drivevbus: drivevbus {
+ regulator-name = "drivevbus";
+ status = "disabled";
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH v4 3/3] arm64: allwinner: a64: bananapi-m64: add usb otg
From: Jagan Teki @ 2018-01-12 6:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515738618-3617-1-git-send-email-jagan@amarulasolutions.com>
Add usb otg support for bananapi-m64 board,
- USB-ID connected with PH9
- USB-DRVVBUS controlled by N_VBUSEN pin from PMIC
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v4:
- rebase on master
- tested otg host mode.
Changes for v3:
- Move the position of reg_drivevbus as per binding documentation.
Changes for v2:
- add drvvbus regulator
- add N_VBUSEN pin
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index a697567..26e8534 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
@@ -86,6 +86,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&ehci1 {
status = "okay";
};
@@ -156,6 +160,10 @@
status = "okay";
};
+&ohci0 {
+ status = "okay";
+};
+
&ohci1 {
status = "okay";
};
@@ -168,6 +176,7 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};
@@ -283,6 +292,11 @@
regulator-name = "vcc-rtc";
};
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
@@ -295,6 +309,13 @@
status = "okay";
};
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
&usbphy {
+ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ usb0_vbus-supply = <®_drivevbus>;
status = "okay";
};
--
2.7.4
^ permalink raw reply related
* [GIT PULL] ARM64: Xilinx ZynqMP SoC patches for v4.16
From: Michal Simek @ 2018-01-12 6:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112012847.iqol2xb2iro6wauk@localhost>
On 12.1.2018 02:28, Olof Johansson wrote:
> On Mon, Jan 08, 2018 at 02:02:18PM +0100, Michal Simek wrote:
>> Hi guys,
>>
>> please consider to pull these 3 patches to your tree. I have discussed
>> it with Arnd that this could be probably fine even it is a little bit late.
>>
>> Thanks,
>> Michal
>>
>>
>> The following changes since commit 4fbd8d194f06c8a3fd2af1ce560ddb31f7ec8323:
>>
>> Linux 4.15-rc1 (2017-11-26 16:01:47 -0800)
>>
>> are available in the git repository at:
>>
>> https://github.com/Xilinx/linux-xlnx.git tags/zynqmp-soc-for-4.16
>>
>> for you to fetch changes up to cee8113a295acfc4cd25728d7c3d44e6bc3bbff9:
>>
>> soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
>> (2018-01-08 13:42:47 +0100)
>>
>> ----------------------------------------------------------------
>> arm: Xilinx ZynqMP SoC patches for v4.16
>>
>> - Create drivers/soc/xilinx folder structure
>> - Add ZynqMP vcu init driver
>>
>> ----------------------------------------------------------------
>> Dhaval Shah (2):
>> dt-bindings: soc: xilinx: Add DT bindings to xlnx_vcu driver
>> soc: xilinx: xlnx_vcu: Add Xilinx ZYNQMP VCU logicoreIP init driver
>>
>> Michal Simek (1):
>> soc: xilinx: Create folder structure for soc specific drivers
>>
>
> Merged, but you should probably add a platform config option for Xilinx
> and use that instead of obj-y to descend into the directory?
Do you think change like this?
-obj-y += xilinx/
+obj-$(CONFIG_ARCH_ZYNQMP) += xilinx/
Just a note. This folder is supposed to be used by arm64/arm32 and
microblaze that's why I didn't put there any single config because it
doesn't exist. If you suggest to introduce new config option to label
xilinx platforms we can talk about it.
Argument against it could be also using these drivers by openrisc or
mips (mipsfpga) which are also fpga based.
Anyway I am happy to hear what you suggest.
Thanks,
Michal
--
Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
w: www.monstr.eu p: +42-0-721842854
Maintainer of Linux kernel - Xilinx Microblaze
Maintainer of Linux kernel - Xilinx Zynq ARM and ZynqMP ARM64 SoCs
U-Boot custodian - Xilinx Microblaze/Zynq/ZynqMP SoCs
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^ permalink raw reply
* [PATCH] dts: ARM: Add Aspeed virtual hub to SoC templates
From: Benjamin Herrenschmidt @ 2018-01-12 6:51 UTC (permalink / raw)
To: linux-arm-kernel
We don't yet enable it in any of the boards
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
---
arch/arm/boot/dts/aspeed-g4.dtsi | 8 ++++++++
arch/arm/boot/dts/aspeed-g5.dtsi | 13 +++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-g4.dtsi b/arch/arm/boot/dts/aspeed-g4.dtsi
index e55f2ad5de59..743b79014d3d 100644
--- a/arch/arm/boot/dts/aspeed-g4.dtsi
+++ b/arch/arm/boot/dts/aspeed-g4.dtsi
@@ -120,6 +120,14 @@
status = "disabled";
};
+ vhub: usb-vhub at 1e6a0000 {
+ compatible = "aspeed,ast2400-usb-vhub";
+ reg = <0x1e6a0000 0x300>;
+ interrupts = <5>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
index 655258edee24..e50d7f3e18a0 100644
--- a/arch/arm/boot/dts/aspeed-g5.dtsi
+++ b/arch/arm/boot/dts/aspeed-g5.dtsi
@@ -163,6 +163,14 @@
status = "disabled";
};
+ vhub: usb-vhub at 1e6a0000 {
+ compatible = "aspeed,ast2500-usb-vhub";
+ reg = <0x1e6a0000 0x300>;
+ interrupts = <5>;
+ clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
+ status = "disabled";
+ };
+
apb {
compatible = "simple-bus";
#address-cells = <1>;
@@ -1388,6 +1396,11 @@
groups = "USB2AH";
};
+ pinctrl_usb2ad_default: usb2ad_default {
+ function = "USB2AD";
+ groups = "USB2AD";
+ };
+
pinctrl_usb11bhid_default: usb11bhid_default {
function = "USB11BHID";
groups = "USB11BHID";
^ permalink raw reply related
* [PATCH v2] arm64: allwinner: a64: a64-olinuxino: add usb otg
From: Jagan Teki @ 2018-01-12 6:57 UTC (permalink / raw)
To: linux-arm-kernel
Add usb otg support for a64-olinuxino board,
- USB0-ID connected with PH9
- USB0-VBUSDET connected with PH6
- USB-DRVVBUS controlled by N_VBUSEN pin from PMIC
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- rebase on master
- tested otg host mode.
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
index 8807664..078ee94 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts
@@ -64,6 +64,10 @@
};
};
+&ehci0 {
+ status = "okay";
+};
+
&mmc0 {
pinctrl-names = "default";
pinctrl-0 = <&mmc0_pins>;
@@ -93,6 +97,10 @@
};
};
+&ohci0 {
+ status = "okay";
+};
+
&r_rsb {
status = "okay";
@@ -101,6 +109,7 @@
reg = <0x3a3>;
interrupt-parent = <&r_intc>;
interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
+ x-powers,drive-vbus-en; /* set N_VBUSEN as output pin */
};
};
@@ -215,8 +224,25 @@
regulator-name = "vcc-rtc";
};
+®_drivevbus {
+ regulator-name = "usb0-vbus";
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins_a>;
status = "okay";
};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpios = <&pio 7 9 GPIO_ACTIVE_HIGH>; /* PH9 */
+ usb0_vbus_det-gpio = <&pio 7 6 GPIO_ACTIVE_HIGH>; /* PH6 */
+ usb0_vbus-supply = <®_drivevbus>;
+ status = "okay";
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/6] crypto: engine - Permit to enqueue all async requests
From: Herbert Xu @ 2018-01-12 7:14 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180103201109.16077-3-clabbe.montjoie@gmail.com>
On Wed, Jan 03, 2018 at 09:11:05PM +0100, Corentin Labbe wrote:
> The crypto engine could actually only enqueue hash and ablkcipher request.
> This patch permit it to enqueue any type of crypto_async_request.
>
> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
> ---
> crypto/crypto_engine.c | 230 ++++++++++++++++++++++++------------------------
> include/crypto/engine.h | 59 +++++++------
> 2 files changed, 148 insertions(+), 141 deletions(-)
>
> diff --git a/crypto/crypto_engine.c b/crypto/crypto_engine.c
> index 61e7c4e02fd2..036270b61648 100644
> --- a/crypto/crypto_engine.c
> +++ b/crypto/crypto_engine.c
> @@ -15,7 +15,6 @@
> #include <linux/err.h>
> #include <linux/delay.h>
> #include <crypto/engine.h>
> -#include <crypto/internal/hash.h>
> #include <uapi/linux/sched/types.h>
> #include "internal.h"
>
> @@ -34,11 +33,10 @@ static void crypto_pump_requests(struct crypto_engine *engine,
> bool in_kthread)
> {
> struct crypto_async_request *async_req, *backlog;
> - struct ahash_request *hreq;
> - struct ablkcipher_request *breq;
> unsigned long flags;
> bool was_busy = false;
> - int ret, rtype;
> + int ret;
> + struct crypto_engine_reqctx *enginectx;
This all looks very good. Just one minor nit, since you're storing
this in the tfm ctx as opposed to the request ctx (which is indeed
an improvement), you should remove the "req" from its name.
Thanks!
--
Email: Herbert Xu <herbert@gondor.apana.org.au>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
^ permalink raw reply
* [PATCH 5/6] arm64: tegra: Add Tegra194 chip device tree
From: Mikko Perttunen @ 2018-01-12 7:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111215638.f5vxykb2vvxeypmk@rob-hp-laptop>
On 11.01.2018 23:56, Rob Herring wrote:
> On Mon, Jan 08, 2018 at 06:54:37AM +0200, Mikko Perttunen wrote:
>> Add the chip-level device tree, including binding headers, for the
>> NVIDIA Tegra194 "Xavier" system-on-chip. Only a small subset of devices
>> are initially available, enough to boot to UART console.
>>
>> Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
>> ---
>> arch/arm64/boot/dts/nvidia/tegra194.dtsi | 334 +++++++++++++++++++++++++++++
>> include/dt-bindings/clock/tegra194-clock.h | 59 +++++
>> include/dt-bindings/gpio/tegra194-gpio.h | 59 +++++
>> include/dt-bindings/reset/tegra194-reset.h | 40 ++++
>> 4 files changed, 492 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> create mode 100644 include/dt-bindings/clock/tegra194-clock.h
>> create mode 100644 include/dt-bindings/gpio/tegra194-gpio.h
>> create mode 100644 include/dt-bindings/reset/tegra194-reset.h
>>
>> diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> new file mode 100644
>> index 000000000000..51eff420816d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
>> @@ -0,0 +1,334 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +#include <dt-bindings/clock/tegra194-clock.h>
>> +#include <dt-bindings/gpio/tegra194-gpio.h>
>> +#include <dt-bindings/interrupt-controller/arm-gic.h>
>> +#include <dt-bindings/mailbox/tegra186-hsp.h>
>> +#include <dt-bindings/reset/tegra194-reset.h>
>> +
>> +/ {
>> + compatible = "nvidia,tegra194";
>
> Documented?
Ah, wasn't aware these needed to be documented as well. Will add in v2.
>
>> + interrupt-parent = <&gic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + uarta: serial at 3100000 {
>
> These should all be under a bus node. Tegra failed to do this at the
> start and we're still copy-n-pasting this mistake.
>
> Then you probably don't need 2 address and size cells for all the
> peripherals.
So I should create one big simple-bus node and put everything with an
address apart from /memory (and maybe /sysram) inside it?
>
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x03100000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTA>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTA>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + uartb: serial at 3110000 {
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x03110000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTB>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTB>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + uartd: serial at 3130000 {
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x03130000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTD>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTD>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + uarte: serial at 3140000 {
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x03140000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTE>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTE>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + uartf: serial at 3150000 {
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x03150000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTF>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTF>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + gen1_i2c: i2c at 3160000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x03160000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C1>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C1>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + uarth: serial at 3170000 {
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x03170000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTH>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTH>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + cam_i2c: i2c at 3180000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x03180000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C3>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C3>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + /* shares pads with dpaux1 */
>> + dp_aux_ch1_i2c: i2c at 3190000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x03190000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C4>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C4>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + /* shares pads with dpaux0 */
>> + dp_aux_ch0_i2c: i2c at 31b0000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x031b0000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C6>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C6>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + gen7_i2c: i2c at 31c0000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x031c0000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C7>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C7>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + gen9_i2c: i2c at 31e0000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x031e0000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C9>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C9>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + sdmmc1: sdhci at 3400000 {
>> + compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
>> + reg = <0x0 0x03400000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_SDMMC1>;
>> + clock-names = "sdhci";
>> + resets = <&bpmp TEGRA194_RESET_SDMMC1>;
>> + reset-names = "sdhci";
>> + status = "disabled";
>> + };
>> +
>> + sdmmc3: sdhci at 3440000 {
>> + compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
>> + reg = <0x0 0x03440000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_SDMMC3>;
>> + clock-names = "sdhci";
>> + resets = <&bpmp TEGRA194_RESET_SDMMC3>;
>> + reset-names = "sdhci";
>> + status = "disabled";
>> + };
>> +
>> + sdmmc4: sdhci at 3460000 {
>> + compatible = "nvidia,tegra194-sdhci", "nvidia,tegra186-sdhci";
>> + reg = <0x0 0x03460000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_SDMMC4>;
>> + clock-names = "sdhci";
>> + resets = <&bpmp TEGRA194_RESET_SDMMC4>;
>> + reset-names = "sdhci";
>> + status = "disabled";
>> + };
>> +
>> + gic: interrupt-controller at 3881000 {
>> + compatible = "arm,gic-400";
>> + #interrupt-cells = <3>;
>> + interrupt-controller;
>> + reg = <0x0 0x03881000 0x0 0x1000>,
>> + <0x0 0x03882000 0x0 0x2000>;
>> + interrupts = <GIC_PPI 9
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
>> + interrupt-parent = <&gic>;
>> + };
>> +
>> + hsp_top0: hsp at 3c00000 {
>> + compatible = "nvidia,tegra186-hsp";
>> + reg = <0x0 0x03c00000 0x0 0xa0000>;
>> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "doorbell";
>> + #mbox-cells = <2>;
>> + };
>> +
>> + gen2_i2c: i2c at c240000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x0c240000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C2>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C2>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + gen8_i2c: i2c at c250000 {
>> + compatible = "nvidia,tegra194-i2c", "nvidia,tegra114-i2c";
>> + reg = <0x0 0x0c250000 0x0 0x10000>;
>> + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + clocks = <&bpmp TEGRA194_CLK_I2C8>;
>> + clock-names = "div-clk";
>> + resets = <&bpmp TEGRA194_RESET_I2C8>;
>> + reset-names = "i2c";
>> + status = "disabled";
>> + };
>> +
>> + uartc: serial at c280000 {
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x0c280000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTC>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTC>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + uartg: serial at c290000 {
>> + compatible = "nvidia,tegra194-uart", "nvidia,tegra20-uart";
>> + reg = <0x0 0x0c290000 0x0 0x40>;
>> + reg-shift = <2>;
>> + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&bpmp TEGRA194_CLK_UARTG>;
>> + clock-names = "serial";
>> + resets = <&bpmp TEGRA194_RESET_UARTG>;
>> + reset-names = "serial";
>> + status = "disabled";
>> + };
>> +
>> + pmc at c360000 {
>> + compatible = "nvidia,tegra194-pmc";
>> + reg = <0 0x0c360000 0 0x10000>,
>> + <0 0x0c370000 0 0x10000>,
>> + <0 0x0c380000 0 0x10000>,
>> + <0 0x0c390000 0 0x10000>,
>> + <0 0x0c3a0000 0 0x10000>;
>> + reg-names = "pmc", "wake", "aotag", "scratch", "misc";
>> + };
>> +
>> + sysram at 40000000 {
>> + compatible = "nvidia,tegra194-sysram", "mmio-sram";
>> + reg = <0x0 0x40000000 0x0 0x50000>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0 0x0 0x0 0x40000000 0x0 0x50000>;
>> +
>> + cpu_bpmp_tx: shmem at 4e000 {
>> + compatible = "nvidia,tegra194-bpmp-shmem";
>> + reg = <0x0 0x4e000 0x0 0x1000>;
>> + label = "cpu-bpmp-tx";
>> + pool;
>> + };
>> +
>> + cpu_bpmp_rx: shmem at 4f000 {
>> + compatible = "nvidia,tegra194-bpmp-shmem";
>> + reg = <0x0 0x4f000 0x0 0x1000>;
>> + label = "cpu-bpmp-rx";
>> + pool;
>> + };
>> + };
>> +
>> + bpmp: bpmp {
>> + compatible = "nvidia,tegra186-bpmp";
>> + mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB
>> + TEGRA_HSP_DB_MASTER_BPMP>;
>> + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;
>> + #clock-cells = <1>;
>> + #reset-cells = <1>;
>> + #power-domain-cells = <1>;
>> +
>> + bpmp_i2c: i2c {
>> + compatible = "nvidia,tegra186-bpmp-i2c";
>> + nvidia,bpmp-bus-id = <5>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + };
>> +
>> + bpmp_thermal: thermal {
>> + compatible = "nvidia,tegra186-bpmp-thermal";
>> + #thermal-sensor-cells = <1>;
>> + };
>> + };
>> +
>> + timer {
>> + compatible = "arm,armv8-timer";
>> + interrupts = <GIC_PPI 13
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 14
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 11
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
>> + <GIC_PPI 10
>> + (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
>> + interrupt-parent = <&gic>;
>> + };
>> +};
>> diff --git a/include/dt-bindings/clock/tegra194-clock.h b/include/dt-bindings/clock/tegra194-clock.h
>> new file mode 100644
>> index 000000000000..7eba4763e375
>> --- /dev/null
>> +++ b/include/dt-bindings/clock/tegra194-clock.h
>> @@ -0,0 +1,59 @@
>> +/*
>> + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>
> Seems you missed using SPDX tag on this one.
Thanks, will fix.
>
>> + */
>> +
>> +#ifndef __ABI_MACH_T194_CLOCK_H
>> +#define __ABI_MACH_T194_CLOCK_H
>> +
>> +/** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
>> +#define TEGRA194_CLK_I2C1 48
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
>> +#define TEGRA194_CLK_I2C2 49
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
>> +#define TEGRA194_CLK_I2C3 50
>> +/** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
>> +#define TEGRA194_CLK_I2C4 51
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
>> +#define TEGRA194_CLK_I2C6 52
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
>> +#define TEGRA194_CLK_I2C7 53
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
>> +#define TEGRA194_CLK_I2C8 54
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
>> +#define TEGRA194_CLK_I2C9 55
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
>> +#define TEGRA194_CLK_SDMMC1 120
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
>> +#define TEGRA194_CLK_SDMMC3 122
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
>> +#define TEGRA194_CLK_SDMMC4 123
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
>> +#define TEGRA194_CLK_UARTA 155
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
>> +#define TEGRA194_CLK_UARTB 156
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
>> +#define TEGRA194_CLK_UARTC 157
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
>> +#define TEGRA194_CLK_UARTD 158
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
>> +#define TEGRA194_CLK_UARTE 159
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
>> +#define TEGRA194_CLK_UARTF 160
>> +/** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
>> +#define TEGRA194_CLK_UARTG 161
>> +/** @brief CLK_RST_CONTROLLER_CLK_SOURCE_UARTH switch divider output */
>> +#define TEGRA194_CLK_UARTH 190
>> +
>> +#endif
>> diff --git a/include/dt-bindings/gpio/tegra194-gpio.h b/include/dt-bindings/gpio/tegra194-gpio.h
>> new file mode 100644
>> index 000000000000..86435a73ef9e
>> --- /dev/null
>> +++ b/include/dt-bindings/gpio/tegra194-gpio.h
>> @@ -0,0 +1,59 @@
>> +/* SPDX-License-Identifier: GPL-2.0 */
>> +/*
>> + * This header provides constants for binding nvidia,tegra194-gpio*.
>> + *
>> + * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
>> + * provide names for this.
>> + *
>> + * The second cell contains standard flag values specified in gpio.h.
>> + */
>> +
>> +#ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
>> +#define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
>> +
>> +#include <dt-bindings/gpio/gpio.h>
>> +
>> +/* GPIOs implemented by main GPIO controller */
>> +#define TEGRA194_MAIN_GPIO_PORT_A 0
>> +#define TEGRA194_MAIN_GPIO_PORT_B 1
>> +#define TEGRA194_MAIN_GPIO_PORT_C 2
>> +#define TEGRA194_MAIN_GPIO_PORT_D 3
>> +#define TEGRA194_MAIN_GPIO_PORT_E 4
>> +#define TEGRA194_MAIN_GPIO_PORT_F 5
>> +#define TEGRA194_MAIN_GPIO_PORT_G 6
>> +#define TEGRA194_MAIN_GPIO_PORT_H 7
>> +#define TEGRA194_MAIN_GPIO_PORT_I 8
>> +#define TEGRA194_MAIN_GPIO_PORT_J 9
>> +#define TEGRA194_MAIN_GPIO_PORT_K 10
>> +#define TEGRA194_MAIN_GPIO_PORT_L 11
>> +#define TEGRA194_MAIN_GPIO_PORT_M 12
>> +#define TEGRA194_MAIN_GPIO_PORT_N 13
>> +#define TEGRA194_MAIN_GPIO_PORT_O 14
>> +#define TEGRA194_MAIN_GPIO_PORT_P 15
>> +#define TEGRA194_MAIN_GPIO_PORT_Q 16
>> +#define TEGRA194_MAIN_GPIO_PORT_R 17
>> +#define TEGRA194_MAIN_GPIO_PORT_S 18
>> +#define TEGRA194_MAIN_GPIO_PORT_T 19
>> +#define TEGRA194_MAIN_GPIO_PORT_U 20
>> +#define TEGRA194_MAIN_GPIO_PORT_V 21
>> +#define TEGRA194_MAIN_GPIO_PORT_W 22
>> +#define TEGRA194_MAIN_GPIO_PORT_X 23
>> +#define TEGRA194_MAIN_GPIO_PORT_Y 24
>> +#define TEGRA194_MAIN_GPIO_PORT_Z 25
>> +#define TEGRA194_MAIN_GPIO_PORT_FF 26
>> +#define TEGRA194_MAIN_GPIO_PORT_GG 27
>> +
>> +#define TEGRA194_MAIN_GPIO(port, offset) \
>> + ((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset)
>> +
>> +/* GPIOs implemented by AON GPIO controller */
>> +#define TEGRA194_AON_GPIO_PORT_AA 0
>> +#define TEGRA194_AON_GPIO_PORT_BB 1
>> +#define TEGRA194_AON_GPIO_PORT_CC 2
>> +#define TEGRA194_AON_GPIO_PORT_DD 3
>> +#define TEGRA194_AON_GPIO_PORT_EE 4
>> +
>> +#define TEGRA194_AON_GPIO(port, offset) \
>> + ((TEGRA194_AON_GPIO_PORT_##port * 8) + offset)
>> +
>> +#endif
>> diff --git a/include/dt-bindings/reset/tegra194-reset.h b/include/dt-bindings/reset/tegra194-reset.h
>> new file mode 100644
>> index 000000000000..7c6afac99c4a
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/tegra194-reset.h
>> @@ -0,0 +1,40 @@
>> +/*
>> + * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
>> + *
>> + * This program is free software; you can redistribute it and/or modify it
>> + * under the terms and conditions of the GNU General Public License,
>> + * version 2, as published by the Free Software Foundation.
>> + *
>> + * This program is distributed in the hope it will be useful, but WITHOUT
>> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
>> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
>> + * more details.
>> + *
>> + * You should have received a copy of the GNU General Public License
>> + * along with this program. If not, see <http://www.gnu.org/licenses/>.
>
> SPDX
Will fix.
Thanks,
Mikko
>
>> + */
>> +
>> +#ifndef __ABI_MACH_T194_RESET_H
>> +#define __ABI_MACH_T194_RESET_H
>> +
>> +#define TEGRA194_RESET_I2C1 24
>> +#define TEGRA194_RESET_I2C2 29
>> +#define TEGRA194_RESET_I2C3 30
>> +#define TEGRA194_RESET_I2C4 31
>> +#define TEGRA194_RESET_I2C6 32
>> +#define TEGRA194_RESET_I2C7 33
>> +#define TEGRA194_RESET_I2C8 34
>> +#define TEGRA194_RESET_I2C9 35
>> +#define TEGRA194_RESET_SDMMC1 82
>> +#define TEGRA194_RESET_SDMMC3 84
>> +#define TEGRA194_RESET_SDMMC4 85
>> +#define TEGRA194_RESET_UARTA 100
>> +#define TEGRA194_RESET_UARTB 101
>> +#define TEGRA194_RESET_UARTC 102
>> +#define TEGRA194_RESET_UARTD 103
>> +#define TEGRA194_RESET_UARTE 104
>> +#define TEGRA194_RESET_UARTF 105
>> +#define TEGRA194_RESET_UARTG 106
>> +#define TEGRA194_RESET_UARTH 107
>> +
>> +#endif
>> --
>> 2.1.4
>>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-tegra" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* [PATCH 1/2] dts: ARM: Aspeed-g5: Add missing USB clock and pinmux
From: Benjamin Herrenschmidt @ 2018-01-12 7:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515736921.31850.92.camel@kernel.crashing.org>
On Fri, 2018-01-12 at 17:02 +1100, Benjamin Herrenschmidt wrote:
> This adds the clock and pinmux default references to
> the Aspeed G5 SoC base device-tree for USB. The clk and
> pinmux drivers already know about these.
Drop this. It depends on a patch you don't have. I'll send a v2
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> ---
> arch/arm/boot/dts/aspeed-g5.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed-g5.dtsi
> index 8b3986a941f5..3c5c9b952ba8 100644
> --- a/arch/arm/boot/dts/aspeed-g5.dtsi
> +++ b/arch/arm/boot/dts/aspeed-g5.dtsi
> @@ -142,6 +142,7 @@
> compatible = "aspeed,ast2500-ehci", "generic-ehci";
> reg = <0x1e6a1000 0x100>;
> interrupts = <5>;
> + clocks = <&syscon ASPEED_CLK_GATE_USBPORT1CLK>;
> status = "disabled";
> };
>
> @@ -149,6 +150,7 @@
> compatible = "aspeed,ast2500-ehci", "generic-ehci";
> reg = <0x1e6a3000 0x100>;
> interrupts = <13>;
> + clocks = <&syscon ASPEED_CLK_GATE_USBPORT2CLK>;
> status = "disabled";
> };
>
> @@ -157,6 +159,7 @@
> reg = <0x1e6b0000 0x100>;
> interrupts = <14>;
> #ports = <2>;
> + clocks = <&syscon ASPEED_CLK_GATE_USBUHCICLK>;
> status = "disabled";
> };
>
> @@ -1387,6 +1390,21 @@
> groups = "USBCKI";
> };
>
> + pinctrl_usb2ah_default: usb2ah_default {
> + function = "USB2AH";
> + groups = "USB2AH";
> + };
> +
> + pinctrl_usb11bhid_default: usb11bhid_default {
> + function = "USB11BHID";
> + groups = "USB11BHID";
> + };
> +
> + pinctrl_usb2bh_default: usb2bh_default {
> + function = "USB2BH";
> + groups = "USB2BH";
> + };
> +
> pinctrl_vgabiosrom_default: vgabiosrom_default {
> function = "VGABIOSROM";
> groups = "VGABIOSROM";
^ permalink raw reply
* [PATCH net-next v4 0/4] net: mvpp2: 1000BaseX and 2500BaseX support
From: Antoine Tenart @ 2018-01-12 7:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111.113203.1899608306187914852.davem@davemloft.net>
Hi David,
On Thu, Jan 11, 2018 at 11:32:03AM -0500, David Miller wrote:
>
> Actually, this introduced build warnings, I'm reverting. Please fix this
> and repost.
The warning points a real issue. I'm sorry about that, seems like I
forgot to test this one after the last change... I'll send a new
(tested) version.
Thanks!
Antoine
--
Antoine T?nart, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH] ARM: imx: Remove epit support
From: Sascha Hauer @ 2018-01-12 7:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515511483-24706-1-git-send-email-fabio.estevam@nxp.com>
On Tue, Jan 09, 2018 at 01:24:43PM -0200, Fabio Estevam wrote:
> Currently there is no user of EPIT, so remove such unused code.
>
> If someone wants to add EPIT support back, then the person needs to
> create a proper support into drivers/clocksource/ and add device
> tree support, proper bindings, etc.
>
> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply
* [PATCH 1/4 v7] drm/bridge: Add bindings for TI THS8134
From: Linus Walleij @ 2018-01-12 7:48 UTC (permalink / raw)
To: linux-arm-kernel
This adds device tree bindings for the Texas Instruments
THS8134, THS8134A and THS8134B VGA DACs by extending and
renaming the existing bindings for THS8135.
These DACs are used for the VGA outputs on the ARM reference
designs such as Integrator, Versatile and RealView.
Cc: devicetree at vger.kernel.org
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v6->v7:
- No changes, just resending with the series.
ChangeLog v5->v6:
- Fix the more-to-less specific compatible strings.
- Fix some speling.
- Collect Laurent's review tag.
ChangeLog v2->v5:
- Dropped the "ti,ths813x" as it turns out we need precise info
about the sub-variant anyways as they all very in timings.
- Refine the THS8134 variants, it turns out ths8134, ths8134a
and ths8134b are three different variants of ths8134.
ChangeLog v1->v2:
- Introduce specific-to-general compatible string:
compatible = "ti,ths8134a", "ti,ths813x";
so drivers can handle the whole family the same way.
- Collected Rob's ACK.
---
.../display/bridge/{ti,ths8135.txt => ti,ths813x.txt} | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
rename Documentation/devicetree/bindings/display/bridge/{ti,ths8135.txt => ti,ths813x.txt} (69%)
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt b/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
similarity index 69%
rename from Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
rename to Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
index 6ec1a880ac18..df3d7c1ac09e 100644
--- a/Documentation/devicetree/bindings/display/bridge/ti,ths8135.txt
+++ b/Documentation/devicetree/bindings/display/bridge/ti,ths813x.txt
@@ -1,11 +1,16 @@
-THS8135 Video DAC
------------------
+THS8134 and THS8135 Video DAC
+-----------------------------
-This is the binding for Texas Instruments THS8135 Video DAC bridge.
+This is the binding for Texas Instruments THS8134, THS8134A, THS8134B and
+THS8135 Video DAC bridges.
Required properties:
-- compatible: Must be "ti,ths8135"
+- compatible: Must be one of
+ "ti,ths8134"
+ "ti,ths8134a," "ti,ths8134"
+ "ti,ths8134b", "ti,ths8134"
+ "ti,ths8135"
Required nodes:
--
2.14.3
^ permalink raw reply related
* [PATCH 2/4 v7] drm/bridge: Provide a way to embed timing info in bridges
From: Linus Walleij @ 2018-01-12 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112074854.9560-1-linus.walleij@linaro.org>
After some discussion and failed patch sets trying to convey
the right timing information between the display engine and
a bridge using the connector, I try instead to use an optional
timing information container in the bridge itself, so that
display engines can retrieve it from any bridge and use it to
determine how to drive outputs.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v6->v7:
- Fix the comment style to use the new inline type of kerneldoc
for struct members.
- Need an explicit ACK/review by someone on this patch to continue
with the series...
ChangeLog v5->v6:
- Sort forward struct declarations alphabetically
- Switch to using DRM_BUS_FLAG_PIXDATA_[POS|NEG]EDGE to indicate
positive or negatice clock samling edge
ChangeLog ->v5:
- New patch
---
include/drm/drm_bridge.h | 33 +++++++++++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/include/drm/drm_bridge.h b/include/drm/drm_bridge.h
index 682d01ba920c..d3c2eea0bb63 100644
--- a/include/drm/drm_bridge.h
+++ b/include/drm/drm_bridge.h
@@ -29,6 +29,7 @@
#include <drm/drm_modes.h>
struct drm_bridge;
+struct drm_bridge_timings;
struct drm_panel;
/**
@@ -222,6 +223,35 @@ struct drm_bridge_funcs {
void (*enable)(struct drm_bridge *bridge);
};
+/**
+ * struct drm_bridge_timings - timing information for the bridge
+ */
+struct drm_bridge_timings {
+ /**
+ * @sampling_edge:
+ *
+ * Tells whether the bridge samples the digital input signal
+ * from the display engine on the positive or negative edge of the clock,
+ * this should reuse the DRM_BUS_FLAG_PIXDATA_[POS|NEG]EDGE bitwise
+ * flags from the DRM connector (bit 2 and 3 valid).
+ */
+ u32 sampling_edge;
+ /**
+ * @setup_time_ps:
+ *
+ * Defines the time in picoseconds the input data lines must be
+ * stable before the clock edge.
+ */
+ u32 setup_time_ps;
+ /**
+ * @hold_time_ps:
+ *
+ * Defines the time in picoseconds taken for the bridge to sample the
+ * input signal after the clock edge.
+ */
+ u32 hold_time_ps;
+};
+
/**
* struct drm_bridge - central DRM bridge control structure
* @dev: DRM device this bridge belongs to
@@ -229,6 +259,8 @@ struct drm_bridge_funcs {
* @next: the next bridge in the encoder chain
* @of_node: device node pointer to the bridge
* @list: to keep track of all added bridges
+ * @timings: the timing specification for the bridge, if any (may
+ * be NULL)
* @funcs: control functions
* @driver_private: pointer to the bridge driver's internal context
*/
@@ -240,6 +272,7 @@ struct drm_bridge {
struct device_node *of_node;
#endif
struct list_head list;
+ const struct drm_bridge_timings *timings;
const struct drm_bridge_funcs *funcs;
void *driver_private;
--
2.14.3
^ permalink raw reply related
* [PATCH 3/4 v7] drm/bridge: Add timing support to dumb VGA DAC
From: Linus Walleij @ 2018-01-12 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112074854.9560-1-linus.walleij@linaro.org>
This extends the dumb VGA DAC bridge to handle the THS8134A
and THS8134B VGA DACs in addition to those already handled.
We assign the proper timing data to the pointer inside the
bridge struct so display controllers that need to align their
timings to the bridge can pick it up and work from there.
Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v5->v6:
- Use DRM_BUS_FLAG_PIXDATA_[POS|NEG]EDGE to indicate
the sampling edge of the clock signal.
- Skip intermediate variable for timings.
- Leave timings as NULL for really dumb VGA DACs.
- Collect Laurent's Review tag.
ChangeLog v4->v5:
- Rewrite the support using the new concept of defining
fine-granular sampling (setup+hold) timing definitions
stored in the bridge timings struct.
ChangeLog v3->v4:
- Actually have the code syntactically correct and compiling :(
(Kconfig mistake.)
(...)
AS usr/initramfs_data.o
AR usr/built-in.o
CC drivers/gpu/drm/bridge/dumb-vga-dac.o
AR drivers/gpu/drm/bridge/built-in.o
AR drivers/gpu/drm/built-in.o
AR drivers/gpu/built-in.o
AR drivers/built-in.o
(...)
ChangeLog v2->v3:
- Move const specifier.
- Cut one line of code assigning bus flags.
- Preserve the "ti,ths8135" compatible for elder device trees.
ChangeLog v1->v2:
- Alphabetize includes
- Use a u32 with the bus polarity flags and just encode the
polarity using the DRM define directly.
- Rename vendor_data to vendor_info.
- Simplify assignment of the flag as it is just a simple
u32 now.
- Probe all TI variants on the "ti,ths813x" wildcard for now,
we only need to know that the device is in this family to
set the clock edge flag right.
---
drivers/gpu/drm/bridge/dumb-vga-dac.c | 59 +++++++++++++++++++++++++++++++++--
1 file changed, 56 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c b/drivers/gpu/drm/bridge/dumb-vga-dac.c
index de5e7dee7ad6..498d5948d1a8 100644
--- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
+++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
@@ -11,6 +11,7 @@
*/
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/of_graph.h>
#include <linux/regulator/consumer.h>
@@ -204,6 +205,7 @@ static int dumb_vga_probe(struct platform_device *pdev)
vga->bridge.funcs = &dumb_vga_bridge_funcs;
vga->bridge.of_node = pdev->dev.of_node;
+ vga->bridge.timings = of_device_get_match_data(&pdev->dev);
drm_bridge_add(&vga->bridge);
@@ -222,10 +224,61 @@ static int dumb_vga_remove(struct platform_device *pdev)
return 0;
}
+/*
+ * We assume the ADV7123 DAC is the "default" for historical reasons
+ * Information taken from the ADV7123 datasheet, revision D.
+ * NOTE: the ADV7123EP seems to have other timings and need a new timings
+ * set if used.
+ */
+static const struct drm_bridge_timings default_dac_timings = {
+ /* Timing specifications, datasheet page 7 */
+ .sampling_edge = DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ .setup_time_ps = 500,
+ .hold_time_ps = 1500,
+};
+
+/*
+ * Information taken from the THS8134, THS8134A, THS8134B datasheet named
+ * "SLVS205D", dated May 1990, revised March 2000.
+ */
+static const struct drm_bridge_timings ti_ths8134_dac_timings = {
+ /* From timing diagram, datasheet page 9 */
+ .sampling_edge = DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ /* From datasheet, page 12 */
+ .setup_time_ps = 3000,
+ /* I guess this means latched input */
+ .hold_time_ps = 0,
+};
+
+/*
+ * Information taken from the THS8135 datasheet named "SLAS343B", dated
+ * May 2001, revised April 2013.
+ */
+static const struct drm_bridge_timings ti_ths8135_dac_timings = {
+ /* From timing diagram, datasheet page 14 */
+ .sampling_edge = DRM_BUS_FLAG_PIXDATA_POSEDGE,
+ /* From datasheet, page 16 */
+ .setup_time_ps = 2000,
+ .hold_time_ps = 500,
+};
+
static const struct of_device_id dumb_vga_match[] = {
- { .compatible = "dumb-vga-dac" },
- { .compatible = "adi,adv7123" },
- { .compatible = "ti,ths8135" },
+ {
+ .compatible = "dumb-vga-dac",
+ .data = NULL,
+ },
+ {
+ .compatible = "adi,adv7123",
+ .data = &default_dac_timings,
+ },
+ {
+ .compatible = "ti,ths8135",
+ .data = &ti_ths8135_dac_timings,
+ },
+ {
+ .compatible = "ti,ths8134",
+ .data = &ti_ths8134_dac_timings,
+ },
{},
};
MODULE_DEVICE_TABLE(of, dumb_vga_match);
--
2.14.3
^ permalink raw reply related
* [PATCH 4/4 v7] drm/pl111: Support handling bridge timings
From: Linus Walleij @ 2018-01-12 7:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112074854.9560-1-linus.walleij@linaro.org>
If the bridge has a too strict setup time for the incoming
signals, we may not be fast enough and then we need to
compensate by outputting the signal on the inverse clock
edge so it is for sure stable when the bridge samples it.
Since bridges in difference to panels does not expose their
connectors, make the connector optional in the display
setup code.
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
---
ChangeLog v6->v7:
- Collect Eric's ACK.
ChangeLog v5->v6:
- Collect Laurent's ACK.
ChangeLog v4->v5:
- Use the new bridge timings setup method.
---
drivers/gpu/drm/pl111/Kconfig | 1 +
drivers/gpu/drm/pl111/pl111_display.c | 35 +++++++++++++++++++++++++++++++----
drivers/gpu/drm/pl111/pl111_drv.c | 20 +++++++++++---------
3 files changed, 43 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/pl111/Kconfig b/drivers/gpu/drm/pl111/Kconfig
index e5e2abd66491..82cb3e60ddc8 100644
--- a/drivers/gpu/drm/pl111/Kconfig
+++ b/drivers/gpu/drm/pl111/Kconfig
@@ -8,6 +8,7 @@ config DRM_PL111
select DRM_GEM_CMA_HELPER
select DRM_BRIDGE
select DRM_PANEL_BRIDGE
+ select DRM_DUMB_VGA_DAC
select VT_HW_CONSOLE_BINDING if FRAMEBUFFER_CONSOLE
help
Choose this option for DRM support for the PL111 CLCD controller.
diff --git a/drivers/gpu/drm/pl111/pl111_display.c b/drivers/gpu/drm/pl111/pl111_display.c
index 06c4bf756b69..7fe4040aea46 100644
--- a/drivers/gpu/drm/pl111/pl111_display.c
+++ b/drivers/gpu/drm/pl111/pl111_display.c
@@ -94,6 +94,7 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
const struct drm_display_mode *mode = &cstate->mode;
struct drm_framebuffer *fb = plane->state->fb;
struct drm_connector *connector = priv->connector;
+ struct drm_bridge *bridge = priv->bridge;
u32 cntl;
u32 ppl, hsw, hfp, hbp;
u32 lpp, vsw, vfp, vbp;
@@ -143,11 +144,37 @@ static void pl111_display_enable(struct drm_simple_display_pipe *pipe,
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
tim2 |= TIM2_IVS;
- if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
- tim2 |= TIM2_IOE;
+ if (connector) {
+ if (connector->display_info.bus_flags & DRM_BUS_FLAG_DE_LOW)
+ tim2 |= TIM2_IOE;
- if (connector->display_info.bus_flags & DRM_BUS_FLAG_PIXDATA_NEGEDGE)
- tim2 |= TIM2_IPC;
+ if (connector->display_info.bus_flags &
+ DRM_BUS_FLAG_PIXDATA_NEGEDGE)
+ tim2 |= TIM2_IPC;
+ }
+
+ if (bridge) {
+ const struct drm_bridge_timings *btimings = bridge->timings;
+
+ /*
+ * Here is when things get really fun. Sometimes the bridge
+ * timings are such that the signal out from PL11x is not
+ * stable before the receiving bridge (such as a dumb VGA DAC
+ * or similar) samples it. If that happens, we compensate by
+ * the only method we have: output the data on the opposite
+ * edge of the clock so it is for sure stable when it gets
+ * sampled.
+ *
+ * The PL111 manual does not contain proper timining diagrams
+ * or data for these details, but we know from experiments
+ * that the setup time is more than 3000 picoseconds (3 ns).
+ * If we have a bridge that requires the signal to be stable
+ * earlier than 3000 ps before the clock pulse, we have to
+ * output the data on the opposite edge to avoid flicker.
+ */
+ if (btimings && btimings->setup_time_ps >= 3000)
+ tim2 ^= TIM2_IPC;
+ }
tim2 |= cpl << 16;
writel(tim2, priv->regs + CLCD_TIM2);
diff --git a/drivers/gpu/drm/pl111/pl111_drv.c b/drivers/gpu/drm/pl111/pl111_drv.c
index 201d57d5cb54..101a9c7db6ff 100644
--- a/drivers/gpu/drm/pl111/pl111_drv.c
+++ b/drivers/gpu/drm/pl111/pl111_drv.c
@@ -107,11 +107,17 @@ static int pl111_modeset_init(struct drm_device *dev)
ret = PTR_ERR(bridge);
goto out_config;
}
- /*
- * TODO: when we are using a different bridge than a panel
- * (such as a dumb VGA connector) we need to devise a different
- * method to get the connector out of the bridge.
- */
+ } else if (bridge) {
+ dev_info(dev->dev, "Using non-panel bridge\n");
+ } else {
+ dev_err(dev->dev, "No bridge, exiting\n");
+ return -ENODEV;
+ }
+
+ priv->bridge = bridge;
+ if (panel) {
+ priv->panel = panel;
+ priv->connector = panel->connector;
}
ret = pl111_display_init(dev);
@@ -125,10 +131,6 @@ static int pl111_modeset_init(struct drm_device *dev)
if (ret)
return ret;
- priv->bridge = bridge;
- priv->panel = panel;
- priv->connector = panel->connector;
-
ret = drm_vblank_init(dev, 1);
if (ret != 0) {
dev_err(dev->dev, "Failed to init vblank\n");
--
2.14.3
^ permalink raw reply related
* [PATCH v4] perf tools: Add ARM Statistical Profiling Extensions (SPE) support
From: gengdongjiu @ 2018-01-12 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <0a07a10c-fc0c-3f97-ac01-59429aab0937@intel.com>
On 2018/1/11 22:17, Adrian Hunter wrote:
>> (e.g., via 'perf inject --itrace'), are also not supported
>>
>> - technically both cs-etm and spe can be used simultaneously, however
>> disabled for simplicity in this release
>>
>> Signed-off-by: Kim Phillips <kim.phillips@arm.com>
> For what is there now, it looks fine from the auxtrace point of view. There
> are a couple of minor points below but nevertheless:
>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
This patch is good to me.
Reviewed-by: gengdongjiu at huawei.com
>
>> ---
>> v4: rebased onto acme's perf/core, whitespace fixes.
^ permalink raw reply
* [PATCH net-next v5 0/4] net: mvpp2: 1000BaseX and 2500BaseX support
From: Antoine Tenart @ 2018-01-12 7:51 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
This series adds 1000BaseX and 2500BaseX support to the Marvell PPv2
driver. In order to use it, the 2.5 SGMII mode is added in the Marvell
common PHY driver (cp110-comphy).
This was tested on a mcbin.
All patches should probably go through net-next as patch 4/4 depends on
patch 1/4 to build and work.
Please note the two mvpp2 patches do not conflict with the ACPI series
v2 Marcin sent a few days ago, and the two series can be processed in
parallel. (Marcin is aware of me sending this series).
Thanks!
Antoine
Since v4:
- Fixed a compilation warning which was a real error in the code.
Since v3:
- Stopped setting the MII_SPEED bit in the GMAC AN register, as the
GMII_SPEED bit takes over anyway.
- Added Andrew's Reviewed-by on patch 4/4.
Since v2:
- Added a comment before mvpp22_comphy_init() about the different PHY modes
used and why they differ between the PPv2 driver and the COMPHY one.
Since v1:
- s/PHY_MODE_SGMII_2_5G/PHY_MODE_2500SGMII/
- Fixed a build error in 'net: mvpp2: 1000baseX support' (which was solved in
the 2500baseX support one, but the bisection was broken).
- Removed the dt patches, as the fourth network interface on the mcbin also
needs PHYLINK support in the PPv2 driver to be correctly supported.
Antoine Tenart (4):
phy: add 2.5G SGMII mode to the phy_mode enum
phy: cp110-comphy: 2.5G SGMII mode
net: mvpp2: 1000baseX support
net: mvpp2: 2500baseX support
drivers/net/ethernet/marvell/mvpp2.c | 74 ++++++++++++++++++++++++----
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 +++++--
include/linux/phy/phy.h | 1 +
3 files changed, 79 insertions(+), 13 deletions(-)
--
2.14.3
^ permalink raw reply
* [PATCH net-next v5 1/4] phy: add 2.5G SGMII mode to the phy_mode enum
From: Antoine Tenart @ 2018-01-12 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112075130.30890-1-antoine.tenart@free-electrons.com>
This patch adds one more generic PHY mode to the phy_mode enum, to allow
configuring generic PHYs to the 2.5G SGMII mode by using the set_mode
callback.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
include/linux/phy/phy.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 4f8423a948d5..5a80e9de3686 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -28,6 +28,7 @@ enum phy_mode {
PHY_MODE_USB_DEVICE,
PHY_MODE_USB_OTG,
PHY_MODE_SGMII,
+ PHY_MODE_2500SGMII,
PHY_MODE_10GKR,
PHY_MODE_UFS_HS_A,
PHY_MODE_UFS_HS_B,
--
2.14.3
^ permalink raw reply related
* [PATCH net-next v5 2/4] phy: cp110-comphy: 2.5G SGMII mode
From: Antoine Tenart @ 2018-01-12 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112075130.30890-1-antoine.tenart@free-electrons.com>
This patch allow the CP100 comphy to configure some lanes in the
2.5G SGMII mode. This mode is quite close to SGMII and uses nearly the
same code path.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/phy/marvell/phy-mvebu-cp110-comphy.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
index a0d522154cdf..4ef429250d7b 100644
--- a/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
+++ b/drivers/phy/marvell/phy-mvebu-cp110-comphy.c
@@ -135,19 +135,25 @@ struct mvebu_comhy_conf {
static const struct mvebu_comhy_conf mvebu_comphy_cp110_modes[] = {
/* lane 0 */
MVEBU_COMPHY_CONF(0, 1, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(0, 1, PHY_MODE_2500SGMII, 0x1),
/* lane 1 */
MVEBU_COMPHY_CONF(1, 2, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(1, 2, PHY_MODE_2500SGMII, 0x1),
/* lane 2 */
MVEBU_COMPHY_CONF(2, 0, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(2, 0, PHY_MODE_2500SGMII, 0x1),
MVEBU_COMPHY_CONF(2, 0, PHY_MODE_10GKR, 0x1),
/* lane 3 */
MVEBU_COMPHY_CONF(3, 1, PHY_MODE_SGMII, 0x2),
+ MVEBU_COMPHY_CONF(3, 1, PHY_MODE_2500SGMII, 0x2),
/* lane 4 */
MVEBU_COMPHY_CONF(4, 0, PHY_MODE_SGMII, 0x2),
+ MVEBU_COMPHY_CONF(4, 0, PHY_MODE_2500SGMII, 0x2),
MVEBU_COMPHY_CONF(4, 0, PHY_MODE_10GKR, 0x2),
MVEBU_COMPHY_CONF(4, 1, PHY_MODE_SGMII, 0x1),
/* lane 5 */
MVEBU_COMPHY_CONF(5, 2, PHY_MODE_SGMII, 0x1),
+ MVEBU_COMPHY_CONF(5, 2, PHY_MODE_2500SGMII, 0x1),
};
struct mvebu_comphy_priv {
@@ -206,6 +212,10 @@ static void mvebu_comphy_ethernet_init_reset(struct mvebu_comphy_lane *lane,
if (mode == PHY_MODE_10GKR)
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0xe) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0xe);
+ else if (mode == PHY_MODE_2500SGMII)
+ val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x8) |
+ MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x8) |
+ MVEBU_COMPHY_SERDES_CFG0_HALF_BUS;
else if (mode == PHY_MODE_SGMII)
val |= MVEBU_COMPHY_SERDES_CFG0_GEN_RX(0x6) |
MVEBU_COMPHY_SERDES_CFG0_GEN_TX(0x6) |
@@ -296,13 +306,13 @@ static int mvebu_comphy_init_plls(struct mvebu_comphy_lane *lane,
return 0;
}
-static int mvebu_comphy_set_mode_sgmii(struct phy *phy)
+static int mvebu_comphy_set_mode_sgmii(struct phy *phy, enum phy_mode mode)
{
struct mvebu_comphy_lane *lane = phy_get_drvdata(phy);
struct mvebu_comphy_priv *priv = lane->priv;
u32 val;
- mvebu_comphy_ethernet_init_reset(lane, PHY_MODE_SGMII);
+ mvebu_comphy_ethernet_init_reset(lane, mode);
val = readl(priv->base + MVEBU_COMPHY_RX_CTRL1(lane->id));
val &= ~MVEBU_COMPHY_RX_CTRL1_CLK8T_EN;
@@ -487,7 +497,8 @@ static int mvebu_comphy_power_on(struct phy *phy)
switch (lane->mode) {
case PHY_MODE_SGMII:
- ret = mvebu_comphy_set_mode_sgmii(phy);
+ case PHY_MODE_2500SGMII:
+ ret = mvebu_comphy_set_mode_sgmii(phy, lane->mode);
break;
case PHY_MODE_10GKR:
ret = mvebu_comphy_set_mode_10gkr(phy);
--
2.14.3
^ permalink raw reply related
* [PATCH net-next v5 3/4] net: mvpp2: 1000baseX support
From: Antoine Tenart @ 2018-01-12 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112075130.30890-1-antoine.tenart@free-electrons.com>
This patch adds the 1000Base-X PHY mode support in the Marvell PPv2
driver. 1000Base-X is quite close the SGMII and uses nearly the same
code path.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
---
drivers/net/ethernet/marvell/mvpp2.c | 45 ++++++++++++++++++++++++++++--------
1 file changed, 35 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index a19760736b71..257a6b99b4ca 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -4501,6 +4501,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
mvpp22_gop_init_rgmii(port);
break;
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
mvpp22_gop_init_sgmii(port);
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4538,7 +4539,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
u32 val;
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
/* Enable the GMAC link status irq for this port */
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
@@ -4568,7 +4570,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
}
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
@@ -4580,7 +4583,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
u32 val;
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_MASK);
val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_MASK);
@@ -4605,6 +4609,7 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
switch (port->phy_interface) {
case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_1000BASEX:
mode = PHY_MODE_SGMII;
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4625,7 +4630,8 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
{
u32 val;
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |
MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
@@ -4640,9 +4646,11 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
writel(val, port->base + MVPP22_GMAC_CTRL_4_REG);
}
- /* The port is connected to a copper PHY */
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
- val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
+ if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ val |= MVPP2_GMAC_PORT_TYPE_MASK;
+ else
+ val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
val = readl(port->base + MVPP2_GMAC_AUTONEG_CONFIG);
@@ -4651,6 +4659,19 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
MVPP2_GMAC_AN_DUPLEX_EN;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
val |= MVPP2_GMAC_IN_BAND_AUTONEG;
+
+ if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ /* 1000BaseX port cannot negotiate speed nor can it
+ * negotiate duplex: they are always operating with a
+ * fixed speed of 1000Mbps in full duplex, so force
+ * 1000 speed and full duplex here.
+ */
+ val |= MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_FULL_DUPLEX;
+ else
+ val |= MVPP2_GMAC_AN_SPEED_EN |
+ MVPP2_GMAC_AN_DUPLEX_EN;
+
writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
}
@@ -4671,7 +4692,8 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
/* Configure the PCS and in-band AN */
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
@@ -4733,7 +4755,8 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
mvpp22_port_mii_set(port);
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
mvpp2_port_mii_gmac_configure(port);
else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
mvpp2_port_mii_xlg_configure(port);
@@ -4810,7 +4833,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port)
else
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -6023,7 +6047,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
link = true;
}
} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
- port->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_STAT);
if (val & MVPP22_GMAC_INT_STAT_LINK) {
event = true;
--
2.14.3
^ permalink raw reply related
* [PATCH net-next v5 4/4] net: mvpp2: 2500baseX support
From: Antoine Tenart @ 2018-01-12 7:51 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112075130.30890-1-antoine.tenart@free-electrons.com>
This patch adds the 2500Base-X PHY mode support in the Marvell PPv2
driver. 2500Base-X is quite close to 1000Base-X and SGMII modes and uses
nearly the same code path.
Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/ethernet/marvell/mvpp2.c | 49 ++++++++++++++++++++++++++++--------
1 file changed, 39 insertions(+), 10 deletions(-)
diff --git a/drivers/net/ethernet/marvell/mvpp2.c b/drivers/net/ethernet/marvell/mvpp2.c
index 257a6b99b4ca..38f9a79481c6 100644
--- a/drivers/net/ethernet/marvell/mvpp2.c
+++ b/drivers/net/ethernet/marvell/mvpp2.c
@@ -4502,6 +4502,7 @@ static int mvpp22_gop_init(struct mvpp2_port *port)
break;
case PHY_INTERFACE_MODE_SGMII:
case PHY_INTERFACE_MODE_1000BASEX:
+ case PHY_INTERFACE_MODE_2500BASEX:
mvpp22_gop_init_sgmii(port);
break;
case PHY_INTERFACE_MODE_10GKR:
@@ -4540,7 +4541,8 @@ static void mvpp22_gop_unmask_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
/* Enable the GMAC link status irq for this port */
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val |= MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
@@ -4571,7 +4573,8 @@ static void mvpp22_gop_mask_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_SUM_MASK);
val &= ~MVPP22_GMAC_INT_SUM_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_SUM_MASK);
@@ -4584,7 +4587,8 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_MASK);
val |= MVPP22_GMAC_INT_MASK_LINK_STAT;
writel(val, port->base + MVPP22_GMAC_INT_MASK);
@@ -4599,6 +4603,16 @@ static void mvpp22_gop_setup_irq(struct mvpp2_port *port)
mvpp22_gop_unmask_irq(port);
}
+/* Sets the PHY mode of the COMPHY (which configures the serdes lanes).
+ *
+ * The PHY mode used by the PPv2 driver comes from the network subsystem, while
+ * the one given to the COMPHY comes from the generic PHY subsystem. Hence they
+ * differ.
+ *
+ * The COMPHY configures the serdes lanes regardless of the actual use of the
+ * lanes by the physical layer. This is why configurations like
+ * "PPv2 (2500BaseX) - COMPHY (2500SGMII)" are valid.
+ */
static int mvpp22_comphy_init(struct mvpp2_port *port)
{
enum phy_mode mode;
@@ -4612,6 +4626,9 @@ static int mvpp22_comphy_init(struct mvpp2_port *port)
case PHY_INTERFACE_MODE_1000BASEX:
mode = PHY_MODE_SGMII;
break;
+ case PHY_INTERFACE_MODE_2500BASEX:
+ mode = PHY_MODE_2500SGMII;
+ break;
case PHY_INTERFACE_MODE_10GKR:
mode = PHY_MODE_10GKR;
break;
@@ -4631,7 +4648,8 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
u32 val;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_CTRL_4_REG);
val |= MVPP22_CTRL4_SYNC_BYPASS_DIS | MVPP22_CTRL4_DP_CLK_SEL |
MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE;
@@ -4647,7 +4665,8 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
}
val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
- if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PORT_TYPE_MASK;
else
val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
@@ -4660,7 +4679,13 @@ static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
val |= MVPP2_GMAC_IN_BAND_AUTONEG;
- if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ /* Clear all fields we may want to explicitly set below */
+ val &= ~(MVPP2_GMAC_CONFIG_FULL_DUPLEX | MVPP2_GMAC_CONFIG_GMII_SPEED |
+ MVPP2_GMAC_CONFIG_MII_SPEED | MVPP2_GMAC_AN_SPEED_EN |
+ MVPP2_GMAC_AN_DUPLEX_EN);
+
+ if (port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
/* 1000BaseX port cannot negotiate speed nor can it
* negotiate duplex: they are always operating with a
* fixed speed of 1000Mbps in full duplex, so force
@@ -4693,7 +4718,8 @@ static void mvpp2_port_mii_gmac_configure(struct mvpp2_port *port)
/* Configure the PCS and in-band AN */
val = readl(port->base + MVPP2_GMAC_CTRL_2_REG);
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val |= MVPP2_GMAC_INBAND_AN_MASK | MVPP2_GMAC_PCS_ENABLE_MASK;
} else if (phy_interface_mode_is_rgmii(port->phy_interface)) {
val &= ~MVPP2_GMAC_PCS_ENABLE_MASK;
@@ -4756,7 +4782,8 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
mvpp2_port_mii_gmac_configure(port);
else if (port->phy_interface == PHY_INTERFACE_MODE_10GKR)
mvpp2_port_mii_xlg_configure(port);
@@ -4834,7 +4861,8 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port)
val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX)
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
val |= MVPP2_GMAC_PCS_LB_EN_MASK;
else
val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
@@ -6048,7 +6076,8 @@ static irqreturn_t mvpp2_link_status_isr(int irq, void *dev_id)
}
} else if (phy_interface_mode_is_rgmii(port->phy_interface) ||
port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
- port->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX) {
val = readl(port->base + MVPP22_GMAC_INT_STAT);
if (val & MVPP22_GMAC_INT_STAT_LINK) {
event = true;
--
2.14.3
^ permalink raw reply related
* [PATCH] usb: dwc2: Fix endless deferral probe
From: Stefan Wahren @ 2018-01-12 8:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAK8P3a3GdHvBBPR3D_qO5+Zjr1CUBMLOAvjTiMQEMO1NtKjb3w@mail.gmail.com>
Am 12.01.2018 um 00:32 schrieb Arnd Bergmann:
> On Wed, Jan 10, 2018 at 1:15 PM, Stefan Wahren <stefan.wahren@i2se.com> wrote:
>> Hi Arnd,
>>
>>
>> Am 09.01.2018 um 22:33 schrieb Arnd Bergmann:
>>> On Tue, Jan 9, 2018 at 8:28 PM, Stefan Wahren <stefan.wahren@i2se.com>
>>> wrote:
>>>> The dwc2 USB driver tries to find a generic PHY first and then look
>>>> for an old style USB PHY. In case of a valid generic PHY node without
>>>> a PHY driver, the PHY layer will return -EPROBE_DEFER forever. So dwc2
>>>> will never tries for an USB PHY.
>>>>
>>>> Fix this issue by finding a generic PHY and an old style USB PHY
>>>> at once.
>>> This would fix only one of the USB controllers (dwc2), but not the others
>>> that are affected. As I wrote in my suggested patch, dwc3 appears to be
>>> affected the same way, and all other host drivers that call usb_add_hcd()
>>> without first setting hcd->phy would suffer from this as well.
>>>
>>> If we go down the route of addressing it here in the hcd drivers, we
>>> should
>>> at least change all three of those, and hope this doesn't regress in
>>> another way.
>>>
>>> Arnd
>>
>> i fully unterstand. But we leaving the path of "fixing a critical issue on
>> BCM2835" and go to "fixing multiple USB host controller". I do this all in
>> my spare time and don't have any of the other USB controller available. So
>> before i proceed with any other patch i like so see some feedback from John,
>> Greg or Felipe.
>>
>> After finalizing this patch i think the chance is little that this would be
>> applied to 4.15. So i seems to me that we still revert my DT clean up patch.
> Could you confirm that this simpler patch fixes the problem for you?
> My feeling right now is that this would be the least invasive variant.
> This is obviously a critical regression for BCM2835, but I'm fairly sure
> it's just as critical for a lot of other SoCs that haven't done as much
> testing on linux-next.
Even worse arm64 and mips could be affected, too.
>
> Hans has already verified the earlier (more complex) version, but my
> analysis today has made it very likely that this one is fully sufficient
> to fix all affected platforms.
>
> Reverting all nine patches that add #phy-cells would still be an option,
> but seems way more invasive at this point.
>
> Arnd
>
> diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
> index b4964b067aec..93b55fb71d54 100644
> --- a/drivers/phy/phy-core.c
> +++ b/drivers/phy/phy-core.c
> @@ -410,6 +410,10 @@ static struct phy *_of_phy_get(struct device_node
> *np, int index)
> if (ret)
> return ERR_PTR(-ENODEV);
>
> + /* This phy type handled by the usb-phy subsystem for now */
> + if (of_device_is_compatible(np, "usb-nop-xceiv"))
> + return ERR_PTR(-ENODEV);
> +
> mutex_lock(&phy_provider_mutex);
> phy_provider = of_phy_provider_lookup(args.np);
> if (IS_ERR(phy_provider) || !try_module_get(phy_provider->owner)) {
I tried this, but it doesn't work. "np" is the node of the USB
controller, not of the phy?
^ permalink raw reply
* [PATCH v3 0/7] Marvell NAND controller rework with ->exec_op()
From: Robert Jarzmik @ 2018-01-12 8:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180111232417.4aa86075@xps13>
Miquel RAYNAL <miquel.raynal@free-electrons.com> writes:
I begun all your test procedure (on my zylonite board).
The timing registers are the same in both pxa3xx_nand and marvell_nand, ie :
[ 3.085539] Timing registers from Bootloader:
[ 3.089971] - NDTR0: 0x00161c1c
[ 3.095979] - NDTR1: 0x0f3c00a2
I can attach the dmesg of the first run (dump of OOB). Yet I think you're
missing the point as to where the bug lies.
In the zylonite setup, the BBT is _not_ in the OOB of each block. Instead, it
lies at the end of the NAND, in the last blocks (see struct
nand_bbt_descr). Reading each block and declaring it as bad as is done in
marvell_nand (at least that is my understanding of your traces), but it is not
what should be done if a match is found for the bbt_pattern. Instead, the BBT
should be loaded from the last 8 blocks of the NAND, ie. page 130944 and page
131008 in my setup.
Therefore, I would rather think that marvell-nand is not using the BBT at the
end of the nand rather than misconfiguring the timing registers.
Cheers.
--
Robert
PS: You really should expunge the mailing recipients a bit ...
[1] DMesg extract
netconsole: port not set
netconsole: registered as netconsole-1
smc91c111 smc91c1110: chip is revision= 9, version= 2
mdio_bus: miibus0: probed
eth0: got preset MAC address: 00:0e:0c:a7:26:f7
nand: NAND device: Manufacturer ID: 0x20, Chip ID: 0xba (ST Micro NAND 256MiB 1,8V 16-bit), 256MiB, page size: 2048, OOB size: 64
mrvl_nand mrvl_nand0: ECC strength 1, ECC step size 512
Bad block table found at page 131008, version 0x04
Bad block table found at page 130944, version 0x04
malloc space: 0x83700000 -> 0x83efffff (size 8 MiB)
running /env/bin/init...
magicvar: No such file or directory
magicvar: No such file or directory
magicvar: No such file or directory
Hit any key to stop autoboot: 3\b\b 2\b\b 1\b\b 0
booting net
netconsole: netconsole initialized with 255.255.255.255:6662
eth0: 100Mbps full duplex link detected
DHCP client bound to address 192.168.1.232
netconsole: netconsole initialized with 255.255.255.255:6662
could not open /mnt/tftp/none-linux-zylonite: No such file or directory
Booting net failed: No such file or directory
booting net failed: No such file or directory
boot: No such file or directory
.[1;32mbarebox at .[1;36mZylonite:/.[0m global linux.bootargs.debug=earlycon
.[1;32mbarebox at .[1;36mZylonite:/.[0m bootm /mnt/tftp/zImage_jenkins
Loading ARM Linux zImage '/mnt/tftp/zImage_jenkins'
commandline: ram=64M console=ttyS0,115200 ip=dhcp root=/dev/nfs nfsroot=/home/none/nfsroot/zylonite,v3,tcp earlycon mtdparts=pxa3xx_nand-0:128k at 0(TIMH)ro,128k at 128k(OBMI)ro,768k at 256k(barebox),256k at 1024k(barebox-env),12M at 1280k(kernel),38016k at 13568k(root)
arch_number: 1233
Uncompressing Linux... done, booting the kernel.
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.15.0-rc1-00047-g3085f79 (jenkins at belgarath) (gcc version 4.8.3 20140320 (prerelease) (Sourcery CodeBench Lite 2014.05-29)) #889 PREEMPT Fri Jan 12 08:26:17 CET 2018
[ 0.000000] CPU: XScale-V3 based processor [69056891] revision 1 (ARMv5TE), cr=0000397f
[ 0.000000] CPU: VIVT data cache, VIVT instruction cache
[ 0.000000] Machine: PXA3xx Platform Development Kit (aka Zylonite)
[ 0.000000] Ignoring tag cmdline (using the default kernel command line)
[ 0.000000] Memory policy: Data cache writeback
[ 0.000000] RO Mode clock: 0.00MHz
[ 0.000000] Run Mode clock: 0.00MHz
[ 0.000000] Turbo Mode clock: 0.00MHz
[ 0.000000] System bus clock: 0.00MHz
[ 0.000000] On node 0 totalpages: 16384
[ 0.000000] Normal zone: 128 pages used for memmap
[ 0.000000] Normal zone: 0 pages reserved
[ 0.000000] Normal zone: 16384 pages, LIFO batch:3
[ 0.000000] random: fast init done
[ 0.000000] pcpu-alloc: s0 r0 d32768 u32768 alloc=1*32768
[ 0.000000] pcpu-alloc: [0] 0
[ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 16256
[ 0.000000] Kernel command line: root=/dev/ram0 ip=192.168.1.232:192.168.1.5::255.255.255.0::eth0:on console=ttyS0,115200 mem=64M mtdparts=pxa3xx_nand-0:128k at 0(TIMH)ro,128k at 128k(OBMI)ro,768k at 256k(barebox),256k at 1024k(barebox-env),12M at 1280k(kernel),38016k at 13568k(root) ubi.mtd=5 earlycon=pxa,io,0xf6200000,115200n8 debug no_console_suspend
[ 0.000000] Dentry cache hash table entries: 8192 (order: 3, 32768 bytes)
[ 0.000000] Inode-cache hash table entries: 4096 (order: 2, 16384 bytes)
[ 0.000000] Memory: 56856K/65536K available (4226K kernel code, 202K rwdata, 972K rodata, 2396K init, 102K bss, 8680K reserved, 0K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB)
[ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB)
[ 0.000000] vmalloc : 0xc4800000 - 0xff800000 ( 944 MB)
[ 0.000000] lowmem : 0xc0000000 - 0xc4000000 ( 64 MB)
[ 0.000000] modules : 0xbf000000 - 0xc0000000 ( 16 MB)
[ 0.000000] .text : 0xc0008000 - 0xc0428a48 (4227 kB)
[ 0.000000] .init : 0xc053f000 - 0xc0796000 (2396 kB)
[ 0.000000] .data : 0xc0796000 - 0xc07c8bec ( 203 kB)
[ 0.000000] .bss : 0xc07c8bec - 0xc07e25fc ( 103 kB)
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Tasks RCU enabled.
[ 0.000000] NR_IRQS: 16, nr_irqs: 336, preallocated irqs: 336
[ 0.000000] RJK: parent_rate=13000000, xl=8, xn=1
[ 0.000070] sched_clock: 32 bits at 3250kHz, resolution 307ns, wraps every 660764198758ns
[ 0.000266] clocksource: oscr0: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 588080137591 ns
[ 0.002134] Console: colour dummy device 80x30
[ 0.002294] Calibrating delay loop... 103.83 BogoMIPS (lpj=519168)
[ 0.081019] pid_max: default: 32768 minimum: 301
[ 0.081862] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.081960] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.085156] CPU: Testing write buffer coherency: ok
[ 0.088957] Setting up static identity map for 0x80008200 - 0x80008260
[ 0.089916] Hierarchical SRCU implementation.
[ 0.102924] devtmpfs: initialized
[ 0.113807] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
[ 0.113948] futex hash table entries: 256 (order: -1, 3072 bytes)
[ 0.116278] NET: Registered protocol family 16
[ 0.119090] DMA: preallocated 256 KiB pool for atomic coherent allocations
[ 0.389530] Advanced Linux Sound Architecture Driver Initialized.
[ 0.400350] clocksource: Switched to clocksource oscr0
[ 0.553012] NET: Registered protocol family 2
[ 0.558410] TCP established hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.558634] TCP bind hash table entries: 1024 (order: 0, 4096 bytes)
[ 0.558815] TCP: Hash tables configured (established 1024 bind 1024)
[ 0.559367] UDP hash table entries: 256 (order: 0, 4096 bytes)
[ 0.559547] UDP-Lite hash table entries: 256 (order: 0, 4096 bytes)
[ 0.561234] NET: Registered protocol family 1
[ 0.563263] RPC: Registered named UNIX socket transport module.
[ 0.563363] RPC: Registered udp transport module.
[ 0.563418] RPC: Registered tcp transport module.
[ 0.563475] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 2.498791] Initialise system trusted keyrings
[ 2.501003] workingset: timestamp_bits=30 max_order=14 bucket_order=0
[ 2.504911] NFS: Registering the id_resolver key type
[ 2.505141] Key type id_resolver registered
[ 2.505204] Key type id_legacy registered
[ 2.511301] Key type asymmetric registered
[ 2.511404] Asymmetric key parser 'x509' registered
[ 2.511567] io scheduler noop registered
[ 2.511632] io scheduler deadline registered
[ 2.512023] io scheduler cfq registered (default)
[ 2.512092] io scheduler mq-deadline registered
[ 2.512155] io scheduler kyber registered
[ 2.569944] pxa-dma pxa-dma.0: initialized 32 channels on 100 requestors
[ 2.575695] pxa2xx-uart.0: ttyS0 at MMIO 0x40100000 (irq = 38, base_baud = 928571) is a UART1
[ 3.050762] console [ttyS0] enabled
[ 3.057118] pxa2xx-uart.1: ttyS1 at MMIO 0x40200000 (irq = 37, base_baud = 928571) is a UART2
[ 3.069632] pxa2xx-uart.2: ttyS2 at MMIO 0x40700000 (irq = 36, base_baud = 928571) is a UART3
[ 3.085539] Timing registers from Bootloader:
[ 3.089971] - NDTR0: 0x00161c1c
[ 3.095979] - NDTR1: 0x0f3c00a2
[ 3.099319] nand: executing subop:
[ 3.103209] nand: ->CMD [0xff]
[ 3.107105] nand: ->WAITRDY [max 250 ms]
[ 3.111915] marvell-nfc pxa3xx-nand:
[ 3.111915] NDCR: 0x90071fff
[ 3.111915] NDCB0: 0x00a000ff
[ 3.111915] NDCB1: 0x00000000
[ 3.111915] NDCB2: 0x00000000
[ 3.111915] NDCB3: 0x00000000
[ 3.131170] nand: executing subop:
[ 3.134638] nand: ->CMD [0x90]
[ 3.138513] nand: ->ADDR [1 cyc: 00]
[ 3.143174] nand: ->DATA_IN [2 B, force 8-bit]
[ 3.148182] marvell-nfc pxa3xx-nand:
[ 3.148182] NDCR: 0x90071fff
[ 3.148182] NDCB0: 0x00610090
[ 3.148182] NDCB1: 0x00000000
[ 3.148182] NDCB2: 0x00000000
[ 3.148182] NDCB3: 0x00000000
[ 3.167016] nand: executing subop:
[ 3.170656] nand: ->CMD [0x90]
[ 3.174543] nand: ->ADDR [1 cyc: 00]
[ 3.178842] nand: ->DATA_IN [8 B, force 8-bit]
[ 3.183955] marvell-nfc pxa3xx-nand:
[ 3.183955] NDCR: 0x90071fff
[ 3.183955] NDCB0: 0x00610090
[ 3.183955] NDCB1: 0x00000000
[ 3.183955] NDCB2: 0x00000000
[ 3.183955] NDCB3: 0x00000000
[ 3.202627] nand: executing subop:
[ 3.206083] nand: ->CMD [0x90]
[ 3.209958] nand: ->ADDR [1 cyc: 20]
[ 3.214403] nand: ->DATA_IN [4 B, force 8-bit]
[ 3.219383] marvell-nfc pxa3xx-nand:
[ 3.219383] NDCR: 0x90071fff
[ 3.219383] NDCB0: 0x00610090
[ 3.219383] NDCB1: 0x00000020
[ 3.219383] NDCB2: 0x00000000
[ 3.219383] NDCB3: 0x00000000
[ 3.238001] nand: executing subop:
[ 3.241598] nand: ->CMD [0x90]
[ 3.245491] nand: ->ADDR [1 cyc: 40]
[ 3.249790] nand: ->DATA_IN [5 B, force 8-bit]
[ 3.254897] marvell-nfc pxa3xx-nand:
[ 3.254897] NDCR: 0x90071fff
[ 3.254897] NDCB0: 0x00610090
[ 3.254897] NDCB1: 0x00000040
[ 3.254897] NDCB2: 0x00000000
[ 3.254897] NDCB3: 0x00000000
[ 3.273547] nand: device found, Manufacturer ID: 0x20, Chip ID: 0xba
[ 3.279923] nand: ST Micro NAND 256MiB 1,8V 16-bit
[ 3.284893] nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
[ 3.292633] marvell-nfc pxa3xx-nand: No minimum ECC strength, using 1b/512B
[ 3.299666] Scanning device for bad blocks
[ 3.303978] nand: nand_do_read_oob: from = 0x00000000, len = 64
[ 3.310000] marvell-nfc pxa3xx-nand:
[ 3.310000] NDCR: 0x9d079fff
[ 3.310000] NDCB0: 0x000d3000
[ 3.310000] NDCB1: 0x00000000
[ 3.310000] NDCB2: 0x00000000
[ 3.310000] NDCB3: 0x00000000
[ 3.329036] OOB from page 0:
[ 3.332122] 00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 3.342950] 01: 00 00 00 00 00 00 00 00 d4 eb 0b f5 fa 02 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 3.353817] Bad eraseblock 0 at 0x000000000000
[ 3.358338] nand: nand_do_read_oob: from = 0x00020000, len = 64
[ 3.364494] marvell-nfc pxa3xx-nand:
[ 3.364494] NDCR: 0x9d079fff
[ 3.364494] NDCB0: 0x000d3000
[ 3.364494] NDCB1: 0x00400000
[ 3.364494] NDCB2: 0x00000000
[ 3.364494] NDCB3: 0x00000000
[ 3.383344] OOB from page 64:
[ 3.386353] 00: ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff
[ 3.397213] 01: ff ff ff ff ff ff ff ff dc 1e ef 48 38 04 e6 95 40 86 da 0f b6 fd 95 6d 7f 05 2d cf fd 61 d9 05
[ 3.408131] nand: nand_do_read_oob: from = 0x00040000, len = 64
[ 3.414298] marvell-nfc pxa3xx-nand:
[ 3.414298] NDCR: 0x9d079fff
[ 3.414298] NDCB0: 0x000d3000
[ 3.414298] NDCB1: 0x00800000
[ 3.414298] NDCB2: 0x00000000
[ 3.414298] NDCB3: 0x00000000
[ 3.433140] OOB from page 128:
[ 3.436237] 00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 3.447080] 01: 00 00 00 00 00 00 00 00 48 5b 01 d2 56 00 a2 ec 23 82 51 02 ef af 9d ae 3e 02 34 82 6c d8 75 0e
[ 3.457961] Bad eraseblock 2 at 0x000000040000
[ 3.462604] nand: nand_do_read_oob: from = 0x00060000, len = 64
[ 3.468627] marvell-nfc pxa3xx-nand:
[ 3.468627] NDCR: 0x9d079fff
[ 3.468627] NDCB0: 0x000d3000
[ 3.468627] NDCB1: 0x00c00000
[ 3.468627] NDCB2: 0x00000000
[ 3.468627] NDCB3: 0x00000000
[ 3.487466] OOB from page 192:
[ 3.490706] 00: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
[ 3.501537] 01: 00 00 00 00 00 00 00 00 a7 23 9c bc 5d 02 5e 55 3b fd 7f 04 ed 35 c0 d1 a7 0a c3 94 09 cf 9a 0d
[ 3.512409] Bad eraseblock 3 at 0x000000060000
^ permalink raw reply
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