* [PATCH 00/14] Add MMCI support for STM32F SoCs family
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
From: Patrice Chotard <patrice.chotard@st.com>
This series reworks patches submitted one year ago by Andrea Merello [1]
but without succeed to merged it.
STM32F4 and STM32F7 SoCs families embeds a variant of the ARM PrimeCell
PL18x SD host controller, for which the mmci driver exists.
This series adds support for these SoCs to the mmci driver.
As other variants, this one need some specific quirks, that this
series address.
This series has been tested on following boards :
_ stm32f429-eval
_ stm32f469-disco
_ stm32f746-eval
_ stm32f769-disco
DT update for stm32f7 pinctrl, stm32f746-eval and stm32f769-disco boards
will be sent later to avoid conflict with pending stm32f7 series [1] which
is not yet merged on kernel mainline.
[1] https://www.spinics.net/lists/linux-mmc/msg41616.html
[2] https://patchwork.kernel.org/patch/10104447/
Andrea Merello (2):
ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
Patrice Chotard (12):
mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
mmc: mmci: Add support for setting pad type via pinctrl
mmc: mmci: Add STM32 variant
ARM: dts: stm32: Add SDIO controller for stm32f746
ARM: dts: stm32: Add SDIO controller for stm32f429
ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
ARM: configs: stm32: Enable MMC_ARMMMCI support
ARM: configs: stm32: Enable EXT3_FS support
clk: stm32: Add clk entry for SDMMC2 on stm32F769
gpio: stmpe: i2c transfer are forbiden in atomic context
arch/arm/boot/dts/stm32429i-eval.dts | 19 ++++++
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++
arch/arm/boot/dts/stm32f429.dtsi | 11 +++
arch/arm/boot/dts/stm32f469-disco.dts | 19 ++++++
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++
arch/arm/configs/stm32_defconfig | 3 +
arch/arm/mach-stm32/Kconfig | 3 +
drivers/clk/clk-stm32f4.c | 3 +-
drivers/gpio/gpio-stmpe.c | 20 +++---
drivers/mmc/host/mmci.c | 120 ++++++++++++++++++++++++++++-----
drivers/mmc/host/mmci.h | 6 ++
11 files changed, 231 insertions(+), 26 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH 01/14] mmc: mmci: Don't pretend all variants to have MMCIMASK1 register
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
Two mask registers are used in order to select which events have to
actually generate an interrupt on each IRQ line.
It seems that in the single-IRQ case it's assumed that the IRQs lines
are simply OR-ed, while the two mask registers are still present. The
driver still programs the two mask registers separately.
However the STM32 variant has only one IRQ, and also has only one mask
register.
This patch prepares for STM32 variant support by making the driver using
only one mask register.
This patch also optimize the MMCIMASK1 mask usage by caching it into
host->mask1_reg which avoid to read it into mmci_irq().
Tested only on STM32 variant. RFT for variants other than STM32
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 28 ++++++++++++++++++++++++----
drivers/mmc/host/mmci.h | 1 +
2 files changed, 25 insertions(+), 4 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 97da0fc..3125dc0 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -82,6 +82,7 @@
* @qcom_fifo: enables qcom specific fifo pio read logic.
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
+ * @mmcimask1: true if variant have a MMCIMASK1 register.
*/
struct variant_data {
unsigned int clkreg;
@@ -111,6 +112,7 @@ struct variant_data {
bool qcom_fifo;
bool qcom_dml;
bool reversed_irq_handling;
+ bool mmcimask1;
};
static struct variant_data variant_arm = {
@@ -120,6 +122,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.reversed_irq_handling = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -128,6 +131,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -137,6 +141,7 @@ struct variant_data {
.datalength_bits = 16,
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
+ .mmcimask1 = true,
};
static struct variant_data variant_u300 = {
@@ -152,6 +157,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_nomadik = {
@@ -168,6 +174,7 @@ struct variant_data {
.signal_direction = true,
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500 = {
@@ -190,6 +197,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_ux500v2 = {
@@ -214,6 +222,7 @@ struct variant_data {
.busy_detect_flag = MCI_ST_CARDBUSY,
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
+ .mmcimask1 = true,
};
static struct variant_data variant_qcom = {
@@ -232,6 +241,7 @@ struct variant_data {
.explicit_mclk_control = true,
.qcom_fifo = true,
.qcom_dml = true,
+ .mmcimask1 = true,
};
/* Busy detection for the ST Micro variant */
@@ -396,6 +406,7 @@ static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
{
void __iomem *base = host->base;
+ struct variant_data *variant = host->variant;
if (host->singleirq) {
unsigned int mask0 = readl(base + MMCIMASK0);
@@ -406,7 +417,10 @@ static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
writel(mask0, base + MMCIMASK0);
}
- writel(mask, base + MMCIMASK1);
+ if (variant->mmcimask1)
+ writel(mask, base + MMCIMASK1);
+
+ host->mask1_reg = mask;
}
static void mmci_stop_data(struct mmci_host *host)
@@ -1286,7 +1300,7 @@ static irqreturn_t mmci_irq(int irq, void *dev_id)
status = readl(host->base + MMCISTATUS);
if (host->singleirq) {
- if (status & readl(host->base + MMCIMASK1))
+ if (status & host->mask1_reg)
mmci_pio_irq(irq, dev_id);
status &= ~MCI_IRQ1MASK;
@@ -1729,7 +1743,10 @@ static int mmci_probe(struct amba_device *dev,
spin_lock_init(&host->lock);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
+
writel(0xfff, host->base + MMCICLEAR);
/*
@@ -1809,6 +1826,7 @@ static int mmci_remove(struct amba_device *dev)
if (mmc) {
struct mmci_host *host = mmc_priv(mmc);
+ struct variant_data *variant = host->variant;
/*
* Undo pm_runtime_put() in probe. We use the _sync
@@ -1819,7 +1837,9 @@ static int mmci_remove(struct amba_device *dev)
mmc_remove_host(mmc);
writel(0, host->base + MMCIMASK0);
- writel(0, host->base + MMCIMASK1);
+
+ if (variant->mmcimask1)
+ writel(0, host->base + MMCIMASK1);
writel(0, host->base + MMCICOMMAND);
writel(0, host->base + MMCIDATACTRL);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 4a8bef1..83160a9 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -223,6 +223,7 @@ struct mmci_host {
u32 clk_reg;
u32 datactrl_reg;
u32 busy_status;
+ u32 mask1_reg;
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
--
1.9.1
^ permalink raw reply related
* [PATCH 02/14] mmc: mmci: Don't pretend all variants to have MCI_STARBITERR flag
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
This patch prepares for supporting the STM32 variant that
has no such bit in the status register.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 16 ++++++++++++++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 3125dc0..7e56f85 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -83,6 +83,8 @@
* @qcom_dml: enables qcom specific dma glue for dma transfers.
* @reversed_irq_handling: handle data irq before cmd irq.
* @mmcimask1: true if variant have a MMCIMASK1 register.
+ * @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
+ * register.
*/
struct variant_data {
unsigned int clkreg;
@@ -113,6 +115,7 @@ struct variant_data {
bool qcom_dml;
bool reversed_irq_handling;
bool mmcimask1;
+ bool start_err;
};
static struct variant_data variant_arm = {
@@ -123,6 +126,7 @@ struct variant_data {
.f_max = 100000000,
.reversed_irq_handling = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -132,6 +136,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -142,6 +147,7 @@ struct variant_data {
.pwrreg_powerup = MCI_PWR_UP,
.f_max = 100000000,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_u300 = {
@@ -158,6 +164,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_nomadik = {
@@ -175,6 +182,7 @@ struct variant_data {
.pwrreg_clkgate = true,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500 = {
@@ -198,6 +206,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_ux500v2 = {
@@ -223,6 +232,7 @@ struct variant_data {
.busy_detect_mask = MCI_ST_BUSYENDMASK,
.pwrreg_nopower = true,
.mmcimask1 = true,
+ .start_err = true,
};
static struct variant_data variant_qcom = {
@@ -242,6 +252,7 @@ struct variant_data {
.qcom_fifo = true,
.qcom_dml = true,
.mmcimask1 = true,
+ .start_err = true,
};
/* Busy detection for the ST Micro variant */
@@ -935,8 +946,9 @@ static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
return;
/* First check for errors */
- if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_STARTBITERR|
- MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
+ if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
+ (host->variant->start_err ? MCI_STARTBITERR : 0) |
+ MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
u32 remain, success;
/* Terminate the DMA transfer */
--
1.9.1
^ permalink raw reply related
* [PATCH 03/14] mmc: mmci: Add support for setting pad type via pinctrl
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
The STM32 variant hasn't the control bit to switch pads in opendrain mode.
In this case we can achieve the same result by asking to the pinmux driver
to configure pins for us.
This patch make the mmci driver able to do this whenever needed.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 54 ++++++++++++++++++++++++++++++++++++++++---------
drivers/mmc/host/mmci.h | 5 +++++
2 files changed, 50 insertions(+), 9 deletions(-)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 7e56f85..38e8c20 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -85,6 +85,8 @@
* @mmcimask1: true if variant have a MMCIMASK1 register.
* @start_err: true is the variant has STARTBITERR bit inside MMCISTATUS
* register.
+ * @opendrain: true if variant have dedicated bit for opendrain pins
+ * configuration.
*/
struct variant_data {
unsigned int clkreg;
@@ -116,6 +118,7 @@ struct variant_data {
bool reversed_irq_handling;
bool mmcimask1;
bool start_err;
+ bool opendrain;
};
static struct variant_data variant_arm = {
@@ -127,6 +130,7 @@ struct variant_data {
.reversed_irq_handling = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo = {
@@ -137,6 +141,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_arm_extended_fifo_hwfc = {
@@ -148,6 +153,7 @@ struct variant_data {
.f_max = 100000000,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_u300 = {
@@ -165,6 +171,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_nomadik = {
@@ -183,6 +190,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500 = {
@@ -207,6 +215,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_ux500v2 = {
@@ -233,6 +242,7 @@ struct variant_data {
.pwrreg_nopower = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
static struct variant_data variant_qcom = {
@@ -253,6 +263,7 @@ struct variant_data {
.qcom_dml = true,
.mmcimask1 = true,
.start_err = true,
+ .opendrain = true,
};
/* Busy detection for the ST Micro variant */
@@ -1394,9 +1405,11 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct mmci_host *host = mmc_priv(mmc);
struct variant_data *variant = host->variant;
+ struct pinctrl_state *pins;
u32 pwr = 0;
unsigned long flags;
int ret;
+ bool is_opendrain;
if (host->plat->ios_handler &&
host->plat->ios_handler(mmc_dev(mmc), ios))
@@ -1455,16 +1468,31 @@ static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
~MCI_ST_DATA2DIREN);
}
- if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
- if (host->hw_designer != AMBA_VENDOR_ST)
- pwr |= MCI_ROD;
- else {
- /*
- * The ST Micro variant use the ROD bit for something
- * else and only has OD (Open Drain).
- */
- pwr |= MCI_OD;
+ if (host->variant->opendrain) {
+ if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) {
+ if (host->hw_designer != AMBA_VENDOR_ST) {
+ pwr |= MCI_ROD;
+ } else {
+ /*
+ * The ST Micro variant use the ROD bit for
+ * something else and only has OD (Open Drain).
+ */
+ pwr |= MCI_OD;
+ }
}
+ } else {
+ /*
+ * If the variant cannot configure the pads by its own, then we
+ * expect the pinctrl to be able to do that for us
+ */
+ is_opendrain = (ios->bus_mode == MMC_BUSMODE_OPENDRAIN);
+ pins = pinctrl_lookup_state(host->pinctrl, is_opendrain ?
+ MMCI_PINCTRL_STATE_OPENDRAIN :
+ MMCI_PINCTRL_STATE_PUSHPULL);
+ if (IS_ERR(pins))
+ dev_warn(mmc_dev(mmc), "Cannot select pin drive type via pinctrl\n");
+ else
+ pinctrl_select_state(host->pinctrl, pins);
}
/*
@@ -1609,6 +1637,14 @@ static int mmci_probe(struct amba_device *dev,
host = mmc_priv(mmc);
host->mmc = mmc;
+ if (!variant->opendrain) {
+ host->pinctrl = devm_pinctrl_get(&dev->dev);
+ if (IS_ERR(host->pinctrl)) {
+ dev_err(&dev->dev, "failed to get pinctrl");
+ goto host_free;
+ }
+ }
+
host->hw_designer = amba_manf(dev);
host->hw_revision = amba_rev(dev);
dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index 83160a9..de3d0b3 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -192,6 +192,10 @@
#define NR_SG 128
+/* pinctrl configs */
+#define MMCI_PINCTRL_STATE_PUSHPULL "default"
+#define MMCI_PINCTRL_STATE_OPENDRAIN "opendrain"
+
struct clk;
struct variant_data;
struct dma_chan;
@@ -227,6 +231,7 @@ struct mmci_host {
bool vqmmc_enabled;
struct mmci_platform_data *plat;
struct variant_data *variant;
+ struct pinctrl *pinctrl;
u8 hw_designer;
u8 hw_revision:4;
--
1.9.1
^ permalink raw reply related
* [PATCH 04/14] mmc: mmci: Add STM32 variant
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
STM32F4 and STM32F7 MCUs has a SDIO controller that looks like
an ARM pl810.
This patch adds the STM32 variant so that mmci driver supports it.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/mmc/host/mmci.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index 38e8c20..9fb5035 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -245,6 +245,23 @@ struct variant_data {
.opendrain = true,
};
+static struct variant_data variant_stm32 = {
+ .fifosize = 32 * 4,
+ .fifohalfsize = 8 * 4,
+ .clkreg = MCI_CLK_ENABLE,
+ .clkreg_enable = MCI_ST_UX500_HWFCEN,
+ .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
+ .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
+ .datalength_bits = 24,
+ .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
+ .st_sdio = true,
+ .st_clkdiv = true,
+ .pwrreg_powerup = MCI_PWR_ON,
+ .f_max = 48000000,
+ .pwrreg_clkgate = true,
+ .pwrreg_nopower = true,
+};
+
static struct variant_data variant_qcom = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
@@ -2019,6 +2036,11 @@ static int mmci_runtime_resume(struct device *dev)
.mask = 0xf0ffffff,
.data = &variant_ux500v2,
},
+ {
+ .id = 0x00880180,
+ .mask = 0x00ffffff,
+ .data = &variant_stm32,
+ },
/* Qualcomm variants */
{
.id = 0x00051180,
--
1.9.1
^ permalink raw reply related
* [PATCH 05/14] ARM: dts: stm32: Add SDIO controller for stm32f746
From: patrice.chotard at st.com @ 2018-01-12 12:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
stm32f746 embeds ARM_PL180 sdio IP, adds SDIO controller
nodes to allow MMC support.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f746.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi
index 5f66d15..cffe1b1 100644
--- a/arch/arm/boot/dts/stm32f746.dtsi
+++ b/arch/arm/boot/dts/stm32f746.dtsi
@@ -429,6 +429,28 @@
status = "disabled";
};
+ sdio2: sdio2 at 40011c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40011c00 0x400>;
+ clocks = <&rcc 0 167>;
+ clock-names = "apb_pclk";
+ interrupts = <103>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
+ sdio: sdio at 40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 171>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config at 40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related
* [PATCH 06/14] ARM: dts: stm32: Add SDIO controller for stm32f429
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
stm32f429 embeds ARM_PL180 sdi IP, adds SDIO controller
node to allow MMC support.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f429.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 10099df..ede77e0 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -511,6 +511,17 @@
};
};
+ sdio: sdio at 40012c00 {
+ compatible = "arm,pl180", "arm,primecell";
+ arm,primecell-periphid = <0x00880180>;
+ reg = <0x40012c00 0x400>;
+ clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
+ clock-names = "apb_pclk";
+ interrupts = <49>;
+ max-frequency = <48000000>;
+ status = "disabled";
+ };
+
syscfg: system-config at 40013800 {
compatible = "syscon";
reg = <0x40013800 0x400>;
--
1.9.1
^ permalink raw reply related
* [PATCH 07/14] ARM: dts: stm32: Add pin map for SDIO controller on stm32f4
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds the pin configuration for SDIO controller on
stm32f4.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
index ae94d86..3520289 100644
--- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi
@@ -338,6 +338,37 @@
slew-rate = <3>;
};
};
+
+ sdio_pins: sdio_pins at 0 {
+ pins {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>, /* SDIO_CK */
+ <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+ };
+
+ sdio_pins_od: sdio_pins_od at 0 {
+ pins1 {
+ pinmux = <STM32_PINMUX('C', 8, AF12)>, /* SDIO_D0 */
+ <STM32_PINMUX('C', 9, AF12)>, /* SDIO_D1 */
+ <STM32_PINMUX('C', 10, AF12)>, /* SDIO_D2 */
+ <STM32_PINMUX('C', 11, AF12)>, /* SDIO_D3 */
+ <STM32_PINMUX('C', 12, AF12)>; /* SDIO_CK */
+ drive-push-pull;
+ slew-rate = <2>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('D', 2, AF12)>; /* SDIO_CMD */
+ drive-open-drain;
+ slew-rate = <2>;
+ };
+ };
};
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH 08/14] ARM: dts: stm32: Enable SDIO controller on stm32f469 disco board
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Andrea Merello <andrea.merello@gmail.com>
This patch adds SDIO-related DT nodes required by stm32f469 board
There is a hardware issue on these boards, it misses a pullup on
the GPIO line used as card detect to allow correct SD card
detection. To allow correct card detection "broken-cd" property
is used.
Signed-off-by: Andrea Merello <andrea.merello@gmail.com>
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32f469-disco.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32f469-disco.dts b/arch/arm/boot/dts/stm32f469-disco.dts
index 318fb12..ebb97c3 100644
--- a/arch/arm/boot/dts/stm32f469-disco.dts
+++ b/arch/arm/boot/dts/stm32f469-disco.dts
@@ -66,6 +66,13 @@
serial0 = &usart3;
};
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
soc {
dma-ranges = <0xc0000000 0x0 0x10000000>;
};
@@ -120,6 +127,18 @@
};
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&gpiog 2 0>;
+ cd-inverted;
+ broken-cd;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+};
+
&usart3 {
pinctrl-0 = <&usart3_pins_a>;
pinctrl-names = "default";
--
1.9.1
^ permalink raw reply related
* [PATCH 09/14] ARM: dts: stm32: Enable SDIO controller on stm32429i-eval board
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
This patch adds SDIO related DT nodes for stm32429i-eval board.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/boot/dts/stm32429i-eval.dts | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
index 1e3d4c6..6a5c701 100644
--- a/arch/arm/boot/dts/stm32429i-eval.dts
+++ b/arch/arm/boot/dts/stm32429i-eval.dts
@@ -144,6 +144,13 @@
};
};
};
+
+ mmc_vcard: mmc_vcard {
+ compatible = "regulator-fixed";
+ regulator-name = "mmc_vcard";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
};
&adc {
@@ -254,6 +261,18 @@
status = "okay";
};
+&sdio {
+ status = "okay";
+ vmmc-supply = <&mmc_vcard>;
+ cd-gpios = <&stmpegpio 15 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default", "opendrain";
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_pins_od>;
+ bus-width = <4>;
+ max-frequency = <12500000>;
+};
+
&timers1 {
status = "okay";
--
1.9.1
^ permalink raw reply related
* [PATCH 10/14] ARM: stm32: Add AMBA support for STM32F4 and STM32F7 SoCs
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
As both STM32F4 and STM32F7 SoCs embeds an AMBA PL180 mmci IP,
we need to enable AMBA support in mach-stm32.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/mach-stm32/Kconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index 0d1889b..f53a8db 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -13,16 +13,19 @@ config ARCH_STM32
config MACH_STM32F429
bool "STMicrolectronics STM32F429"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F469
bool "STMicrolectronics STM32F469"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32F746
bool "STMicrolectronics STM32F746"
depends on ARCH_STM32
+ select ARM_AMBA
default y
config MACH_STM32H743
--
1.9.1
^ permalink raw reply related
* [PATCH 11/14] ARM: configs: stm32: Enable MMC_ARMMMCI support
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
Enable MMC_ARMMCI support to add SDIO support for
STM32F4 and STM32F7 SoCs family
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 21b2bf7..8b64a9e 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -56,6 +56,8 @@ CONFIG_MFD_STMPE=y
CONFIG_REGULATOR=y
CONFIG_REGULATOR_FIXED_VOLTAGE=y
# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_ARMMMCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=y
CONFIG_LEDS_GPIO=y
--
1.9.1
^ permalink raw reply related
* [PATCH 12/14] ARM: configs: stm32: Enable EXT3_FS support
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
Enable EXT3_FS support to be able to read rootfs from MMC partition
formatted in EXT2/3/4 .
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
arch/arm/configs/stm32_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
index 8b64a9e..b736823 100644
--- a/arch/arm/configs/stm32_defconfig
+++ b/arch/arm/configs/stm32_defconfig
@@ -72,6 +72,7 @@ CONFIG_STM32_MDMA=y
CONFIG_IIO=y
CONFIG_STM32_ADC_CORE=y
CONFIG_STM32_ADC=y
+CONFIG_EXT3_FS=y
# CONFIG_FILE_LOCKING is not set
# CONFIG_DNOTIFY is not set
# CONFIG_INOTIFY_USER is not set
--
1.9.1
^ permalink raw reply related
* [PATCH 13/14] clk: stm32: Add clk entry for SDMMC2 on stm32F769
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
STM32F769 has 2 SDMMC port, add clock entry for the second one.
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/clk/clk-stm32f4.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-stm32f4.c b/drivers/clk/clk-stm32f4.c
index 96c6b6b..8f8a178 100644
--- a/drivers/clk/clk-stm32f4.c
+++ b/drivers/clk/clk-stm32f4.c
@@ -282,6 +282,7 @@ struct stm32f4_gate_data {
{ STM32F4_RCC_APB2ENR, 0, "tim1", "apb2_mul" },
{ STM32F4_RCC_APB2ENR, 1, "tim8", "apb2_mul" },
+ { STM32F4_RCC_APB2ENR, 7, "sdmmc2", "sdmux" },
{ STM32F4_RCC_APB2ENR, 8, "adc1", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 9, "adc2", "apb2_div" },
{ STM32F4_RCC_APB2ENR, 10, "adc3", "apb2_div" },
@@ -315,7 +316,7 @@ struct stm32f4_gate_data {
static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
0x0000000000000003ull,
- 0x04f77f033e01c9ffull };
+ 0x04f77f833e01c9ffull };
static const u64 *stm32f4_gate_map;
--
1.9.1
^ permalink raw reply related
* [PATCH 14/14] gpio: stmpe: i2c transfer are forbiden in atomic context
From: patrice.chotard at st.com @ 2018-01-12 12:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515759368-16946-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
Move the workaround from stmpe_gpio_irq_unmask() which is executed
in atomic context to stmpe_gpio_irq_sync_unlock() which is not.
It fixes the following issue:
[ 1.500000] BUG: scheduling while atomic: swapper/1/0x00000002
[ 1.500000] CPU: 0 PID: 1 Comm: swapper Not tainted 4.15.0-rc2-00020-gbd4301f-dirty #28
[ 1.520000] Hardware name: STM32 (Device Tree Support)
[ 1.520000] [<0000bfc9>] (unwind_backtrace) from [<0000b347>] (show_stack+0xb/0xc)
[ 1.530000] [<0000b347>] (show_stack) from [<0001fc49>] (__schedule_bug+0x39/0x58)
[ 1.530000] [<0001fc49>] (__schedule_bug) from [<00168211>] (__schedule+0x23/0x2b2)
[ 1.550000] [<00168211>] (__schedule) from [<001684f7>] (schedule+0x57/0x64)
[ 1.550000] [<001684f7>] (schedule) from [<0016a513>] (schedule_timeout+0x137/0x164)
[ 1.550000] [<0016a513>] (schedule_timeout) from [<00168b91>] (wait_for_common+0x8d/0xfc)
[ 1.570000] [<00168b91>] (wait_for_common) from [<00139753>] (stm32f4_i2c_xfer+0xe9/0xfe)
[ 1.580000] [<00139753>] (stm32f4_i2c_xfer) from [<00138545>] (__i2c_transfer+0x111/0x148)
[ 1.590000] [<00138545>] (__i2c_transfer) from [<001385cf>] (i2c_transfer+0x53/0x70)
[ 1.590000] [<001385cf>] (i2c_transfer) from [<001388a5>] (i2c_smbus_xfer+0x12f/0x36e)
[ 1.600000] [<001388a5>] (i2c_smbus_xfer) from [<00138b49>] (i2c_smbus_read_byte_data+0x1f/0x2a)
[ 1.610000] [<00138b49>] (i2c_smbus_read_byte_data) from [<00124fdd>] (__stmpe_reg_read+0xd/0x24)
[ 1.620000] [<00124fdd>] (__stmpe_reg_read) from [<001252b3>] (stmpe_reg_read+0x19/0x24)
[ 1.630000] [<001252b3>] (stmpe_reg_read) from [<0002c4d1>] (unmask_irq+0x17/0x22)
[ 1.640000] [<0002c4d1>] (unmask_irq) from [<0002c57f>] (irq_startup+0x6f/0x78)
[ 1.650000] [<0002c57f>] (irq_startup) from [<0002b7a1>] (__setup_irq+0x319/0x47c)
[ 1.650000] [<0002b7a1>] (__setup_irq) from [<0002bad3>] (request_threaded_irq+0x6b/0xe8)
[ 1.660000] [<0002bad3>] (request_threaded_irq) from [<0002d0b9>] (devm_request_threaded_irq+0x3b/0x6a)
[ 1.670000] [<0002d0b9>] (devm_request_threaded_irq) from [<001446e7>] (mmc_gpiod_request_cd_irq+0x49/0x8a)
[ 1.680000] [<001446e7>] (mmc_gpiod_request_cd_irq) from [<0013d45d>] (mmc_start_host+0x49/0x60)
[ 1.690000] [<0013d45d>] (mmc_start_host) from [<0013e40b>] (mmc_add_host+0x3b/0x54)
[ 1.700000] [<0013e40b>] (mmc_add_host) from [<00148119>] (mmci_probe+0x4d1/0x60c)
[ 1.710000] [<00148119>] (mmci_probe) from [<000f903b>] (amba_probe+0x7b/0xbe)
[ 1.720000] [<000f903b>] (amba_probe) from [<001170e5>] (driver_probe_device+0x169/0x1f8)
[ 1.730000] [<001170e5>] (driver_probe_device) from [<001171b7>] (__driver_attach+0x43/0x5c)
[ 1.740000] [<001171b7>] (__driver_attach) from [<0011618d>] (bus_for_each_dev+0x3d/0x46)
[ 1.740000] [<0011618d>] (bus_for_each_dev) from [<001165cd>] (bus_add_driver+0xcd/0x124)
[ 1.740000] [<001165cd>] (bus_add_driver) from [<00117713>] (driver_register+0x4d/0x7a)
[ 1.760000] [<00117713>] (driver_register) from [<001fc765>] (do_one_initcall+0xbd/0xe8)
[ 1.770000] [<001fc765>] (do_one_initcall) from [<001fc88b>] (kernel_init_freeable+0xfb/0x134)
[ 1.780000] [<001fc88b>] (kernel_init_freeable) from [<00167ee3>] (kernel_init+0x7/0x9c)
[ 1.790000] [<00167ee3>] (kernel_init) from [<00009b65>] (ret_from_fork+0x11/0x2c)
Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
---
drivers/gpio/gpio-stmpe.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpio/gpio-stmpe.c b/drivers/gpio/gpio-stmpe.c
index e6e5cca..91c8ae2 100644
--- a/drivers/gpio/gpio-stmpe.c
+++ b/drivers/gpio/gpio-stmpe.c
@@ -190,6 +190,16 @@ static void stmpe_gpio_irq_sync_unlock(struct irq_data *d)
};
int i, j;
+ /*
+ * STMPE1600: to be able to get IRQ from pins,
+ * a read must be done on GPMR register, or a write in
+ * GPSR or GPCR registers
+ */
+ if (stmpe->partnum == STMPE1600) {
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_LSB]);
+ stmpe_reg_read(stmpe, stmpe->regs[STMPE_IDX_GPMR_CSB]);
+ };
+
for (i = 0; i < CACHE_NR_REGS; i++) {
/* STMPE801 and STMPE1600 don't have RE and FE registers */
if ((stmpe->partnum == STMPE801 ||
@@ -227,21 +237,11 @@ static void stmpe_gpio_irq_unmask(struct irq_data *d)
{
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
struct stmpe_gpio *stmpe_gpio = gpiochip_get_data(gc);
- struct stmpe *stmpe = stmpe_gpio->stmpe;
int offset = d->hwirq;
int regoffset = offset / 8;
int mask = BIT(offset % 8);
stmpe_gpio->regs[REG_IE][regoffset] |= mask;
-
- /*
- * STMPE1600 workaround: to be able to get IRQ from pins,
- * a read must be done on GPMR register, or a write in
- * GPSR or GPCR registers
- */
- if (stmpe->partnum == STMPE1600)
- stmpe_reg_read(stmpe,
- stmpe->regs[STMPE_IDX_GPMR_LSB + regoffset]);
}
static void stmpe_dbg_show_one(struct seq_file *s,
--
1.9.1
^ permalink raw reply related
* [PATCH] arm64: support do_csum with neon
From: Robin Murphy @ 2018-01-12 12:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1515757996-4675-1-git-send-email-chenzhou10@huawei.com>
On 12/01/18 11:53, Chen Zhou wrote:
> On arm64 little endian such as the Cortex-A57, the
> neon based implementation performance increases by
> about 70% when len is greater than 512.
Um, I don't see the kernel-mode NEON infrastructure being used anywhere
here. Blindly destroying someone else's register context is never going
to end well, regardless of how fast you can do it...
Robin.
> Signed-off-by: Chen Zhou <chenzhou10@huawei.com>
> ---
> arch/arm64/include/asm/checksum.h | 3 +
> arch/arm64/lib/Makefile | 1 +
> arch/arm64/lib/do_csum.S | 177 ++++++++++++++++++++++++++++++++++++++
> 3 files changed, 181 insertions(+)
> create mode 100644 arch/arm64/lib/do_csum.S
>
> diff --git a/arch/arm64/include/asm/checksum.h b/arch/arm64/include/asm/checksum.h
> index 09f6533..e300782 100644
> --- a/arch/arm64/include/asm/checksum.h
> +++ b/arch/arm64/include/asm/checksum.h
> @@ -26,6 +26,9 @@ static inline __sum16 csum_fold(__wsum csum)
> }
> #define csum_fold csum_fold
>
> +#define do_csum do_csum
> +extern unsigned int do_csum(const unsigned char *, size_t);
> +
> static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
> {
> __uint128_t tmp;
> diff --git a/arch/arm64/lib/Makefile b/arch/arm64/lib/Makefile
> index 1a811ec..5b6aa34 100644
> --- a/arch/arm64/lib/Makefile
> +++ b/arch/arm64/lib/Makefile
> @@ -3,6 +3,7 @@ lib-y := bitops.o clear_user.o delay.o copy_from_user.o \
> clear_page.o memchr.o memcpy.o memmove.o memset.o \
> memcmp.o strcmp.o strncmp.o strlen.o strnlen.o \
> strchr.o strrchr.o
> +lib-y += do_csum.o
>
> # Tell the compiler to treat all general purpose registers as
> # callee-saved, which allows for efficient runtime patching of the bl
> diff --git a/arch/arm64/lib/do_csum.S b/arch/arm64/lib/do_csum.S
> new file mode 100644
> index 0000000..8e7b486
> --- /dev/null
> +++ b/arch/arm64/lib/do_csum.S
> @@ -0,0 +1,177 @@
> +/*
> + * Optmized version of the standard do_csum() function
> + *
> + * Parameters:
> + * x0 - address of buffer to checksum (const unsigned char *)
> + * x1 - length of the buffer (int)
> + * Returns:
> + * x0 - the return checksum of the buffer
> + */
> +
> +#include <linux/linkage.h>
> +#include <asm/assembler.h>
> +
> +ENTRY(do_csum)
> + ldr x13, =0xffff
> + eor x4, x4, x4
> + eor x5, x5, x5
> + eor v0.16b, v0.16b, v0.16b
> +
> + //len is zero or negative
> + and x6, x1, #0x80000000
> + cmp x6, #0
> + b.gt out
> + cbz w1, out
> +
> + tst x0, #1
> + b.eq addr_not_odd
> +
> + //addr is odd
> + mov x4, #1
> + ldr x6, [x0], #1
> +#ifdef __AARCH64EB__
> + and x6, x6, #0xff
> +#else
> + lsl x6, x6, #8
> + and x6, x6, x13
> +#endif
> + add x5, x5, x6
> + sub x1, x1, #1
> +
> +addr_not_odd:
> + cmp x1, #32
> + b.lt len_4
> + cmp x1, #192
> + b.ge len_than_192
> + b do_loop_16
> +
> +len_than_192:
> + ldp q1, q0, [x0], #32
> + ldp q3, q2, [x0], #32
> + ldp q5, q4, [x0], #32
> + sub x1, x1, #96
> +
> +do_loop_96:
> + ldp q7, q6, [x0], #32
> + ldp q9, q8, [x0], #32
> + ldp q11, q10, [x0], #32
> +
> + uaddl v12.4s, v0.4h, v6.4h
> + uaddl2 v13.4s, v0.8h, v6.8h
> +
> + uaddl v14.4s, v1.4h, v7.4h
> + uaddl2 v15.4s, v1.8h, v7.8h
> +
> + uaddl v16.4s, v2.4h, v8.4h
> + uaddl2 v17.4s, v2.8h, v8.8h
> +
> + uaddl v18.4s, v3.4h, v9.4h
> + uaddl2 v19.4s, v3.8h, v9.8h
> +
> + uaddl v20.4s, v4.4h, v10.4h
> + uaddl2 v21.4s, v4.8h, v10.8h
> + uaddl v22.4s, v5.4h, v11.4h
> + uaddl2 v23.4s, v5.8h, v11.8h
> +
> + add v0.4s, v12.4s, v13.4s
> + add v1.4s, v14.4s, v15.4s
> + add v2.4s, v16.4s, v17.4s
> + add v3.4s, v18.4s, v19.4s
> + add v4.4s, v20.4s, v21.4s
> + add v5.4s, v22.4s, v23.4s
> +
> + sub x1, x1, #96
> + cmp x1, #96
> + b.ge do_loop_96
> +
> + add v0.4s, v0.4s, v1.4s
> + add v2.4s, v2.4s, v3.4s
> + add v4.4s, v4.4s, v5.4s
> + add v0.4s, v0.4s, v2.4s
> + add v0.4s, v0.4s, v4.4s //get result
> +
> + cmp x1, #16
> + b.lt get_64
> +
> +do_loop_16:
> + ldr q6, [x0], #16
> + uaddl v24.4s, v0.4h, v6.4h
> + uaddl2 v25.4s, v0.8h, v6.8h
> + add v0.4s, v24.4s, v25.4s
> + sub x1, x1, #16
> + cmp x1, #16
> + b.ge do_loop_16
> +
> +get_64:
> + mov x6, v0.d[0]
> + add x5, x5, x6
> + mov x6, v0.d[1]
> +
> + add x5, x5, x6
> + cmp x5, x6
> + b.ge len_4
> + add x5, x5, #1
> +
> +len_4:
> + cmp x1, #4
> + b.lt len_2
> +
> + sub x1, x1, #4
> + ldr w6, [x0], #4
> + and x6, x6, #0xffffffff
> + add x5, x5, x6
> + b len_4
> +
> +len_2:
> + cmp x1, #2
> + b.lt len_1
> + sub x1, x1, #2
> + ldrh w6, [x0], #2
> + and x6, x6, x13
> + add x5, x5, x6
> +
> +len_1:
> + cmp x1, #1
> + b.lt fold_32
> + ldr x6, [x0], #1
> +#ifdef __AARCH64EB__
> + lsl x6, x6, #8
> + and x6, x6, x13
> +#else
> + and x6, x6, #0xff
> +#endif
> + add x5, x5, x6
> +
> +fold_32:
> + and x9, x5, x13 //[15:0]
> + and x10, x13, x5, lsr #16 //[31:16]
> + and x11, x13, x5, lsr #32 //[47:32]
> + and x12, x13, x5, lsr #48 //[47:32]
> +
> + add x9, x9, x10
> + add x11, x11, x12
> +
> + add x9, x9, x11
> +
> + and x10, x9, x13
> + and x11, x13, x9, lsr #16
> +
> + add x5, x10, x11
> +
> + and x9, x5, x13 //add carry
> + and x10, x13, x5, lsr #16
> + add x5, x9, x10
> +
> + cbz x4, out //addr isn't odd
> +
> + lsr x6, x5, #8
> + and x6, x6, #0xff
> + and x7, x5, #0xff
> + lsl x7, x7, #8
> +
> + orr x5, x6, x7
> +
> +out:
> + mov x0, x5
> + ret
> +ENDPROC(do_csum)
>
^ permalink raw reply
* PM regression in next
From: Rafael J. Wysocki @ 2018-01-12 12:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112013257.GB4059@atomide.com>
On Friday, January 12, 2018 2:32:57 AM CET Tony Lindgren wrote:
> * Tony Lindgren <tony@atomide.com> [180111 17:20]:
> > Well I tried to measure suspend power consumption and noticed
> > that system suspend fails too hand hangs the network device:
> >
> > # echo mem > /sys/power/state
> > [ 32.577850] PM: suspend entry (deep)
> > [ 32.582031] PM: Syncing filesystems ... done.
> > [ 32.598083] Freezing user space processes ... (elapsed 0.002 seconds) done.
> > [ 32.608398] OOM killer disabled.
> > [ 32.611846] Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done.
> > [ 32.622192] Suspending console(s) (use no_console_suspend to debug)
> > [ 32.651123] dpm_run_callback(): mdio_bus_suspend+0x0/0x24 returns 4352
> > [ 32.651428] PM: Device 2c000000.ethernet-ffffffff:01 failed to suspend: error 4352
This looks totally bogus.
First, "error" should be a negative number and we print it as int.
Second, error codes are not in this range anyway.
> > [ 32.653289] PM: Some devices failed to suspend, or early wake event detected
> > [ 32.685455] OOM killer enabled.
> > [ 32.688629] Restarting tasks ... done.
> > [ 32.695983] PM: suspend exit
> > ash: write error: Bad address
> >
> > That too works just fine at commit 70286688e5ad.
>
> Suspend fails at commit e2d7fe89e8ae though, so looks like we
> have two separate issues. I'll try to bisect that separately.
BTW, can you please CC PM bug reports to linux-pm? That may help sometimes.
Thanks,
Rafael
^ permalink raw reply
* PM regression in next
From: Rafael J. Wysocki @ 2018-01-12 12:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <4913146.sVL6sFxzC8@aspire.rjw.lan>
On Friday, January 12, 2018 1:23:54 PM CET Rafael J. Wysocki wrote:
> On Friday, January 12, 2018 2:32:57 AM CET Tony Lindgren wrote:
> > * Tony Lindgren <tony@atomide.com> [180111 17:20]:
> > > Well I tried to measure suspend power consumption and noticed
> > > that system suspend fails too hand hangs the network device:
> > >
> > > # echo mem > /sys/power/state
> > > [ 32.577850] PM: suspend entry (deep)
> > > [ 32.582031] PM: Syncing filesystems ... done.
> > > [ 32.598083] Freezing user space processes ... (elapsed 0.002 seconds) done.
> > > [ 32.608398] OOM killer disabled.
> > > [ 32.611846] Freezing remaining freezable tasks ... (elapsed 0.002 seconds) done.
> > > [ 32.622192] Suspending console(s) (use no_console_suspend to debug)
> > > [ 32.651123] dpm_run_callback(): mdio_bus_suspend+0x0/0x24 returns 4352
> > > [ 32.651428] PM: Device 2c000000.ethernet-ffffffff:01 failed to suspend: error 4352
>
> This looks totally bogus.
>
> First, "error" should be a negative number and we print it as int.
>
> Second, error codes are not in this range anyway.
>
> > > [ 32.653289] PM: Some devices failed to suspend, or early wake event detected
> > > [ 32.685455] OOM killer enabled.
> > > [ 32.688629] Restarting tasks ... done.
> > > [ 32.695983] PM: suspend exit
> > > ash: write error: Bad address
> > >
> > > That too works just fine at commit 70286688e5ad.
> >
> > Suspend fails at commit e2d7fe89e8ae though, so looks like we
> > have two separate issues. I'll try to bisect that separately.
I guess what may happen is that something started to return positive numbers
which confuse things all over when passed along by its callers as error codes.
Thanks,
Rafael
^ permalink raw reply
* [PATCH] arm64: kpti: Fix the interaction between ASID switching and software PAN
From: Catalin Marinas @ 2018-01-12 12:30 UTC (permalink / raw)
To: linux-arm-kernel
With ARM64_SW_TTBR0_PAN enabled, the exception entry code checks the
active ASID to decide whether user access was enabled (non-zero ASID)
when the exception was taken. On return from exception, if user access
was previously disabled, it re-instates TTBR0_EL1 from the per-thread
saved value (updated in switch_mm() or efi_set_pgd()).
Commit 7655abb95386 ("arm64: mm: Move ASID from TTBR0 to TTBR1") makes a
TTBR0_EL1 + ASID switching non-atomic. Subsequently, commit 27a921e75711
("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN") changes the
__uaccess_ttbr0_disable() function and asm macro to first write the
reserved TTBR0_EL1 followed by the ASID=0 update in TTBR1_EL1. If an
exception occurs between these two, the exception return code will
re-instate a valid TTBR0_EL1. Similar scenario can happen in
cpu_switch_mm() between setting the reserved TTBR0_EL1 and the ASID
update in cpu_do_switch_mm().
This patch reverts the entry.S check for ASID == 0 to TTBR0_EL1 and
disables the interrupts around the TTBR0_EL1 and ASID switching code in
__uaccess_ttbr0_disable(). It also ensures that, when returning from the
EFI runtime services, efi_set_pgd() doesn't leave a non-zero ASID in
TTBR1_EL1.
As a safety measure, __uaccess_ttbr0_enable() always masks out any
existing non-zero ASID TTBR1_EL1 before writing in the new ASID.
Fixes: 27a921e75711 ("arm64: mm: Fix and re-enable ARM64_SW_TTBR0_PAN")
Cc: Will Deacon <will.deacon@arm.com>
Cc: James Morse <james.morse@arm.com>
Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Co-developed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
---
arch/arm64/include/asm/asm-uaccess.h | 12 +++++++-----
arch/arm64/include/asm/efi.h | 2 +-
arch/arm64/include/asm/uaccess.h | 7 +++++--
arch/arm64/kernel/entry.S | 2 +-
arch/arm64/lib/clear_user.S | 2 +-
arch/arm64/lib/copy_from_user.S | 2 +-
arch/arm64/lib/copy_in_user.S | 2 +-
arch/arm64/lib/copy_to_user.S | 2 +-
arch/arm64/mm/cache.S | 2 +-
arch/arm64/mm/proc.S | 3 +++
arch/arm64/xen/hypercall.S | 2 +-
11 files changed, 23 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/include/asm/asm-uaccess.h b/arch/arm64/include/asm/asm-uaccess.h
index f4f234b6155e..dd49c3567f20 100644
--- a/arch/arm64/include/asm/asm-uaccess.h
+++ b/arch/arm64/include/asm/asm-uaccess.h
@@ -14,11 +14,11 @@
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
.macro __uaccess_ttbr0_disable, tmp1
mrs \tmp1, ttbr1_el1 // swapper_pg_dir
+ bic \tmp1, \tmp1, #TTBR_ASID_MASK
add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir
msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1
isb
sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE
- bic \tmp1, \tmp1, #TTBR_ASID_MASK
msr ttbr1_el1, \tmp1 // set reserved ASID
isb
.endm
@@ -35,9 +35,11 @@
isb
.endm
- .macro uaccess_ttbr0_disable, tmp1
+ .macro uaccess_ttbr0_disable, tmp1, tmp2
alternative_if_not ARM64_HAS_PAN
+ save_and_disable_irq \tmp2 // avoid preemption
__uaccess_ttbr0_disable \tmp1
+ restore_irq \tmp2
alternative_else_nop_endif
.endm
@@ -49,7 +51,7 @@ alternative_if_not ARM64_HAS_PAN
alternative_else_nop_endif
.endm
#else
- .macro uaccess_ttbr0_disable, tmp1
+ .macro uaccess_ttbr0_disable, tmp1, tmp2
.endm
.macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3
@@ -59,8 +61,8 @@ alternative_else_nop_endif
/*
* These macros are no-ops when UAO is present.
*/
- .macro uaccess_disable_not_uao, tmp1
- uaccess_ttbr0_disable \tmp1
+ .macro uaccess_disable_not_uao, tmp1, tmp2
+ uaccess_ttbr0_disable \tmp1, \tmp2
alternative_if ARM64_ALT_PAN_NOT_UAO
SET_PSTATE_PAN(1)
alternative_else_nop_endif
diff --git a/arch/arm64/include/asm/efi.h b/arch/arm64/include/asm/efi.h
index c4cd5081d78b..2bf1b8522a62 100644
--- a/arch/arm64/include/asm/efi.h
+++ b/arch/arm64/include/asm/efi.h
@@ -133,7 +133,7 @@ static inline void efi_set_pgd(struct mm_struct *mm)
* until uaccess_enable(). Restore the current
* thread's saved ttbr0 corresponding to its active_mm
*/
- cpu_set_reserved_ttbr0();
+ uaccess_ttbr0_disable();
update_saved_ttbr0(current, current->active_mm);
}
}
diff --git a/arch/arm64/include/asm/uaccess.h b/arch/arm64/include/asm/uaccess.h
index 6eadf55ebaf0..f12e2f7c3854 100644
--- a/arch/arm64/include/asm/uaccess.h
+++ b/arch/arm64/include/asm/uaccess.h
@@ -105,16 +105,18 @@ static inline void set_fs(mm_segment_t fs)
#ifdef CONFIG_ARM64_SW_TTBR0_PAN
static inline void __uaccess_ttbr0_disable(void)
{
- unsigned long ttbr;
+ unsigned long flags, ttbr;
+ local_irq_save(flags);
ttbr = read_sysreg(ttbr1_el1);
+ ttbr &= ~TTBR_ASID_MASK;
/* reserved_ttbr0 placed at the end of swapper_pg_dir */
write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1);
isb();
/* Set reserved ASID */
- ttbr &= ~TTBR_ASID_MASK;
write_sysreg(ttbr, ttbr1_el1);
isb();
+ local_irq_restore(flags);
}
static inline void __uaccess_ttbr0_enable(void)
@@ -131,6 +133,7 @@ static inline void __uaccess_ttbr0_enable(void)
/* Restore active ASID */
ttbr1 = read_sysreg(ttbr1_el1);
+ ttbr1 &= ~TTBR_ASID_MASK; /* safety measure */
ttbr1 |= ttbr0 & TTBR_ASID_MASK;
write_sysreg(ttbr1, ttbr1_el1);
isb();
diff --git a/arch/arm64/kernel/entry.S b/arch/arm64/kernel/entry.S
index 07a7d4db8ec4..3fe51520106d 100644
--- a/arch/arm64/kernel/entry.S
+++ b/arch/arm64/kernel/entry.S
@@ -204,7 +204,7 @@ alternative_if ARM64_HAS_PAN
alternative_else_nop_endif
.if \el != 0
- mrs x21, ttbr1_el1
+ mrs x21, ttbr0_el1
tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
b.eq 1f // TTBR0 access already disabled
diff --git a/arch/arm64/lib/clear_user.S b/arch/arm64/lib/clear_user.S
index 8f9c4641e706..3d69a8d41fa5 100644
--- a/arch/arm64/lib/clear_user.S
+++ b/arch/arm64/lib/clear_user.S
@@ -50,7 +50,7 @@ uao_user_alternative 9f, strh, sttrh, wzr, x0, 2
b.mi 5f
uao_user_alternative 9f, strb, sttrb, wzr, x0, 0
5: mov x0, #0
- uaccess_disable_not_uao x2
+ uaccess_disable_not_uao x2, x3
ret
ENDPROC(__clear_user)
diff --git a/arch/arm64/lib/copy_from_user.S b/arch/arm64/lib/copy_from_user.S
index 69d86a80f3e2..20305d485046 100644
--- a/arch/arm64/lib/copy_from_user.S
+++ b/arch/arm64/lib/copy_from_user.S
@@ -67,7 +67,7 @@ ENTRY(__arch_copy_from_user)
uaccess_enable_not_uao x3, x4, x5
add end, x0, x2
#include "copy_template.S"
- uaccess_disable_not_uao x3
+ uaccess_disable_not_uao x3, x4
mov x0, #0 // Nothing to copy
ret
ENDPROC(__arch_copy_from_user)
diff --git a/arch/arm64/lib/copy_in_user.S b/arch/arm64/lib/copy_in_user.S
index e442b531252a..fbb090f431a5 100644
--- a/arch/arm64/lib/copy_in_user.S
+++ b/arch/arm64/lib/copy_in_user.S
@@ -68,7 +68,7 @@ ENTRY(raw_copy_in_user)
uaccess_enable_not_uao x3, x4, x5
add end, x0, x2
#include "copy_template.S"
- uaccess_disable_not_uao x3
+ uaccess_disable_not_uao x3, x4
mov x0, #0
ret
ENDPROC(raw_copy_in_user)
diff --git a/arch/arm64/lib/copy_to_user.S b/arch/arm64/lib/copy_to_user.S
index 318f15d5c336..fda6172d6b88 100644
--- a/arch/arm64/lib/copy_to_user.S
+++ b/arch/arm64/lib/copy_to_user.S
@@ -66,7 +66,7 @@ ENTRY(__arch_copy_to_user)
uaccess_enable_not_uao x3, x4, x5
add end, x0, x2
#include "copy_template.S"
- uaccess_disable_not_uao x3
+ uaccess_disable_not_uao x3, x4
mov x0, #0
ret
ENDPROC(__arch_copy_to_user)
diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S
index 6cd20a8c0952..91464e7f77cc 100644
--- a/arch/arm64/mm/cache.S
+++ b/arch/arm64/mm/cache.S
@@ -72,7 +72,7 @@ USER(9f, ic ivau, x4 ) // invalidate I line PoU
isb
mov x0, #0
1:
- uaccess_ttbr0_disable x1
+ uaccess_ttbr0_disable x1, x2
ret
9:
mov x0, #-EFAULT
diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
index bc86f7ef8620..d4cd399c5925 100644
--- a/arch/arm64/mm/proc.S
+++ b/arch/arm64/mm/proc.S
@@ -140,6 +140,9 @@ ENDPROC(cpu_do_resume)
ENTRY(cpu_do_switch_mm)
mrs x2, ttbr1_el1
mmid x1, x1 // get mm->context.id
+#ifdef CONFIG_ARM64_SW_TTBR0_PAN
+ bfi x0, x1, #48, #16 // set the ASID field in TTBR0
+#endif
bfi x2, x1, #48, #16 // set the ASID
msr ttbr1_el1, x2 // in TTBR1 (since TCR.A1 is set)
isb
diff --git a/arch/arm64/xen/hypercall.S b/arch/arm64/xen/hypercall.S
index acdbd2c9e899..c5f05c4a4d00 100644
--- a/arch/arm64/xen/hypercall.S
+++ b/arch/arm64/xen/hypercall.S
@@ -107,6 +107,6 @@ ENTRY(privcmd_call)
/*
* Disable userspace access from kernel once the hyp call completed.
*/
- uaccess_ttbr0_disable x6
+ uaccess_ttbr0_disable x6, x7
ret
ENDPROC(privcmd_call);
^ permalink raw reply related
* [PULL 0/2] KVM/ARM Fixes for v4.15 - Round 3
From: Christoffer Dall @ 2018-01-12 12:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi Paolo and Radim,
This is the third round of fixes for KVM/ARM for v4.15, including two more
fixes for v4.15 fixing incorrect huge page mappings on systems using the
contiguous hint for hugetlbfs and supporting an alternative GICv4 init
sequence.
The following changes since commit 0eb7c33cadf6b2f1a94e58ded8b0eb89b4eba382:
KVM: arm/arm64: Fix timer enable flow (2017-12-18 10:53:24 +0100)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvm-arm-fixes-for-v4.15-3
for you to fetch changes up to f8f85dc00b7427de6222ea3955c52512315d13cd:
KVM: arm64: Fix GICv4 init when called from vgic_its_create (2018-01-12 11:40:21 +0100)
Thanks,
-Christoffer
Christoffer Dall (1):
KVM: arm64: Fix GICv4 init when called from vgic_its_create
Punit Agrawal (1):
KVM: arm/arm64: Check pagesize when allocating a hugepage at Stage 2
virt/kvm/arm/mmu.c | 2 +-
virt/kvm/arm/vgic/vgic-init.c | 8 +++++---
virt/kvm/arm/vgic/vgic-v4.c | 2 +-
3 files changed, 7 insertions(+), 5 deletions(-)
^ permalink raw reply
* [PULL 1/2] KVM: arm/arm64: Check pagesize when allocating a hugepage at Stage 2
From: Christoffer Dall @ 2018-01-12 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112123334.28687-1-christoffer.dall@linaro.org>
From: Punit Agrawal <punit.agrawal@arm.com>
KVM only supports PMD hugepages at stage 2 but doesn't actually check
that the provided hugepage memory pagesize is PMD_SIZE before populating
stage 2 entries.
In cases where the backing hugepage size is smaller than PMD_SIZE (such
as when using contiguous hugepages), KVM can end up creating stage 2
mappings that extend beyond the supplied memory.
Fix this by checking for the pagesize of userspace vma before creating
PMD hugepage at stage 2.
Fixes: 66b3923a1a0f77a ("arm64: hugetlb: add support for PTE contiguous bit")
Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: <stable@vger.kernel.org> # v4.5+
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index b4b69c2d1012..9dea96380339 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -1310,7 +1310,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
return -EFAULT;
}
- if (is_vm_hugetlb_page(vma) && !logging_active) {
+ if (vma_kernel_pagesize(vma) == PMD_SIZE && !logging_active) {
hugetlb = true;
gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
} else {
--
2.14.2
^ permalink raw reply related
* [PULL 2/2] KVM: arm64: Fix GICv4 init when called from vgic_its_create
From: Christoffer Dall @ 2018-01-12 12:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112123334.28687-1-christoffer.dall@linaro.org>
Commit 3d1ad640f8c94 ("KVM: arm/arm64: Fix GICv4 ITS initialization
issues") moved the vgic_supports_direct_msis() check in vgic_v4_init().
However when vgic_v4_init is called from vgic_its_create(), the has_its
field is not yet set. Hence vgic_supports_direct_msis returns false and
vgic_v4_init does nothing.
The gic/its init sequence is a bit messy, so let's be specific about the
prerequisite checks in the various call paths instead of relying on a
common wrapper.
Fixes: 3d1ad640f8c94 ("KVM: arm/arm64: Fix GICv4 ITS initialization issues")
Reported-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
---
virt/kvm/arm/vgic/vgic-init.c | 8 +++++---
virt/kvm/arm/vgic/vgic-v4.c | 2 +-
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/virt/kvm/arm/vgic/vgic-init.c b/virt/kvm/arm/vgic/vgic-init.c
index 62310122ee78..743ca5cb05ef 100644
--- a/virt/kvm/arm/vgic/vgic-init.c
+++ b/virt/kvm/arm/vgic/vgic-init.c
@@ -285,9 +285,11 @@ int vgic_init(struct kvm *kvm)
if (ret)
goto out;
- ret = vgic_v4_init(kvm);
- if (ret)
- goto out;
+ if (vgic_has_its(kvm)) {
+ ret = vgic_v4_init(kvm);
+ if (ret)
+ goto out;
+ }
kvm_for_each_vcpu(i, vcpu, kvm)
kvm_vgic_vcpu_enable(vcpu);
diff --git a/virt/kvm/arm/vgic/vgic-v4.c b/virt/kvm/arm/vgic/vgic-v4.c
index 4a37292855bc..bc4265154bac 100644
--- a/virt/kvm/arm/vgic/vgic-v4.c
+++ b/virt/kvm/arm/vgic/vgic-v4.c
@@ -118,7 +118,7 @@ int vgic_v4_init(struct kvm *kvm)
struct kvm_vcpu *vcpu;
int i, nr_vcpus, ret;
- if (!vgic_supports_direct_msis(kvm))
+ if (!kvm_vgic_global_state.has_gicv4)
return 0; /* Nothing to see here... move along. */
if (dist->its_vm.vpes)
--
2.14.2
^ permalink raw reply related
* [PATCH] soc: brcmstb: Only register SoC device on STB platforms
From: Thierry Reding @ 2018-01-12 12:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <cc470686-374e-0c71-d797-62cffd76bb82@arm.com>
On Fri, Jan 12, 2018 at 11:39:30AM +0000, Sudeep Holla wrote:
>
>
> On 09/01/18 14:54, Thierry Reding wrote:
> > From: Thierry Reding <treding@nvidia.com>
> >
> > After moving the SoC device initialization to an early initcall in
> > commit f780429adfbc ("soc: brcmstb: biuctrl: Move to early_initcall"),
> > the Broadcom STB SoC device is registered on all platforms if support
> > for the device is enabled in the kernel configuration.
> >
> > This causes an additional SoC device to appear on platforms that already
> > register a native one. In case of Tegra the STB SoC device is registered
> > as soc0 (with totally meaningless content in the sysfs attributes) and
> > causes various scripts and programs to fail because they don't know how
> > to parse that data.
> >
> > To fix this, duplicate the check from brcmstb_soc_device_early_init()
> > that already prevents the code from doing anything nonsensical on non-
> > STB platforms.
> >
> > Fixes: f780429adfbc ("soc: brcmstb: biuctrl: Move to early_initcall")
> > Signed-off-by: Thierry Reding <treding@nvidia.com>
> > ---
> > drivers/soc/bcm/brcmstb/common.c | 5 +++++
> > 1 file changed, 5 insertions(+)
> >
> > diff --git a/drivers/soc/bcm/brcmstb/common.c b/drivers/soc/bcm/brcmstb/common.c
> > index 781ada62d0a3..4fe1cb73b39a 100644
> > --- a/drivers/soc/bcm/brcmstb/common.c
> > +++ b/drivers/soc/bcm/brcmstb/common.c
> > @@ -89,8 +89,13 @@ early_initcall(brcmstb_soc_device_early_init);
> > static int __init brcmstb_soc_device_init(void)
> > {
> > struct soc_device_attribute *soc_dev_attr;
> > + struct device_node *sun_top_ctrl;
> > struct soc_device *soc_dev;
> >
> > + sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
> > + if (!sun_top_ctrl)
> > + return -ENODEV;
> > +
>
> missing of_node_put(sun_top_ctrl) ? or am I missing to see that elsewhere ?
Hm... you're right. I was blindly copying this from
brcmstb_soc_device_early() which doesn't have the of_node_put() either.
Let me fix this up with another couple of patches.
Thanks,
Thierry
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^ permalink raw reply
* [PATCH] soc: brcmstb: Only register SoC device on STB platforms
From: Thierry Reding @ 2018-01-12 12:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <973b2445-48ca-87a9-b4c2-21d8bfec76dd@arm.com>
On Fri, Jan 12, 2018 at 12:12:11PM +0000, Sudeep Holla wrote:
>
>
> On 12/01/18 11:39, Sudeep Holla wrote:
> >
> >
> > On 09/01/18 14:54, Thierry Reding wrote:
> >> From: Thierry Reding <treding@nvidia.com>
> >>
> >> After moving the SoC device initialization to an early initcall in
> >> commit f780429adfbc ("soc: brcmstb: biuctrl: Move to early_initcall"),
> >> the Broadcom STB SoC device is registered on all platforms if support
> >> for the device is enabled in the kernel configuration.
> >>
> >> This causes an additional SoC device to appear on platforms that already
> >> register a native one. In case of Tegra the STB SoC device is registered
> >> as soc0 (with totally meaningless content in the sysfs attributes) and
> >> causes various scripts and programs to fail because they don't know how
> >> to parse that data.
> >>
> >> To fix this, duplicate the check from brcmstb_soc_device_early_init()
> >> that already prevents the code from doing anything nonsensical on non-
> >> STB platforms.
> >>
> >> Fixes: f780429adfbc ("soc: brcmstb: biuctrl: Move to early_initcall")
> >> Signed-off-by: Thierry Reding <treding@nvidia.com>
> >> ---
> >> drivers/soc/bcm/brcmstb/common.c | 5 +++++
> >> 1 file changed, 5 insertions(+)
> >>
> >> diff --git a/drivers/soc/bcm/brcmstb/common.c b/drivers/soc/bcm/brcmstb/common.c
> >> index 781ada62d0a3..4fe1cb73b39a 100644
> >> --- a/drivers/soc/bcm/brcmstb/common.c
> >> +++ b/drivers/soc/bcm/brcmstb/common.c
> >> @@ -89,8 +89,13 @@ early_initcall(brcmstb_soc_device_early_init);
> >> static int __init brcmstb_soc_device_init(void)
> >> {
> >> struct soc_device_attribute *soc_dev_attr;
> >> + struct device_node *sun_top_ctrl;
> >> struct soc_device *soc_dev;
> >>
> >> + sun_top_ctrl = of_find_matching_node(NULL, sun_top_ctrl_match);
> >> + if (!sun_top_ctrl)
> >> + return -ENODEV;
> >> +
> >
> > missing of_node_put(sun_top_ctrl) ? or am I missing to see that elsewhere ?
> >
>
> Further, I still the error messags on my Juno with this patch applied. I
> fail to see how this patch prevents brcmstb_biuctrl_init which is
> early_initcall in drivers/soc/bcm/brcmstb/biuctrl.c getting called ?
I'm not sure I understand. There's no way we can prevent the early
initcall from running. The point here is to prevent it from running code
that shouldn't be run on a platform.
That said, perhaps an even better thing would be to return 0 in order to
avoid marking this as failure, since it really isn't an error if this
happens.
Thierry
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^ permalink raw reply
* [PULL 0/2] KVM/ARM Fixes for v4.15 - Round 3
From: Paolo Bonzini @ 2018-01-12 12:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180112123334.28687-1-christoffer.dall@linaro.org>
On 12/01/2018 13:33, Christoffer Dall wrote:
> Hi Paolo and Radim,
>
> This is the third round of fixes for KVM/ARM for v4.15, including two more
> fixes for v4.15 fixing incorrect huge page mappings on systems using the
> contiguous hint for hugetlbfs and supporting an alternative GICv4 init
> sequence.
>
> The following changes since commit 0eb7c33cadf6b2f1a94e58ded8b0eb89b4eba382:
>
> KVM: arm/arm64: Fix timer enable flow (2017-12-18 10:53:24 +0100)
>
> are available in the git repository at:
>
> git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git tags/kvm-arm-fixes-for-v4.15-3
>
> for you to fetch changes up to f8f85dc00b7427de6222ea3955c52512315d13cd:
>
> KVM: arm64: Fix GICv4 init when called from vgic_its_create (2018-01-12 11:40:21 +0100)
>
> Thanks,
> -Christoffer
>
> Christoffer Dall (1):
> KVM: arm64: Fix GICv4 init when called from vgic_its_create
>
> Punit Agrawal (1):
> KVM: arm/arm64: Check pagesize when allocating a hugepage at Stage 2
>
> virt/kvm/arm/mmu.c | 2 +-
> virt/kvm/arm/vgic/vgic-init.c | 8 +++++---
> virt/kvm/arm/vgic/vgic-v4.c | 2 +-
> 3 files changed, 7 insertions(+), 5 deletions(-)
>
Oops, missed this by a few minutes. :(
We'll send it next week.
Paolo
^ permalink raw reply
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