* [PATCH v1 03/13] drm/kms/mode/exynos-dsi: using helper func drm_display_mode_to_videomode for calculating timing parameters
From: Robin Murphy @ 2018-05-04 11:25 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525421726-2817-1-git-send-email-satendra.t@samsung.com>
On 04/05/18 09:15, Satendra Singh Thakur wrote:
> To avoid duplicate logic for the same
>
> Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Please read section 13 of Documentation/process/submitting-patches.rst
for what this tag means; specifically, it is definitely not "this guy
read my patch".
FWIW, in my case the patches I give trivial coding style comments on
tend to be the ones I'm specifically *not* in a position to review in a
technical capacity - the reason I'm looking at them in the first place
is out of interest to learn more about how the relevant subsystems work.
Robin.
> Signed-off-by: Satendra Singh Thakur <satendra.t@samsung.com>
> Acked-by: Madhur Verma <madhur.verma@samsung.com>
> Cc: Hemanshu Srivastava <hemanshu.s@samsung.com>
> ---
> drivers/gpu/drm/exynos/exynos_drm_dsi.c | 13 ++-----------
> 1 file changed, 2 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/exynos/exynos_drm_dsi.c b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> index 7904ffa..7fe84fd 100644
> --- a/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> +++ b/drivers/gpu/drm/exynos/exynos_drm_dsi.c
> @@ -1490,17 +1490,8 @@ static void exynos_dsi_mode_set(struct drm_encoder *encoder,
> struct drm_display_mode *adjusted_mode)
> {
> struct exynos_dsi *dsi = encoder_to_dsi(encoder);
> - struct videomode *vm = &dsi->vm;
> - struct drm_display_mode *m = adjusted_mode;
> -
> - vm->hactive = m->hdisplay;
> - vm->vactive = m->vdisplay;
> - vm->vfront_porch = m->vsync_start - m->vdisplay;
> - vm->vback_porch = m->vtotal - m->vsync_end;
> - vm->vsync_len = m->vsync_end - m->vsync_start;
> - vm->hfront_porch = m->hsync_start - m->hdisplay;
> - vm->hback_porch = m->htotal - m->hsync_end;
> - vm->hsync_len = m->hsync_end - m->hsync_start;
> +
> + drm_display_mode_to_videomode(adjusted_mode, &dsi->vm);
> }
>
> static const struct drm_encoder_helper_funcs exynos_dsi_encoder_helper_funcs = {
>
^ permalink raw reply
* [PATCH 2/2] arm64: Clear the stack
From: Mark Rutland @ 2018-05-04 11:16 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <a8ce3e4d-f0f3-1321-92af-9aed0097d205@redhat.com>
On Thu, May 03, 2018 at 12:00:26PM -0700, Laura Abbott wrote:
> On 05/03/2018 12:19 AM, Mark Rutland wrote:
> > On Wed, May 02, 2018 at 01:33:26PM -0700, Laura Abbott wrote:
> > > +asmlinkage void erase_kstack(void)
> > > +{
> > > +
> > > + /*
> > > + * So let's write the poison value to the kernel stack.
> > > + * Start from the address in p and move up till the new boundary.
> > > + */
> > > + boundary = current_stack_pointer;
> >
> > I worry a little that the compiler can move the SP during a function's
> > lifetime, but maybe that's only the case when there are VLAs, or something like
> > that?
>
> I think that's true and a risk we take writing this in C. Here's
> the disassembly on gcc-7.3.1:
>
> ffff00000809d4d8 <erase_kstack>:
> ffff00000809d4d8: a9bf7bfd stp x29, x30, [sp, #-16]!
> ffff00000809d4dc: d5384100 mrs x0, sp_el0
> ffff00000809d4e0: 910003fd mov x29, sp
> ffff00000809d4e4: f946e400 ldr x0, [x0, #3528]
> ffff00000809d4e8: 9272c404 and x4, x0, #0xffffffffffffc000
> ffff00000809d4ec: eb04001f cmp x0, x4
> ffff00000809d4f0: 540002c9 b.ls ffff00000809d548 <erase_kstack+0x70> // b.plast
> ffff00000809d4f4: d2800003 mov x3, #0x0 // #0
> ffff00000809d4f8: 9297ddc5 mov x5, #0xffffffffffff4111 // #-48879
> ffff00000809d4fc: 14000008 b ffff00000809d51c <erase_kstack+0x44>
> ffff00000809d500: d1002000 sub x0, x0, #0x8
> ffff00000809d504: 52800022 mov w2, #0x1 // #1
> ffff00000809d508: eb00009f cmp x4, x0
> ffff00000809d50c: d2800003 mov x3, #0x0 // #0
> ffff00000809d510: 1a9f27e1 cset w1, cc // cc = lo, ul, last
> ffff00000809d514: 6a01005f tst w2, w1
> ffff00000809d518: 54000180 b.eq ffff00000809d548 <erase_kstack+0x70> // b.none
> ffff00000809d51c: f9400001 ldr x1, [x0]
> ffff00000809d520: eb05003f cmp x1, x5
> ffff00000809d524: 54fffee1 b.ne ffff00000809d500 <erase_kstack+0x28> // b.any
> ffff00000809d528: 91000463 add x3, x3, #0x1
> ffff00000809d52c: d1002000 sub x0, x0, #0x8
> ffff00000809d530: f100407f cmp x3, #0x10
> ffff00000809d534: 1a9f87e2 cset w2, ls // ls = plast
> ffff00000809d538: eb00009f cmp x4, x0
> ffff00000809d53c: 1a9f27e1 cset w1, cc // cc = lo, ul, last
> ffff00000809d540: 6a01005f tst w2, w1
> ffff00000809d544: 54fffec1 b.ne ffff00000809d51c <erase_kstack+0x44> // b.any
> ffff00000809d548: eb00009f cmp x4, x0
> ffff00000809d54c: 91002001 add x1, x0, #0x8
> ffff00000809d550: 9a800020 csel x0, x1, x0, eq // eq = none
> ffff00000809d554: 910003e1 mov x1, sp
> ffff00000809d558: d5384102 mrs x2, sp_el0
> ffff00000809d55c: f906e840 str x0, [x2, #3536]
> ffff00000809d560: cb000023 sub x3, x1, x0
> ffff00000809d564: d287ffe2 mov x2, #0x3fff // #16383
> ffff00000809d568: eb02007f cmp x3, x2
> ffff00000809d56c: 540001a8 b.hi ffff00000809d5a0 <erase_kstack+0xc8> // b.pmore
> ffff00000809d570: 9297ddc2 mov x2, #0xffffffffffff4111 // #-48879
> ffff00000809d574: eb01001f cmp x0, x1
> ffff00000809d578: 54000082 b.cs ffff00000809d588 <erase_kstack+0xb0> // b.hs, b.nlast
> ffff00000809d57c: f8008402 str x2, [x0], #8
> ffff00000809d580: eb00003f cmp x1, x0
> ffff00000809d584: 54ffffc8 b.hi ffff00000809d57c <erase_kstack+0xa4> // b.pmore
> ffff00000809d588: 910003e1 mov x1, sp
> ffff00000809d58c: d5384100 mrs x0, sp_el0
> ffff00000809d590: f906e401 str x1, [x0, #3528]
> ffff00000809d594: a8c17bfd ldp x29, x30, [sp], #16
> ffff00000809d598: d65f03c0 ret
> ffff00000809d59c: d503201f nop
> ffff00000809d5a0: d4210000 brk #0x800
> ffff00000809d5a4: 00000000 .inst 0x00000000 ; undefined
>
> It looks to be okay although admittedly that's subject to compiler
> whims. It might be safer to save the stack pointer almost as soon as
> we get into the function and use that?
I think that's still potentially a problem. If the compiler expands the
stack frame after we've taken a snaphot of the stack pointer, we might
end up erasing portions of the active stackframe.
Maybe we should just document we rely on the compiler not doing that,
and if we end up seeing it in practice we rewrite this in asm? I can't
think of a simple way we can auto-detect if this happens. :/
Thanks,
Mark.
^ permalink raw reply
* [PATCH 2/2] arm64: Clear the stack
From: Mark Rutland @ 2018-05-04 11:09 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <dd6ad26c-1d2c-88f3-8f01-e68d2b31d6ea@linux.com>
On Thu, May 03, 2018 at 08:33:38PM +0300, Alexander Popov wrote:
> Hello Mark and Laura,
>
> Let me join the discussion. Mark, thanks for your feedback!
>
> On 03.05.2018 10:19, Mark Rutland wrote:
> > Hi Laura,
> >
> > On Wed, May 02, 2018 at 01:33:26PM -0700, Laura Abbott wrote:
> >>
> >> Implementation of stackleak based heavily on the x86 version
> >>
> >> Signed-off-by: Laura Abbott <labbott@redhat.com>
> >> ---
> >> Now written in C instead of a bunch of assembly.
> >
> > This looks neat!
> >
> > I have a few minor comments below.
> >
> >> diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
> >> index bf825f38d206..0ceea613c65b 100644
> >> --- a/arch/arm64/kernel/Makefile
> >> +++ b/arch/arm64/kernel/Makefile
> >> @@ -55,6 +55,9 @@ arm64-reloc-test-y := reloc_test_core.o reloc_test_syms.o
> >> arm64-obj-$(CONFIG_CRASH_DUMP) += crash_dump.o
> >> arm64-obj-$(CONFIG_ARM_SDE_INTERFACE) += sdei.o
> >>
> >> +arm64-obj-$(CONFIG_GCC_PLUGIN_STACKLEAK) += erase.o
> >> +KASAN_SANITIZE_erase.o := n
> >
> > I suspect we want to avoid the full set of instrumentation suspects here, e.g.
> > GKOV, KASAN, UBSAN, and KCOV.
>
> I've disabled KASAN instrumentation for that file on x86 because erase_kstack()
> intentionally writes to the stack and causes KASAN false positive reports.
>
> But I didn't see any conflicts with other types of instrumentation that you
> mentioned.
The rationale is that any of these can result in implicit calls to C
functions at arbitrary points during erase_kstack(). That could
interfere with the search for poison, and/or leave data on the stack
which is not erased.
They won't result in hard failures, as KASAN would, but we should
probably avoid them regardless.
[...]
> >> +asmlinkage void erase_kstack(void)
> >> +{
> >> + unsigned long p = current->thread.lowest_stack;
> >> + unsigned long boundary = p & ~(THREAD_SIZE - 1);
> >> + unsigned long poison = 0;
> >> + const unsigned long check_depth = STACKLEAK_POISON_CHECK_DEPTH /
> >> + sizeof(unsigned long);
> >> +
> >> + /*
> >> + * Let's search for the poison value in the stack.
> >> + * Start from the lowest_stack and go to the bottom.
> >> + */
> >> + while (p > boundary && poison <= check_depth) {
> >> + if (*(unsigned long *)p == STACKLEAK_POISON)
> >> + poison++;
> >> + else
> >> + poison = 0;
> >> +
> >> + p -= sizeof(unsigned long);
> >> + }
> >> +
> >> + /*
> >> + * One long int at the bottom of the thread stack is reserved and
> >> + * should not be poisoned (see CONFIG_SCHED_STACK_END_CHECK).
> >> + */
> >> + if (p == boundary)
> >> + p += sizeof(unsigned long);
> >
> > I wonder if end_of_stack() should be taught about CONFIG_SCHED_STACK_END_CHECK,
> > given that's supposed to return the last *usable* long on the stack, and we
> > don't account for this elsewhere.
>
> I would be afraid to change the meaning of end_of_stack()... Currently it
> considers that magic long as usable (include/linux/sched/task_stack.h):
>
> #define task_stack_end_corrupted(task) \
> (*(end_of_stack(task)) != STACK_END_MAGIC)
>
>
> > If we did, then IIUC we could do:
> >
> > unsigned long boundary = (unsigned long)end_of_stack(current);
> >
> > ... at the start of the function, and not have to worry about this explicitly.
>
> I should mention that erase_kstack() can be called from x86 trampoline stack.
> That's why the boundary is calculated from the lowest_stack.
Ok. Under what circumstances does that happen?
It seems a little scary that curent::thread::lowest_stack might not be
on current's task stack. Is that reset when transitioning to/from the
trampoile stack?
[...]
> >> +#ifdef CONFIG_GCC_PLUGIN_STACKLEAK
> >> +void __used check_alloca(unsigned long size)
> >> +{
> >> + unsigned long sp, stack_left;
> >> +
> >> + sp = current_stack_pointer;
> >> +
> >> + stack_left = sp & (THREAD_SIZE - 1);
> >> + BUG_ON(stack_left < 256 || size >= stack_left - 256);
> >> +}
> >
> > Is this arbitrary, or is there something special about 256?
> >
> > Even if this is arbitrary, can we give it some mnemonic?
>
> It's just a reasonable number. We can introduce a macro for it.
I'm just not sure I see the point in the offset, given things like
VMAP_STACK exist. BUG_ON() handling will likely require *more* than 256
bytes of stack, so it seems superfluous, as we'd be relying on stack
overflow detection at that point.
I can see that we should take the CONFIG_SCHED_STACK_END_CHECK offset
into account, though.
> >> +EXPORT_SYMBOL(check_alloca);
> >> +#endif
> >> diff --git a/drivers/firmware/efi/libstub/Makefile b/drivers/firmware/efi/libstub/Makefile
> >> index a34e9290a699..25dd2a14560d 100644
> >> --- a/drivers/firmware/efi/libstub/Makefile
> >> +++ b/drivers/firmware/efi/libstub/Makefile
> >> @@ -20,7 +20,8 @@ cflags-$(CONFIG_EFI_ARMSTUB) += -I$(srctree)/scripts/dtc/libfdt
> >> KBUILD_CFLAGS := $(cflags-y) -DDISABLE_BRANCH_PROFILING \
> >> -D__NO_FORTIFY \
> >> $(call cc-option,-ffreestanding) \
> >> - $(call cc-option,-fno-stack-protector)
> >> + $(call cc-option,-fno-stack-protector) \
> >> + $(DISABLE_STACKLEAK_PLUGIN)
> >>
> >> GCOV_PROFILE := n
> >> KASAN_SANITIZE := n
> >
> > I believe we'll also need to do this for the KVM hyp code in arch/arm64/kvm/hyp/.
>
> Could you please give more details on that? Why STACKLEAK breaks it?
In the hyp/EL2 exception level, we only map the hyp text, and not the
rest of the kernel. So erase_kstack and check_alloca won't be mapped,
and attempt to branch to them will fault.
Even if it were mapped, things like BUG_ON(), get_current(), etc do not
work at hyp.
Additionally, the hyp code is mapped as a different virtual address from
the rest of the kernel, so if any of the STACKLEAK code happens to use
an absolute address, this will not work correctly.
Thanks,
Mark.
^ permalink raw reply
* Potential deadlock in vgic
From: Jan Glauber @ 2018-05-04 11:03 UTC (permalink / raw)
To: linux-arm-kernel
Hi all,
enabling lockdep I see the following reported in the host when I start a kvm guest:
[12399.954245] CPU0 CPU1
[12399.958762] ---- ----
[12399.963279] lock(&(&dist->lpi_list_lock)->rlock);
[12399.968146] local_irq_disable();
[12399.974052] lock(&(&vgic_cpu->ap_list_lock)->rlock);
[12399.981696] lock(&(&dist->lpi_list_lock)->rlock);
[12399.989081] <Interrupt>
[12399.991688] lock(&(&vgic_cpu->ap_list_lock)->rlock);
[12399.996989]
*** DEADLOCK ***
[12400.002897] 2 locks held by qemu-system-aar/5597:
[12400.007587] #0: 0000000042beb9dc (&vcpu->mutex){+.+.}, at: kvm_vcpu_ioctl+0x7c/0xa68
[12400.015411] #1: 00000000c45d644a (&(&vgic_cpu->ap_list_lock)->rlock){-.-.}, at: kvm_vgic_sync_hwstate+0x8c/0x328
There is nothing unusual in my config or qemu parameters, I can upload these
if needed. I see this on ThunderX and ThunderX2 and also with older kernels
(4.13+ distribution kernel).
I tried making the lpi_list_lock irq safe but that just leads to different
warnings. The locking here seems to be quite sophisticated and I'm not familiar
with it.
Full dmesg: https://paste.ubuntu.com/p/BZ5QTg62Ym/
--Jan
^ permalink raw reply
* [PATCH] arm/unwind: use a raw_spin_lock
From: Sebastian Andrzej Siewior @ 2018-05-04 10:56 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504105600.20613-1-bigeasy@linutronix.de>
Mostly unwind is done with irqs enabled however SLUB may call it with
irqs disabled while creating a new SLUB cache.
I had system freeze while loading a module which called
kmem_cache_create() on init. That means SLUB's __slab_alloc() disabled
interrupts and then
->new_slab_objects()
->new_slab()
->setup_object()
->setup_object_debug()
->init_tracking()
->set_track()
->save_stack_trace()
->save_stack_trace_tsk()
->walk_stackframe()
->unwind_frame()
->unwind_find_idx()
=>spin_lock_irqsave(&unwind_lock);
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/kernel/unwind.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
--- a/arch/arm/kernel/unwind.c
+++ b/arch/arm/kernel/unwind.c
@@ -93,7 +93,7 @@ extern const struct unwind_idx __start_u
static const struct unwind_idx *__origin_unwind_idx;
extern const struct unwind_idx __stop_unwind_idx[];
-static DEFINE_SPINLOCK(unwind_lock);
+static DEFINE_RAW_SPINLOCK(unwind_lock);
static LIST_HEAD(unwind_tables);
/* Convert a prel31 symbol to an absolute address */
@@ -201,7 +201,7 @@ static const struct unwind_idx *unwind_f
/* module unwind tables */
struct unwind_table *table;
- spin_lock_irqsave(&unwind_lock, flags);
+ raw_spin_lock_irqsave(&unwind_lock, flags);
list_for_each_entry(table, &unwind_tables, list) {
if (addr >= table->begin_addr &&
addr < table->end_addr) {
@@ -213,7 +213,7 @@ static const struct unwind_idx *unwind_f
break;
}
}
- spin_unlock_irqrestore(&unwind_lock, flags);
+ raw_spin_unlock_irqrestore(&unwind_lock, flags);
}
pr_debug("%s: idx = %p\n", __func__, idx);
@@ -529,9 +529,9 @@ struct unwind_table *unwind_table_add(un
tab->begin_addr = text_addr;
tab->end_addr = text_addr + text_size;
- spin_lock_irqsave(&unwind_lock, flags);
+ raw_spin_lock_irqsave(&unwind_lock, flags);
list_add_tail(&tab->list, &unwind_tables);
- spin_unlock_irqrestore(&unwind_lock, flags);
+ raw_spin_unlock_irqrestore(&unwind_lock, flags);
return tab;
}
@@ -543,9 +543,9 @@ void unwind_table_del(struct unwind_tabl
if (!tab)
return;
- spin_lock_irqsave(&unwind_lock, flags);
+ raw_spin_lock_irqsave(&unwind_lock, flags);
list_del(&tab->list);
- spin_unlock_irqrestore(&unwind_lock, flags);
+ raw_spin_unlock_irqrestore(&unwind_lock, flags);
kfree(tab);
}
^ permalink raw reply
* [PATCH] arm: kprobe: replace patch_lock to raw lock
From: Sebastian Andrzej Siewior @ 2018-05-04 10:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504105600.20613-1-bigeasy@linutronix.de>
From: Yang Shi <yang.shi@linaro.org>
When running kprobe on -rt kernel, the below bug is caught:
BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:931
in_atomic(): 1, irqs_disabled(): 128, pid: 14, name: migration/0
INFO: lockdep is turned off.
irq event stamp: 238
hardirqs last enabled at (237): [<80b5aecc>] _raw_spin_unlock_irqrestore+0x88/0x90
hardirqs last disabled at (238): [<80b56d88>] __schedule+0xec/0x94c
softirqs last enabled at (0): [<80225584>] copy_process.part.5+0x30c/0x1994
softirqs last disabled at (0): [< (null)>] (null)
Preemption disabled at:[<802f2b98>] cpu_stopper_thread+0xc0/0x140
CPU: 0 PID: 14 Comm: migration/0 Tainted: G O 4.8.3-rt2 #1
Hardware name: Freescale LS1021A
[<80212e7c>] (unwind_backtrace) from [<8020cd2c>] (show_stack+0x20/0x24)
[<8020cd2c>] (show_stack) from [<80689e14>] (dump_stack+0xa0/0xcc)
[<80689e14>] (dump_stack) from [<8025a43c>] (___might_sleep+0x1b8/0x2a4)
[<8025a43c>] (___might_sleep) from [<80b5b324>] (rt_spin_lock+0x34/0x74)
[<80b5b324>] (rt_spin_lock) from [<80b5c31c>] (__patch_text_real+0x70/0xe8)
[<80b5c31c>] (__patch_text_real) from [<80b5c3ac>] (patch_text_stop_machine+0x18/0x20)
[<80b5c3ac>] (patch_text_stop_machine) from [<802f2920>] (multi_cpu_stop+0xfc/0x134)
[<802f2920>] (multi_cpu_stop) from [<802f2ba0>] (cpu_stopper_thread+0xc8/0x140)
[<802f2ba0>] (cpu_stopper_thread) from [<802563a4>] (smpboot_thread_fn+0x1a4/0x354)
[<802563a4>] (smpboot_thread_fn) from [<80251d38>] (kthread+0x104/0x11c)
[<80251d38>] (kthread) from [<80207f70>] (ret_from_fork+0x14/0x24)
Since patch_text_stop_machine() is called in stop_machine() which disables IRQ,
sleepable lock should be not used in this atomic context, so replace patch_lock
to raw lock.
Cc: Russell King <linux@armlinux.org.uk>
Signed-off-by: Yang Shi <yang.shi@linaro.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/kernel/patch.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
--- a/arch/arm/kernel/patch.c
+++ b/arch/arm/kernel/patch.c
@@ -16,7 +16,7 @@ struct patch {
unsigned int insn;
};
-static DEFINE_SPINLOCK(patch_lock);
+static DEFINE_RAW_SPINLOCK(patch_lock);
static void __kprobes *patch_map(void *addr, int fixmap, unsigned long *flags)
__acquires(&patch_lock)
@@ -33,7 +33,7 @@ static void __kprobes *patch_map(void *a
return addr;
if (flags)
- spin_lock_irqsave(&patch_lock, *flags);
+ raw_spin_lock_irqsave(&patch_lock, *flags);
else
__acquire(&patch_lock);
@@ -48,7 +48,7 @@ static void __kprobes patch_unmap(int fi
clear_fixmap(fixmap);
if (flags)
- spin_unlock_irqrestore(&patch_lock, *flags);
+ raw_spin_unlock_irqrestore(&patch_lock, *flags);
else
__release(&patch_lock);
}
^ permalink raw reply
* [PATCH] arm: Convert arm boot_lock to raw
From: Sebastian Andrzej Siewior @ 2018-05-04 10:55 UTC (permalink / raw)
To: linux-arm-kernel
From: Frank Rowand <frank.rowand@am.sony.com>
The arm boot_lock is used by the secondary processor startup code. The locking
task is the idle thread, which has idle->sched_class == &idle_sched_class.
idle_sched_class->enqueue_task == NULL, so if the idle task blocks on the
lock, the attempt to wake it when the lock becomes available will fail:
try_to_wake_up()
...
activate_task()
enqueue_task()
p->sched_class->enqueue_task(rq, p, flags)
Fix by converting boot_lock to a raw spin lock.
Cc: "Andreas F?rber" <afaerber@suse.de>
Cc: Russell King <linux@armlinux.org.uk>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Wei Xu <xuwei5@hisilicon.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Barry Song <baohua@kernel.org>
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Viresh Kumar <vireshk@kernel.org>
Cc: Shiraz Hashim <shiraz.linux.kernel@gmail.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-samsung-soc at vger.kernel.org
Cc: linux-omap at vger.kernel.org
Cc: linux-arm-msm at vger.kernel.org
Cc: linux-soc at vger.kernel.org
Signed-off-by: Frank Rowand <frank.rowand@am.sony.com>
Link: http://lkml.kernel.org/r/4E77B952.3010606 at am.sony.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
[bigeasy: added new boot_lock user]
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
arch/arm/mach-actions/platsmp.c | 6 +++---
arch/arm/mach-exynos/platsmp.c | 12 ++++++------
arch/arm/mach-hisi/platmcpm.c | 22 +++++++++++-----------
arch/arm/mach-omap2/omap-smp.c | 10 +++++-----
arch/arm/mach-prima2/platsmp.c | 10 +++++-----
arch/arm/mach-qcom/platsmp.c | 10 +++++-----
arch/arm/mach-spear/platsmp.c | 10 +++++-----
arch/arm/mach-sti/platsmp.c | 10 +++++-----
arch/arm/mach-sunxi/mc_smp.c | 20 ++++++++++----------
arch/arm/plat-versatile/platsmp.c | 10 +++++-----
10 files changed, 60 insertions(+), 60 deletions(-)
--- a/arch/arm/mach-actions/platsmp.c
+++ b/arch/arm/mach-actions/platsmp.c
@@ -39,7 +39,7 @@ static void __iomem *sps_base_addr;
static void __iomem *timer_base_addr;
static int ncores;
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
void owl_secondary_startup(void);
@@ -93,7 +93,7 @@ static int s500_smp_boot_secondary(unsig
udelay(10);
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
smp_send_reschedule(cpu);
@@ -106,7 +106,7 @@ static int s500_smp_boot_secondary(unsig
writel(0, timer_base_addr + OWL_CPU1_ADDR + (cpu - 1) * 4);
writel(0, timer_base_addr + OWL_CPU1_FLAG + (cpu - 1) * 4);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return 0;
}
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -224,7 +224,7 @@ static void __iomem *scu_base_addr(void)
return (void __iomem *)(S5P_VA_SCU);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void exynos_secondary_init(unsigned int cpu)
{
@@ -237,8 +237,8 @@ static void exynos_secondary_init(unsign
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
int exynos_set_boot_addr(u32 core_id, unsigned long boot_addr)
@@ -302,7 +302,7 @@ static int exynos_boot_secondary(unsigne
* Set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -329,7 +329,7 @@ static int exynos_boot_secondary(unsigne
if (timeout == 0) {
printk(KERN_ERR "cpu1 power enable failed");
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return -ETIMEDOUT;
}
}
@@ -375,7 +375,7 @@ static int exynos_boot_secondary(unsigne
* calibrations, then wait for it to finish
*/
fail:
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? ret : 0;
}
--- a/arch/arm/mach-hisi/platmcpm.c
+++ b/arch/arm/mach-hisi/platmcpm.c
@@ -61,7 +61,7 @@
static void __iomem *sysctrl, *fabric;
static int hip04_cpu_table[HIP04_MAX_CLUSTERS][HIP04_MAX_CPUS_PER_CLUSTER];
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static u32 fabric_phys_addr;
/*
* [0]: bootwrapper physical address
@@ -113,7 +113,7 @@ static int hip04_boot_secondary(unsigned
if (cluster >= HIP04_MAX_CLUSTERS || cpu >= HIP04_MAX_CPUS_PER_CLUSTER)
return -EINVAL;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
if (hip04_cpu_table[cluster][cpu])
goto out;
@@ -147,7 +147,7 @@ static int hip04_boot_secondary(unsigned
out:
hip04_cpu_table[cluster][cpu]++;
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 0;
}
@@ -162,11 +162,11 @@ static void hip04_cpu_die(unsigned int l
cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
hip04_cpu_table[cluster][cpu]--;
if (hip04_cpu_table[cluster][cpu] == 1) {
/* A power_up request went ahead of us. */
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return;
} else if (hip04_cpu_table[cluster][cpu] > 1) {
pr_err("Cluster %d CPU%d boots multiple times\n", cluster, cpu);
@@ -174,7 +174,7 @@ static void hip04_cpu_die(unsigned int l
}
last_man = hip04_cluster_is_down(cluster);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
if (last_man) {
/* Since it's Cortex A15, disable L2 prefetching. */
asm volatile(
@@ -203,7 +203,7 @@ static int hip04_cpu_kill(unsigned int l
cpu >= HIP04_MAX_CPUS_PER_CLUSTER);
count = TIMEOUT_MSEC / POLL_MSEC;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
for (tries = 0; tries < count; tries++) {
if (hip04_cpu_table[cluster][cpu])
goto err;
@@ -211,10 +211,10 @@ static int hip04_cpu_kill(unsigned int l
data = readl_relaxed(sysctrl + SC_CPU_RESET_STATUS(cluster));
if (data & CORE_WFI_STATUS(cpu))
break;
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
/* Wait for clean L2 when the whole cluster is down. */
msleep(POLL_MSEC);
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
}
if (tries >= count)
goto err;
@@ -231,10 +231,10 @@ static int hip04_cpu_kill(unsigned int l
goto err;
if (hip04_cluster_is_down(cluster))
hip04_set_snoop_filter(cluster, 0);
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 1;
err:
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 0;
}
#endif
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -69,7 +69,7 @@ static const struct omap_smp_config omap
.startup_addr = omap5_secondary_startup,
};
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
void __iomem *omap4_get_scu_base(void)
{
@@ -136,8 +136,8 @@ static void omap4_secondary_init(unsigne
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -150,7 +150,7 @@ static int omap4_boot_secondary(unsigned
* Set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* Update the AuxCoreBoot0 with boot state for secondary core.
@@ -229,7 +229,7 @@ static int omap4_boot_secondary(unsigned
* Now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return 0;
}
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -22,7 +22,7 @@
static void __iomem *clk_base;
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void sirfsoc_secondary_init(unsigned int cpu)
{
@@ -36,8 +36,8 @@ static void sirfsoc_secondary_init(unsig
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static const struct of_device_id clk_ids[] = {
@@ -75,7 +75,7 @@ static int sirfsoc_boot_secondary(unsign
/* make sure write buffer is drained */
mb();
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -107,7 +107,7 @@ static int sirfsoc_boot_secondary(unsign
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
--- a/arch/arm/mach-qcom/platsmp.c
+++ b/arch/arm/mach-qcom/platsmp.c
@@ -46,7 +46,7 @@
extern void secondary_startup_arm(void);
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
#ifdef CONFIG_HOTPLUG_CPU
static void qcom_cpu_die(unsigned int cpu)
@@ -60,8 +60,8 @@ static void qcom_secondary_init(unsigned
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int scss_release_secondary(unsigned int cpu)
@@ -284,7 +284,7 @@ static int qcom_boot_secondary(unsigned
* set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* Send the secondary CPU a soft interrupt, thereby causing
@@ -297,7 +297,7 @@ static int qcom_boot_secondary(unsigned
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return ret;
}
--- a/arch/arm/mach-spear/platsmp.c
+++ b/arch/arm/mach-spear/platsmp.c
@@ -32,7 +32,7 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
@@ -47,8 +47,8 @@ static void spear13xx_secondary_init(uns
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int spear13xx_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -59,7 +59,7 @@ static int spear13xx_boot_secondary(unsi
* set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -84,7 +84,7 @@ static int spear13xx_boot_secondary(unsi
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
--- a/arch/arm/mach-sti/platsmp.c
+++ b/arch/arm/mach-sti/platsmp.c
@@ -35,7 +35,7 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static void sti_secondary_init(unsigned int cpu)
{
@@ -48,8 +48,8 @@ static void sti_secondary_init(unsigned
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -60,7 +60,7 @@ static int sti_boot_secondary(unsigned i
* set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* The secondary processor is waiting to be released from
@@ -91,7 +91,7 @@ static int sti_boot_secondary(unsigned i
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
--- a/arch/arm/mach-sunxi/mc_smp.c
+++ b/arch/arm/mach-sunxi/mc_smp.c
@@ -369,7 +369,7 @@ static void __naked sunxi_mc_smp_seconda
);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
static bool sunxi_mc_smp_cluster_is_down(unsigned int cluster)
{
@@ -401,7 +401,7 @@ static int sunxi_mc_smp_boot_secondary(u
if (cluster >= SUNXI_NR_CLUSTERS || cpu >= SUNXI_CPUS_PER_CLUSTER)
return -EINVAL;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
if (sunxi_mc_smp_cpu_table[cluster][cpu])
goto out;
@@ -419,7 +419,7 @@ static int sunxi_mc_smp_boot_secondary(u
out:
sunxi_mc_smp_cpu_table[cluster][cpu]++;
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
return 0;
}
@@ -450,13 +450,13 @@ static void sunxi_mc_smp_cpu_die(unsigne
cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
pr_debug("%s: cluster %u cpu %u\n", __func__, cluster, cpu);
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
sunxi_mc_smp_cpu_table[cluster][cpu]--;
if (sunxi_mc_smp_cpu_table[cluster][cpu] == 1) {
/* A power_up request went ahead of us. */
pr_debug("%s: aborting due to a power up request\n",
__func__);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return;
} else if (sunxi_mc_smp_cpu_table[cluster][cpu] > 1) {
pr_err("Cluster %d CPU%d boots multiple times\n",
@@ -465,7 +465,7 @@ static void sunxi_mc_smp_cpu_die(unsigne
}
last_man = sunxi_mc_smp_cluster_is_down(cluster);
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
gic_cpu_if_down(0);
if (last_man)
@@ -541,11 +541,11 @@ static int sunxi_mc_smp_cpu_kill(unsigne
/* wait for CPU core to die and enter WFI */
count = TIMEOUT_USEC / POLL_USEC;
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
for (tries = 0; tries < count; tries++) {
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
usleep_range(POLL_USEC / 2, POLL_USEC);
- spin_lock_irq(&boot_lock);
+ raw_spin_lock_irq(&boot_lock);
/*
* If the user turns off a bunch of cores@the same
@@ -592,7 +592,7 @@ static int sunxi_mc_smp_cpu_kill(unsigne
sunxi_cluster_powerdown(cluster);
out:
- spin_unlock_irq(&boot_lock);
+ raw_spin_unlock_irq(&boot_lock);
pr_debug("%s: cluster %u cpu %u powerdown: %d\n",
__func__, cluster, cpu, ret);
return !ret;
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -32,7 +32,7 @@ static void write_pen_release(int val)
sync_cache_w(&pen_release);
}
-static DEFINE_SPINLOCK(boot_lock);
+static DEFINE_RAW_SPINLOCK(boot_lock);
void versatile_secondary_init(unsigned int cpu)
{
@@ -45,8 +45,8 @@ void versatile_secondary_init(unsigned i
/*
* Synchronise with the boot thread.
*/
- spin_lock(&boot_lock);
- spin_unlock(&boot_lock);
+ raw_spin_lock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
}
int versatile_boot_secondary(unsigned int cpu, struct task_struct *idle)
@@ -57,7 +57,7 @@ int versatile_boot_secondary(unsigned in
* Set synchronisation state between this boot processor
* and the secondary one
*/
- spin_lock(&boot_lock);
+ raw_spin_lock(&boot_lock);
/*
* This is really belt and braces; we hold unintended secondary
@@ -87,7 +87,7 @@ int versatile_boot_secondary(unsigned in
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
- spin_unlock(&boot_lock);
+ raw_spin_unlock(&boot_lock);
return pen_release != -1 ? -ENOSYS : 0;
}
^ permalink raw reply
* [PATCH] drivers/perf: arm-ccn: stop spamming dmesg in event_init
From: Mark Rutland @ 2018-05-04 10:41 UTC (permalink / raw)
To: linux-arm-kernel
The ARM CCN PMU driver uses dev_warn() to complain about parameters in
the user-provided perf_event_attr. This means that under normal
operation (e.g. a single invocation of the perf tool), dmesg may be
spammed with multiple messages.
Tools may issue multiple syscalls to probe for feature support, and
multiple applications (from multiple users) can attempt to open events
simultaneously, so this is not very helpful, even if a user happens to
have access to dmesg. Worse, this can push important information out of
the dmesg ring buffer, and can significantly slow down syscall fuzzers,
vastly increasing the time it takes to find critical bugs.
Demote the dev_warn() instances to dev_dbg(), as is the case for all
other PMU drivers under drivers/perf/. Users who wish to debug PMU event
initialisation can enable dynamic debug to receive these messages.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
---
drivers/perf/arm-ccn.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/perf/arm-ccn.c b/drivers/perf/arm-ccn.c
index 65b7e4042ece..07771e28f572 100644
--- a/drivers/perf/arm-ccn.c
+++ b/drivers/perf/arm-ccn.c
@@ -736,7 +736,7 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
ccn = pmu_to_arm_ccn(event->pmu);
if (hw->sample_period) {
- dev_warn(ccn->dev, "Sampling not supported!\n");
+ dev_dbg(ccn->dev, "Sampling not supported!\n");
return -EOPNOTSUPP;
}
@@ -744,12 +744,12 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
event->attr.exclude_kernel || event->attr.exclude_hv ||
event->attr.exclude_idle || event->attr.exclude_host ||
event->attr.exclude_guest) {
- dev_warn(ccn->dev, "Can't exclude execution levels!\n");
+ dev_dbg(ccn->dev, "Can't exclude execution levels!\n");
return -EINVAL;
}
if (event->cpu < 0) {
- dev_warn(ccn->dev, "Can't provide per-task data!\n");
+ dev_dbg(ccn->dev, "Can't provide per-task data!\n");
return -EOPNOTSUPP;
}
/*
@@ -771,13 +771,13 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
switch (type) {
case CCN_TYPE_MN:
if (node_xp != ccn->mn_id) {
- dev_warn(ccn->dev, "Invalid MN ID %d!\n", node_xp);
+ dev_dbg(ccn->dev, "Invalid MN ID %d!\n", node_xp);
return -EINVAL;
}
break;
case CCN_TYPE_XP:
if (node_xp >= ccn->num_xps) {
- dev_warn(ccn->dev, "Invalid XP ID %d!\n", node_xp);
+ dev_dbg(ccn->dev, "Invalid XP ID %d!\n", node_xp);
return -EINVAL;
}
break;
@@ -785,11 +785,11 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
break;
default:
if (node_xp >= ccn->num_nodes) {
- dev_warn(ccn->dev, "Invalid node ID %d!\n", node_xp);
+ dev_dbg(ccn->dev, "Invalid node ID %d!\n", node_xp);
return -EINVAL;
}
if (!arm_ccn_pmu_type_eq(type, ccn->node[node_xp].type)) {
- dev_warn(ccn->dev, "Invalid type 0x%x for node %d!\n",
+ dev_dbg(ccn->dev, "Invalid type 0x%x for node %d!\n",
type, node_xp);
return -EINVAL;
}
@@ -808,19 +808,19 @@ static int arm_ccn_pmu_event_init(struct perf_event *event)
if (event_id != e->event)
continue;
if (e->num_ports && port >= e->num_ports) {
- dev_warn(ccn->dev, "Invalid port %d for node/XP %d!\n",
+ dev_dbg(ccn->dev, "Invalid port %d for node/XP %d!\n",
port, node_xp);
return -EINVAL;
}
if (e->num_vcs && vc >= e->num_vcs) {
- dev_warn(ccn->dev, "Invalid vc %d for node/XP %d!\n",
+ dev_dbg(ccn->dev, "Invalid vc %d for node/XP %d!\n",
vc, node_xp);
return -EINVAL;
}
valid = 1;
}
if (!valid) {
- dev_warn(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
+ dev_dbg(ccn->dev, "Invalid event 0x%x for node/XP %d!\n",
event_id, node_xp);
return -EINVAL;
}
--
2.11.0
^ permalink raw reply related
* [PATCH REPOST] mfd: syscon: atmel-smc: include string.h
From: Sebastian Andrzej Siewior @ 2018-05-04 10:34 UTC (permalink / raw)
To: linux-arm-kernel
The string.h header file is needed for the memset() definition. The RT
build fails because it is not pulled in via other header files.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Nicolas Ferre <nicolas.ferre@microchip.com>
Cc: Alexandre Belloni <alexandre.belloni@bootlin.com>
Cc: linux-arm-kernel at lists.infradead.org
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
drivers/mfd/atmel-smc.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/mfd/atmel-smc.c
+++ b/drivers/mfd/atmel-smc.c
@@ -12,6 +12,7 @@
*/
#include <linux/mfd/syscon/atmel-smc.h>
+#include <linux/string.h>
/**
* atmel_smc_cs_conf_init - initialize a SMC CS conf
^ permalink raw reply
* [PATCH v2] tty/serial: atmel: use port->name as name in request_irq()
From: Richard Genoud @ 2018-05-04 10:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504081447.enontsm6jod4xa6g@linutronix.de>
On 04/05/2018 10:14, Sebastian Andrzej Siewior wrote:
> I was puzzled while looking at /proc/interrupts and random things showed
> up between reboots. This occurred more often but I realised it later. The
> "correct" output should be:
> |38: 11861 atmel-aic5 2 Level ttyS0
>
> but I saw sometimes
> |38: 6426 atmel-aic5 2 Level tty1
>
> and accounted it wrongly as correct. This is use after free and the
> former example randomly got the "old" pointer which pointed to the same
> content. With SLAB_FREELIST_RANDOM and HARDENED I even got
> |38: 7067 atmel-aic5 2 Level E=Started User Manager for UID 0
>
> or other nonsense.
> As it turns out the tty, pointer that is accessed in atmel_startup(), is
> freed() before atmel_shutdown(). It seems to happen quite often that the
> tty for ttyS0 is allocated and freed while ->shutdown is not invoked. I
> don't do anything special - just a systemd boot :)
>
> Use port->name as the IRQ name for request_irq(). This exists as long as
> the driver is loaded so no use-after-free here.
> For backports before v4.12 I suggest to use `"atmel_serial"' instead
> `port->name' (that member was introduced in f7048b15900f ("tty: serial_core:
> Add name field to uart_port struct").
>
> Cc: stable at vger.kernel.org
I think it's safer to use:
Cc: stable at vger.kernel.org # 4.14
Because the stable team may miss your comment, and even if they don't, I
think it's not their role to adapt the patch to 4.9.x (and test it !)
IMHO, the best way is to add # 4.14 and when it's applied on 4.14.x,
send a tested backport for 4.9.x
Besides that, you can add my:
Acked-by: Richard Genoud <richard.genoud@gmail.com>
Rob, do you agree with this fix ?
> Fixes: 761ed4a94582 ("tty: serial_core: convert uart_close to use tty_port_close")
> Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
> ---
> v1?v2: - Bisected and added a Fixes tag
> - added a note for backporters to v4.9 ? v4.12 (pointed out by
> Richard Genoud)
>
> drivers/tty/serial/atmel_serial.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
> index e287fe8f10fc..d3189816740e 100644
> --- a/drivers/tty/serial/atmel_serial.c
> +++ b/drivers/tty/serial/atmel_serial.c
> @@ -1757,7 +1757,6 @@ static int atmel_startup(struct uart_port *port)
> {
> struct platform_device *pdev = to_platform_device(port->dev);
> struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
> - struct tty_struct *tty = port->state->port.tty;
> int retval;
>
> /*
> @@ -1772,8 +1771,7 @@ static int atmel_startup(struct uart_port *port)
> * Allocate the IRQ
> */
> retval = request_irq(port->irq, atmel_interrupt,
> - IRQF_SHARED | IRQF_COND_SUSPEND,
> - tty ? tty->name : "atmel_serial", port);
> + IRQF_SHARED | IRQF_COND_SUSPEND, port->name, port);
> if (retval) {
> dev_err(port->dev, "atmel_startup - Can't get irq\n");
> return retval;
>
Thanks !
^ permalink raw reply
* [PATCH v2 2/6] arm64: alternative: Apply alternatives early in boot process
From: Julien Thierry @ 2018-05-04 10:06 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1516190084-18978-3-git-send-email-julien.thierry@arm.com>
Hi,
In order to prepare the v3 of this patchset, I'd like people's opinion
on what this patch does. More below.
On 17/01/18 11:54, Julien Thierry wrote:
> From: Daniel Thompson <daniel.thompson@linaro.org>
>
> Currently alternatives are applied very late in the boot process (and
> a long time after we enable scheduling). Some alternative sequences,
> such as those that alter the way CPU context is stored, must be applied
> much earlier in the boot sequence.
>
> Introduce apply_alternatives_early() to allow some alternatives to be
> applied immediately after we detect the CPU features of the boot CPU.
>
> Signed-off-by: Daniel Thompson <daniel.thompson@linaro.org>
> Signed-off-by: Julien Thierry <julien.thierry@arm.com>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm64/include/asm/alternative.h | 1 +
> arch/arm64/kernel/alternative.c | 39 +++++++++++++++++++++++++++++++++---
> arch/arm64/kernel/smp.c | 6 ++++++
> 3 files changed, 43 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/include/asm/alternative.h b/arch/arm64/include/asm/alternative.h
> index 4a85c69..1fc1cdb 100644
> --- a/arch/arm64/include/asm/alternative.h
> +++ b/arch/arm64/include/asm/alternative.h
> @@ -20,6 +20,7 @@ struct alt_instr {
> u8 alt_len; /* size of new instruction(s), <= orig_len */
> };
>
> +void __init apply_alternatives_early(void);
> void __init apply_alternatives_all(void);
> void apply_alternatives(void *start, size_t length);
>
> diff --git a/arch/arm64/kernel/alternative.c b/arch/arm64/kernel/alternative.c
> index 6dd0a3a3..78051d4 100644
> --- a/arch/arm64/kernel/alternative.c
> +++ b/arch/arm64/kernel/alternative.c
> @@ -28,6 +28,18 @@
> #include <asm/sections.h>
> #include <linux/stop_machine.h>
>
> +/*
> + * early-apply features are detected using only the boot CPU and checked on
> + * secondary CPUs startup, even then,
> + * These early-apply features should only include features where we must
> + * patch the kernel very early in the boot process.
> + *
> + * Note that the cpufeature logic *must* be made aware of early-apply
> + * features to ensure they are reported as enabled without waiting
> + * for other CPUs to boot.
> + */
> +#define EARLY_APPLY_FEATURE_MASK BIT(ARM64_HAS_SYSREG_GIC_CPUIF)
> +
Following the change in the cpufeature infrastructure,
ARM64_HAS_SYSREG_GIC_CPUIF will have the scope
ARM64_CPUCAP_SCOPE_BOOT_CPU in order to be checked early in the boot
process.
Now, regarding the early application of alternative, I am wondering
whether we can apply all the alternatives associated with SCOPE_BOOT
features that *do not* have a cpu_enable callback.
Otherwise we can keep the macro to list individually each feature that
is patchable at boot time as the current patch does (or put this info in
a flag within the arm64_cpu_capabilities structure).
Any thoughts or preferences on this?
Thanks,
> #define __ALT_PTR(a,f) ((void *)&(a)->f + (a)->f)
> #define ALT_ORIG_PTR(a) __ALT_PTR(a, orig_offset)
> #define ALT_REPL_PTR(a) __ALT_PTR(a, alt_offset)
> @@ -105,7 +117,8 @@ static u32 get_alt_insn(struct alt_instr *alt, __le32 *insnptr, __le32 *altinsnp
> return insn;
> }
>
> -static void __apply_alternatives(void *alt_region, bool use_linear_alias)
> +static void __apply_alternatives(void *alt_region, bool use_linear_alias,
> + unsigned long feature_mask)
> {
> struct alt_instr *alt;
> struct alt_region *region = alt_region;
> @@ -115,6 +128,9 @@ static void __apply_alternatives(void *alt_region, bool use_linear_alias)
> u32 insn;
> int i, nr_inst;
>
> + if ((BIT(alt->cpufeature) & feature_mask) == 0)
> + continue;
> +
> if (!cpus_have_cap(alt->cpufeature))
> continue;
>
> @@ -138,6 +154,21 @@ static void __apply_alternatives(void *alt_region, bool use_linear_alias)
> }
>
> /*
> + * This is called very early in the boot process (directly after we run
> + * a feature detect on the boot CPU). No need to worry about other CPUs
> + * here.
> + */
> +void apply_alternatives_early(void)
> +{
> + struct alt_region region = {
> + .begin = (struct alt_instr *)__alt_instructions,
> + .end = (struct alt_instr *)__alt_instructions_end,
> + };
> +
> + __apply_alternatives(®ion, true, EARLY_APPLY_FEATURE_MASK);
> +}
> +
> +/*
> * We might be patching the stop_machine state machine, so implement a
> * really simple polling protocol here.
> */
> @@ -156,7 +187,9 @@ static int __apply_alternatives_multi_stop(void *unused)
> isb();
> } else {
> BUG_ON(patched);
> - __apply_alternatives(®ion, true);
> +
> + __apply_alternatives(®ion, true, ~EARLY_APPLY_FEATURE_MASK);
> +
> /* Barriers provided by the cache flushing */
> WRITE_ONCE(patched, 1);
> }
> @@ -177,5 +210,5 @@ void apply_alternatives(void *start, size_t length)
> .end = start + length,
> };
>
> - __apply_alternatives(®ion, false);
> + __apply_alternatives(®ion, false, -1);
> }
> diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
> index 551eb07..37361b5 100644
> --- a/arch/arm64/kernel/smp.c
> +++ b/arch/arm64/kernel/smp.c
> @@ -453,6 +453,12 @@ void __init smp_prepare_boot_cpu(void)
> * cpuinfo_store_boot_cpu() above.
> */
> update_cpu_errata_workarounds();
> + /*
> + * We now know enough about the boot CPU to apply the
> + * alternatives that cannot wait until interrupt handling
> + * and/or scheduling is enabled.
> + */
> + apply_alternatives_early();
> }
>
> static u64 __init of_get_cpu_mpidr(struct device_node *dn)
> --
> 1.9.1
>
--
Julien Thierry
^ permalink raw reply
* [PATCH] ARM: dts: BCM5301X: Relicense Asus RT-AC87U file to the GPL 2.0+ / MIT
From: Rafał Miłecki @ 2018-05-04 10:03 UTC (permalink / raw)
To: linux-arm-kernel
From: Rafa? Mi?ecki <rafal@milecki.pl>
This matches licensing used by other BCM5301X files and is preferred as:
1) GPL 2.0+ makes is clearly compatible with Linux kernel
2) MIT is also permissive but preferred over ISC
This file were created and ever touched by a group of three people only:
?lvaro, Hauke and me.
Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
---
?lvaro, Hauke: I need approve for this change from each of you. If you
are OK with it, can you reply with an Acked-by, please?
---
arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
index df473cc41572..22271818f901 100644
--- a/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
+++ b/arch/arm/boot/dts/bcm4709-asus-rt-ac87u.dts
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for Asus RT-AC87U
*
* Copyright (C) 2015 Rafa? Mi?ecki <zajec5@gmail.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
- * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
*/
/dts-v1/;
--
2.13.6
^ permalink raw reply related
* [PATCH] ARM: dts: BCM5301X: Relicense Buffalo files to the GPL 2.0+ / MIT
From: Felix Fietkau @ 2018-05-04 10:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504095445.30918-1-zajec5@gmail.com>
On 2018-05-04 11:54, Rafa? Mi?ecki wrote:
> From: Rafa? Mi?ecki <rafal@milecki.pl>
>
> This matches licensing used by other BCM5301X files and is preferred as:
> 1) GPL 2.0+ makes is clearly compatible with Linux kernel
> 2) MIT is also permissive but preferred over ISC
>
> These files were created and ever touched by a group of four people
> only: Felix, INAGAKI, Hauke and me.
>
> Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
Acked-by: Felix Fietkau <nbd@nbd.name>
^ permalink raw reply
* [PATCH v9 07/27] ARM: davinci: dm355: add new clock init using common clock framework
From: Sekhar Nori @ 2018-05-04 10:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <18b7b217-7ccb-d2dd-8f2c-ba3ba0e5d893@lechnology.com>
On Thursday 03 May 2018 09:14 PM, David Lechner wrote:
> On 05/03/2018 10:34 AM, Sekhar Nori wrote:
>> On Friday 27 April 2018 05:47 AM, David Lechner wrote:
>>> This adds the new board-specific clock init in mach-davinci/dm355.c
>>> using the new common clock framework drivers.
>>>
>>> The #ifdefs are needed to prevent compile errors until the entire
>>> ARCH_DAVINCI is converted.
>>>
>>> Also clean up the #includes since we are adding some here.
>>>
>>> Signed-off-by: David Lechner <david@lechnology.com>
>>
>> I am having trouble booting DM355 EVM with the series applied.
>> Still to debug what is going wrong.
>
> Can you dump the PLL registers using /sys/kernel/debug/clk/... ?
I was able to get to ramdisk shell if I set clk_ignore_unused. Here is
the dump:
root at dm355-evm:/sys/kernel/debug# cat clk/clk_summary
enable prepare protect
clock count count count rate accuracy phase
----------------------------------------------------------------------------------------
ref_clk 1 1 0 24000000 0 0
oscin 3 3 0 24000000 0 0
pll2_sysclkbp 0 0 0 3000000 0 0
pll2_prediv 2 2 0 3000000 0 0
pll2_pllout 1 1 0 342000000 0 0
pll2_postdiv 1 1 0 342000000 0 0
pll2_pllen 0 0 0 342000000 0 0
pll1_sysclkbp 0 0 0 8000000 0 0
pll1_auxclk 4 5 0 24000000 0 0
timer2 1 4 0 24000000 0 0
timer1 0 0 0 24000000 0 0
timer0 2 2 0 24000000 0 0
pwm2 0 0 0 24000000 0 0
pwm1 0 0 0 24000000 0 0
pwm0 0 0 0 24000000 0 0
uart1 1 4 0 24000000 0 0
uart0 1 4 0 24000000 0 0
i2c 0 3 0 24000000 0 0
rto 0 0 0 24000000 0 0
pwm3 0 0 0 24000000 0 0
timer3 0 0 0 24000000 0 0
pll1_prediv 2 2 0 3000000 0 0
pll1_pllout 1 1 0 432000000 0 0
pll1_postdiv 1 1 0 432000000 0 0
pll1_pllen 0 0 0 432000000 0 0
pll2_sysclk2 1 1 0 0 0 0
pll2_sysclk1 0 0 0 0 0 0
pll1_sysclk4 1 3 0 0 0 0
vpss_slave 0 1 0 0 0 0
vpss_master 0 1 0 0 0 0
pll1_sysclk3 1 1 0 0 0 0
vpss_dac 0 0 0 0 0 0
pll1_sysclk2 4 5 0 0 0 0
gpio 1 1 0 0 0 0
spi0 0 3 0 0 0 0
uart2 1 4 0 0 0 0
asp0 0 0 0 0 0 0
mmcsd0 0 0 0 0 0 0
aemif 1 1 0 0 0 0
spi2 0 0 0 0 0 0
usb 0 0 0 0 0 0
asp1 0 0 0 0 0 0
mmcsd1 0 0 0 0 0 0
spi1 0 0 0 0 0 0
pll1_sysclk1 2 2 0 0 0 0
mjcp 0 0 0 0 0 0
arm 1 1 0 0 0 0
and the dump with current master:
root at dm355-evm:/sys/kernel/debug# cat davinci_clocks
ref_clk users= 7 24000000 Hz
pll1 users= 7 pll 432000000 Hz
pll1_sysclk1 users= 1 pll 216000000 Hz
arm_clk users= 1 psc 216000000 Hz
mjcp users= 0 psc 216000000 Hz
pll1_sysclk2 users= 3 pll 108000000 Hz
uart2 users= 1 psc 108000000 Hz
asp0 users= 0 psc 108000000 Hz
asp1 users= 0 psc 108000000 Hz
mmcsd0 users= 0 psc 108000000 Hz
mmcsd1 users= 0 psc 108000000 Hz
spi0 users= 0 psc 108000000 Hz
spi1 users= 0 psc 108000000 Hz
spi2 users= 0 psc 108000000 Hz
gpio users= 1 psc 108000000 Hz
aemif users= 1 psc 108000000 Hz
usb users= 0 psc 108000000 Hz
pll1_sysclk3 users= 0 pll 27000000 Hz
vpss_dac users= 0 psc 27000000 Hz
pll1_sysclk4 users= 0 pll 108000000 Hz
vpss_master users= 0 psc 108000000 Hz
vpss_slave users= 0 psc 108000000 Hz
pll1_aux_clk users= 3 pll 24000000 Hz
clkout1 users= 0 24000000 Hz
uart0 users= 1 psc 24000000 Hz
uart1 users= 1 psc 24000000 Hz
i2c users= 0 psc 24000000 Hz
pwm0 users= 0 psc 24000000 Hz
pwm1 users= 0 psc 24000000 Hz
pwm2 users= 0 psc 24000000 Hz
pwm3 users= 0 psc 24000000 Hz
timer0 users= 1 psc 24000000 Hz
timer1 users= 0 psc 24000000 Hz
timer2 users= 1 psc 24000000 Hz
timer3 users= 0 psc 24000000 Hz
rto users= 0 psc 24000000 Hz
pll1_sysclkbp users= 0 pll 8000000 Hz
clkout2 users= 0 8000000 Hz
pll2 users= 0 pll 342000000 Hz
pll2_sysclk1 users= 0 pll 342000000 Hz
pll2_sysclkbp users= 0 pll 3000000 Hz
clkout3 users= 0 3000000 Hz
I didn't have time today to analyze these myself. Hope it helps.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] ARM: dts: BCM5301X: Relicense Buffalo files to the GPL 2.0+ / MIT
From: Rafał Miłecki @ 2018-05-04 9:54 UTC (permalink / raw)
To: linux-arm-kernel
From: Rafa? Mi?ecki <rafal@milecki.pl>
This matches licensing used by other BCM5301X files and is preferred as:
1) GPL 2.0+ makes is clearly compatible with Linux kernel
2) MIT is also permissive but preferred over ISC
These files were created and ever touched by a group of four people
only: Felix, INAGAKI, Hauke and me.
Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
---
Felix, INAGAKI, Hauke: I need approve for this change from each of you.
If you are OK with it, can you reply with a line like:
Acked-by: <name> "<e-mail>"
please?
---
arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts | 3 +--
arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts | 13 +------------
arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts | 3 +--
3 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
index 8b64caabaad8..a587384f8e40 100644
--- a/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
+++ b/arch/arm/boot/dts/bcm4708-buffalo-wzr-1750dhp.dts
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for Buffalo WZR-1750DHP
*
* Copyright (C) 2014 Rafa? Mi?ecki <zajec5@gmail.com>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
index 87ea6ba664f5..8ea46eed26e2 100644
--- a/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
+++ b/arch/arm/boot/dts/bcm47081-buffalo-wzr-900dhp.dts
@@ -1,20 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for Buffalo WZR-900DHP
*
* Copyright (C) 2015 Rafa? Mi?ecki <zajec5@gmail.com>
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
- * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
- * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
- * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
- * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE
- * OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
- * PERFORMANCE OF THIS SOFTWARE.
*/
/dts-v1/;
diff --git a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
index 92058c73ee59..79a9633ec417 100644
--- a/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
+++ b/arch/arm/boot/dts/bcm4709-buffalo-wxr-1900dhp.dts
@@ -1,10 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Broadcom BCM470X / BCM5301X ARM platform code.
* DTS for Buffalo WXR-1900DHP
*
* Copyright (C) 2015 Felix Fietkau <nbd@openwrt.org>
- *
- * Licensed under the GNU/GPL. See COPYING for details.
*/
/dts-v1/;
--
2.13.6
^ permalink raw reply related
* [PATCH v2 2/2] ARM64: dts: meson-axg: enable AP6255 wifi module
From: Yixun Lan @ 2018-05-04 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504094533.15588-1-yixun.lan@amlogic.com>
The Meson-AXG S400 board is shipped with AP6255 wifi module,
which is actually using the brcmfmac 43455 driver.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 47 +++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 6b6581c513a8..b3e1bdca32bb 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -48,6 +48,20 @@
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_7 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ab 0 30518 0>; /* PWM_A at 32.768KHz */
+ };
};
ðmac {
@@ -81,6 +95,12 @@
pinctrl-names = "default";
};
+&pwm_ab {
+ status = "okay";
+ pinctrl-0 = <&pwm_a_x20_pins>;
+ pinctrl-names = "default";
+};
+
/* emmc storage */
&sd_emmc_c {
status = "okay";
@@ -100,3 +120,30 @@
vmmc-supply = <&vcc_3v3>;
vqmmc-supply = <&vddio_boot>;
};
+
+/* wifi module */
+&sd_emmc_b {
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pinctrl-0 = <&sdio_pins>;
+ pinctrl-1 = <&sdio_clk_gate_pins>;
+ pinctrl-names = "default", "clk-gate";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ non-removable;
+ disable-wp;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+
+ brcmf: wifi at 1 {
+ reg = <1>;
+ compatible = "brcm,bcm4329-fmac";
+ };
+};
--
2.17.0
^ permalink raw reply related
* [PATCH v2 1/2] ARM64: dts: meson-axg: drop sdio pwrseq property
From: Yixun Lan @ 2018-05-04 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504094533.15588-1-yixun.lan@amlogic.com>
This sdio-pwrseq property is not used untill wifi driver is merged,
also the gpio reset is GPIOX_7 which need to be fixed.
Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index f67d4e47e641..6b6581c513a8 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -48,11 +48,6 @@
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
};
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- };
};
ðmac {
--
2.17.0
^ permalink raw reply related
* [PATCH v2 0/2] ARM64: dts: meson-axg: enable wifi driver
From: Yixun Lan @ 2018-05-04 9:45 UTC (permalink / raw)
To: linux-arm-kernel
These patches try to enable the WIFI module AP6255 in Meson-AXG S400
baord. First patch revert an error which was introduced in early commit.
Hi Kevin
Please squash patch 1 into the commit[1] of your v4.18/dt64 branch,
which was the error introduced there.
Change since v1 at [2]:
- fix wrong reset gpio pin
[1] 7e1eee2ec496 'ARM64: dts: meson-axg: enable the eMMC controller'
[2] https://lkml.kernel.org/r/20180423145729.14368-1-yixun.lan at amlogic.com
Yixun Lan (2):
ARM64: dts: meson-axg: drop sdio pwrseq property
ARM64: dts: meson-axg: enable AP6255 wifi module
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 44 ++++++++++++++++++-
1 file changed, 43 insertions(+), 1 deletion(-)
--
2.17.0
^ permalink raw reply
* [PATCH v1] drm/kms/mode: added a new helper for calculating videomode from crtc's display mode
From: Jani Nikula @ 2018-05-04 9:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525419600-1774-1-git-send-email-satendra.t@samsung.com>
On Fri, 04 May 2018, Satendra Singh Thakur <satendra.t@samsung.com> wrote:
> Reviewed-by: Jani Nikula <jani.nikula@linux.intel.com>
No. I commented on the patch, but I never said Reviewed-by. Never assume
Reviewed-by based on random comments on patches.
BR,
Jani.
--
Jani Nikula, Intel Open Source Technology Center
^ permalink raw reply
* [PATCH v1] drm/kms/mode: added a new helper for calculating videomode from crtc's display mode
From: Liviu Dudau @ 2018-05-04 9:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525424523-3367-1-git-send-email-satendra.t@samsung.com>
On Fri, May 04, 2018 at 02:32:03PM +0530, Satendra Singh Thakur wrote:
> On Thu, May 03, 2018 at 11:36:39 +0100, Liviu Dudau wrote:
> > On Thu, May 03, 2018 at 11:28:37AM +0530, Satendra Singh Thakur wrote:
> > > 1.
> > > -Added a new helper drm_display_mode_crtc_to_videomode
> > > -This helper calculates mode parameters like
> > > horizontal front_porch, back_porch, sync length
> > > vertical front_porch, back_porch, sync length
> > > using crtc_* fields of struct drm_display_mode
> > > -It uses following fields of crtc mode
> > > horizontal sync start/end, active and total length
> > > vertical sync start/end, active and total length
> > > 2.
> > > -Most of the driver use user-supplied mode for calculating videomode
> > > -However, few drivers use HW (crtc) mode for calculating videomode
> > > -This helper will be useful for such drivers
> > > 3.
> > > -Currently following drivers will be using this new helper
> > > -arm hdlcd
> > > -atmel hlcdc
> > > -exynos 5433 decon
> > > -exynos7 decon
> > > -exynos fimd
> > > 4.
> > > -This patch removes related duplicate code from above mentioned drivers
> > >
> > > Signed-off-by: Satendra Singh Thakur <satendra.t@samsung.com>
> > > Cc: Madhur Verma <madhur.verma@samsung.com>
> > > Cc: Hemanshu Srivastava <hemanshu.s@samsung.com>
> > > ---
> > > drivers/gpu/drm/arm/hdlcd_crtc.c | 8 +-------
> > > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c | 7 +------
> > > drivers/gpu/drm/drm_modes.c | 20 ++++++++++++++++++++
> > > drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 22 ++++++++++------------
> > > drivers/gpu/drm/exynos/exynos7_drm_decon.c | 23 ++++++++++-------------
> > > drivers/gpu/drm/exynos/exynos_drm_fimd.c | 22 +++++++++-------------
> > > include/drm/drm_modes.h | 2 ++
> > > 7 files changed, 53 insertions(+), 51 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/arm/hdlcd_crtc.c b/drivers/gpu/drm/arm/hdlcd_crtc.c
> > > index cf5cbd6..d20e471 100644
> > > --- a/drivers/gpu/drm/arm/hdlcd_crtc.c
> > > +++ b/drivers/gpu/drm/arm/hdlcd_crtc.c
> > > @@ -130,13 +130,7 @@ static void hdlcd_crtc_mode_set_nofb(struct drm_crtc *crtc)
> > > struct videomode vm;
> > > unsigned int polarities, err;
> > >
> > > - vm.vfront_porch = m->crtc_vsync_start - m->crtc_vdisplay;
> > > - vm.vback_porch = m->crtc_vtotal - m->crtc_vsync_end;
> > > - vm.vsync_len = m->crtc_vsync_end - m->crtc_vsync_start;
> > > - vm.hfront_porch = m->crtc_hsync_start - m->crtc_hdisplay;
> > > - vm.hback_porch = m->crtc_htotal - m->crtc_hsync_end;
> > > - vm.hsync_len = m->crtc_hsync_end - m->crtc_hsync_start;
> > > -
> > > + drm_display_mode_crtc_to_videomode(m, &vm);
> > > polarities = HDLCD_POLARITY_DATAEN | HDLCD_POLARITY_DATA;
> > >
> > > if (m->flags & DRM_MODE_FLAG_PHSYNC)
> >
> > For the HDLCD part:
> >
> > Acked-by: Liviu Dudau <liviu.dudau@arm.com>
> >
> > If you're not sending the final version through drm-misc then let me
> > know and I can pick up the HDLCD part separately.
> >
> > Best regards,
> > Liviu
> >
> >
>
> Hi Mr Liviu,
> Thanks for accepting the patch.
> I don't know how to send patch through drm-misc.
> You may please go ahead and pick HDLCD part separately.
Lets wait for the maintainers of other drivers to give their ACKs and
then we'll sort out the submission. Usually it is just a matter of
asking for the patch to be pulled from the relevant people. For drm-misc
there are quite a few people and with enough patches accepted others can
join too. I'll just put here some names, in no particular order, that
you can ask for the patch to be pulled.
Gustavo Padovan <gustavo@padovan.org>
Daniel Stone <daniel@fooishbar.org>
Eric Anholt <eric@anholt.net>
Jani Nikula <jani.nikula@intel.com>
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Sean Paul <seanpaul@chromium.org>
Daniel Vetter <daniel.vetter@intel.com>
Best regards,
Liviu
>
> Thanks
> -Satendra
--
====================
| I would like to |
| fix the world, |
| but they're not |
| giving me the |
\ source code! /
---------------
?\_(?)_/?
^ permalink raw reply
* [GIT PULL] Ux500 DTS changes for v4.18
From: Linus Walleij @ 2018-05-04 9:33 UTC (permalink / raw)
To: linux-arm-kernel
Hi there ARM SoC folks,
here is two DTS update patches for Ux500 for v4.18.
We fix up the debounces and delete the unused U8540
and U9540 device trees.
Please pull it in!
Yours,
Linus Walleij
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-dts-arm-soc
for you to fetch changes up to f6601ae15fffbb3ade2cdbace9a2c9a25aba85ea:
ARM: ux500: Drop the U8540 device trees (2018-05-04 11:15:43 +0200)
----------------------------------------------------------------
This:
- Corrects the debounce interval on some nodes
- Drops the U8540/U9540 device trees
----------------------------------------------------------------
Geert Uytterhoeven (1):
ARM: dts: Ux500: Fix "debounce-interval" property misspelling
Linus Walleij (1):
ARM: ux500: Drop the U8540 device trees
arch/arm/boot/dts/Makefile | 4 +-
arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi | 196 -----------------------------
arch/arm/boot/dts/ste-ccu8540.dts | 94 --------------
arch/arm/boot/dts/ste-ccu9540.dts | 79 ------------
arch/arm/boot/dts/ste-snowball.dts | 10 +-
5 files changed, 6 insertions(+), 377 deletions(-)
delete mode 100644 arch/arm/boot/dts/ste-ccu8540-pinctrl.dtsi
delete mode 100644 arch/arm/boot/dts/ste-ccu8540.dts
delete mode 100644 arch/arm/boot/dts/ste-ccu9540.dts
^ permalink raw reply
* [GIT PULL] Ux500 updates for v4.18
From: Linus Walleij @ 2018-05-04 9:30 UTC (permalink / raw)
To: linux-arm-kernel
Hi there ARM SoC folks,
here are some Ux500 updates for v4.18. We drop
the experimental silicon in U8540 and U9540 and
tidy up Kconfig a bit.
Please pull it in!
Yours,
Linus Walleij
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-stericsson.git
tags/ux500-machine-arm-soc
for you to fetch changes up to 52b12be584ba554a40ad61d4d07bfbc100ffa1ac:
ARM: ux500: Cut down Kconfig options (2018-05-04 11:02:52 +0200)
----------------------------------------------------------------
These changes for ux500:
- Drops U8540 and U9540
- Cuts down the Kconfig options due to accumulated simplifications
----------------------------------------------------------------
Linus Walleij (2):
ARM: ux500: Drop U8540/9540 support
ARM: ux500: Cut down Kconfig options
arch/arm/mach-ux500/Kconfig | 53 ++++++++-------------------------------
arch/arm/mach-ux500/cpu-db8500.c | 16 ++----------
arch/arm/mach-ux500/db8500-regs.h | 4 ---
3 files changed, 13 insertions(+), 60 deletions(-)
^ permalink raw reply
* [PATCH 1/2] ARM: dts: imx6sx-sabreauto: drop 'regulators' container node
From: Shawn Guo @ 2018-05-04 9:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525426030-17221-1-git-send-email-shawnguo@kernel.org>
Hi Anson,
I will push these two patches to imx/dt branch soon. Please base your
imx6sx-sabreauto dts patches on them.
Shawn
On Fri, May 04, 2018 at 05:27:09PM +0800, Shawn Guo wrote:
> Let's drop the 'regulators' container node by giving VCC_SD3 an unique
> name and removing 'reg' property, so that the fixed regulator can be
> under root node directly.
>
> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
> ---
> arch/arm/boot/dts/imx6sx-sabreauto.dts | 25 +++++++++----------------
> 1 file changed, 9 insertions(+), 16 deletions(-)
>
> diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
> index 57d1ea0a3f8e..e5c1d6daa5e0 100644
> --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
> +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
> @@ -18,22 +18,15 @@
> reg = <0x80000000 0x80000000>;
> };
>
> - regulators {
> - compatible = "simple-bus";
> - #address-cells = <1>;
> - #size-cells = <0>;
> -
> - vcc_sd3: regulator at 0 {
> - compatible = "regulator-fixed";
> - reg = <0>;
> - pinctrl-names = "default";
> - pinctrl-0 = <&pinctrl_vcc_sd3>;
> - regulator-name = "VCC_SD3";
> - regulator-min-microvolt = <3000000>;
> - regulator-max-microvolt = <3000000>;
> - gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
> - enable-active-high;
> - };
> + vcc_sd3: regulator-vcc-sd3 {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_vcc_sd3>;
> + regulator-name = "VCC_SD3";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
> + enable-active-high;
> };
> };
>
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH 2/2] ARM: dts: imx6sx-sabreauto: drop board specific pinctrl container node
From: Shawn Guo @ 2018-05-04 9:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525426030-17221-1-git-send-email-shawnguo@kernel.org>
The board specific pinctrl function container node 'imx6x-sabreauto' is
not really necessary, since commit 5fcdf6a7ed95 ("pinctrl: imx: Allow
parsing DT without function nodes"). Let's drop it to save one level of
indentation.
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6sx-sabreauto.dts | 134 ++++++++++++++++-----------------
1 file changed, 66 insertions(+), 68 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index e5c1d6daa5e0..87ffe2c820f7 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -66,78 +66,76 @@
};
&iomuxc {
- imx6x-sabreauto {
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
- MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
- >;
- };
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ >;
+ };
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
- MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
- MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
- >;
- };
+ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+ MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
+ MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
+ >;
+ };
- pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
- fsl,pins = <
- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
- >;
- };
+ pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+ >;
+ };
- pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
- fsl,pins = <
- MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
- MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
- MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
- MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
- MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
- MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
- MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
- MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
- MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
- MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
- >;
- };
+ pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+ >;
+ };
- pinctrl_usdhc4: usdhc4grp {
- fsl,pins = <
- MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
- MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
- MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
- MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
- MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
- MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
- MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
- MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
- >;
- };
+ pinctrl_usdhc4: usdhc4grp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
+ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
+ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+ MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
+ MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
+ >;
+ };
- pinctrl_vcc_sd3: vccsd3grp {
- fsl,pins = <
- MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
- >;
- };
+ pinctrl_vcc_sd3: vccsd3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
+ >;
};
};
--
1.9.1
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: imx6sx-sabreauto: drop 'regulators' container node
From: Shawn Guo @ 2018-05-04 9:27 UTC (permalink / raw)
To: linux-arm-kernel
Let's drop the 'regulators' container node by giving VCC_SD3 an unique
name and removing 'reg' property, so that the fixed regulator can be
under root node directly.
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
arch/arm/boot/dts/imx6sx-sabreauto.dts | 25 +++++++++----------------
1 file changed, 9 insertions(+), 16 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 57d1ea0a3f8e..e5c1d6daa5e0 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -18,22 +18,15 @@
reg = <0x80000000 0x80000000>;
};
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- vcc_sd3: regulator at 0 {
- compatible = "regulator-fixed";
- reg = <0>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_vcc_sd3>;
- regulator-name = "VCC_SD3";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
+ vcc_sd3: regulator-vcc-sd3 {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_vcc_sd3>;
+ regulator-name = "VCC_SD3";
+ regulator-min-microvolt = <3000000>;
+ regulator-max-microvolt = <3000000>;
+ gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
};
};
--
1.9.1
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