* [PATCH] ARM: dts: imx: Switch to SPDX identifier
From: Fabio Estevam @ 2018-05-07 18:23 UTC (permalink / raw)
To: linux-arm-kernel
From: Fabio Estevam <fabio.estevam@nxp.com>
Adopt the SPDX license identifier headers to ease license compliance
management.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
---
arch/arm/boot/dts/imx1.dtsi | 13 +++---------
arch/arm/boot/dts/imx23.dtsi | 13 +++---------
arch/arm/boot/dts/imx25.dtsi | 13 +++---------
arch/arm/boot/dts/imx27.dtsi | 13 +++---------
arch/arm/boot/dts/imx28.dtsi | 13 +++---------
arch/arm/boot/dts/imx31.dtsi | 13 +++---------
arch/arm/boot/dts/imx35.dtsi | 14 +++++--------
arch/arm/boot/dts/imx51.dtsi | 15 ++++----------
arch/arm/boot/dts/imx6dl.dtsi | 12 +++--------
arch/arm/boot/dts/imx6q.dtsi | 12 +++--------
arch/arm/boot/dts/imx6qdl.dtsi | 15 ++++----------
arch/arm/boot/dts/imx6qp.dtsi | 44 +++-------------------------------------
arch/arm/boot/dts/imx6sl.dtsi | 11 +++-------
arch/arm/boot/dts/imx6sx.dtsi | 10 +++------
arch/arm/boot/dts/imx6ul.dtsi | 10 +++------
arch/arm/boot/dts/imx7d.dtsi | 46 ++++--------------------------------------
arch/arm/boot/dts/imx7s.dtsi | 46 ++++--------------------------------------
17 files changed, 57 insertions(+), 256 deletions(-)
diff --git a/arch/arm/boot/dts/imx1.dtsi b/arch/arm/boot/dts/imx1.dtsi
index 78cba94..3edc7b5 100644
--- a/arch/arm/boot/dts/imx1.dtsi
+++ b/arch/arm/boot/dts/imx1.dtsi
@@ -1,13 +1,6 @@
-/*
- * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
#include "imx1-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index cb0a3fe..71bfd2b 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -1,13 +1,6 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
#include "imx23-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx25.dtsi b/arch/arm/boot/dts/imx25.dtsi
index 67606dd..85c15ee 100644
--- a/arch/arm/boot/dts/imx25.dtsi
+++ b/arch/arm/boot/dts/imx25.dtsi
@@ -1,13 +1,6 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
#include <dt-bindings/gpio/gpio.h>
#include "imx25-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx27.dtsi b/arch/arm/boot/dts/imx27.dtsi
index 6c28b9c..08ea75ae 100644
--- a/arch/arm/boot/dts/imx27.dtsi
+++ b/arch/arm/boot/dts/imx27.dtsi
@@ -1,13 +1,6 @@
-/*
- * Copyright 2012 Sascha Hauer, Pengutronix
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+//Copyright 2012 Sascha Hauer, Pengutronix
#include "imx27-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 9ad8d35..5107fdc 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -1,13 +1,6 @@
-/*
- * Copyright 2012 Freescale Semiconductor, Inc.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Freescale Semiconductor, Inc.
#include <dt-bindings/gpio/gpio.h>
#include "imx28-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi
index ebc3f2d..4642c81 100644
--- a/arch/arm/boot/dts/imx31.dtsi
+++ b/arch/arm/boot/dts/imx31.dtsi
@@ -1,13 +1,6 @@
-/*
- * Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
/ {
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index bf343195..3236053 100644
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -1,12 +1,8 @@
-/*
- * Copyright 2012 Steffen Trumtrar, Pengutronix
- *
- * based on imx27.dtsi
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2012 Steffen Trumtrar, Pengutronix
+//
+// based on imx27.dtsi
#include "imx35-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index b5db83cd..fe01b89 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -1,14 +1,7 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2011 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
#include "imx51-pinfunc.h"
#include <dt-bindings/clock/imx5-clock.h>
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 558bce8..b384913 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -1,12 +1,6 @@
-
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6dl-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 48429e8..6f3a0e6 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -1,12 +1,6 @@
-
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6q-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 69648e2..866bfa0 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1,14 +1,7 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Copyright 2011 Freescale Semiconductor, Inc.
+// Copyright 2011 Linaro Ltd.
#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
diff --git a/arch/arm/boot/dts/imx6qp.dtsi b/arch/arm/boot/dts/imx6qp.dtsi
index 5f4fdce..5f51f8e 100644
--- a/arch/arm/boot/dts/imx6qp.dtsi
+++ b/arch/arm/boot/dts/imx6qp.dtsi
@@ -1,44 +1,6 @@
-/*
- * Copyright 2016 Freescale Semiconductor, Inc.
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2016 Freescale Semiconductor, Inc.
#include "imx6q.dtsi"
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 2002db2..559f9e0 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -1,11 +1,6 @@
-/*
- * Copyright 2013 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2013 Freescale Semiconductor, Inc.
#include <dt-bindings/interrupt-controller/irq.h>
#include "imx6sl-pinfunc.h"
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 7e463d2..d9c21b8 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -1,10 +1,6 @@
-/*
- * Copyright 2014 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2014 Freescale Semiconductor, Inc.
#include <dt-bindings/clock/imx6sx-clock.h>
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 2b854d1..62ac4a6 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -1,10 +1,6 @@
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
+// SPDX-License-Identifier: GPL-2.0
+//
+// Copyright 2015 Freescale Semiconductor, Inc.
#include <dt-bindings/clock/imx6ul-clock.h>
#include <dt-bindings/gpio/gpio.h>
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 200714e..4c9877e 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -1,45 +1,7 @@
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Freescale Semiconductor, Inc.
+// Copyright 2016 Toradex AG
#include "imx7s.dtsi"
#include <dt-bindings/reset/imx7-reset.h>
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index b416d2b..061e741 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -1,45 +1,7 @@
-/*
- * Copyright 2015 Freescale Semiconductor, Inc.
- * Copyright 2016 Toradex AG
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This file is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This file is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+//
+// Copyright 2015 Freescale Semiconductor, Inc.
+// Copyright 2016 Toradex AG
#include <dt-bindings/clock/imx7d-clock.h>
#include <dt-bindings/power/imx7-power.h>
--
2.7.4
^ permalink raw reply related
* [PATCH v2] ARM: dts: cygnus: fix irq type for arm global timer
From: Florian Fainelli @ 2018-05-07 18:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503153207.7668-1-peron.clem@gmail.com>
On Thu, 3 May 2018 17:32:07 +0200, Cl?ment P?ron <peron.clem@gmail.com> wrote:
> As per ARM documentation
> PPI(0) ID27 - global timer interrupt is rising-edge sensitive.
>
> set IRQ triggering type to IRQ_TYPE_EDGE_RISING for ARM Global timers.
>
> Fixes: c9ad7bc5fe3 ("ARM: dts: Enable Broadcom Cygnus SoC")
> Signed-off-by: Cl?ment P?ron <peron.clem@gmail.com>
> ---
Applied to devicetree/fixes, thanks!
--
Florian
^ permalink raw reply
* [PATCH] ARM: dts: BCM5301X: Relicense Buffalo files to the GPL 2.0+ / MIT
From: Florian Fainelli @ 2018-05-07 18:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180504095445.30918-1-zajec5@gmail.com>
On Fri, 4 May 2018 11:54:45 +0200, Rafa? Mi?ecki <zajec5@gmail.com> wrote:
> From: Rafa? Mi?ecki <rafal@milecki.pl>
>
> This matches licensing used by other BCM5301X files and is preferred as:
> 1) GPL 2.0+ makes is clearly compatible with Linux kernel
> 2) MIT is also permissive but preferred over ISC
>
> These files were created and ever touched by a group of four people
> only: Felix, INAGAKI, Hauke and me.
>
> Signed-off-by: Rafa? Mi?ecki <rafal@milecki.pl>
> ---
Applied to devicetree/next, thanks!
--
Florian
^ permalink raw reply
* [PATCH v3 11/14] media: platform: Add Sunxi-Cedrus VPU decoder driver
From: kbuild test robot @ 2018-05-07 18:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507124500.20434-12-paul.kocialkowski@bootlin.com>
Hi Paul,
I love your patch! Yet something to improve:
[auto build test ERROR on linuxtv-media/master]
[also build test ERROR on v4.17-rc4 next-20180507]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Paul-Kocialkowski/Sunxi-Cedrus-driver-for-the-Allwinner-Video-Engine-using-media-requests/20180508-004955
base: git://linuxtv.org/media_tree.git master
config: arm-allmodconfig (attached as .config)
compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm
All error/warnings (new ones prefixed by >>):
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus.c:205:3: error: 'const struct media_device_ops' has no member named 'req_validate'
.req_validate = vb2_request_validate,
^~~~~~~~~~~~
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus.c:205:18: error: 'vb2_request_validate' undeclared here (not in a function); did you mean 'vb2_queue_release'?
.req_validate = vb2_request_validate,
^~~~~~~~~~~~~~~~~~~~
vb2_queue_release
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus.c:206:3: error: 'const struct media_device_ops' has no member named 'req_queue'
.req_queue = vb2_m2m_request_queue,
^~~~~~~~~
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus.c:206:15: error: 'vb2_m2m_request_queue' undeclared here (not in a function); did you mean 'v4l2_m2m_buf_queue'?
.req_queue = vb2_m2m_request_queue,
^~~~~~~~~~~~~~~~~~~~~
v4l2_m2m_buf_queue
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus.c:206:15: warning: excess elements in struct initializer
drivers/media//platform/sunxi/cedrus/sunxi_cedrus.c:206:15: note: (near initialization for 'sunxi_cedrus_m2m_media_ops')
--
drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c: In function 'sunxi_cedrus_stop_streaming':
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c:437:3: error: implicit declaration of function 'v4l2_ctrl_request_complete'; did you mean 'v4l2_ctrl_replace'? [-Werror=implicit-function-declaration]
v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req,
^~~~~~~~~~~~~~~~~~~~~~~~~~
v4l2_ctrl_replace
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c:437:43: error: 'struct vb2_buffer' has no member named 'req_obj'
v4l2_ctrl_request_complete(vbuf->vb2_buf.req_obj.req,
^
drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c: In function 'sunxi_cedrus_buf_request_complete':
drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c:455:31: error: 'struct vb2_buffer' has no member named 'req_obj'
v4l2_ctrl_request_complete(vb->req_obj.req, &ctx->hdl);
^~
drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c: At top level:
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c:464:3: error: 'struct vb2_ops' has no member named 'buf_request_complete'
.buf_request_complete = sunxi_cedrus_buf_request_complete,
^~~~~~~~~~~~~~~~~~~~
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c:464:26: warning: excess elements in struct initializer
.buf_request_complete = sunxi_cedrus_buf_request_complete,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/media//platform/sunxi/cedrus/sunxi_cedrus_video.c:464:26: note: (near initialization for 'sunxi_cedrus_qops')
cc1: some warnings being treated as errors
--
drivers/media//platform/sunxi/cedrus/sunxi_cedrus_dec.c: In function 'sunxi_cedrus_device_run':
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus_dec.c:100:28: error: 'struct vb2_buffer' has no member named 'req_obj'
src_req = run.src->vb2_buf.req_obj.req;
^
drivers/media//platform/sunxi/cedrus/sunxi_cedrus_dec.c:101:28: error: 'struct vb2_buffer' has no member named 'req_obj'
dst_req = run.dst->vb2_buf.req_obj.req;
^
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus_dec.c:104:3: error: implicit declaration of function 'v4l2_ctrl_request_setup'; did you mean 'v4l2_ctrl_handler_setup'? [-Werror=implicit-function-declaration]
v4l2_ctrl_request_setup(src_req, &ctx->hdl);
^~~~~~~~~~~~~~~~~~~~~~~
v4l2_ctrl_handler_setup
>> drivers/media//platform/sunxi/cedrus/sunxi_cedrus_dec.c:138:3: error: implicit declaration of function 'v4l2_ctrl_request_complete'; did you mean 'v4l2_ctrl_replace'? [-Werror=implicit-function-declaration]
v4l2_ctrl_request_complete(src_req, &ctx->hdl);
^~~~~~~~~~~~~~~~~~~~~~~~~~
v4l2_ctrl_replace
cc1: some warnings being treated as errors
vim +205 drivers/media//platform/sunxi/cedrus/sunxi_cedrus.c
203
204 static const struct media_device_ops sunxi_cedrus_m2m_media_ops = {
> 205 .req_validate = vb2_request_validate,
> 206 .req_queue = vb2_m2m_request_queue,
207 };
208
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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^ permalink raw reply
* [PATCH v2 17/27] coresight: etr: Add support for save restore buffers
From: Mathieu Poirier @ 2018-05-07 17:48 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525165857-11096-18-git-send-email-suzuki.poulose@arm.com>
On Tue, May 01, 2018 at 10:10:47AM +0100, Suzuki K Poulose wrote:
> Add support for creating buffers which can be used in save-restore
> mode (e.g, for use by perf). If the TMC-ETR supports save-restore
> feature, we could support the mode in all buffer backends. However,
> if it doesn't, we should fall back to using in built SG mechanism,
> where we can rotate the SG table by making some adjustments in the
> page table.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 142 +++++++++++++++++++++++-
> drivers/hwtracing/coresight/coresight-tmc.h | 16 +++
> 2 files changed, 153 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index fde3fa6..25e7feb 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -604,7 +604,7 @@ tmc_etr_sg_table_index_to_daddr(struct tmc_sg_table *sg_table, u32 index)
> * which starts @base_offset.
> * 2) Mark the page at the base_offset + size as LAST.
> */
> -static int __maybe_unused
> +static int
> tmc_etr_sg_table_rotate(struct etr_sg_table *etr_table,
> unsigned long base_offset, unsigned long size)
> {
> @@ -736,6 +736,9 @@ static int tmc_etr_alloc_flat_buf(struct tmc_drvdata *drvdata,
> flat_buf->size = etr_buf->size;
> flat_buf->dev = drvdata->dev;
> etr_buf->hwaddr = flat_buf->daddr;
> + etr_buf->rrp = flat_buf->daddr;
> + etr_buf->rwp = flat_buf->daddr;
> + etr_buf->status = 0;
> etr_buf->mode = ETR_MODE_FLAT;
> etr_buf->private = flat_buf;
> return 0;
> @@ -777,11 +780,36 @@ static ssize_t tmc_etr_get_data_flat_buf(struct etr_buf *etr_buf,
> return len;
> }
>
> +/*
> + * tmc_etr_restore_flat_buf: Restore the flat buffer pointers.
> + * This is only possible with in-built ETR capability to save-restore
> + * the pointers. The DBA will still point to the original start of the
> + * buffer.
> + */
> +static int tmc_etr_restore_flat_buf(struct etr_buf *etr_buf,
> + unsigned long r_offset,
> + unsigned long w_offset,
> + unsigned long size,
> + u32 status,
> + bool has_save_restore)
> +{
> + struct etr_flat_buf *flat_buf = etr_buf->private;
> +
> + if (!has_save_restore || !flat_buf || size > flat_buf->size)
> + return -EINVAL;
> + etr_buf->rrp = flat_buf->daddr + (r_offset % flat_buf->size);
> + etr_buf->rwp = flat_buf->daddr + (w_offset % flat_buf->size);
> + etr_buf->size = size;
> + etr_buf->status = status;
> + return 0;
> +}
> +
> static const struct etr_buf_operations etr_flat_buf_ops = {
> .alloc = tmc_etr_alloc_flat_buf,
> .free = tmc_etr_free_flat_buf,
> .sync = tmc_etr_sync_flat_buf,
> .get_data = tmc_etr_get_data_flat_buf,
> + .restore = tmc_etr_restore_flat_buf,
> };
>
> /*
> @@ -799,6 +827,7 @@ static int tmc_etr_alloc_sg_buf(struct tmc_drvdata *drvdata,
> if (IS_ERR(etr_table))
> return -ENOMEM;
> etr_buf->hwaddr = etr_table->hwaddr;
> + etr_buf->status = 0;
> etr_buf->mode = ETR_MODE_ETR_SG;
> etr_buf->private = etr_table;
> return 0;
> @@ -825,9 +854,11 @@ static ssize_t tmc_etr_get_data_sg_buf(struct etr_buf *etr_buf, u64 offset,
> static void tmc_etr_sync_sg_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
> {
> long r_offset, w_offset;
> + unsigned long buf_size;
> struct etr_sg_table *etr_table = etr_buf->private;
> struct tmc_sg_table *table = etr_table->sg_table;
>
> + buf_size = tmc_sg_table_buf_size(table);
> /* Convert hw address to offset in the buffer */
> r_offset = tmc_sg_get_data_page_offset(table, rrp);
> if (r_offset < 0) {
> @@ -849,16 +880,62 @@ static void tmc_etr_sync_sg_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
> if (etr_buf->full)
> etr_buf->len = etr_buf->size;
> else
> - etr_buf->len = ((w_offset < r_offset) ? etr_buf->size : 0) +
> + etr_buf->len = ((w_offset < r_offset) ? buf_size : 0) +
> w_offset - r_offset;
> tmc_sg_table_sync_data_range(table, r_offset, etr_buf->len);
> }
>
> +static int tmc_etr_restore_sg_buf(struct etr_buf *etr_buf,
> + unsigned long r_offset,
> + unsigned long w_offset,
> + unsigned long size,
> + u32 __always_unused status,
> + bool has_save_restore)
> +{
> + int rc;
> + struct etr_sg_table *etr_table = etr_buf->private;
> + struct device *dev = etr_table->sg_table->dev;
> +
> + /*
> + * It is highly unlikely that we have an ETR with in-built SG and
> + * Save-Restore capability and we are not sure if the PTRs will
> + * be updated.
> + */
> + if (has_save_restore) {
> + dev_warn_once(dev,
> + "Unexpected feature combination of SG and save-restore\n");
> + return -EINVAL;
> + }
> +
> + /*
> + * Since we cannot program RRP/RWP different from DBAL, the offsets
> + * should match.
> + */
> + if (r_offset != w_offset) {
> + dev_dbg(dev, "Mismatched RRP/RWP offsets\n");
> + return -EINVAL;
> + }
> +
> + /* Make sure the size is aligned */
> + size &= ~(ETR_SG_PAGE_SIZE - 1);
> +
> + rc = tmc_etr_sg_table_rotate(etr_table, w_offset, size);
> + if (!rc) {
> + etr_buf->hwaddr = etr_table->hwaddr;
> + etr_buf->rrp = etr_table->hwaddr;
> + etr_buf->rwp = etr_table->hwaddr;
> + etr_buf->size = size;
> + }
> +
> + return rc;
> +}
> +
> static const struct etr_buf_operations etr_sg_buf_ops = {
> .alloc = tmc_etr_alloc_sg_buf,
> .free = tmc_etr_free_sg_buf,
> .sync = tmc_etr_sync_sg_buf,
> .get_data = tmc_etr_get_data_sg_buf,
> + .restore = tmc_etr_restore_sg_buf,
> };
>
> static const struct etr_buf_operations *etr_buf_ops[] = {
> @@ -899,10 +976,42 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata,
> {
> int rc = -ENOMEM;
> bool has_etr_sg, has_iommu;
> + bool has_flat, has_save_restore;
> struct etr_buf *etr_buf;
>
> has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG);
> has_iommu = iommu_get_domain_for_dev(drvdata->dev);
> + has_save_restore = tmc_etr_has_cap(drvdata, TMC_ETR_SAVE_RESTORE);
> +
> + /*
> + * We can normally use flat DMA buffer provided that the buffer
> + * is not used in save restore fashion without hardware support.
> + */
> + has_flat = !(flags & ETR_BUF_F_RESTORE_PTRS) || has_save_restore;
> +
> + /*
> + * To support save-restore on a given ETR we have the following
> + * conditions:
> + * 1) If the buffer requires save-restore of a pointers as well
> + * as the Status bit, we require ETR support for it and we coul
/coul/could
> + * support all the backends.
> + * 2) If the buffer requires only save-restore of pointers, then
> + * we could exploit a circular ETR SG list. None of the other
> + * backends can support it without the ETR feature.
> + *
> + * If the buffer will be used in a save-restore mode without
> + * the ETR support for SAVE_RESTORE, we can only support TMC
> + * ETR in-built SG tables which can be rotated to make it work.
> + */
> + if ((flags & ETR_BUF_F_RESTORE_STATUS) && !has_save_restore)
> + return ERR_PTR(-EINVAL);
> +
> + if (!has_flat && !has_etr_sg) {
> + dev_dbg(drvdata->dev,
> + "No available backends for ETR buffer with flags %x\n",
> + flags);
> + return ERR_PTR(-EINVAL);
> + }
>
> etr_buf = kzalloc(sizeof(*etr_buf), GFP_KERNEL);
> if (!etr_buf)
> @@ -922,7 +1031,7 @@ static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata,
> * Fallback to available mechanisms.
> *
> */
> - if (!pages &&
> + if (!pages && has_flat &&
> (!has_etr_sg || has_iommu || size < SZ_1M))
> rc = tmc_etr_mode_alloc_buf(ETR_MODE_FLAT, drvdata,
> etr_buf, node, pages);
> @@ -999,6 +1108,29 @@ static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
> tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
> }
>
> +static int __maybe_unused
> +tmc_restore_etr_buf(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,
> + unsigned long r_offset, unsigned long w_offset,
> + unsigned long size, u32 status)
> +{
> + bool has_save_restore = tmc_etr_has_cap(drvdata, TMC_ETR_SAVE_RESTORE);
> +
> + if (WARN_ON_ONCE(!has_save_restore && etr_buf->mode != ETR_MODE_ETR_SG))
> + return -EINVAL;
> + /*
> + * If we use a circular SG list without ETR support, we can't
> + * support restoring "Full" bit.
> + */
> + if (WARN_ON_ONCE(!has_save_restore && status))
> + return -EINVAL;
> + if (status & ~TMC_STS_FULL)
> + return -EINVAL;
> + if (etr_buf->ops->restore)
> + return etr_buf->ops->restore(etr_buf, r_offset, w_offset, size,
> + status, has_save_restore);
> + return -EINVAL;
> +}
> +
> static inline void tmc_etr_enable_catu(struct tmc_drvdata *drvdata)
> {
> struct coresight_device *catu = tmc_etr_get_catu_device(drvdata);
> @@ -1058,8 +1190,8 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> * STS to "not full").
> */
> if (tmc_etr_has_cap(drvdata, TMC_ETR_SAVE_RESTORE)) {
> - tmc_write_rrp(drvdata, etr_buf->hwaddr);
> - tmc_write_rwp(drvdata, etr_buf->hwaddr);
> + tmc_write_rrp(drvdata, etr_buf->rrp);
> + tmc_write_rwp(drvdata, etr_buf->rwp);
> sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL;
> writel_relaxed(sts, drvdata->base + TMC_STS);
> }
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 6f7bec7..1bdfb38 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -141,12 +141,22 @@ enum etr_mode {
> ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
> };
>
> +/* ETR buffer should support save-restore */
> +#define ETR_BUF_F_RESTORE_PTRS 0x1
> +#define ETR_BUF_F_RESTORE_STATUS 0x2
> +
> +#define ETR_BUF_F_RESTORE_MINIMAL ETR_BUF_F_RESTORE_PTRS
> +#define ETR_BUF_F_RESTORE_FULL (ETR_BUF_F_RESTORE_PTRS |\
> + ETR_BUF_F_RESTORE_STATUS)
> struct etr_buf_operations;
>
> /**
> * struct etr_buf - Details of the buffer used by ETR
> * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.
> * @full : Trace data overflow
> + * @status : Value for STATUS if the ETR supports save-restore.
> + * @rrp : Value for RRP{LO:HI} if the ETR supports save-restore
> + * @rwp : Value for RWP{LO:HI} if the ETR supports save-restore
> * @size : Size of the buffer.
> * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI}
> * @offset : Offset of the trace data in the buffer for consumption.
> @@ -157,6 +167,9 @@ struct etr_buf_operations;
> struct etr_buf {
> enum etr_mode mode;
> bool full;
> + u32 status;
> + dma_addr_t rrp;
> + dma_addr_t rwp;
> ssize_t size;
> dma_addr_t hwaddr;
> unsigned long offset;
> @@ -207,6 +220,9 @@ struct etr_buf_operations {
> int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,
> int node, void **pages);
> void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp);
> + int (*restore)(struct etr_buf *etr_buf, unsigned long r_offset,
> + unsigned long w_offset, unsigned long size,
> + u32 status, bool has_save_restore);
> ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len,
> char **bufpp);
> void (*free)(struct etr_buf *etr_buf);
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v2 3/3] ARM: dts: stm32: Add ADC support to stm32mp157c
From: Jonathan Cameron @ 2018-05-07 17:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525247091-18143-4-git-send-email-fabrice.gasnier@st.com>
On Wed, 2 May 2018 09:44:51 +0200
Fabrice Gasnier <fabrice.gasnier@st.com> wrote:
> stm32mp157c has an ADC block with two physical ADCs.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
The driver support is now queued up in the IIO tree and should
be in Linux next later this week.
Thanks,
Jonathan
> ---
> arch/arm/boot/dts/stm32mp157c.dtsi | 32 ++++++++++++++++++++++++++++++++
> 1 file changed, 32 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
> index bc3eddc..7758a90 100644
> --- a/arch/arm/boot/dts/stm32mp157c.dtsi
> +++ b/arch/arm/boot/dts/stm32mp157c.dtsi
> @@ -160,6 +160,38 @@
> status = "disabled";
> };
>
> + adc: adc at 48003000 {
> + compatible = "st,stm32mp1-adc-core";
> + reg = <0x48003000 0x400>;
> + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&rcc ADC12>, <&rcc ADC12_K>;
> + clock-names = "bus", "adc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + adc1: adc at 0 {
> + compatible = "st,stm32mp1-adc";
> + #io-channel-cells = <1>;
> + reg = <0x0>;
> + interrupt-parent = <&adc>;
> + interrupts = <0>;
> + status = "disabled";
> + };
> +
> + adc2: adc at 100 {
> + compatible = "st,stm32mp1-adc";
> + #io-channel-cells = <1>;
> + reg = <0x100>;
> + interrupt-parent = <&adc>;
> + interrupts = <1>;
> + status = "disabled";
> + };
> + };
> +
> rcc: rcc at 50000000 {
> compatible = "st,stm32mp1-rcc", "syscon";
> reg = <0x50000000 0x1000>;
^ permalink raw reply
* [PATCH v2 2/3] iio: adc: stm32-adc: add support for STM32MP1
From: Jonathan Cameron @ 2018-05-07 17:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525247091-18143-3-git-send-email-fabrice.gasnier@st.com>
On Wed, 2 May 2018 09:44:50 +0200
Fabrice Gasnier <fabrice.gasnier@st.com> wrote:
> Add support for STM32MP1 ADC. It's quite similar to STM32H7 ADC.
> Introduce new compatible to handle variants of this hardware such as
> vregready flag, trigger list, interrupts, clock rate.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Applied to the togreg branch of iio.git and pushed out as testing for the
autobuilders to play with it.
Thanks,
Jonathan
> ---
> drivers/iio/adc/stm32-adc-core.c | 66 +++++++++++++++++++++++++++++-----------
> drivers/iio/adc/stm32-adc.c | 47 +++++++++++++++++++++++++---
> 2 files changed, 91 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/iio/adc/stm32-adc-core.c b/drivers/iio/adc/stm32-adc-core.c
> index 40be7d9..ca432e7 100644
> --- a/drivers/iio/adc/stm32-adc-core.c
> +++ b/drivers/iio/adc/stm32-adc-core.c
> @@ -34,9 +34,6 @@
> #define STM32F4_ADC_ADCPRE_SHIFT 16
> #define STM32F4_ADC_ADCPRE_MASK GENMASK(17, 16)
>
> -/* STM32 F4 maximum analog clock rate (from datasheet) */
> -#define STM32F4_ADC_MAX_CLK_RATE 36000000
> -
> /* STM32H7 - common registers for all ADC instances */
> #define STM32H7_ADC_CSR (STM32_ADCX_COMN_OFFSET + 0x00)
> #define STM32H7_ADC_CCR (STM32_ADCX_COMN_OFFSET + 0x08)
> @@ -51,9 +48,6 @@
> #define STM32H7_CKMODE_SHIFT 16
> #define STM32H7_CKMODE_MASK GENMASK(17, 16)
>
> -/* STM32 H7 maximum analog clock rate (from datasheet) */
> -#define STM32H7_ADC_MAX_CLK_RATE 36000000
> -
> /**
> * stm32_adc_common_regs - stm32 common registers, compatible dependent data
> * @csr: common status register offset
> @@ -74,15 +68,17 @@ struct stm32_adc_common_regs {
> * stm32_adc_priv_cfg - stm32 core compatible configuration data
> * @regs: common registers for all instances
> * @clk_sel: clock selection routine
> + * @max_clk_rate_hz: maximum analog clock rate (Hz, from datasheet)
> */
> struct stm32_adc_priv_cfg {
> const struct stm32_adc_common_regs *regs;
> int (*clk_sel)(struct platform_device *, struct stm32_adc_priv *);
> + u32 max_clk_rate_hz;
> };
>
> /**
> * struct stm32_adc_priv - stm32 ADC core private data
> - * @irq: irq for ADC block
> + * @irq: irq(s) for ADC block
> * @domain: irq domain reference
> * @aclk: clock reference for the analog circuitry
> * @bclk: bus clock common for all ADCs, depends on part used
> @@ -91,7 +87,7 @@ struct stm32_adc_priv_cfg {
> * @common: common data for all ADC instances
> */
> struct stm32_adc_priv {
> - int irq;
> + int irq[STM32_ADC_MAX_ADCS];
> struct irq_domain *domain;
> struct clk *aclk;
> struct clk *bclk;
> @@ -133,7 +129,7 @@ static int stm32f4_adc_clk_sel(struct platform_device *pdev,
> }
>
> for (i = 0; i < ARRAY_SIZE(stm32f4_pclk_div); i++) {
> - if ((rate / stm32f4_pclk_div[i]) <= STM32F4_ADC_MAX_CLK_RATE)
> + if ((rate / stm32f4_pclk_div[i]) <= priv->cfg->max_clk_rate_hz)
> break;
> }
> if (i >= ARRAY_SIZE(stm32f4_pclk_div)) {
> @@ -222,7 +218,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
> if (ckmode)
> continue;
>
> - if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
> + if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> goto out;
> }
> }
> @@ -242,7 +238,7 @@ static int stm32h7_adc_clk_sel(struct platform_device *pdev,
> if (!ckmode)
> continue;
>
> - if ((rate / div) <= STM32H7_ADC_MAX_CLK_RATE)
> + if ((rate / div) <= priv->cfg->max_clk_rate_hz)
> goto out;
> }
>
> @@ -328,11 +324,24 @@ static int stm32_adc_irq_probe(struct platform_device *pdev,
> struct stm32_adc_priv *priv)
> {
> struct device_node *np = pdev->dev.of_node;
> + unsigned int i;
> +
> + for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
> + priv->irq[i] = platform_get_irq(pdev, i);
> + if (priv->irq[i] < 0) {
> + /*
> + * At least one interrupt must be provided, make others
> + * optional:
> + * - stm32f4/h7 shares a common interrupt.
> + * - stm32mp1, has one line per ADC (either for ADC1,
> + * ADC2 or both).
> + */
> + if (i && priv->irq[i] == -ENXIO)
> + continue;
> + dev_err(&pdev->dev, "failed to get irq\n");
>
> - priv->irq = platform_get_irq(pdev, 0);
> - if (priv->irq < 0) {
> - dev_err(&pdev->dev, "failed to get irq\n");
> - return priv->irq;
> + return priv->irq[i];
> + }
> }
>
> priv->domain = irq_domain_add_simple(np, STM32_ADC_MAX_ADCS, 0,
> @@ -343,8 +352,12 @@ static int stm32_adc_irq_probe(struct platform_device *pdev,
> return -ENOMEM;
> }
>
> - irq_set_chained_handler(priv->irq, stm32_adc_irq_handler);
> - irq_set_handler_data(priv->irq, priv);
> + for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
> + if (priv->irq[i] < 0)
> + continue;
> + irq_set_chained_handler(priv->irq[i], stm32_adc_irq_handler);
> + irq_set_handler_data(priv->irq[i], priv);
> + }
>
> return 0;
> }
> @@ -353,11 +366,17 @@ static void stm32_adc_irq_remove(struct platform_device *pdev,
> struct stm32_adc_priv *priv)
> {
> int hwirq;
> + unsigned int i;
>
> for (hwirq = 0; hwirq < STM32_ADC_MAX_ADCS; hwirq++)
> irq_dispose_mapping(irq_find_mapping(priv->domain, hwirq));
> irq_domain_remove(priv->domain);
> - irq_set_chained_handler(priv->irq, NULL);
> +
> + for (i = 0; i < STM32_ADC_MAX_ADCS; i++) {
> + if (priv->irq[i] < 0)
> + continue;
> + irq_set_chained_handler(priv->irq[i], NULL);
> + }
> }
>
> static int stm32_adc_probe(struct platform_device *pdev)
> @@ -497,11 +516,19 @@ static int stm32_adc_remove(struct platform_device *pdev)
> static const struct stm32_adc_priv_cfg stm32f4_adc_priv_cfg = {
> .regs = &stm32f4_adc_common_regs,
> .clk_sel = stm32f4_adc_clk_sel,
> + .max_clk_rate_hz = 36000000,
> };
>
> static const struct stm32_adc_priv_cfg stm32h7_adc_priv_cfg = {
> .regs = &stm32h7_adc_common_regs,
> .clk_sel = stm32h7_adc_clk_sel,
> + .max_clk_rate_hz = 36000000,
> +};
> +
> +static const struct stm32_adc_priv_cfg stm32mp1_adc_priv_cfg = {
> + .regs = &stm32h7_adc_common_regs,
> + .clk_sel = stm32h7_adc_clk_sel,
> + .max_clk_rate_hz = 40000000,
> };
>
> static const struct of_device_id stm32_adc_of_match[] = {
> @@ -512,6 +539,9 @@ static int stm32_adc_remove(struct platform_device *pdev)
> .compatible = "st,stm32h7-adc-core",
> .data = (void *)&stm32h7_adc_priv_cfg
> }, {
> + .compatible = "st,stm32mp1-adc-core",
> + .data = (void *)&stm32mp1_adc_priv_cfg
> + }, {
> },
> };
> MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
> diff --git a/drivers/iio/adc/stm32-adc.c b/drivers/iio/adc/stm32-adc.c
> index 9a2583ca..3784118 100644
> --- a/drivers/iio/adc/stm32-adc.c
> +++ b/drivers/iio/adc/stm32-adc.c
> @@ -84,6 +84,7 @@
> #define STM32H7_ADC_CALFACT2 0xC8
>
> /* STM32H7_ADC_ISR - bit fields */
> +#define STM32MP1_VREGREADY BIT(12)
> #define STM32H7_EOC BIT(2)
> #define STM32H7_ADRDY BIT(0)
>
> @@ -249,6 +250,7 @@ struct stm32_adc_regspec {
> * @adc_info: per instance input channels definitions
> * @trigs: external trigger sources
> * @clk_required: clock is required
> + * @has_vregready: vregready status flag presence
> * @selfcalib: optional routine for self-calibration
> * @prepare: optional prepare routine (power-up, enable)
> * @start_conv: routine to start conversions
> @@ -261,6 +263,7 @@ struct stm32_adc_cfg {
> const struct stm32_adc_info *adc_info;
> struct stm32_adc_trig_info *trigs;
> bool clk_required;
> + bool has_vregready;
> int (*selfcalib)(struct stm32_adc *);
> int (*prepare)(struct stm32_adc *);
> void (*start_conv)(struct stm32_adc *, bool dma);
> @@ -695,8 +698,12 @@ static void stm32h7_adc_stop_conv(struct stm32_adc *adc)
> stm32_adc_clr_bits(adc, STM32H7_ADC_CFGR, STM32H7_DMNGT_MASK);
> }
>
> -static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
> +static int stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
> {
> + struct iio_dev *indio_dev = iio_priv_to_dev(adc);
> + int ret;
> + u32 val;
> +
> /* Exit deep power down, then enable ADC voltage regulator */
> stm32_adc_clr_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
> stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_ADVREGEN);
> @@ -705,7 +712,20 @@ static void stm32h7_adc_exit_pwr_down(struct stm32_adc *adc)
> stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_BOOST);
>
> /* Wait for startup time */
> - usleep_range(10, 20);
> + if (!adc->cfg->has_vregready) {
> + usleep_range(10, 20);
> + return 0;
> + }
> +
> + ret = stm32_adc_readl_poll_timeout(STM32H7_ADC_ISR, val,
> + val & STM32MP1_VREGREADY, 100,
> + STM32_ADC_TIMEOUT_US);
> + if (ret) {
> + stm32_adc_set_bits(adc, STM32H7_ADC_CR, STM32H7_DEEPPWD);
> + dev_err(&indio_dev->dev, "Failed to exit power down\n");
> + }
> +
> + return ret;
> }
>
> static void stm32h7_adc_enter_pwr_down(struct stm32_adc *adc)
> @@ -888,7 +908,9 @@ static int stm32h7_adc_selfcalib(struct stm32_adc *adc)
> int ret;
> u32 val;
>
> - stm32h7_adc_exit_pwr_down(adc);
> + ret = stm32h7_adc_exit_pwr_down(adc);
> + if (ret)
> + return ret;
>
> /*
> * Select calibration mode:
> @@ -952,7 +974,10 @@ static int stm32h7_adc_prepare(struct stm32_adc *adc)
> {
> int ret;
>
> - stm32h7_adc_exit_pwr_down(adc);
> + ret = stm32h7_adc_exit_pwr_down(adc);
> + if (ret)
> + return ret;
> +
> stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel);
>
> ret = stm32h7_adc_enable(adc);
> @@ -1944,9 +1969,23 @@ static int stm32_adc_remove(struct platform_device *pdev)
> .smp_cycles = stm32h7_adc_smp_cycles,
> };
>
> +static const struct stm32_adc_cfg stm32mp1_adc_cfg = {
> + .regs = &stm32h7_adc_regspec,
> + .adc_info = &stm32h7_adc_info,
> + .trigs = stm32h7_adc_trigs,
> + .has_vregready = true,
> + .selfcalib = stm32h7_adc_selfcalib,
> + .start_conv = stm32h7_adc_start_conv,
> + .stop_conv = stm32h7_adc_stop_conv,
> + .prepare = stm32h7_adc_prepare,
> + .unprepare = stm32h7_adc_unprepare,
> + .smp_cycles = stm32h7_adc_smp_cycles,
> +};
> +
> static const struct of_device_id stm32_adc_of_match[] = {
> { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
> { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
> + { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
> {},
> };
> MODULE_DEVICE_TABLE(of, stm32_adc_of_match);
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: iio: stm32-adc: add support for STM32MP1
From: Jonathan Cameron @ 2018-05-07 17:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507162830.GA11497@rob-hp-laptop>
On Mon, 7 May 2018 11:28:31 -0500
Rob Herring <robh@kernel.org> wrote:
> On Wed, May 02, 2018 at 09:44:49AM +0200, Fabrice Gasnier wrote:
> > Document support for STM32MP1 ADC. It's quite similar to STM32H7 ADC.
> > Introduce "st,stm32mp1-adc" compatible to handle variants of this
> > hardware such as vregready flag, interrupts, clock rate.
> >
> > Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> > ---
> > Changes in v2:
> > - Update dt-bindings following Rob's remark: STM32MP1 ADC has two
> > interrupt lines
> > ---
> > Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
Thanks. Applied to the togreg branch of iio.git and pushed out as
testing for the autobuilders to play with it.
Jonathan
^ permalink raw reply
* [PATCH v2 16/27] coresight: tmc-etr: Add transparent buffer management
From: Mathieu Poirier @ 2018-05-07 17:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525165857-11096-17-git-send-email-suzuki.poulose@arm.com>
On Tue, May 01, 2018 at 10:10:46AM +0100, Suzuki K Poulose wrote:
> At the moment we always use contiguous memory for TMC ETR tracing
> when used from sysfs. The size of the buffer is fixed at boot time
> and can only be changed by modifiying the DT. With the introduction
> of SG support we could support really large buffers in that mode.
> This patch abstracts the buffer used for ETR to switch between a
> contiguous buffer or a SG table depending on the availability of
> the memory.
>
> This also enables the sysfs mode to use the ETR in SG mode depending
> on configured the trace buffer size. Also, since ETR will use the
> new infrastructure to manage the buffer, we can get rid of some
> of the members in the tmc_drvdata and clean up the fields a bit.
>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 451 +++++++++++++++++++-----
> drivers/hwtracing/coresight/coresight-tmc.h | 57 ++-
> 2 files changed, 418 insertions(+), 90 deletions(-)
Good work on cleanly dealing with the different modes of operation from sysFS.
It is that kind of kitchen work I was too lazy to do when first worked on this
driver.
One a side note this patch doesn't apply on my CS next branch due to some
refactoring in tmc_enable_etr_sink_sysfs(). No need to worry about it for this
iteration though.
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index d18043d..fde3fa6 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -23,6 +23,13 @@
> #include "coresight-priv.h"
> #include "coresight-tmc.h"
>
> +struct etr_flat_buf {
> + struct device *dev;
> + dma_addr_t daddr;
> + void *vaddr;
> + size_t size;
> +};
> +
> /*
> * The TMC ETR SG has a page size of 4K. The SG table contains pointers
> * to 4KB buffers. However, the OS may use a PAGE_SIZE different from
> @@ -666,7 +673,7 @@ tmc_etr_sg_table_rotate(struct etr_sg_table *etr_table,
> * @size - Total size of the data buffer
> * @pages - Optional list of page virtual address
> */
> -static struct etr_sg_table __maybe_unused *
> +static struct etr_sg_table *
> tmc_init_etr_sg_table(struct device *dev, int node,
> unsigned long size, void **pages)
> {
> @@ -702,6 +709,296 @@ tmc_init_etr_sg_table(struct device *dev, int node,
> return etr_table;
> }
>
> +/*
> + * tmc_etr_alloc_flat_buf: Allocate a contiguous DMA buffer.
> + */
> +static int tmc_etr_alloc_flat_buf(struct tmc_drvdata *drvdata,
> + struct etr_buf *etr_buf, int node,
> + void **pages)
> +{
> + struct etr_flat_buf *flat_buf;
> +
> + /* We cannot reuse existing pages for flat buf */
> + if (pages)
> + return -EINVAL;
> +
> + flat_buf = kzalloc(sizeof(*flat_buf), GFP_KERNEL);
> + if (!flat_buf)
> + return -ENOMEM;
> +
> + flat_buf->vaddr = dma_alloc_coherent(drvdata->dev, etr_buf->size,
> + &flat_buf->daddr, GFP_KERNEL);
> + if (!flat_buf->vaddr) {
> + kfree(flat_buf);
> + return -ENOMEM;
> + }
> +
> + flat_buf->size = etr_buf->size;
> + flat_buf->dev = drvdata->dev;
> + etr_buf->hwaddr = flat_buf->daddr;
> + etr_buf->mode = ETR_MODE_FLAT;
> + etr_buf->private = flat_buf;
> + return 0;
> +}
> +
> +static void tmc_etr_free_flat_buf(struct etr_buf *etr_buf)
> +{
> + struct etr_flat_buf *flat_buf = etr_buf->private;
> +
> + if (flat_buf && flat_buf->daddr)
> + dma_free_coherent(flat_buf->dev, flat_buf->size,
> + flat_buf->vaddr, flat_buf->daddr);
> + kfree(flat_buf);
> +}
> +
> +static void tmc_etr_sync_flat_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
> +{
> + /*
> + * Adjust the buffer to point to the beginning of the trace data
> + * and update the available trace data.
> + */
> + etr_buf->offset = rrp - etr_buf->hwaddr;
> + if (etr_buf->full)
> + etr_buf->len = etr_buf->size;
> + else
> + etr_buf->len = rwp - rrp;
> +}
> +
> +static ssize_t tmc_etr_get_data_flat_buf(struct etr_buf *etr_buf,
> + u64 offset, size_t len, char **bufpp)
> +{
> + struct etr_flat_buf *flat_buf = etr_buf->private;
> +
> + *bufpp = (char *)flat_buf->vaddr + offset;
> + /*
> + * tmc_etr_buf_get_data already adjusts the length to handle
> + * buffer wrapping around.
> + */
> + return len;
> +}
> +
> +static const struct etr_buf_operations etr_flat_buf_ops = {
> + .alloc = tmc_etr_alloc_flat_buf,
> + .free = tmc_etr_free_flat_buf,
> + .sync = tmc_etr_sync_flat_buf,
> + .get_data = tmc_etr_get_data_flat_buf,
> +};
> +
> +/*
> + * tmc_etr_alloc_sg_buf: Allocate an SG buf @etr_buf. Setup the parameters
> + * appropriately.
> + */
> +static int tmc_etr_alloc_sg_buf(struct tmc_drvdata *drvdata,
> + struct etr_buf *etr_buf, int node,
> + void **pages)
> +{
> + struct etr_sg_table *etr_table;
> +
> + etr_table = tmc_init_etr_sg_table(drvdata->dev, node,
> + etr_buf->size, pages);
> + if (IS_ERR(etr_table))
> + return -ENOMEM;
> + etr_buf->hwaddr = etr_table->hwaddr;
> + etr_buf->mode = ETR_MODE_ETR_SG;
> + etr_buf->private = etr_table;
> + return 0;
> +}
> +
> +static void tmc_etr_free_sg_buf(struct etr_buf *etr_buf)
> +{
> + struct etr_sg_table *etr_table = etr_buf->private;
> +
> + if (etr_table) {
> + tmc_free_sg_table(etr_table->sg_table);
> + kfree(etr_table);
> + }
> +}
> +
> +static ssize_t tmc_etr_get_data_sg_buf(struct etr_buf *etr_buf, u64 offset,
> + size_t len, char **bufpp)
> +{
> + struct etr_sg_table *etr_table = etr_buf->private;
> +
> + return tmc_sg_table_get_data(etr_table->sg_table, offset, len, bufpp);
> +}
> +
> +static void tmc_etr_sync_sg_buf(struct etr_buf *etr_buf, u64 rrp, u64 rwp)
> +{
> + long r_offset, w_offset;
> + struct etr_sg_table *etr_table = etr_buf->private;
> + struct tmc_sg_table *table = etr_table->sg_table;
> +
> + /* Convert hw address to offset in the buffer */
> + r_offset = tmc_sg_get_data_page_offset(table, rrp);
> + if (r_offset < 0) {
> + dev_warn(table->dev,
> + "Unable to map RRP %llx to offset\n", rrp);
> + etr_buf->len = 0;
> + return;
> + }
> +
> + w_offset = tmc_sg_get_data_page_offset(table, rwp);
> + if (w_offset < 0) {
> + dev_warn(table->dev,
> + "Unable to map RWP %llx to offset\n", rwp);
> + etr_buf->len = 0;
> + return;
> + }
> +
> + etr_buf->offset = r_offset;
> + if (etr_buf->full)
> + etr_buf->len = etr_buf->size;
> + else
> + etr_buf->len = ((w_offset < r_offset) ? etr_buf->size : 0) +
> + w_offset - r_offset;
> + tmc_sg_table_sync_data_range(table, r_offset, etr_buf->len);
> +}
> +
> +static const struct etr_buf_operations etr_sg_buf_ops = {
> + .alloc = tmc_etr_alloc_sg_buf,
> + .free = tmc_etr_free_sg_buf,
> + .sync = tmc_etr_sync_sg_buf,
> + .get_data = tmc_etr_get_data_sg_buf,
> +};
> +
> +static const struct etr_buf_operations *etr_buf_ops[] = {
> + [ETR_MODE_FLAT] = &etr_flat_buf_ops,
> + [ETR_MODE_ETR_SG] = &etr_sg_buf_ops,
> +};
> +
> +static inline int tmc_etr_mode_alloc_buf(int mode,
> + struct tmc_drvdata *drvdata,
> + struct etr_buf *etr_buf, int node,
> + void **pages)
> +{
> + int rc;
> +
> + switch (mode) {
> + case ETR_MODE_FLAT:
> + case ETR_MODE_ETR_SG:
> + rc = etr_buf_ops[mode]->alloc(drvdata, etr_buf, node, pages);
> + if (!rc)
> + etr_buf->ops = etr_buf_ops[mode];
> + return rc;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +/*
> + * tmc_alloc_etr_buf: Allocate a buffer use by ETR.
> + * @drvdata : ETR device details.
> + * @size : size of the requested buffer.
> + * @flags : Required properties for the buffer.
> + * @node : Node for memory allocations.
> + * @pages : An optional list of pages.
> + */
> +static struct etr_buf *tmc_alloc_etr_buf(struct tmc_drvdata *drvdata,
> + ssize_t size, int flags,
> + int node, void **pages)
> +{
> + int rc = -ENOMEM;
> + bool has_etr_sg, has_iommu;
> + struct etr_buf *etr_buf;
> +
> + has_etr_sg = tmc_etr_has_cap(drvdata, TMC_ETR_SG);
> + has_iommu = iommu_get_domain_for_dev(drvdata->dev);
> +
> + etr_buf = kzalloc(sizeof(*etr_buf), GFP_KERNEL);
> + if (!etr_buf)
> + return ERR_PTR(-ENOMEM);
> +
> + etr_buf->size = size;
> +
> + /*
> + * If we have to use an existing list of pages, we cannot reliably
> + * use a contiguous DMA memory (even if we have an IOMMU). Otherwise,
> + * we use the contiguous DMA memory if at least one of the following
> + * conditions is true:
> + * a) The ETR cannot use Scatter-Gather.
> + * b) we have a backing IOMMU
> + * c) The requested memory size is smaller (< 1M).
> + *
> + * Fallback to available mechanisms.
> + *
> + */
> + if (!pages &&
> + (!has_etr_sg || has_iommu || size < SZ_1M))
> + rc = tmc_etr_mode_alloc_buf(ETR_MODE_FLAT, drvdata,
> + etr_buf, node, pages);
> + if (rc && has_etr_sg)
> + rc = tmc_etr_mode_alloc_buf(ETR_MODE_ETR_SG, drvdata,
> + etr_buf, node, pages);
> + if (rc) {
> + kfree(etr_buf);
> + return ERR_PTR(rc);
> + }
> +
> + return etr_buf;
> +}
> +
> +static void tmc_free_etr_buf(struct etr_buf *etr_buf)
> +{
> + WARN_ON(!etr_buf->ops || !etr_buf->ops->free);
> + etr_buf->ops->free(etr_buf);
> + kfree(etr_buf);
> +}
> +
> +/*
> + * tmc_etr_buf_get_data: Get the pointer the trace data at @offset
> + * with a maximum of @len bytes.
> + * Returns: The size of the linear data available @pos, with *bufpp
> + * updated to point to the buffer.
> + */
> +static ssize_t tmc_etr_buf_get_data(struct etr_buf *etr_buf,
> + u64 offset, size_t len, char **bufpp)
> +{
> + /* Adjust the length to limit this transaction to end of buffer */
> + len = (len < (etr_buf->size - offset)) ? len : etr_buf->size - offset;
> +
> + return etr_buf->ops->get_data(etr_buf, (u64)offset, len, bufpp);
> +}
> +
> +static inline s64
> +tmc_etr_buf_insert_barrier_packet(struct etr_buf *etr_buf, u64 offset)
> +{
> + ssize_t len;
> + char *bufp;
> +
> + len = tmc_etr_buf_get_data(etr_buf, offset,
> + CORESIGHT_BARRIER_PKT_SIZE, &bufp);
> + if (WARN_ON(len <= CORESIGHT_BARRIER_PKT_SIZE))
> + return -EINVAL;
> + coresight_insert_barrier_packet(bufp);
> + return offset + CORESIGHT_BARRIER_PKT_SIZE;
> +}
> +
> +/*
> + * tmc_sync_etr_buf: Sync the trace buffer availability with drvdata.
> + * Makes sure the trace data is synced to the memory for consumption.
> + * @etr_buf->offset will hold the offset to the beginning of the trace data
> + * within the buffer, with @etr_buf->len bytes to consume.
> + */
> +static void tmc_sync_etr_buf(struct tmc_drvdata *drvdata)
> +{
> + struct etr_buf *etr_buf = drvdata->etr_buf;
> + u64 rrp, rwp;
> + u32 status;
> +
> + rrp = tmc_read_rrp(drvdata);
> + rwp = tmc_read_rwp(drvdata);
> + status = readl_relaxed(drvdata->base + TMC_STS);
> + etr_buf->full = status & TMC_STS_FULL;
> +
> + WARN_ON(!etr_buf->ops || !etr_buf->ops->sync);
> +
> + etr_buf->ops->sync(etr_buf, rrp, rwp);
> +
> + /* Insert barrier packets at the beginning, if there was an overflow */
> + if (etr_buf->full)
> + tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
> +}
> +
> static inline void tmc_etr_enable_catu(struct tmc_drvdata *drvdata)
> {
> struct coresight_device *catu = tmc_etr_get_catu_device(drvdata);
> @@ -721,6 +1018,7 @@ static inline void tmc_etr_disable_catu(struct tmc_drvdata *drvdata)
> static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> {
> u32 axictl, sts;
> + struct etr_buf *etr_buf = drvdata->etr_buf;
>
> /*
> * If this ETR is connected to a CATU, enable it before we turn
> @@ -733,7 +1031,7 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> /* Wait for TMCSReady bit to be set */
> tmc_wait_for_tmcready(drvdata);
>
> - writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
> + writel_relaxed(etr_buf->size / 4, drvdata->base + TMC_RSZ);
> writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
>
> axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
> @@ -746,16 +1044,22 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> axictl |= TMC_AXICTL_ARCACHE_OS;
> }
>
> + if (etr_buf->mode == ETR_MODE_ETR_SG) {
> + if (WARN_ON(!tmc_etr_has_cap(drvdata, TMC_ETR_SG)))
> + return;
> + axictl |= TMC_AXICTL_SCT_GAT_MODE;
> + }
> +
> writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
> - tmc_write_dba(drvdata, drvdata->paddr);
> + tmc_write_dba(drvdata, etr_buf->hwaddr);
> /*
> * If the TMC pointers must be programmed before the session,
> * we have to set it properly (i.e, RRP/RWP to base address and
> * STS to "not full").
> */
> if (tmc_etr_has_cap(drvdata, TMC_ETR_SAVE_RESTORE)) {
> - tmc_write_rrp(drvdata, drvdata->paddr);
> - tmc_write_rwp(drvdata, drvdata->paddr);
> + tmc_write_rrp(drvdata, etr_buf->hwaddr);
> + tmc_write_rwp(drvdata, etr_buf->hwaddr);
> sts = readl_relaxed(drvdata->base + TMC_STS) & ~TMC_STS_FULL;
> writel_relaxed(sts, drvdata->base + TMC_STS);
> }
> @@ -771,63 +1075,53 @@ static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
> }
>
> /*
> - * Return the available trace data in the buffer @pos, with a maximum
> - * limit of @len, also updating the @bufpp on where to find it.
> + * Return the available trace data in the buffer (starts at etr_buf->offset,
> + * limited by etr_buf->len) from @pos, with a maximum limit of @len,
> + * also updating the @bufpp on where to find it. Since the trace data
> + * starts at anywhere in the buffer, depending on the RRP, we adjust the
> + * @len returned to handle buffer wrapping around.
> */
> ssize_t tmc_etr_get_sysfs_trace(struct tmc_drvdata *drvdata,
> - loff_t pos, size_t len, char **bufpp)
> + loff_t pos, size_t len, char **bufpp)
> {
> + s64 offset;
> ssize_t actual = len;
> - char *bufp = drvdata->buf + pos;
> - char *bufend = (char *)(drvdata->vaddr + drvdata->size);
> -
> - /* Adjust the len to available size @pos */
> - if (pos + actual > drvdata->len)
> - actual = drvdata->len - pos;
> + struct etr_buf *etr_buf = drvdata->etr_buf;
>
> + if (pos + actual > etr_buf->len)
> + actual = etr_buf->len - pos;
> if (actual <= 0)
> return actual;
>
> - /*
> - * Since we use a circular buffer, with trace data starting
> - * @drvdata->buf, possibly anywhere in the buffer @drvdata->vaddr,
> - * wrap the current @pos to within the buffer.
> - */
> - if (bufp >= bufend)
> - bufp -= drvdata->size;
> - /*
> - * For simplicity, avoid copying over a wrapped around buffer.
> - */
> - if ((bufp + actual) > bufend)
> - actual = bufend - bufp;
> - *bufpp = bufp;
> - return actual;
> + /* Compute the offset from which we read the data */
> + offset = etr_buf->offset + pos;
> + if (offset >= etr_buf->size)
> + offset -= etr_buf->size;
> + return tmc_etr_buf_get_data(etr_buf, offset, actual, bufpp);
> }
>
> -static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
> +static struct etr_buf *
> +tmc_etr_setup_sysfs_buf(struct tmc_drvdata *drvdata)
> {
> - u32 val;
> - u64 rwp;
> + return tmc_alloc_etr_buf(drvdata, drvdata->size,
> + 0, cpu_to_node(0), NULL);
> +}
>
> - rwp = tmc_read_rwp(drvdata);
> - val = readl_relaxed(drvdata->base + TMC_STS);
> +static void
> +tmc_etr_free_sysfs_buf(struct etr_buf *buf)
> +{
> + if (buf)
> + tmc_free_etr_buf(buf);
> +}
>
> - /*
> - * Adjust the buffer to point to the beginning of the trace data
> - * and update the available trace data.
> - */
> - if (val & TMC_STS_FULL) {
> - drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
> - drvdata->len = drvdata->size;
> - coresight_insert_barrier_packet(drvdata->buf);
> - } else {
> - drvdata->buf = drvdata->vaddr;
> - drvdata->len = rwp - drvdata->paddr;
> - }
> +static void tmc_etr_sync_sysfs_buf(struct tmc_drvdata *drvdata)
> +{
> + tmc_sync_etr_buf(drvdata);
> }
>
> static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> {
> +
> CS_UNLOCK(drvdata->base);
>
> tmc_flush_and_stop(drvdata);
> @@ -836,7 +1130,8 @@ static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
> * read before the TMC is disabled.
> */
> if (drvdata->mode == CS_MODE_SYSFS)
> - tmc_etr_dump_hw(drvdata);
> + tmc_etr_sync_sysfs_buf(drvdata);
> +
> tmc_disable_hw(drvdata);
>
> CS_LOCK(drvdata->base);
> @@ -850,34 +1145,31 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
> int ret = 0;
> bool used = false;
> unsigned long flags;
> - void __iomem *vaddr = NULL;
> - dma_addr_t paddr;
> struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
> + struct etr_buf *new_buf = NULL, *free_buf = NULL;
>
>
> /*
> - * If we don't have a buffer release the lock and allocate memory.
> - * Otherwise keep the lock and move along.
> + * If we are enabling the ETR from disabled state, we need to make
> + * sure we have a buffer with the right size. The etr_buf is not reset
> + * immediately after we stop the tracing in SYSFS mode as we wait for
> + * the user to collect the data. We may be able to reuse the existing
> + * buffer, provided the size matches. Any allocation has to be done
> + * with the lock released.
> */
> spin_lock_irqsave(&drvdata->spinlock, flags);
> - if (!drvdata->vaddr) {
> + if (!drvdata->etr_buf || (drvdata->etr_buf->size != drvdata->size)) {
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
> -
> - /*
> - * Contiguous memory can't be allocated while a spinlock is
> - * held. As such allocate memory here and free it if a buffer
> - * has already been allocated (from a previous session).
> - */
> - vaddr = dma_alloc_coherent(drvdata->dev, drvdata->size,
> - &paddr, GFP_KERNEL);
> - if (!vaddr)
> - return -ENOMEM;
> + /* Allocate memory with the spinlock released */
> + free_buf = new_buf = tmc_etr_setup_sysfs_buf(drvdata);
> + if (IS_ERR(new_buf))
> + return PTR_ERR(new_buf);
>
> /* Let's try again */
> spin_lock_irqsave(&drvdata->spinlock, flags);
> }
>
> - if (drvdata->reading) {
> + if (drvdata->reading || drvdata->mode == CS_MODE_PERF) {
> ret = -EBUSY;
> goto out;
> }
> @@ -885,21 +1177,20 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
> /*
> * In sysFS mode we can have multiple writers per sink. Since this
> * sink is already enabled no memory is needed and the HW need not be
> - * touched.
> + * touched, even if the buffer size has changed.
> */
> if (drvdata->mode == CS_MODE_SYSFS)
> goto out;
>
> /*
> - * If drvdata::buf == NULL, use the memory allocated above.
> - * Otherwise a buffer still exists from a previous session, so
> - * simply use that.
> + * If we don't have a buffer or it doesn't match the requested size,
> + * use the memory allocated above. Otherwise reuse it.
> */
> - if (drvdata->buf == NULL) {
> + if (!drvdata->etr_buf ||
> + (new_buf && drvdata->etr_buf->size != new_buf->size)) {
> used = true;
> - drvdata->vaddr = vaddr;
> - drvdata->paddr = paddr;
> - drvdata->buf = drvdata->vaddr;
> + free_buf = drvdata->etr_buf;
> + drvdata->etr_buf = new_buf;
> }
>
> drvdata->mode = CS_MODE_SYSFS;
> @@ -908,8 +1199,8 @@ static int tmc_enable_etr_sink_sysfs(struct coresight_device *csdev)
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
>
> /* Free memory outside the spinlock if need be */
> - if (!used && vaddr)
> - dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr);
> + if (free_buf)
> + tmc_etr_free_sysfs_buf(free_buf);
>
> if (!ret)
> dev_info(drvdata->dev, "TMC-ETR enabled\n");
> @@ -988,8 +1279,8 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
> goto out;
> }
>
> - /* If drvdata::buf is NULL the trace data has been read already */
> - if (drvdata->buf == NULL) {
> + /* If drvdata::etr_buf is NULL the trace data has been read already */
> + if (drvdata->etr_buf == NULL) {
> ret = -EINVAL;
> goto out;
> }
> @@ -1008,8 +1299,7 @@ int tmc_read_prepare_etr(struct tmc_drvdata *drvdata)
> int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
> {
> unsigned long flags;
> - dma_addr_t paddr;
> - void __iomem *vaddr = NULL;
> + struct etr_buf *etr_buf = NULL;
>
> /* config types are set a boot time and never change */
> if (WARN_ON_ONCE(drvdata->config_type != TMC_CONFIG_TYPE_ETR))
> @@ -1030,17 +1320,16 @@ int tmc_read_unprepare_etr(struct tmc_drvdata *drvdata)
> * The ETR is not tracing and the buffer was just read.
> * As such prepare to free the trace buffer.
> */
> - vaddr = drvdata->vaddr;
> - paddr = drvdata->paddr;
> - drvdata->buf = drvdata->vaddr = NULL;
> + etr_buf = drvdata->etr_buf;
> + drvdata->etr_buf = NULL;
> }
>
> drvdata->reading = false;
> spin_unlock_irqrestore(&drvdata->spinlock, flags);
>
> /* Free allocated memory out side of the spinlock */
> - if (vaddr)
> - dma_free_coherent(drvdata->dev, drvdata->size, vaddr, paddr);
> + if (etr_buf)
> + tmc_free_etr_buf(etr_buf);
>
> return 0;
> }
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index 74d8f24..6f7bec7 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -56,6 +56,7 @@
> #define TMC_STS_TMCREADY_BIT 2
> #define TMC_STS_FULL BIT(0)
> #define TMC_STS_TRIGGERED BIT(1)
> +
> /*
> * TMC_AXICTL - 0x110
> *
> @@ -135,6 +136,35 @@ enum tmc_mem_intf_width {
> #define CORESIGHT_SOC_600_ETR_CAPS \
> (TMC_ETR_SAVE_RESTORE | TMC_ETR_AXI_ARCACHE)
>
> +enum etr_mode {
> + ETR_MODE_FLAT, /* Uses contiguous flat buffer */
> + ETR_MODE_ETR_SG, /* Uses in-built TMC ETR SG mechanism */
> +};
> +
> +struct etr_buf_operations;
> +
> +/**
> + * struct etr_buf - Details of the buffer used by ETR
> + * @mode : Mode of the ETR buffer, contiguous, Scatter Gather etc.
> + * @full : Trace data overflow
> + * @size : Size of the buffer.
> + * @hwaddr : Address to be programmed in the TMC:DBA{LO,HI}
> + * @offset : Offset of the trace data in the buffer for consumption.
> + * @len : Available trace data @buf (may round up to the beginning).
> + * @ops : ETR buffer operations for the mode.
> + * @private : Backend specific information for the buf
> + */
> +struct etr_buf {
> + enum etr_mode mode;
> + bool full;
> + ssize_t size;
> + dma_addr_t hwaddr;
> + unsigned long offset;
> + s64 len;
> + const struct etr_buf_operations *ops;
> + void *private;
> +};
> +
> /**
> * struct tmc_drvdata - specifics associated to an TMC component
> * @base: memory mapped base address for this component.
> @@ -142,11 +172,10 @@ enum tmc_mem_intf_width {
> * @csdev: component vitals needed by the framework.
> * @miscdev: specifics to handle "/dev/xyz.tmc" entry.
> * @spinlock: only one at a time pls.
> - * @buf: area of memory where trace data get sent.
> - * @paddr: DMA start location in RAM.
> - * @vaddr: virtual representation of @paddr.
> - * @size: trace buffer size.
> - * @len: size of the available trace.
> + * @buf: Snapshot of the trace data for ETF/ETB.
> + * @etr_buf: details of buffer used in TMC-ETR
> + * @len: size of the available trace for ETF/ETB.
> + * @size: trace buffer size for this TMC (common for all modes).
> * @mode: how this TMC is being used.
> * @config_type: TMC variant, must be of type @tmc_config_type.
> * @memwidth: width of the memory interface databus, in bytes.
> @@ -161,11 +190,12 @@ struct tmc_drvdata {
> struct miscdevice miscdev;
> spinlock_t spinlock;
> bool reading;
> - char *buf;
> - dma_addr_t paddr;
> - void __iomem *vaddr;
> - u32 size;
> + union {
> + char *buf; /* TMC ETB */
> + struct etr_buf *etr_buf; /* TMC ETR */
> + };
> u32 len;
> + u32 size;
> u32 mode;
> enum tmc_config_type config_type;
> enum tmc_mem_intf_width memwidth;
> @@ -173,6 +203,15 @@ struct tmc_drvdata {
> u32 etr_caps;
> };
>
> +struct etr_buf_operations {
> + int (*alloc)(struct tmc_drvdata *drvdata, struct etr_buf *etr_buf,
> + int node, void **pages);
> + void (*sync)(struct etr_buf *etr_buf, u64 rrp, u64 rwp);
> + ssize_t (*get_data)(struct etr_buf *etr_buf, u64 offset, size_t len,
> + char **bufpp);
> + void (*free)(struct etr_buf *etr_buf);
> +};
> +
> /**
> * struct tmc_pages - Collection of pages used for SG.
> * @nr_pages: Number of pages in the list.
> --
> 2.7.4
>
^ permalink raw reply
* [PATCH v3] tty/serial: atmel: use port->name as name in request_irq()
From: Sebastian Andrzej Siewior @ 2018-05-07 17:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAL_JsqJ+84OFyN07XWsb0hSHxtxL_V6gSfO+iMSOU1bceztr3Q@mail.gmail.com>
I was puzzled while looking at /proc/interrupts and random things showed
up between reboots. This occurred more often but I realised it later. The
"correct" output should be:
|38: 11861 atmel-aic5 2 Level ttyS0
but I saw sometimes
|38: 6426 atmel-aic5 2 Level tty1
and accounted it wrongly as correct. This is use after free and the
former example randomly got the "old" pointer which pointed to the same
content. With SLAB_FREELIST_RANDOM and HARDENED I even got
|38: 7067 atmel-aic5 2 Level E=Started User Manager for UID 0
or other nonsense.
As it turns out the tty, pointer that is accessed in atmel_startup(), is
freed() before atmel_shutdown(). It seems to happen quite often that the
tty for ttyS0 is allocated and freed while ->shutdown is not invoked. I
don't do anything special - just a systemd boot :)
Use dev_name(&pdev->dev) as the IRQ name for request_irq(). This exists
as long as the driver is loaded so no use-after-free here.
Cc: stable at vger.kernel.org
Fixes: 761ed4a94582 ("tty: serial_core: convert uart_close to use tty_port_close")
Acked-by: Richard Genoud <richard.genoud@gmail.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
---
v2?v3: - Add Acked-by
- replace port->name -> dev_name(&pdev->dev) to ease work for
backporters (suggested by Rob)
v1?v2: add Fixes after bisect.
drivers/tty/serial/atmel_serial.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index e287fe8f10fc..55b3eff148b1 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -1757,7 +1757,6 @@ static int atmel_startup(struct uart_port *port)
{
struct platform_device *pdev = to_platform_device(port->dev);
struct atmel_uart_port *atmel_port = to_atmel_uart_port(port);
- struct tty_struct *tty = port->state->port.tty;
int retval;
/*
@@ -1772,8 +1771,8 @@ static int atmel_startup(struct uart_port *port)
* Allocate the IRQ
*/
retval = request_irq(port->irq, atmel_interrupt,
- IRQF_SHARED | IRQF_COND_SUSPEND,
- tty ? tty->name : "atmel_serial", port);
+ IRQF_SHARED | IRQF_COND_SUSPEND,
+ dev_name(&pdev->dev), port);
if (retval) {
dev_err(port->dev, "atmel_startup - Can't get irq\n");
return retval;
--
2.17.0
^ permalink raw reply related
* [PATCH v2 1/2] ARM: dts: am335x: Replace numeric pinmux address with macro defines
From: Rob Herring @ 2018-05-07 17:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180505085921.5513-2-cquast@baylibre.com>
On Sat, May 05, 2018 at 10:59:20AM +0200, Christina Quast wrote:
> The values are extraced from the "AM335x SitaraTM Processors Technical
> Reference Manual", Section 9.3.1 CONTROL_MODULE Registers, based on the
> file autogenerated by TI PinMux.
>
> The register conf_rtc_kaldo_enn was removed from the Control Module
> Registers table with Revision M.
>
> Signed-off-by: Christina Quast <cquast@baylibre.com>
> Signed-off-by: Oleg Kokorin <ole2mail@mail.com>
> ---
> include/dt-bindings/pinctrl/am335x.h | 147 +++++++++++++++++++++++++++
> 1 file changed, 147 insertions(+)
> create mode 100644 include/dt-bindings/pinctrl/am335x.h
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v2 1/2] dt-bindings: add MediaTek XS-PHY binding
From: Rob Herring @ 2018-05-07 17:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525486506-19301-2-git-send-email-chunfeng.yun@mediatek.com>
On Sat, May 05, 2018 at 10:15:05AM +0800, Chunfeng Yun wrote:
> Add a DT binding documentation of XS-PHY for MediaTek SoCs
> with USB3.1 GEN2 controller
>
> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
> ---
> .../devicetree/bindings/phy/phy-mtk-xsphy.txt | 110 ++++++++++++++++++++
> 1 file changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> new file mode 100644
> index 0000000..9a95fab
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/phy-mtk-xsphy.txt
> @@ -0,0 +1,110 @@
> +MediaTek XS-PHY binding
> +--------------------------
> +
> +The XS-PHY controller supports physical layer functionality for USB3.1
> +GEN2 controller on MediaTek SoCs.
> +
> +Required properties (controller (parent) node):
> + - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy",
> + soc-model is the name of SoC, such as mt2712 etc;
> + when using "mediatek,xsphy" compatible string, you need SoC specific
> + ones in addition, one of:
> + - "mediatek,mt3611-xsphy"
What about mt2712 you mention above?
^ permalink raw reply
* [PATCHv2 3/3] arm64: dts: stratix10: add sdram ecc
From: Borislav Petkov @ 2018-05-07 16:59 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1524854238-19394-4-git-send-email-thor.thayer@linux.intel.com>
On Fri, Apr 27, 2018 at 01:37:18PM -0500, thor.thayer at linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Add the Stratix10 ECC Manager and SDRAM EDAC nodes to the
> device tree.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
> v2 Remove unused SysMan syscon
> Remove unused SDRAM ECC register defines
> Remove unused address, size and range from device tree.
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> index c89d0c307f8d..688391f3bf78 100644
> --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
> @@ -387,5 +387,17 @@
> resets = <&rst WATCHDOG3_RESET>;
> status = "disabled";
> };
> +
> + eccmgr {
> + compatible = "altr,socfpga-s10-ecc-manager";
> + interrupts = <0 15 4>, <0 95 4>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> +
> + sdramedac {
> + compatible = "altr,sdram-edac-s10";
> + interrupts = <16 4>, <48 4>;
> + };
> + };
> };
> };
> --
> 2.7.4
>
> --
Hey Rob,
ACK here too?
Also, this one:
https://lkml.kernel.org/r/1525203036-21774-1-git-send-email-thor.thayer at linux.intel.com
?
Thx.
--
Regards/Gruss,
Boris.
Good mailing practices for 400: avoid top-posting and trim the reply.
^ permalink raw reply
* [PATCH V2 2/8] dt-bindings: stm32-dwmac: add support of MPU families
From: Rob Herring @ 2018-05-07 16:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525270723-18241-3-git-send-email-christophe.roullier@st.com>
On Wed, May 02, 2018 at 04:18:37PM +0200, Christophe Roullier wrote:
> Add description for Ethernet MPU families fields
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
> ---
> Documentation/devicetree/bindings/net/stm32-dwmac.txt | 18 ++++++++++++++++--
> 1 file changed, 16 insertions(+), 2 deletions(-)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH V2 4/8] ARM: dts: stm32: Add syscfg on stm32mp1
From: Rob Herring @ 2018-05-07 16:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525270723-18241-5-git-send-email-christophe.roullier@st.com>
On Wed, May 02, 2018 at 04:18:39PM +0200, Christophe Roullier wrote:
> System configuration controller is mainly used to manage
> the compensation cell and other IOs and system related
> settings.
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
> ---
> arch/arm/boot/dts/stm32mp157c.dtsi | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
> index bc3eddc..86421ba 100644
> --- a/arch/arm/boot/dts/stm32mp157c.dtsi
> +++ b/arch/arm/boot/dts/stm32mp157c.dtsi
> @@ -167,6 +167,11 @@
> #reset-cells = <1>;
> };
>
> + syscfg: system-config at 50020000 {
> + compatible = "syscon";
> + reg = <0x50020000 0x400>;
> + };
NAK as explained in the documentation patch.
Rob
^ permalink raw reply
* [PATCH V2 8/8] dt-bindings: stm32: add compatible for syscon
From: Rob Herring @ 2018-05-07 16:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525270723-18241-9-git-send-email-christophe.roullier@st.com>
On Wed, May 02, 2018 at 04:18:43PM +0200, Christophe Roullier wrote:
> This patch describes syscon DT bindings.
>
> Signed-off-by: Christophe Roullier <christophe.roullier@st.com>
> ---
> Documentation/devicetree/bindings/arm/stm32.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/stm32.txt b/Documentation/devicetree/bindings/arm/stm32.txt
> index 6808ed9..06e3834 100644
> --- a/Documentation/devicetree/bindings/arm/stm32.txt
> +++ b/Documentation/devicetree/bindings/arm/stm32.txt
> @@ -8,3 +8,7 @@ using one of the following compatible strings:
> st,stm32f746
> st,stm32h743
> st,stm32mp157
> +
> +Required nodes:
> +- syscon: the soc bus node must have a system controller node pointing to the
> + global control registers, with the compatible string "syscon";
You misunderstood my prior comment. 'syscon' alone is not valid. You
need SoC specific compatible string for it and 'stm32' is not SoC
specific. IOW, the compatible property for a syscon should imply every
single register field in the block.
Rob
^ permalink raw reply
* [GIT PULL] one bug fix and few other fixes for v4.17-rc cycle
From: Tony Lindgren @ 2018-05-07 16:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHCN7xLZ-qY95qy6ntucc782nm9bzF=pV-G9KbFdk=dxww5sXg@mail.gmail.com>
* Adam Ford <aford173@gmail.com> [180507 16:28]:
> On Mon, May 7, 2018 at 10:31 AM, Tony Lindgren <tony@atomide.com> wrote:
> > OK reverted and pushed out omap-for-v4.17/fixes. Can you please
> > test that branch and make sure things are OK now?
>
> I just pulled everything, built and tested. We're good from my
> perspective. Thank you for your patience and help.
OK thanks!
Tony
^ permalink raw reply
* [PATCH v2 1/3] dt-bindings: iio: stm32-adc: add support for STM32MP1
From: Rob Herring @ 2018-05-07 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525247091-18143-2-git-send-email-fabrice.gasnier@st.com>
On Wed, May 02, 2018 at 09:44:49AM +0200, Fabrice Gasnier wrote:
> Document support for STM32MP1 ADC. It's quite similar to STM32H7 ADC.
> Introduce "st,stm32mp1-adc" compatible to handle variants of this
> hardware such as vregready flag, interrupts, clock rate.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> Changes in v2:
> - Update dt-bindings following Rob's remark: STM32MP1 ADC has two
> interrupt lines
> ---
> Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [GIT PULL] one bug fix and few other fixes for v4.17-rc cycle
From: Adam Ford @ 2018-05-07 16:26 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507153133.GN98604@atomide.com>
On Mon, May 7, 2018 at 10:31 AM, Tony Lindgren <tony@atomide.com> wrote:
> * Adam Ford <aford173@gmail.com> [180505 23:45]:
>> On Sat, May 5, 2018 at 2:43 PM, Tony Lindgren <tony@atomide.com> wrote:
>> > * Tony Lindgren <tony@atomide.com> [180504 15:51]:
>> >> From: "Tony Lindgren" <tony@atomide.com>
>> >>
>> >> The following changes since commit fb289e3ab10c16834741bb02be740fa9d025fde0:
>> >>
>> >> Merge branch 'omap-for-v4.17/fixes-ti-sysc' into omap-for-v4.17/fixes (2018-04-19 15:48:46 -0700)
>> >>
>> >> are available in the Git repository at:
>> >>
>> >> git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.17/fixes-rc3
>> >>
>> >> for you to fetch changes up to 647efef69de483f1dd7944ede31b4cae16acb124:
>> >>
>> >> ARM: dts: correct missing "compatible" entry for ti81xx SoCs (2018-05-03 10:07:47 -0700)
>> >>
>> >> ----------------------------------------------------------------
>> >> Fixes for omap variants for v4.17-rc cycle
>> >>
>> >> This series of patches contains one BUG fix for trace if
>> >> CONFIG_DEBUG_PREEMPT is enabled and a regression fix for omap1
>> >> FIQ handling on ams-delta. Then there's a dts fix for missing SoC
>> >> compatible on ti81xx board dts files that did matter until we added
>> >> the clkctrl clocks and without that some clocks are now not found.
>> >>
>> >> Then there are three minor logicpd-som-lv specific dts fixes that
>> >> fix misconfigured pins for WLAN, audio and USB.
>> >>
>> >> ----------------------------------------------------------------
>> >> Adam Ford (3):
>> >> ARM: dts: logicpd-som-lv: Fix WL127x Startup Issues
>> >> ARM: dts: logicpd-som-lv: Fix Audio Mute
>> >> ARM: dts: logicpd-som-lv: Fix pinmux controller references
>> >
>> > Adam emailled that one of these has a side effect for breaking
>> > USB. So let's not use this pull request if not yet merged, I'll
>> > send an updated pull request early next week.
>> >
>> The WL127x and Audio patches are good, but pinmux controller fails on
>> cold-boot, so I'd like to revert that one.
>
> OK reverted and pushed out omap-for-v4.17/fixes. Can you please
> test that branch and make sure things are OK now?
I just pulled everything, built and tested. We're good from my
perspective. Thank you for your patience and help.
adam
>
> Regards,
>
> Tony
^ permalink raw reply
* [PATCHv4 4/7] dt-bindings: fpga: add Stratix10 SoC FPGA manager binding
From: Rob Herring @ 2018-05-07 16:10 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525443697-31009-5-git-send-email-richard.gong@linux.intel.com>
On Fri, May 04, 2018 at 09:21:34AM -0500, richard.gong at linux.intel.com wrote:
> From: Alan Tull <atull@kernel.org>
>
> Add a Device Tree binding for the Intel Stratix10 SoC FPGA manager.
>
> Signed-off-by: Alan Tull <atull@kernel.org>
> Signed-off-by: Richard Gong <richard.gong@intel.com>
> ---
> v2: this patch is added in patch set version 2
> v3: change to put fpga_mgr node under firmware/svc node
> v4: s/fpga-mgr at 0/fpga-mgr/ to remove unit_address
> Add Richard's signed-off-by
> ---
> .../bindings/fpga/intel-stratix10-soc-fpga-mgr.txt | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/intel-stratix10-soc-fpga-mgr.txt
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v5 10/14] dt-bindings: qcom_spmi: Add support for SAW documentation
From: Rob Herring @ 2018-05-07 16:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525348355-25471-11-git-send-email-ilialin@codeaurora.org>
On Thu, May 03, 2018 at 02:52:31PM +0300, Ilia Lin wrote:
> Add support for SAW controlled regulators.
> The regulators defined as SAW controlled in the device tree
> will be controlled through special CPU registers instead of direct
> SPMI accesses.
> This is required especially for CPU supply regulators to synchronize
> with clock scaling and for Automatic Voltage Switching.
> Document it.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* [PATCH v3 11/14] media: platform: Add Sunxi-Cedrus VPU decoder driver
From: Maxime Ripard @ 2018-05-07 15:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507124500.20434-12-paul.kocialkowski@bootlin.com>
On Mon, May 07, 2018 at 02:44:57PM +0200, Paul Kocialkowski wrote:
> +#define SYSCON_SRAM_CTRL_REG0 0x0
> +#define SYSCON_SRAM_C1_MAP_VE 0x7fffffff
This isn't needed anymore
> + dev->ahb_clk = devm_clk_get(dev->dev, "ahb");
> + if (IS_ERR(dev->ahb_clk)) {
> + dev_err(dev->dev, "failed to get ahb clock\n");
> + return PTR_ERR(dev->ahb_clk);
> + }
> + dev->mod_clk = devm_clk_get(dev->dev, "mod");
> + if (IS_ERR(dev->mod_clk)) {
> + dev_err(dev->dev, "failed to get mod clock\n");
> + return PTR_ERR(dev->mod_clk);
> + }
> + dev->ram_clk = devm_clk_get(dev->dev, "ram");
> + if (IS_ERR(dev->ram_clk)) {
> + dev_err(dev->dev, "failed to get ram clock\n");
> + return PTR_ERR(dev->ram_clk);
> + }
Please add some blank lines between those blocks
> + dev->rstc = devm_reset_control_get(dev->dev, NULL);
You're not checking the error code here
> + dev->syscon = syscon_regmap_lookup_by_phandle(dev->dev->of_node,
> + "syscon");
> + if (IS_ERR(dev->syscon)) {
> + dev->syscon = NULL;
> + } else {
> + regmap_write_bits(dev->syscon, SYSCON_SRAM_CTRL_REG0,
> + SYSCON_SRAM_C1_MAP_VE,
> + SYSCON_SRAM_C1_MAP_VE);
> + }
You don't need the syscon part anymore either
> + ret = clk_prepare_enable(dev->ahb_clk);
> + if (ret) {
> + dev_err(dev->dev, "could not enable ahb clock\n");
> + return -EFAULT;
> + }
> + ret = clk_prepare_enable(dev->mod_clk);
> + if (ret) {
> + clk_disable_unprepare(dev->ahb_clk);
> + dev_err(dev->dev, "could not enable mod clock\n");
> + return -EFAULT;
> + }
> + ret = clk_prepare_enable(dev->ram_clk);
> + if (ret) {
> + clk_disable_unprepare(dev->mod_clk);
> + clk_disable_unprepare(dev->ahb_clk);
> + dev_err(dev->dev, "could not enable ram clock\n");
> + return -EFAULT;
> + }
> +
> + ret = reset_control_reset(dev->rstc);
> + if (ret) {
> + clk_disable_unprepare(dev->ram_clk);
> + clk_disable_unprepare(dev->mod_clk);
> + clk_disable_unprepare(dev->ahb_clk);
> + dev_err(dev->dev, "could not reset device\n");
> + return -EFAULT;
labels would simplify this greatly, and you should also release the
sram and the memory region here.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply
* [GIT PULL] one bug fix and few other fixes for v4.17-rc cycle
From: Tony Lindgren @ 2018-05-07 15:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHCN7xJ8yAU=zjJuS6rPh61qNuRc7nr2e+i0z-YHCZQREcs0Yg@mail.gmail.com>
* Adam Ford <aford173@gmail.com> [180505 23:45]:
> On Sat, May 5, 2018 at 2:43 PM, Tony Lindgren <tony@atomide.com> wrote:
> > * Tony Lindgren <tony@atomide.com> [180504 15:51]:
> >> From: "Tony Lindgren" <tony@atomide.com>
> >>
> >> The following changes since commit fb289e3ab10c16834741bb02be740fa9d025fde0:
> >>
> >> Merge branch 'omap-for-v4.17/fixes-ti-sysc' into omap-for-v4.17/fixes (2018-04-19 15:48:46 -0700)
> >>
> >> are available in the Git repository at:
> >>
> >> git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap tags/omap-for-v4.17/fixes-rc3
> >>
> >> for you to fetch changes up to 647efef69de483f1dd7944ede31b4cae16acb124:
> >>
> >> ARM: dts: correct missing "compatible" entry for ti81xx SoCs (2018-05-03 10:07:47 -0700)
> >>
> >> ----------------------------------------------------------------
> >> Fixes for omap variants for v4.17-rc cycle
> >>
> >> This series of patches contains one BUG fix for trace if
> >> CONFIG_DEBUG_PREEMPT is enabled and a regression fix for omap1
> >> FIQ handling on ams-delta. Then there's a dts fix for missing SoC
> >> compatible on ti81xx board dts files that did matter until we added
> >> the clkctrl clocks and without that some clocks are now not found.
> >>
> >> Then there are three minor logicpd-som-lv specific dts fixes that
> >> fix misconfigured pins for WLAN, audio and USB.
> >>
> >> ----------------------------------------------------------------
> >> Adam Ford (3):
> >> ARM: dts: logicpd-som-lv: Fix WL127x Startup Issues
> >> ARM: dts: logicpd-som-lv: Fix Audio Mute
> >> ARM: dts: logicpd-som-lv: Fix pinmux controller references
> >
> > Adam emailled that one of these has a side effect for breaking
> > USB. So let's not use this pull request if not yet merged, I'll
> > send an updated pull request early next week.
> >
> The WL127x and Audio patches are good, but pinmux controller fails on
> cold-boot, so I'd like to revert that one.
OK reverted and pushed out omap-for-v4.17/fixes. Can you please
test that branch and make sure things are OK now?
Regards,
Tony
^ permalink raw reply
* [PATCH v2 1/2] clk: davinci: pll-dm355: fix SYSCLKn parent names
From: Sekhar Nori @ 2018-05-07 15:21 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507144307.32364-1-david@lechnology.com>
On Monday 07 May 2018 08:13 PM, David Lechner wrote:
> This fixes the parent clock names of the SYSCLKn clocks for the DM355
> SoC in the TI DaVinici PLL clock driver.
>
> It appears that this name just didn't get updated to the correct name
> like the other SoCs during the driver's development.
>
> Reported-by: Sekhar Nori <nsekhar@ti.com>
> Signed-off-by: David Lechner <david@lechnology.com>
> ---
>
> v2 changes:
> - add second patch to fix additional problems with DM355
>
> drivers/clk/davinci/pll-dm355.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/clk/davinci/pll-dm355.c b/drivers/clk/davinci/pll-dm355.c
> index 5345f8286c50..1f746d2fc894 100644
> --- a/drivers/clk/davinci/pll-dm355.c
> +++ b/drivers/clk/davinci/pll-dm355.c
> @@ -22,10 +22,10 @@ static const struct davinci_pll_clk_info dm355_pll1_info = {
> PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
> };
>
> -SYSCLK(1, pll1_sysclk1, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> -SYSCLK(2, pll1_sysclk2, pll1, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> -SYSCLK(3, pll1_sysclk3, pll1, 5, SYSCLK_ALWAYS_ENABLED);
> -SYSCLK(4, pll1_sysclk4, pll1, 5, SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(1, pll1_sysclk1, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(2, pll1_sysclk2, pll1_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(3, pll1_sysclk3, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(4, pll1_sysclk4, pll1_pllen, 5, SYSCLK_ALWAYS_ENABLED);
>
> int dm355_pll1_init(struct device *dev, void __iomem *base)
> {
> @@ -62,8 +62,8 @@ static const struct davinci_pll_clk_info dm355_pll2_info = {
> PLL_POSTDIV_ALWAYS_ENABLED | PLL_POSTDIV_FIXED_DIV,
> };
>
> -SYSCLK(1, pll2_sysclk1, pll2, 5, SYSCLK_FIXED_DIV);
> -SYSCLK(2, pll2_sysclk2, pll2, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
> +SYSCLK(1, pll2_sysclk1, pll2_pllen, 5, SYSCLK_FIXED_DIV);
> +SYSCLK(2, pll2_sysclk2, pll2_pllen, 5, SYSCLK_FIXED_DIV | SYSCLK_ALWAYS_ENABLED);
Good find with PLL2 SYSCLK2. Can you reverse the patch order so we are
not fixing up a non-existent clock?
Thanks,
Sekhar
^ permalink raw reply
* [PATCH 5/5] arm64: allwinner: h6: enable USB3 port on Pine H64
From: Icenowy Zheng @ 2018-05-07 15:18 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507151817.55663-1-icenowy@aosc.io>
Pine H64 board have a USB3 port, which is connected to the USB3 pins of
the H6 SoC, and the 5V power supply is controlled via GPIO (shared with
the power USB ports).
Enable this port.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 23 +++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index b6f2d6b2ecae..e2e262b4e3d8 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -20,6 +20,20 @@
chosen {
stdout-path = "serial0:115200n8";
};
+
+ reg_usb_vbus: vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usb-vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ startup-delay-us = <100000>;
+ gpio = <&r_pio 0 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&dwc3 {
+ status = "okay";
};
&r_i2c {
@@ -37,3 +51,12 @@
pinctrl-0 = <&uart0_ph_pins>;
status = "okay";
};
+
+&usb3 {
+ status = "okay";
+};
+
+&usb3phy {
+ phy-supply = <®_usb_vbus>;
+ status = "okay";
+};
--
2.17.0
^ permalink raw reply related
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