* [PATCH v2 1/3] x86/mm: disable ioremap free page handling on x86-PAE
From: Toshi Kani @ 2018-05-15 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180515213931.23885-1-toshi.kani@hpe.com>
ioremap() supports pmd mappings on x86-PAE. However, kernel's pmd
tables are not shared among processes on x86-PAE. Therefore, any
update to sync'd pmd entries need re-syncing. Freeing a pte page
also leads to a vmalloc fault and hits the BUG_ON in vmalloc_sync_one().
Disable free page handling on x86-PAE. pud_free_pmd_page() and
pmd_free_pte_page() simply return 0 if a given pud/pmd entry is present.
This assures that ioremap() does not update sync'd pmd entries at the
cost of falling back to pte mappings.
Fixes: 28ee90fe6048 ("x86/mm: implement free pmd/pte page interfaces")
Reported-by: Joerg Roedel <joro@8bytes.org>
Signed-off-by: Toshi Kani <toshi.kani@hpe.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: <stable@vger.kernel.org>
---
arch/x86/mm/pgtable.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index ffc8c13c50e4..08cdd7c13619 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -715,6 +715,7 @@ int pmd_clear_huge(pmd_t *pmd)
return 0;
}
+#ifdef CONFIG_X86_64
/**
* pud_free_pmd_page - Clear pud entry and free pmd page.
* @pud: Pointer to a PUD.
@@ -762,4 +763,22 @@ int pmd_free_pte_page(pmd_t *pmd)
return 1;
}
+
+#else /* !CONFIG_X86_64 */
+
+int pud_free_pmd_page(pud_t *pud, unsigned long addr)
+{
+ return pud_none(*pud);
+}
+
+/*
+ * Disable free page handling on x86-PAE. This assures that ioremap()
+ * does not update sync'd pmd entries. See vmalloc_sync_one().
+ */
+int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
+{
+ return pmd_none(*pmd);
+}
+
+#endif /* CONFIG_X86_64 */
#endif /* CONFIG_HAVE_ARCH_HUGE_VMAP */
^ permalink raw reply related
* [PATCH v2 2/3] ioremap: Update pgtable free interfaces with addr
From: Toshi Kani @ 2018-05-15 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180515213931.23885-1-toshi.kani@hpe.com>
From: Chintan Pandya <cpandya@codeaurora.org>
This patch ("mm/vmalloc: Add interfaces to free unmapped
page table") adds following 2 interfaces to free the page
table in case we implement huge mapping.
pud_free_pmd_page() and pmd_free_pte_page()
Some architectures (like arm64) needs to do proper TLB
maintanance after updating pagetable entry even in map.
Why ? Read this,
https://patchwork.kernel.org/patch/10134581/
Pass 'addr' in these interfaces so that proper TLB ops
can be performed.
Fixes: 28ee90fe6048 ("x86/mm: implement free pmd/pte page interfaces")
Signed-off-by: Chintan Pandya <cpandya@codeaurora.org>
Signed-off-by: Toshi Kani <toshi.kani@hpe.com>
Cc: <stable@vger.kernel.org>
---
arch/arm64/mm/mmu.c | 4 ++--
arch/x86/mm/pgtable.c | 8 +++++---
include/asm-generic/pgtable.h | 8 ++++----
lib/ioremap.c | 4 ++--
4 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index 2dbb2c9f1ec1..da98828609a1 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -973,12 +973,12 @@ int pmd_clear_huge(pmd_t *pmdp)
return 1;
}
-int pud_free_pmd_page(pud_t *pud)
+int pud_free_pmd_page(pud_t *pud, unsigned long addr)
{
return pud_none(*pud);
}
-int pmd_free_pte_page(pmd_t *pmd)
+int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
{
return pmd_none(*pmd);
}
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 08cdd7c13619..f60fdf411103 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -719,11 +719,12 @@ int pmd_clear_huge(pmd_t *pmd)
/**
* pud_free_pmd_page - Clear pud entry and free pmd page.
* @pud: Pointer to a PUD.
+ * @addr: Virtual address associated with pud.
*
* Context: The pud range has been unmaped and TLB purged.
* Return: 1 if clearing the entry succeeded. 0 otherwise.
*/
-int pud_free_pmd_page(pud_t *pud)
+int pud_free_pmd_page(pud_t *pud, unsigned long addr)
{
pmd_t *pmd;
int i;
@@ -734,7 +735,7 @@ int pud_free_pmd_page(pud_t *pud)
pmd = (pmd_t *)pud_page_vaddr(*pud);
for (i = 0; i < PTRS_PER_PMD; i++)
- if (!pmd_free_pte_page(&pmd[i]))
+ if (!pmd_free_pte_page(&pmd[i], addr + (i * PMD_SIZE)))
return 0;
pud_clear(pud);
@@ -746,11 +747,12 @@ int pud_free_pmd_page(pud_t *pud)
/**
* pmd_free_pte_page - Clear pmd entry and free pte page.
* @pmd: Pointer to a PMD.
+ * @addr: Virtual address associated with pmd.
*
* Context: The pmd range has been unmaped and TLB purged.
* Return: 1 if clearing the entry succeeded. 0 otherwise.
*/
-int pmd_free_pte_page(pmd_t *pmd)
+int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
{
pte_t *pte;
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index f59639afaa39..b081794ba135 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -1019,8 +1019,8 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot);
int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot);
int pud_clear_huge(pud_t *pud);
int pmd_clear_huge(pmd_t *pmd);
-int pud_free_pmd_page(pud_t *pud);
-int pmd_free_pte_page(pmd_t *pmd);
+int pud_free_pmd_page(pud_t *pud, unsigned long addr);
+int pmd_free_pte_page(pmd_t *pmd, unsigned long addr);
#else /* !CONFIG_HAVE_ARCH_HUGE_VMAP */
static inline int p4d_set_huge(p4d_t *p4d, phys_addr_t addr, pgprot_t prot)
{
@@ -1046,11 +1046,11 @@ static inline int pmd_clear_huge(pmd_t *pmd)
{
return 0;
}
-static inline int pud_free_pmd_page(pud_t *pud)
+static inline int pud_free_pmd_page(pud_t *pud, unsigned long addr)
{
return 0;
}
-static inline int pmd_free_pte_page(pmd_t *pmd)
+static inline int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
{
return 0;
}
diff --git a/lib/ioremap.c b/lib/ioremap.c
index 54e5bbaa3200..517f5853ffed 100644
--- a/lib/ioremap.c
+++ b/lib/ioremap.c
@@ -92,7 +92,7 @@ static inline int ioremap_pmd_range(pud_t *pud, unsigned long addr,
if (ioremap_pmd_enabled() &&
((next - addr) == PMD_SIZE) &&
IS_ALIGNED(phys_addr + addr, PMD_SIZE) &&
- pmd_free_pte_page(pmd)) {
+ pmd_free_pte_page(pmd, addr)) {
if (pmd_set_huge(pmd, phys_addr + addr, prot))
continue;
}
@@ -119,7 +119,7 @@ static inline int ioremap_pud_range(p4d_t *p4d, unsigned long addr,
if (ioremap_pud_enabled() &&
((next - addr) == PUD_SIZE) &&
IS_ALIGNED(phys_addr + addr, PUD_SIZE) &&
- pud_free_pmd_page(pud)) {
+ pud_free_pmd_page(pud, addr)) {
if (pud_set_huge(pud, phys_addr + addr, prot))
continue;
}
^ permalink raw reply related
* [PATCH v2 3/3] x86/mm: add TLB purge to free pmd/pte page interfaces
From: Toshi Kani @ 2018-05-15 21:39 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180515213931.23885-1-toshi.kani@hpe.com>
ioremap() calls pud_free_pmd_page() / pmd_free_pte_page() when it creates
a pud / pmd map. The following preconditions are met at their entry.
- All pte entries for a target pud/pmd address range have been cleared.
- System-wide TLB purges have been peformed for a target pud/pmd address
range.
The preconditions assure that there is no stale TLB entry for the range.
Speculation may not cache TLB entries since it requires all levels of page
entries, including ptes, to have P & A-bits set for an associated address.
However, speculation may cache pud/pmd entries (paging-structure caches)
when they have P-bit set.
Add a system-wide TLB purge (INVLPG) to a single page after clearing
pud/pmd entry's P-bit.
SDM 4.10.4.1, Operation that Invalidate TLBs and Paging-Structure Caches,
states that:
INVLPG invalidates all paging-structure caches associated with the
current PCID regardless of the liner addresses to which they correspond.
Fixes: 28ee90fe6048 ("x86/mm: implement free pmd/pte page interfaces")
Signed-off-by: Toshi Kani <toshi.kani@hpe.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Michal Hocko <mhocko@suse.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Joerg Roedel <joro@8bytes.org>
Cc: <stable@vger.kernel.org>
---
arch/x86/mm/pgtable.c | 34 ++++++++++++++++++++++++++++------
1 file changed, 28 insertions(+), 6 deletions(-)
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index f60fdf411103..7e96594c7e97 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -721,24 +721,42 @@ int pmd_clear_huge(pmd_t *pmd)
* @pud: Pointer to a PUD.
* @addr: Virtual address associated with pud.
*
- * Context: The pud range has been unmaped and TLB purged.
+ * Context: The pud range has been unmapped and TLB purged.
* Return: 1 if clearing the entry succeeded. 0 otherwise.
*/
int pud_free_pmd_page(pud_t *pud, unsigned long addr)
{
- pmd_t *pmd;
+ pmd_t *pmd, *pmd_sv;
+ pte_t *pte;
int i;
if (pud_none(*pud))
return 1;
pmd = (pmd_t *)pud_page_vaddr(*pud);
+ pmd_sv = (pmd_t *)__get_free_page(GFP_KERNEL);
+ if (!pmd_sv)
+ return 0;
- for (i = 0; i < PTRS_PER_PMD; i++)
- if (!pmd_free_pte_page(&pmd[i], addr + (i * PMD_SIZE)))
- return 0;
+ for (i = 0; i < PTRS_PER_PMD; i++) {
+ pmd_sv[i] = pmd[i];
+ if (!pmd_none(pmd[i]))
+ pmd_clear(&pmd[i]);
+ }
pud_clear(pud);
+
+ /* INVLPG to clear all paging-structure caches */
+ flush_tlb_kernel_range(addr, addr + PAGE_SIZE-1);
+
+ for (i = 0; i < PTRS_PER_PMD; i++) {
+ if (!pmd_none(pmd_sv[i])) {
+ pte = (pte_t *)pmd_page_vaddr(pmd_sv[i]);
+ free_page((unsigned long)pte);
+ }
+ }
+
+ free_page((unsigned long)pmd_sv);
free_page((unsigned long)pmd);
return 1;
@@ -749,7 +767,7 @@ int pud_free_pmd_page(pud_t *pud, unsigned long addr)
* @pmd: Pointer to a PMD.
* @addr: Virtual address associated with pmd.
*
- * Context: The pmd range has been unmaped and TLB purged.
+ * Context: The pmd range has been unmapped and TLB purged.
* Return: 1 if clearing the entry succeeded. 0 otherwise.
*/
int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
@@ -761,6 +779,10 @@ int pmd_free_pte_page(pmd_t *pmd, unsigned long addr)
pte = (pte_t *)pmd_page_vaddr(*pmd);
pmd_clear(pmd);
+
+ /* INVLPG to clear all paging-structure caches */
+ flush_tlb_kernel_range(addr, addr + PAGE_SIZE-1);
+
free_page((unsigned long)pte);
return 1;
^ permalink raw reply related
* [GIT PULL 4/4] Rockchip arm64 defconfig updates for 4.18 round 1
From: Heiko Stübner @ 2018-05-15 21:41 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180515205354.whll4pj74exaci5h@localhost>
Am Dienstag, 15. Mai 2018, 22:53:54 CEST schrieb Olof Johansson:
> On Tue, May 15, 2018 at 12:40:05PM +0200, Heiko Stuebner wrote:
> > The following changes since commit
60cc43fc888428bb2f18f08997432d426a243338:
> > Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
> >
> > are available in the Git repository at:
> > git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
> > tags/v4.18-rockchip-defconfig64-1>
> > for you to fetch changes up to 214f2c319a140f8a0121f362ad8e73ea1576d5ad:
> > arm64: defconfig: enable rockchip efuse (2018-05-09 16:33:09 +0200)
> >
> > ----------------------------------------------------------------
> > Enablement of Rockchip-specific efuse, io-domain and typec drivers
> > as well as general cros-ec, hid, touchscreen bluetooth and wifi-drivers
> > on 64bit arm platforms.
> >
> > ----------------------------------------------------------------
> >
> > Enric Balletbo i Serra (3):
> > arm64: defconfig: Enable typec-phy and extcon-usbc-cros-ec for
> > rk3399
> > arm64: defconfig: Enable Rockchip io-domain driver
> > arm64: defconfig: Enable ChromeOS EC drivers for supported
> > Chromebooks.
> >
> > Ezequiel Garcia (4):
> > arm64: defconfig: Enable HID over I2C drivers
> > arm64: defconfig: Enable Atmel Maxtouch driver
> > arm64: defconfig: Enable Marvell WiFi-Ex PCIe driver
> > arm64: defconfig: Enable bluetooth USB support
> >
> > Heiko Stuebner (1):
> > arm64: defconfig: enable rockchip efuse
>
> Merged. Not sure if it's useful to split defconfig updates quite this
> granular, might make sense to just do slightly more consolidated patches.
>
> Anyway, no harm, just a bit verbose.
ok, I'll check if things can be merged more, the next time :-)
Heiko
^ permalink raw reply
* [PATCH v9 05/12] ACPI/PPTT: Add Processor Properties Topology Table parsing
From: Jeremy Linton @ 2018-05-15 21:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJZ5v0h4OeTaG2h0Q1c8zX93tici_nfLftpEyKWSkXoztHuUDg@mail.gmail.com>
Hi,
On 05/12/2018 05:09 AM, Rafael J. Wysocki wrote:
> On Sat, May 12, 2018 at 1:58 AM, Jeremy Linton <jeremy.linton@arm.com> wrote:
>> ACPI 6.2 adds a new table, which describes how processing units
>> are related to each other in tree like fashion. Caches are
>> also sprinkled throughout the tree and describe the properties
>> of the caches in relation to other caches and processing units.
>>
>> Add the code to parse the cache hierarchy and report the total
>> number of levels of cache for a given core using
>> acpi_find_last_cache_level() as well as fill out the individual
>> cores cache information with cache_setup_acpi() once the
>> cpu_cacheinfo structure has been populated by the arch specific
>> code.
>>
>> An additional patch later in the set adds the ability to report
>> peers in the topology using find_acpi_cpu_topology()
>> to report a unique ID for each processing unit at a given level
>> in the tree. These unique id's can then be used to match related
>> processing units which exist as threads, within a given
>> package, etc.
>>
>> Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
>> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> Tested-by: Vijaya Kumar K <vkilari@codeaurora.org>
>> Tested-by: Xiongfeng Wang <wangxiongfeng2@huawei.com>
>> Tested-by: Tomasz Nowicki <Tomasz.Nowicki@cavium.com>
>> Acked-by: Sudeep Holla <sudeep.holla@arm.com>
>> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
>> ---
>> drivers/acpi/pptt.c | 655 +++++++++++++++++++++++++++++++++++++++++++++++++++
>> include/linux/acpi.h | 4 +
>> 2 files changed, 659 insertions(+)
>> create mode 100644 drivers/acpi/pptt.c
>>
>> diff --git a/drivers/acpi/pptt.c b/drivers/acpi/pptt.c
>> new file mode 100644
>> index 000000000000..e5ea1974d1e3
>> --- /dev/null
>> +++ b/drivers/acpi/pptt.c
>> @@ -0,0 +1,655 @@
>> +// SPDX-License-Identifier: GPL-2.0
>> +/*
>> + * pptt.c - parsing of Processor Properties Topology Table (PPTT)
>> + *
>> + * Copyright (C) 2018, ARM
>> + *
>> + * This file implements parsing of the Processor Properties Topology Table
>> + * which is optionally used to describe the processor and cache topology.
>> + * Due to the relative pointers used throughout the table, this doesn't
>> + * leverage the existing subtable parsing in the kernel.
>> + *
>> + * The PPTT structure is an inverted tree, with each node potentially
>> + * holding one or two inverted tree data structures describing
>> + * the caches available at that level. Each cache structure optionally
>> + * contains properties describing the cache at a given level which can be
>> + * used to override hardware probed values.
>> + */
>> +#define pr_fmt(fmt) "ACPI PPTT: " fmt
>> +
>> +#include <linux/acpi.h>
>> +#include <linux/cacheinfo.h>
>> +#include <acpi/processor.h>
>> +
>> +static struct acpi_subtable_header *fetch_pptt_subtable(struct acpi_table_header *table_hdr,
>> + u32 pptt_ref)
>> +{
>> + struct acpi_subtable_header *entry;
>> +
>> + /* there isn't a subtable at reference 0 */
>> + if (pptt_ref < sizeof(struct acpi_subtable_header))
>> + return NULL;
>> +
>> + if (pptt_ref + sizeof(struct acpi_subtable_header) > table_hdr->length)
>> + return NULL;
>> +
>> + entry = ACPI_ADD_PTR(struct acpi_subtable_header, table_hdr, pptt_ref);
>> +
>> + if (entry->length == 0)
>> + return NULL;
>> +
>> + if (pptt_ref + entry->length > table_hdr->length)
>> + return NULL;
>> +
>> + return entry;
>> +}
>> +
>> +static struct acpi_pptt_processor *fetch_pptt_node(struct acpi_table_header *table_hdr,
>> + u32 pptt_ref)
>> +{
>> + return (struct acpi_pptt_processor *)fetch_pptt_subtable(table_hdr, pptt_ref);
>> +}
>> +
>> +static struct acpi_pptt_cache *fetch_pptt_cache(struct acpi_table_header *table_hdr,
>> + u32 pptt_ref)
>> +{
>> + return (struct acpi_pptt_cache *)fetch_pptt_subtable(table_hdr, pptt_ref);
>
> I don't think you really need the explicit type cast here and above,
> but that's very minor.
>
>> +}
>
> Please feel free to add
>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
>
> to the patch and route it through the arch tree as needed.
Thanks for looking at this (and the ack of course)!
As an FYI, the in my build without the type cast, the
-Werror=incompatible-pointer-types (sourced from the root Makefile)
triggers an error.
thanks again.
^ permalink raw reply
* [PATCH v2] clk: aspeed: Support second reset register
From: Stephen Boyd @ 2018-05-15 22:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180427025547.14115-1-joel@jms.id.au>
Quoting Joel Stanley (2018-04-26 19:55:47)
> The ast2500 has an additional reset register that contains resets not
> present in the ast2400. This enables support for this register, and adds
> the one reset line that is controlled by it.
>
> Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
> Signed-off-by: Joel Stanley <joel@jms.id.au>
> ---
Applied to clk-next
^ permalink raw reply
* [PATCH] clk:aspeed: Fix reset bits for PCI/VGA and PECI
From: Stephen Boyd @ 2018-05-15 22:02 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <5a449d93-eef0-4243-9889-bd13786edde1@linux.intel.com>
Quoting Jae Hyun Yoo (2018-05-01 09:27:32)
> On 5/1/2018 8:02 AM, Rob Herring wrote:
> > On Thu, Apr 26, 2018 at 10:22:32AM -0700, Jae Hyun Yoo wrote:
> >> diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
> >> index d3558d897a4d..8d69b9134bef 100644
> >> --- a/include/dt-bindings/clock/aspeed-clock.h
> >> +++ b/include/dt-bindings/clock/aspeed-clock.h
> >> @@ -45,7 +45,7 @@
> >> #define ASPEED_RESET_JTAG_MASTER 3
> >> #define ASPEED_RESET_MIC 4
> >> #define ASPEED_RESET_PWM 5
> >> -#define ASPEED_RESET_PCIVGA 6
> >> +#define ASPEED_RESET_PECI 6
> >
> > You can't really be changing these as they represent an ABI.
> >
> > Is there no PCIVGA reset?
> >
>
> This is a bug fixing. Previously, PCI/VGA used PECI reset bit so this
> patch corrects the reset bit for PCI/VGA from bit '10' to bit '8', and
> it adds PECI reset bit '10' here as it can't be combined with a clock
> gate bit.
>
Presumably nobody is using the #define because it's wrong, so this is OK
for me. I'll apply to clk-next and yank it if Rob objects.
^ permalink raw reply
* [PATCH] clk: hisilicon: add missing usb3 clocks for Hi3798CV200 SoC
From: Stephen Boyd @ 2018-05-15 22:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525424190-15619-1-git-send-email-sunjg79@163.com>
Quoting sunjg79 at 163.com (2018-05-04 01:56:30)
> From: Jianguo Sun <sunjianguo1@huawei.com>
>
> There are two USB3 host controllers on Hi3798CV200 SoC.
> This commit adds missing clocks for them.
>
> Signed-off-by: Jianguo Sun <sunjianguo1@huawei.com>
> ---
Applied to clk-next
^ permalink raw reply
* [PATCH v1 1/1] clk: npcm750: fix base address and of_clk_get_by_name error handling. Also update error messages to be more informative
From: Stephen Boyd @ 2018-05-15 22:15 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525159407-31708-2-git-send-email-tali.perry1@gmail.com>
Quoting Tali Perry (2018-05-01 00:23:27)
>
> Nuvoton NPCM7XX Clock Controller
> fix base address and of_clk_get_by_name error handling.
> Also update error messages to be more informative.
>
> In case clk_base allocation is erronoeous the return value is null.
> Also fix handling of of_clk_get_by_name returns an error.
> Print a better error message pointing to the dt-binding documention.
>
>
> Signed-off-by: Tali Perry <tali.perry1@gmail.com>
> Reviewed-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
>
> Tali Perry (2):
>
This doesn't apply to clk-next so I'm not sure what's going on. Please
resend if something needs to be fixed.
^ permalink raw reply
* [PATCH v1] clk: mediatek: correct the clocks for MT2701 HDMI PHY module
From: Stephen Boyd @ 2018-05-15 22:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <dc75b5b289d1f6e4914e60543c2611f387f0c164.1523944160.git.ryder.lee@mediatek.com>
Quoting Ryder Lee (2018-04-17 05:30:27)
> The hdmitx_dig_cts clock signal is not a child of clk26m,
> and the actual output of the PLL block is derived from
> the tvdpll via a configurable PLL post-divider.
>
> It is used as the PLL reference input to the HDMI PHY module.
>
> Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
> Signed-off-by: Chunhui Dai <chunhui.dai@mediatek.com>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> ---
Applied to clk-next
^ permalink raw reply
* [PATCH v3 4/4] KVM: arm64: Add support for PUD hugepages at stage 2
From: Suzuki K Poulose @ 2018-05-15 22:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180514144304.10484-5-punit.agrawal@arm.com>
On 05/14/2018 03:43 PM, Punit Agrawal wrote:
> KVM only supports PMD hugepages at stage 2. Extend the stage 2 fault
> handling to add support for PUD hugepages.
>
> Addition of pud hugepage support enables additional hugepage
> sizes (e.g., 1G with 4K granule) which can be useful on cores that
> support mapping larger block sizes in the TLB entries.
>
> Signed-off-by: Punit Agrawal <punit.agrawal@arm.com>
> Reviewed-by: Christoffer Dall <christoffer.dall@arm.com>
> Cc: Marc Zyngier <marc.zyngier@arm.com>
> Cc: Russell King <linux@armlinux.org.uk>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will.deacon@arm.com>
> ---
> arch/arm/include/asm/kvm_mmu.h | 19 ++++++++++++
> arch/arm64/include/asm/kvm_mmu.h | 15 ++++++++++
> arch/arm64/include/asm/pgtable-hwdef.h | 4 +++
> arch/arm64/include/asm/pgtable.h | 2 ++
> virt/kvm/arm/mmu.c | 40 ++++++++++++++++++++++++--
> 5 files changed, 77 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/include/asm/kvm_mmu.h b/arch/arm/include/asm/kvm_mmu.h
> index 224c22c0a69c..155916dbdd7e 100644
> --- a/arch/arm/include/asm/kvm_mmu.h
> +++ b/arch/arm/include/asm/kvm_mmu.h
> @@ -77,8 +77,11 @@ void kvm_clear_hyp_idmap(void);
>
> #define kvm_pfn_pte(pfn, prot) pfn_pte(pfn, prot)
> #define kvm_pfn_pmd(pfn, prot) pfn_pmd(pfn, prot)
> +#define kvm_pfn_pud(pfn, prot) (__pud(0))
>
> #define kvm_pmd_mkhuge(pmd) pmd_mkhuge(pmd)
> +/* No support for pud hugepages */
> +#define kvm_pud_mkhuge(pud) (pud)
>
> /*
> * The following kvm_*pud*() functionas are provided strictly to allow
> @@ -95,6 +98,22 @@ static inline bool kvm_s2pud_readonly(pud_t *pud)
> return false;
> }
>
> +static inline void kvm_set_pud(pud_t *pud, pud_t new_pud)
> +{
> + BUG();
> +}
> +
> +static inline pud_t kvm_s2pud_mkwrite(pud_t pud)
> +{
> + BUG();
> + return pud;
> +}
> +
> +static inline pud_t kvm_s2pud_mkexec(pud_t pud)
> +{
> + BUG();
> + return pud;
> +}
>
> static inline void kvm_set_pmd(pmd_t *pmd, pmd_t new_pmd)
> {
> diff --git a/arch/arm64/include/asm/kvm_mmu.h b/arch/arm64/include/asm/kvm_mmu.h
> index f440cf216a23..f49a68fcbf26 100644
> --- a/arch/arm64/include/asm/kvm_mmu.h
> +++ b/arch/arm64/include/asm/kvm_mmu.h
> @@ -172,11 +172,14 @@ void kvm_clear_hyp_idmap(void);
>
> #define kvm_set_pte(ptep, pte) set_pte(ptep, pte)
> #define kvm_set_pmd(pmdp, pmd) set_pmd(pmdp, pmd)
> +#define kvm_set_pud(pudp, pud) set_pud(pudp, pud)
>
> #define kvm_pfn_pte(pfn, prot) pfn_pte(pfn, prot)
> #define kvm_pfn_pmd(pfn, prot) pfn_pmd(pfn, prot)
> +#define kvm_pfn_pud(pfn, prot) pfn_pud(pfn, prot)
>
> #define kvm_pmd_mkhuge(pmd) pmd_mkhuge(pmd)
> +#define kvm_pud_mkhuge(pud) pud_mkhuge(pud)
>
> static inline pte_t kvm_s2pte_mkwrite(pte_t pte)
> {
> @@ -190,6 +193,12 @@ static inline pmd_t kvm_s2pmd_mkwrite(pmd_t pmd)
> return pmd;
> }
>
> +static inline pud_t kvm_s2pud_mkwrite(pud_t pud)
> +{
> + pud_val(pud) |= PUD_S2_RDWR;
> + return pud;
> +}
> +
> static inline pte_t kvm_s2pte_mkexec(pte_t pte)
> {
> pte_val(pte) &= ~PTE_S2_XN;
> @@ -202,6 +211,12 @@ static inline pmd_t kvm_s2pmd_mkexec(pmd_t pmd)
> return pmd;
> }
>
> +static inline pud_t kvm_s2pud_mkexec(pud_t pud)
> +{
> + pud_val(pud) &= ~PUD_S2_XN;
> + return pud;
> +}
> +
> static inline void kvm_set_s2pte_readonly(pte_t *ptep)
> {
> pteval_t old_pteval, pteval;
> diff --git a/arch/arm64/include/asm/pgtable-hwdef.h b/arch/arm64/include/asm/pgtable-hwdef.h
> index fd208eac9f2a..e327665e94d1 100644
> --- a/arch/arm64/include/asm/pgtable-hwdef.h
> +++ b/arch/arm64/include/asm/pgtable-hwdef.h
> @@ -193,6 +193,10 @@
> #define PMD_S2_RDWR (_AT(pmdval_t, 3) << 6) /* HAP[2:1] */
> #define PMD_S2_XN (_AT(pmdval_t, 2) << 53) /* XN[1:0] */
>
> +#define PUD_S2_RDONLY (_AT(pudval_t, 1) << 6) /* HAP[2:1] */
> +#define PUD_S2_RDWR (_AT(pudval_t, 3) << 6) /* HAP[2:1] */
> +#define PUD_S2_XN (_AT(pudval_t, 2) << 53) /* XN[1:0] */
> +
> /*
> * Memory Attribute override for Stage-2 (MemAttr[3:0])
> */
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 7c4c8f318ba9..31ea9fda07e3 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -386,6 +386,8 @@ static inline int pmd_protnone(pmd_t pmd)
>
> #define pud_write(pud) pte_write(pud_pte(pud))
>
> +#define pud_mkhuge(pud) (__pud(pud_val(pud) & ~PUD_TABLE_BIT))
> +
> #define __pud_to_phys(pud) __pte_to_phys(pud_pte(pud))
> #define __phys_to_pud_val(phys) __phys_to_pte_val(phys)
> #define pud_pfn(pud) ((__pud_to_phys(pud) & PUD_MASK) >> PAGE_SHIFT)
> diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
> index 671d3c0825f2..b0931fa2d64e 100644
> --- a/virt/kvm/arm/mmu.c
> +++ b/virt/kvm/arm/mmu.c
> @@ -1036,6 +1036,26 @@ static int stage2_set_pmd_huge(struct kvm *kvm, struct kvm_mmu_memory_cache
> return 0;
> }
>
> +static int stage2_set_pud_huge(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
> + phys_addr_t addr, const pud_t *new_pud)
> +{
> + pud_t *pud, old_pud;
> +
> + pud = stage2_get_pud(kvm, cache, addr);
> + VM_BUG_ON(!pud);
> +
> + old_pud = *pud;
> + if (pud_present(old_pud)) {
> + pud_clear(pud);
> + kvm_tlb_flush_vmid_ipa(kvm, addr);
> + } else {
> + get_page(virt_to_page(pud));
> + }
> +
> + kvm_set_pud(pud, *new_pud);
> + return 0;
> +}
> +
> static bool stage2_is_exec(struct kvm *kvm, phys_addr_t addr)
> {
> pmd_t *pmdp;
> @@ -1467,9 +1487,12 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
> }
>
> vma_pagesize = vma_kernel_pagesize(vma);
> - if (vma_pagesize == PMD_SIZE && !logging_active) {
> + if ((vma_pagesize == PMD_SIZE || vma_pagesize == PUD_SIZE) &&
> + !logging_active) {
> + struct hstate *h = hstate_vma(vma);
> +
> hugetlb = true;
> - gfn = (fault_ipa & PMD_MASK) >> PAGE_SHIFT;
> + gfn = (fault_ipa & huge_page_mask(h)) >> PAGE_SHIFT;
> } else {
> /*
> * Pages belonging to memslots that don't have the same
> @@ -1555,7 +1578,18 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
> if (exec_fault)
> invalidate_icache_guest_page(pfn, vma_pagesize);
>
> - if (vma_pagesize == PMD_SIZE) {
> + if (vma_pagesize == PUD_SIZE) {
> + pud_t new_pud = kvm_pfn_pud(pfn, mem_type);
> +
> + new_pud = kvm_pud_mkhuge(new_pud);
> + if (writable)
> + new_pud = kvm_s2pud_mkwrite(new_pud);
> +
> + if (stage2_should_exec(kvm, fault_ipa, exec_fault, fault_status))
> + new_pud = kvm_s2pud_mkexec(new_pud);
> +
> + ret = stage2_set_pud_huge(kvm, memcache, fault_ipa, &new_pud);
> + } else if (vma_pagesize == PMD_SIZE) {
> pmd_t new_pmd = kvm_pfn_pmd(pfn, mem_type);
>
> new_pmd = kvm_pmd_mkhuge(new_pmd);
>
Punit,
Sorry for the late notice. I was looking deeply in to the stage2 table
code to rework the same for dynamic IPA and thus found this.
I am wondering if these changes are sufficient enough to add the PUD
hugepage support. There are lots places where we simply get the
stage2_pmd of a given address and then go about doing something at the
PMD level or drill down to PTE if the PMD is not huge. (e.g
stage2_is_exec, handle_access_fault etc). We simply do a pmd_offset()
on a PUD entry, without even checking if the PUD is huge or not.
With the PUD huge support, I think we need to go a level up in all these
cases and drill down from PUD level, down to the PMD level and then
further down, depending on whether we have huge page support at either
of these levels.
Cheers
Suzuki
^ permalink raw reply
* [PATCH v2 2/6] dt-bindings: clock: mediatek: add g3dsys bindings
From: Stephen Boyd @ 2018-05-15 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <665c38d5803573aa9a01471253f406301b1123a1.1524816502.git.sean.wang@mediatek.com>
Quoting sean.wang at mediatek.com (2018-04-27 01:14:43)
> From: Sean Wang <sean.wang@mediatek.com>
>
> Add bindings to g3dsys providing necessary clock and reset control to
> Mali-450.
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
Applied to clk-next
^ permalink raw reply
* [PATCH v2 3/6] dt-bindings: clock: mediatek: add entry for Mali-450 node to refer
From: Stephen Boyd @ 2018-05-15 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <082c3040e2be27d30e0642943f6df35ff4de5666.1524816502.git.sean.wang@mediatek.com>
Quoting sean.wang at mediatek.com (2018-04-27 01:14:44)
> From: Sean Wang <sean.wang@mediatek.com>
>
> Just add binding for a required clock referenced by Mali-450 on MT7623
> or MT2701 SoC.
>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
Applied to clk-next
^ permalink raw reply
* [PATCH v2 4/6] dt-bindings: reset: mediatek: add entry for Mali-450 node to refer
From: Stephen Boyd @ 2018-05-15 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d9f327fa30c987ac9cf3a349551bbaa037d1b24a.1524816502.git.sean.wang@mediatek.com>
Quoting sean.wang at mediatek.com (2018-04-27 01:14:45)
> From: Sean Wang <sean.wang@mediatek.com>
>
> Just add binding for a required reset referenced by Mali-450 on MT7623
> or MT2701 SoC.
>
> Cc: devicetree at vger.kernel.org
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
Applied to clk-next
^ permalink raw reply
* [PATCH v2 5/6] clk: mediatek: add g3dsys support for MT2701 and MT7623
From: Stephen Boyd @ 2018-05-15 22:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <caf1cbbd0758cbb9c25c081f4d8fdb9f64769a44.1524816502.git.sean.wang@mediatek.com>
Quoting sean.wang at mediatek.com (2018-04-27 01:14:46)
> From: Sean Wang <sean.wang@mediatek.com>
>
> Add clock driver support for g3dsys on MT2701 and MT7623, which is
> providing essential clock gate and reset controller to Mali-450.
>
> Signed-off-by: Sean Wang <sean.wang@mediatek.com>
> ---
Applied to clk-next
^ permalink raw reply
* [PATCHv3] arm64: dts: stratix10: Add QSPI support for Stratix10
From: thor.thayer at linux.intel.com @ 2018-05-15 22:26 UTC (permalink / raw)
To: linux-arm-kernel
From: Thor Thayer <thor.thayer@linux.intel.com>
Add qspi_clock
The qspi_clk frequency is updated by U-Boot before starting Linux.
Add QSPI interface node.
Add QSPI flash memory child node.
Setup the QSPI memory in 2 partitions.
Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
---
v2 s/_/-/ in qspi-clk
rename flash node.
use partition child node notation
v3 remove unused bus-num node
use device id from table (n25q00a)
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 21 +++++++++++++
.../boot/dts/altera/socfpga_stratix10_socdk.dts | 35 ++++++++++++++++++++++
2 files changed, 56 insertions(+)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index e6b059378dc0..d8c94d5ff4b4 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -119,6 +119,12 @@
#clock-cells = <0>;
compatible = "fixed-clock";
};
+
+ qspi_clk: qspi-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
};
gmac0: ethernet at ff800000 {
@@ -466,5 +472,20 @@
interrupts = <16 4>, <48 4>;
};
};
+
+ qspi: spi at ff8d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0xff8d2000 0x100>,
+ <0xff900000 0x100000>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+
+ status = "disabled";
+ };
};
};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index f9b1ef12db48..6edc4fa9fd42 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -147,3 +147,38 @@
reg = <0x68>;
};
};
+
+&qspi {
+ flash at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q00a";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition at 0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x4000000>;
+ };
+
+ qspi_rootfs: partition at 4000000 {
+ label = "Root Filesystem - JFFS2";
+ reg = <0x4000000 0x4000000>;
+ };
+ };
+ };
+};
--
2.7.4
^ permalink raw reply related
* [GIT PULL] Amlogic 32-bit DT updates for v4.18
From: Kevin Hilman @ 2018-05-15 22:29 UTC (permalink / raw)
To: linux-arm-kernel
Hi Arnd, Olof,
This is mostly DT, but contains also contains the mach-meson change to
build the new DT, which might be more appropriate for the 'soc' branch,
but I left it here because it's just about enabling the new DT. Let me
know if you prefer it split out.
Kevin
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-dt
for you to fetch changes up to 35ee52bea66c74a7c33cebda8692d61b1ed7c6e9:
ARM: dts: meson8m2: add support for the Tronsmart MXIII Plus (2018-05-10 17:03:28 -0700)
----------------------------------------------------------------
Amlogic 32-bit DT updates for v4.18
- add support for meson8m2 SoC
- new board: Tronsmart MXIII Plus using meson8m2 SoC
- odroid-c1: add IR
----------------------------------------------------------------
Martin Blumenstingl (7):
ARM: dts: meson8: add the cortex-a9-pmu compatible PMU
ARM: dts: meson8b: add the cortex-a5-pmu compatible PMU
ARM: dts: meson8b: odroid-c1: sort nodes alphabetically
ARM: dts: meson8b: odroid-c1: enable the IR receiver
ARM: meson: add support for the Meson8m2 SoCs
ARM: dts: meson: add support for the Meson8m2 SoC
ARM: dts: meson8: add the uart_A pins
Oleg Ivanov (1):
ARM: dts: meson8m2: add support for the Tronsmart MXIII Plus
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/meson8.dtsi | 33 +++++++++++--
arch/arm/boot/dts/meson8b-odroidc1.dts | 68 ++++++++++++++------------
arch/arm/boot/dts/meson8b.dtsi | 24 +++++++--
arch/arm/boot/dts/meson8m2-mxiii-plus.dts | 244 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/meson8m2.dtsi | 54 ++++++++++++++++++++
arch/arm/mach-meson/Kconfig | 2 +-
arch/arm/mach-meson/meson.c | 1 +
8 files changed, 388 insertions(+), 41 deletions(-)
create mode 100644 arch/arm/boot/dts/meson8m2-mxiii-plus.dts
create mode 100644 arch/arm/boot/dts/meson8m2.dtsi
^ permalink raw reply
* [GIT PULL] Amlogic 64-bit DT updates for v4.18
From: Kevin Hilman @ 2018-05-15 22:33 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-dt64
for you to fetch changes up to c51fb2d458a6d62215c1ff6bbca8e5c876370e71:
dt-bindings: arm: amlogic: add support for the Tronsmart MXIII Plus (2018-05-09 15:25:20 -0700)
----------------------------------------------------------------
Amlogic 64-bit DT updates for v4.18
- AXG family: support more peripherals (wifi, eMMC, clocks)
- GX family: add/enable USB host support
----------------------------------------------------------------
Jerome Brunet (6):
dt-bindings: clock: meson: update documentation with hhi syscon
ARM64: dts: meson-gx: sysctrl is the parent of the clock controller
ARM64: dts: meson-axg: use hhi syscon for the clock controller
ARM64: dts: meson-gx: fix gxl clock controller compatible
ARM64: dts: meson-axg: add tdm pins
ARM64: dts: meson: add MMC resets
Martin Blumenstingl (9):
ARM64: dts: meson-gxl: add USB host support
ARM64: dts: meson-gxm: add GXM specific USB host configuration
ARM64: dts: meson-gxl-s905x-p212: enable the USB controller
ARM64: dts: meson-gx-p23x-q20x: enable the USB controller
ARM64: dts: meson-gxl-s905x-libretech-cc: enable the USB controller
ARM64: dts: meson-gxl-nexbox-a95x: enable the USB controller
ARM64: dts: meson-gxm-khadas-vim2: enable the USB controller
dt-bindings: arm: amlogic: add support for the Meson8m2 SoC
dt-bindings: arm: amlogic: add support for the Tronsmart MXIII Plus
Nan Li (1):
ARM64: dts: meson-axg: enable the eMMC controller
Yixun Lan (3):
ARM64: dts: meson-axg: add GPIO interrupt controller support
ARM64: dts: meson-axg: add an 32K alt aoclk
ARM64: dts: meson-axg: enable AP6255 wifi module
Documentation/devicetree/bindings/arm/amlogic.txt | 6 ++
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt | 16 +++-
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 100 ++++++++++++++++++++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 358 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi | 4 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 +-
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 12 +++
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-nexbox-a95x.dts | 4 +
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-p212.dtsi | 4 +
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 73 ++++++++++++++-
arch/arm64/boot/dts/amlogic/meson-gxm-khadas-vim2.dts | 4 +
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 17 ++++
12 files changed, 589 insertions(+), 17 deletions(-)
^ permalink raw reply
* [PATCH] clk: davinci: psc-da830: fix USB0 48MHz PHY clock registration
From: Stephen Boyd @ 2018-05-15 22:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507113457.4716-1-nsekhar@ti.com>
Quoting Sekhar Nori (2018-05-07 04:34:57)
> USB0 48MHz PHY clock registration fails on DA830 because the
> da8xx-cfgchip clock driver cannot get a reference to USB0
> LPSC clock.
>
> The USB0 LPSC needs to be enabled during PHY clock enable. Setup
> the clock lookup correctly to fix this.
>
> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
> ---
Applied to clk-next
Did this need a fixes tag? And should it go into 4.17 final? Or it's not
causing problems right now?
^ permalink raw reply
* [GIT PULL] Amlogic defconfig updates for v4.18
From: Kevin Hilman @ 2018-05-15 22:35 UTC (permalink / raw)
To: linux-arm-kernel
The following changes since commit 60cc43fc888428bb2f18f08997432d426a243338:
Linux 4.17-rc1 (2018-04-15 18:24:20 -0700)
are available in the git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic.git tags/amlogic-defconfig
for you to fetch changes up to 1e3e7a9f27dc73c50ad7b0f06e6e519bbaa3fee9:
ARM: multi_v7_defconfig: enable the Meson PWM controller (2018-04-27 12:06:02 -0700)
----------------------------------------------------------------
Amlogic: defconfig updates for v4.18
- multi_v7_defconfig: enable meson PWM, I2C drivers
----------------------------------------------------------------
Martin Blumenstingl (2):
arm: multi_v7_defconfig: enable the Amlogic Meson I2C driver
ARM: multi_v7_defconfig: enable the Meson PWM controller
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
^ permalink raw reply
* Re: [PATCH v10 00/27] ARM: davinci: convert to common clock framework
From: Adam Ford @ 2018-05-15 22:44 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAMRc=MdO0EtzDHp3RF4ym3umWM_KfhvpWHV2+Y3270ygKz9iGw@mail.gmail.com>
On Tue, May 15, 2018 at 4:25 AM, Bartosz Golaszewski <brgl@bgdev.pl> wrote:
> 2018-05-14 2:40 GMT+02:00 Adam Ford <aford173@gmail.com>:
>> On Wed, May 9, 2018 at 12:25 PM, David Lechner <david@lechnology.com> wrote:
>>> This series converts mach-davinci to use the common clock framework.
>>>
>>> The series works like this, the first 3 patches fix some issues with the clock
>>> drivers that have already been accepted into the mainline kernel.
>>>
>>> Then, starting with "ARM: davinci: pass clock as parameter to
>>> davinci_timer_init()", we get the mach code ready for the switch by adding the
>>> code needed for the new clock drivers and adding #ifndef CONFIG_COMMON_CLK
>>> around the legacy clocks so that we can switch easily between the old and the
>>> new.
>>>
>>> "ARM: davinci: switch to common clock framework" actually flips the switch
>>> to start using the new clock drivers. Then the next 8 patches remove all
>>> of the old clock code.
>>>
>>> The final four patches add device tree clock support to the one SoC that
>>> supports it.
>>>
>>> This series has been tested on TI OMAP-L138 LCDK (both device tree and legacy
>>> board file).
>>>
>>
>> I am not sure if I did something wrong, but I attempted to build and I
>> wasn't able to boot the da850-evm.dtb your repo common-clk-v11,
>> however the legacy board file boot was OK.
>>
>> make davinci_all_defconfig ARCH=arm
>> make zImage modules da850-evm.dtb ARCH=arm CROSS_COMPILE=arm-linux- -j8
>>
>> 3140416 bytes read in 1464 ms (2 MiB/s)
>> 20353 bytes read in 15 ms (1.3 MiB/s)
>> ## Flattened Device Tree blob at c0600000
>> Booting using the fdt blob at 0xc0600000
>> Loading Device Tree to c7e57000, end c7e5ef80 ... OK
>>
>> Starting kernel ...
>>
>> Uncompressing Linux... done, booting the kernel.
>>
>> (and hang)
>>
>> If you have some suggestions, I am try them as I get time.
>>
>> adam
>>
>
> Runs fine on da850-lcdk and dm365-evm. I'll test the da850-evm
> tomorrow when I'll have access to it.
I set the bootargs to: bootargs=console=ttyS2,115200n8
clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
I enabled DEBUG_LL and EARLY_PRINTK, yet when it loads, I only get:
## Flattened Device Tree blob at c0600000
Booting using the fdt blob at 0xc0600000
Loading Device Tree to c7e57000, end c7e5ef35 ... OK
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
I am doing this at my home, so I don't have a debugger for the
DA850-EVM. I am using a SOM that is an AM1808, but I vaguely remember
something about enabling a DSP clock somewhere, but I cannot seem to
find the e-mail. I know its counter intuitive that we'd need to
enable a clock that runs the DSP since it doesn't exist on the AM1808,
but I would have thought the clk_ignore_unused would have worked
around that issue.
If someone else has a DA850-EVM or suggestions, I'm willing to try
them as I have time.
adam
>
> Bart
^ permalink raw reply
* [PATCH 2/4] ARM: davinci: board-da850-evm: fix GPIO lookup for MMC/SD
From: Adam Ford @ 2018-05-15 22:53 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <fa8feb04-2231-88b8-4d2b-10264187ba7e@lechnology.com>
On Thu, Apr 26, 2018 at 8:40 PM, David Lechner <david@lechnology.com> wrote:
> On 04/24/2018 09:35 AM, Sekhar Nori wrote:
>>
>> The GPIO chip is called davinci_gpio.0 in legacy mode. Fix it, so that
>> mmc can correctly lookup the wp and cp gpios. Also fix the GPIO numbers
>> as they are not offsets within a bank.
>>
>> Note that it is the gpio-davinci driver that sets the gpiochip label to
>> davinci_gpio.0.
>>
>> Fixes: bdf0e8364fd3 ("ARM: davinci: da850-evm: use gpio descriptor for mmc
>> pins")
>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>> ---
>> arch/arm/mach-davinci/board-da850-evm.c | 9 +++++++--
>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm/mach-davinci/board-da850-evm.c
>> b/arch/arm/mach-davinci/board-da850-evm.c
>> index 3063478bcc36..158ed9a1483f 100644
>> --- a/arch/arm/mach-davinci/board-da850-evm.c
>> +++ b/arch/arm/mach-davinci/board-da850-evm.c
>> @@ -763,12 +763,17 @@ static const short da850_evm_mcasp_pins[]
>> __initconst = {
>> -1
>> };
>> +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
>> +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
>> +
>> static struct gpiod_lookup_table mmc_gpios_table = {
>> .dev_id = "da830-mmc.0",
>> .table = {
>> /* gpio chip 2 contains gpio range 64-95 */
>> - GPIO_LOOKUP("davinci_gpio.2", 0, "cd", GPIO_ACTIVE_LOW),
>> - GPIO_LOOKUP("davinci_gpio.2", 1, "wp", GPIO_ACTIVE_LOW),
>> + GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
>> + GPIO_ACTIVE_LOW),
>> + GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
>> + GPIO_ACTIVE_LOW),
I don't think the WP polarity is working correctly. If I boot the
board 'rw' enabled but WP disabled on the SD card, the system crashes.
If I enable WP, the board boots correctly.
Comparing this to the device tree version that I did, and double
checking the behavior for my sanity, I believe WP needs to be
GPIO_ACTIVE_HIGH
adam
>> },
>> };
>>
>
>
> Reviewed-by: David Lechner <david@lechnology.com>
>
^ permalink raw reply
* [GIT PULL] arm64: defconfig: hisilicon config updates for v4.18
From: Daniel Lezcano @ 2018-05-15 23:00 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180515203755.esjnphfep5ep7wbe@localhost>
On Tue, May 15, 2018 at 01:37:55PM -0700, Olof Johansson wrote:
> On Tue, May 15, 2018 at 10:28:11AM +0200, Daniel Lezcano wrote:
> > On Mon, May 14, 2018 at 01:14:45PM -0700, Olof Johansson wrote:
> > > Hi Wei,
> > >
> > > On Fri, May 11, 2018 at 03:31:38PM +0100, Wei Xu wrote:
> > > > Hi Arnd, Hi Olof,
> > > >
> > > > Please help to pull the following changes.
> > > >
> > > > About the CLOCK_STUB and the MAILBOX consolidate patch,
> > > > Jassi and Stephen have acked it.
> > > > Could you let me know how to handle this kind case
> > > > if it is not OK to be in this pull?
> > >
> > > I don't think there's any need to group the Kconfig changes with the defconfig
> > > updates here, is there?
> >
> > I don't have the patches history, but likely this patch should come together with:
> >
> > https://patchwork.kernel.org/patch/10399799/
> > https://patchwork.kernel.org/patch/10399801/
> >
> > Otherwise the compilation options won't be consistent with what is enabled in
> > the DT.
>
> As long as neither side regresses due to the changes, there should be no
> problem. Just because a DT node is added in the tree there's no need to
> configure the driver. Or am I missing some aspect of it here?
Actually, the DT node being added do not introduce regressions.
However it is expected by adding the clock stub and the mailbox to have the
cpufreq working which is not necessarily the case because the config may be
inconsistent, so the cpufreq may be working on some config if the user had the
options for the clock and the mailbox enabled but these options can disappear
and not come back because of this Kconfig inconsistencies.
>From my point of view, by adding those DT nodes, it makes sense to give a
consolidated Kconfig coming together and ensuring the drivers are enabled when
the node is parsed.
On the other side, the patch is simple enough to be split and submitted in
separated trees, hoping the maintainer Wu Xei and the branch users keep in mind
if the board does not boot or has inconsistent behavior they will have to
double check the options are enabled for the clock stub and the mailbox.
I don't have a strong opinion on this actually, whatever the decision is, I
will be fine with resubmitting the patch to the different trees, or keep it as
is and merge it through the hisi tree.
-- Daniel
--
<http://www.linaro.org/> Linaro.org ? Open source software for ARM SoCs
Follow Linaro: <http://www.facebook.com/pages/Linaro> Facebook |
<http://twitter.com/#!/linaroorg> Twitter |
<http://www.linaro.org/linaro-blog/> Blog
^ permalink raw reply
* [PATCH V4] clk: at91: PLL recalc_rate() now using cached MUL and DIV values
From: Stephen Boyd @ 2018-05-15 23:04 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180509043205.GA57916@hak8or>
Quoting Marcin Ziemianowicz (2018-05-08 21:32:05)
> On Mon, Apr 30, 2018 at 07:58:47AM +0200, Boris Brezillon wrote:
> > On Sun, 29 Apr 2018 15:01:11 -0400
> > Marcin Ziemianowicz <marcin@ziemianowicz.com> wrote:
> >
> > > When a USB device is connected to the USB host port on the SAM9N12 then
> > > you get "-62" error which seems to indicate USB replies from the device
> > > are timing out. Based on a logic sniffer, I saw the USB bus was running
> > > at half speed.
> > >
> > > The PLL code uses cached MUL and DIV values which get set in set_rate()
> > > and applied in prepare(), but the recalc_rate() function instead
> > > queries the hardware instead of using these cached values. Therefore,
> > > if recalc_rate() is called between a set_rate() and prepare(), the
> > > wrong frequency is calculated and later the USB clock divider for the
> > > SAM9N12 SOC will be configured for an incorrect clock.
> > >
> > > In my case, the PLL hardware was set to 96 Mhz before the OHCI
> > > driver loads, and therefore the usb clock divider was being set
> > > to /2 even though the OHCI driver set the PLL to 48 Mhz.
> > >
> > > As an alternative explanation, I noticed this was fixed in the past by
> > > 87e2ed338f1b ("clk: at91: fix recalc_rate implementation of PLL
> > > driver") but the bug was later re-introduced by 1bdf02326b71 ("clk:
> > > at91: make use of syscon/regmap internally").
> > >
> > > Fixes: 1bdf02326b71 ("clk: at91: make use of syscon/regmap internally)
> > > Cc: <stable@vger.kernel.org>
> > > Signed-off-by: Marcin Ziemianowicz <marcin@ziemianowicz.com>
> >
> > Acked-by: Boris Brezillon <boris.brezillon@bootlin.com>
>
> Apologies for being a bother, but since it's been a bit over a week,
> should I do something with this now that it has been ACK'd? I was thinking
> I would see it somewhere on the git group repo but am not seeing it there
> yet. Googling says that there is a "review cycle" for some maintainers, but
> I am not clear on if I need to initiate it manually or anything of the sort.
>
I'll apply it to clk-next. Should appear in linux-next in day or so.
^ permalink raw reply
* Re: [PATCH v10 00/27] ARM: davinci: convert to common clock framework
From: David Lechner @ 2018-05-16 0:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHCN7xJt=tsc2zHWu+6y_2z=+kHdaovh3TD_MJ1+UeUbTdyj8w@mail.gmail.com>
On 5/15/18 5:44 PM, Adam Ford wrote:
> On Tue, May 15, 2018 at 4:25 AM, Bartosz Golaszewski <brgl@bgdev.pl> wrote:
>> 2018-05-14 2:40 GMT+02:00 Adam Ford <aford173@gmail.com>:
>>> On Wed, May 9, 2018 at 12:25 PM, David Lechner <david@lechnology.com> wrote:
>>>> This series converts mach-davinci to use the common clock framework.
>>>>
>>>> The series works like this, the first 3 patches fix some issues with the clock
>>>> drivers that have already been accepted into the mainline kernel.
>>>>
>>>> Then, starting with "ARM: davinci: pass clock as parameter to
>>>> davinci_timer_init()", we get the mach code ready for the switch by adding the
>>>> code needed for the new clock drivers and adding #ifndef CONFIG_COMMON_CLK
>>>> around the legacy clocks so that we can switch easily between the old and the
>>>> new.
>>>>
>>>> "ARM: davinci: switch to common clock framework" actually flips the switch
>>>> to start using the new clock drivers. Then the next 8 patches remove all
>>>> of the old clock code.
>>>>
>>>> The final four patches add device tree clock support to the one SoC that
>>>> supports it.
>>>>
>>>> This series has been tested on TI OMAP-L138 LCDK (both device tree and legacy
>>>> board file).
>>>>
>>>
>>> I am not sure if I did something wrong, but I attempted to build and I
>>> wasn't able to boot the da850-evm.dtb your repo common-clk-v11,
>>> however the legacy board file boot was OK.
>>>
>>> make davinci_all_defconfig ARCH=arm
>>> make zImage modules da850-evm.dtb ARCH=arm CROSS_COMPILE=arm-linux- -j8
>>>
>>> 3140416 bytes read in 1464 ms (2 MiB/s)
>>> 20353 bytes read in 15 ms (1.3 MiB/s)
>>> ## Flattened Device Tree blob at c0600000
>>> Booting using the fdt blob at 0xc0600000
>>> Loading Device Tree to c7e57000, end c7e5ef80 ... OK
>>>
>>> Starting kernel ...
>>>
>>> Uncompressing Linux... done, booting the kernel.
>>>
>>> (and hang)
>>>
>>> If you have some suggestions, I am try them as I get time.
>>>
>>> adam
>>>
>>
>> Runs fine on da850-lcdk and dm365-evm. I'll test the da850-evm
>> tomorrow when I'll have access to it.
>
> I set the bootargs to: bootargs=console=ttyS2,115200n8
> clk_ignore_unused root=/dev/mmcblk0p2 rw rootfstype=ext4 rootwait
It looks like you forgot earlyprintk in your bootargs.
>
> I enabled DEBUG_LL and EARLY_PRINTK, yet when it loads, I only get:
>
> ## Flattened Device Tree blob at c0600000
> Booting using the fdt blob at 0xc0600000
> Loading Device Tree to c7e57000, end c7e5ef35 ... OK
>
> Starting kernel ...
>
> Uncompressing Linux... done, booting the kernel.
>
>
> I am doing this at my home, so I don't have a debugger for the
> DA850-EVM. I am using a SOM that is an AM1808, but I vaguely remember
> something about enabling a DSP clock somewhere, but I cannot seem to
> find the e-mail. I know its counter intuitive that we'd need to
> enable a clock that runs the DSP since it doesn't exist on the AM1808,
> but I would have thought the clk_ignore_unused would have worked
> around that issue.
>
> If someone else has a DA850-EVM or suggestions, I'm willing to try
> them as I have time.
>
> adam
>>
>> Bart
^ permalink raw reply
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