* [PATCH V6 07/12] ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Add the common data for all dk07 based boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 +++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
new file mode 100644
index 0000000..9f1a5a66
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK07.1";
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x20000000>; /* 512MB */
+ };
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ soc {
+ pinctrl at 1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial at 78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7884000 {
+ status = "ok";
+ };
+
+ i2c at 78b7000 { /* BLSP1 QUP2 */
+ pinctrl-0 = <&i2c_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ qpic-nand at 79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 06/12] ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +++++++++
2 files changed, 10 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4e15d0d..c6cabec 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -761,6 +761,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
qcom-ipq4019-ap.dk04.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c3.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
new file mode 100644
index 0000000..2d1c4c6
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C3";
+ compatible = "qcom,ipq4019-ap-dk04.1-c3";
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 05/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Tested-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 +++++++++++++++++++
2 files changed, 20 insertions(+)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7e24249..4e15d0d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -760,6 +760,7 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-apq8084-ifc6540.dtb \
qcom-apq8084-mtp.dtb \
qcom-ipq4019-ap.dk01.1-c1.dtb \
+ qcom-ipq4019-ap.dk04.1-c1.dtb \
qcom-ipq8064-ap148.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8960-cdp.dtb \
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
new file mode 100644
index 0000000..7a96f30
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019-ap.dk04.1.dtsi"
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1-C1";
+ compatible = "qcom,ipq4019-dk04.1-c1";
+
+ soc {
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ qpic-nand at 79b0000 {
+ status = "ok";
+ };
+ };
+};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 04/12] ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Add the common parts for the dk04 boards.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 ++++++++++++++++++++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 112 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
new file mode 100644
index 0000000..7c1eb19
--- /dev/null
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2018, The Linux Foundation. All rights reserved.
+
+#include "qcom-ipq4019.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK04.1";
+
+ aliases {
+ serial0 = &blsp1_uart1;
+ serial1 = &blsp1_uart2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x80000000 0x10000000>; /* 256MB */
+ };
+
+ soc {
+ pinctrl at 1000000 {
+ serial_0_pins: serial0-pinmux {
+ pins = "gpio16", "gpio17";
+ function = "blsp_uart0";
+ bias-disable;
+ };
+
+ serial_1_pins: serial1-pinmux {
+ pins = "gpio8", "gpio9",
+ "gpio10", "gpio11";
+ function = "blsp_uart1";
+ bias-disable;
+ };
+
+ spi_0_pins: spi-0-pinmux {
+ pinmux {
+ function = "blsp_spi0";
+ pins = "gpio13", "gpio14", "gpio15";
+ bias-disable;
+ };
+ pinmux_cs {
+ function = "gpio";
+ pins = "gpio12";
+ bias-disable;
+ output-high;
+ };
+ };
+
+ i2c_0_pins: i2c-0-pinmux {
+ pins = "gpio20", "gpio21";
+ function = "blsp_i2c0";
+ bias-disable;
+ };
+
+ nand_pins: nand-pins {
+ pins = "gpio53", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59",
+ "gpio60", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66",
+ "gpio67", "gpio68", "gpio69";
+ function = "qpic";
+ };
+ };
+
+ serial at 78af000 {
+ pinctrl-0 = <&serial_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ serial at 78b0000 {
+ pinctrl-0 = <&serial_1_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ };
+
+ dma at 7884000 {
+ status = "ok";
+ };
+
+ spi at 78b5000 { /* BLSP1 QUP1 */
+ pinctrl-0 = <&spi_0_pins>;
+ pinctrl-names = "default";
+ status = "ok";
+ cs-gpios = <&tlmm 12 0>;
+
+ m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0>;
+ compatible = "n25q128a11";
+ spi-max-frequency = <24000000>;
+ };
+ };
+
+ pci at 40000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 38 0x1>;
+ };
+
+ qpic-nand at 79b0000 {
+ pinctrl-0 = <&nand_pins>;
+ pinctrl-names = "default";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 2c4ad7d..815c912 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -307,7 +307,7 @@
dma-names = "rx", "tx";
};
- serial at 78b0000 {
+ blsp1_uart2: serial at 78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 03/12] ARM: dts: ipq4019: Change the max opp frequency
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
The max opp frequency is 716MHZ. So update that.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1541e18..2c4ad7d 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -47,7 +47,7 @@
48000 1100000
200000 1100000
500000 1100000
- 666000 1100000
+ 716000 1100000
>;
clock-latency = <256000>;
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 02/12] ARM: dts: ipq4019: Add a few peripheral nodes
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Now with the driver updates for some peripherals being there,
add i2c, spi, pcie, bam, qpic-nand, scm nodes to enhance the available
peripheral support.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 2 +-
arch/arm/boot/dts/qcom-ipq4019.dtsi | 156 ++++++++++++++++++++++++--
2 files changed, 146 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index ef8d8c8..418f9a0 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -69,7 +69,7 @@
status = "ok";
};
- spi_0: spi at 78b5000 {
+ spi at 78b5000 {
pinctrl-0 = <&spi_0_pins>;
pinctrl-names = "default";
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index ea9202a..1541e18 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -24,8 +24,10 @@
interrupt-parent = <&intc>;
aliases {
- spi0 = &spi_0;
- i2c0 = &i2c_0;
+ spi0 = &blsp1_spi1;
+ spi1 = &blsp1_spi2;
+ i2c0 = &blsp1_i2c3;
+ i2c1 = &blsp1_i2c4;
};
cpus {
@@ -104,6 +106,12 @@
};
};
+ firmware {
+ scm {
+ compatible = "qcom,scm-ipq4019";
+ };
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
@@ -149,13 +157,13 @@
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
- interrupts = <0 208 0>;
+ interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
};
blsp_dma: dma at 7884000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x07884000 0x23000>;
- interrupts = <GIC_SPI 238 IRQ_TYPE_NONE>;
+ interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -163,7 +171,7 @@
status = "disabled";
};
- spi_0: spi at 78b5000 {
+ blsp1_spi1: spi at 78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
@@ -172,10 +180,26 @@
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 5>, <&blsp_dma 4>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ blsp1_spi2: spi at 78b6000 { /* BLSP1 QUP2 */
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x78b6000 0x600>;
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 7>, <&blsp_dma 6>;
+ dma-names = "rx", "tx";
status = "disabled";
};
- i2c_0: i2c at 78b7000 {
+ blsp1_i2c3: i2c at 78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
@@ -184,14 +208,29 @@
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
+ dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+ dma-names = "rx", "tx";
status = "disabled";
};
+ blsp1_i2c4: i2c at 78b8000 { /* BLSP1 QUP4 */
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x78b8000 0x600>;
+ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_AHB_CLK>,
+ <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "iface", "core";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ dmas = <&blsp_dma 11>, <&blsp_dma 10>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
cryptobam: dma at 8e04000 {
compatible = "qcom,bam-v1.7.0";
reg = <0x08e04000 0x20000>;
- interrupts = <GIC_SPI 207 0>;
+ interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_CRYPTO_AHB_CLK>;
clock-names = "bam_clk";
#dma-cells = <1>;
@@ -259,7 +298,7 @@
blsp1_uart1: serial at 78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
- interrupts = <0 107 0>;
+ interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -271,7 +310,7 @@
serial at 78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78b0000 0x200>;
- interrupts = <0 108 0>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
@@ -293,6 +332,101 @@
reg = <0x4ab000 0x4>;
};
+ pcie0: pci at 40000000 {
+ compatible = "qcom,pcie-ipq4019", "snps,dw-pcie";
+ reg = <0x40000000 0xf1d
+ 0x40000f20 0xa8
+ 0x80000 0x2000
+ 0x40100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ ranges = <0x81000000 0 0x40200000 0x40200000 0 0x00100000
+ 0x82000000 0 0x48000000 0x48000000 0 0x10000000>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+ clocks = <&gcc GCC_PCIE_AHB_CLK>,
+ <&gcc GCC_PCIE_AXI_M_CLK>,
+ <&gcc GCC_PCIE_AXI_S_CLK>;
+ clock-names = "aux",
+ "master_bus",
+ "slave_bus";
+
+ resets = <&gcc PCIE_AXI_M_ARES>,
+ <&gcc PCIE_AXI_S_ARES>,
+ <&gcc PCIE_PIPE_ARES>,
+ <&gcc PCIE_AXI_M_VMIDMT_ARES>,
+ <&gcc PCIE_AXI_S_XPU_ARES>,
+ <&gcc PCIE_PARF_XPU_ARES>,
+ <&gcc PCIE_PHY_ARES>,
+ <&gcc PCIE_AXI_M_STICKY_ARES>,
+ <&gcc PCIE_PIPE_STICKY_ARES>,
+ <&gcc PCIE_PWR_ARES>,
+ <&gcc PCIE_AHB_ARES>,
+ <&gcc PCIE_PHY_AHB_ARES>;
+ reset-names = "axi_m",
+ "axi_s",
+ "pipe",
+ "axi_m_vmid",
+ "axi_s_xpu",
+ "parf",
+ "phy",
+ "axi_m_sticky",
+ "pipe_sticky",
+ "pwr",
+ "ahb",
+ "phy_ahb";
+
+ status = "disabled";
+ };
+
+ qpic_bam: dma at 7984000 {
+ compatible = "qcom,bam-v1.7.0";
+ reg = <0x7984000 0x1a000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_QPIC_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ status = "disabled";
+ };
+
+ nand: qpic-nand at 79b0000 {
+ compatible = "qcom,ipq4019-nand";
+ reg = <0x79b0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&gcc GCC_QPIC_CLK>,
+ <&gcc GCC_QPIC_AHB_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&qpic_bam 0>,
+ <&qpic_bam 1>,
+ <&qpic_bam 2>;
+ dma-names = "tx", "rx", "cmd";
+ status = "disabled";
+
+ nand at 0 {
+ reg = <0>;
+
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
wifi0: wifi at a000000 {
compatible = "qcom,ipq4019-wifi";
reg = <0xa000000 0x200000>;
@@ -326,7 +460,7 @@
<GIC_SPI 45 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 46 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 47 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 168 IRQ_TYPE_NONE>;
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
@@ -368,7 +502,7 @@
<GIC_SPI 61 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 62 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 63 IRQ_TYPE_EDGE_RISING>,
- <GIC_SPI 169 IRQ_TYPE_NONE>;
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi0", "msi1", "msi2", "msi3",
"msi4", "msi5", "msi6", "msi7",
"msi8", "msi9", "msi10", "msi11",
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 01/12] ARM: dts: ipq4019: Add a default chosen node
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526475004-10341-1-git-send-email-sricharan@codeaurora.org>
Add a 'chosen' node to select the serial console.
This is needed when bootloaders do not pass the
'console=' bootargs.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 8 ++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
index e413b21e..ef8d8c8 100644
--- a/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi
@@ -20,6 +20,14 @@
model = "Qualcomm Technologies, Inc. IPQ4019/AP-DK01.1";
compatible = "qcom,ipq4019";
+ aliases {
+ serial0 = &blsp1_uart1;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
soc {
rng at 22000 {
status = "ok";
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 10d112a..ea9202a 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -256,7 +256,7 @@
regulator;
};
- serial at 78af000 {
+ blsp1_uart1: serial at 78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V6 00/12] ARM: dts: ipq: updates to enable a few peripherals
From: Sricharan R @ 2018-05-16 12:49 UTC (permalink / raw)
To: linux-arm-kernel
All the patches have been tested on ipq4019 dk01, 04, 07 and ipq8074 hk01
boards for spi, bam, qup, qpic, spi-nor, serial, pci.
[V6]
* Fixed Bjorn's comments, added his acks that he gave, added Varada's acks
* Rebased on top of Andy's for-next branch.
[v5]
* Fixed a minor comment that i missed earlier.
* https://www.spinics.net/lists/arm-kernel/msg643071.html
[v4]
* Fixed more comments.
* Dropped reserved-memory nodes from board files as
that might break existing users whose u-boot do not
specify the fdt_high accordingly.
* Added chosen serial node for all boards to have
the default serial console specified from DT.
[v3]
* Fixed minor comments from v2,
https://www.spinics.net/lists/arm-kernel/msg641480.html
* Added Abhishek's review tags
[v2]
* Addressed all comments from Abhishek
* Removed dk01-c2 and dk04-c5 spinand based boards
as support for spinand is not complete
* Based all patches on top of Andy's for-next branch
[V1]
* https://www.spinics.net/lists/arm-kernel/msg631318.html
Sricharan R (12):
ARM: dts: ipq4019: Add a default chosen node
ARM: dts: ipq4019: Add a few peripheral nodes
ARM: dts: ipq4019: Change the max opp frequency
ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi
ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file
ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file
ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file
ARM: dts: ipq8074: Add peripheral nodes
ARM: dts: ipq8074: Add pcie nodes
ARM: dts: ipq8074: Enable few peripherals for hk01 board
arch/arm/boot/dts/Makefile | 4 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk01.1.dtsi | 10 +-
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts | 19 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts | 9 +
arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi | 111 +++++++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts | 64 +++++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts | 25 ++
arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi | 75 ++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 162 ++++++++++--
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 62 ++++-
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 313 +++++++++++++++++++++++-
11 files changed, 827 insertions(+), 27 deletions(-)
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1-c3.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk04.1.dtsi
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c1.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1-c2.dts
create mode 100644 arch/arm/boot/dts/qcom-ipq4019-ap.dk07.1.dtsi
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply
* [PATCH] arm64: KVM: reduce guest fpsimd trap
From: Christoffer Dall @ 2018-05-16 12:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516103216.GR7753@e103592.cambridge.arm.com>
On Wed, May 16, 2018 at 11:32:17AM +0100, Dave Martin wrote:
> On Wed, May 16, 2018 at 10:25:40AM +0100, Marc Zyngier wrote:
> > [+Dave]
> >
> > Hi Nianyao,
> >
> > On 16/05/18 10:08, Tangnianyao (ICT) wrote:
> > > Add last_fpsimd_trap to notify if guest last exit reason is handling fpsimd. If guest is using fpsimd frequently, save host's fpsimd state and restore guest's fpsimd state and deactive fpsimd trap before returning to guest. It can avoid guest fpsimd trap soon to improve performance.
>
> So, the purpose of this patch is to context switch the FPSIMD state on
> initial entry to the guest, instead of enabling the trap and context
> switching the FPSIMD state lazily?
>
> And you decide whether to do this or not, based on whether the guest
> triggered a lazy FPSIMD switch previously?
>
> > >
> > > Signed-off-by: Nianyao Tang <tangnianyao@huawei.com>
> > > ---
> > > arch/arm64/kernel/asm-offsets.c | 1 +
> > > arch/arm64/kvm/hyp/entry.S | 5 +++++
> > > arch/arm64/kvm/hyp/switch.c | 38 ++++++++++++++++++++++++++++++++++++--
> > > include/linux/kvm_host.h | 1 +
> > > 4 files changed, 43 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/kernel/asm-offsets.c b/arch/arm64/kernel/asm-offsets.c index 5bdda65..35a9c5c 100644
> > > --- a/arch/arm64/kernel/asm-offsets.c
> > > +++ b/arch/arm64/kernel/asm-offsets.c
> > > @@ -136,6 +136,7 @@ int main(void)
> > > #ifdef CONFIG_KVM_ARM_HOST
> > > DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
> > > DEFINE(VCPU_FAULT_DISR, offsetof(struct kvm_vcpu, arch.fault.disr_el1));
> > > + DEFINE(VCPU_LAST_FPSIMD_TRAP, offsetof(struct kvm_vcpu,
> > > + last_fpsimd_trap));
> > > DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
> > > DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
> > > DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
> > > diff --git a/arch/arm64/kvm/hyp/entry.S b/arch/arm64/kvm/hyp/entry.S index e41a161..956e042 100644
> > > --- a/arch/arm64/kvm/hyp/entry.S
> > > +++ b/arch/arm64/kvm/hyp/entry.S
> > > @@ -197,6 +197,11 @@ alternative_endif
> > > add x0, x2, #CPU_GP_REG_OFFSET(CPU_FP_REGS)
> > > bl __fpsimd_restore_state
> > >
> > > + // Mark guest using fpsimd now
> > > + ldr x0, [x3, #VCPU_LAST_FPSIMD_TRAP]
> > > + add x0, x0, #1
>
> Can this overflow?
>
> > > + str x0, [x3, #VCPU_LAST_FPSIMD_TRAP]
> > > +
> > > // Skip restoring fpexc32 for AArch64 guests
> > > mrs x1, hcr_el2
> > > tbnz x1, #HCR_RW_SHIFT, 1f
> > > diff --git a/arch/arm64/kvm/hyp/switch.c b/arch/arm64/kvm/hyp/switch.c index d964523..86eea1b 100644
> > > --- a/arch/arm64/kvm/hyp/switch.c
> > > +++ b/arch/arm64/kvm/hyp/switch.c
> > > @@ -92,7 +92,13 @@ static void activate_traps_vhe(struct kvm_vcpu *vcpu)
> > >
> > > val = read_sysreg(cpacr_el1);
> > > val |= CPACR_EL1_TTA;
> > > - val &= ~(CPACR_EL1_FPEN | CPACR_EL1_ZEN);
> > > + val &= ~CPACR_EL1_ZEN;
> > > +
> > > + if (vcpu->last_fpsimd_trap)
> > > + val |= CPACR_EL1_FPEN;
> > > + else
> > > + val &= ~CPACR_EL1_FPEN;
> > > +
> > > write_sysreg(val, cpacr_el1);
> > >
> > > write_sysreg(kvm_get_hyp_vector(), vbar_el1); @@ -105,7 +111,13 @@ static void __hyp_text __activate_traps_nvhe(struct kvm_vcpu *vcpu)
> > > __activate_traps_common(vcpu);
> > >
> > > val = CPTR_EL2_DEFAULT;
> > > - val |= CPTR_EL2_TTA | CPTR_EL2_TFP | CPTR_EL2_TZ;
> > > + val |= CPTR_EL2_TTA | CPTR_EL2_TZ;
> > > +
> > > + if (vcpu->last_fpsimd_trap)
> > > + val &= ~CPTR_EL2_TFP;
> > > + else
> > > + val |= CPTR_EL2_TFP;
> > > +
> > > write_sysreg(val, cptr_el2);
> > > }
> > >
> > > @@ -406,6 +418,17 @@ int kvm_vcpu_run_vhe(struct kvm_vcpu *vcpu)
> > > __activate_traps(vcpu);
> > > __activate_vm(vcpu->kvm);
> > >
> > > + /*
> > > + * If guest last trap to host for handling fpsimd, last_fpsimd_trap
> > > + * is set. Restore guest's fpsimd state and deactivate fpsimd trap
> > > + * to avoid guest traping soon.
> > > + */
> > > + if (vcpu->last_fpsimd_trap) {
> > > + __fpsimd_save_state(&host_ctxt->gp_regs.fp_regs);
> > > + __fpsimd_restore_state(&guest_ctxt->gp_regs.fp_regs);
> > > + vcpu->last_fpsimd_trap = 0;
> > > + }
> > > +
> > > sysreg_restore_guest_state_vhe(guest_ctxt);
> > > __debug_switch_to_guest(vcpu);
> > >
> > > @@ -454,6 +477,17 @@ int __hyp_text __kvm_vcpu_run_nvhe(struct kvm_vcpu *vcpu)
> > > __activate_traps(vcpu);
> > > __activate_vm(kern_hyp_va(vcpu->kvm));
> > >
> > > + /*
> > > + * If guest last trap to host for handling fpsimd, last_fpsimd_trap
> > > + * is set. Restore guest's fpsimd state and deactivate fpsimd trap
> > > + * to avoid guest traping soon.
> > > + */
> > > + if (vcpu->last_fpsimd_trap) {
> > > + __fpsimd_save_state(&host_ctxt->gp_regs.fp_regs);
> > > + __fpsimd_restore_state(&guest_ctxt->gp_regs.fp_regs);
> > > + vcpu->last_fpsimd_trap = 0;
> > > + }
> > > +
> > > __hyp_vgic_restore_state(vcpu);
> > > __timer_enable_traps(vcpu);
> > >
> > > diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h index 6930c63..46bdf0d 100644
> > > --- a/include/linux/kvm_host.h
> > > +++ b/include/linux/kvm_host.h
> > > @@ -274,6 +274,7 @@ struct kvm_vcpu {
> > > bool preempted;
> > > struct kvm_vcpu_arch arch;
> > > struct dentry *debugfs_dentry;
> > > + unsigned int last_fpsimd_trap;
> > > };
> > >
> > > static inline int kvm_vcpu_exiting_guest_mode(struct kvm_vcpu *vcpu)
> > > --
> > > 2.7.4
> > >
> >
> > This doesn't seem to be the 100% correct. I can't see how this works
> > when being preempted, for example... I suggest you look at Dave Martin's
> > series[1], which does this correctly.
>
> If I've understood correctly, this chooses between eager and lazy
> switching, which is addressing a different issue from [1].
>
> In effect, this code is attempting to predict whether the guest will
> use FPSIMD before the next exit. If the prediction is correct and the
> guest does use FPSIMD, then the overhead of the lazy FPSIMD trap
> disappears. This is probably a good thing, though it may increase
> interrupt latency a little. However, if the prediction is wrong and
> the guest doesn't use FPSIMD before the next exit, then the overhead of
> guest entry increases for no benefit, because FPSIMD was switched
> unnecessarily.
>
> Do you have any benchmarks or metrics on the accuracy of the
> prediction and the overall impact on performance?
>
> The changes in [1] should reduce the number of FPSIMD context switches
> overall, so may reduce the benefit of this patch.
>
Based on previous measurements [2], I found that only in 29% of the
times when we return to userspace or are preempted, has the VCPU touched
the FPSIMD registers, and therefore a significant majority of the times
we enter the guest, the guest doesn't touch the FPSIMD state, even if it
has touched it before.
As Dave suggests, if there is data that shows that an immediately
following entry from an exit that had VFP enabled implies with a very
high probablity that the guest will touch VFP again, then something like
this might make sense, but I'd like to see some data to back up this
hypothesis before adding additional complexity to the code.
[2]: https://lists.cs.columbia.edu/pipermail/kvmarm/2018-February/029835.html
Thanks,
-Christoffer
^ permalink raw reply
* [PATCH v2] ARM: dts: imx6/7: Remove unit-address from anatop regulators
From: Fabio Estevam @ 2018-05-16 12:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180515074042.GP26863@dragon>
Hi Shawn,
On Tue, May 15, 2018 at 4:40 AM, Shawn Guo <shawnguo@kernel.org> wrote:
> I'm a bit confused. It looks that the change is just to revert commit
> 685e1321ba74 ("ARM: dts: imx6: Add unit address and reg for the anatop
> nodes"). But what about the simple_bus_reg warning the commit was
> fixing?
Yes, I don't get the original simple_bus_reg warning anymore.
I think we don't need the unit address and reg properties to the
anatop regulators.
There is already a 'anatop-reg-offset' property that indicates the
anatop register offset.
Rob, is this patch the correct solution to fix the duplicate
unit-address dtc warnings?
Thanks
^ permalink raw reply
* [PATCH] PCI: Clean up resource allocation in devm_of_pci_get_host_bridge_resources()
From: Jan Kiszka @ 2018-05-16 12:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAHp75VeM7_8+9QJjOypXaiBhpWP4B5KACdUQ-p3frbS3jPh=OQ@mail.gmail.com>
Instead of first allocating and then freeing memory for struct resource
in case we cannot parse a PCI resource from the device tree, work
against a local struct and kmemdup it when we decide to go with it.
Suggested-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
---
drivers/pci/of.c | 14 ++++++--------
1 file changed, 6 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/of.c b/drivers/pci/of.c
index b06585a1da75..fc0f906c5c25 100644
--- a/drivers/pci/of.c
+++ b/drivers/pci/of.c
@@ -266,7 +266,7 @@ int devm_of_pci_get_host_bridge_resources(struct device *dev,
struct list_head *resources, resource_size_t *io_base)
{
struct device_node *dev_node = dev->of_node;
- struct resource *res;
+ struct resource *res, tmp_res;
struct resource *bus_range;
struct of_pci_range range;
struct of_pci_range_parser parser;
@@ -320,18 +320,16 @@ int devm_of_pci_get_host_bridge_resources(struct device *dev,
if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
continue;
- res = devm_kzalloc(dev, sizeof(struct resource), GFP_KERNEL);
+ err = of_pci_range_to_resource(&range, dev_node, &tmp_res);
+ if (err)
+ continue;
+
+ res = devm_kmemdup(dev, &tmp_res, sizeof(tmp_res), GFP_KERNEL);
if (!res) {
err = -ENOMEM;
goto failed;
}
- err = of_pci_range_to_resource(&range, dev_node, res);
- if (err) {
- devm_kfree(dev, res);
- continue;
- }
-
if (resource_type(res) == IORESOURCE_IO) {
if (!io_base) {
dev_err(dev,
--
2.13.6
^ permalink raw reply related
* [PATCH 3/3] ARM: dts: imx28/imx53: enable edt-ft5x06 wakeup source
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516122829.23694-1-daniel@zonque.org>
The touchscreen driver no longer configures the device as wakeup source by
default. A "wakeup-source" property is needed.
To avoid regressions, this patch changes the DTS files for the only two
users of this driver that didn't have this property yet.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
arch/arm/boot/dts/imx28-tx28.dts | 1 +
arch/arm/boot/dts/imx53-tx53-x03x.dts | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/imx28-tx28.dts b/arch/arm/boot/dts/imx28-tx28.dts
index 0ebbc83852d0..094a39a67ec8 100644
--- a/arch/arm/boot/dts/imx28-tx28.dts
+++ b/arch/arm/boot/dts/imx28-tx28.dts
@@ -328,6 +328,7 @@
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
};
touchscreen: tsc2007 at 48 {
diff --git a/arch/arm/boot/dts/imx53-tx53-x03x.dts b/arch/arm/boot/dts/imx53-tx53-x03x.dts
index 0ecb43d88522..dbf0d73dc7b9 100644
--- a/arch/arm/boot/dts/imx53-tx53-x03x.dts
+++ b/arch/arm/boot/dts/imx53-tx53-x03x.dts
@@ -220,6 +220,7 @@
interrupts = <15 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 22 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio2 21 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
};
touchscreen: tsc2007 at 48 {
--
2.14.3
^ permalink raw reply related
* [PATCH 2/3] input: touchscreen: edt-ft5x06: assert reset during suspend
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516122829.23694-1-daniel@zonque.org>
If the device is not configured as wakeup source, it can be put in reset
during suspend to save some power.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
drivers/input/touchscreen/edt-ft5x06.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index 955f085627fa..c34a0b23f90a 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1036,9 +1036,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client *client)
static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
if (device_may_wakeup(dev))
enable_irq_wake(client->irq);
+ else if (tsdata->reset_gpio)
+ gpiod_set_value_cansleep(tsdata->reset_gpio, 1);
return 0;
}
@@ -1046,9 +1049,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
{
struct i2c_client *client = to_i2c_client(dev);
+ struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
if (device_may_wakeup(dev))
disable_irq_wake(client->irq);
+ else if (tsdata->reset_gpio)
+ gpiod_set_value_cansleep(tsdata->reset_gpio, 0);
return 0;
}
--
2.14.3
^ permalink raw reply related
* [PATCH 1/3] input: touchscreen: edt-ft5x06: make wakeup source behavior configurable
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516122829.23694-1-daniel@zonque.org>
Allow configuring the device as wakeup source through device properties, as
not all platforms want to wake up on touch screen activity.
Note that by default, the device will now no longer be a wakeup source.
Signed-off-by: Daniel Mack <daniel@zonque.org>
---
Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt | 3 +++
drivers/input/touchscreen/edt-ft5x06.c | 3 ++-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
index 025cf8c9324a..83f792d4d88c 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
+++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
@@ -52,6 +52,8 @@ Optional properties:
- touchscreen-inverted-y : See touchscreen.txt
- touchscreen-swapped-x-y : See touchscreen.txt
+ - wakeup-source: touchscreen acts as wakeup source
+
Example:
polytouch: edt-ft5x06 at 38 {
compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
@@ -62,4 +64,5 @@ Example:
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
+ wakeup-source;
};
diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
index 5bf63f76ddda..955f085627fa 100644
--- a/drivers/input/touchscreen/edt-ft5x06.c
+++ b/drivers/input/touchscreen/edt-ft5x06.c
@@ -1007,7 +1007,8 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
goto err_remove_attrs;
edt_ft5x06_ts_prepare_debugfs(tsdata, dev_driver_string(&client->dev));
- device_init_wakeup(&client->dev, 1);
+ device_init_wakeup(&client->dev,
+ device_property_read_bool(dev, "wakeup-source"));
dev_dbg(&client->dev,
"EDT FT5x06 initialized: IRQ %d, WAKE pin %d, Reset pin %d.\n",
--
2.14.3
^ permalink raw reply related
* [PATCH 0/3] input: touchscreen: edt-ft5x06: make wakeup source behavior configurable
From: Daniel Mack @ 2018-05-16 12:28 UTC (permalink / raw)
To: linux-arm-kernel
Hi,
I have a platform that features an edt-ft5x06 touch panel and that
doesn't want to wake on touch screen activity.
Here's a trivial series of patches that make the edt-ft5x06 driver only
act as wakeup source when requested through device properties or DTS.
The third patch changes the default in two DTS files that use this
driver.
I guess the first two patches should go through the input tree, while
the third can be picked by the IMX people. There are no compile-time
dependencies, so the order doesn't matter.
Thanks,
Daniel
Daniel Mack (3):
input: touchscreen: edt-ft5x06: make wakeup source behavior
configurable
input: touchscreen: edt-ft5x06: assert reset during suspend
ARM: dts: imx28/imx53: enable edt-ft5x06 wakeup source
.../devicetree/bindings/input/touchscreen/edt-ft5x06.txt | 3 +++
arch/arm/boot/dts/imx28-tx28.dts | 1 +
arch/arm/boot/dts/imx53-tx53-x03x.dts | 1 +
drivers/input/touchscreen/edt-ft5x06.c | 9 ++++++++-
4 files changed, 13 insertions(+), 1 deletion(-)
--
2.14.3
^ permalink raw reply
* [PATCH v4] pinctrl: msm: fix gpio-hog related boot issues
From: Linus Walleij @ 2018-05-16 12:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CACRpkdZPEHvnQdwh5Uu5kwqK7yVGTaw_cZR+GOzsG9pg4oEktA@mail.gmail.com>
On Thu, Apr 26, 2018 at 2:03 PM, Linus Walleij <linus.walleij@linaro.org> wrote:
> On Thu, Apr 12, 2018 at 9:01 PM, Christian Lamparter <chunkeey@gmail.com> wrote:
>
>> Sven Eckelmann reported an issue with the current IPQ4019 pinctrl.
>> Setting up any gpio-hog in the device-tree for his device would
>> "kill the bootup completely":
(...)
>> Reported-by: Sven Eckelmann <sven.eckelmann@openmesh.com>
>> Signed-off-by: Christian Lamparter <chunkeey@gmail.com>
>
> This patch looks VERY good to me.
>
> I am fine in merging it into pin control including the ranges
> fixes.
>
> I need Andy's and Bjorn's ACKs on it though!
>
> Can you guys provide that?
Hm? Andy, Bjorn?
Seems you guys are a bit snowed under.
I guess I have to just apply it at some point and see what
happens...
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH 3/7] pinctrl: sunxi: add support for H6 R_PIO pin controller
From: Linus Walleij @ 2018-05-16 12:20 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503183847.11046-4-icenowy@aosc.io>
On Thu, May 3, 2018 at 8:38 PM, Icenowy Zheng <icenowy@aosc.io> wrote:
> Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
> which controls the PL and PM pin banks.
>
> Add support for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Patch applied with the ACKs.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH v1] pinctrl: armada-37xx: Convert to use match_string() helper
From: Linus Walleij @ 2018-05-16 12:17 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180503172642.21031-1-andriy.shevchenko@linux.intel.com>
On Thu, May 3, 2018 at 7:26 PM, Andy Shevchenko
<andriy.shevchenko@linux.intel.com> wrote:
> The new helper returns index of the matching string in an array.
> We are going to use it here.
>
> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Patch applied.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] arm64: dts: juno: fix graph node unit addresses for coresight components
From: Sudeep Holla @ 2018-05-16 11:49 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <574f6959-6a84-9e0e-3d89-84d2d75d9191@arm.com>
On 16/05/18 12:23, Suzuki K Poulose wrote:
> On 05/16/2018 11:34 AM, Sudeep Holla wrote:
[..]
>> Hi Suzuki/Mathieu,
>>
>> I did a quick scan @ drivers/hwtracing/coresight/of_coresight.c to
>> check if reg field is being used or not and whether this change
>> causes any regression. I don't think so, but I may be wrong, let me
>> know.
>
> Unfortunately, I think this would break the components like funnel,
> where we need the input port number for the connected master to enable
> the port. Similarly for the output port number for master components in
> the paths. I have a set of patches which address this by taking care of
> the port number order to find out the hardware port number.
>
Ah ok, I now see of_graph_parse_endpoint, sorry for missing that.
> I will dust it up and send it. That would bring up another important
> question.
>
Cool
> How do we deal with the change in the port number scheme ? e.g, should
> the new kernel support DTBs with old scheme ?
IIUC, that's needed for backward compatibility as it was used schema.
Again I may be wrong.
> If so, how do we specify that the DT uses new scheme.
Perhaps, add something to indicate the change in numbering scheme ?
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH 1/1] ARM:dts:sunxi: Add Olimex A20-SOM-EVB-eMMC board
From: Stefan Mavrodiev @ 2018-05-16 11:38 UTC (permalink / raw)
To: linux-arm-kernel
With the new rev.E of A20-SOM-EVB, there is option for 16GB eMMC.
Currently used card is KLMAG2GEND, wired to MMC2 slot.
Signed-off-by: Stefan Mavrodiev <stefan@olimex.com>
---
arch/arm/boot/dts/Makefile | 1 +
.../arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts | 37 ++++++++++++++++++++++
2 files changed, 38 insertions(+)
create mode 100644 arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 1db91ec..7f1ee65 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -959,6 +959,7 @@ dtb-$(CONFIG_MACH_SUN7I) += \
sun7i-a20-m3.dtb \
sun7i-a20-mk808c.dtb \
sun7i-a20-olimex-som-evb.dtb \
+ sun7i-a20-olimex-som-evb-emmc.dtb \
sun7i-a20-olimex-som204-evb.dtb \
sun7i-a20-olimex-som204-evb-emmc.dtb \
sun7i-a20-olinuxino-lime.dtb \
diff --git a/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
new file mode 100644
index 0000000..81ebc97
--- /dev/null
+++ b/arch/arm/boot/dts/sun7i-a20-olimex-som-evb-emmc.dts
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree Source for A20-Olimex-SOM-EVB-eMMC Board
+ *
+ * Copyright (C) 2018 Olimex Ltd.
+ * Author: Stefan Mavrodiev <stefan@olimex.com>
+ */
+
+/dts-v1/;
+#include "sun7i-a20-olimex-som-evb.dts"
+
+/ {
+
+ model = "Olimex A20-Olimex-SOM-EVB-eMMC";
+ compatible = "olimex,a20-olimex-som-evb-emmc", "allwinner,sun7i-a20";
+
+ mmc2_pwrseq: mmc2_pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&pio 2 18 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&mmc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc2_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ mmc-pwrseq = <&mmc2_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ emmc: emmc at 0 {
+ reg = <0>;
+ compatible = "mmc-card";
+ broken-hpi;
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH 06/14] ARM: spectre-v2: harden branch predictor on context switches
From: Vladimir Murzin @ 2018-05-16 11:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fIuBA-0003pt-00@rmk-PC.armlinux.org.uk>
On 16/05/18 12:01, Russell King wrote:
> __v7_cr7mp_proc_info:
> .long 0x410fc170
> .long 0xff0ffff0
> - __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup
> + __v7_proc __v7_cr7mp_proc_info, __v7_cr7mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
> .size __v7_cr7mp_proc_info, . - __v7_cr7mp_proc_info
>
> /*
> @@ -649,7 +700,7 @@ ENDPROC(__v7_setup)
> __v7_cr8mp_proc_info:
> .long 0x410fc180
> .long 0xff0ffff0
> - __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup
> + __v7_proc __v7_cr8mp_proc_info, __v7_cr8mp_setup, proc_fns = HARDENED_BPIALL_PROCESSOR_FUNCTIONS
> .size __v7_cr8mp_proc_info, . - __v7_cr8mp_proc_info
For R-class cores, the mitigation doesn't make much sense since we do not enforce user/kernel
isolation anyway. I believe the same also applies to A-class cores built with !MMU, so you might
want to guard CPU_SPECTRE with MMU in PATCH 05/14.
Cheers
Vladimir
^ permalink raw reply
* [PATCH 14/14] mm: turn on vm_fault_t type checking
From: Matthew Wilcox @ 2018-05-16 11:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516054348.15950-15-hch@lst.de>
On Wed, May 16, 2018 at 07:43:48AM +0200, Christoph Hellwig wrote:
> Switch vm_fault_t to point to an unsigned int with __b?twise annotations.
> This both catches any old ->fault or ->page_mkwrite instance with plain
> compiler type checking, as well as finding more intricate problems with
> sparse.
Come on, Christoph; you know better than this. This patch is completely
unreviewable. Split it into one patch per maintainer tree, and in any
event, the patch to convert vm_fault_t to an unsigned int should be
separated from all the trivial conversions.
^ permalink raw reply
* vm_fault_t conversion, for real
From: Matthew Wilcox @ 2018-05-16 11:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516054348.15950-1-hch@lst.de>
On Wed, May 16, 2018 at 07:43:34AM +0200, Christoph Hellwig wrote:
> this series tries to actually turn vm_fault_t into a type that can be
> typechecked and checks the fallout instead of sprinkling random
> annotations without context.
Yes, why should we have small tasks that newcomers can do when the mighty
Christoph Hellwig can swoop in and take over from them? Seriously,
can't your talents find a better use than this?
> The first one fixes a real bug in orangefs, the second and third fix
> mismatched existing vm_fault_t annotations on the same function, the
> fourth removes an unused export that was in the chain. The remainder
> until the last one do some not quite trivial conversions, and the last
> one does the trivial mass annotation and flips vm_fault_t to a __bitwise
> unsigned int - the unsigned means we also get plain compiler type
> checking for the new ->fault signature even without sparse.
Yes, that was (part of) the eventual goal. Well done. Would you like
a biscuit?
^ permalink raw reply
* [PATCH] arm64: dts: juno: fix graph node unit addresses for coresight components
From: Suzuki K Poulose @ 2018-05-16 11:23 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526466862-19173-1-git-send-email-sudeep.holla@arm.com>
On 05/16/2018 11:34 AM, Sudeep Holla wrote:
> Currently the coresight components graph node unit addresses are
> continuous for both input and output ports while the "reg"
> properties are restarted for input and output ports separately. This
> results is the following DTC warnings:
>
> (graph_port): /etf at 20010000/ports/port at 1: graph node unit address
> error, expected "0" (graph_port): /etf at 20140000/ports/port at 1: graph
> node unit address error, expected "0" (graph_port):
> /funnel at 20040000/ports/port at 1: graph node unit address error,
> expected "0" (graph_port): /funnel at 20040000/ports/port at 2: graph node
> unit address error, expected "1" (graph_port):
> /funnel at 20040000/ports/port at 3: graph node unit address error,
> expected "2" (graph_port): /funnel at 20130000/ports/port at 1: graph node
> unit address error, expected "0" (graph_port):
> /funnel at 20150000/ports/port at 1: graph node unit address error,
> expected "0" (graph_port): /funnel at 20150000/ports/port at 2: graph node
> unit address error, expected "1" (graph_port):
> /funnel at 220c0000/ports/port at 1: graph node unit address error,
> expected "0" (graph_port): /funnel at 220c0000/ports/port at 2: graph node
> unit address error, expected "1" (graph_port):
> /funnel at 230c0000/ports/port at 1: graph node unit address error,
> expected "0" (graph_port): /funnel at 230c0000/ports/port at 2: graph node
> unit address error, expected "1" (graph_port):
> /funnel at 230c0000/ports/port at 3: graph node unit address error,
> expected "2" (graph_port): /funnel at 230c0000/ports/port at 4: graph node
> unit address error, expected "3" (graph_port):
> /replicator at 20120000/ports/port at 2: graph node unit address error,
> expected "0"
>
> This patch makes even the reg property to follow the continuous
> numbering as in the graph node unit address.
>
> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Mathieu Poirier
> <mathieu.poirier@linaro.org> Cc: Liviu Dudau <liviu.dudau@arm.com>
> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>> ---
> arch/arm64/boot/dts/arm/juno-base.dtsi | 20 ++++++++++----------
> arch/arm64/boot/dts/arm/juno-cs-r1r2.dtsi | 8 ++++----
> arch/arm64/boot/dts/arm/juno.dts | 2 +- 3 files changed, 15
> insertions(+), 15 deletions(-)
>
> Hi Suzuki/Mathieu,
>
> I did a quick scan @ drivers/hwtracing/coresight/of_coresight.c to
> check if reg field is being used or not and whether this change
> causes any regression. I don't think so, but I may be wrong, let me
> know.
Unfortunately, I think this would break the components like funnel,
where we need the input port number for the connected master to enable
the port. Similarly for the output port number for master components in
the paths. I have a set of patches which address this by taking care of
the port number order to find out the hardware port number.
I will dust it up and send it. That would bring up another important
question.
How do we deal with the change in the port number scheme ? e.g, should
the new kernel support DTBs with old scheme ? If so, how do we specify
that the DT uses new scheme.
Cheers
Suzuki
^ permalink raw reply
* [PATCH] arm64: cmpwait: Clear event register before arming exclusive monitor
From: Catalin Marinas @ 2018-05-16 11:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525092992-16819-1-git-send-email-will.deacon@arm.com>
On Mon, Apr 30, 2018 at 01:56:32PM +0100, Will Deacon wrote:
> When waiting for a cacheline to change state in cmpwait, we may immediately
> wake-up the first time around the outer loop if the event register was
> already set (for example, because of the event stream).
>
> Avoid these spurious wakeups by explicitly clearing the event register
> before loading the cacheline and setting the exclusive monitor.
>
> Signed-off-by: Will Deacon <will.deacon@arm.com>
Queued for 4.18. Thanks.
--
Catalin
^ permalink raw reply
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