* [PATCH] ghes_edac: enable HIP08 platform edac driver
From: James Morse @ 2018-05-16 13:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180514164720.GH23049@pd.tnic>
Hi Borislav, Zhengqiang
On 14/05/18 17:47, Borislav Petkov wrote:
> On Mon, May 14, 2018 at 04:12:08PM +0100, James Morse wrote:
>> I'm afraid I'd like to keep both doors open. Kernel-first handling will require
>> some ACPI-table/DT property as some aspects of the CPU extensions aren't
>> discover-able. Can't we use this to pick up whether the platform supports
>> firmware-first (HEST and GHES entries) or kernel-first via some as-yet-undefined
>> HEST bits?
>
> So how you detect those platforms is largely undefined as we're walking
> new grounds here with the FF crap on the one hand and platform-specific
> drivers on the other. So whatever works for you and as long as the
> ugliness is nicely hidden. :-)
>> Without GHES entries this code would never be run. So we 'just' need to catch
>> systems that are describing both. (which can be the platform specific kernel
>> first bits problem to do)
>
> So the reason why we're doing this on x86 is that the majority of
> GHES-advertizing platforms out there are a serious turd when it comes
> to functioning fw.
>
> So we've opted for known-good platforms list where there's backing from
> the vendor to have firmware which is getting fixes and is being tested
> properly.
Okay, so the question is whether we need a white/blacklist. The two older
platforms that describes GHES in their HEST tables are AMD-Seattle and APM-XGene.
XGene has its own edac driver, but it doesn't probe when booted via ACPI so
won't conflict with ghes_edac. On XGene:
| ghes_edac: GOT 2 DIMMS
| EDAC MC0: Giving out device to module ghes_edac.c controller ghes_edac: DEV
ghes (INTERRUPT)
On Seattle:
[ 6.119586] ghes_edac: GOT 4 DIMMS
[ 6.127294] EDAC MC0: Giving out device to module ghes_edac.c controller ghes
_edac: DEV ghes (INTERRUPT)
The thing has 4 dimm slots, but only two are populated. I swapped them round and
the table was regenerated, so I don't think its faking it.
So I think we're good to make the whitelist x86 only.
Your diff-hunk makes 'idx=-1', so we always get the 'Unfortunately' warning. I'd
like to suppress this unless force_load has been used.
> Anyway, this is the story in x86 land. JFYI guys in case it helps making
> some decisions.
Thanks!
What is the history behind the fake thing here? It predates 32fa1f53c2d
"ghes_edac: do a better job of filling EDAC DIMM info", was it to support a
valid system, or just to ease merging the driver when not all systems had the
dmi table?
It looks like even the oldest Arm64 ACPI systems have dmi tables, so we can
probably require DMI or the 'force' flag.
Thanks,
James
^ permalink raw reply
* [PATCH RFC 6/6] arm64: defconfig: Enable RPi voltage sensor
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526477827-10859-1-git-send-email-stefan.wahren@i2se.com>
The patch enables the hwmon driver for the Raspberry Pi.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d25121b..5cdecef 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -352,6 +352,7 @@ CONFIG_BATTERY_BQ27XXX=y
CONFIG_SENSORS_ARM_SCPI=y
CONFIG_SENSORS_LM90=m
CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y
CONFIG_CPU_THERMAL=y
CONFIG_THERMAL_EMULATION=y
--
2.7.4
^ permalink raw reply related
* [PATCH RFC 5/6] ARM: multi_v7_defconfig: Enable RPi voltage sensor
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526477827-10859-1-git-send-email-stefan.wahren@i2se.com>
The patch enables the hwmon driver for the Raspberry Pi.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 720461b..5c9dc00 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -477,6 +477,7 @@ CONFIG_SENSORS_LM90=y
CONFIG_SENSORS_LM95245=y
CONFIG_SENSORS_NTC_THERMISTOR=m
CONFIG_SENSORS_PWM_FAN=m
+CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_SENSORS_INA2XX=m
CONFIG_CPU_THERMAL=y
CONFIG_BCM2835_THERMAL=m
--
2.7.4
^ permalink raw reply related
* [PATCH RFC 4/6] ARM: bcm2835_defconfig: Enable RPi voltage sensor
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526477827-10859-1-git-send-email-stefan.wahren@i2se.com>
The patch enables the hwmon driver for the Raspberry Pi.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
arch/arm/configs/bcm2835_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig
index e4d188f..e9bc889 100644
--- a/arch/arm/configs/bcm2835_defconfig
+++ b/arch/arm/configs/bcm2835_defconfig
@@ -86,7 +86,7 @@ CONFIG_SPI=y
CONFIG_SPI_BCM2835=y
CONFIG_SPI_BCM2835AUX=y
CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
+CONFIG_SENSORS_RASPBERRYPI_HWMON=m
CONFIG_THERMAL=y
CONFIG_BCM2835_THERMAL=y
CONFIG_WATCHDOG=y
--
2.7.4
^ permalink raw reply related
* [PATCH RFC 3/6] hwmon: Add support for RPi voltage sensor
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526477827-10859-1-git-send-email-stefan.wahren@i2se.com>
Currently there is no easy way to detect under-voltage conditions on a remote
Raspberry Pi. This hwmon driver retrieves the state of the under-voltage sensor
via mailbox interface. The handling based on Noralf's modifications to the
downstream firmware driver. In case of an under-voltage condition only an entry
is written to the kernel log.
CC: "Noralf Tr?nnes" <noralf@tronnes.org>
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
drivers/hwmon/Kconfig | 10 ++
drivers/hwmon/Makefile | 1 +
drivers/hwmon/raspberrypi-hwmon.c | 207 ++++++++++++++++++++++++++++++++++++++
3 files changed, 218 insertions(+)
create mode 100644 drivers/hwmon/raspberrypi-hwmon.c
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 768aed5..7f935cf 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -1298,6 +1298,16 @@ config SENSORS_PWM_FAN
This driver can also be built as a module. If so, the module
will be called pwm-fan.
+config SENSORS_RASPBERRYPI_HWMON
+ tristate "Raspberry Pi voltage monitor"
+ depends on (ARCH_BCM2835 && RASPBERRYPI_FIRMWARE) || (COMPILE_TEST && !RASPBERRYPI_FIRMWARE)
+ help
+ If you say yes here you get support for voltage sensor on the
+ Raspberry Pi.
+
+ This driver can also be built as a module. If so, the module
+ will be called raspberrypi-hwmon.
+
config SENSORS_SHT15
tristate "Sensiron humidity and temperature sensors. SHT15 and compat."
depends on GPIOLIB || COMPILE_TEST
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index e7d52a3..a929770 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -141,6 +141,7 @@ obj-$(CONFIG_SENSORS_PC87427) += pc87427.o
obj-$(CONFIG_SENSORS_PCF8591) += pcf8591.o
obj-$(CONFIG_SENSORS_POWR1220) += powr1220.o
obj-$(CONFIG_SENSORS_PWM_FAN) += pwm-fan.o
+obj-$(CONFIG_SENSORS_RASPBERRYPI_HWMON) += raspberrypi-hwmon.o
obj-$(CONFIG_SENSORS_S3C) += s3c-hwmon.o
obj-$(CONFIG_SENSORS_SCH56XX_COMMON)+= sch56xx-common.o
obj-$(CONFIG_SENSORS_SCH5627) += sch5627.o
diff --git a/drivers/hwmon/raspberrypi-hwmon.c b/drivers/hwmon/raspberrypi-hwmon.c
new file mode 100644
index 0000000..2003f6c
--- /dev/null
+++ b/drivers/hwmon/raspberrypi-hwmon.c
@@ -0,0 +1,207 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Raspberry Pi voltage sensor driver
+ *
+ * Based on firmware/raspberrypi.c by Noralf Tr?nnes
+ *
+ * Copyright (C) 2018 Stefan Wahren <stefan.wahren@i2se.com>
+ */
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <soc/bcm2835/raspberrypi-firmware.h>
+
+#define UNDERVOLTAGE_STICKY_BIT BIT(16)
+
+struct rpi_hwmon_data {
+ struct device *hwmon_dev;
+ struct rpi_firmware *fw;
+ u32 last_throttled;
+ struct delayed_work get_values_poll_work;
+};
+
+static void rpi_firmware_get_throttled(struct rpi_hwmon_data *data)
+{
+ u32 new_uv, old_uv, value;
+ int ret;
+
+ /* Clear sticky bits */
+ value = 0xffff;
+
+ ret = rpi_firmware_property(data->fw, RPI_FIRMWARE_GET_THROTTLED,
+ &value, sizeof(value));
+ if (ret) {
+ dev_err_once(data->hwmon_dev, "%s: Failed to get throttled (%d)\n",
+ __func__, ret);
+ return;
+ }
+
+ new_uv = value & UNDERVOLTAGE_STICKY_BIT;
+ old_uv = data->last_throttled & UNDERVOLTAGE_STICKY_BIT;
+ data->last_throttled = value;
+
+ if (new_uv == old_uv)
+ return;
+
+ if (new_uv)
+ dev_crit(data->hwmon_dev, "Under-voltage detected! (0x%08x)\n",
+ value);
+ else
+ dev_info(data->hwmon_dev, "Voltage normalised (0x%08x)\n",
+ value);
+
+ sysfs_notify(&data->hwmon_dev->kobj, NULL, "in0_lcrit_alarm");
+}
+
+static void get_values_poll(struct work_struct *work)
+{
+ struct rpi_hwmon_data *data;
+
+ data = container_of(work, struct rpi_hwmon_data,
+ get_values_poll_work.work);
+
+ rpi_firmware_get_throttled(data);
+
+ /*
+ * We can't run faster than the sticky shift (100ms) since we get
+ * flipping in the sticky bits that are cleared.
+ */
+ schedule_delayed_work(&data->get_values_poll_work, 2 * HZ);
+}
+
+static int rpi_read(struct device *dev, enum hwmon_sensor_types type,
+ u32 attr, int channel, long *val)
+{
+ struct rpi_hwmon_data *data = dev_get_drvdata(dev);
+
+ if (type != hwmon_in)
+ return -EOPNOTSUPP;
+
+ if (attr != hwmon_in_lcrit_alarm)
+ return -EOPNOTSUPP;
+
+ if (channel)
+ return -EOPNOTSUPP;
+
+ *val = !!(data->last_throttled & UNDERVOLTAGE_STICKY_BIT);
+ return 0;
+}
+
+static umode_t rpi_is_visible(const void *_data, enum hwmon_sensor_types type,
+ u32 attr, int channel)
+{
+ if (type != hwmon_in)
+ return 0;
+
+ if (attr != hwmon_in_lcrit_alarm)
+ return 0;
+
+ if (channel)
+ return 0;
+
+ return 0444;
+}
+
+static const u32 rpi_in_config[] = {
+ HWMON_I_LCRIT_ALARM,
+ 0
+};
+
+static const struct hwmon_channel_info rpi_in = {
+ .type = hwmon_in,
+ .config = rpi_in_config,
+};
+
+static const struct hwmon_channel_info *rpi_info[] = {
+ &rpi_in,
+ NULL
+};
+
+static const struct hwmon_ops rpi_hwmon_ops = {
+ .is_visible = rpi_is_visible,
+ .read = rpi_read,
+};
+
+static const struct hwmon_chip_info rpi_chip_info = {
+ .ops = &rpi_hwmon_ops,
+ .info = rpi_info,
+};
+
+static int rpi_hwmon_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *fw_node;
+ struct rpi_hwmon_data *data;
+ int ret;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ fw_node = of_get_parent(dev->of_node);
+ if (!fw_node) {
+ dev_err(dev, "Missing firmware node\n");
+ return -ENOENT;
+ }
+
+ data->fw = rpi_firmware_get(fw_node);
+ of_node_put(fw_node);
+ if (!data->fw)
+ return -EPROBE_DEFER;
+
+ ret = rpi_firmware_property(data->fw, RPI_FIRMWARE_GET_THROTTLED,
+ &data->last_throttled,
+ sizeof(data->last_throttled));
+ if (ret) {
+ dev_info(dev, "Firmware doesn't support GET_THROTTLED\n");
+ return -EOPNOTSUPP;
+ }
+
+ data->hwmon_dev = devm_hwmon_device_register_with_info(dev, "rpi_volt",
+ data,
+ &rpi_chip_info,
+ NULL);
+
+ INIT_DELAYED_WORK(&data->get_values_poll_work, get_values_poll);
+ platform_set_drvdata(pdev, data);
+
+ if (!PTR_ERR_OR_ZERO(data->hwmon_dev))
+ schedule_delayed_work(&data->get_values_poll_work, 2 * HZ);
+
+ return PTR_ERR_OR_ZERO(data->hwmon_dev);
+}
+
+static int rpi_hwmon_remove(struct platform_device *pdev)
+{
+ struct rpi_hwmon_data *data = platform_get_drvdata(pdev);
+
+ cancel_delayed_work_sync(&data->get_values_poll_work);
+
+ return 0;
+}
+
+static const struct of_device_id rpi_hwmon_of_match[] = {
+ { .compatible = "raspberrypi,bcm2835-hwmon", },
+ { /* sentinel */},
+};
+MODULE_DEVICE_TABLE(of, rpi_hwmon_of_match);
+
+static struct platform_driver rpi_hwmon_driver = {
+ .probe = rpi_hwmon_probe,
+ .remove = rpi_hwmon_remove,
+ .driver = {
+ .name = "raspberrypi-hwmon",
+ .of_match_table = rpi_hwmon_of_match,
+ },
+};
+module_platform_driver(rpi_hwmon_driver);
+
+MODULE_AUTHOR("Stefan Wahren <stefan.wahren@i2se.com>");
+MODULE_DESCRIPTION("Raspberry Pi voltage sensor driver");
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [PATCH RFC 2/6] dt-bindings: hwmon: Add Raspberry Pi voltage sensor
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526477827-10859-1-git-send-email-stefan.wahren@i2se.com>
Recent VC4 firmware provides a hardware-independent way to retrieve the
under-voltage sensor on the following Raspberry Pi boards:
- Raspberry Pi B+ (via GPIO on SoC)
- Raspberry Pi A+ (via GPIO on SoC)
- Raspberry Pi 2 B (via GPIO on SoC)
- Raspberry Pi 3 B (via GPIO on port expander)
- Raspberry Pi 3 B+ (via PMIC)
TODO:
- try to make bcm2835 firmware a bus driver
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
.../devicetree/bindings/hwmon/raspberrypi-hwmon.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/raspberrypi-hwmon.txt
diff --git a/Documentation/devicetree/bindings/hwmon/raspberrypi-hwmon.txt b/Documentation/devicetree/bindings/hwmon/raspberrypi-hwmon.txt
new file mode 100644
index 0000000..ec2523f
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/raspberrypi-hwmon.txt
@@ -0,0 +1,19 @@
+Raspberry Pi voltage sensor
+---------------------------
+
+The VC4 firmware exposes a mailbox interface that allows the ARM core
+to access the board's voltage sensor.
+
+Required properties :
+- compatible : Should be "raspberrypi,bcm2835-hwmon"
+
+Example:
+
+firmware: firmware-rpi {
+ compatible = "raspberrypi,bcm2835-firmware";
+ mboxes = <&mailbox>;
+
+ voltage-sensor {
+ compatible = "raspberrypi,bcm2835-hwmon";
+ };
+};
--
2.7.4
^ permalink raw reply related
* [PATCH RFC 1/6] ARM: bcm2835: Add GET_THROTTLED firmware property
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526477827-10859-1-git-send-email-stefan.wahren@i2se.com>
Recent Raspberry Pi firmware provides a mailbox property to detect
under-voltage conditions. Here is the current definition.
The u32 value returned by the firmware is divided into 2 parts:
- lower 16-bits are the live value
- upper 16-bits are the history or sticky value
Bits:
0: under-voltage
1: arm frequency capped
2: currently throttled
16: under-voltage has occurred
17: arm frequency capped has occurred
18: throttling has occurred
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
---
include/soc/bcm2835/raspberrypi-firmware.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/soc/bcm2835/raspberrypi-firmware.h b/include/soc/bcm2835/raspberrypi-firmware.h
index 8ee8991..c4a5c9e 100644
--- a/include/soc/bcm2835/raspberrypi-firmware.h
+++ b/include/soc/bcm2835/raspberrypi-firmware.h
@@ -75,6 +75,7 @@ enum rpi_firmware_property_tag {
RPI_FIRMWARE_GET_EDID_BLOCK = 0x00030020,
RPI_FIRMWARE_GET_CUSTOMER_OTP = 0x00030021,
RPI_FIRMWARE_GET_DOMAIN_STATE = 0x00030030,
+ RPI_FIRMWARE_GET_THROTTLED = 0x00030046,
RPI_FIRMWARE_SET_CLOCK_STATE = 0x00038001,
RPI_FIRMWARE_SET_CLOCK_RATE = 0x00038002,
RPI_FIRMWARE_SET_VOLTAGE = 0x00038003,
--
2.7.4
^ permalink raw reply related
* [PATCH RFC 0/6] hwmon: Add support for Raspberry Pi voltage sensor
From: Stefan Wahren @ 2018-05-16 13:37 UTC (permalink / raw)
To: linux-arm-kernel
A common issue for the Raspberry Pi is an inadequate power supply.
Noralf Tr?nnes started a discussion [1] about writting such under-voltage
conditions into the kernel log.
This series is a draft to upstream the resulting kernel patch and is not
intended for 4.18.
[1] - https://github.com/raspberrypi/linux/issues/2367
Stefan Wahren (6):
ARM: bcm2835: Add GET_THROTTLED firmware property
dt-bindings: hwmon: Add Raspberry Pi voltage sensor
hwmon: Add support for RPi voltage sensor
ARM: bcm2835_defconfig: Enable RPi voltage sensor
ARM: multi_v7_defconfig: Enable RPi voltage sensor
arm64: defconfig: Enable RPi voltage sensor
.../bindings/hwmon/raspberrypi-hwmon.txt | 19 ++
arch/arm/configs/bcm2835_defconfig | 2 +-
arch/arm/configs/multi_v7_defconfig | 1 +
arch/arm64/configs/defconfig | 1 +
drivers/hwmon/Kconfig | 10 +
drivers/hwmon/Makefile | 1 +
drivers/hwmon/raspberrypi-hwmon.c | 207 +++++++++++++++++++++
include/soc/bcm2835/raspberrypi-firmware.h | 1 +
8 files changed, 241 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/hwmon/raspberrypi-hwmon.txt
create mode 100644 drivers/hwmon/raspberrypi-hwmon.c
--
2.7.4
^ permalink raw reply
* [PATCHv3] arm64: dts: stratix10: Add QSPI support for Stratix10
From: Dinh Nguyen @ 2018-05-16 13:36 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526423187-27521-1-git-send-email-thor.thayer@linux.intel.com>
On 05/15/2018 05:26 PM, thor.thayer at linux.intel.com wrote:
> From: Thor Thayer <thor.thayer@linux.intel.com>
>
> Add qspi_clock
> The qspi_clk frequency is updated by U-Boot before starting Linux.
> Add QSPI interface node.
> Add QSPI flash memory child node.
> Setup the QSPI memory in 2 partitions.
>
> Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com>
> ---
> v2 s/_/-/ in qspi-clk
> rename flash node.
> use partition child node notation
> v3 remove unused bus-num node
> use device id from table (n25q00a)
> ---
> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 21 +++++++++++++
> .../boot/dts/altera/socfpga_stratix10_socdk.dts | 35 ++++++++++++++++++++++
> 2 files changed, 56 insertions(+)
>
Applied!
Thanks,
Dinh
^ permalink raw reply
* [PATCH 2/4] ARM: davinci: board-da850-evm: fix GPIO lookup for MMC/SD
From: Adam Ford @ 2018-05-16 13:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <bf023e5e-5831-c9ad-bcd6-c9bb587ba848@ti.com>
On Wed, May 16, 2018 at 5:14 AM, Sekhar Nori <nsekhar@ti.com> wrote:
> On Wednesday 16 May 2018 04:23 AM, Adam Ford wrote:
>> On Thu, Apr 26, 2018 at 8:40 PM, David Lechner <david@lechnology.com> wrote:
>>> On 04/24/2018 09:35 AM, Sekhar Nori wrote:
>>>>
>>>> The GPIO chip is called davinci_gpio.0 in legacy mode. Fix it, so that
>>>> mmc can correctly lookup the wp and cp gpios. Also fix the GPIO numbers
>>>> as they are not offsets within a bank.
>>>>
>>>> Note that it is the gpio-davinci driver that sets the gpiochip label to
>>>> davinci_gpio.0.
>>>>
>>>> Fixes: bdf0e8364fd3 ("ARM: davinci: da850-evm: use gpio descriptor for mmc
>>>> pins")
>>>> Signed-off-by: Sekhar Nori <nsekhar@ti.com>
>>>> ---
>>>> arch/arm/mach-davinci/board-da850-evm.c | 9 +++++++--
>>>> 1 file changed, 7 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/arch/arm/mach-davinci/board-da850-evm.c
>>>> b/arch/arm/mach-davinci/board-da850-evm.c
>>>> index 3063478bcc36..158ed9a1483f 100644
>>>> --- a/arch/arm/mach-davinci/board-da850-evm.c
>>>> +++ b/arch/arm/mach-davinci/board-da850-evm.c
>>>> @@ -763,12 +763,17 @@ static const short da850_evm_mcasp_pins[]
>>>> __initconst = {
>>>> -1
>>>> };
>>>> +#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0)
>>>> +#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1)
>>>> +
>>>> static struct gpiod_lookup_table mmc_gpios_table = {
>>>> .dev_id = "da830-mmc.0",
>>>> .table = {
>>>> /* gpio chip 2 contains gpio range 64-95 */
>>>> - GPIO_LOOKUP("davinci_gpio.2", 0, "cd", GPIO_ACTIVE_LOW),
>>>> - GPIO_LOOKUP("davinci_gpio.2", 1, "wp", GPIO_ACTIVE_LOW),
>>>> + GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_CD_PIN, "cd",
>>>> + GPIO_ACTIVE_LOW),
>>>> + GPIO_LOOKUP("davinci_gpio.0", DA850_MMCSD_WP_PIN, "wp",
>>>> + GPIO_ACTIVE_LOW),
>>
>> I don't think the WP polarity is working correctly. If I boot the
>> board 'rw' enabled but WP disabled on the SD card, the system crashes.
>> If I enable WP, the board boots correctly.
>>
>> Comparing this to the device tree version that I did, and double
>> checking the behavior for my sanity, I believe WP needs to be
>> GPIO_ACTIVE_HIGH
>
> You are right, I see the issue on my board too. Although this patch did
> not touch the polarity, we could have fixed it here.
>
> Anyway, do you want to send a patch for that? Or I can do it too. A
> similar fix is needed for DA830 EVM too.
I don't have a DA830, so if I do a patch, it will be limited to the
DA850-evm. I can submit a patch later this afternoon, but if you have
time and want to do both at the same time, go head.
adam
>
> Thanks,
> Sekhar
^ permalink raw reply
* [PATCH net-next v2 15/15] arm64: dts: allwinner: a64: add SRAM controller device tree node
From: Maxime Ripard @ 2018-05-16 13:31 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAGb2v65uZeueE=2FfsxWen9zNvCtMsJ+b=KgMfSh-ZKmO+S=cQ@mail.gmail.com>
Hi,
On Tue, May 15, 2018 at 11:47:16PM -0700, Chen-Yu Tsai wrote:
> On Mon, May 14, 2018 at 1:03 AM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > 1;5201;0c
> > On Sun, May 13, 2018 at 12:37:49PM -0700, Chen-Yu Tsai wrote:
> >> On Wed, May 2, 2018 at 4:54 AM, Maxime Ripard <maxime.ripard@bootlin.com> wrote:
> >> > On Wed, May 02, 2018 at 06:19:51PM +0800, Icenowy Zheng wrote:
> >> >>
> >> >>
> >> >> ? 2018?5?2? GMT+08:00 ??5:53:21, Chen-Yu Tsai <wens@csie.org> ??:
> >> >> >On Wed, May 2, 2018 at 5:51 PM, Maxime Ripard
> >> >> ><maxime.ripard@bootlin.com> wrote:
> >> >> >> Hi,
> >> >> >>
> >> >> >> On Wed, May 02, 2018 at 12:12:27AM +0800, Chen-Yu Tsai wrote:
> >> >> >>> From: Icenowy Zheng <icenowy@aosc.io>
> >> >> >>>
> >> >> >>> Allwinner A64 has a SRAM controller, and in the device tree
> >> >> >currently
> >> >> >>> we have a syscon node to enable EMAC driver to access the EMAC clock
> >> >> >>> register. As SRAM controller driver can now export regmap for this
> >> >> >>> register, replace the syscon node to the SRAM controller device
> >> >> >node,
> >> >> >>> and let EMAC driver to acquire its EMAC clock regmap.
> >> >> >>>
> >> >> >>> Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
> >> >> >>> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
> >> >> >>> ---
> >> >> >>> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 23
> >> >> >+++++++++++++++----
> >> >> >>> 1 file changed, 19 insertions(+), 4 deletions(-)
> >> >> >>>
> >> >> >>> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >>> index 1b2ef28c42bd..1c37659d9d41 100644
> >> >> >>> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >>> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> >> >> >>> @@ -168,10 +168,25 @@
> >> >> >>> #size-cells = <1>;
> >> >> >>> ranges;
> >> >> >>>
> >> >> >>> - syscon: syscon at 1c00000 {
> >> >> >>> - compatible =
> >> >> >"allwinner,sun50i-a64-system-controller",
> >> >> >>> - "syscon";
> >> >> >>> + sram_controller: sram-controller at 1c00000 {
> >> >> >>> + compatible =
> >> >> >"allwinner,sun50i-a64-sram-controller";
> >> >> >>
> >> >> >> I don't think there's anything preventing us from keeping the
> >> >> >> -system-controller compatible. It's what was in the DT before, and
> >> >> >> it's how it's called in the datasheet.
> >> >> >
> >> >> >I actually meant to ask you about this. The -system-controller
> >> >> >compatible matches the datasheet better. Maybe we should just
> >> >> >switch to that one?
> >> >>
> >> >> No, if we do the switch the system-controller compatible,
> >> >> the device will be probed on the same memory region with
> >> >> a syscon on old DTs.
> >> >
> >> > The device hasn't magically changed either. Maybe we just need to add
> >> > a check to make sure we don't have the syscon compatible in the SRAM
> >> > driver probe so that the double driver issue doesn't happen?
> >>
> >> The syscon interface (which is not even a full blown device driver)
> >> only looks at the "syscon" compatible. Either way we're removing that
> >> part from the device tree so things should be ok for new device trees.
> >> As Maxime mentioned we can do a check for the syscon compatible and
> >> either give a warning to the user asking them to update their device
> >> tree, or not register our custom regmap, or not probe the SRAM driver.
> >> Personally I prefer the first option. The system controller block is
> >> probed before any syscon users, so we should be fine, given the dwmac
> >> driver goes the custom regmap path first.
> >>
> >> BTW, I still might end up changing the compatible. The manual uses
> >> "system control", not "system controller", which I think makes sense,
> >> since it is just a bunch of register files, kind of like the GRF
> >> (General Register Files) block found in Rockchip SoCs [1], and not an
> >> actual "controller".
> >
> > I'm not really fond of that, but we should at least make it consistent
> > on the other patches Paul sent then.
>
> For the A10s / A13 right?
And A33, yep.
> I think my naming is slightly better, but it's just a minor detail.
Let's do this then.
> While we're still debating this, can I merge the R40 stuff first?
> The driver bits are already in.
Yep, go ahead.
Maxime
--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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^ permalink raw reply
* vm_fault_t conversion, for real
From: Matthew Wilcox @ 2018-05-16 13:22 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516130309.GB32454@lst.de>
On Wed, May 16, 2018 at 03:03:09PM +0200, Christoph Hellwig wrote:
> On Wed, May 16, 2018 at 04:23:47AM -0700, Matthew Wilcox wrote:
> > On Wed, May 16, 2018 at 07:43:34AM +0200, Christoph Hellwig wrote:
> > > this series tries to actually turn vm_fault_t into a type that can be
> > > typechecked and checks the fallout instead of sprinkling random
> > > annotations without context.
> >
> > Yes, why should we have small tasks that newcomers can do when the mighty
> > Christoph Hellwig can swoop in and take over from them? Seriously,
> > can't your talents find a better use than this?
>
> I've spent less time on this than trying to argue to you and Souptick
> that these changes are only to get ignored and yelled at as an
> "asshole maintainer". So yes, I could have done more productive things
> if you hadn't forced this escalation.
Perhaps you should try being less of an arsehole if you don't want to
get yelled at? I don't mind when you're an arsehole towards me, but I
do mind when you're an arsehole towards newcomers. How are we supposed
to attract and retain new maintainers when you're so rude?
^ permalink raw reply
* [PATCH 10/14] vgem: separate errno from VM_FAULT_* values
From: Matthew Wilcox @ 2018-05-16 13:13 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516130159.GA32454@lst.de>
On Wed, May 16, 2018 at 03:01:59PM +0200, Christoph Hellwig wrote:
> On Wed, May 16, 2018 at 11:53:03AM +0200, Daniel Vetter wrote:
> > Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
> >
> > Want me to merge this through drm-misc or plan to pick it up yourself?
>
> For now I just want a honest discussion if people really actually
> want the vm_fault_t change with the whole picture in place.
That discussion already happened on the -mm mailing list. And again
at LSFMM. Both times the answer was yes.
^ permalink raw reply
* [PATCH v7 03/14] clk: qcom: Add CPU clock driver for msm8996
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526375616-16904-4-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> Each of the CPU clusters (Power and Perf) on msm8996 are
> clocked via 2 PLLs, a primary and alternate. There are also
> 2 Mux'es, a primary and secondary all connected together
> as shown below
>
> +-------+
> XO | |
> +------------------>0 |
> | |
> PLL/2 | SMUX +----+
> +------->1 | |
> | | | |
> | +-------+ | +-------+
> | +---->0 |
> | | |
> +---------------+ | +----------->1 | CPU clk
> |Primary PLL +----+ PLL_EARLY | | +------>
> | +------+-----------+ +------>2 PMUX |
> +---------------+ | | | |
> | +------+ | +-->3 |
> +--^+ ACD +-----+ | +-------+
> +---------------+ +------+ |
> |Alt PLL | |
> | +---------------------------+
> +---------------+ PLL_EARLY
>
> The primary PLL is what drives the CPU clk, except for times
> when we are reprogramming the PLL itself (for rate changes) when
> we temporarily switch to an alternate PLL. A subsequent patch adds
> support to switch between primary and alternate PLL during rate
> changes.
>
> The primary PLL operates on a single VCO range, between 600MHz
> and 3GHz. However the CPUs do support OPPs with frequencies
> between 300MHz and 600MHz. In order to support running the CPUs
> at those frequencies we end up having to lock the PLL at twice
> the rate and drive the CPU clk via the PLL/2 output and SMUX.
>
> So for frequencies above 600MHz we follow the following path
> Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
> and for frequencies between 300MHz and 600MHz we follow
> Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
> Support for this is added in a subsequent patch as well.
>
> ACD stands for Adaptive Clock Distribution and is used to
> detect voltage droops. We do not add support for ACD as yet.
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/clk/clk-fixed-factor.c | 2 +-
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clk-alpha-pll.h | 6 +
> drivers/clk/qcom/clk-cpu-8996.c | 412 +++++++++++++++++++++++++++++++++++++++
> 5 files changed, 429 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
>
> diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
> index a5d402d..8e39bda 100644
> --- a/drivers/clk/clk-fixed-factor.c
> +++ b/drivers/clk/clk-fixed-factor.c
> @@ -94,7 +94,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
> init.num_parents = 1;
>
> hw = &fix->hw;
> - ret = clk_hw_register(dev, hw);
> + ret = devm_clk_hw_register(dev, hw);
This should probably go in its own separate patch.
> if (ret) {
> kfree(fix);
> hw = ERR_PTR(ret);
> diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
> index e42e1af..866ce1f 100644
> --- a/drivers/clk/qcom/Kconfig
> +++ b/drivers/clk/qcom/Kconfig
> @@ -33,6 +33,15 @@ config QCOM_CLK_APCS_MSM8916
> Say Y if you want to support CPU frequency scaling on devices
> such as msm8916.
>
> +config QCOM_CLK_APCC_MSM8996
> + tristate "MSM8996 CPU Clock Controller"
> + depends on COMMON_CLK_QCOM
> + select QCOM_KRYO_L2_ACCESSORS
> + help
> + Support for the CPU clock controller on msm8996 devices.
> + Say Y if you want to support CPU clock scaling using CPUfreq
> + drivers for dyanmic power management.
> +
> config QCOM_CLK_RPM
> tristate "RPM based Clock Controller"
> depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 7c09ab1..a822fc8 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -36,6 +36,7 @@ obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
> obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
> obj-$(CONFIG_QCOM_A53PLL) += a53-pll.o
> obj-$(CONFIG_QCOM_CLK_APCS_MSM8916) += apcs-msm8916.o
> +obj-$(CONFIG_QCOM_CLK_APCC_MSM8996) += clk-cpu-8996.o
> obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
> obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
> obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
> diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h
> index f981b48..9ce2a32 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.h
> +++ b/drivers/clk/qcom/clk-alpha-pll.h
> @@ -50,6 +50,12 @@ struct pll_vco {
> u32 val;
> };
>
> +#define VCO(a, b, c) { \
> + .val = a,\
> + .min_freq = b,\
> + .max_freq = c,\
> +}
> +
> /**
> * struct clk_alpha_pll - phase locked loop (PLL)
> * @offset: base address of registers
> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
> new file mode 100644
> index 0000000..beb97eb
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-cpu-8996.c
> @@ -0,0 +1,412 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/*
> + * Each of the CPU clusters (Power and Perf) on msm8996 are
> + * clocked via 2 PLLs, a primary and alternate. There are also
> + * 2 Mux'es, a primary and secondary all connected together
> + * as shown below
> + *
> + * +-------+
> + * XO | |
> + * +------------------>0 |
> + * | |
> + * PLL/2 | SMUX +----+
> + * +------->1 | |
> + * | | | |
> + * | +-------+ | +-------+
> + * | +---->0 |
> + * | | |
> + * +---------------+ | +----------->1 | CPU clk
> + * |Primary PLL +----+ PLL_EARLY | | +------>
> + * | +------+-----------+ +------>2 PMUX |
> + * +---------------+ | | | |
> + * | +------+ | +-->3 |
> + * +--^+ ACD +-----+ | +-------+
> + * +---------------+ +------+ |
> + * |Alt PLL | |
> + * | +---------------------------+
> + * +---------------+ PLL_EARLY
> + *
> + * The primary PLL is what drives the CPU clk, except for times
> + * when we are reprogramming the PLL itself (for rate changes) when
> + * we temporarily switch to an alternate PLL. A subsequent patch adds
> + * support to switch between primary and alternate PLL during rate
> + * changes.
> + *
> + * The primary PLL operates on a single VCO range, between 600MHz
> + * and 3GHz. However the CPUs do support OPPs with frequencies
> + * between 300MHz and 600MHz. In order to support running the CPUs
> + * at those frequencies we end up having to lock the PLL at twice
> + * the rate and drive the CPU clk via the PLL/2 output and SMUX.
> + *
> + * So for frequencies above 600MHz we follow the following path
> + * Primary PLL --> PLL_EARLY --> PMUX(1) --> CPU clk
> + * and for frequencies between 300MHz and 600MHz we follow
> + * Primary PLL --> PLL/2 --> SMUX(1) --> PMUX(0) --> CPU clk
> + * Support for this is added in a subsequent patch as well.
> + *
> + * ACD stands for Adaptive Clock Distribution and is used to
> + * detect voltage droops. We do not add support for ACD as yet.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +#include "clk-alpha-pll.h"
> +#include "clk-regmap.h"
> +
> +enum _pmux_input {
> + DIV_2_INDEX = 0,
> + PLL_INDEX,
> + ACD_INDEX,
> + ALT_INDEX,
> + NUM_OF_PMUX_INPUTS
> +};
> +
> +static const u8 prim_pll_regs[PLL_OFF_MAX_REGS] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_USER_CTL] = 0x10,
> + [PLL_OFF_CONFIG_CTL] = 0x18,
> + [PLL_OFF_CONFIG_CTL_U] = 0x1c,
> + [PLL_OFF_TEST_CTL] = 0x20,
> + [PLL_OFF_TEST_CTL_U] = 0x24,
> + [PLL_OFF_STATUS] = 0x28,
> +};
> +
> +static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
> + [PLL_OFF_L_VAL] = 0x04,
> + [PLL_OFF_ALPHA_VAL] = 0x08,
> + [PLL_OFF_ALPHA_VAL_U] = 0x0c,
> + [PLL_OFF_USER_CTL] = 0x10,
> + [PLL_OFF_USER_CTL_U] = 0x14,
> + [PLL_OFF_CONFIG_CTL] = 0x18,
> + [PLL_OFF_TEST_CTL] = 0x20,
> + [PLL_OFF_TEST_CTL_U] = 0x24,
> + [PLL_OFF_STATUS] = 0x28,
> +};
> +
> +/* PLLs */
> +
> +static const struct alpha_pll_config hfpll_config = {
> + .l = 60,
> + .config_ctl_val = 0x200d4828,
> + .config_ctl_hi_val = 0x006,
> + .pre_div_mask = BIT(12),
> + .post_div_mask = 0x3 << 8,
> + .main_output_mask = BIT(0),
> + .early_output_mask = BIT(3),
> +};
> +
> +static struct clk_alpha_pll perfcl_pll = {
> + .offset = 0x80000,
> + .regs = prim_pll_regs,
> + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "perfcl_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll pwrcl_pll = {
> + .offset = 0x0,
> + .regs = prim_pll_regs,
> + .flags = SUPPORTS_DYNAMIC_UPDATE | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data){
> + .name = "pwrcl_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_huayra_ops,
> + },
> +};
> +
> +static const struct pll_vco alt_pll_vco_modes[] = {
> + VCO(3, 250000000, 500000000),
> + VCO(2, 500000000, 750000000),
> + VCO(1, 750000000, 1000000000),
> + VCO(0, 1000000000, 2150400000),
> +};
> +
> +static const struct alpha_pll_config altpll_config = {
> + .l = 16,
> + .vco_val = 0x3 << 20,
> + .vco_mask = 0x3 << 20,
> + .config_ctl_val = 0x4001051b,
> + .post_div_mask = 0x3 << 8,
> + .post_div_val = 0x1,
> + .main_output_mask = BIT(0),
> + .early_output_mask = BIT(3),
> +};
> +
> +static struct clk_alpha_pll perfcl_alt_pll = {
> + .offset = 0x80100,
> + .regs = alt_pll_regs,
> + .vco_table = alt_pll_vco_modes,
> + .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
> + .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "perfcl_alt_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_hwfsm_ops,
> + },
> +};
> +
> +static struct clk_alpha_pll pwrcl_alt_pll = {
> + .offset = 0x100,
> + .regs = alt_pll_regs,
> + .vco_table = alt_pll_vco_modes,
> + .num_vco = ARRAY_SIZE(alt_pll_vco_modes),
> + .flags = SUPPORTS_OFFLINE_REQ | SUPPORTS_FSM_MODE,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pwrcl_alt_pll",
> + .parent_names = (const char *[]){ "xo" },
> + .num_parents = 1,
> + .ops = &clk_alpha_pll_hwfsm_ops,
> + },
> +};
> +
> +/* Mux'es */
> +
> +struct clk_cpu_8996_mux {
> + u32 reg;
> + u8 shift;
> + u8 width;
> + struct clk_hw *pll;
> + struct clk_regmap clkr;
> +};
> +
> +static inline
> +struct clk_cpu_8996_mux *to_clk_cpu_8996_mux_hw(struct clk_hw *hw)
> +{
> + return container_of(to_clk_regmap(hw), struct clk_cpu_8996_mux, clkr);
> +}
> +
> +static u8 clk_cpu_8996_mux_get_parent(struct clk_hw *hw)
> +{
> + u32 val;
> + struct clk_regmap *clkr = to_clk_regmap(hw);
> + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
> + u32 mask = (u32)GENMASK(cpuclk->width - 1, 0);
> +
> + regmap_read(clkr->regmap, cpuclk->reg, &val);
> + val >>= (u32)(cpuclk->shift);
> +
> + return (u8)(val & mask);
> +}
> +
> +static int clk_cpu_8996_mux_set_parent(struct clk_hw *hw, u8 index)
> +{
> + u32 val;
> + struct clk_regmap *clkr = to_clk_regmap(hw);
> + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
> + unsigned int mask = GENMASK(cpuclk->width + cpuclk->shift - 1,
> + cpuclk->shift);
> +
> + val = (u32)index;
> + val <<= (u32)(cpuclk->shift);
> +
> + return regmap_update_bits(clkr->regmap, cpuclk->reg, mask, val);
> +}
> +
> +static int
> +clk_cpu_8996_mux_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
> +{
> + struct clk_cpu_8996_mux *cpuclk = to_clk_cpu_8996_mux_hw(hw);
> + struct clk_hw *parent = cpuclk->pll;
> +
> + req->best_parent_rate = clk_hw_round_rate(parent, req->rate);
> + req->best_parent_hw = parent;
> +
> + return 0;
> +}
> +
> +const struct clk_ops clk_cpu_8996_mux_ops = {
> + .set_parent = clk_cpu_8996_mux_set_parent,
> + .get_parent = clk_cpu_8996_mux_get_parent,
> + .determine_rate = clk_cpu_8996_mux_determine_rate,
> +};
> +
> +static struct clk_cpu_8996_mux pwrcl_smux = {
> + .reg = 0x40,
> + .shift = 2,
> + .width = 2,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pwrcl_smux",
> + .parent_names = (const char *[]){
> + "xo",
> + "pwrcl_pll_main",
> + },
> + .num_parents = 2,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_cpu_8996_mux perfcl_smux = {
> + .reg = 0x80040,
> + .shift = 2,
> + .width = 2,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "perfcl_smux",
> + .parent_names = (const char *[]){
> + "xo",
> + "perfcl_pll_main",
> + },
> + .num_parents = 2,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_cpu_8996_mux pwrcl_pmux = {
> + .reg = 0x40,
> + .shift = 0,
> + .width = 2,
> + .pll = &pwrcl_pll.clkr.hw,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "pwrcl_pmux",
> + .parent_names = (const char *[]){
> + "pwrcl_smux",
> + "pwrcl_pll",
> + "pwrcl_pll_acd",
> + "pwrcl_alt_pll",
> + },
> + .num_parents = 4,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> + },
> +};
> +
> +static struct clk_cpu_8996_mux perfcl_pmux = {
> + .reg = 0x80040,
> + .shift = 0,
> + .width = 2,
> + .pll = &perfcl_pll.clkr.hw,
> + .clkr.hw.init = &(struct clk_init_data) {
> + .name = "perfcl_pmux",
> + .parent_names = (const char *[]){
> + "perfcl_smux",
> + "perfcl_pll",
> + "perfcl_pll_acd",
> + "perfcl_alt_pll",
> + },
> + .num_parents = 4,
> + .ops = &clk_cpu_8996_mux_ops,
> + .flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
> + },
> +};
> +
> +static const struct regmap_config cpu_msm8996_regmap_config = {
> + .reg_bits = 32,
> + .reg_stride = 4,
> + .val_bits = 32,
> + .max_register = 0x80210,
> + .fast_io = true,
> + .val_format_endian = REGMAP_ENDIAN_LITTLE,
> +};
> +
> +struct clk_regmap *clks[] = {
> + &perfcl_pll.clkr,
> + &pwrcl_pll.clkr,
> + &perfcl_alt_pll.clkr,
> + &pwrcl_alt_pll.clkr,
> + &perfcl_smux.clkr,
> + &pwrcl_smux.clkr,
> + &perfcl_pmux.clkr,
> + &pwrcl_pmux.clkr,
> +};
> +
> +static int
> +qcom_cpu_clk_msm8996_register_clks(struct device *dev, struct regmap *regmap)
> +{
> + int i, ret;
> +
> + perfcl_smux.pll = clk_hw_register_fixed_factor(dev, "perfcl_pll_main",
> + "perfcl_pll",
> + CLK_SET_RATE_PARENT, 1, 2);
> +
> + pwrcl_smux.pll = clk_hw_register_fixed_factor(dev, "pwrcl_pll_main",
> + "pwrcl_pll",
> + CLK_SET_RATE_PARENT, 1, 2);
> +
> + for (i = 0; i < ARRAY_SIZE(clks); i++) {
> + ret = devm_clk_register_regmap(dev, clks[i]);
> + if (ret)
> + return ret;
> + }
> +
> + clk_alpha_pll_configure(&perfcl_pll, regmap, &hfpll_config);
> + clk_alpha_pll_configure(&pwrcl_pll, regmap, &hfpll_config);
> + clk_alpha_pll_configure(&perfcl_alt_pll, regmap, &altpll_config);
> + clk_alpha_pll_configure(&pwrcl_alt_pll, regmap, &altpll_config);
> +
> + return ret;
> +}
> +
> +static int qcom_cpu_clk_msm8996_driver_probe(struct platform_device *pdev)
> +{
> + int ret;
> + void __iomem *base;
> + struct resource *res;
> + struct regmap *regmap;
> + struct clk_hw_onecell_data *data;
> + struct device *dev = &pdev->dev;
> +
> + data = devm_kzalloc(dev, sizeof(*data) + 2 * sizeof(struct clk_hw *),
> + GFP_KERNEL);
> + if (!data)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(base))
> + return PTR_ERR(base);
> +
> + regmap = devm_regmap_init_mmio(dev, base, &cpu_msm8996_regmap_config);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + ret = qcom_cpu_clk_msm8996_register_clks(dev, regmap);
> + if (ret)
> + return ret;
> +
> + data->hws[0] = &pwrcl_pmux.clkr.hw;
> + data->hws[1] = &perfcl_pmux.clkr.hw;
> + data->num = 2;
> +
> + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, data);
> +}
> +
> +static const struct of_device_id qcom_cpu_clk_msm8996_match_table[] = {
> + { .compatible = "qcom,msm8996-apcc" },
> + {}
> +};
> +
> +static struct platform_driver qcom_cpu_clk_msm8996_driver = {
> + .probe = qcom_cpu_clk_msm8996_driver_probe,
> + .driver = {
> + .name = "qcom-msm8996-apcc",
> + .of_match_table = qcom_cpu_clk_msm8996_match_table,
> + },
> +};
> +module_platform_driver(qcom_cpu_clk_msm8996_driver);
> +
> +MODULE_ALIAS("platform:msm8996-apcc");
> +MODULE_DESCRIPTION("QCOM MSM8996 CPU Clock Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v7 10/14] dt-bindings: qcom_spmi: Add support for SAW documentation
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526375616-16904-11-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> Add support for SAW controlled regulators.
> The regulators defined as SAW controlled in the device tree
> will be controlled through special CPU registers instead of direct
> SPMI accesses.
> This is required especially for CPU supply regulators to synchronize
> with clock scaling and for Automatic Voltage Switching.
> Document it.
Replace this boiler plate with what this patch actual does. Besides
changing the subject, it could be, for example,
"Document the DT bindings for the SAW regulators.
The saw-slave property allows ganging (grouping) of several regulators
so that their outputs can be combined... blah blah.
The saw-leader is the only one that then is configurable in DT"
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
> index 57d2c65..406f2e5 100644
> --- a/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
> +++ b/Documentation/devicetree/bindings/regulator/qcom,spmi-regulator.txt
> @@ -110,6 +110,11 @@ Qualcomm SPMI Regulators
> Definition: Reference to regulator supplying the input pin, as
> described in the data sheet.
>
> +- qcom,saw-reg:
> + Usage: optional
> + Value type: <phandle>
> + Description: Reference to syscon node defining the SAW registers.
> +
>
> The regulator node houses sub-nodes for each regulator within the device. Each
> sub-node is identified using the node's name, with valid values listed for each
> @@ -201,6 +206,17 @@ see regulator.txt - with additional custom properties described below:
> 2 = 0.55 uA
> 3 = 0.75 uA
>
> +- qcom,saw-slave:
> + Usage: optional
> + Value type: <boo>
> + Description: SAW controlled gang slave. Will not be configured.
> +
> +- qcom,saw-leader:
> + Usage: optional
> + Value type: <boo>
> + Description: SAW controlled gang leader. Will be configured as
> + SAW regulator.
> +
> Example:
>
> regulators {
> @@ -221,3 +237,32 @@ Example:
>
> ....
> };
> +
> +Example 2:
> +
> + saw3: syscon at 9A10000 {
> + compatible = "syscon";
> + reg = <0x9A10000 0x1000>;
> + };
> +
> + ...
> +
> + spm-regulators {
> + compatible = "qcom,pm8994-regulators";
> + qcom,saw-reg = <&saw3>;
> + s8 {
> + qcom,saw-slave;
> + };
> + s9 {
> + qcom,saw-slave;
> + };
> + s10 {
> + qcom,saw-slave;
> + };
> + pm8994_s11_saw: s11 {
> + qcom,saw-leader;
> + regulator-always-on;
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1140000>;
> + };
> + };
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v7 12/14] cpufreq: Add Kryo CPU scaling driver
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526375616-16904-13-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> In Certain QCOM SoCs like apq8096 and msm8996 that have KRYO processors,
> the CPU ferequencies subset and voltage value of each OPP varies
s/ferequencies/frequency
> based on the silicon variant in use. Qualcomm Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/cpufreq/Kconfig.arm | 11 +++
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/cpufreq-dt-platdev.c | 3 +
> drivers/cpufreq/qcom-cpufreq-kryo.c | 150 +++++++++++++++++++++++++++++++++++
> 4 files changed, 165 insertions(+)
> create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
>
> diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
> index de55c7d..5c16f05 100644
> --- a/drivers/cpufreq/Kconfig.arm
> +++ b/drivers/cpufreq/Kconfig.arm
> @@ -124,6 +124,17 @@ config ARM_OMAP2PLUS_CPUFREQ
> depends on ARCH_OMAP2PLUS
> default ARCH_OMAP2PLUS
>
> +config ARM_QCOM_CPUFREQ_KRYO
> + bool "Qualcomm Technologies, Inc. Kryo based CPUFreq"
"Qualcomm Kryo CPUFreq support" should be enough. Kconfig isn't the
place for Trademark compliance :-)
> + depends on QCOM_QFPROM
> + depends on QCOM_SMEM
> + select PM_OPP
> + help
> + This adds the CPUFreq driver for
> + Qualcomm Technologies, Inc. Kryo SoC based boards.
> +
> + If in doubt, say N.
> +
> config ARM_S3C_CPUFREQ
> bool
> help
> diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
> index 8d24ade..fb4a2ec 100644
> --- a/drivers/cpufreq/Makefile
> +++ b/drivers/cpufreq/Makefile
> @@ -65,6 +65,7 @@ obj-$(CONFIG_MACH_MVEBU_V7) += mvebu-cpufreq.o
> obj-$(CONFIG_ARM_OMAP2PLUS_CPUFREQ) += omap-cpufreq.o
> obj-$(CONFIG_ARM_PXA2xx_CPUFREQ) += pxa2xx-cpufreq.o
> obj-$(CONFIG_PXA3xx) += pxa3xx-cpufreq.o
> +obj-$(CONFIG_ARM_QCOM_CPUFREQ_KRYO) += qcom-cpufreq-kryo.o
> obj-$(CONFIG_ARM_S3C2410_CPUFREQ) += s3c2410-cpufreq.o
> obj-$(CONFIG_ARM_S3C2412_CPUFREQ) += s3c2412-cpufreq.o
> obj-$(CONFIG_ARM_S3C2416_CPUFREQ) += s3c2416-cpufreq.o
> diff --git a/drivers/cpufreq/cpufreq-dt-platdev.c b/drivers/cpufreq/cpufreq-dt-platdev.c
> index 3b585e4..77d6ab8 100644
> --- a/drivers/cpufreq/cpufreq-dt-platdev.c
> +++ b/drivers/cpufreq/cpufreq-dt-platdev.c
> @@ -118,6 +118,9 @@
>
> { .compatible = "nvidia,tegra124", },
>
> + { .compatible = "qcom,apq8096", },
> + { .compatible = "qcom,msm8996", },
> +
> { .compatible = "st,stih407", },
> { .compatible = "st,stih410", },
>
> diff --git a/drivers/cpufreq/qcom-cpufreq-kryo.c b/drivers/cpufreq/qcom-cpufreq-kryo.c
> new file mode 100644
> index 0000000..10d7236
> --- /dev/null
> +++ b/drivers/cpufreq/qcom-cpufreq-kryo.c
> @@ -0,0 +1,150 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
Stray space here.
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/cpu.h>
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/slab.h>
> +#include <linux/soc/qcom/smem.h>
> +
> +#define MSM_ID_SMEM 137
> +#define SILVER_LEAD 0
> +#define GOLD_LEAD 2
> +
> +enum _msm_id {
> + MSM8996V3 = 0xF6ul,
> + APQ8096V3 = 0x123ul,
> + MSM8996SG = 0x131ul,
> + APQ8096SG = 0x138ul,
> +};
> +
> +enum _msm8996_version {
> + MSM8996_V3,
> + MSM8996_SG,
> + NUM_OF_MSM8996_VERSIONS,
> +};
> +
> +static enum _msm8996_version __init qcom_cpufreq_kryo_get_msm_id(void)
> +{
> + size_t len;
> + u32 *msm_id;
> + enum _msm8996_version version;
> +
> + msm_id = qcom_smem_get(QCOM_SMEM_HOST_ANY, MSM_ID_SMEM, &len);
> + /* The first 4 bytes are format, next to them is the actual msm-id */
> + msm_id++;
> +
> + switch ((enum _msm_id)*msm_id) {
> + case MSM8996V3:
> + case APQ8096V3:
> + version = MSM8996_V3;
> + break;
> + case MSM8996SG:
> + case APQ8096SG:
> + version = MSM8996_SG;
> + break;
> + default:
> + version = NUM_OF_MSM8996_VERSIONS;
> + }
> +
> + return version;
> +}
> +
> +static int __init qcom_cpufreq_kryo_driver_init(void)
> +{
> + size_t len;
> + int ret;
> + u32 versions;
> + enum _msm8996_version msm8996_version;
> + u8 *speedbin;
> + struct device *cpu_dev;
> + struct device_node *np;
> + struct nvmem_cell *speedbin_nvmem;
> + struct opp_table *opp_temp = NULL;
> +
> + cpu_dev = get_cpu_device(SILVER_LEAD);
> + if (IS_ERR_OR_NULL(cpu_dev))
> + return PTR_ERR(cpu_dev);
> +
> + msm8996_version = qcom_cpufreq_kryo_get_msm_id();
> + if (NUM_OF_MSM8996_VERSIONS == msm8996_version) {
> + dev_err(cpu_dev, "Not Snapdragon 820/821!");
> + return -ENODEV;
> + }
Use tab instead of spaces.
> +
> + np = dev_pm_opp_of_get_opp_desc_node(cpu_dev);
> + if (IS_ERR_OR_NULL(np))
> + return PTR_ERR(np);
> +
> + if (!of_device_is_compatible(np, "operating-points-v2-kryo-cpu")) {
> + ret = -ENOENT;
> + goto free_np;
> + }
> +
> + speedbin_nvmem = of_nvmem_cell_get(np, NULL);
> + if (IS_ERR(speedbin_nvmem)) {
> + ret = PTR_ERR(speedbin_nvmem);
> + dev_err(cpu_dev, "Could not get nvmem cell: %d\n", ret);
> + goto free_np;
> + }
> +
> + speedbin = nvmem_cell_read(speedbin_nvmem, &len);
> +
> + switch (msm8996_version) {
> + case MSM8996_V3:
> + versions = 1 << (unsigned int)(*speedbin);
> + break;
> + case MSM8996_SG:
> + versions = 1 << ((unsigned int)(*speedbin) + 4);
> + break;
> + default:
> + BUG();
> + break;
> + }
> +
> + ret = PTR_ERR_OR_ZERO(opp_temp =
> + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> + if (0 > ret)
Any particular reason to prefer this over (ret < 0) that is generally
used? I've seen it used to avoid the == vs. = typos, but not for other
comparisons.
Suggest sticking to what is commonly used i.e. ret < 0.
> + goto free_opp;
> +
> + cpu_dev = get_cpu_device(GOLD_LEAD);
Error check cpu_dev here?
> + ret = PTR_ERR_OR_ZERO(opp_temp =
> + dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
> + if (0 > ret)
> + goto free_opp;
> +
> +
> + ret = PTR_ERR_OR_ZERO(platform_device_register_simple("cpufreq-dt",
> + -1, NULL, 0));
> +
> + if (0 == ret)
> + return 0;
> +
> +free_opp:
> + dev_pm_opp_put_supported_hw(opp_temp);
This is not needed because dev_pm_opp_set_supported_hw will free
memory in case of failure. This call in only needed in case of a
successful get.
> +
> +free_np:
> + of_node_put(np);
> + return ret;
Suggest something like this instead:
.
.
opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
if (IS_ERR(opp_temp)) {
dev_err(cpu_dev, "Failed to set supported hardware\n");
ret = PTR_ERR(opp_temp);
goto free_np;
}
cpu_dev = get_cpu_device(GOLD_LEAD);
opp_temp = dev_pm_opp_set_supported_hw(cpu_dev,&versions,1));
if (IS_ERR(opp_temp)) {
dev_err(cpu_dev, "Failed to set supported hardware\n");
ret = PTR_ERR(opp_temp);
goto free_np;
}
ret = platform_device_register_simple("cpufreq-dt", -1, NULL, 0));
if (!IS_ERR_OR_NULL(ret))
goto out;
free_np:
of_node_put(np);
out:
return ret;
> +}
> +late_initcall(qcom_cpufreq_kryo_driver_init);
> +
> +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Kryo CPUfreq driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v7 14/14] dt: qcom: Add qcom-cpufreq-kryo driver configuration
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526375616-16904-15-git-send-email-ilialin@codeaurora.org>
2018-05-15 12:13 GMT+03:00 Ilia Lin <ilialin@codeaurora.org>:
No commit message?
Perhaps something listing the different hw types?
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 311 +++++++++++++++++++++++++++-
> 2 files changed, 310 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> index 230e9c8..da23bda 100644
> --- a/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> +++ b/arch/arm64/boot/dts/qcom/apq8096-db820c.dts
> @@ -17,5 +17,5 @@
>
> / {
> model = "Qualcomm Technologies, Inc. DB820c";
> - compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc";
> + compatible = "arrow,apq8096-db820c", "qcom,apq8096-sbc", "qcom,apq8096";
> };
> diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> index d7adef9..1dedfb8 100644
> --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
> @@ -174,218 +174,520 @@
> };
>
> cluster0_opp: opp_table0 {
> - compatible = "operating-points-v2";
> + compatible = "operating-points-v2-kryo-cpu",
> + "operating-points-v2";
> + nvmem-cells = <&speedbin_efuse>;
> opp-shared;
>
> opp-307200000 {
> opp-hz = /bits/ 64 <307200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-422400000 {
> opp-hz = /bits/ 64 <422400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-480000000 {
> opp-hz = /bits/ 64 <480000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-556800000 {
> opp-hz = /bits/ 64 <556800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-652800000 {
> opp-hz = /bits/ 64 <652800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-729600000 {
> opp-hz = /bits/ 64 <729600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-768000000 {
> + opp-hz = /bits/ 64 <768000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-844800000 {
> opp-hz = /bits/ 64 <844800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-960000000 {
> opp-hz = /bits/ 64 <960000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1036800000 {
> opp-hz = /bits/ 64 <1036800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1113600000 {
> opp-hz = /bits/ 64 <1113600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1190400000 {
> opp-hz = /bits/ 64 <1190400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1228800000 {
> opp-hz = /bits/ 64 <1228800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1324800000 {
> opp-hz = /bits/ 64 <1324800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x72>;
> clock-latency-ns = <200000>;
> };
> opp-1401600000 {
> opp-hz = /bits/ 64 <1401600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1478400000 {
> opp-hz = /bits/ 64 <1478400000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1497600000 {
> + opp-hz = /bits/ 64 <1497600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x4>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1593600000 {
> opp-hz = /bits/ 64 <1593600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1996800000 {
> + opp-hz = /bits/ 64 <1996800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x20>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2188800000 {
> + opp-hz = /bits/ 64 <2188800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> clock-latency-ns = <200000>;
> };
> };
>
> cluster1_opp: opp_table1 {
> - compatible = "operating-points-v2";
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> opp-shared;
>
> opp-307200000 {
> opp-hz = /bits/ 64 <307200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-403200000 {
> opp-hz = /bits/ 64 <403200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-480000000 {
> opp-hz = /bits/ 64 <480000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-556800000 {
> opp-hz = /bits/ 64 <556800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-652800000 {
> opp-hz = /bits/ 64 <652800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-729600000 {
> opp-hz = /bits/ 64 <729600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-748800000 {
> + opp-hz = /bits/ 64 <748800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-806400000 {
> opp-hz = /bits/ 64 <806400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-825600000 {
> + opp-hz = /bits/ 64 <825600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-883200000 {
> opp-hz = /bits/ 64 <883200000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-940800000 {
> opp-hz = /bits/ 64 <940800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1036800000 {
> opp-hz = /bits/ 64 <1036800000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1113600000 {
> opp-hz = /bits/ 64 <1113600000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1190400000 {
> opp-hz = /bits/ 64 <1190400000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1248000000 {
> opp-hz = /bits/ 64 <1248000000>;
> opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1324800000 {
> opp-hz = /bits/ 64 <1324800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1401600000 {
> opp-hz = /bits/ 64 <1401600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1478400000 {
> opp-hz = /bits/ 64 <1478400000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1555200000 {
> opp-hz = /bits/ 64 <1555200000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1632000000 {
> opp-hz = /bits/ 64 <1632000000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1670400000 {
> + opp-hz = /bits/ 64 <1670400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1708800000 {
> opp-hz = /bits/ 64 <1708800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1747200000 {
> + opp-hz = /bits/ 64 <1747200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> clock-latency-ns = <200000>;
> };
> opp-1785600000 {
> opp-hz = /bits/ 64 <1785600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1804800000 {
> + opp-hz = /bits/ 64 <1804800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x6>;
> clock-latency-ns = <200000>;
> };
> opp-1824000000 {
> opp-hz = /bits/ 64 <1824000000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1900800000 {
> + opp-hz = /bits/ 64 <1900800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x74>;
> clock-latency-ns = <200000>;
> };
> opp-1920000000 {
> opp-hz = /bits/ 64 <1920000000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1977600000 {
> + opp-hz = /bits/ 64 <1977600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> clock-latency-ns = <200000>;
> };
> opp-1996800000 {
> opp-hz = /bits/ 64 <1996800000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2054400000 {
> + opp-hz = /bits/ 64 <2054400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> clock-latency-ns = <200000>;
> };
> opp-2073600000 {
> opp-hz = /bits/ 64 <2073600000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> clock-latency-ns = <200000>;
> };
> opp-2150400000 {
> opp-hz = /bits/ 64 <2150400000>;
> opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x31>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2246400000 {
> + opp-hz = /bits/ 64 <2246400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2342400000 {
> + opp-hz = /bits/ 64 <2342400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> clock-latency-ns = <200000>;
> };
> };
> @@ -992,6 +1294,11 @@
> reg = <0x24f 0x1>;
> bits = <1 4>;
> };
> +
> + speedbin_efuse: speedbin at 133 {
> + reg = <0x133 0x1>;
> + bits = <5 3>;
> + };
> };
>
> phy at 34000 {
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v7 13/14] dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526375616-16904-14-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> that have KRYO processors, the CPU ferequencies subset and voltage value
s/ferequencies/frequency
> of each OPP varies based on the silicon variant in use.
> Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> defines the voltage and frequency value based on the msm-id in SMEM
> and speedbin blown in the efuse combination.
> The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> to provide the OPP framework with required information.
> This is used to determine the voltage and frequency value for each OPP of
> operating-points-v2 table when it is parsed by the OPP framework.
>
> This change adds documentation.
Change this to actually document the extension of the op-v2 binding
with a list of compatible HW.
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
> ---
> .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 +++++++++++++++++++++
> 1 file changed, 680 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
>
> diff --git a/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> new file mode 100644
> index 0000000..c2127b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> @@ -0,0 +1,680 @@
> +Qualcomm Technologies, Inc. KRYO CPUFreq and OPP bindings
> +===================================
> +
> +In Certain Qualcomm Technologies, Inc. SoCs like apq8096 and msm8996
> +that have KRYO processors, the CPU ferequencies subset and voltage value
> +of each OPP varies based on the silicon variant in use.
> +Qualcomm Technologies, Inc. Process Voltage Scaling Tables
> +defines the voltage and frequency value based on the msm-id in SMEM
> +and speedbin blown in the efuse combination.
> +The qcom-cpufreq-kryo driver reads the msm-id and efuse value from the SoC
> +to provide the OPP framework with required information (existing HW bitmap).
> +This is used to determine the voltage and frequency value for each OPP of
> +operating-points-v2 table when it is parsed by the OPP framework.
> +
> +Required properties:
> +--------------------
> +In 'cpus' nodes:
> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
> +
> +In 'operating-points-v2' table:
> +- compatible: Should be
> + - 'operating-points-v2-kryo-cpu' for apq8096 and msm8996.
> +- nvmem-cells: A phandle pointing to a nvmem-cells node representing the
> + efuse registers that has information about the
> + speedbin that is used to select the right frequency/voltage
> + value pair.
> + Please refer the for nvmem-cells
> + bindings Documentation/devicetree/bindings/nvmem/nvmem.txt
> + and also examples below.
> +
> +In every OPP node:
> +- opp-supported-hw: A single 32 bit bitmap value, representing compatible HW.
> + Bitmap:
> + 0: MSM8996 V3, speedbin 0
> + 1: MSM8996 V3, speedbin 1
> + 2: MSM8996 V3, speedbin 2
> + 3: unused
> + 4: MSM8996 SG, speedbin 0
> + 5: MSM8996 SG, speedbin 1
> + 6: MSM8996 SG, speedbin 2
> + 7-31: unused
> +
> +Example 1:
> +---------
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + clocks = <&kryocc 0>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster0_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_0>;
> + L2_0: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + clocks = <&kryocc 0>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster0_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_0>;
> + };
> +
> + CPU2: cpu at 100 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x100>;
> + enable-method = "psci";
> + clocks = <&kryocc 1>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster1_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_1>;
> + L2_1: l2-cache {
> + compatible = "cache";
> + cache-level = <2>;
> + };
> + };
> +
> + CPU3: cpu at 101 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0x0 0x101>;
> + enable-method = "psci";
> + clocks = <&kryocc 1>;
> + cpu-supply = <&pm8994_s11_saw>;
> + operating-points-v2 = <&cluster1_opp>;
> + #cooling-cells = <2>;
> + next-level-cache = <&L2_1>;
> + };
> +
> + cpu-map {
> + cluster0 {
> + core0 {
> + cpu = <&CPU0>;
> + };
> +
> + core1 {
> + cpu = <&CPU1>;
> + };
> + };
> +
> + cluster1 {
> + core0 {
> + cpu = <&CPU2>;
> + };
> +
> + core1 {
> + cpu = <&CPU3>;
> + };
> + };
> + };
> + };
> +
> + cluster0_opp: opp_table0 {
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> + opp-shared;
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-422400000 {
> + opp-hz = /bits/ 64 <422400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-556800000 {
> + opp-hz = /bits/ 64 <556800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-652800000 {
> + opp-hz = /bits/ 64 <652800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-768000000 {
> + opp-hz = /bits/ 64 <768000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-844800000 {
> + opp-hz = /bits/ 64 <844800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-960000000 {
> + opp-hz = /bits/ 64 <960000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1036800000 {
> + opp-hz = /bits/ 64 <1036800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1190400000 {
> + opp-hz = /bits/ 64 <1190400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1228800000 {
> + opp-hz = /bits/ 64 <1228800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1324800000 {
> + opp-hz = /bits/ 64 <1324800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x72>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x5>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1478400000 {
> + opp-hz = /bits/ 64 <1478400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1497600000 {
> + opp-hz = /bits/ 64 <1497600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x4>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1996800000 {
> + opp-hz = /bits/ 64 <1996800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x20>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2188800000 {
> + opp-hz = /bits/ 64 <2188800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> + cluster1_opp: opp_table1 {
> + compatible = "operating-points-v2-kryo-cpu";
> + nvmem-cells = <&speedbin_efuse>;
> + opp-shared;
> +
> + opp-307200000 {
> + opp-hz = /bits/ 64 <307200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x77>;
> + clock-latency-ns = <200000>;
> + };
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-403200000 {
> + opp-hz = /bits/ 64 <403200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-460800000 {
> + opp-hz = /bits/ 64 <460800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-480000000 {
> + opp-hz = /bits/ 64 <480000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-537600000 {
> + opp-hz = /bits/ 64 <537600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-556800000 {
> + opp-hz = /bits/ 64 <556800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-614400000 {
> + opp-hz = /bits/ 64 <614400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-652800000 {
> + opp-hz = /bits/ 64 <652800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-691200000 {
> + opp-hz = /bits/ 64 <691200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-729600000 {
> + opp-hz = /bits/ 64 <729600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-748800000 {
> + opp-hz = /bits/ 64 <748800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-806400000 {
> + opp-hz = /bits/ 64 <806400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-825600000 {
> + opp-hz = /bits/ 64 <825600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-883200000 {
> + opp-hz = /bits/ 64 <883200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-902400000 {
> + opp-hz = /bits/ 64 <902400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-940800000 {
> + opp-hz = /bits/ 64 <940800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-979200000 {
> + opp-hz = /bits/ 64 <979200000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1036800000 {
> + opp-hz = /bits/ 64 <1036800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1056000000 {
> + opp-hz = /bits/ 64 <1056000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1113600000 {
> + opp-hz = /bits/ 64 <1113600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1132800000 {
> + opp-hz = /bits/ 64 <1132800000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1190400000 {
> + opp-hz = /bits/ 64 <1190400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1209600000 {
> + opp-hz = /bits/ 64 <1209600000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1248000000 {
> + opp-hz = /bits/ 64 <1248000000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1286400000 {
> + opp-hz = /bits/ 64 <1286400000>;
> + opp-microvolt = <905000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1324800000 {
> + opp-hz = /bits/ 64 <1324800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1363200000 {
> + opp-hz = /bits/ 64 <1363200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1401600000 {
> + opp-hz = /bits/ 64 <1401600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1440000000 {
> + opp-hz = /bits/ 64 <1440000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1478400000 {
> + opp-hz = /bits/ 64 <1478400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1516800000 {
> + opp-hz = /bits/ 64 <1516800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1555200000 {
> + opp-hz = /bits/ 64 <1555200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1593600000 {
> + opp-hz = /bits/ 64 <1593600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1632000000 {
> + opp-hz = /bits/ 64 <1632000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1670400000 {
> + opp-hz = /bits/ 64 <1670400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1708800000 {
> + opp-hz = /bits/ 64 <1708800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1747200000 {
> + opp-hz = /bits/ 64 <1747200000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x70>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1785600000 {
> + opp-hz = /bits/ 64 <1785600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x7>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1804800000 {
> + opp-hz = /bits/ 64 <1804800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x6>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1824000000 {
> + opp-hz = /bits/ 64 <1824000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x71>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1900800000 {
> + opp-hz = /bits/ 64 <1900800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x74>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1920000000 {
> + opp-hz = /bits/ 64 <1920000000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1977600000 {
> + opp-hz = /bits/ 64 <1977600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> + clock-latency-ns = <200000>;
> + };
> + opp-1996800000 {
> + opp-hz = /bits/ 64 <1996800000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2054400000 {
> + opp-hz = /bits/ 64 <2054400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x30>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2073600000 {
> + opp-hz = /bits/ 64 <2073600000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x1>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2150400000 {
> + opp-hz = /bits/ 64 <2150400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x31>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2246400000 {
> + opp-hz = /bits/ 64 <2246400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + opp-2342400000 {
> + opp-hz = /bits/ 64 <2342400000>;
> + opp-microvolt = <1140000 905000 1140000>;
> + opp-supported-hw = <0x10>;
> + clock-latency-ns = <200000>;
> + };
> + };
> +
> +....
> +
> +reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +....
> + smem_mem: smem-mem at 86000000 {
> + reg = <0x0 0x86000000 0x0 0x200000>;
> + no-map;
> + };
> +....
> +};
> +
> +smem {
> + compatible = "qcom,smem";
> + memory-region = <&smem_mem>;
> + hwlocks = <&tcsr_mutex 3>;
> +};
> +
> +soc {
> +....
> + qfprom: qfprom at 74000 {
> + compatible = "qcom,qfprom";
> + reg = <0x00074000 0x8ff>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ....
> + speedbin_efuse: speedbin at 133 {
> + reg = <0x133 0x1>;
> + bits = <5 3>;
> + };
> + };
> +};
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v7 01/14] soc: qcom: Separate kryo l2 accessors from PMU driver
From: Amit Kucheria @ 2018-05-16 13:12 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526375616-16904-2-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> The driver provides kernel level API for other drivers
> to access the MSM8996 L2 cache registers.
> Separating the L2 access code from the PMU driver and
> making it public to allow other drivers use it.
> The accesses must be separated with a single spinlock,
> maintained in this driver.
>
> Signed-off-by: Ilia Lin <ilialin@codeaurora.org>
> ---
> drivers/perf/Kconfig | 1 +
> drivers/perf/qcom_l2_pmu.c | 90 ++++++++++--------------------------
> drivers/soc/qcom/Kconfig | 3 ++
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/kryo-l2-accessors.c | 65 ++++++++++++++++++++++++++
> include/soc/qcom/kryo-l2-accessors.h | 21 +++++++++
> 6 files changed, 115 insertions(+), 66 deletions(-)
> create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c
> create mode 100644 include/soc/qcom/kryo-l2-accessors.h
>
> diff --git a/drivers/perf/Kconfig b/drivers/perf/Kconfig
> index 28bb5a0..561252a 100644
> --- a/drivers/perf/Kconfig
> +++ b/drivers/perf/Kconfig
> @@ -69,6 +69,7 @@ config HISI_PMU
> config QCOM_L2_PMU
> bool "Qualcomm Technologies L2-cache PMU"
> depends on ARCH_QCOM && ARM64 && ACPI
> + select QCOM_KRYO_L2_ACCESSORS
> help
> Provides support for the L2 cache performance monitor unit (PMU)
> in Qualcomm Technologies processors.
> diff --git a/drivers/perf/qcom_l2_pmu.c b/drivers/perf/qcom_l2_pmu.c
> index 842135c..cc31f51 100644
> --- a/drivers/perf/qcom_l2_pmu.c
> +++ b/drivers/perf/qcom_l2_pmu.c
> @@ -31,6 +31,7 @@
> #include <asm/barrier.h>
> #include <asm/local64.h>
> #include <asm/sysreg.h>
> +#include <soc/qcom/kryo-l2-accessors.h>
>
> #define MAX_L2_CTRS 9
>
> @@ -87,8 +88,6 @@
> #define L2_COUNTER_RELOAD BIT_ULL(31)
> #define L2_CYCLE_COUNTER_RELOAD BIT_ULL(63)
>
> -#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6)
> -#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
>
> #define reg_idx(reg, i) (((i) * IA_L2_REG_OFFSET) + reg##_BASE)
>
> @@ -107,48 +106,7 @@
> #define L2_EVENT_STREX 0x421
> #define L2_EVENT_CLREX 0x422
>
> -static DEFINE_RAW_SPINLOCK(l2_access_lock);
>
> -/**
> - * set_l2_indirect_reg: write value to an L2 register
> - * @reg: Address of L2 register.
> - * @value: Value to be written to register.
> - *
> - * Use architecturally required barriers for ordering between system register
> - * accesses
> - */
> -static void set_l2_indirect_reg(u64 reg, u64 val)
> -{
> - unsigned long flags;
> -
> - raw_spin_lock_irqsave(&l2_access_lock, flags);
> - write_sysreg_s(reg, L2CPUSRSELR_EL1);
> - isb();
> - write_sysreg_s(val, L2CPUSRDR_EL1);
> - isb();
> - raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> -}
> -
> -/**
> - * get_l2_indirect_reg: read an L2 register value
> - * @reg: Address of L2 register.
> - *
> - * Use architecturally required barriers for ordering between system register
> - * accesses
> - */
> -static u64 get_l2_indirect_reg(u64 reg)
> -{
> - u64 val;
> - unsigned long flags;
> -
> - raw_spin_lock_irqsave(&l2_access_lock, flags);
> - write_sysreg_s(reg, L2CPUSRSELR_EL1);
> - isb();
> - val = read_sysreg_s(L2CPUSRDR_EL1);
> - raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> -
> - return val;
> -}
>
> struct cluster_pmu;
>
> @@ -219,28 +177,28 @@ static inline struct cluster_pmu *get_cluster_pmu(
> static void cluster_pmu_reset(void)
> {
> /* Reset all counters */
> - set_l2_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
> - set_l2_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask);
> - set_l2_indirect_reg(L2PMINTENCLR, l2_counter_present_mask);
> - set_l2_indirect_reg(L2PMOVSCLR, l2_counter_present_mask);
> + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_RESET_ALL);
> + kryo_l2_set_indirect_reg(L2PMCNTENCLR, l2_counter_present_mask);
> + kryo_l2_set_indirect_reg(L2PMINTENCLR, l2_counter_present_mask);
> + kryo_l2_set_indirect_reg(L2PMOVSCLR, l2_counter_present_mask);
> }
>
> static inline void cluster_pmu_enable(void)
> {
> - set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE);
> + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_ENABLE);
> }
>
> static inline void cluster_pmu_disable(void)
> {
> - set_l2_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE);
> + kryo_l2_set_indirect_reg(L2PMCR, L2PMCR_COUNTERS_DISABLE);
> }
>
> static inline void cluster_pmu_counter_set_value(u32 idx, u64 value)
> {
> if (idx == l2_cycle_ctr_idx)
> - set_l2_indirect_reg(L2PMCCNTR, value);
> + kryo_l2_set_indirect_reg(L2PMCCNTR, value);
> else
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx), value);
> }
>
> static inline u64 cluster_pmu_counter_get_value(u32 idx)
> @@ -248,46 +206,46 @@ static inline u64 cluster_pmu_counter_get_value(u32 idx)
> u64 value;
>
> if (idx == l2_cycle_ctr_idx)
> - value = get_l2_indirect_reg(L2PMCCNTR);
> + value = kryo_l2_get_indirect_reg(L2PMCCNTR);
> else
> - value = get_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx));
> + value = kryo_l2_get_indirect_reg(reg_idx(IA_L2PMXEVCNTR, idx));
>
> return value;
> }
>
> static inline void cluster_pmu_counter_enable(u32 idx)
> {
> - set_l2_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMCNTENSET, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_counter_disable(u32 idx)
> {
> - set_l2_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMCNTENCLR, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_counter_enable_interrupt(u32 idx)
> {
> - set_l2_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMINTENSET, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_counter_disable_interrupt(u32 idx)
> {
> - set_l2_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx));
> + kryo_l2_set_indirect_reg(L2PMINTENCLR, idx_to_reg_bit(idx));
> }
>
> static inline void cluster_pmu_set_evccntcr(u32 val)
> {
> - set_l2_indirect_reg(L2PMCCNTCR, val);
> + kryo_l2_set_indirect_reg(L2PMCCNTCR, val);
> }
>
> static inline void cluster_pmu_set_evcntcr(u32 ctr, u32 val)
> {
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVCNTCR, ctr), val);
> }
>
> static inline void cluster_pmu_set_evtyper(u32 ctr, u32 val)
> {
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVTYPER, ctr), val);
> }
>
> static void cluster_pmu_set_resr(struct cluster_pmu *cluster,
> @@ -303,11 +261,11 @@ static void cluster_pmu_set_resr(struct cluster_pmu *cluster,
>
> spin_lock_irqsave(&cluster->pmu_lock, flags);
>
> - resr_val = get_l2_indirect_reg(L2PMRESR);
> + resr_val = kryo_l2_get_indirect_reg(L2PMRESR);
> resr_val &= ~(L2PMRESR_GROUP_MASK << shift);
> resr_val |= field;
> resr_val |= L2PMRESR_EN;
> - set_l2_indirect_reg(L2PMRESR, resr_val);
> + kryo_l2_set_indirect_reg(L2PMRESR, resr_val);
>
> spin_unlock_irqrestore(&cluster->pmu_lock, flags);
> }
> @@ -323,14 +281,14 @@ static inline void cluster_pmu_set_evfilter_sys_mode(u32 ctr)
> L2PMXEVFILTER_ORGFILTER_IDINDEP |
> L2PMXEVFILTER_ORGFILTER_ALL;
>
> - set_l2_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val);
> + kryo_l2_set_indirect_reg(reg_idx(IA_L2PMXEVFILTER, ctr), val);
> }
>
> static inline u32 cluster_pmu_getreset_ovsr(void)
> {
> - u32 result = get_l2_indirect_reg(L2PMOVSSET);
> + u32 result = kryo_l2_get_indirect_reg(L2PMOVSSET);
>
> - set_l2_indirect_reg(L2PMOVSCLR, result);
> + kryo_l2_set_indirect_reg(L2PMOVSCLR, result);
> return result;
> }
>
> @@ -783,7 +741,7 @@ static int get_num_counters(void)
> {
> int val;
>
> - val = get_l2_indirect_reg(L2PMCR);
> + val = kryo_l2_get_indirect_reg(L2PMCR);
>
> /*
> * Read number of counters from L2PMCR and add 1
> diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
> index 7093fe7..0567dff 100644
> --- a/drivers/soc/qcom/Kconfig
> +++ b/drivers/soc/qcom/Kconfig
> @@ -39,6 +39,9 @@ config QCOM_GSBI
> functions for connecting the underlying serial UART, SPI, and I2C
> devices to the output pins.
>
> +config QCOM_KRYO_L2_ACCESSORS
> + bool
> +
> config QCOM_MDT_LOADER
> tristate
> select QCOM_SCM
> diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> index cbf414c..e4d3f5a 100644
> --- a/drivers/soc/qcom/Makefile
> +++ b/drivers/soc/qcom/Makefile
> @@ -14,3 +14,4 @@ obj-$(CONFIG_QCOM_SMEM_STATE) += smem_state.o
> obj-$(CONFIG_QCOM_SMP2P) += smp2p.o
> obj-$(CONFIG_QCOM_SMSM) += smsm.o
> obj-$(CONFIG_QCOM_WCNSS_CTRL) += wcnss_ctrl.o
> +obj-$(CONFIG_QCOM_KRYO_L2_ACCESSORS) += kryo-l2-accessors.o
> diff --git a/drivers/soc/qcom/kryo-l2-accessors.c b/drivers/soc/qcom/kryo-l2-accessors.c
> new file mode 100644
> index 0000000..d35a860
> --- /dev/null
> +++ b/drivers/soc/qcom/kryo-l2-accessors.c
> @@ -0,0 +1,65 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (c) 2014-2015, 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
Get rid of the GPL boilerplate i.e. everything after the Copyright
line. You only need the SPDX line at the top.
> +#include <linux/spinlock.h>
> +#include <asm/sysreg.h>
> +#include <soc/qcom/kryo-l2-accessors.h>
> +
> +#define L2CPUSRSELR_EL1 sys_reg(3, 3, 15, 0, 6)
> +#define L2CPUSRDR_EL1 sys_reg(3, 3, 15, 0, 7)
> +
> +static DEFINE_RAW_SPINLOCK(l2_access_lock);
> +
> +/**
> + * kryo_l2_set_indirect_reg() - write value to an L2 register
> + * @reg: Address of L2 register.
> + * @value: Value to be written to register.
> + *
> + * Use architecturally required barriers for ordering between system register
> + * accesses, and system registers with respect to device memory
> + */
> +void kryo_l2_set_indirect_reg(u64 reg, u64 val)
> +{
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&l2_access_lock, flags);
> + write_sysreg_s(reg, L2CPUSRSELR_EL1);
> + isb();
> + write_sysreg_s(val, L2CPUSRDR_EL1);
> + isb();
> + raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> +}
> +EXPORT_SYMBOL(kryo_l2_set_indirect_reg);
> +
> +/**
> + * kryo_l2_get_indirect_reg() - read an L2 register value
> + * @reg: Address of L2 register.
> + *
> + * Use architecturally required barriers for ordering between system register
> + * accesses, and system registers with respect to device memory
> + */
> +u64 kryo_l2_get_indirect_reg(u64 reg)
> +{
> + u64 val;
> + unsigned long flags;
> +
> + raw_spin_lock_irqsave(&l2_access_lock, flags);
> + write_sysreg_s(reg, L2CPUSRSELR_EL1);
> + isb();
> + val = read_sysreg_s(L2CPUSRDR_EL1);
> + raw_spin_unlock_irqrestore(&l2_access_lock, flags);
> +
> + return val;
> +}
> +EXPORT_SYMBOL(kryo_l2_get_indirect_reg);
> diff --git a/include/soc/qcom/kryo-l2-accessors.h b/include/soc/qcom/kryo-l2-accessors.h
> new file mode 100644
> index 0000000..0840e87
> --- /dev/null
> +++ b/include/soc/qcom/kryo-l2-accessors.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (c) 2018, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
Get rid of the GPL boilerplate i.e. everything after the Copyright
line. You only need the SPDX line at the top.
> +#ifndef __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
> +#define __SOC_ARCH_QCOM_KRYO_L2_ACCESSORS_H
> +
> +void kryo_l2_set_indirect_reg(u64 reg, u64 val);
> +u64 kryo_l2_get_indirect_reg(u64 reg);
> +
> +#endif
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH v7 00/14] CPU scaling support for msm8996
From: Amit Kucheria @ 2018-05-16 13:11 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526375616-16904-1-git-send-email-ilialin@codeaurora.org>
On Tue, May 15, 2018 at 12:13 PM, Ilia Lin <ilialin@codeaurora.org> wrote:
> [v7]
> * Addressed comments from Viresh about resourses deallocation
> and DT compatible
Hi Ilia,
Thanks for working on this series. Here a few comments regarding the
series as a whole.
- The series could use a better cover letter describing how the
various patches are grouped. e.g. 1-7 are clock related and probably
will get merged through the clk maintainers tree. The regulator bits
might get merged through the regulator maintainer tree and so forth.
If there are any dependencies, please outline those as well so
maintainers can decide how best to merge this.
- Please describe what features this series adds - just frequency
scaling or more. Please describe in more detail what the dependency on
the SAW regulator changes is.
- Please get rid of the GPL boiler plate since you already have the
SPDX tags. See comments on patch 1 for what I'm referring to.
- You also mention that ACD is not implemented in the earlier patches
and then there is a patch that seems to add ACD related features
(7/14).
A few other comments follow across the individual patches.
Regards,
Amit
> [v6]
> * Addressed comments from Viresh about:
> ** Comments style
> ** Kconfig bool instead of tristate
> ** DT and documentation style
> ** Resourses deallocation on an error
> ** Typos
>
> [v5]
> * Rebased
> * Addressed comments from Bjorn about SPDX style,
> functions and parameters naming
> * Addressed comments from Viresh DT properties and style, comments style,
> resourses deallocation, documentation placement
> * Addressed comments from Sricharan about unnessesary include
> * Addressed comments from Nicolas
> * Addressed comments from Rob about the commit messages and acks
> * Addressed comments from Mark
>
> [v4]
> * Adressed all comments from Stephen
> * Added CPU regulator support
> * Added qcom-cpufreq-kryo driver
>
> [v3]
> * Rebased on top of the latest PLL driver changes
> * Addressed comment from Rob Herring for bindings
>
> [v2]
> * Addressed comments from Rob Herring for bindings
> * Addressed comments from Mark Rutland for memory barrier
> * Addressed comments from Julien Thierry for clock reenabling condition
> * Tuned the HW configuration for clock frequencies below 600MHz
>
> Clocks:
> This series adds support for the CPU clocks on msm8996 devices.
> The driver uses the existing PLL drivers and is required to control
> the CPU frequency scaling on the MSM8996.
>
> Regulators:
> Added SAW regulator support to the SPMI regulator driver. The SAW regulators
> will be controlled through special CPU registers instead of direct
> SPMI accesses.
>
> Cpufreq:
> The qcom-cpufreq-kryo driver is aimed to support different SOC versions.
> The driver reads eFuse information and chooses the required OPP subset
> by passing the OPP supported-hw parameter.
>
> A previous post of RFC can be found here:
> https://patchwork.kernel.org/patch/10398455/
>
> Ilia Lin (11):
> soc: qcom: Separate kryo l2 accessors from PMU driver
> clk: qcom: Add CPU clock driver for msm8996
> clk: qcom: Add DT bindings for CPU clock driver for msm8996
> clk: qcom: Add ACD path to CPU clock driver for msm8996
> dt: qcom: Add opp and thermal to the msm8996
> regulator: qcom_spmi: Add support for SAW
> dt-bindings: qcom_spmi: Add support for SAW documentation
> dt: qcom: Add SAW regulator for 8x96 CPUs
> cpufreq: Add Kryo CPU scaling driver
> dt-bindings: cpufreq: Document operating-points-v2-kryo-cpu
> dt: qcom: Add qcom-cpufreq-kryo driver configuration
>
> Rajendra Nayak (3):
> clk: qcom: Make clk_alpha_pll_configure available to modules
> clk: qcom: cpu-8996: Add support to switch to alternate PLL
> clk: qcom: cpu-8996: Add support to switch below 600Mhz
>
> .../devicetree/bindings/clock/qcom,kryocc.txt | 17 +
> .../devicetree/bindings/opp/kryo-cpufreq.txt | 680 +++++++++++++++++++++
> .../bindings/regulator/qcom,spmi-regulator.txt | 45 ++
> arch/arm64/boot/dts/qcom/apq8096-db820c.dts | 2 +-
> arch/arm64/boot/dts/qcom/msm8996.dtsi | 651 +++++++++++++++++++-
> drivers/clk/clk-fixed-factor.c | 2 +-
> drivers/clk/qcom/Kconfig | 9 +
> drivers/clk/qcom/Makefile | 1 +
> drivers/clk/qcom/clk-alpha-pll.c | 1 +
> drivers/clk/qcom/clk-alpha-pll.h | 6 +
> drivers/clk/qcom/clk-cpu-8996.c | 519 ++++++++++++++++
> drivers/cpufreq/Kconfig.arm | 11 +
> drivers/cpufreq/Makefile | 1 +
> drivers/cpufreq/cpufreq-dt-platdev.c | 3 +
> drivers/cpufreq/qcom-cpufreq-kryo.c | 150 +++++
> drivers/perf/Kconfig | 1 +
> drivers/perf/qcom_l2_pmu.c | 90 +--
> drivers/regulator/qcom_spmi-regulator.c | 133 +++-
> drivers/soc/qcom/Kconfig | 3 +
> drivers/soc/qcom/Makefile | 1 +
> drivers/soc/qcom/kryo-l2-accessors.c | 65 ++
> include/soc/qcom/kryo-l2-accessors.h | 21 +
> 22 files changed, 2332 insertions(+), 80 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,kryocc.txt
> create mode 100644 Documentation/devicetree/bindings/opp/kryo-cpufreq.txt
> create mode 100644 drivers/clk/qcom/clk-cpu-8996.c
> create mode 100644 drivers/cpufreq/qcom-cpufreq-kryo.c
> create mode 100644 drivers/soc/qcom/kryo-l2-accessors.c
> create mode 100644 include/soc/qcom/kryo-l2-accessors.h
>
> --
> 1.9.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-arm-msm" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 14/14] mm: turn on vm_fault_t type checking
From: Christoph Hellwig @ 2018-05-16 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516112813.GC20670@bombadil.infradead.org>
On Wed, May 16, 2018 at 04:28:13AM -0700, Matthew Wilcox wrote:
> On Wed, May 16, 2018 at 07:43:48AM +0200, Christoph Hellwig wrote:
> > Switch vm_fault_t to point to an unsigned int with __b?twise annotations.
> > This both catches any old ->fault or ->page_mkwrite instance with plain
> > compiler type checking, as well as finding more intricate problems with
> > sparse.
>
> Come on, Christoph; you know better than this. This patch is completely
> unreviewable. Split it into one patch per maintainer tree, and in any
> event, the patch to convert vm_fault_t to an unsigned int should be
> separated from all the trivial conversions.
The whole point is that tiny split patches for mechnical translations
are totally pointless. Switching the typedef might be worth splitting
if people really insist.
^ permalink raw reply
* vm_fault_t conversion, for real
From: Christoph Hellwig @ 2018-05-16 13:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516112347.GB20670@bombadil.infradead.org>
On Wed, May 16, 2018 at 04:23:47AM -0700, Matthew Wilcox wrote:
> On Wed, May 16, 2018 at 07:43:34AM +0200, Christoph Hellwig wrote:
> > this series tries to actually turn vm_fault_t into a type that can be
> > typechecked and checks the fallout instead of sprinkling random
> > annotations without context.
>
> Yes, why should we have small tasks that newcomers can do when the mighty
> Christoph Hellwig can swoop in and take over from them? Seriously,
> can't your talents find a better use than this?
I've spent less time on this than trying to argue to you and Souptick
that these changes are only to get ignored and yelled at as an
"asshole maintainer". So yes, I could have done more productive things
if you hadn't forced this escalation.
^ permalink raw reply
* [PATCH 10/14] vgem: separate errno from VM_FAULT_* values
From: Christoph Hellwig @ 2018-05-16 13:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516095303.GH3438@phenom.ffwll.local>
On Wed, May 16, 2018 at 11:53:03AM +0200, Daniel Vetter wrote:
> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
>
> Want me to merge this through drm-misc or plan to pick it up yourself?
For now I just want a honest discussion if people really actually
want the vm_fault_t change with the whole picture in place.
^ permalink raw reply
* [PATCH -next] gpio: Fix return value check in owl_gpio_probe()
From: Linus Walleij @ 2018-05-16 12:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525657224-88189-1-git-send-email-weiyongjun1@huawei.com>
On Mon, May 7, 2018 at 3:40 AM, Wei Yongjun <weiyongjun1@huawei.com> wrote:
> In case of error, the function of_iomap() returns NULL pointer not
> ERR_PTR(). The IS_ERR() test in the return value check should be
> replaced with NULL test.
>
> Fixes: d3654d38809c ("gpio: Add gpio driver for Actions OWL S900 SoC")
> Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com>
We dropped this driver from the GPIO tree in favor of an extended
pin control driver.
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] pinctrl: mvebu: use correct MPP sel value for dev pins
From: Linus Walleij @ 2018-05-16 12:55 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180507022555.31645-1-chris.packham@alliedtelesis.co.nz>
On Mon, May 7, 2018 at 4:25 AM, Chris Packham
<chris.packham@alliedtelesis.co.nz> wrote:
> The "dev" function is selected with the value 0x4 not 0x01.
>
> Fixes: commit d7ae8f8dee7f ("pinctrl: mvebu: pinctrl driver for 98DX3236 SoC")
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Patch applied.
Does it need to go into fixes? Stable?
Yours,
Linus Walleij
^ permalink raw reply
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