* [PATCH v4 08/12] ACPI / APEI: Split fixmap pages for arm64 NMI-like notifications
From: James Morse @ 2018-05-16 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516162829.14348-1-james.morse@arm.com>
Now that ghes uses the fixmap addresses and locks via some indirection
we can support multiple NMI-like notifications on arm64.
These should be named after their notification method. x86's
NOTIFY_NMI already is, move it to live with the ghes_nmi list.
Change the SEA fixmap entry to be called FIX_APEI_GHES_SEA.
Future patches can add support for FIX_APEI_GHES_SEI and
FIX_APEI_GHES_SDEI_{NORMAL,CRITICAL}.
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Punit Agrawal <punit.agrawal@arm.com>
Tested-by: Tyler Baicar <tbaicar@codeaurora.org>
---
Changes since v3:
* idx/lock are now in a separate struct.
* Add to the comment above ghes_fixmap_lock_irq so that it makes more
sense in isolation.
arch/arm64/include/asm/fixmap.h | 4 +++-
drivers/acpi/apei/ghes.c | 12 ++++++++----
2 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h
index ec1e6d6fa14c..c3974517c2cb 100644
--- a/arch/arm64/include/asm/fixmap.h
+++ b/arch/arm64/include/asm/fixmap.h
@@ -55,7 +55,9 @@ enum fixed_addresses {
#ifdef CONFIG_ACPI_APEI_GHES
/* Used for GHES mapping from assorted contexts */
FIX_APEI_GHES_IRQ,
- FIX_APEI_GHES_NMI,
+#ifdef CONFIG_ACPI_APEI_SEA
+ FIX_APEI_GHES_SEA,
+#endif
#endif /* CONFIG_ACPI_APEI_GHES */
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 13bb3bb94fbd..014966bdd0a7 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -117,8 +117,10 @@ static DEFINE_MUTEX(ghes_list_mutex);
* from BIOS to Linux can be determined only in NMI, IRQ or timer
* handler, but general ioremap can not be used in atomic context, so
* the fixmap is used instead.
+ * This lock protects access to the FIX_APEI_GHES_IRQ entry.
+ * NMI-like notifications use DEFINE_GHES_NMI_FIXMAP() to pair a fixmap
+ * entry and a lock.
*/
-static DEFINE_GHES_NMI_FIXMAP(nmi_fixmap, FIX_APEI_GHES_NMI);
static DEFINE_SPINLOCK(ghes_fixmap_lock_irq);
static struct gen_pool *ghes_estatus_pool;
@@ -948,6 +950,7 @@ static struct notifier_block ghes_notifier_hed = {
#ifdef CONFIG_ACPI_APEI_SEA
static LIST_HEAD(ghes_sea);
+static DEFINE_GHES_NMI_FIXMAP(sea_fixmap, FIX_APEI_GHES_SEA);
/*
* Return 0 only if one of the SEA error sources successfully reported an error
@@ -960,7 +963,7 @@ int ghes_notify_sea(void)
static void ghes_sea_add(struct ghes *ghes)
{
- ghes->nmi_fixmap = &nmi_fixmap;
+ ghes->nmi_fixmap = &sea_fixmap;
ghes_estatus_queue_grow_pool(ghes);
mutex_lock(&ghes_list_mutex);
@@ -984,12 +987,13 @@ static inline void ghes_sea_remove(struct ghes *ghes) { }
#ifdef CONFIG_HAVE_ACPI_APEI_NMI
/*
- * NMI may be triggered on any CPU, so ghes_in_nmi is used for
- * having only one concurrent reader.
+ * NOTIFY_NMI may be triggered on any CPU, so ghes_in_nmi is
+ * used for having only one concurrent reader.
*/
static atomic_t ghes_in_nmi = ATOMIC_INIT(0);
static LIST_HEAD(ghes_nmi);
+static DEFINE_GHES_NMI_FIXMAP(nmi_fixmap, FIX_APEI_GHES_NMI);
static int ghes_notify_nmi(unsigned int cmd, struct pt_regs *regs)
{
--
2.16.2
^ permalink raw reply related
* [PATCH v4 09/12] firmware: arm_sdei: Add ACPI GHES registration helper
From: James Morse @ 2018-05-16 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516162829.14348-1-james.morse@arm.com>
APEI's Generic Hardware Error Source structures do not describe
whether the SDEI event is shared or private, as this information is
discoverable via the API.
GHES needs to know whether an event is normal or critical to avoid
sharing locks or fixmap entries.
Add a helper to ask firmware for this information so it can initialise
the struct ghes and register then enable the event.
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Punit Agrawal <punit.agrawal@arm.com>
---
Changes since v3:
* Removed acpi_disabled() checks that aren't necessary after v2s #ifdef
change.
Changes since v2:
* Added header file, thanks kbuild-robot!
* changed ifdef to the GHES version to match the fixmap definition
Changes since v1:
* ghes->fixmap_idx variable rename
arch/arm64/include/asm/fixmap.h | 4 +++
drivers/firmware/arm_sdei.c | 67 +++++++++++++++++++++++++++++++++++++++++
include/linux/arm_sdei.h | 5 +++
3 files changed, 76 insertions(+)
diff --git a/arch/arm64/include/asm/fixmap.h b/arch/arm64/include/asm/fixmap.h
index c3974517c2cb..e2b423a5feaf 100644
--- a/arch/arm64/include/asm/fixmap.h
+++ b/arch/arm64/include/asm/fixmap.h
@@ -58,6 +58,10 @@ enum fixed_addresses {
#ifdef CONFIG_ACPI_APEI_SEA
FIX_APEI_GHES_SEA,
#endif
+#ifdef CONFIG_ARM_SDE_INTERFACE
+ FIX_APEI_GHES_SDEI_NORMAL,
+ FIX_APEI_GHES_SDEI_CRITICAL,
+#endif
#endif /* CONFIG_ACPI_APEI_GHES */
#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
diff --git a/drivers/firmware/arm_sdei.c b/drivers/firmware/arm_sdei.c
index 1ea71640fdc2..7c304ebb6282 100644
--- a/drivers/firmware/arm_sdei.c
+++ b/drivers/firmware/arm_sdei.c
@@ -2,6 +2,7 @@
// Copyright (C) 2017 Arm Ltd.
#define pr_fmt(fmt) "sdei: " fmt
+#include <acpi/ghes.h>
#include <linux/acpi.h>
#include <linux/arm_sdei.h>
#include <linux/arm-smccc.h>
@@ -32,6 +33,8 @@
#include <linux/spinlock.h>
#include <linux/uaccess.h>
+#include <asm/fixmap.h>
+
/*
* The call to use to reach the firmware.
*/
@@ -887,6 +890,70 @@ static void sdei_smccc_hvc(unsigned long function_id,
arm_smccc_hvc(function_id, arg0, arg1, arg2, arg3, arg4, 0, 0, res);
}
+#ifdef CONFIG_ACPI_APEI_GHES
+static DEFINE_GHES_NMI_FIXMAP(sde_normal, FIX_APEI_GHES_SDEI_NORMAL);
+static DEFINE_GHES_NMI_FIXMAP(sde_critical, FIX_APEI_GHES_SDEI_CRITICAL);
+
+int sdei_register_ghes(struct ghes *ghes, sdei_event_callback *cb)
+{
+ int err;
+ u32 event_num;
+ u64 result;
+
+ event_num = ghes->generic->notify.vector;
+ if (event_num == 0) {
+ /*
+ * Event 0 is reserved by the specification for
+ * SDEI_EVENT_SIGNAL.
+ */
+ return -EINVAL;
+ }
+
+ err = sdei_api_event_get_info(event_num, SDEI_EVENT_INFO_EV_PRIORITY,
+ &result);
+ if (err)
+ return err;
+
+ if (result == SDEI_EVENT_PRIORITY_CRITICAL)
+ ghes->nmi_fixmap = &sde_critical;
+ else
+ ghes->nmi_fixmap = &sde_normal;
+
+ err = sdei_event_register(event_num, cb, ghes);
+ if (!err)
+ err = sdei_event_enable(event_num);
+
+ return err;
+}
+
+int sdei_unregister_ghes(struct ghes *ghes)
+{
+ int i;
+ int err;
+ u32 event_num = ghes->generic->notify.vector;
+
+ might_sleep();
+
+ /*
+ * The event may be running on another CPU. Disable it
+ * to stop new events, then try to unregister a few times.
+ */
+ err = sdei_event_disable(event_num);
+ if (err)
+ return err;
+
+ for (i = 0; i < 3; i++) {
+ err = sdei_event_unregister(event_num);
+ if (err != -EINPROGRESS)
+ break;
+
+ schedule();
+ }
+
+ return err;
+}
+#endif /* CONFIG_ACPI_APEI_GHES */
+
static int sdei_get_conduit(struct platform_device *pdev)
{
const char *method;
diff --git a/include/linux/arm_sdei.h b/include/linux/arm_sdei.h
index 942afbd544b7..5fdf799be026 100644
--- a/include/linux/arm_sdei.h
+++ b/include/linux/arm_sdei.h
@@ -11,6 +11,7 @@ enum sdei_conduit_types {
CONDUIT_HVC,
};
+#include <acpi/ghes.h>
#include <asm/sdei.h>
/* Arch code should override this to set the entry point from firmware... */
@@ -39,6 +40,10 @@ int sdei_event_unregister(u32 event_num);
int sdei_event_enable(u32 event_num);
int sdei_event_disable(u32 event_num);
+/* GHES register/unregister helpers */
+int sdei_register_ghes(struct ghes *ghes, sdei_event_callback *cb);
+int sdei_unregister_ghes(struct ghes *ghes);
+
#ifdef CONFIG_ARM_SDE_INTERFACE
/* For use by arch code when CPU hotplug notifiers are not appropriate. */
int sdei_mask_local_cpu(void);
--
2.16.2
^ permalink raw reply related
* [PATCH v4 10/12] ACPI / APEI: Add support for the SDEI GHES Notification type
From: James Morse @ 2018-05-16 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516162829.14348-1-james.morse@arm.com>
If the GHES notification type is SDEI, register the provided event
number and point the callback at ghes_sdei_callback().
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Punit Agrawal <punit.agrawal@arm.com>
---
drivers/acpi/apei/ghes.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++--
include/linux/arm_sdei.h | 3 +++
2 files changed, 67 insertions(+), 2 deletions(-)
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index 014966bdd0a7..72f7bc8435f7 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -25,6 +25,7 @@
* GNU General Public License for more details.
*/
+#include <linux/arm_sdei.h>
#include <linux/kernel.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
@@ -58,7 +59,7 @@
#define GHES_PFX "GHES: "
-#if defined(CONFIG_HAVE_ACPI_APEI_NMI) || defined(CONFIG_ACPI_APEI_SEA)
+#if defined(CONFIG_HAVE_ACPI_APEI_NMI) || defined(CONFIG_ACPI_APEI_SEA) || defined(CONFIG_ARM_SDE_INTERFACE)
#define WANT_NMI_ESTATUS_QUEUE 1
#endif
@@ -750,7 +751,7 @@ static int _in_nmi_notify_one(struct ghes *ghes)
return 0;
}
-static int ghes_estatus_queue_notified(struct list_head *rcu_list)
+static int __maybe_unused ghes_estatus_queue_notified(struct list_head *rcu_list)
{
int ret = -ENOENT;
struct ghes *ghes;
@@ -1042,6 +1043,49 @@ static inline void ghes_nmi_add(struct ghes *ghes) { }
static inline void ghes_nmi_remove(struct ghes *ghes) { }
#endif /* CONFIG_HAVE_ACPI_APEI_NMI */
+static int ghes_sdei_callback(u32 event_num, struct pt_regs *regs, void *arg)
+{
+ struct ghes *ghes = arg;
+
+ if (!_in_nmi_notify_one(ghes)) {
+ if (IS_ENABLED(CONFIG_ARCH_HAVE_NMI_SAFE_CMPXCHG))
+ irq_work_queue(&ghes_proc_irq_work);
+
+ return 0;
+ }
+
+ return -ENOENT;
+}
+
+static int apei_sdei_register_ghes(struct ghes *ghes)
+{
+ int err = -EINVAL;
+
+ if (IS_ENABLED(CONFIG_ARM_SDE_INTERFACE)) {
+ ghes_estatus_queue_grow_pool(ghes);
+
+ err = sdei_register_ghes(ghes, ghes_sdei_callback);
+ if (err)
+ ghes_estatus_queue_shrink_pool(ghes);
+ }
+
+ return err;
+}
+
+static int apei_sdei_unregister_ghes(struct ghes *ghes)
+{
+ int err = -EINVAL;
+
+ if (IS_ENABLED(CONFIG_ARM_SDE_INTERFACE)) {
+ err = sdei_unregister_ghes(ghes);
+
+ if (!err)
+ ghes_estatus_queue_shrink_pool(ghes);
+ }
+
+ return err;
+}
+
static int ghes_probe(struct platform_device *ghes_dev)
{
struct acpi_hest_generic *generic;
@@ -1076,6 +1120,13 @@ static int ghes_probe(struct platform_device *ghes_dev)
goto err;
}
break;
+ case ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED:
+ if (!IS_ENABLED(CONFIG_ARM_SDE_INTERFACE)) {
+ pr_warn(GHES_PFX "Generic hardware error source: %d notified via SDE Interface is not supported!\n",
+ generic->header.source_id);
+ goto err;
+ }
+ break;
case ACPI_HEST_NOTIFY_LOCAL:
pr_warning(GHES_PFX "Generic hardware error source: %d notified via local interrupt is not supported!\n",
generic->header.source_id);
@@ -1143,6 +1194,11 @@ static int ghes_probe(struct platform_device *ghes_dev)
case ACPI_HEST_NOTIFY_NMI:
ghes_nmi_add(ghes);
break;
+ case ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED:
+ rc = apei_sdei_register_ghes(ghes);
+ if (rc)
+ goto err_edac_unreg;
+ break;
default:
BUG();
}
@@ -1164,6 +1220,7 @@ err:
static int ghes_remove(struct platform_device *ghes_dev)
{
+ int rc;
struct ghes *ghes;
struct acpi_hest_generic *generic;
@@ -1196,6 +1253,11 @@ static int ghes_remove(struct platform_device *ghes_dev)
case ACPI_HEST_NOTIFY_NMI:
ghes_nmi_remove(ghes);
break;
+ case ACPI_HEST_NOTIFY_SOFTWARE_DELEGATED:
+ rc = apei_sdei_unregister_ghes(ghes);
+ if (rc)
+ return rc;
+ break;
default:
BUG();
break;
diff --git a/include/linux/arm_sdei.h b/include/linux/arm_sdei.h
index 5fdf799be026..f49063ca206d 100644
--- a/include/linux/arm_sdei.h
+++ b/include/linux/arm_sdei.h
@@ -12,7 +12,10 @@ enum sdei_conduit_types {
};
#include <acpi/ghes.h>
+
+#ifdef CONFIG_ARM_SDE_INTERFACE
#include <asm/sdei.h>
+#endif
/* Arch code should override this to set the entry point from firmware... */
#ifndef sdei_arch_get_entry_point
--
2.16.2
^ permalink raw reply related
* [PATCH v4 11/12] mm/memory-failure: increase queued recovery work's priority
From: James Morse @ 2018-05-16 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516162829.14348-1-james.morse@arm.com>
arm64 can take an NMI-like error notification when user-space steps in
some corrupt memory. APEI's GHES code will call memory_failure_queue()
to schedule the recovery work. We then return to user-space, possibly
taking the fault again.
Currently the arch code unconditionally signals user-space from this
path, so we don't get stuck in this loop, but the affected process
never benefits from memory_failure()s recovery work. To fix this we
need to know the recovery work will run before we get back to user-space.
Increase the priority of the recovery work by scheduling it on the
system_highpri_wq, then try to bump the current task off this CPU
so that the recover work starts immediately.
Reported-by: Xie XiuQi <xiexiuqi@huawei.com>
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Punit Agrawal <punit.agrawal@arm.com>
Tested-by: Tyler Baicar <tbaicar@codeaurora.org>
CC: Xie XiuQi <xiexiuqi@huawei.com>
CC: gengdongjiu <gengdongjiu@huawei.com>
---
mm/memory-failure.c | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/mm/memory-failure.c b/mm/memory-failure.c
index 9d142b9b86dc..f0e69d7ac406 100644
--- a/mm/memory-failure.c
+++ b/mm/memory-failure.c
@@ -55,6 +55,7 @@
#include <linux/hugetlb.h>
#include <linux/memory_hotplug.h>
#include <linux/mm_inline.h>
+#include <linux/preempt.h>
#include <linux/kfifo.h>
#include <linux/ratelimit.h>
#include "internal.h"
@@ -1333,6 +1334,7 @@ static DEFINE_PER_CPU(struct memory_failure_cpu, memory_failure_cpu);
*/
void memory_failure_queue(unsigned long pfn, int flags)
{
+ int cpu = smp_processor_id();
struct memory_failure_cpu *mf_cpu;
unsigned long proc_flags;
struct memory_failure_entry entry = {
@@ -1342,11 +1344,14 @@ void memory_failure_queue(unsigned long pfn, int flags)
mf_cpu = &get_cpu_var(memory_failure_cpu);
spin_lock_irqsave(&mf_cpu->lock, proc_flags);
- if (kfifo_put(&mf_cpu->fifo, entry))
- schedule_work_on(smp_processor_id(), &mf_cpu->work);
- else
+ if (kfifo_put(&mf_cpu->fifo, entry)) {
+ queue_work_on(cpu, system_highpri_wq, &mf_cpu->work);
+ set_tsk_need_resched(current);
+ preempt_set_need_resched();
+ } else {
pr_err("Memory failure: buffer overflow when queuing memory failure at %#lx\n",
pfn);
+ }
spin_unlock_irqrestore(&mf_cpu->lock, proc_flags);
put_cpu_var(memory_failure_cpu);
}
--
2.16.2
^ permalink raw reply related
* [PATCH v4 12/12] arm64: acpi: Make apei_claim_sea() synchronise with APEI's irq work
From: James Morse @ 2018-05-16 16:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516162829.14348-1-james.morse@arm.com>
APEI is unable to do all of its error handling work in nmi-context, so
it defers non-fatal work onto the irq_work queue. arch_irq_work_raise()
sends an IPI to the calling cpu, but we can't guarantee this will be
taken before we return.
Unless we interrupted a context with irqs-masked, we can call
irq_work_run() to do the work now. Otherwise return -EINPROGRESS to
indicate ghes_notify_sea() found some work to do, but it hasn't
finished yet.
With this we can take apei_claim_sea() returning '0' to mean this
external-abort was also notification of a firmware-first RAS error,
and that APEI has processed the CPER records.
Signed-off-by: James Morse <james.morse@arm.com>
Reviewed-by: Punit Agrawal <punit.agrawal@arm.com>
Tested-by: Tyler Baicar <tbaicar@codeaurora.org>
CC: Xie XiuQi <xiexiuqi@huawei.com>
CC: gengdongjiu <gengdongjiu@huawei.com>
---
Changes since v2:
* Removed IS_ENABLED() check, done by the caller unless we have a dummy
definition.
arch/arm64/kernel/acpi.c | 19 +++++++++++++++++++
arch/arm64/mm/fault.c | 9 ++++-----
2 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel/acpi.c b/arch/arm64/kernel/acpi.c
index df2c6bff8c58..9ef2d91f0000 100644
--- a/arch/arm64/kernel/acpi.c
+++ b/arch/arm64/kernel/acpi.c
@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
+#include <linux/irq_work.h>
#include <linux/memblock.h>
#include <linux/of_fdt.h>
#include <linux/smp.h>
@@ -275,10 +276,14 @@ int apei_claim_sea(struct pt_regs *regs)
{
int err = -ENOENT;
unsigned long current_flags = arch_local_save_flags();
+ unsigned long interrupted_flags = current_flags;
if (!IS_ENABLED(CONFIG_ACPI_APEI_SEA))
return err;
+ if (regs)
+ interrupted_flags = regs->pstate;
+
/*
* SEA can interrupt SError, mask it and describe this as an NMI so
* that APEI defers the handling.
@@ -287,6 +292,20 @@ int apei_claim_sea(struct pt_regs *regs)
nmi_enter();
err = ghes_notify_sea();
nmi_exit();
+
+ /*
+ * APEI NMI-like notifications are deferred to irq_work. Unless
+ * we interrupted irqs-masked code, we can do that now.
+ */
+ if (!err) {
+ if (!arch_irqs_disabled_flags(interrupted_flags)) {
+ local_daif_restore(DAIF_PROCCTX_NOIRQ);
+ irq_work_run();
+ } else {
+ err = -EINPROGRESS;
+ }
+ }
+
local_daif_restore(current_flags);
return err;
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index d7e89da0e5df..0232e9064144 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -568,11 +568,10 @@ static int do_sea(unsigned long addr, unsigned int esr, struct pt_regs *regs)
inf = esr_to_fault_info(esr);
- /*
- * Return value ignored as we rely on signal merging.
- * Future patches will make this more robust.
- */
- apei_claim_sea(regs);
+ if (apei_claim_sea(regs) == 0) {
+ /* APEI claimed this as a firmware-first notification */
+ return 0;
+ }
info.si_signo = inf->sig;
info.si_errno = 0;
--
2.16.2
^ permalink raw reply related
* [PATCH 1/6] dt-bindings: media: rcar-vin: Describe optional ep properties
From: Jacopo Mondi @ 2018-05-16 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526488352-898-1-git-send-email-jacopo+renesas@jmondi.org>
Describe the optional endpoint properties for endpoint nodes of port at 0
and port at 1 of the R-Car VIN driver device tree bindings documentation.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
Documentation/devicetree/bindings/media/rcar_vin.txt | 13 ++++++++++++-
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
index a19517e1..c53ce4e 100644
--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
+++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
@@ -53,6 +53,16 @@ from local SoC CSI-2 receivers (port1) depending on SoC.
from external SoC pins described in video-interfaces.txt[1].
Describing more then one endpoint in port 0 is invalid. Only VIN
instances that are connected to external pins should have port 0.
+
+ - Optional properties for endpoint nodes of port at 0:
+ - hsync-active: active state of the HSYNC signal, 0/1 for LOW/HIGH
+ respectively. Default is active high.
+ - vsync-active: active state of the VSYNC signal, 0/1 for LOW/HIGH
+ respectively. Default is active high.
+
+ If both HSYNC and VSYNC polarities are not specified, embedded
+ synchronization is selected.
+
- port 1 - sub-nodes describing one or more endpoints connected to
the VIN from local SoC CSI-2 receivers. The endpoint numbers must
use the following schema.
@@ -62,6 +72,8 @@ from local SoC CSI-2 receivers (port1) depending on SoC.
- Endpoint 2 - sub-node describing the endpoint connected to CSI40
- Endpoint 3 - sub-node describing the endpoint connected to CSI41
+ Endpoint nodes of port at 1 do not support any optional endpoint property.
+
Device node example for Gen2 platforms
--------------------------------------
@@ -112,7 +124,6 @@ Board setup example for Gen2 platforms (vin1 composite video input)
vin1ep0: endpoint {
remote-endpoint = <&adv7180>;
- bus-width = <8>;
};
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 2/6] dt-bindings: media: rcar-vin: Document data-active
From: Jacopo Mondi @ 2018-05-16 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526488352-898-1-git-send-email-jacopo+renesas@jmondi.org>
Document 'data-active' property in R-Car VIN device tree bindings.
The property is optional when running with explicit synchronization
(eg. BT.601) but mandatory when embedded synchronization is in use (eg.
BT.656) as specified by the hardware manual.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
Documentation/devicetree/bindings/media/rcar_vin.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/rcar_vin.txt b/Documentation/devicetree/bindings/media/rcar_vin.txt
index c53ce4e..17eac8a 100644
--- a/Documentation/devicetree/bindings/media/rcar_vin.txt
+++ b/Documentation/devicetree/bindings/media/rcar_vin.txt
@@ -63,6 +63,11 @@ from local SoC CSI-2 receivers (port1) depending on SoC.
If both HSYNC and VSYNC polarities are not specified, embedded
synchronization is selected.
+ - data-active: active state of data enable signal (CLOCKENB pin).
+ 0/1 for LOW/HIGH respectively. If not specified, use HSYNC as
+ data enable signal. When using embedded synchronization this
+ property is mandatory.
+
- port 1 - sub-nodes describing one or more endpoints connected to
the VIN from local SoC CSI-2 receivers. The endpoint numbers must
use the following schema.
--
2.7.4
^ permalink raw reply related
* [PATCH 5/6] ARM: dts: rcar-gen2: Remove unused VIN properties
From: Jacopo Mondi @ 2018-05-16 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526488352-898-1-git-send-email-jacopo+renesas@jmondi.org>
The 'bus-width' and 'pclk-sample' properties are not parsed by the VIN
driver and only confuse users. Remove them in all Gen2 SoC that used
them.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
arch/arm/boot/dts/r8a7790-lager.dts | 3 ---
arch/arm/boot/dts/r8a7791-koelsch.dts | 3 ---
arch/arm/boot/dts/r8a7791-porter.dts | 1 -
arch/arm/boot/dts/r8a7793-gose.dts | 3 ---
arch/arm/boot/dts/r8a7794-alt.dts | 1 -
arch/arm/boot/dts/r8a7794-silk.dts | 1 -
6 files changed, 12 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index 063fdb6..b56b309 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -873,10 +873,8 @@
port {
vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>;
- bus-width = <24>;
hsync-active = <0>;
vsync-active = <0>;
- pclk-sample = <1>;
data-active = <1>;
};
};
@@ -895,7 +893,6 @@
vin1ep0: endpoint {
remote-endpoint = <&adv7180>;
- bus-width = <8>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index f40321a..9967666 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -849,10 +849,8 @@
vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>;
- bus-width = <24>;
hsync-active = <0>;
vsync-active = <0>;
- pclk-sample = <1>;
data-active = <1>;
};
};
@@ -870,7 +868,6 @@
vin1ep: endpoint {
remote-endpoint = <&adv7180>;
- bus-width = <8>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index c14e6fe..055a7f1 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -391,7 +391,6 @@
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
- bus-width = <8>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 9ed6961..9d3fba2 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -759,10 +759,8 @@
vin0ep2: endpoint {
remote-endpoint = <&adv7612_out>;
- bus-width = <24>;
hsync-active = <0>;
vsync-active = <0>;
- pclk-sample = <1>;
data-active = <1>;
};
};
@@ -781,7 +779,6 @@
vin1ep: endpoint {
remote-endpoint = <&adv7180_out>;
- bus-width = <8>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 26a8834..4bbb9cc 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -380,7 +380,6 @@
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
- bus-width = <8>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index 351cb3b..c0c5d31 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -480,7 +480,6 @@
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
- bus-width = <8>;
};
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 6/6] ARM: dts: rcar-gen2: Add 'data-active' property
From: Jacopo Mondi @ 2018-05-16 16:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526488352-898-1-git-send-email-jacopo+renesas@jmondi.org>
The 'data-active' property needs to be specified when using embedded
synchronization. Add it to the Gen-2 boards using composite video input.
Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
arch/arm/boot/dts/r8a7790-lager.dts | 1 +
arch/arm/boot/dts/r8a7791-koelsch.dts | 1 +
arch/arm/boot/dts/r8a7791-porter.dts | 1 +
arch/arm/boot/dts/r8a7793-gose.dts | 1 +
arch/arm/boot/dts/r8a7794-alt.dts | 1 +
arch/arm/boot/dts/r8a7794-silk.dts | 1 +
6 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/r8a7790-lager.dts b/arch/arm/boot/dts/r8a7790-lager.dts
index b56b309..48fcb44 100644
--- a/arch/arm/boot/dts/r8a7790-lager.dts
+++ b/arch/arm/boot/dts/r8a7790-lager.dts
@@ -893,6 +893,7 @@
vin1ep0: endpoint {
remote-endpoint = <&adv7180>;
+ data-active = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index 9967666..fa0b25f 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -868,6 +868,7 @@
vin1ep: endpoint {
remote-endpoint = <&adv7180>;
+ data-active = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7791-porter.dts b/arch/arm/boot/dts/r8a7791-porter.dts
index 055a7f1..96b9605 100644
--- a/arch/arm/boot/dts/r8a7791-porter.dts
+++ b/arch/arm/boot/dts/r8a7791-porter.dts
@@ -391,6 +391,7 @@
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
+ data-active = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7793-gose.dts b/arch/arm/boot/dts/r8a7793-gose.dts
index 9d3fba2..80b4fa8 100644
--- a/arch/arm/boot/dts/r8a7793-gose.dts
+++ b/arch/arm/boot/dts/r8a7793-gose.dts
@@ -779,6 +779,7 @@
vin1ep: endpoint {
remote-endpoint = <&adv7180_out>;
+ data-active = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 4bbb9cc..00df605d 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -380,6 +380,7 @@
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
+ data-active = <1>;
};
};
};
diff --git a/arch/arm/boot/dts/r8a7794-silk.dts b/arch/arm/boot/dts/r8a7794-silk.dts
index c0c5d31..ed17376 100644
--- a/arch/arm/boot/dts/r8a7794-silk.dts
+++ b/arch/arm/boot/dts/r8a7794-silk.dts
@@ -480,6 +480,7 @@
vin0ep: endpoint {
remote-endpoint = <&adv7180>;
+ data-active = <1>;
};
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 07/14] ARM: spectre-v2: add Cortex A8 and A15 validation of the IBE bit
From: Florian Fainelli @ 2018-05-16 16:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fIuBF-0003q0-3d@rmk-PC.armlinux.org.uk>
On 05/16/2018 04:01 AM, Russell King wrote:
> When the branch predictor hardening is enabled, firmware must have set
> the IBE bit in the auxiliary control register. If this bit has not
> been set, the Spectre workarounds will not be functional.
>
> Add validation that this bit is set, and print a warning at alert level
> if this is not the case.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
I would be keen on updating arch/arm/kernel/head.S to to attempt setting
ACTRL[0]=1 on A15/B15, if the kernel executes at the appropriate
privilege level, this will succeed, if not, this should result in an
ignored write. What do you think?
--
Florian
^ permalink raw reply
* [PATCH 07/14] ARM: spectre-v2: add Cortex A8 and A15 validation of the IBE bit
From: Florian Fainelli @ 2018-05-16 16:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fIuBF-0003q0-3d@rmk-PC.armlinux.org.uk>
On 05/16/2018 04:01 AM, Russell King wrote:
> When the branch predictor hardening is enabled, firmware must have set
> the IBE bit in the auxiliary control register. If this bit has not
> been set, the Spectre workarounds will not be functional.
>
> Add validation that this bit is set, and print a warning at alert level
> if this is not the case.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
* [PATCH 08/14] ARM: spectre-v2: harden user aborts in kernel space
From: Florian Fainelli @ 2018-05-16 16:35 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fIuBK-0003q7-9n@rmk-PC.armlinux.org.uk>
On 05/16/2018 04:01 AM, Russell King wrote:
> In order to prevent aliasing attacks on the branch predictor,
> invalidate the BTB or instruction cache on CPUs that are known to be
> affected when taking an abort on a address that is outside of a user
> task limit:
>
> Cortex A8, A9, A12, A17, A73, A75: flush BTB.
> Cortex A15, Brahma B15: invalidate icache.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
--
Florian
^ permalink raw reply
* [PATCH v4 00/12] APEI in_nmi() rework and arm64 SDEI wire-up
From: James Morse @ 2018-05-16 16:46 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516162829.14348-1-james.morse@arm.com>
On 16/05/18 17:28, James Morse wrote:
> The aim of this series is to wire arm64's SDEI into APEI.
... and I missed the 'l' from the beginning of the well know inux-mm at kvack.org
mailing list. I won't increase the spam by resending, please fix it when
pointing out my other mistakes!
Thanks,
James
> Since v3 the NMI fixmap entries and locks have moved into their own
> structure. This moves the indirection up from the 'lock', which should
> be more acceptable to polite society.
> Changes are noted in each patch.
>
> This touches a few trees, so I'm not sure how best it should be merged.
> Patches 11 and 12 are reducing a race that is made worse by patch 4, I'd
> like them to arrive together, even though patch 11 doesn't depend on anything
> else in the series. A partial merge of this would be 1-3 and 11.
[...]
> Patch 11 makes the reschedule to memory_failure() run as soon as possible.
[...]
> James Morse (12):
> ACPI / APEI: Move the estatus queue code up, and under its own ifdef
> ACPI / APEI: Generalise the estatus queue's add/remove and notify code
> ACPI / APEI: don't wait to serialise with oops messages when
> panic()ing
> ACPI / APEI: Switch NOTIFY_SEA to use the estatus queue
> KVM: arm/arm64: Add kvm_ras.h to collect kvm specific RAS plumbing
> arm64: KVM/mm: Move SEA handling behind a single 'claim' interface
> ACPI / APEI: Make the nmi_fixmap_idx per-ghes to allow multiple
> in_nmi() users
> ACPI / APEI: Split fixmap pages for arm64 NMI-like notifications
> firmware: arm_sdei: Add ACPI GHES registration helper
> ACPI / APEI: Add support for the SDEI GHES Notification type
> mm/memory-failure: increase queued recovery work's priority
> arm64: acpi: Make apei_claim_sea() synchronise with APEI's irq work
>
> arch/arm/include/asm/kvm_ras.h | 14 +
> arch/arm/include/asm/system_misc.h | 5 -
> arch/arm64/include/asm/acpi.h | 4 +
> arch/arm64/include/asm/daifflags.h | 1 +
> arch/arm64/include/asm/fixmap.h | 8 +-
> arch/arm64/include/asm/kvm_ras.h | 24 ++
> arch/arm64/include/asm/system_misc.h | 2 -
> arch/arm64/kernel/acpi.c | 49 ++++
> arch/arm64/mm/fault.c | 30 +-
> drivers/acpi/apei/ghes.c | 518 ++++++++++++++++++++---------------
> drivers/firmware/arm_sdei.c | 67 +++++
> include/acpi/ghes.h | 17 ++
> include/linux/arm_sdei.h | 8 +
> mm/memory-failure.c | 11 +-
> virt/kvm/arm/mmu.c | 4 +-
> 15 files changed, 503 insertions(+), 259 deletions(-)
> create mode 100644 arch/arm/include/asm/kvm_ras.h
> create mode 100644 arch/arm64/include/asm/kvm_ras.h
>
^ permalink raw reply
* [PATCH 09/14] ARM: spectre-v2: add PSCI based hardening
From: Marc Zyngier @ 2018-05-16 17:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <E1fIuBP-0003qE-DZ@rmk-PC.armlinux.org.uk>
[updating Christoffer's email address]
On 16/05/18 12:01, Russell King wrote:
> Add PSCI based hardening for cores that require more complex handling in
> firmware.
>
> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
> ---
> arch/arm/mm/proc-v7-bugs.c | 50 ++++++++++++++++++++++++++++++++++++++++++++++
> arch/arm/mm/proc-v7.S | 21 +++++++++++++++++++
> 2 files changed, 71 insertions(+)
>
> diff --git a/arch/arm/mm/proc-v7-bugs.c b/arch/arm/mm/proc-v7-bugs.c
> index 65a9b8141f86..81de4a8e74c6 100644
> --- a/arch/arm/mm/proc-v7-bugs.c
> +++ b/arch/arm/mm/proc-v7-bugs.c
> @@ -1,9 +1,12 @@
> // SPDX-License-Identifier: GPL-2.0
> +#include <linux/arm-smccc.h>
> #include <linux/kernel.h>
> +#include <linux/psci.h>
> #include <linux/smp.h>
>
> #include <asm/cp15.h>
> #include <asm/cputype.h>
> +#include <asm/proc-fns.h>
> #include <asm/system_misc.h>
>
> void cpu_v7_bugs_init(void);
> @@ -39,6 +42,9 @@ void cpu_v7_ca15_ibe(void)
> #ifdef CONFIG_HARDEN_BRANCH_PREDICTOR
> void (*harden_branch_predictor)(void);
>
> +extern void cpu_v7_smc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
> +extern void cpu_v7_hvc_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
> +
> static void harden_branch_predictor_bpiall(void)
> {
> write_sysreg(0, BPIALL);
> @@ -49,6 +55,18 @@ static void harden_branch_predictor_iciallu(void)
> write_sysreg(0, ICIALLU);
> }
>
> +#ifdef CONFIG_ARM_PSCI
> +static void call_smc_arch_workaround_1(void)
> +{
> + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
> +}
> +
> +static void call_hvc_arch_workaround_1(void)
> +{
> + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_WORKAROUND_1, NULL);
> +}
> +#endif
> +
> void cpu_v7_bugs_init(void)
> {
> const char *spectre_v2_method = NULL;
> @@ -73,6 +91,38 @@ void cpu_v7_bugs_init(void)
> spectre_v2_method = "ICIALLU";
> break;
> }
> +
> +#ifdef CONFIG_ARM_PSCI
> + if (psci_ops.smccc_version != SMCCC_VERSION_1_0) {
> + struct arm_smccc_res res;
> +
> + switch (psci_ops.conduit) {
> + case PSCI_CONDUIT_HVC:
> + arm_smccc_1_1_hvc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
> + ARM_SMCCC_ARCH_WORKAROUND_1, &res);
> + if ((int)res.a0 < 0)
> + break;
> + harden_branch_predictor = call_hvc_arch_workaround_1;
> + processor.switch_mm = cpu_v7_hvc_switch_mm;
> + spectre_v2_method = "hypervisor PSCI";
nit: strictly speaking, this is not provided by PSCI, but by
ARCH_WORKAROUND_1. We just use the same conduit as PSCI to discover it.
> + break;
> +
> + case PSCI_CONDUIT_SMC:
> + arm_smccc_1_1_smc(ARM_SMCCC_ARCH_FEATURES_FUNC_ID,
> + ARM_SMCCC_ARCH_WORKAROUND_1, &res);
> + if ((int)res.a0 < 0)
> + break;
> + harden_branch_predictor = call_smc_arch_workaround_1;
> + processor.switch_mm = cpu_v7_smc_switch_mm;
> + spectre_v2_method = "firmware PSCI";
> + break;
> +
> + default:
> + break;
> + }
> + }
> +#endif
> +
> if (spectre_v2_method)
> pr_info("CPU: Spectre v2: using %s workaround\n",
> spectre_v2_method);
> diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
> index 989864676f8b..7e6719a0eada 100644
> --- a/arch/arm/mm/proc-v7.S
> +++ b/arch/arm/mm/proc-v7.S
> @@ -9,6 +9,7 @@
> *
> * This is the "shell" of the ARMv7 processor support.
> */
> +#include <linux/arm-smccc.h>
> #include <linux/init.h>
> #include <linux/linkage.h>
> #include <asm/assembler.h>
> @@ -93,6 +94,26 @@ ENTRY(cpu_v7_dcache_clean_area)
> ret lr
> ENDPROC(cpu_v7_dcache_clean_area)
>
> +#ifdef CONFIG_ARM_PSCI
> + .arch_extension sec
> +ENTRY(cpu_v7_smc_switch_mm)
> + stmfd sp!, {r0 - r3}
> + movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
> + movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
> + smc #0
> + ldmfd sp!, {r0 - r3}
> + b cpu_v7_switch_mm
> +ENDPROC(cpu_v7_smc_switch_mm)
> + .arch_extension virt
> +ENTRY(cpu_v7_hvc_switch_mm)
> + stmfd sp!, {r0 - r3}
> + movw r0, #:lower16:ARM_SMCCC_ARCH_WORKAROUND_1
> + movt r0, #:upper16:ARM_SMCCC_ARCH_WORKAROUND_1
> + hvc #0
> + ldmfd sp!, {r0 - r3}
> + b cpu_v7_switch_mm
> +ENDPROC(cpu_v7_smc_switch_mm)
> +#endif
> ENTRY(cpu_v7_iciallu_switch_mm)
> mov r3, #0
> mcr p15, 0, r3, c7, c5, 0 @ ICIALLU
>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
M.
--
Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
From: Stephen Boyd @ 2018-05-16 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1525810921-15878-2-git-send-email-rishabhb@codeaurora.org>
Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> new file mode 100644
> index 0000000..a586a17
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
> @@ -0,0 +1,32 @@
> +== Introduction==
> +
> +LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
> +that can be shared by multiple clients. Clients here are different cores in the
> +SOC, the idea is to minimize the local caches at the clients and migrate to
> +common pool of memory. Cache memory is divided into partitions called slices
> +which are assigned to clients. Clients can query the slice details, activate
> +and deactivate them.
> +
> +Properties:
> +- compatible:
> + Usage: required
> + Value type: <string>
> + Definition: must be "qcom,sdm845-llcc"
> +
> +- reg:
> + Usage: required
> + Value Type: <prop-encoded-array>
> + Definition: Start address and the range of the LLCC registers.
Start address and size?
> +
> +- max-slices:
> + usage: required
> + Value Type: <u32>
> + Definition: Number of cache slices supported by hardware
> +
> +Example:
> +
> + llcc: qcom,llcc at 1100000 {
cache-controller at 1100000 ?
> + compatible = "qcom,sdm845-llcc";
> + reg = <0x1100000 0x250000>;
> + max-slices = <32>;
> + };
> --
^ permalink raw reply
* [PATCH 1/3] input: touchscreen: edt-ft5x06: make wakeup source behavior configurable
From: Dmitry Torokhov @ 2018-05-16 17:03 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516122829.23694-2-daniel@zonque.org>
Hi Daniel,
On Wed, May 16, 2018 at 02:28:27PM +0200, Daniel Mack wrote:
> Allow configuring the device as wakeup source through device properties, as
> not all platforms want to wake up on touch screen activity.
>
> Note that by default, the device will now no longer be a wakeup source.
>
> Signed-off-by: Daniel Mack <daniel@zonque.org>
> ---
> Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt | 3 +++
> drivers/input/touchscreen/edt-ft5x06.c | 3 ++-
> 2 files changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> index 025cf8c9324a..83f792d4d88c 100644
> --- a/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> +++ b/Documentation/devicetree/bindings/input/touchscreen/edt-ft5x06.txt
> @@ -52,6 +52,8 @@ Optional properties:
> - touchscreen-inverted-y : See touchscreen.txt
> - touchscreen-swapped-x-y : See touchscreen.txt
>
> + - wakeup-source: touchscreen acts as wakeup source
> +
> Example:
> polytouch: edt-ft5x06 at 38 {
> compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
> @@ -62,4 +64,5 @@ Example:
> interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
> wake-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
> + wakeup-source;
> };
> diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
> index 5bf63f76ddda..955f085627fa 100644
> --- a/drivers/input/touchscreen/edt-ft5x06.c
> +++ b/drivers/input/touchscreen/edt-ft5x06.c
> @@ -1007,7 +1007,8 @@ static int edt_ft5x06_ts_probe(struct i2c_client *client,
> goto err_remove_attrs;
>
> edt_ft5x06_ts_prepare_debugfs(tsdata, dev_driver_string(&client->dev));
> - device_init_wakeup(&client->dev, 1);
> + device_init_wakeup(&client->dev,
> + device_property_read_bool(dev, "wakeup-source"));
I think we should actually drop device_init_wakeup() call. I2C core
already handles "wakeup-source" property (for OF). The static board
files can instantiate clients with I2C_CLIENT_WAKE, so that's handled
too, and I think ACPI has its own notion of annotating wakeup sources.
>
> dev_dbg(&client->dev,
> "EDT FT5x06 initialized: IRQ %d, WAKE pin %d, Reset pin %d.\n",
> --
> 2.14.3
>
Thanks.
--
Dmitry
^ permalink raw reply
* [PATCH 2/3] input: touchscreen: edt-ft5x06: assert reset during suspend
From: Dmitry Torokhov @ 2018-05-16 17:05 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516122829.23694-3-daniel@zonque.org>
On Wed, May 16, 2018 at 02:28:28PM +0200, Daniel Mack wrote:
> If the device is not configured as wakeup source, it can be put in reset
> during suspend to save some power.
>
> Signed-off-by: Daniel Mack <daniel@zonque.org>
> ---
> drivers/input/touchscreen/edt-ft5x06.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/drivers/input/touchscreen/edt-ft5x06.c b/drivers/input/touchscreen/edt-ft5x06.c
> index 955f085627fa..c34a0b23f90a 100644
> --- a/drivers/input/touchscreen/edt-ft5x06.c
> +++ b/drivers/input/touchscreen/edt-ft5x06.c
> @@ -1036,9 +1036,12 @@ static int edt_ft5x06_ts_remove(struct i2c_client *client)
> static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> {
> struct i2c_client *client = to_i2c_client(dev);
> + struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
>
> if (device_may_wakeup(dev))
> enable_irq_wake(client->irq);
> + else if (tsdata->reset_gpio)
> + gpiod_set_value_cansleep(tsdata->reset_gpio, 1);
>
> return 0;
> }
> @@ -1046,9 +1049,12 @@ static int __maybe_unused edt_ft5x06_ts_suspend(struct device *dev)
> static int __maybe_unused edt_ft5x06_ts_resume(struct device *dev)
> {
> struct i2c_client *client = to_i2c_client(dev);
> + struct edt_ft5x06_ts_data *tsdata = i2c_get_clientdata(client);
>
> if (device_may_wakeup(dev))
> disable_irq_wake(client->irq);
> + else if (tsdata->reset_gpio)
> + gpiod_set_value_cansleep(tsdata->reset_gpio, 0);
I think you need msleep() here as the chip needs a bit to get out of
reset before it is ready. FWIW we have 300 ms delay in probe().
Thanks.
--
Dmitry
^ permalink raw reply
* [PATCH 00/27] Add multi-channel and overheat IRQ support to Armada thermal driver
From: Gregory CLEMENT @ 2018-05-16 17:28 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180421151255.29929-1-miquel.raynal@bootlin.com>
Hi Miquel,
On sam., avril 21 2018, Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> The only capability of the Armada thermal driver is currently just to
> read one sensor (the default one) per AP and one per CP.
>
> Actually, there is one sensor per core in the AP806 plus one sensor in
> the thermal IP itself. The CP110 just features one thermal sensor in its
> own thermal IP.
>
> Also, there is no need for the thermal core to poll the temperature of
> each sensor by software as this IP (at least for AP806 and CP110
> compatibles) features an hardware overheat interrupt.
>
> This series first improves the readability of this driver, then adds
> support for multi-channel thermal IPs, and finally adds support for the
> hardware overheat interrupt. The bindings and the device-trees are
> updated accordingly.
>
> Please note that the thermal IP raises SEI interrupts, from which the
> support as just been contributed and not merged yet. Applying the last
> DT patches referring to the 'sei' and 'icu_sei' nodes will require this
> feature [1] to have been accepted first.
>
> [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2018-April/572852.html
>
> Thank you,
> Miqu?l
>
>
> Miquel Raynal (27):
> thermal: armada: add a function that sanitizes the thermal zone name
> thermal: armada: remove useless register accesses
> thermal: armada: remove misleading comments
> thermal: armada: rename the initialization routine
> thermal: armada: dissociate a380 and cp110 ->init() hooks
> thermal: armada: average over samples to avoid glitches
> thermal: armada: convert driver to syscon register accesses
> thermal: armada: use the resource managed registration helper
> alternative
> thermal: armada: add multi-channel sensors support
> thermal: armada: remove sensors validity from the IP initialization
> thermal: armada: move validity check out of the read function
> thermal: armada: get rid of the ->is_valid() pointer
> thermal: armada: add overheat interrupt support
> dt-bindings: cp110: rename cp110 syscon file
> dt-bindings: ap806: prepare the syscon file to list other syscons
> nodes
> dt-bindings: cp110: prepare the syscon file to list other syscons
> nodes
> dt-bindings: ap806: add the thermal node in the syscon file
> dt-bindings: cp110: update documentation since DT de-duplication
> dt-bindings: cp110: add the thermal node in the syscon file
> dt-bindings: thermal: armada: add reference to new bindings
> arm64: dts: marvell: rename ap806 syscon node
> arm64: dts: marvell: move AP806/CP110 thermal nodes into a new syscon
> arm64: dts: marvell: add thermal-zone node in ap806 DTSI file
> arm64: dts: marvell: add macro to make distinction between node names
> arm64: dts: marvell: add thermal-zone node in cp110 DTSI file
> arm64: dts: marvell: add interrupt support to ap806 thermal node
> arm64: dts: marvell: add interrupt support to cp110 thermal node
>
> .../arm/marvell/ap806-system-controller.txt | 55 +-
> ...controller0.txt => cp110-system-controller.txt} | 66 +-
> .../devicetree/bindings/thermal/armada-thermal.txt | 5 +
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 85 +-
> arch/arm64/boot/dts/marvell/armada-common.dtsi | 1 +
> arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 45 +-
> drivers/thermal/armada_thermal.c | 875 ++++++++++++++++++---
> 7 files changed, 976 insertions(+), 156 deletions(-)
> rename Documentation/devicetree/bindings/arm/marvell/{cp110-system-controller0.txt => cp110-system-controller.txt} (83%)
What is the status of this series?
I am especially interested in the dt part.
Do you expect sending a new series modifying them?
Gregory
>
> --
> 2.14.1
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply
* [PATCH] arm64: dts: juno: fix graph node unit addresses for coresight components
From: Mathieu Poirier @ 2018-05-16 17:29 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <eba4cddf-f668-a5e1-acea-5e6538c230f0@arm.com>
On 16 May 2018 at 05:49, Sudeep Holla <sudeep.holla@arm.com> wrote:
>
>
> On 16/05/18 12:23, Suzuki K Poulose wrote:
>> On 05/16/2018 11:34 AM, Sudeep Holla wrote:
>
> [..]
>
>>> Hi Suzuki/Mathieu,
>>>
>>> I did a quick scan @ drivers/hwtracing/coresight/of_coresight.c to
>>> check if reg field is being used or not and whether this change
>>> causes any regression. I don't think so, but I may be wrong, let me
>>> know.
>>
>> Unfortunately, I think this would break the components like funnel,
>> where we need the input port number for the connected master to enable
>> the port. Similarly for the output port number for master components in
>> the paths. I have a set of patches which address this by taking care of
>> the port number order to find out the hardware port number.
>>
>
> Ah ok, I now see of_graph_parse_endpoint, sorry for missing that.
The problem is not with of_graph_parse_endpoint(), that will work just
fine. In fact you can add whatever number you want there without
impact on how devices see each other in the framework. The problem is
that the port numbering doesn't reflect the HW layout anymore and as
such you can't rely on the port value when configuring the HW.
>
>> I will dust it up and send it. That would bring up another important
>> question.
>>
>
> Cool
>
>> How do we deal with the change in the port number scheme ? e.g, should
>> the new kernel support DTBs with old scheme ?
>
DT files following the old scheme will spew out warnings like we're
getting on Juno and are bound to be fixed.
> IIUC, that's needed for backward compatibility as it was used schema.
> Again I may be wrong.
>
>> If so, how do we specify that the DT uses new scheme.
>
> Perhaps, add something to indicate the change in numbering scheme ?
The current customers should be moved to the new scheme. That way we
don't have to support two different DT scheme (where one will die
eventually).
>
> --
> Regards,
> Sudeep
^ permalink raw reply
* vm_fault_t conversion, for real
From: Christoph Hellwig @ 2018-05-16 17:32 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516132256.GG20670@bombadil.infradead.org>
On Wed, May 16, 2018 at 06:22:56AM -0700, Matthew Wilcox wrote:
> Perhaps you should try being less of an arsehole if you don't want to
> get yelled at? I don't mind when you're an arsehole towards me, but I
> do mind when you're an arsehole towards newcomers. How are we supposed
> to attract and retain new maintainers when you're so rude?
*plonk* The only one I'm seeing being extremely rude here is you.
^ permalink raw reply
* [PATCH v6 1/2] dt-bindings: Documentation for qcom, llcc
From: rishabhb at codeaurora.org @ 2018-05-16 17:33 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <152649021310.210890.14841324536807182632@swboyd.mtv.corp.google.com>
On 2018-05-16 10:03, Stephen Boyd wrote:
> Quoting Rishabh Bhatnagar (2018-05-08 13:22:00)
>> diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> new file mode 100644
>> index 0000000..a586a17
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
>> @@ -0,0 +1,32 @@
>> +== Introduction==
>> +
>> +LLCC (Last Level Cache Controller) provides last level of cache
>> memory in SOC,
>> +that can be shared by multiple clients. Clients here are different
>> cores in the
>> +SOC, the idea is to minimize the local caches at the clients and
>> migrate to
>> +common pool of memory. Cache memory is divided into partitions called
>> slices
>> +which are assigned to clients. Clients can query the slice details,
>> activate
>> +and deactivate them.
>> +
>> +Properties:
>> +- compatible:
>> + Usage: required
>> + Value type: <string>
>> + Definition: must be "qcom,sdm845-llcc"
>> +
>> +- reg:
>> + Usage: required
>> + Value Type: <prop-encoded-array>
>> + Definition: Start address and the range of the LLCC registers.
>
> Start address and size?
>
Yes i'll change it to Start address and size of the register region.
>> +
>> +- max-slices:
>> + usage: required
>> + Value Type: <u32>
>> + Definition: Number of cache slices supported by hardware
>> +
>> +Example:
>> +
>> + llcc: qcom,llcc at 1100000 {
>
> cache-controller at 1100000 ?
>
We have tried to use consistent naming convention as in llcc_*
everywhere.
Using cache-controller will mix and match the naming convention. Also in
the documentation it is explained what llcc is and its full form.
>> + compatible = "qcom,sdm845-llcc";
>> + reg = <0x1100000 0x250000>;
>> + max-slices = <32>;
>> + };
>> --
^ permalink raw reply
* [PATCH 14/14] mm: turn on vm_fault_t type checking
From: Christoph Hellwig @ 2018-05-16 17:34 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180516150829.GA4904@magnolia>
On Wed, May 16, 2018 at 08:08:29AM -0700, Darrick J. Wong wrote:
> Uh, we're changing function signatures /and/ redefinining vm_fault_t?
> All in the same 90K patch?
>
> I /was/ expecting a series of "convert XXXXX and all callers/users"
> patches followed by a trivial one to switch the definition, not a giant
> pile of change. FWIW I don't mind so much if you make a patch
> containing a change for some super-common primitive and a hojillion
> little diff hunks tree-wide, but only one logical change at a time for a
> big patch, please...
>
> I quite prefer seeing the whole series from start to finish all packaged
> up in one series, but wow this was overwhelming. :/
Another vote to split the change of the typedef, ok I get the message..
^ permalink raw reply
* [PATCH] arm64: dts: juno: fix graph node unit addresses for coresight components
From: Sudeep Holla @ 2018-05-16 17:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CANLsYkyi+m_uQydSWZkf_e1PNSoU-n1rLixuJ0+P9G8hpm68TA@mail.gmail.com>
On 16/05/18 18:29, Mathieu Poirier wrote:
> On 16 May 2018 at 05:49, Sudeep Holla <sudeep.holla@arm.com> wrote:
>>
>>
>> On 16/05/18 12:23, Suzuki K Poulose wrote:
>>> On 05/16/2018 11:34 AM, Sudeep Holla wrote:
>>
>> [..]
>>
>>>> Hi Suzuki/Mathieu,
>>>>
>>>> I did a quick scan @ drivers/hwtracing/coresight/of_coresight.c to
>>>> check if reg field is being used or not and whether this change
>>>> causes any regression. I don't think so, but I may be wrong, let me
>>>> know.
>>>
>>> Unfortunately, I think this would break the components like funnel,
>>> where we need the input port number for the connected master to enable
>>> the port. Similarly for the output port number for master components in
>>> the paths. I have a set of patches which address this by taking care of
>>> the port number order to find out the hardware port number.
>>>
>>
>> Ah ok, I now see of_graph_parse_endpoint, sorry for missing that.
>
> The problem is not with of_graph_parse_endpoint(), that will work just
> fine. In fact you can add whatever number you want there without
> impact on how devices see each other in the framework. The problem is
> that the port numbering doesn't reflect the HW layout anymore and as
> such you can't rely on the port value when configuring the HW.
>
Exactly, I had a chat with Suzuki. One option is to introduce new hwid
field to fix that. If the field is present, it will be used and reg
field will be ignored. In that way, you won't break the compatibility.
Just my thoughts. I am not sure if we need to support old kernel with
updated DTs though. That may be difficult.
>>
>>> I will dust it up and send it. That would bring up another important
>>> question.
>>>
>>
>> Cool
>>
>>> How do we deal with the change in the port number scheme ? e.g, should
>>> the new kernel support DTBs with old scheme ?
>>
>
> DT files following the old scheme will spew out warnings like we're
> getting on Juno and are bound to be fixed.
>
True, they can pick up the new changes too along with changes just
fixing the warning.
>> IIUC, that's needed for backward compatibility as it was used schema.
>> Again I may be wrong.
>>
>>> If so, how do we specify that the DT uses new scheme.
>>
>> Perhaps, add something to indicate the change in numbering scheme ?
>
> The current customers should be moved to the new scheme. That way we
> don't have to support two different DT scheme (where one will die
> eventually).
>
But the problem is if someone has DT which can't be modified and we move
to new scheme only in the kernel, then they will see regression on their
platforms. If that's fine, it simplifies things a lot. But I am not so
sure of that ...
--
Regards,
Sudeep
^ permalink raw reply
* [PATCH 0/2] ARM: Update multi_v7_defconfig and add add Marvel NAND
From: Gregory CLEMENT @ 2018-05-16 17:42 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180424081528.25883-1-gregory.clement@bootlin.com>
Hi,
On mar., avril 24 2018, Gregory CLEMENT <gregory.clement@bootlin.com> wrote:
> Hi,
>
> While adding Marvel NAND controller support in to the
> multi_v7_defconfig, I noticed that this file had greatly diverged, so
> the first patch updates it.
>
> Maybe this first patch should be merged in the current rc to reduce
> the number of merge conflict.
>
> Gregpry
>
> Gregory CLEMENT (2):
> ARM: multi_v7_defconfig: Update with current configuration
> ARM: multi_v7_defconfig: Add Marvel NAND controller support
Both applied on mvebu/arm with fixes reported by Thomas.
Gregory
>
> arch/arm/configs/multi_v7_defconfig | 369 +++++++++++++++---------------------
> 1 file changed, 153 insertions(+), 216 deletions(-)
>
> --
> 2.16.3
>
--
Gregory Clement, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
http://bootlin.com
^ permalink raw reply
* [PATCH v7 0/2] SDM845 System Cache Driver
From: Rishabh Bhatnagar @ 2018-05-16 17:43 UTC (permalink / raw)
To: linux-arm-kernel
This series implements system cache or LLCC(Last Level Cache Controller)
driver for SDM845 SOC. The purpose of the driver is to partition the
system cache and program the settings such as priortiy, lines to probe
while doing a look up in the system cache, low power related settings etc.
The partitions are called cache slices. Each cache slice is associated
with size and SCID(System Cache ID). The driver also provides API for
clients to query the cache slice details,activate and deactivate them.
The driver can be broadly classified into:
* SOC specific driver: llcc-sdm845.c: Cache partitioning and cache slice
properties for usecases on sdm845 that need to use system cache.
* API : llcc-slice.c: Exports APIs to clients to query cache slice details,
activate and deactivate cache slices.
Changes since v6:
* Remove the max-slices property from DT.
* Make client's slice_ids as macros.
* Unlock mutex while returning from function in case of error.
Changes since v5:
* Remove client information from DT.
* Make the llcc driver data as global.
* Check return value of llcc_update_act_ctrl function
* Change error returned from -EFAULT to -EINVAL
Changes since v4:
* Remove null pointer checks as per comments.
* Remove extra blank lines.
Changes since v3:
* Use the regmap_read_poll_timeout function
* Check for regmap read/write errors.
* Remove memory barrier after regmap write
* Derive memory bank offsets using stride macro variable
* Remove debug statements from code
* Remove the qcom_llcc_remove function
* Use if IS_ENABLED in place of ifdef for built-in module
* Change EXPORT_SYMBOL to EXPORT_SYMBOL_GPL
* Remove unnecessary free functions
* Change the variable names as per review comments
Changes since v2:
* Corrected the Makefile to fix compilation.
Changes since v1:
* Added Makefile and Kconfig.
Changes since v0:
* Removed the syscon and simple-mfd approach
* Updated the device tree nodes to mention LLCC as a single HW block
* Moved llcc bank offsets from device tree and handled the offset
in the driver.
ckadabi at codeaurora.org (2):
dt-bindings: Documentation for qcom, llcc
drivers: soc: Add LLCC driver
.../devicetree/bindings/arm/msm/qcom,llcc.txt | 26 ++
drivers/soc/qcom/Kconfig | 17 ++
drivers/soc/qcom/Makefile | 2 +
drivers/soc/qcom/llcc-sdm845.c | 106 +++++++
drivers/soc/qcom/llcc-slice.c | 337 +++++++++++++++++++++
include/linux/soc/qcom/llcc-qcom.h | 180 +++++++++++
6 files changed, 668 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,llcc.txt
create mode 100644 drivers/soc/qcom/llcc-sdm845.c
create mode 100644 drivers/soc/qcom/llcc-slice.c
create mode 100644 include/linux/soc/qcom/llcc-qcom.h
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
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