* [PATCH V7 11/12] ARM: dts: ipq8074: Add pcie nodes
From: Sricharan R @ 2018-05-18 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526631565-9972-1-git-send-email-sricharan@codeaurora.org>
The driver/phy support for ipq8074 is available now.
So enabling the nodes in DT.
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 157 +++++++++++++++++++++++++++++++++-
1 file changed, 156 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index bd58ab4..1822698 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -24,7 +24,7 @@
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
- pinctrl at 1000000 {
+ tlmm: pinctrl at 1000000 {
compatible = "qcom,ipq8074-pinctrl";
reg = <0x1000000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
@@ -278,6 +278,161 @@
pinctrl-names = "default";
status = "disabled";
};
+
+ pcie_phy0: phy at 86000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x86000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE0_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy0_pipe_clk";
+
+ resets = <&gcc GCC_PCIE0_PHY_BCR>,
+ <&gcc GCC_PCIE0PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie0: pci at 20000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x20000000 0xf1d
+ 0x20000f20 0xa8
+ 0x80000 0x2000
+ 0x20100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <0>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy0>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x20200000 0x20200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x20300000 0x20300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 75
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 78
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 79
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 83
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>,
+ <&gcc GCC_PCIE0_AXI_M_CLK>,
+ <&gcc GCC_PCIE0_AXI_S_CLK>,
+ <&gcc GCC_PCIE0_AHB_CLK>,
+ <&gcc GCC_PCIE0_AUX_CLK>;
+
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE0_PIPE_ARES>,
+ <&gcc GCC_PCIE0_SLEEP_ARES>,
+ <&gcc GCC_PCIE0_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE0_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE0_AHB_ARES>,
+ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
+
+ pcie_phy1: phy at 8e000 {
+ compatible = "qcom,ipq8074-qmp-pcie-phy";
+ reg = <0x8e000 0x1000>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_PCIE1_PIPE_CLK>;
+ clock-names = "pipe_clk";
+ clock-output-names = "pcie20_phy1_pipe_clk";
+
+ resets = <&gcc GCC_PCIE1_PHY_BCR>,
+ <&gcc GCC_PCIE1PHY_PHY_BCR>;
+ reset-names = "phy",
+ "common";
+ status = "disabled";
+ };
+
+ pcie1: pci at 10000000 {
+ compatible = "qcom,pcie-ipq8074";
+ reg = <0x10000000 0xf1d
+ 0x10000f20 0xa8
+ 0x88000 0x2000
+ 0x10100000 0x1000>;
+ reg-names = "dbi", "elbi", "parf", "config";
+ device_type = "pci";
+ linux,pci-domain = <1>;
+ bus-range = <0x00 0xff>;
+ num-lanes = <1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ phys = <&pcie_phy1>;
+ phy-names = "pciephy";
+
+ ranges = <0x81000000 0 0x10200000 0x10200000
+ 0 0x100000 /* downstream I/O */
+ 0x82000000 0 0x10300000 0x10300000
+ 0 0xd00000>; /* non-prefetchable memory */
+
+ interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi";
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 142
+ IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+ <0 0 0 2 &intc 0 143
+ IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+ <0 0 0 3 &intc 0 144
+ IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+ <0 0 0 4 &intc 0 145
+ IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+ clocks = <&gcc GCC_SYS_NOC_PCIE1_AXI_CLK>,
+ <&gcc GCC_PCIE1_AXI_M_CLK>,
+ <&gcc GCC_PCIE1_AXI_S_CLK>,
+ <&gcc GCC_PCIE1_AHB_CLK>,
+ <&gcc GCC_PCIE1_AUX_CLK>;
+ clock-names = "iface",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "aux";
+ resets = <&gcc GCC_PCIE1_PIPE_ARES>,
+ <&gcc GCC_PCIE1_SLEEP_ARES>,
+ <&gcc GCC_PCIE1_CORE_STICKY_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_ARES>,
+ <&gcc GCC_PCIE1_AXI_SLAVE_ARES>,
+ <&gcc GCC_PCIE1_AHB_ARES>,
+ <&gcc GCC_PCIE1_AXI_MASTER_STICKY_ARES>;
+ reset-names = "pipe",
+ "sleep",
+ "sticky",
+ "axi_m",
+ "axi_s",
+ "ahb",
+ "axi_m_sticky";
+ status = "disabled";
+ };
};
cpus {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [PATCH V7 12/12] ARM: dts: ipq8074: Enable few peripherals for hk01 board
From: Sricharan R @ 2018-05-18 8:19 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526631565-9972-1-git-send-email-sricharan@codeaurora.org>
Reviewed-by: Abhishek Sahu <absahu@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
---
arch/arm64/boot/dts/qcom/ipq8074-hk01.dts | 54 +++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
index 72c5b4a3..c13ddee 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
+++ b/arch/arm64/boot/dts/qcom/ipq8074-hk01.dts
@@ -21,6 +21,7 @@
aliases {
serial0 = &blsp1_uart5;
+ serial1 = &blsp1_uart3;
};
chosen {
@@ -36,5 +37,58 @@
serial at 78b3000 {
status = "ok";
};
+
+ spi at 78b5000 {
+ status = "ok";
+
+ m25p80 at 0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+ };
+
+ serial at 78b1000 {
+ status = "ok";
+ };
+
+ i2c at 78b6000 {
+ status = "ok";
+ };
+
+ dma at 7984000 {
+ status = "ok";
+ };
+
+ nand at 79b0000 {
+ status = "ok";
+
+ nand at 0 {
+ reg = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ nand-bus-width = <8>;
+ };
+ };
+
+ phy at 86000 {
+ status = "ok";
+ };
+
+ phy at 8e000 {
+ status = "ok";
+ };
+
+ pci at 20000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 58 0x1>;
+ };
+
+ pci at 10000000 {
+ status = "ok";
+ perst-gpio = <&tlmm 61 0x1>;
+ };
};
};
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related
* [RFC PATCH] drm/rockchip: update cursors asynchronously through atomic.
From: Enric Balletbo i Serra @ 2018-05-18 8:25 UTC (permalink / raw)
To: linux-arm-kernel
Add support to async updates of cursors by using the new atomic
interface for that.
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
---
I am sending this as RFC because I still don't have a deep knowledge of
the hw and I am not sure if the vop_plane_update function can be reused
in both cases, atomic_updates and atomic_async_updates. I think that
someone with more knowledge should take a look. The patch was tested on
a Samsung Chromebook Plus in two ways.
1. Running all igt kms_cursor_legacy and kms_atomic at plane_cursor_legacy
tests and see that there is no regression after the patch.
2. Running weston using the atomic API.
Best regards,
Enric
drivers/gpu/drm/rockchip/rockchip_drm_vop.c | 79 ++++++++++++++++-----
1 file changed, 63 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
index 53d4afe15278..a89214541439 100644
--- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
+++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.c
@@ -688,8 +688,7 @@ static void vop_plane_atomic_disable(struct drm_plane *plane,
spin_unlock(&vop->reg_lock);
}
-static void vop_plane_atomic_update(struct drm_plane *plane,
- struct drm_plane_state *old_state)
+static void vop_plane_update(struct drm_plane *plane)
{
struct drm_plane_state *state = plane->state;
struct drm_crtc *crtc = state->crtc;
@@ -710,20 +709,6 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
bool rb_swap;
int format;
- /*
- * can't update plane when vop is disabled.
- */
- if (WARN_ON(!crtc))
- return;
-
- if (WARN_ON(!vop->is_enabled))
- return;
-
- if (!state->visible) {
- vop_plane_atomic_disable(plane, old_state);
- return;
- }
-
obj = rockchip_fb_get_gem_obj(fb, 0);
rk_obj = to_rockchip_obj(obj);
@@ -794,10 +779,72 @@ static void vop_plane_atomic_update(struct drm_plane *plane,
spin_unlock(&vop->reg_lock);
}
+static void vop_plane_atomic_update(struct drm_plane *plane,
+ struct drm_plane_state *old_state)
+{
+ struct drm_plane_state *state = plane->state;
+ struct vop *vop = to_vop(state->crtc);
+
+ /*
+ * can't update plane when vop is disabled.
+ */
+ if (WARN_ON(!state->crtc))
+ return;
+
+ if (WARN_ON(!vop->is_enabled))
+ return;
+
+ if (!state->visible) {
+ vop_plane_atomic_disable(plane, old_state);
+ return;
+ }
+
+ vop_plane_update(plane);
+}
+
+static int vop_plane_atomic_async_check(struct drm_plane *plane,
+ struct drm_plane_state *state)
+{
+ struct drm_crtc_state *crtc_state;
+
+ crtc_state = drm_atomic_get_existing_crtc_state(state->state,
+ state->crtc);
+ if (WARN_ON(!crtc_state))
+ return -EINVAL;
+
+ if (!crtc_state->active)
+ return -EINVAL;
+
+ if (plane->state->crtc != state->crtc ||
+ plane->state->src_w != state->src_w ||
+ plane->state->src_h != state->src_h ||
+ plane->state->crtc_w != state->crtc_w ||
+ plane->state->crtc_h != state->crtc_h ||
+ !plane->state->fb ||
+ plane->state->fb != state->fb)
+ return -EINVAL;
+
+ return 0;
+}
+
+static void vop_plane_atomic_async_update(struct drm_plane *plane,
+ struct drm_plane_state *new_state)
+{
+ plane->state->src_x = new_state->src_x;
+ plane->state->src_y = new_state->src_y;
+ plane->state->crtc_x = new_state->crtc_x;
+ plane->state->crtc_y = new_state->crtc_y;
+ plane->state->fb = new_state->fb;
+
+ vop_plane_update(plane);
+}
+
static const struct drm_plane_helper_funcs plane_helper_funcs = {
.atomic_check = vop_plane_atomic_check,
.atomic_update = vop_plane_atomic_update,
.atomic_disable = vop_plane_atomic_disable,
+ .atomic_async_check = vop_plane_atomic_async_check,
+ .atomic_async_update = vop_plane_atomic_async_update,
};
static const struct drm_plane_funcs vop_plane_funcs = {
--
2.17.0
^ permalink raw reply related
* [PATCH 4.9 27/33] futex: Remove duplicated code and fix undefined behaviour
From: Jiri Slaby @ 2018-05-18 8:30 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518081536.166573281@linuxfoundation.org>
On 05/18/2018, 10:16 AM, Greg Kroah-Hartman wrote:
> 4.9-stable review patch. If anyone has any objections, please let me know.
>
> ------------------
>
> From: Jiri Slaby <jslaby@suse.cz>
>
> commit 30d6e0a4190d37740e9447e4e4815f06992dd8c3 upstream.
...
> --- a/kernel/futex.c
> +++ b/kernel/futex.c
> @@ -1458,6 +1458,45 @@ out:
> return ret;
> }
>
> +static int futex_atomic_op_inuser(unsigned int encoded_op, u32 __user *uaddr)
> +{
> + unsigned int op = (encoded_op & 0x70000000) >> 28;
> + unsigned int cmp = (encoded_op & 0x0f000000) >> 24;
> + int oparg = sign_extend32((encoded_op & 0x00fff000) >> 12, 12);
> + int cmparg = sign_extend32(encoded_op & 0x00000fff, 12);
12 is wrong here ? wherever you apply this, you need also a follow-up fix:
commit d70ef22892ed6c066e51e118b225923c9b74af34
Author: Jiri Slaby <jslaby@suse.cz>
Date: Thu Nov 30 15:35:44 2017 +0100
futex: futex_wake_op, fix sign_extend32 sign bits
thanks,
--
js
suse labs
^ permalink raw reply
* [PATCH 2/4] omap2: clockdomain: Inroduce cpu_pm notifiers for context save/restore
From: Tero Kristo @ 2018-05-18 8:38 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <18c013bb-4f3b-81af-f565-825513e2b501@ti.com>
On 18/05/18 08:57, Keerthy wrote:
>
>
> On Friday 18 May 2018 03:13 AM, Tony Lindgren wrote:
>> * Keerthy <j-keerthy@ti.com> [180516 15:21]:
>>> Inroduce cpu_pm notifiers for context save/restore. This will be
>>> needed for am43xx family in case of rtc only mode with ddr in
>>> self-refresh.
>> ...
>>> +static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
>>> +{
>>> + switch (cmd) {
>>> + case CPU_CLUSTER_PM_ENTER:
>>> + if (enable_off_mode)
>>> + clkdm_save_context();
>>> + break;
>>> + case CPU_CLUSTER_PM_EXIT:
>>> + if (enable_off_mode)
>>> + clkdm_restore_context();
>>> + break;
>>> + }
>>> +
>>> + return NOTIFY_OK;
>>> +}
>>
>> Can you do this too only on suspend instead of the cpu notifier?
>> If you need to call this eventually from cpuidle also then yeah
>> the notifier makes sense.
>
> Clockdomain under omap2 does not have suspend/resume calls as its still
> not a driver. The initial version of this patch had save/restore calls
> directly from pm33xx-core during suspend/resume platform ops are called.
>
> Are you suggesting that?
I think using cpu notifiers would help in eventual transition of this
under drivers also, as this doesn't need any custom interfaces to be
exported around. And, as it seems now, this is only needed for AM43xx at
the moment, no other SoCs need this for any purpose, even if device off
would be implemented. Only exception would be if we want to implement
RTC+DDR sort of functionality on any other SoC.
-Tero
--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
^ permalink raw reply
* [PATCH 1/2] ARM: OMAP2+: prm44xx: Introduce context save/restore for am43 PRCM IO
From: Keerthy @ 2018-05-18 8:40 UTC (permalink / raw)
To: linux-arm-kernel
From: Dave Gerlach <d-gerlach@ti.com>
There are two registers on am43x needed for IO daisy chain wake to work
properly, however currently after an RTC+DDR cycle they are lost. We
must take care to save and restore these before and after entering RTC
mode otherwise IO daisy chain wake will stop working from DeepSleep
after resuming.
Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
arch/arm/mach-omap2/prm44xx.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index acb9593..0a4aa90 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -57,6 +57,13 @@
.reconfigure_io_chain = &omap44xx_prm_reconfigure_io_chain,
};
+struct omap_prm_irq_context {
+ unsigned long irq_enable;
+ unsigned long pm_ctrl;
+};
+
+static struct omap_prm_irq_context omap_prm_context;
+
/*
* omap44xx_prm_reset_src_map - map from bits in the PRM_RSTST
* hardware register (which are specific to OMAP44xx SoCs) to reset
@@ -689,6 +696,28 @@ struct pwrdm_ops omap4_pwrdm_operations = {
static int omap44xx_prm_late_init(void);
+void prm_save_context(void)
+{
+ omap_prm_context.irq_enable =
+ omap4_prm_read_inst_reg(AM43XX_PRM_OCP_SOCKET_INST,
+ omap4_prcm_irq_setup.mask);
+
+ omap_prm_context.pm_ctrl =
+ omap4_prm_read_inst_reg(AM43XX_PRM_DEVICE_INST,
+ omap4_prcm_irq_setup.pm_ctrl);
+}
+
+void prm_restore_context(void)
+{
+ omap4_prm_write_inst_reg(omap_prm_context.irq_enable,
+ OMAP4430_PRM_OCP_SOCKET_INST,
+ omap4_prcm_irq_setup.mask);
+
+ omap4_prm_write_inst_reg(omap_prm_context.pm_ctrl,
+ AM43XX_PRM_DEVICE_INST,
+ omap4_prcm_irq_setup.pm_ctrl);
+}
+
/*
* XXX document
*/
--
1.9.1
^ permalink raw reply related
* [PATCH 2/2] ARM: mach-omap2: prm44xx: Inroduce cpu_pm notifiers for context save/restore
From: Keerthy @ 2018-05-18 8:40 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526632822-26049-1-git-send-email-j-keerthy@ti.com>
Inroduce cpu_pm notifiers for context save/restore. This will be
needed for am43xx family in case of rtc only mode with ddr in
self-refresh.
Signed-off-by: Keerthy <j-keerthy@ti.com>
---
arch/arm/mach-omap2/prm44xx.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/arm/mach-omap2/prm44xx.c b/arch/arm/mach-omap2/prm44xx.c
index 0a4aa90..5478c71 100644
--- a/arch/arm/mach-omap2/prm44xx.c
+++ b/arch/arm/mach-omap2/prm44xx.c
@@ -12,6 +12,7 @@
* published by the Free Software Foundation.
*/
+#include <linux/cpu_pm.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/errno.h>
@@ -30,6 +31,7 @@
#include "prcm44xx.h"
#include "prminst44xx.h"
#include "powerdomain.h"
+#include "pm.h"
/* Static data */
@@ -718,6 +720,22 @@ void prm_restore_context(void)
omap4_prcm_irq_setup.pm_ctrl);
}
+static int cpu_notifier(struct notifier_block *nb, unsigned long cmd, void *v)
+{
+ switch (cmd) {
+ case CPU_CLUSTER_PM_ENTER:
+ if (enable_off_mode)
+ prm_save_context();
+ break;
+ case CPU_CLUSTER_PM_EXIT:
+ if (enable_off_mode)
+ prm_restore_context();
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
/*
* XXX document
*/
@@ -738,6 +756,7 @@ void prm_restore_context(void)
int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
{
+ static struct notifier_block nb;
omap_prm_base_init();
prm_init_data = data;
@@ -759,6 +778,12 @@ int __init omap44xx_prm_init(const struct omap_prcm_init_data *data)
omap4_prcm_irq_setup.mask = AM43XX_PRM_IRQENABLE_MPU_OFFSET;
}
+ /* Only AM43XX can lose prm context during rtc-ddr suspend */
+ if (soc_is_am43xx()) {
+ nb.notifier_call = cpu_notifier;
+ cpu_pm_register_notifier(&nb);
+ }
+
return prm_register(&omap44xx_prm_ll_data);
}
--
1.9.1
^ permalink raw reply related
* [PATCH] PM / runtime: Fixup reference counting of device link suppliers at probe
From: Ulf Hansson @ 2018-05-18 8:48 UTC (permalink / raw)
To: linux-arm-kernel
In the driver core, before it invokes really_probe() it runtime resumes the
suppliers for the device via calling pm_runtime_get_suppliers(), which also
increases the runtime PM usage count for each of the available supplier.
This makes sense, as to be able to allow the consumer device to be probed
by its driver. However, if the driver decides to add a new supplier link
during ->probe(), hence updating the list of suppliers, the following call
to pm_runtime_put_suppliers(), invoked after really_probe() in the driver
core, we get into trouble.
More precisely, pm_runtime_put() gets called also for the new supplier(s),
which is wrong as the driver core, didn't trigger pm_runtime_get_sync() to
be called for it in the first place. In other words, the new supplier may
be runtime suspended even in cases when it shouldn't.
Fix this behaviour, by runtime resume suppliers according to the same
conditions as managed by the runtime PM core, when runtime resume callbacks
are being invoked.
Additionally, don't try to runtime suspend any of the suppliers after
really_probe(), but instead rely on that to happen via the consumer device,
when it becomes runtime suspended.
Fixes: 21d5c57b3726 ("PM / runtime: Use device links")
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
---
An optional solution (requires to add code, rather than remove), in case we
think it's not suffient to rely on the consumer device to be runtime suspended
after probe.
This could be done via adding a new bool member to the struct device_link, and
set it from pm_runtime_get_suppliers(). Check it at pm_runtime_put_suppliers(),
and only call pm_runtime_put() on those suppliers that has it set.
---
drivers/base/dd.c | 3 +--
drivers/base/power/runtime.c | 27 +++------------------------
include/linux/pm_runtime.h | 6 ++----
3 files changed, 6 insertions(+), 30 deletions(-)
diff --git a/drivers/base/dd.c b/drivers/base/dd.c
index 10454fe..a41c91b 100644
--- a/drivers/base/dd.c
+++ b/drivers/base/dd.c
@@ -580,7 +580,7 @@ int driver_probe_device(struct device_driver *drv, struct device *dev)
pr_debug("bus: '%s': %s: matched device %s with driver %s\n",
drv->bus->name, __func__, dev_name(dev), drv->name);
- pm_runtime_get_suppliers(dev);
+ pm_runtime_resume_suppliers(dev);
if (dev->parent)
pm_runtime_get_sync(dev->parent);
@@ -591,7 +591,6 @@ int driver_probe_device(struct device_driver *drv, struct device *dev)
if (dev->parent)
pm_runtime_put(dev->parent);
- pm_runtime_put_suppliers(dev);
return ret;
}
diff --git a/drivers/base/power/runtime.c b/drivers/base/power/runtime.c
index 8bef3cb..6f4f50e 100644
--- a/drivers/base/power/runtime.c
+++ b/drivers/base/power/runtime.c
@@ -1563,37 +1563,16 @@ void pm_runtime_clean_up_links(struct device *dev)
}
/**
- * pm_runtime_get_suppliers - Resume and reference-count supplier devices.
+ * pm_runtime_resume_suppliers - Resume supplier devices.
* @dev: Consumer device.
*/
-void pm_runtime_get_suppliers(struct device *dev)
+void pm_runtime_resume_suppliers(struct device *dev)
{
- struct device_link *link;
int idx;
idx = device_links_read_lock();
- list_for_each_entry_rcu(link, &dev->links.suppliers, c_node)
- if (link->flags & DL_FLAG_PM_RUNTIME)
- pm_runtime_get_sync(link->supplier);
-
- device_links_read_unlock(idx);
-}
-
-/**
- * pm_runtime_put_suppliers - Drop references to supplier devices.
- * @dev: Consumer device.
- */
-void pm_runtime_put_suppliers(struct device *dev)
-{
- struct device_link *link;
- int idx;
-
- idx = device_links_read_lock();
-
- list_for_each_entry_rcu(link, &dev->links.suppliers, c_node)
- if (link->flags & DL_FLAG_PM_RUNTIME)
- pm_runtime_put(link->supplier);
+ rpm_get_suppliers(dev);
device_links_read_unlock(idx);
}
diff --git a/include/linux/pm_runtime.h b/include/linux/pm_runtime.h
index f0fc470..db5dbbf 100644
--- a/include/linux/pm_runtime.h
+++ b/include/linux/pm_runtime.h
@@ -56,8 +56,7 @@ extern void pm_runtime_update_max_time_suspended(struct device *dev,
s64 delta_ns);
extern void pm_runtime_set_memalloc_noio(struct device *dev, bool enable);
extern void pm_runtime_clean_up_links(struct device *dev);
-extern void pm_runtime_get_suppliers(struct device *dev);
-extern void pm_runtime_put_suppliers(struct device *dev);
+extern void pm_runtime_resume_suppliers(struct device *dev);
extern void pm_runtime_new_link(struct device *dev);
extern void pm_runtime_drop_link(struct device *dev);
@@ -173,8 +172,7 @@ static inline unsigned long pm_runtime_autosuspend_expiration(
static inline void pm_runtime_set_memalloc_noio(struct device *dev,
bool enable){}
static inline void pm_runtime_clean_up_links(struct device *dev) {}
-static inline void pm_runtime_get_suppliers(struct device *dev) {}
-static inline void pm_runtime_put_suppliers(struct device *dev) {}
+static inline void pm_runtime_resume_suppliers(struct device *dev) {}
static inline void pm_runtime_new_link(struct device *dev) {}
static inline void pm_runtime_drop_link(struct device *dev) {}
--
2.7.4
^ permalink raw reply related
* [PATCH v5 4/4] drm/rockchip: support dp training outside dp firmware
From: Heiko Stuebner @ 2018-05-18 8:52 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CA+ASDXN2LT6FcX_2-MM=Qu7cZOHwVK3+2rGDLGcC1SnY3BJaSw@mail.gmail.com>
Am Freitag, 18. Mai 2018, 03:45:46 CEST schrieb Brian Norris:
> On Thu, May 17, 2018 at 6:41 PM, hl <hl@rock-chips.com> wrote:
> > On Thursday, May 17, 2018 09:51 PM, Sean Paul wrote:
> >> On Thu, May 17, 2018 at 05:18:00PM +0800, Lin Huang wrote:
> >>> DP firmware uses fixed phy config values to do training, but some
> >>> boards need to adjust these values to fit for their unique hardware
> >>> design. So get phy config values from dts and use software link training
> >>> instead of relying on firmware, if software training fail, keep firmware
> >>> training as a fallback if sw training fails.
> >>>
> >>> Signed-off-by: Chris Zhong <zyw@rock-chips.com>
> >>> Signed-off-by: Lin Huang <hl@rock-chips.com>
> >>> ---
> >>> Changes in v2:
> >>> - update patch following Enric suggest
> >>> Changes in v3:
> >>> - use variable fw_training instead sw_training_success
> >>> - base on DP SPCE, if training fail use lower link rate to retry training
> >>> Changes in v4:
> >>> - improve cdn_dp_get_lower_link_rate() and cdn_dp_software_train_link() follow Sean suggest
> >>> Changes in v5:
> >>> - fix some whitespcae issue
> >>>
> >>> drivers/gpu/drm/rockchip/Makefile | 3 +-
> >>> drivers/gpu/drm/rockchip/cdn-dp-core.c | 24 +-
> >>> drivers/gpu/drm/rockchip/cdn-dp-core.h | 2 +
> >>> drivers/gpu/drm/rockchip/cdn-dp-link-training.c | 420 ++++++++++++++++++++++++
> >>> drivers/gpu/drm/rockchip/cdn-dp-reg.c | 31 +-
> >>> drivers/gpu/drm/rockchip/cdn-dp-reg.h | 38 ++-
> >>> 6 files changed, 505 insertions(+), 13 deletions(-)
> >>> create mode 100644 drivers/gpu/drm/rockchip/cdn-dp-link-training.c
> >>>
> ...
> >>> diff --git a/drivers/gpu/drm/rockchip/cdn-dp-link-training.c b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
> >>> new file mode 100644
> >>> index 0000000..73c3290
> >>> --- /dev/null
> >>> +++ b/drivers/gpu/drm/rockchip/cdn-dp-link-training.c
> >>> @@ -0,0 +1,420 @@
> >>> +// SPDX-License-Identifier: GPL-2.0
> >>> +/*
> >>> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> >>> + * Author: Chris Zhong <zyw@rock-chips.com>
> >>> + */
> >>> +
> >>> +#include <linux/device.h>
> >>> +#include <linux/delay.h>
> >>> +#include <linux/phy/phy.h>
> >>> +#include <soc/rockchip/rockchip_phy_typec.h>
> >>> +
> >>> +#include "cdn-dp-core.h"
> >>> +#include "cdn-dp-reg.h"
> >>> +
> >>> +static void cdn_dp_set_signal_levels(struct cdn_dp_device *dp)
> >>> +{
> >>> + struct cdn_dp_port *port = dp->port[dp->active_port];
> >>> + struct rockchip_typec_phy *tcphy = phy_get_drvdata(port->phy);
> >>
> >> You ignored Brian's comment on the previous patch:
> >> This is still antithetical to the PHY framework; you're assuming that
> >> this is a particular type of PHY here.
> >>
> >> FWIW, the mediatek drm driver also assumes a certain PHY type. A quick grep of
> >> drivers/ shows that the only other non-phy/ driver using this function
> >> (pinctrl-tegra-xusb.c) also casts it.
> >>
> >> Sean
> >
> > Thanks Sean, except phy framework have new API to handle it, i have not
> > idea how to do it in a better way.
>
> Well, if Mediatek can do it for their MIPI and HDMI, then maybe we just do it...
I'd think so too. This is in Rockchip-specific code so it will always be
possible to easily get the soc-type and thus phy-type, if that combination
really changes down the road.
Heiko
^ permalink raw reply
* [PATCH] clk: aspeed: Add 24MHz fixed clock
From: Lei YU @ 2018-05-18 8:57 UTC (permalink / raw)
To: linux-arm-kernel
Add a 24MHz fixed clock.
This clock will be used for certain devices, e.g. pwm.
Signed-off-by: Lei YU <mine260309@gmail.com>
---
drivers/clk/clk-aspeed.c | 9 ++++++++-
include/dt-bindings/clock/aspeed-clock.h | 1 +
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c
index 5eb50c3..4664088 100644
--- a/drivers/clk/clk-aspeed.c
+++ b/drivers/clk/clk-aspeed.c
@@ -14,7 +14,7 @@
#include <dt-bindings/clock/aspeed-clock.h>
-#define ASPEED_NUM_CLKS 35
+#define ASPEED_NUM_CLKS 36
#define ASPEED_RESET_CTRL 0x04
#define ASPEED_CLK_SELECTION 0x08
@@ -474,6 +474,13 @@ static int aspeed_clk_probe(struct platform_device *pdev)
return PTR_ERR(hw);
aspeed_clk_data->hws[ASPEED_CLK_BCLK] = hw;
+ /* Fixed 24MHz clock */
+ hw = clk_hw_register_fixed_rate(NULL, "fixed-24m", "clkin",
+ 0, 24000000);
+ if (IS_ERR(hw))
+ return PTR_ERR(hw);
+ aspeed_clk_data->hws[ASPEED_CLK_24M] = hw;
+
/*
* TODO: There are a number of clocks that not included in this driver
* as more information is required:
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index d3558d8..ff29d8e 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -38,6 +38,7 @@
#define ASPEED_CLK_MAC 32
#define ASPEED_CLK_BCLK 33
#define ASPEED_CLK_MPLL 34
+#define ASPEED_CLK_24M 35
#define ASPEED_RESET_XDMA 0
#define ASPEED_RESET_MCTP 1
--
2.7.4
^ permalink raw reply related
* [PATCH] PM / runtime: Fixup reference counting of device link suppliers at probe
From: Rafael J. Wysocki @ 2018-05-18 8:58 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526633329-31729-1-git-send-email-ulf.hansson@linaro.org>
On Fri, May 18, 2018 at 10:48 AM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
> In the driver core, before it invokes really_probe() it runtime resumes the
> suppliers for the device via calling pm_runtime_get_suppliers(), which also
> increases the runtime PM usage count for each of the available supplier.
>
> This makes sense, as to be able to allow the consumer device to be probed
> by its driver. However, if the driver decides to add a new supplier link
> during ->probe(), hence updating the list of suppliers,
Do any of the existing drivers do that?
> the following call to pm_runtime_put_suppliers(), invoked after really_probe()
> in the driver core, we get into trouble.
^ permalink raw reply
* [PATCH 4.9 27/33] futex: Remove duplicated code and fix undefined behaviour
From: Greg Kroah-Hartman @ 2018-05-18 9:01 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <e8dc5f94-3b52-dcf0-3b5e-b442bde7d803@suse.cz>
On Fri, May 18, 2018 at 10:30:24AM +0200, Jiri Slaby wrote:
> On 05/18/2018, 10:16 AM, Greg Kroah-Hartman wrote:
> > 4.9-stable review patch. If anyone has any objections, please let me know.
> >
> > ------------------
> >
> > From: Jiri Slaby <jslaby@suse.cz>
> >
> > commit 30d6e0a4190d37740e9447e4e4815f06992dd8c3 upstream.
> ...
> > --- a/kernel/futex.c
> > +++ b/kernel/futex.c
> > @@ -1458,6 +1458,45 @@ out:
> > return ret;
> > }
> >
> > +static int futex_atomic_op_inuser(unsigned int encoded_op, u32 __user *uaddr)
> > +{
> > + unsigned int op = (encoded_op & 0x70000000) >> 28;
> > + unsigned int cmp = (encoded_op & 0x0f000000) >> 24;
> > + int oparg = sign_extend32((encoded_op & 0x00fff000) >> 12, 12);
> > + int cmparg = sign_extend32(encoded_op & 0x00000fff, 12);
>
> 12 is wrong here ? wherever you apply this, you need also a follow-up fix:
> commit d70ef22892ed6c066e51e118b225923c9b74af34
> Author: Jiri Slaby <jslaby@suse.cz>
> Date: Thu Nov 30 15:35:44 2017 +0100
>
> futex: futex_wake_op, fix sign_extend32 sign bits
Thanks for letting me know, I've now queued it up to the needed trees.
greg k-h
^ permalink raw reply
* [PATCH] PM / runtime: Fixup reference counting of device link suppliers at probe
From: Ulf Hansson @ 2018-05-18 9:07 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <CAJZ5v0ikXsWdXq-h8rWLd-vfzi-gFmxyHmOGvRvDUoJHC3L2XA@mail.gmail.com>
On 18 May 2018 at 10:58, Rafael J. Wysocki <rafael@kernel.org> wrote:
> On Fri, May 18, 2018 at 10:48 AM, Ulf Hansson <ulf.hansson@linaro.org> wrote:
>> In the driver core, before it invokes really_probe() it runtime resumes the
>> suppliers for the device via calling pm_runtime_get_suppliers(), which also
>> increases the runtime PM usage count for each of the available supplier.
>>
>> This makes sense, as to be able to allow the consumer device to be probed
>> by its driver. However, if the driver decides to add a new supplier link
>> during ->probe(), hence updating the list of suppliers,
>
> Do any of the existing drivers do that?
Yes.
At least these, but possibly even more...
drivers/gpu/drm/rockchip/rockchip_drm_drv.c
drivers/gpu/drm/tegra/dc.c
drivers/gpu/ipu-v3/ipu-prg.c
drivers/pci/dwc/pci-dra7xx.c
>
>> the following call to pm_runtime_put_suppliers(), invoked after really_probe()
>> in the driver core, we get into trouble.
Kind regards
Uffe
^ permalink raw reply
* [PATCH v2 1/2] KVM: arm/arm64: add WARN_ON if size is not PAGE_SIZE aligned in unmap_stage2_range
From: Jia He @ 2018-05-18 9:27 UTC (permalink / raw)
To: linux-arm-kernel
There is a panic in armv8a server(QDF2400) under memory pressure tests
(start 20 guests and run memhog in the host).
---------------------------------begin--------------------------------
[35380.800950] BUG: Bad page state in process qemu-kvm pfn:dd0b6
[35380.805825] page:ffff7fe003742d80 count:-4871 mapcount:-2126053375
mapping: (null) index:0x0
[35380.815024] flags: 0x1fffc00000000000()
[35380.818845] raw: 1fffc00000000000 0000000000000000 0000000000000000
ffffecf981470000
[35380.826569] raw: dead000000000100 dead000000000200 ffff8017c001c000
0000000000000000
[35380.805825] page:ffff7fe003742d80 count:-4871 mapcount:-2126053375
mapping: (null) index:0x0
[35380.815024] flags: 0x1fffc00000000000()
[35380.818845] raw: 1fffc00000000000 0000000000000000 0000000000000000
ffffecf981470000
[35380.826569] raw: dead000000000100 dead000000000200 ffff8017c001c000
0000000000000000
[35380.834294] page dumped because: nonzero _refcount
[35380.839069] Modules linked in: vhost_net vhost tap ebtable_filter
ebtables ip6table_filter ip6_tables iptable_filter fcoe libfcoe libfc
8021q garp mrp stp llc scsi_transport_fc openvswitch nf_conntrack_ipv6
nf_nat_ipv6 nf_conntrack_ipv4 nf_defrag_ipv4 nf_nat_ipv4 nf_defrag_ipv6
nf_nat nf_conntrack vfat fat rpcrdma ib_isert iscsi_target_mod ib_iser
libiscsi scsi_transport_iscsi ib_srpt target_core_mod ib_srp
scsi_transport_srp ib_ipoib rdma_ucm ib_ucm ib_uverbs ib_umad rdma_cm
ib_cm iw_cm mlx5_ib ib_core crc32_ce ipmi_ssif tpm_tis tpm_tis_core sg
nfsd auth_rpcgss nfs_acl lockd grace sunrpc dm_multipath ip_tables xfs
libcrc32c mlx5_core mlxfw devlink ahci_platform libahci_platform libahci
qcom_emac sdhci_acpi sdhci hdma mmc_core hdma_mgmt i2c_qup dm_mirror
dm_region_hash dm_log dm_mod
[35380.908341] CPU: 29 PID: 18323 Comm: qemu-kvm Tainted: G W
4.14.15-5.hxt.aarch64 #1
[35380.917107] Hardware name: <snip for confidential issues>
[35380.930909] Call trace:
[35380.933345] [<ffff000008088f00>] dump_backtrace+0x0/0x22c
[35380.938723] [<ffff000008089150>] show_stack+0x24/0x2c
[35380.943759] [<ffff00000893c078>] dump_stack+0x8c/0xb0
[35380.948794] [<ffff00000820ab50>] bad_page+0xf4/0x154
[35380.953740] [<ffff000008211ce8>] free_pages_check_bad+0x90/0x9c
[35380.959642] [<ffff00000820c430>] free_pcppages_bulk+0x464/0x518
[35380.965545] [<ffff00000820db98>] free_hot_cold_page+0x22c/0x300
[35380.971448] [<ffff0000082176fc>] __put_page+0x54/0x60
[35380.976484] [<ffff0000080b1164>] unmap_stage2_range+0x170/0x2b4
[35380.982385] [<ffff0000080b12d8>] kvm_unmap_hva_handler+0x30/0x40
[35380.988375] [<ffff0000080b0104>] handle_hva_to_gpa+0xb0/0xec
[35380.994016] [<ffff0000080b2644>] kvm_unmap_hva_range+0x5c/0xd0
[35380.999833] [<ffff0000080a8054>]
kvm_mmu_notifier_invalidate_range_start+0x60/0xb0
[35381.007387] [<ffff000008271f44>]
__mmu_notifier_invalidate_range_start+0x64/0x8c
[35381.014765] [<ffff0000082547c8>] try_to_unmap_one+0x78c/0x7a4
[35381.020493] [<ffff000008276d04>] rmap_walk_ksm+0x124/0x1a0
[35381.025961] [<ffff0000082551b4>] rmap_walk+0x94/0x98
[35381.030909] [<ffff0000082555e4>] try_to_unmap+0x100/0x124
[35381.036293] [<ffff00000828243c>] unmap_and_move+0x480/0x6fc
[35381.041847] [<ffff000008282b6c>] migrate_pages+0x10c/0x288
[35381.047318] [<ffff00000823c164>] compact_zone+0x238/0x954
[35381.052697] [<ffff00000823c944>] compact_zone_order+0xc4/0xe8
[35381.058427] [<ffff00000823d25c>] try_to_compact_pages+0x160/0x294
[35381.064503] [<ffff00000820f074>]
__alloc_pages_direct_compact+0x68/0x194
[35381.071187] [<ffff000008210138>] __alloc_pages_nodemask+0xc20/0xf7c
[35381.077437] [<ffff0000082709e4>] alloc_pages_vma+0x1a4/0x1c0
[35381.083080] [<ffff000008285b68>]
do_huge_pmd_anonymous_page+0x128/0x324
[35381.089677] [<ffff000008248a24>] __handle_mm_fault+0x71c/0x7e8
[35381.095492] [<ffff000008248be8>] handle_mm_fault+0xf8/0x194
[35381.101049] [<ffff000008240dcc>] __get_user_pages+0x124/0x34c
[35381.106777] [<ffff000008241870>] populate_vma_page_range+0x90/0x9c
[35381.112941] [<ffff000008241940>] __mm_populate+0xc4/0x15c
[35381.118322] [<ffff00000824b294>] SyS_mlockall+0x100/0x164
[35381.123705] Exception stack(0xffff800dce5f3ec0 to 0xffff800dce5f4000)
[35381.130128] 3ec0: 0000000000000003 d6e6024cc9b87e00 0000aaaabe94f000
0000000000000000
[35381.137940] 3ee0: 0000000000000002 0000000000000000 0000000000000000
0000aaaacf6fc3c0
[35381.145753] 3f00: 00000000000000e6 0000aaaacf6fc490 0000ffffeeeab0f0
d6e6024cc9b87e00
[35381.153565] 3f20: 0000000000000000 0000aaaabe81b3c0 0000000000000020
00009e53eff806b5
[35381.161379] 3f40: 0000aaaabe94de48 0000ffffa7c269b0 0000000000000011
0000ffffeeeabf68
[35381.169190] 3f60: 0000aaaaceacfe60 0000aaaabe94f000 0000aaaabe9ba358
0000aaaabe7ffb80
[35381.177003] 3f80: 0000aaaabe9ba000 0000aaaabe959f64 0000000000000000
0000aaaabe94f000
[35381.184815] 3fa0: 0000000000000000 0000ffffeeeabdb0 0000aaaabe5f3bf8
0000ffffeeeabdb0
[35381.192628] 3fc0: 0000ffffa7c269b8 0000000060000000 0000000000000003
00000000000000e6
[35381.200440] 3fe0: 0000000000000000 0000000000000000 0000000000000000
0000000000000000
[35381.208254] [<ffff00000808339c>] __sys_trace_return+0x0/0x4
[35381.213809] Disabling lock debugging due to kernel taint
--------------------------------end--------------------------------------
The root cause might be what I fixed at [1]. But from arm kvm points of
view, it would be better we caught the exception earlier and clearer.
If the size is not PAGE_SIZE aligned, unmap_stage2_range might unmap the
wrong(more or less) page range. Hence it caused the "BUG: Bad page
state"
[1] https://lkml.org/lkml/2018/5/3/1042
Signed-off-by: jia.he at hxt-semitech.com
Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
v2: refine the commit log
virt/kvm/arm/mmu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 7f6a944..8dac311 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -297,6 +297,8 @@ static void unmap_stage2_range(struct kvm *kvm, phys_addr_t start, u64 size)
phys_addr_t next;
assert_spin_locked(&kvm->mmu_lock);
+ WARN_ON(size & ~PAGE_MASK);
+
pgd = kvm->arch.pgd + stage2_pgd_index(addr);
do {
/*
--
1.8.3.1
^ permalink raw reply related
* [PATCH v2 2/2] KVM: arm/arm64: harden unmap_stage2_ptes in case end is not PAGE_SIZE aligned
From: Jia He @ 2018-05-18 9:27 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <1526635630-18917-1-git-send-email-hejianet@gmail.com>
If it passes addr=0x202920000,size=0xfe00 to unmap_stage2_range->
...->unmap_stage2_ptes, unmap_stage2_ptes will get addr=0x202920000,
end=0x20292fe00. After first while loop addr=0x202930000, end=0x20292fe00,
then addr!=end. Thus it will touch another pages by put_pages() in the
2nd loop.
This patch fixes it by hardening the break condition of while loop.
Signed-off-by: jia.he at hxt-semitech.com
---
v2: newly added
virt/kvm/arm/mmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/virt/kvm/arm/mmu.c b/virt/kvm/arm/mmu.c
index 8dac311..45cd040 100644
--- a/virt/kvm/arm/mmu.c
+++ b/virt/kvm/arm/mmu.c
@@ -217,7 +217,7 @@ static void unmap_stage2_ptes(struct kvm *kvm, pmd_t *pmd,
put_page(virt_to_page(pte));
}
- } while (pte++, addr += PAGE_SIZE, addr != end);
+ } while (pte++, addr += PAGE_SIZE, addr < end);
if (stage2_pte_table_empty(start_pte))
clear_stage2_pmd_entry(kvm, pmd, start_addr);
--
1.8.3.1
^ permalink raw reply related
* [PATCH] arm: bcm2835: Add the PMU to the devicetree.
From: Stefan Wahren @ 2018-05-18 9:37 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <d6b6f632-2051-a239-3e44-4750f2ac89d5@arm.com>
Hi Marc,
> Marc Zyngier <marc.zyngier@arm.com> hat am 18. Mai 2018 um 10:07 geschrieben:
>
> I have a pretty simple series[1] which I used to profile 32bit guests on
> an arm64 KVM host. Nobody really cared about it because running a 32bit
> kernel on 64bit HW is a bit odd, to say the least, and I'm probably the
> only one actually running 32bit VMs.
>
> > FWIW, Broadcom STB chips, even when 64-bit capable or often used with an
> > 32-bit ARM kernel, so having the ARMv8 PMUs work under a 32-bit ARM
> > kernel would be great. The downstream solution we have sued thus far is
> > to find the closest compatible string to represent those, which is not
> > great...
> Ah, so you're *really* doing that? I'm not going to ask why, I'm scared
> of the answer... ;-)
>
> Anyway, I can repost that series if that will prevent people from having
> that kind of silly hacks.
yes please. But there is a minor nit: some patches introduce new files without SPDX tags.
Thanks
Stefan
>
> Thanks,
>
> M.
>
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git/log/?h=kvm-arm/pmuv3-32bit
> --
> Jazz is not dead. It just smells funny...
^ permalink raw reply
* [PATCH v2 00/26] arm64: allwinner: Add A64 DE2 HDMI support
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
Allwinner A64 has display engine pipeline like other Allwinner SOC's A83T/H3/H5.
A64 behaviour similar to Allwinner A83T where
Mixer0 => TCON0 => LVDS/RGB/MIPI-DSI
Mixer1 => TCON1 => HDMI
as per Display System Block DiagramAllwinner_A64_User_Manual_V1.1.pdf
This is second patch-set followed with previous RFC[1] and first series[2]
and merely concentrated on HDMI pipeline through TCON1 and rest will add eventually.
This series fixed previous version comments
- about documenting fallback compatibles
- adding new compatible for mixer1
- support for multiple DW HDMI PHY clock parents (thanks, to Jernej)
Note:
Pine64 boards are unable to get edid by default like other A64 boards,
but forcing 'video=HDMI-A-1:1920x1080 at 60D' kernel command line can
create edid with display on penel.
Log:
[ 1.613196] sun4i-drm display-engine: bound 1200000.mixer (ops sun8i_mixer_ops)
[ 1.620764] sun4i-drm display-engine: No panel or bridge found... RGB output disabled
[ 1.628612] sun4i-drm display-engine: bound 1c0d000.lcd-controller (ops sun4i_tcon_ops)
[ 1.637677] sun8i-dw-hdmi 1ee0000.hdmi: Detected HDMI TX controller v1.32a with HDCP (sun8i_dw_hdmi_ph
y)
[ 1.647699] sun8i-dw-hdmi 1ee0000.hdmi: registered DesignWare HDMI I2C bus driver
[ 1.656090] [drm] forcing HDMI-A-1 connector on
[ 1.660664] sun4i-drm display-engine: bound 1ee0000.hdmi (ops sun8i_dw_hdmi_ops)
[ 1.668063] [drm] Supports vblank timestamp caching Rev 2 (21.10.2013).
[ 1.674684] [drm] No driver support for vblank timestamp query.
[ 2.497502] Console: switching to colour frame buffer device 240x67
[ 2.551795] sun4i-drm display-engine: fb0: frame buffer device
[ 2.558166] [drm] Initialized sun4i-drm 1.0.0 20150629 for display-engine on minor 0
[2] https://lkml.org/lkml/2018/4/30/288
[1] https://lkml.org/lkml/2018/4/24/547
Icenowy Zheng (1):
drm: sun4i: add support for HVCC regulator for DWC HDMI glue
Jagan Teki (22):
dt-bindings: clock: Add compatible for A64 DE2 CCU
arm64: dts: allwinner: a64: Add DE2 CCU
clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
clk: sunxi-ng: a64: Add minimal rate for video PLLs
drm/sun4i: Add support for A64 mixer1
dt-bindings: display: Add compatible for A64 DE2 tcon1 blocks
drm/sun4i: Add support for A64 display engine
arm64: dts: allwinner: a64: Add DE2 tcon1 pipeline
drm/sun4i: Enable DE2 Mixer for SUN8I and SUN50I
arm64: defconfig: Enable CONFIG_DRM_SUN4I
dt-bindings: display: Add compatible for A64 HDMI
dt-bindings: display: Add compatible for A64 HDMI PHY
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO[0-1] macros
arm64: dts: allwinner: a64: Add HDMI support
drm/sun4i: Enable DesignWare HDMI for SUN8I and SUN50I
arm64: dts: allwinner: a64: Add HDMI pipeline
arm64: dts: allwinner: a64: bananapi-m64: Enable HDMI output
arm64: dts: allwinner: a64: nanopi-a64: Enable HDMI output
arm64: dts: allwinner: a64: orangepi-win: Enable HDMI output
arm64: dts: allwinner: a64: a64-olinuxino: Enable HDMI output
arm64: dts: allwinner: a64: pine64: Enable HDMI output
arm64: dts: allwinner: a64: sopine: Enable HDMI output
Jernej Skrabec (3):
drm/sun4i: DE2 mixer: Add index quirk
drm/sun4i: Add support for multiple DW HDMI PHY clock parents
drm/sun4i: Add support for A64 HDMI PHY
.../devicetree/bindings/clock/sun8i-de2.txt | 1 +
.../bindings/display/sunxi/sun4i-drm.txt | 5 +
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 26 +++++
.../boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 26 +++++
.../boot/dts/allwinner/sun50i-a64-olinuxino.dts | 26 +++++
.../boot/dts/allwinner/sun50i-a64-orangepi-win.dts | 26 +++++
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 26 +++++
.../dts/allwinner/sun50i-a64-sopine-baseboard.dts | 26 +++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 124 +++++++++++++++++++++
arch/arm64/configs/defconfig | 1 +
drivers/clk/sunxi-ng/Kconfig | 2 +
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 ++++----
drivers/gpu/drm/sun4i/Kconfig | 3 +-
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.c | 14 +++
drivers/gpu/drm/sun4i/sun8i_dw_hdmi.h | 11 +-
drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 44 ++++++--
drivers/gpu/drm/sun4i/sun8i_hdmi_phy_clk.c | 89 +++++++++++----
drivers/gpu/drm/sun4i/sun8i_mixer.c | 17 ++-
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 +
include/dt-bindings/clock/sun50i-a64-ccu.h | 2 +
21 files changed, 458 insertions(+), 60 deletions(-)
--
2.14.3
^ permalink raw reply
* [PATCH v2 01/26] dt-bindings: clock: Add compatible for A64 DE2 CCU
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
Allwinner A64 has DE2 CCU is similar to H3/H5 SoC.
So add compatible for A64 which is fallback compatible
for H5, so update fallback binding.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
Changes for v2:
- Add fallback compatible
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
index f2fa87c4765c..e3ffe0bcd0a0 100644
--- a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
+++ b/Documentation/devicetree/bindings/clock/sun8i-de2.txt
@@ -7,6 +7,7 @@ Required properties :
- "allwinner,sun8i-h3-de2-clk"
- "allwinner,sun8i-v3s-de2-clk"
- "allwinner,sun50i-h5-de2-clk"
+ - "allwinner,sun50i-a64-de2-clk", "allwinner,sun50i-h5-de2-clk"
- reg: Must contain the registers base address and length
- clocks: phandle to the clocks feeding the display engine subsystem.
--
2.14.3
^ permalink raw reply related
* [PATCH v2 02/26] arm64: dts: allwinner: a64: Add DE2 CCU
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
DE2 CCU in Allwinner A64 has same like H5, so use the
similar dts details for A64 with fallback compatible.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Add h5 compatible first since A64 came first.
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
index 1b2ef28c42bd..26c2a9c44727 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
@@ -43,9 +43,11 @@
*/
#include <dt-bindings/clock/sun50i-a64-ccu.h>
+#include <dt-bindings/clock/sun8i-de2.h>
#include <dt-bindings/clock/sun8i-r-ccu.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/sun50i-a64-ccu.h>
+#include <dt-bindings/reset/sun8i-de2.h>
/ {
interrupt-parent = <&gic>;
@@ -168,6 +170,19 @@
#size-cells = <1>;
ranges;
+ display_clocks: clock at 1000000 {
+ compatible = "allwinner,sun50i-h5-de2-clk",
+ "allwinner,sun50i-a64-de2-clk";
+ reg = <0x01000000 0x100000>;
+ clocks = <&ccu CLK_DE>,
+ <&ccu CLK_BUS_DE>;
+ clock-names = "mod",
+ "bus";
+ resets = <&ccu RST_BUS_DE>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
syscon: syscon at 1c00000 {
compatible = "allwinner,sun50i-a64-system-controller",
"syscon";
--
2.14.3
^ permalink raw reply related
* [PATCH v2 03/26] clk: sunxi-ng: Enable DE2_CCU for SUN8I and SUN50I
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
Allwinner SoC like SUN8I and SUN50I has DE2 CCU so enable them
as default.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Enable for MACH_SUN8I
drivers/clk/sunxi-ng/Kconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/clk/sunxi-ng/Kconfig b/drivers/clk/sunxi-ng/Kconfig
index 826674d090fd..e20182aa9748 100644
--- a/drivers/clk/sunxi-ng/Kconfig
+++ b/drivers/clk/sunxi-ng/Kconfig
@@ -63,6 +63,8 @@ config SUN8I_V3S_CCU
config SUN8I_DE2_CCU
bool "Support for the Allwinner SoCs DE2 CCU"
+ default MACH_SUN8I || (ARM64 && ARCH_SUNXI)
+ depends on DRM_SUN4I && (MACH_SUN8I || (ARM64 && ARCH_SUNXI))
config SUN8I_R40_CCU
bool "Support for the Allwinner R40 CCU"
--
2.14.3
^ permalink raw reply related
* [PATCH v2 04/26] clk: sunxi-ng: a64: Add minimal rate for video PLLs
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- New patch
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 ++++++++++++++++++-----------------
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
index ee9c12cf3f08..d0e30192f0cf 100644
--- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
+++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
@@ -64,17 +64,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0",
- "osc24M", 0x010,
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0",
+ "osc24M", 0x010,
+ 192000000, /* Minimum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x018,
@@ -125,17 +126,18 @@ static struct ccu_nk pll_periph1_clk = {
},
};
-static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1",
- "osc24M", 0x030,
- 8, 7, /* N */
- 0, 4, /* M */
- BIT(24), /* frac enable */
- BIT(25), /* frac select */
- 270000000, /* frac rate 0 */
- 297000000, /* frac rate 1 */
- BIT(31), /* gate */
- BIT(28), /* lock */
- CLK_SET_RATE_UNGATE);
+static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1",
+ "osc24M", 0x030,
+ 192000000, /* Minimum rate */
+ 8, 7, /* N */
+ 0, 4, /* M */
+ BIT(24), /* frac enable */
+ BIT(25), /* frac select */
+ 270000000, /* frac rate 0 */
+ 297000000, /* frac rate 1 */
+ BIT(31), /* gate */
+ BIT(28), /* lock */
+ CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu",
"osc24M", 0x038,
--
2.14.3
^ permalink raw reply related
* [PATCH v2 05/26] drm/sun4i: DE2 mixer: Add index quirk
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
From: Jernej Skrabec <jernej.skrabec@siol.net>
When TCON set up TCON TOP, it needs to know mixer index. Here we do that
by setting engine ID to number provided in mixer index quirk.
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- New patch
drivers/gpu/drm/sun4i/sun8i_mixer.c | 4 ++--
drivers/gpu/drm/sun4i/sun8i_mixer.h | 2 ++
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 126899d6f0d3..36d90c76317a 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -353,13 +353,13 @@ static int sun8i_mixer_bind(struct device *dev, struct device *master,
dev_set_drvdata(dev, mixer);
mixer->engine.ops = &sun8i_engine_ops;
mixer->engine.node = dev->of_node;
- /* The ID of the mixer currently doesn't matter */
- mixer->engine.id = -1;
mixer->cfg = of_device_get_match_data(dev);
if (!mixer->cfg)
return -EINVAL;
+ mixer->engine.id = mixer->cfg->index;
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
regs = devm_ioremap_resource(dev, res);
if (IS_ERR(regs))
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.h b/drivers/gpu/drm/sun4i/sun8i_mixer.h
index f34e70c42adf..aeda6e9a7627 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.h
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.h
@@ -123,6 +123,7 @@ struct de2_fmt_info {
* are invalid.
* @mod_rate: module clock rate that needs to be set in order to have
* a functional block.
+ * @index: mixer index, needed to properly set TCON TOP
*/
struct sun8i_mixer_cfg {
int vi_num;
@@ -130,6 +131,7 @@ struct sun8i_mixer_cfg {
int scaler_mask;
int ccsc;
unsigned long mod_rate;
+ int index;
};
struct sun8i_mixer {
--
2.14.3
^ permalink raw reply related
* [PATCH v2 06/26] drm/sun4i: Add support for A64 mixer1
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Mixer1 has 1 VI and 1 UI planes and supports HW scaling on all
planes.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- New patch
drivers/gpu/drm/sun4i/sun8i_mixer.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/sun4i/sun8i_mixer.c b/drivers/gpu/drm/sun4i/sun8i_mixer.c
index 36d90c76317a..5b02c6ee2be6 100644
--- a/drivers/gpu/drm/sun4i/sun8i_mixer.c
+++ b/drivers/gpu/drm/sun4i/sun8i_mixer.c
@@ -508,6 +508,15 @@ static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = {
.mod_rate = 150000000,
};
+static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = {
+ .ccsc = 1,
+ .index = 1,
+ .mod_rate = 297000000,
+ .scaler_mask = 0x3,
+ .ui_num = 1,
+ .vi_num = 1,
+};
+
static const struct of_device_id sun8i_mixer_of_table[] = {
{
.compatible = "allwinner,sun8i-a83t-de2-mixer-0",
@@ -525,6 +534,10 @@ static const struct of_device_id sun8i_mixer_of_table[] = {
.compatible = "allwinner,sun8i-v3s-de2-mixer",
.data = &sun8i_v3s_mixer_cfg,
},
+ {
+ .compatible = "allwinner,sun50i-a64-de2-mixer-1",
+ .data = &sun50i_a64_mixer1_cfg,
+ },
{ }
};
MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table);
--
2.14.3
^ permalink raw reply related
* [PATCH v2 07/26] dt-bindings: display: Add compatible for A64 DE2 tcon1 blocks
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
Allwinner A64 has DE2 pipeline with tcon0 and tcon1 block
which is similar Allwinner A83T.
This patch adds dt-binding documentation for A64 DE2 tcon1 blocks.
Mixer1 has different configuration for A64 so use separate compatible
but tcon1 has similar behaviour with A83T so add fallback compatible.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- Add fallback compatible for tcon1
- Add separate compatible for mixer1
Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
index 3346c1e2a7a0..863afad6a4df 100644
--- a/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
+++ b/Documentation/devicetree/bindings/display/sunxi/sun4i-drm.txt
@@ -148,6 +148,7 @@ Required properties:
* allwinner,sun8i-v3s-tcon
* allwinner,sun9i-a80-tcon-lcd
* allwinner,sun9i-a80-tcon-tv
+ * "allwinner,sun50i-a64-tcon-tv", "allwinner,sun8i-a83t-tcon-tv"
- reg: base address and size of memory-mapped region
- interrupts: interrupt associated to this IP
- clocks: phandles to the clocks feeding the TCON.
@@ -311,6 +312,7 @@ Required properties:
* allwinner,sun8i-a83t-de2-mixer-1
* allwinner,sun8i-h3-de2-mixer-0
* allwinner,sun8i-v3s-de2-mixer
+ * allwinner,sun50i-a64-de2-mixer-1"
- reg: base address and size of the memory-mapped region.
- clocks: phandles to the clocks feeding the mixer
* bus: the mixer interface clock
@@ -343,6 +345,7 @@ Required properties:
* allwinner,sun8i-h3-display-engine
* allwinner,sun8i-v3s-display-engine
* allwinner,sun9i-a80-display-engine
+ * allwinner,sun50i-a64-display-engine
- allwinner,pipelines: list of phandle to the display engine
frontends (DE 1.0) or mixers (DE 2.0) available.
--
2.14.3
^ permalink raw reply related
* [PATCH v2 08/26] drm/sun4i: Add support for A64 display engine
From: Jagan Teki @ 2018-05-18 9:45 UTC (permalink / raw)
To: linux-arm-kernel
In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com>
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes for v2:
- none
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c b/drivers/gpu/drm/sun4i/sun4i_drv.c
index 50d19605c38f..c84102a750f8 100644
--- a/drivers/gpu/drm/sun4i/sun4i_drv.c
+++ b/drivers/gpu/drm/sun4i/sun4i_drv.c
@@ -368,6 +368,7 @@ static const struct of_device_id sun4i_drv_of_table[] = {
{ .compatible = "allwinner,sun8i-h3-display-engine" },
{ .compatible = "allwinner,sun8i-v3s-display-engine" },
{ .compatible = "allwinner,sun9i-a80-display-engine" },
+ { .compatible = "allwinner,sun50i-a64-display-engine" },
{ }
};
MODULE_DEVICE_TABLE(of, sun4i_drv_of_table);
--
2.14.3
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